I created the footprint using four layers (the inner two for the loop and top and bottom for the shield) using tracks, vias, 'virtual shorts' and pads (three for the loop+CT, one for the shield).
For the information of others who may not know what a "virtual short" (VS) is, it is a set of pads which have between them a very small gap, small enough that, for many reasons, it should not be fabricatable unless (1) the round-off process in generating photoplots leaves as much as a 1 mil gap and (2) an enthusiastic fabricator increases this to correct what is thought to be an obvious error, and fails to flag it for engineering approval. There are ways to avoid these problems, but one should know about the possibility.
Because the pads are not in actual contact as far as Protel Advanced PCB is concerned, they can carry separate nets; and a special clearance rule allows the tiny clearance (several microinches, usually) just for those pads.
The connection pads take on the correct nets, but generate DRC clearance errors on the tracks that are part of the footprint. Thanks to the virtual shorts and associated rules the loop itself is error-free, it's just the connection pads that generate the errors......
I'm not sure I understand why this is happening. The shield would not require VS pads, if I'm correct. Then there is essentially a center-tapped inductor, so this would require three connection points. Each connection point would be a VS pair of pads. The outer pads would be connected to the outside world as normal component pads. The inner pads would be connected to each other by the antenna track. However, I would not assign any net at all to the antenna track itself, so the problem mentioned would not arise. But perhaps there is a reason for assigning a net to that track.... And then this track would behave as described.
The 'update free primitives from component pads' command does not help since the violating primitives are not free (they are part of the footprint).
I don't think this is true. "Update free primitives" does, in fact, update all connected primitives except for component pads. But it might not look like it works, because the error markers are not cleared. If you run DRC, however, the error markers go away.
Releasing the footprint does not help much either, I then have an unplaced component....
Plus if you have an otherwise efficient method of defining the virtual short clearance rule, you'll lose the application of the definition. The simplest and broadest rule is to assign the micro-clearance to the footprint of the virtual short. You could give the pads distinctive names and then define the clearance based on named pads, and this would work with free pads, but that is not as simple. By not having the footprint, you'd also lose the mutual position lock that is characteristic of footprints and which is, of course, crucial to the operation of a virtual short.
Is there any way out of this?
Mr Potjewijd in a subsequent post noted that "Update Free Primitives" does work, but then he added that this was required with every Update from Schematic. Again, I don't think that is true. If the net name assigned to the pads changes, yes. But if not, no. As I recall, the net assignment of tracks -- free other otherwise -- does not change when a netlist is loaded or the PCB is updated from Schematic, unless the net assigned to the track does not exist in the new net list, in which case it is cleared from the track.
If, after running Update from Schematic, there then exists a pad and track in contact which do not have the same net name, an error marker is created. Then, if no real shorts exist, running Update Free Primitives will assign the pad net to the track. "Update Free Primitives" is shorthand for
"Update Non-Pad Copper Primitives and Free Pads from Component Pads in Contact with Such Primitives." Now, why didn't they just say that? :-)
There is one other common source for error markers in a virtual short situation. If the pad sizes and track sizes are such that the outside connecting track violates clearance to the internal virtual short pad, you might get a clearance violation.
Consider the original virtual short application: distinct ground nets shorting at the virtual short. One pad is connected to, say, GND, and the other to GNDA. If the pads were 50 mil square and the tracks 50 mils, the GND and GNDA tracks would still short. You could fix this in two ways. One would be to back off the track from pad center to pad edge. This would create 50 mils of clearance between the tracks, without changing what ends up on the films. But if tracks terminating other than on pad center offends you, or offends your autorouter, which might be more to the point, then you could make the pads longer. Making each VS pad be 100 mils by 50 mils would, again, leave the films unchanged, except perhaps for solder mask, provided that the tracks were originally running straight together....
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