Ray Mitchell wrote:


In the past I've developed my Xilinx FPGAs by creating a schematic in Protel 99SE, generating a netlist in Xilinx XNF 5.0 format, then compiling the XNFs using the Xilinx 3.1i application. To be compatible with the newer Xilinx devices, such as the Coolrunner II series, I have acquired their 6.1i application. However, 6.1i no longer supports XNF files. So my question is how to create something using 99SE that Xilinx 6.1i can handle. I've tried creating the Protel netlist in both VHDL and EDIF 2.0 format but either I'm doing something wrong or they are not compatible with Xilinx 6.1i. Does Protel DSP support this better? All suggestions are welcome.

I have done this, but it gets a bit messy. I'm not sure my method is actually any improvement.
The only thing I found that worked was VHDL (architectural) netlists. An annoying bug
is that P99SE Sp6 will only output one VHDL netlist, then you have to restart P99.
If you don't restart P99 each time, it will hang on the netlist step. If you wait half
an hour, it outputs 65536 lines of garbage before the valid netlist.

But, you get a netlist almost ready for Xilinx isp. You have to manually add the library
unisim and the line "use unisim.vcomponents" to get the use of those library components.
You can edit away the _sch extension from all VHDL files made from schematic sheets.
You have to manually remove duplicate component declarations for all of the user-created
components. This only comes up on sheets where you have placed the same user-created library
component multiple times.

The rough edges are that P99 wants input and output pads on the top level page for sim
and ERC, but Xilinx DOESN'T want pads, it assumes any ports on the top page are


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