I do that all the time. The hole for the TO-220 tab is the hole that will be
in the board. You don't need to place another 'free' hole. My "lay-flat"
TO-220 pad is defined as pad number 0 and is 0.125" so I can use a machine
screw and nut to hold it down. 
The area below it is part of my GND polygon pour. I manually connect this
PAD0 to the GND net. To expose the copper, I place a fill on the Top Solder
mask layer and it's usually the size of the tab and the body (helps if the
back of the body is metal and not plastic)

This will DRC properly because of the manual net assignment, however the
thing to watch is when you do an UpdatePCB from the schematic. It will try
and generate a macro to remove U?_PAD0 from net GND. Just delete that macro
and continue.



> -----Original Message-----
> From: Dom Bragge [mailto:[EMAIL PROTECTED] 
> Sent: Wednesday, January 28, 2004 9:23 PM
> To: protel
> Subject: [PEDA] TO-220 4th pin?
> 
> I just would like to ask a question about how you handle 
> TO-220 footprints (& the like)...
> 
> I have the three (electrical) pin device, that's fine.
> I'm placing the T)-220's flat on the board.
> 
> What if I want to (selectively) put copper on the top layer 
> under the TO-220 & have a suitable soldermask antipad? This 
> could aid in cooling without resorting to an actual heatsink.
> How should I best do that?
> 
> Do I place on the board a free pad, rectangle, with a hole 
> the same size as the hole for the TO-220 tab? Seems a bit 
> ugly, two holes etc etc but it should probably give me the 
> SMask opening.
> 
> Do I make a 4pin lib part, have a 4th pin on the footprint 
> being the large hole & add a polygon connected to that net? I 
> suppose I'll have to add an opening for the SMask on the 
> TO-220 footprint as well.
> 
> 
> What say you?
> 
> --
> Regards,
> 
> Dom   99SESP6
> 
> Dom Bragge, CID MIEEE  | Silverbrook Research PL, PO Box 207
> Snr PCB Layout Engr    | Balmain NSW 2041, AUSTRALIA
> Ph +61-2-9818-6633xt163| [EMAIL PROTECTED]
> 
> 
> 
> 



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