It's great to have the point of view of a FPGA designer/developer. We don't
all do FPGA design and find the direction that Protel is taking very
unsettling when there are so many other things they could be doing to
improve the product. Thanks for your insight Harry. It lends a voice of
reason to the mix.

Bill Brooks 
PCB Design Engineer , C.I.D., C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510

-----Original Message-----
From: Harry Lemmens [mailto:[EMAIL PROTECTED] 
Sent: Monday, April 12, 2004 6:36 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Would it not be nice?

I have been following this discussion on DXP/2004 with some interest. I do
many more FPGA designs than PCB designs and find it somewhat amusing that
Altium are again trying to hit upon the FPGA market. Protel has previously
tried to enter the FPGA (specifically Xilinx) with a schematic capture entry
system. Although, I did play with it for some small time, I soon returned to
the tried and proven tools that I used at the time. (What was worse, the
Protel designs at the time had to be processed through part of the Orcad
tool chain, and unless you had a particular Orcad tool for this function,
you could not proceed to completion anyway!)

On the surface, it seems to be a logical extension of the engineering
required in this day and age. However, the FPGA market in its own right
seems to alter dramatically every few years. It was not that long ago that
schematic capture was sufficient for most FPGA designs. Now VHDL/Verilog
seem to be the default FPGA design entry tools, along with such tools as
Mathcad, etc, to input (mathematical models) from a higher level viewpoint.
(Mathcad like design entry generally spits out VHDL/Verilog based on the
entered mathematical model, and can rapidly consume vast amounts of FPGA
gates. Would anyone on this forum suggest that Altium have the necessary
drive to compete in all these markets?) (Especially based on their previous
track record?)

 As someone has stated, Xilinx do indeed give away a VERY GOOD design suite
that gets you easily to several hundred k gates, and covers the entire
design very nicely. (even schematic capture, if you wish) This tool even
lets you easily alter specific synthesis topologies for individual modules
at the click of a few buttons. (See the Xilinx Webpack)

If you really wish vendor independence with FPGA's, you spend your dollars
and go with one of the industry leaders, you do not use an unknown tool to
get potentially wishy washy results. (Would you use Altium FPGA tools for a
big design? I wouldn't!)

For instance, Exemplar, which have been in the FPGA market for some time,
producing such tools as Leonardo, Modelsim ... Their "foundry" tools have
always been able to target multiple FPGA vendors, and Modelsim (as such) is
the design verification tool. Expect to spend big bucks for the ability to
target multiple vendors FPGA's, but the results can be well worth it!) Other
companies also provide similar excellent FPGA retargeting ability within
their tools as well. (Again, at a price ...))

I should point out that the tools from these vendors are aware of the
internal architecture of the particular FPGA being targeted, and produce
(semi optimal) results that differ based on the chosen device. I doubt that
the Altium tools are going to be that specific! FPGA's look like a black box
to most designers, but they do differ dramatically from one Vendor to the
next. Even device families from one vendor can be significantly different in
their internal features.)

Unfortunately, design verification for FPGA's can easily take much longer
than actually doing the design, the simulation "program" written in VHDL or
Verilog can easily take 5..10 times the time to write. Final design
verification also relies on back annotation of the actual targeted design to
the simulation tools, and this always relies on the targeting tools from
specific vendors. (Be they Xilinx, Altera, Actel, Atmel, Quicklogic, etc)
Unless you also have the Foundry tools from each vendor you wish to attempt
retargeting on, you really do NOT know if you are going to be successful.
Since the pin outs for any FPGA is not standardized, FPGA retargeting must
be achieved BEFORE PCB layout anyway. It would normally be done based on
quoted price for the amount of k gates each vendor claims is equivalent to
(some competitors) device. (Alas, comparisons between vendors of different
FPGA devices is nowhere near that straight forward.)

Complete PCB board simulation is also going to be problematical. While the
concept of total simulation from schematics and FPGA logic through to the
final PCB design sounds good, in actual implementation, it will be difficult
beyond belief. It takes long enough just to set up a simple spice
simulation. Now multiply this by many thousands, and consider how many PCB's
you might be able to fully verify before fabrication proceeds. As it stands,
the designer is generally aware of specific constraints for certain nets,
and will attempt to ensure that these net constraints are met. (Or at least,
he should indicate potential problems to the person doing the PCB design.)
This does not even factor in many of the other potential issues with board
design, like how topologies affect line impeadance, what the actual pin
delay times (and capacitance, frequency response, etc).  (Yes, I know that
some vendors do have the relevant models for their device pins. Be aware
that these are already somewhat simplified. Using these models though
several serial connections is undoubtedly going to introduce significant
errors anyway.)

Having said all this, I have not even looked at DXP, or 2004. I still use
99SE. (I have used virtually every Protel package over the years. Except
their very first versions, which I saw, but never used as it was not as good
as the package I used then.) In fact, from what I have seen on this forum
about the change in methodologies from 99Se to later packages, I will stick
to 99SE until I no longer have the option. (As someone stated, It will
eventuate that 99SE will eventually break with some later operating system!)

I still think the swap to an integrated database in 98/99/99se was a mistake
that slows design loading beyond belief! (The last service pack for 99SE
makes this even worse, playing a database compaction game every time you
exit a project. (even if nothing has changed!)

I must wonder though, where the Nanoboard fits in? what real use will this
be to 99% of the users already out their? Certainly, I suspect very few will
leverage any of the provided design. (Especially anyone who is already savvy
in modern FPGA design!)  Beyond the initial plug in and play with evaluation
boards of this nature, very rarely are evaluation boards ever looked at
again. (A few years later, they invariably end up in the trash!)

As others have pointed out. Please work on the bread and butter parts of the
package. (Schematic Capture, PCB layout, and to a lesser extent, simulation)
Device footprint libraries could also be MUCH improved. (Ever tried to find
an appropriate footprint within the Libraries from Protel? It's easier,
faster, and more accurate to re-design your own!)

There are so many area's within Protel packages that need cleanup
(completion?) that I wonder why Altium have embarked down the track of being
another "me too" FPGA tool at the risk of disenfranchising their current

It used to be obvious that the Protel team writing the Schematic capture did
not communicate with the design team writing the PCB side. I imagine that
this will only get worse in the future, as more engineering modules get
ladled into the package. (What next? RF design tools? Full 3D design entry

There is so much more that can be said about this subject that I shudder! In
fact, virtually a whole book could easily be written about individual topic
area's within the Altium package.

Having said all the above, Protel isn't all that bad. Its just that it could
have been so much better, especially if some of the niggling deficiencies
that have existed between one version to the next (and to the next ...) had
been addressed, rather than going off in questionable directions, and
releasing half baked tools that (occasionally?) destroy productivity. (Or
having features in one tool that appear should propagate through to another
tool, but in fact do not!)

Cheers Harry

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