Harry Lemmens wrote:

As someone has stated, Xilinx do indeed give away a VERY GOOD design suite that
gets you easily to several hundred k gates, and covers the entire design very

As does Altera. I don't know the others, but it is probably safe to assume that the smaller players in the FPGA market provide tools for their devices as well. Both Xilinx and Altera provide processor soft cores also, so the whole point of Nexar kind of escapes me(*). I would much prefer seeing Protel get the core stuff done brilliantly, such as gate/pin swapping, autorouting and my pet peeve, component placement(**). For FPGA stuff, it would be very sufficient to have seamless integration to the vendor tools.

I share the doubts that Altium can't be able to keep up with the industry with one integrated tool. Nexar looks cool, but it has very limited set of design blocks, only a few 8 bit processors and no Verilog support. As Harry pointed out, the FPGA field moves fast. A few years back it was schematics, yesterday it was VHDL/Verilog, to day it is design re-use. As an example, we are doing a system that has a 32-bit processor, multimaster bus, DDR memory interface, video converter and serial, parallel, network and USB interfaces integrated on an FPGA. Guess how many of these functions was designed in-house. Right, none. It will be very hard for a relatively small company to keep up. On the other hand, Altium has a key position to tie the toolchain together. I just don't think the key is doing it all in-house.

*: Of course, Nexar looks very cool from investors point of view, so I kind of do see the point...

**: I still find it pathetic that no software I know of properly understands the most common electronic component, the bypass capacitor. If Altium want to really increase their market share, they would design something like the this (which, by the way, is far easier than any functionality that Nexar brings in): Let me define a few bypass schemes, like regular bypass cap, which connects from the supply line to the cap to the power pin. In this order, to the specified pin, within specified distance - although equivalent at the netlist level, no other scheme works: a nearby control pin tied high does no good, nor does a bypass cap away from the chip. Also, a more sensitive pin might need something like a ferrite bead, 10u, 100n, supply pin; again in this order. Why can't I just assign bypass schemes to supply pins and have the computer to make the connections, collect the caps to a separate sheet (in order not to clutter the main sheet) but still show which caps belong to which pin), have the computer place the caps correctly by the chips and group them together (so that if I move the chip, the caps move as well) and finally, have the router to fanout/route these correctly (as noted above). For a digital designer, this would be the single biggest productivity boost I can imagine after a really great autorouter. If Altium would provide these, most people would switch, company policies allowing!

Juha Kuusama
Kuusama Design

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