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Thanks you Duane ....for the inputs.   
How did it work for you?   

Mike Reagan



-----Original Message-----
From: Duane Foster [mailto:[EMAIL PROTECTED]
Sent: Monday, September 20, 2004 12:27 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Electra router


Good morning,

You should catch a missing parentheses on page 7 if you're going to revise
your article.  I couldn't get the special clearance rules to work until i
added a closing parentheses to your DO file command below:

rule pcb (clearance 17(type via_via)


many thanks for writing this article

duane

> -----Original Message-----
> From: Mike Reagan [mailto:[EMAIL PROTECTED]
> Sent: Monday, September 20, 2004 8:01 AM
> To: 'Protel EDA Forum'


 I might work on second revision 
> because I want to
> elaborate on moving in and out, routing selected nets and 
> components only.



> -----Original Message-----
> From: Tony Karavidas [mailto:[EMAIL PROTECTED]
> Sent: Saturday, September 18, 2004 3:05 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] Electra router
> 
> 
> Hi Mike,
> 
> It's nice to see this published.
> 
> Figures 2 and 3 need to be swapped or the text needs to be swapped.
> 
> One page 7, there is a sentence which doesn't make sense to me:
> "A good rule is to use is maximum via" I tried to make sense of it by
> continuing to read, but it didn't help. Can you explain what you mean?
> 
> There is a typo on page 8. (first paragraph, second to last sentence.)
> 
> How come you say not to use DXP's DO file? Does it generate 
> bad info? Isn't
> it a good place to start and then manually tweek it? Doesn't 
> DXP communicate
> the PCB rules into Electra through the DO file, or do the 
> rules migrate
> through the DSN file? (I thought that was the board layout only)
> 
> 
> Thanks!
> Tony




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