Early on in this discussion engineers from multiple router vendors stated publicly that that their engineers knew how to build routers that would handle FIBs that were at least 4M entries or more (10M was mentioned), using commodity hardware parts. It also became clear, at least to a few of us talking on the side, that what the hardware guys were telling one router vendor, in terms of what memory parts they will have in a few years, is the same thing that they are telling other router vendors. In various private conversations it also became clear to me that the router hardware engineers working on the hardware forwarding parts of routers were not even considering any major change to the architecture, for the simple reason that they didn't need to.
There may be many reasons to consider making a major change to the way that the Internet does routing and addressing, but the inability to build equipment that can handle several million entries is NOT a valid reason. Ross -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Steven Blake Sent: 01 January 2009 11:47 To: Robin Whittle Cc: RRG Subject: Re: [rrg] BGP scaling limit? On Thu, 2009-01-01 at 14:59 +1100, Robin Whittle wrote: > Short version: Limits on using PC hardware for router FIBs. > Fast SRAM is needed, not DRAM. [snip] One can build a 4M+ prefix, 300M LPM/sec FIB engine (v4 or v6) using commercially available FPGA + DDR3. Regarding RIB processing: I'll accept the argument that rate*state growth is exceeding Moore's Law. However, most RPs I've seen are anemic compared to commodity server hardware (for legitimate reasons). So there is plenty of room for improvement here. Regards, // Steve _______________________________________________ rrg mailing list [email protected] https://www.irtf.org/mailman/listinfo/rrg _______________________________________________ rrg mailing list [email protected] https://www.irtf.org/mailman/listinfo/rrg
