On 2017年01月13日 11:06, Peter Xu wrote:
In this patch, IOMMUNotifier.{start|end} are introduced to store section
information for a specific notifier. When notification occurs, we not
only check the notification type (MAP|UNMAP), but also check whether the
notified iova is in the range of specific
On 2017年01月13日 11:06, Peter Xu wrote:
VT-d codes are still using static DEBUG_INTEL_IOMMU macro. That's not
good, and we should end the day when we need to recompile the code
before getting useful debugging information for vt-d. Time to switch to
the trace system.
This is the first patch to do
On migration target, msix_vector_use() will be called in vmxnet3_post_load()
in second time, without a matching second call to msi_vector_unuse(),
which results in vector reference leak.
CC: Dmitry Fleytman
CC: Jason Wang
CC: Markus Armbruster
CC: Michael S. Tsirkin
Reviewed-by: Markus Armbru
Internal flag msix_used is unnecessary, it has the same effect as
msix_enabled().
The corresponding msi flag is already dropped in commit 1070048e.
CC: Dmitry Fleytman
CC: Jason Wang
CC: Markus Armbruster
CC: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Reviewed-by: Dmitry Fleytman
Ac
msix_init() reports errors with error_report(), which is wrong when
it's used in realize(). The same issue was fixed for msi_init() in
commit 1108b2f.
For some devices(like e1000e, vmxnet3) who won't fail because of
msix_init's failure, suppress the error report by passing NULL error object.
Bon
Also move certain hunk above, to place msix init related code together.
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Signed-off-by: Cao jin
---
hw/scsi/megasas.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletio
Resolve the TODO, msix=auto means msix on; if user specify msix=on,
then device creation fail on msix_init failure.
Also undo the overwrites of user configuration of msix.
CC: Michael S. Tsirkin
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
Reviewed-by: Mar
Resolve the TODO, msix=auto means msix on; if user specify msix=on,
then device creation fail on msix_init failure.
CC: Gerd Hoffmann
CC: Michael S. Tsirkin
CC: Markus Armbruster
CC: Marcel Apfelbaum
Reviewed-by: Gerd Hoffmann
Reviewed-by: Markus Armbruster
Acked-by: Marcel Apfelbaum
Signe
Commit afea4e14 seems forgetting to undo the overwrites, which is
unsuitable.
CC: Hannes Reinecke
CC: Paolo Bonzini
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Reviewed-by: Hannes Reinecke
Acked-by: Marcel Apfelbaum
Signed-off-by: Cao j
According to the disscussion:
http://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg08215.html
Let leaf function returns reasonable -errno, let caller decide how to
handle the return value.
Suggested-by: Markus Armbruster
CC: Markus Armbruster
CC: Michael S. Tsirkin
CC: Marcel Apfelbaum
Only a tiny modification in patch "megasas: remove unnecessary
megasas_use_msix()" to fix a megasas issue.
v8 changelog:
1. reorder: place the "megasas: remove unnecessary megasas_use_msix()"
as the last one. and fix the bug in it, detailed description in it,
also removed the R-b of it.
2. A
usb_xhci_realize() corrects invalid values of property "intrs"
automatically, but the uncorrected value is passed to msi_init(),
which chokes on invalid values. Delay that until after the
correction.
Resources allocated by usb_xhci_init() are leaked when msi_init()
fails. Fix by calling it after
CC: Markus Armbruster
CC: Marcel Apfelbaum
CC: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Acked-by: Marcel Apfelbaum
Signed-off-by: Cao jin
---
hw/pci/msix.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 0ec1cb14fc60..
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: 1484288903-18807-1-git-send-email-sjitindarsi...@gmail.com
Subject: [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries
tcg legacy kernel support
Type: series
=== TEST SC
We are calculating the authority mask register key value wrong.
The pte entry contains the key value with the two upper bits and the three
lower bits stored separately. We should use these two portions to get a 5
bit value, not or them together which will only give us a 3 bit value.
Fix this.
Si
We were printing an unsigned value as a signed value, fix this.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/mmu-hash64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03607d5..08d2393 100644
--- a/target/ppc
The cp_abort instruction is used to remove the state of an in progress
copy paste sequence. POWER9 compilers add this in various places, such
as context switches which causes illegal instruction signals since we
don't yet implement this instruction.
Given there is no implementation of the copy pas
The page table entry format was updated for the POWER9 processor.
It was decided that kernels would used the old format irrespective
with the translation occuring at the hypervisor level. Thus we convert
between the old and new format when accessing the ptes. Since we need the
whole pte to perform
Add a new mmu fault handler for the POWER9 cpu and add it as the handler
for the POWER9 cpu definition.
This handler checks if the guest is radix or hash based on the value in the
partition table entry and calls the correct fault handler accordingly.
The hash fault handling code has also been upd
It can be useful when debugging to print the LPCR value.
Thus we add the LPCR to the "info registers" output if the register had
been defined.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/ppc/translate.c b/target/pp
Similarly to how we have an external hpt pointer in the cpu state, add
an external partition table pointer and update it to point to the
partition table entry in the machine state struct on cpu reset.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr_cpu_core.c | 12 ++--
target/ppc/c
Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/ppc/
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h| 20 ++
The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.
Signed-off-by: S
The SDR1 registers was used to store the location of the hash page table.
This register no longer exists on POWER9 processors, so don't create it.
We now store the hash page table location in the process table entry.
We now check if the SDR1 register exists before printing its value when
display
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jiti
Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr_cpu_core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/h
POWER9 uses a partition table to store information relating to how
address translation is performed on a per partition basis.
Add a data area for this to the sPAPRMachineState struct and (re)allocate
it on machine reset.
Signed-off-by: Suraj Jitindar Singh
---
hw/ppc/spapr.c | 38 ++
This patch set provides the initial implementation of support for the
POWER9 processor running in tcg mode under the pseries machine type.
To use a POWER9 cpu provide the command line option "-cpu POWER9".
This is the initial work to make the mmu emulation model look like a POWER9
Currently onl
pcr_supported is used to define the supported PCR values for a given
processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05
compatibility modes, thus we set this accordingly.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu.h| 1 +
target/ppc/translate_init.c | 2 +
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu-qom.h| 5 -
target/ppc/mmu_helper.c | 2 ++
target/ppc/transl
This logical PVR value now corresponds to ISA version 3.00 so rename it
accordingly.
Signed-off-by: Suraj Jitindar Singh
---
target/ppc/cpu-models.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index aafbbd7..d587e69 100644
On Fri, Jan 13, 2017 at 3:19 AM, Jianjun Duan wrote:
> I have a question related to interplay of bypassing the shared memory in
> migration and memory hotplugging. If on the source guest a big chunk of
> memory is plugged in, will the shared memory still be mapped the same
> way on the guest? i.e,
Richard Henderson writes:
> On 01/12/2017 07:54 PM, Nikunj A Dadhania wrote:
>> +uint32_t match = 0; \
>> +\
>> +getVSR(xbn, &xb, env); \
>> +memset(&xt, 0,
On 01/12/2017 07:54 PM, Nikunj A Dadhania wrote:
+uint32_t match = 0; \
+\
+getVSR(xbn, &xb, env); \
+memset(&xt, 0, sizeof(xt));
xststdcsp: VSX Scalar Test Data Class Single-Precision
xststdcdp: VSX Scalar Test Data Class Double-Precision
xststdcqp: VSX Scalar Test Data Class Quad-Precision
Signed-off-by: Nikunj A Dadhania
---
target/ppc/fpu_helper.c | 66 -
target/ppc/helpe
xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision
Signed-off-by: Nikunj A Dadhania
---
target/ppc/fpu_helper.c | 39 +
target/ppc/helper.h | 2 ++
target/ppc/internal.h
This series contains 5 new instructions for POWER9 ISA3.0
VSX Scalar Test Data Class
VSX Vector Test Data Class
Changelog:
v0:
* Concise logic for identifying data class in Scalar/Vector
test data class instructions
Nikunj A Dadhania (2):
target-ppc: Add xvtstdc[sp,dp] instructions
On (Fri) 06 Jan 2017 [12:10:22], Peter Maydell wrote:
> On 5 January 2017 at 16:32, Amit Shah wrote:
> > The following changes since commit dbe2b65566e76d3c3a0c3358285c0336ac61e757:
> >
> > Merge remote-tracking branch
> > 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging (2016-12-28
Richard Henderson writes:
> On 01/12/2017 08:24 AM, Nikunj A Dadhania wrote:
>> +nan = tp##_is_any_nan(xb.fld); \
>> +infinity = tp##_is_infinity(xb.fld);\
>> +sign = tp##_is_neg(xb.fld); \
>> +zero = deno
This patch is based on Aviv Ben-David ()'s patch
upstream:
"IOMMU: enable intel_iommu map and unmap notifiers"
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg01453.html
However I removed/fixed some content, and added my own codes.
Instead of translate() every page for iotlb invalid
The default replay() don't work for VT-d since vt-d will have a huge
default memory region which covers address range 0-(2^64-1). This will
normally bring a dead loop when guest starts.
The solution is simple - we don't walk over all the regions. Instead, we
jump over the regions when we found tha
Generalizing the notify logic in memory_region_notify_iommu() into a
single function. This can be further used in customized replay()
functions for IOMMUs.
Signed-off-by: Peter Xu
---
include/exec/memory.h | 15 +++
memory.c | 29 ++---
2 files ch
This is preparation work to finally enabled dynamic switching ON/OFF for
VT-d protection. The old VT-d codes is using static IOMMU address space,
and that won't satisfy vfio-pci device listeners.
Let me explain.
vfio-pci devices depend on the memory region listener and IOMMU replay
mechanism to m
In this patch, IOMMUNotifier.{start|end} are introduced to store section
information for a specific notifier. When notification occurs, we not
only check the notification type (MAP|UNMAP), but also check whether the
notified iova is in the range of specific IOMMU notifier, and skip those
notifiers
Before this one we only invalidate context cache when we receive context
entry invalidations. However it's possible that the invalidation also
contains a domain switch (only if cache-mode is enabled for vIOMMU). In
that case we need to notify all the registered components about the new
mapping.
Si
Another patch to convert the DPRINTF() stuffs. This patch focuses on the
address translation path and caching.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 84 +--
hw/i386/trace-events | 7 +
2 files changed, 48 insertions(+), 43 delet
Originally we have one memory_region_iommu_replay() function, which is
the default behavior to replay the translations of the whole IOMMU
region. However, on some platform like x86, we may want our own replay
logic for IOMMU regions. This patch add one more hook for IOMMUOps for
the callback, and i
Before we have int-remap, we need to bypass interrupt write requests.
That's not necessary now - we have supported int-remap, and all the irq
region requests should be redirected there. Cleaning up the block with
an assertion instead.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 28 ++
This is an "global" version of exising memory_region_iommu_replay() - we
announce the translations to all the registered notifiers, instead of a
specific one.
Signed-off-by: Peter Xu
---
include/exec/memory.h | 8
memory.c | 9 +
2 files changed, 17 insertions(+)
d
From: Aviv Ben-David
This capability asks the guest to invalidate cache before each map operation.
We can use this invalidation to trap map operations in the hypervisor.
Signed-off-by: Aviv Ben-David
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 5 +
hw/i386/intel_iommu_int
There are lots of places in current intel_iommu.c codes that named
"iova" as "gpa". It is really confusing to use a name "gpa" in these
places (which is very easily to be understood as "Guest Physical
Address", while it's not). To make the codes (much) easier to be read, I
decided to do this once a
VT-d codes are still using static DEBUG_INTEL_IOMMU macro. That's not
good, and we should end the day when we need to recompile the code
before getting useful debugging information for vt-d. Time to switch to
the trace system.
This is the first patch to do it.
Generally, the rule of mine is:
- f
This helps in debugging incorrect level passed in.
Signed-off-by: Peter Xu
---
hw/i386/intel_iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index b4166e0..b4019d0 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -168,6 +
v3:
- fix style error reported by patchew
- fix comment in domain switch patch: use "IOMMU address space" rather
than "IOMMU region" [Kevin]
- add ack-by for Paolo in patch:
"memory: add section range info for IOMMU notifier"
(this is seperately collected besides this thread)
- remove 3 patch
From: Li Qiang
The spec doesn't say the namespace label can't be zero
when read/write it. As this is no harmful, just allow
it.
Signed-off-by: Li Qiang
---
hw/mem/nvdimm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
index db896b0..40420
On Thu, Jan 12, 2017 at 09:54:04PM +0530, Nikunj A Dadhania wrote:
> This series contains 11 new instructions for POWER9 ISA3.0
> VSX Scalar Test Data Class
> VSX Vector Test Data Class
> VSX Vector Convert HP/SP
> VSX Scalar Multiply/Divide
> VSX Scalar Convert Unsigned/Signed
On Fri, Jan 13, 2017 at 10:19:27AM +0800, Peter Xu wrote:
[...]
> > This all looks good to me. The series needs to be
> > rebased on top of latest bits.
> > In particular, Jason made changes which conflict
> > with this.
>
> Michael,
>
> Thanks for your positive feedback.
>
> Could you provide
>
> On Thu, Jan 12, 2017 at 12:26:24PM +, Gonglei (Arei) wrote:
> > Hi,
> >
> >
> > >
> > > On 01/04/2017 11:10 AM, Gonglei (Arei) wrote:
> > > > Hi all,
> > > >
> > > > I attach the diff files between v14 and v15 for better review.
> > > >
> > > Hi,
> > >
> > > only had a quick look. Will tr
On Thu, 01/12 19:07, Paolo Bonzini wrote:
> This is the first step of pushing down the AioContext lock. Bottom halves
> are already protected by their own lock, use it also for walking_bh
> and for the handlers list (including walking_handlers). The (lock,
> walking_foo) pair is wrapped into the
On 2017年01月12日 22:17, Michael S. Tsirkin wrote:
On Wed, Jan 11, 2017 at 12:32:12PM +0800, Jason Wang wrote:
This patches implements Device IOTLB support for vhost kernel. This is
done through:
1) switch to use dma helpers when map/unmap vrings from vhost codes
2) introduce a set of VhostOps t
On Thu, Jan 12, 2017 at 04:27:30PM +0200, Michael S. Tsirkin wrote:
> On Tue, Jan 03, 2017 at 03:29:37PM +0800, Peter Xu wrote:
> > (I renamed the title for this RFC v2, since starting from this version
> > the series will be based on master, also I picked up some more fixes
> > for vt-d into thi
>
> On Thu, Jan 12, 2017 at 03:10:25PM +0100, Christian Borntraeger wrote:
> > On 01/10/2017 01:56 PM, Christian Borntraeger wrote:
> > > On 01/10/2017 01:36 PM, Gonglei (Arei) wrote:
> > >> Hi,
> > >>
> > >>>
> > >>> On 12/15/2016 03:03 AM, Gonglei wrote:
> > >>> [...]
> > +
> > +static
AVX512_VPOPCNTDQ: Vector POPCNT instructions for word and qwords.
variable precision.
Signed-off-by: He Chen
---
Changes from v1:
* Rename vpopcntdq to avx512-vpopcntdq.
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i3
Currently, VQs are started as soon as a SET_VRING_KICK is received. That
is too early in the VQ setup process, as the backend might not yet have
a callfd to notify in case it received a kick and fully processed the
request/command. This patch only starts a VQ when a SET_VRING_CALL is
received.
Sig
Hi Paolo,
Thanks again for the review.
Just to clarify:
> On 2 Jan 2017, at 02:25, Paolo Bonzini wrote:
>
>
>
> On 21/12/2016 23:17, Felipe Franciosi wrote:
>> To use it, one must configure Qemu with --enable-vhost-user-scsi and
>> start Qemu with a command line equivalent to:
>>
>> qemu-sys
CCed Haozhong
On 01/12/2017 07:09 PM, Stefan Hajnoczi wrote:
On Thu, Jan 12, 2017 at 11:18:25AM +0800, Xiao Guangrong wrote:
On 01/11/2017 05:36 PM, Stefan Hajnoczi wrote:
Unlike g_free(), g_array_free() does not accept a NULL pointer argument.
The following error is logged when an nvdimm d
On Thu, Jan 12, 2017 at 03:47:31PM +, Alex Bennée wrote:
> We have never has the concept of global TLB entries which would avoid
> the flush so we never actually use this flag. Drop it and make clear
> that tlb_flush is the sledge-hammer it has always been.
>
> Signed-off-by: Alex Bennée
> Re
On Thu, Jan 12, 2017 at 03:47:29PM +, Alex Bennée wrote:
> It is a common thing amongst the various cpu reset functions want to
> flush the SoftMMU's TLB entries. This is done either by calling
> tlb_flush directly or by way of a general memset of the CPU
> structure (sometimes both).
>
> This
On Thu, Jan 12, 2017 at 09:47:29AM +0100, Hervé Poussineau wrote:
> Signed-off-by: Hervé Poussineau
Merged to ppc-for-2.9.
> ---
> MAINTAINERS | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1444b26..f4b02ab 100644
> --- a/MAINTAIN
On Wed, Jan 11, 2017 at 07:42:04PM -0800, no-re...@patchew.org wrote:
> Hi,
>
> Your series seems to have some coding style problems. See output below for
> more information:
I don't think this is a real problem:
> Checking PATCH 46/67: target-ppc: Add xxextractuw instruction...
> ERROR: Macros
Applied to ppc-for-2.9.
On Thu, Jan 12, 2017 at 06:08:31PM -0200, Jose Ricardo Ziviani wrote:
> v6:
> - improves bcdtrunc/bcdutrunc overflow comparison
> - removes bcds/bcdus/bcdsr applied patches
>
> v5:
> - removes 'unlikely' gcc branch pred. hints from not unlikely places
> - adds comment
On Thu, Jan 12, 2017 at 12:53:28PM -0500, Laine Stump wrote:
> On 01/12/2017 11:35 AM, Michael Roth wrote:
> > Quoting Laine Stump (2017-01-12 08:52:10)
> > > On 01/12/2017 05:31 AM, Andrea Bolognani wrote:
> > > > On Mon, 2017-01-09 at 10:46 +1100, David Gibson wrote:
> > > > > > > * To allow
On Thu, Jan 12, 2017 at 11:31:35AM +0100, Andrea Bolognani wrote:
> On Mon, 2017-01-09 at 10:46 +1100, David Gibson wrote:
> > > >* To allow for hotplugged devices, libvirt should also add a number
> > > > of additional, empty vPHBs (the PAPR spec allows for hotplug of
> > > > PHBs, b
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
Grammar in subject is a bit terse; maybe:
char: move QIOChannel-related stuff to char-io.h
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char-io.h | 24 +++
> chardev/char-io.c | 168
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Curiously unused since its introduction in commit 7b0bfdf52d69.
>
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char.c | 1 -
> 1 file changed, 1 deletion(-)
Reviewed-by: Eric Blake
--
Eric Blake eblake redhat com+1-919-301-3266
L
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char-ringbuf.c | 226
> +
> chardev/char.c | 218 ---
> chardev/Makefile.objs | 1 +
> 3 file
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> This define is used by several character devices, place it in char
> common header.
>
> Signed-off-by: Marc-André Lureau
> ---
> include/sysemu/char.h | 1 +
> chardev/char.c| 13 ++---
> 2 files changed, 7 insertions(+), 7 dele
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> A mechanical move, except that qemu_chr_write_all() needs to be declared
> in char.h header to be used from chardev unit files.
>
> Signed-off-by: Marc-André Lureau
> ---
> +++ b/chardev/char-mux.h
> @@ -0,0 +1,40 @@
> +#ifndef CHAR_MUX_H
> +#de
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> Signed-off-by: Marc-André Lureau
> ---
> chardev/char-null.c | 31 +++
> chardev/char.c| 23 ---
> chardev/Makefile.objs | 1 +
> 3 files changed, 32 insertions(+), 23 deletions(-)
> cre
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> All chardev must implement chr_write(), but parallel and null chardev
> both use null_chr_write(). Move it to the base class, so we don't need
> to export the function when splitting the chardev in respective files.
>
> Signed-off-by: Marc-André L
Switch to virtio_mmio.h from Linux - will make it
easier to implement virtio 1.
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio-mmio.c | 95 +++--
1 file changed, 37 insertions(+), 58 deletions(-)
diff --git a/hw/virtio/virtio-mmio.c b/hw/virti
Signed-off-by: Michael S. Tsirkin
---
include/standard-headers/linux/virtio_mmio.h | 141 +++
1 file changed, 141 insertions(+)
create mode 100644 include/standard-headers/linux/virtio_mmio.h
diff --git a/include/standard-headers/linux/virtio_mmio.h
b/include/standard-h
On 12 January 2017 at 20:41, Edgar E. Iglesias wrote:
> On Tue, Jan 10, 2017 at 06:44:07PM +, Peter Maydell wrote:
>> Add support for generating the ISS (Instruction Specific Syndrome)
>> for Data Abort exceptions taken from AArch32. These syndromes are
>> used by hypervisors for example to tr
On 01/11/2017 11:29 AM, Marc-André Lureau wrote:
> This will help to split char.c in several units without having to
> reference them all everywhere. This is useful in particular for tests.
>
> Signed-off-by: Marc-André Lureau
> ---
> @@ -221,7 +222,7 @@ subdir-dtc:dtc/libfdt dtc/tests
> dtc/%:
On Tue, Jan 10, 2017 at 06:44:08PM +, Peter Maydell wrote:
> To run a VM in 32-bit EL1 our AArch32 interrupt handling code
> needs to be able to cope with VIRQ and VFIQ exceptions.
> These behave like IRQ and FIQ except that we don't need to try
> to route them to Monitor mode.
>
> Signed-off-
Le 12/01/2017 à 22:14, Thomas Huth a écrit :
> On 12.01.2017 21:18, Laurent Vivier wrote:
>> Address Register indirect With postincrement:
>>
>> When using the stack pointer (A7) with byte size data, the register
>> is incremented by two.
>>
>> Address Register indirect With predecrement:
>>
>> Whe
virtio core has code to revert queue number
to maximum on reset. Drop TODO to add that.
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio-pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 8baaf2b..09230c0 100644
--- a/hw/virtio/vi
This patch fixes passing through a keyboard for me. I tried a Logitech
K120 (046d:c31c).
After that, I tried my real-world use case being a standard USB sound
card (046d:0a4d). This does not crash the machine anymore, but linux
reports:
xhci_hcd :00:03.0: ERROR Transfer event TRB DMA ptr not
Current code seems to assume ring size is
always decreased but this is not required by spec:
what spec says is just that size can not exceed
the maximum. Fix it up.
Signed-off-by: Michael S. Tsirkin
---
include/hw/virtio/virtio.h | 1 +
hw/s390x/virtio-ccw.c | 2 +-
hw/virtio/virtio.c
On 12/01/2017 20:37, Lluís Vilanova wrote:
> Stefan Hajnoczi writes:
>
>> On Tue, Jan 10, 2017 at 05:31:37PM +0100, Paolo Bonzini wrote:
>>> On 09/01/2017 18:01, Stefan Hajnoczi wrote:
Or use a simpler scheme:
struct CPUState {
...
uint32_t dstate_update_count;
>
Qemu 2.8.0 is no better. Actually now win-10 can even boot, getting the
light blue window with sad face saying: "Your PC ran into a problem and
needs to restart...". Moreover, the qemu monitor mode (alt-2) pops up a
frozen useless window, so no way to try reseting...
--
You received this bug n
On 12.01.2017 21:18, Laurent Vivier wrote:
> Address Register indirect With postincrement:
>
> When using the stack pointer (A7) with byte size data, the register
> is incremented by two.
>
> Address Register indirect With predecrement:
>
> When using the stack pointer (A7) with byte size data,
On Wed, Jan 11, 2017 at 11:51 PM, Eric Blake wrote:
> On 01/11/2017 12:24 PM, Nir Soffer wrote:
>> From: Nir Soffer
>>
>> The result of openfile was not checked, leading to failure deep in the
>> actual command with confusing error message, and exiting with exit code 0.
>>
>> Here is one example
On Tue, Jan 10, 2017 at 06:44:09PM +, Peter Maydell wrote:
> The DBGVCR_EL2 system register is needed to run a 32-bit
> EL1 guest under a Linux EL2 64-bit hypervisor. Its only
> purpose is to provide AArch64 with access to the state of
> the DBGVCR AArch32 register. Since we only have a dummy
>
On Tue, Jan 10, 2017 at 06:44:06PM +, Peter Maydell wrote:
> The GICv3 virt patchset is sufficient to run a 64-bit guest under
> a 64-bit host kernel. To run 32-bit guests under the 64-bit host
> you need a few more things:
> * data aborts from AArch32 need to provide instruction syndrome info
On Tue, Jan 10, 2017 at 06:44:07PM +, Peter Maydell wrote:
> Add support for generating the ISS (Instruction Specific Syndrome)
> for Data Abort exceptions taken from AArch32. These syndromes are
> used by hypervisors for example to trap and emulate memory accesses.
>
> This is the equivalent
On Thu, Jan 12, 2017 at 5:01 AM, Fam Zheng wrote:
> On Wed, 01/11 15:51, Eric Blake wrote:
>> On 01/11/2017 12:24 PM, Nir Soffer wrote:
>> > From: Nir Soffer
>> >
>> > The result of openfile was not checked, leading to failure deep in the
>> > actual command with confusing error message, and exit
Signed-off-by: Laurent Vivier
---
target/m68k/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 23e2b06..cf5d8dd 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1934,7 +1934,6 @@ DISAS_INSN(cas)
defau
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.
We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)
FIX: https://github.co
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