Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Hi all
I like that idea - in this way we can do it really affordable with lower end
FPGAs and still compatible with MTCA.
If we place all RF stuff on the modules, with RF connectors mounted directly
on the front panel, this could work.
How we would deliver the clocks? Using external SMA connectors?
The only think I worry about is performance of the DACs.
ZynQ US+ can run IOserdes with almost 2Gbit/s performance - one can make
1000base-x directly on IO pins using oversampling technique.
Greg

-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] 
Sent: Wednesday, March 30, 2016 1:50 PM
To: Grzegorz Kasprowicz 
Cc: 'Slichter, Daniel H. (Fed)' ; 'Grzegorz
Kasprowicz' ; artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> - they can be used immediately with existing OSHW carriers like AFC/AFCK. 

AFCK may be overkill. We are still working on evaluating the FPGA resource
requirements.

> - it could be hard to fit FPGA, supply, DACs and several RF modules, 
> all on single dual width AMC, especially when shielding is required. 
> RTM relaxes these constraints
> - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF 
> modules. In case of single AMC board it would be hard to achieve such 
> channels density.

How about this:
* we reduce the number of channels per AMC to 4 DACs + 4 ADCs
* we can therefore use a smaller FPGA. Communication lanes to the master
board are relatively cheap if we put them on IOSERDES.
* the power density and cooling requirements are also reduced.
* for the RF daughter cards, we use a custom form factor that can use at
least
2/3 of the AMC front panel
* connectors between the DSP card and the RF daughter card are 2mm header
and 8x SMP
* the rest of the AMC front panel used for (optional, runtime selectable)
clock input and some TTLs.

Sébastien


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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Such assembly technique is called:
castellated PCB module
https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB


On 30 March 2016 at 22:40, Grzegorz Kasprowicz  wrote:

> One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6
> ones, we won't be able to screw them.
> But we can install MMCX ones for clocks and fit in total of 7 RF
> connectors,
> Look here
> http://www.ohwr.org/attachments/3390/fmc_top.jpg
> Greg
>
> On 30 March 2016 at 22:38, Grzegorz Kasprowicz  wrote:
>
>> Well, we can do another crazy thing - solder small module with RF stuff
>> on the FMC board, under same shield.
>> In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the
>> functionality by soldering (automatic or manual) of just RF modules. WE can
>> even design such modules to hold the front-end connectors of leave them on
>> the FMC.
>> Such approach has also some attractive feature - we can make them using
>> small pieces of Rogers material which is hell expensive and it's hard to
>> make small vias and thin traces needed for JESD signals.
>> these modules could look like that
>> http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
>> You can mount them by pick and place or manually.
>> IT is also possible to manually disassemble them.
>> This is a form factor of popular RF modules, i.e. wifi, GPS and LTE
>> modems.
>> http://www.emcfastpass.com/rf-modules/
>> And is simply works
>> Greg
>>
>>
>> On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) <
>> daniel.slich...@nist.gov> wrote:
>>
>>> > Maybe we should come back to the roots:) What if we use standard FMCs
>>> > (LPC) with DAC/ADC channels and RF stuff _on_ them.
>>> > JESD204B and some pins would go to the FPGA while DAC and RF clock
>>> would
>>> > be fed externally.
>>> > In this way we leave general purpose AMC board and define its
>>> functionality
>>> > by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
>>> > ADC+DAC,DAC+DAC, we would cover several use cases:
>>> > Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
>>> > FMCs with only DAC and RF stuff on it can be simple, 4 layer boards
>>> with
>>> > external sield.
>>> > Look at this shield (my project)
>>> > http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
>>> > In this way we could use existing AFCK for quick tests
>>>
>>> We have been working with the notion that should be many possible front
>>> ends for each of the DACs or ADCs, depending on what the particular
>>> application is, and so we want to separate the analog daughtercards from
>>> whatever board has the DACs and ADCs on it.  This way, you can reconfigure
>>> the hardware for high-frequency or low-frequency applications, for example,
>>> by changing daughtercards and not having to build entire new AMC cards.
>>> The modularity principle lets one have a single design for the AMC card
>>> (aka DSP card) that can be used for many different applications, by
>>> shifting the analog signal processing circuitry onto a separate card.
>>>
>>> Now, as you suggest we could just change the level at which we make this
>>> break from the AMC card, shift the DACs and ADCs onto the daughter card as
>>> well, and use FMC to communicate with the whole thing.  This makes it a bit
>>> more expensive/difficult to reconfigure the analog front end, but the DAC
>>> and ADC costs are not so high that it is impossible to do.  I had
>>> envisioned the notion of making the daughtercards simple enough that end
>>> users could redesign/respin easily to accommodate their own applications,
>>> or we could ship unstuffed or partially stuffed boards that they could
>>> complete with the particular filters etc they desire.
>>>
>>> However, I agree that there are compelling arguments for using the
>>> architecture you propose.  We would need to pick just a few board styles (I
>>> suggest quad DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board
>>> styles we would need to make several different variants with different
>>> analog front ends (3 types for DAC - low frequency, baseband RF,
>>> upconverted RF - and 2 types for ADC - baseband RF and downconverted RF,
>>> both likely including switchable gain).  So now we are looking at making 3
>>> types of quad DAC boards, 2 types of ADC board, and probably 3 types of
>>> DAC/ADC board (upconvert DAC/downconvert ADC, baseband RF DAC/baseband RF
>>> ADC, and low frequency DAC/baseband RF ADC).  So now there are 8 different
>>> daughterboard designs.  If we restrict ourselves to just quad DAC or quad
>>> ADC on a given daughtercard, then there are 5 designs, same as in the
>>> current proposal for analog-only daughtercards.  I would still want to have
>>> boards be partially stuffed (or stuffed in different 

Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Actually HPC with LPC IO assignment and 8 x GTP links is popular
configuration
So you have 34 LVDS pairs and 8 GTP links.

On 30 March 2016 at 23:00, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:

> > On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed)
> >  wrote:
> > > Now, as you suggest we could just change the level at which we make
> this
> > break from the AMC card, shift the DACs and ADCs onto the daughter card
> as
> > well, and use FMC to communicate with the whole thing.  This makes it a
> bit
> > more expensive/difficult to reconfigure the analog front end, but the DAC
> > and ADC costs are not so high that it is impossible to do.  I had
> envisioned the
> > notion of making the daughtercards simple enough that end users could
> > redesign/respin easily to accommodate their own applications, or we could
> > ship unstuffed or partially stuffed boards that they could complete with
> the
> > particular filters etc they desire.
> >
> > It makes letting unused mezzanines collect dust on the shelf more
> > expensive.
>
> The point is you buy X number of daughtercards for Y AMC cards, where X>Y
> (perhaps X=2*Y or X=3*Y), and the daughtercards either do or don't have
> ADC/DAC on them.  If they do, it costs you more than if the ADC/DAC were on
> the AMC modules.
>
> > > However, I agree that there are compelling arguments for using the
> > architecture you propose.  We would need to pick just a few board styles
> (I
> > suggest quad DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board
> > styles we would need to make several different variants with different
> > analog front ends (3 types for DAC - low frequency, baseband RF,
> > upconverted RF - and 2 types for ADC - baseband RF and downconverted RF,
> > both likely including switchable gain).  So now we are looking at making
> 3
> > types of quad DAC boards, 2 types of ADC board, and probably 3 types of
> > DAC/ADC board (upconvert DAC/downconvert ADC, baseband RF
> > DAC/baseband RF ADC, and low frequency DAC/baseband RF ADC).  So now
> > there are 8 different daughterboard designs.  If we restrict ourselves
> to just
> > quad DAC or quad ADC on a given daughtercard, then there are 5 designs,
> > same as in the current proposal for analog-only daughtercards.  I would
> still
> > want to have boards be partially stuffed (or stuffed in different
> > configurations on demand) to allow users to choose the frequencies of
> > interest for analog filters etc.
> > >
> > > If we proceed this way, we will need an external clock SMA for each FMC
> > module, because we don't want the high-quality external clock going down
> > one FMC connector, across the AMC, and up the other FMC connector for
> > signal integrity/crosstalk reasons.
> >
> > For a digital clock with fast edges 60 dB of crosstalk is _much_ less of
> a
> > problem.
>
> No!  The clock coming in will be a sine wave from a low phase noise
> oscillator somewhere.  The DACs and ADCs will threshold this clock to
> determine their sample times.  Any amount of crosstalk will distort the
> clock signal (adding or subtracting to the voltage at a given time), thus
> skewing the time at which the threshold is reached and thus inducing jitter
> into the sampling times.  This would also hold true even if you have an
> LVPECL clock signal, because at frequencies like 2.4 GHz the rise and fall
> times (~100-200 ps) are similar to that of a sine wave.  Unlike for digital
> data signals, any amount of crosstalk will degrade the jitter and/or edge
> time performance for a clock signal.
>
> > > Are we thinking we would try to implement the actual VITA 57 standard
> on
> > these connectors?  Or just use them as convenient high-speed-capable
> > connectors?  I agree with the second idea, but I don't like the first
> one.
> >
> > What from the VITA 57 pin assignmend do you not like?
>
> If you comply with VITA 57, we will need to use an HPC connector to get
> enough gigabit transceivers into the connector, and we will have to
> populate all the other digital lines.  We could use an HPC connector with
> the VITA 57 LPC connections, plus adding on the gigabit transceivers in the
> locations where they would go for an HPC connector, and thus have an LPC
> compliant connector with "extra features" for the needed gigabit
> transceivers.  I am just trying to reduce unnecessary complexity in routing
> the AMC board to the FMC connectors, since HPC is much more of a pain than
> LPC in this regard.
>
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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote:
> [GK] If you don't use ARM, you still get hardened SDRAM controller and 
> GBE MACs.

Yes, that's what I was saying: you cannot get rid of them (i.e. use their
pins like other IOs). So you need to use the Zynq-specific features of
Vivado, interface your design to the hardened AXI system, use some obscure
Vivado "wizard" to set up the SDRAM, and write a software driver for
Xilinx's GbE MAC. All doable, but annoying.

[GK]
Well, you don't have to write it.
It is already available for RTOS and linux.
But it's true - it occupies MIO bank and dedicated DDR port. But this is axi
and can be easily accessible from PL part.
How many IOs do you need?

> > * we want to avoid RTMs and instead put the DAC/ADCs on the AMC card 
> > and have analog plug-ins using the FMC form factor (see my document).
> > **Are you sure you would get noise performance from such setup that 
> > satisfies you?
> 
> Unless the FMC connector is particularly bad with analog signals, I 
> think it should not be worse than the current hardware. [GK] All 
> depends how you deliver the clock for such DAC. This is the weakest point
of such solution.

The DACs will be mounted on the DSP cards (AMC directly), not the RF
daughtercards. And the DSP cards will have an external clocking option, that
may use semi-rigid coax if need be.

[GK]
OK, if you make clock splitter and deliver the clocks for both DACs and RF
modules externally, this should work.
Another issue are ground loops, so clock and RF SMA outputs may need to be
isolated.


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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Maybe we should come back to the roots:)
What if we use standard FMCs (LPC) with DAC/ADC channels and RF stuff _on_ them.
JESD204B and some pins would go to the FPGA while DAC and RF clock would be fed 
externally.
In this way we leave general purpose AMC board and define its functionality by 
FMC boards
If we make 3 flavours of FMCs: ADC+ADC, ADC+DAC,DAC+DAC, we would cover several 
use cases:
Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with 
external sield.
Look at this shield (my project)
http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
In this way we could use existing AFCK for quick tests

-Original Message-
From: Slichter, Daniel H. (Fed) [mailto:daniel.slich...@nist.gov] 
Sent: Wednesday, March 30, 2016 5:46 PM
To: Leibrandt, David R. (Fed) ; Sébastien 
Bourdeauducq ; Grzegorz Kasprowicz 
Cc: 'Grzegorz Kasprowicz' ; artiq@lists.m-labs.hk
Subject: RE: [ARTIQ] FW: initial specification of the project

> I like this plan.  I think 4 + 4 channels will also make the front 
> panel connector density more reasonable.  What are you thinking for 
> number of daughter cards?  I suppose that more would give us more 
> flexibility, but less would be more economical in terms of cost and 
> layout area.  Perhaps two daughter cards would be reasonable: one for 
> all of the inputs and one for all of the outputs?

Agreed that ~ 8 front panel SMA connections, plus one clock SMA connection, is 
about what one can tolerate in a reasonable way in terms of physical footprint. 
 If we split this as 4 DAC + 4 ADC, it makes a nice symmetry although my 
suspicion is that most applications would prefer something more asymmetric with 
a few more DAC channels than ADC channels (6 DAC/2 ADC or 6 DAC/4 ADC, for 
example). One could go a simple as 4 DAC/2 ADC and make the space requirements 
even simpler to fulfill on the cards.  All of these modifications will increase 
the price per channel, even though we may be able to save on FPGA costs.  For 
example, if we do 4 DAC/2 ADC on a card with 1x AD9154 and 1x ADC16DX370 (our 
currently planned parts), we only need 10 GTX transceivers on the FPGA.  With 4 
DAC/4 ADC, this would be 12 GTX transceivers.  With these numbers we could look 
at the ZU5EV Zynq Ultrascale, instead of the ZU9EG, which we had been 
discussing.

To Greg's question on the RTM, we have had a number of extensive internal 
discussions about pros and cons of RTM and it seems that we don't want to 
pursue this avenue for a number of carefully considered reasons.  Let's just 
take it as a given that we will need to put everything on the AMC card or its 
analog daughtercards.  As stated, the DAC and ADC chips themselves will be on 
the AMC card, not the analog daughtercards.  

I am in favor of separate analog daughtercards for the inputs and the outputs, 
this seems sensible.  


> On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> > - they can be used immediately with existing OSHW carriers like AFC/AFCK.
> 
> AFCK may be overkill. We are still working on evaluating the FPGA 
> resource requirements.
> 
> > - it could be hard to fit FPGA, supply, DACs and several RF modules, 
> > all on single dual width AMC, especially when shielding is required.
> > RTM relaxes these constraints
> > - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF 
> > modules. In case of single AMC board it would be hard to achieve 
> > such channels density.
> 
> How about this:
> * we reduce the number of channels per AMC to 4 DACs + 4 ADCs
> * we can therefore use a smaller FPGA. Communication lanes to the 
> master board are relatively cheap if we put them on IOSERDES.
> * the power density and cooling requirements are also reduced.
> * for the RF daughter cards, we use a custom form factor that can use 
> at least
> 2/3 of the AMC front panel
> * connectors between the DSP card and the RF daughter card are 2mm 
> header and 8x SMP
> * the rest of the AMC front panel used for (optional, runtime 
> selectable) clock input and some TTLs.



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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration
So you have 34 LVDS pairs and 8 GTP links.

If this works for you then I don’t have major objections.  The other issue to 
consider is power rails, since for the analog circuitry we will probably want 
+/- 5V, +/- 15V as well as +3.3V, +1.8V, +12V.  Can we put these through on the 
FMC without breaking back compatibility?  For example, one rail on each of the 
4 VADJ pins?  I am sure this would not be VITA 57 compliant….and we don’t want 
switching converters on the FMC daughtercard for space and noise reasons both.
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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Well, it depends on trace width matching. We can simulate and characterize
it even at much higher frequencies.
If we place them really close to the DAC and match widths, remove grounds
under pads, we can match it not worse than SMA connectors.
We can even do even more crazy thing - try to make them mountable.
The only signals that would need to be transmitted is DAC output / ADC
input.
We can use low profile board to board connectors for rest of the signals -
I know ones that have 1mm stacking hight. For RF we could use PCB mounted
UFL connectors.
This is just crazy idea that need to be verified.

On 30 March 2016 at 23:02, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:

> This is an interesting potential solution although I am not sure how the
> signal integrity is at ~3 GHz, for example.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
> *Sent:* Wednesday, March 30, 2016 2:44 PM
> *To:* Slichter, Daniel H. (Fed) 
> *Cc:* Grzegorz Kasprowicz ; Leibrandt, David R.
> (Fed) ; Sébastien Bourdeauducq ;
> artiq@lists.m-labs.hk
> *Subject:* Re: [ARTIQ] FW: initial specification of the project
>
>
>
> Such assembly technique is called:
>
> castellated PCB module
>
> https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB
> 
>
>
>
> On 30 March 2016 at 22:40, Grzegorz Kasprowicz  wrote:
>
> One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6
> ones, we won't be able to screw them.
>
> But we can install MMCX ones for clocks and fit in total of 7 RF
> connectors,
>
> Look here
> http://www.ohwr.org/attachments/3390/fmc_top.jpg
>
> Greg
>
>
>
> On 30 March 2016 at 22:38, Grzegorz Kasprowicz  wrote:
>
> Well, we can do another crazy thing - solder small module with RF stuff on
> the FMC board, under same shield.
>
> In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the
> functionality by soldering (automatic or manual) of just RF modules. WE can
> even design such modules to hold the front-end connectors of leave them on
> the FMC.
>
> Such approach has also some attractive feature - we can make them using
> small pieces of Rogers material which is hell expensive and it's hard to
> make small vias and thin traces needed for JESD signals.
>
> these modules could look like that
> http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
>
> You can mount them by pick and place or manually.
>
> IT is also possible to manually disassemble them.
>
> This is a form factor of popular RF modules, i.e. wifi, GPS and LTE modems.
> http://www.emcfastpass.com/rf-modules/
>
> And is simply works
>
> Greg
>
>
>
>
>
> On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) <
> daniel.slich...@nist.gov> wrote:
>
> > Maybe we should come back to the roots:) What if we use standard FMCs
> > (LPC) with DAC/ADC channels and RF stuff _on_ them.
> > JESD204B and some pins would go to the FPGA while DAC and RF clock would
> > be fed externally.
> > In this way we leave general purpose AMC board and define its
> functionality
> > by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> > ADC+DAC,DAC+DAC, we would cover several use cases:
> > Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> > FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> > external sield.
> > Look at this shield (my project)
> > http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> > In this way we could use existing AFCK for quick tests
>
> We have been working with the notion that should be many possible front
> ends for each of the DACs or ADCs, depending on what the particular
> application is, and so we want to separate the analog daughtercards from
> whatever board has the DACs and ADCs on it.  This way, you can reconfigure
> the hardware for high-frequency or low-frequency applications, for example,
> by changing daughtercards and not having to build entire new AMC cards.
> The modularity principle lets one have a single design for the AMC card
> (aka DSP card) that can be used for many different applications, by
> shifting the analog signal processing circuitry onto a separate card.
>
> Now, as you suggest we could just change the level at which we make this
> break from the AMC card, shift the DACs and ADCs onto the daughter card as
> well, and use FMC to communicate with the whole thing.  This makes it a bit
> more expensive/difficult to reconfigure the analog front end, but the DAC
> and ADC costs are not so high that it is impossible to do.  I had
> envisioned the notion of making the daughtercards simple enough that end
> users could redesign/respin easily to accommodate their own applications,
> 

Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

So now we are moving towards complying with the AMC FMC physical standard.  Is 
this something we want to do?  There are pluses (able to use existing AMC FMC 
cards) and minuses (squeezing things in more tightly than we otherwise might 
have to).

From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 2:41 PM
To: Slichter, Daniel H. (Fed) 
Cc: Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) 
; Sébastien Bourdeauducq ; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6 ones, 
we won't be able to screw them.
But we can install MMCX ones for clocks and fit in total of 7 RF connectors,
Look here
http://www.ohwr.org/attachments/3390/fmc_top.jpg
Greg

On 30 March 2016 at 22:38, Grzegorz Kasprowicz 
> wrote:
Well, we can do another crazy thing - solder small module with RF stuff on the 
FMC board, under same shield.
In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the 
functionality by soldering (automatic or manual) of just RF modules. WE can 
even design such modules to hold the front-end connectors of leave them on the 
FMC.
Such approach has also some attractive feature - we can make them using small 
pieces of Rogers material which is hell expensive and it's hard to make small 
vias and thin traces needed for JESD signals.
these modules could look like that
http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
You can mount them by pick and place or manually.
IT is also possible to manually disassemble them.
This is a form factor of popular RF modules, i.e. wifi, GPS and LTE modems.
http://www.emcfastpass.com/rf-modules/
And is simply works
Greg


On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) 
> wrote:
> Maybe we should come back to the roots:) What if we use standard FMCs
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would
> be fed externally.
> In this way we leave general purpose AMC board and define its functionality
> by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> ADC+DAC,DAC+DAC, we would cover several use cases:
> Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> external sield.
> Look at this shield (my project)
> http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> In this way we could use existing AFCK for quick tests

We have been working with the notion that should be many possible front ends 
for each of the DACs or ADCs, depending on what the particular application is, 
and so we want to separate the analog daughtercards from whatever board has the 
DACs and ADCs on it.  This way, you can reconfigure the hardware for 
high-frequency or low-frequency applications, for example, by changing 
daughtercards and not having to build entire new AMC cards.  The modularity 
principle lets one have a single design for the AMC card (aka DSP card) that 
can be used for many different applications, by shifting the analog signal 
processing circuitry onto a separate card.

Now, as you suggest we could just change the level at which we make this break 
from the AMC card, shift the DACs and ADCs onto the daughter card as well, and 
use FMC to communicate with the whole thing.  This makes it a bit more 
expensive/difficult to reconfigure the analog front end, but the DAC and ADC 
costs are not so high that it is impossible to do.  I had envisioned the notion 
of making the daughtercards simple enough that end users could redesign/respin 
easily to accommodate their own applications, or we could ship unstuffed or 
partially stuffed boards that they could complete with the particular filters 
etc they desire.

However, I agree that there are compelling arguments for using the architecture 
you propose.  We would need to pick just a few board styles (I suggest quad 
DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board styles we would 
need to make several different variants with different analog front ends (3 
types for DAC - low frequency, baseband RF, upconverted RF - and 2 types for 
ADC - baseband RF and downconverted RF, both likely including switchable gain). 
 So now we are looking at making 3 types of quad DAC boards, 2 types of ADC 
board, and probably 3 types of DAC/ADC board (upconvert DAC/downconvert ADC, 
baseband RF DAC/baseband RF ADC, and low frequency DAC/baseband RF ADC).  So 
now there are 8 different daughterboard designs.  If we restrict ourselves to 
just quad DAC or quad ADC on a given daughtercard, then there are 5 designs, 
same as in the current proposal for analog-only daughtercards.  I would still 
want to have boards be partially stuffed (or 

Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Are we talking about double width AMCs?
Two DAC channels and 2 RF modules should fit.
Greg

-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] 
Sent: Wednesday, March 30, 2016 5:46 PM
To: Leibrandt, David R. (Fed) 
Cc: Grzegorz Kasprowicz ; 'Grzegorz Kasprowicz'
; artiq@lists.m-labs.hk; Slichter, Daniel H. (Fed)

Subject: Re: [ARTIQ] FW: initial specification of the project

On Wednesday, 30 March 2016 3:15:59 PM HKT Leibrandt, David R. (Fed) wrote:
> What are you thinking for number of daughter cards?  I suppose that 
> more would give us more flexibility, but less would be more economical 
> in terms of cost and layout area.  Perhaps two daughter cards would be
reasonable:
> one for all of the inputs and one for all of the outputs?

Just one, the space on the AMC is rather limited.

As for splitting inputs and outputs - maybe, but then it makes sense to
allow resource sharing and/or space to be redistributed within one card.
Similar to double FMC, e.g.
http://www.euvis.com/products/mod/fmc/image/FMC2653.JPG

Sébastien


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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

OK, I see your point

On 30 March 2016 at 23:17, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:

> We definitely need +/- 15V for the low frequency (e.g. trap electrode)
> amplifiers.  Many low noise amplifiers and RF components run off +5V or +/-
> 5V and have substantial current draws, so if you pull everything from +/-
> 15V rails you are tripling your power dissipation and you end up with very
> hot regulators.  The DACs and ADCs will be dissipating a fair amount of
> power already so we want to try to keep the power budget under control.
> Other than that, I don’t see major reasons why one couldn’t run fewer
> analog rails.  I think we are better off with DC/DC converters on the AMC
> card making a number of rails, which then have some filtering/regulation on
> the AMC card and then a final stage of LDO regulation on the FMC
> daughtercard itself, as close to the amplifiers etc as possible.
>
>
>
> Using the alternating grounds a la CERN seems like a suitable solution to
> me for sending in these additional analog rails.
>
>
>
> *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
> *Sent:* Wednesday, March 30, 2016 3:13 PM
> *To:* Slichter, Daniel H. (Fed) 
> *Cc:* Robert Jördens ; Grzegorz Kasprowicz <
> gkasp...@elka.pw.edu.pl>; Leibrandt, David R. (Fed) <
> david.leibra...@nist.gov>; Sébastien Bourdeauducq ;
> artiq@lists.m-labs.hk
> *Subject:* Re: [ARTIQ] FW: initial specification of the project
>
>
>
> Well, CERN does it in their FMC carriers. They use HPC routed like LPC and
> then some of grounds are used as symmetrical analog supplies. In this way
> if you plug wrong board, it will short the supply but no damage will occur.
>
> I assume that low nosie DC/DC converters + LDOs will be installed on the
> AMC board.
>
> Do we need all these voltages, especially +/-5 and +/- 15? Won't single
> +/- 8 or +/- 15V be sufficient?
>
> Greg
>
>
>
> On 30 March 2016 at 23:08, Slichter, Daniel H. (Fed) <
> daniel.slich...@nist.gov> wrote:
>
>
>
> Actually HPC with LPC IO assignment and 8 x GTP links is popular
> configuration
>
> So you have 34 LVDS pairs and 8 GTP links.
>
>
>
> If this works for you then I don’t have major objections.  The other issue
> to consider is power rails, since for the analog circuitry we will probably
> want +/- 5V, +/- 15V as well as +3.3V, +1.8V, +12V.  Can we put these
> through on the FMC without breaking back compatibility?  For example, one
> rail on each of the 4 VADJ pins?  I am sure this would not be VITA 57
> compliant….and we don’t want switching converters on the FMC daughtercard
> for space and noise reasons both.
>
>
>
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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

> Maybe we should come back to the roots:) What if we use standard FMCs
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would
> be fed externally.
> In this way we leave general purpose AMC board and define its functionality
> by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> ADC+DAC,DAC+DAC, we would cover several use cases:
> Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> external sield.
> Look at this shield (my project)
> http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> In this way we could use existing AFCK for quick tests

We have been working with the notion that should be many possible front ends 
for each of the DACs or ADCs, depending on what the particular application is, 
and so we want to separate the analog daughtercards from whatever board has the 
DACs and ADCs on it.  This way, you can reconfigure the hardware for 
high-frequency or low-frequency applications, for example, by changing 
daughtercards and not having to build entire new AMC cards.  The modularity 
principle lets one have a single design for the AMC card (aka DSP card) that 
can be used for many different applications, by shifting the analog signal 
processing circuitry onto a separate card.  

Now, as you suggest we could just change the level at which we make this break 
from the AMC card, shift the DACs and ADCs onto the daughter card as well, and 
use FMC to communicate with the whole thing.  This makes it a bit more 
expensive/difficult to reconfigure the analog front end, but the DAC and ADC 
costs are not so high that it is impossible to do.  I had envisioned the notion 
of making the daughtercards simple enough that end users could redesign/respin 
easily to accommodate their own applications, or we could ship unstuffed or 
partially stuffed boards that they could complete with the particular filters 
etc they desire.  

However, I agree that there are compelling arguments for using the architecture 
you propose.  We would need to pick just a few board styles (I suggest quad 
DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board styles we would 
need to make several different variants with different analog front ends (3 
types for DAC - low frequency, baseband RF, upconverted RF - and 2 types for 
ADC - baseband RF and downconverted RF, both likely including switchable gain). 
 So now we are looking at making 3 types of quad DAC boards, 2 types of ADC 
board, and probably 3 types of DAC/ADC board (upconvert DAC/downconvert ADC, 
baseband RF DAC/baseband RF ADC, and low frequency DAC/baseband RF ADC).  So 
now there are 8 different daughterboard designs.  If we restrict ourselves to 
just quad DAC or quad ADC on a given daughtercard, then there are 5 designs, 
same as in the current proposal for analog-only daughtercards.  I would still 
want to have boards be partially stuffed (or stuffed in different 
configurations on demand) to allow users to choose the frequencies of interest 
for analog filters etc.

If we proceed this way, we will need an external clock SMA for each FMC module, 
because we don't want the high-quality external clock going down one FMC 
connector, across the AMC, and up the other FMC connector for signal 
integrity/crosstalk reasons.  

Are we thinking we would try to implement the actual VITA 57 standard on these 
connectors?  Or just use them as convenient high-speed-capable connectors?  I 
agree with the second idea, but I don't like the first one.  
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Re: [ARTIQ] FW: initial specification of the project

[Grzegorz Kasprowicz]

Well, we can do another crazy thing - solder small module with RF stuff on
the FMC board, under same shield.
In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the
functionality by soldering (automatic or manual) of just RF modules. WE can
even design such modules to hold the front-end connectors of leave them on
the FMC.
Such approach has also some attractive feature - we can make them using
small pieces of Rogers material which is hell expensive and it's hard to
make small vias and thin traces needed for JESD signals.
these modules could look like that
http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
You can mount them by pick and place or manually.
IT is also possible to manually disassemble them.
This is a form factor of popular RF modules, i.e. wifi, GPS and LTE modems.
http://www.emcfastpass.com/rf-modules/
And is simply works
Greg

On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:

> > Maybe we should come back to the roots:) What if we use standard FMCs
> > (LPC) with DAC/ADC channels and RF stuff _on_ them.
> > JESD204B and some pins would go to the FPGA while DAC and RF clock would
> > be fed externally.
> > In this way we leave general purpose AMC board and define its
> functionality
> > by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> > ADC+DAC,DAC+DAC, we would cover several use cases:
> > Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> > FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> > external sield.
> > Look at this shield (my project)
> > http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> > In this way we could use existing AFCK for quick tests
>
> We have been working with the notion that should be many possible front
> ends for each of the DACs or ADCs, depending on what the particular
> application is, and so we want to separate the analog daughtercards from
> whatever board has the DACs and ADCs on it.  This way, you can reconfigure
> the hardware for high-frequency or low-frequency applications, for example,
> by changing daughtercards and not having to build entire new AMC cards.
> The modularity principle lets one have a single design for the AMC card
> (aka DSP card) that can be used for many different applications, by
> shifting the analog signal processing circuitry onto a separate card.
>
> Now, as you suggest we could just change the level at which we make this
> break from the AMC card, shift the DACs and ADCs onto the daughter card as
> well, and use FMC to communicate with the whole thing.  This makes it a bit
> more expensive/difficult to reconfigure the analog front end, but the DAC
> and ADC costs are not so high that it is impossible to do.  I had
> envisioned the notion of making the daughtercards simple enough that end
> users could redesign/respin easily to accommodate their own applications,
> or we could ship unstuffed or partially stuffed boards that they could
> complete with the particular filters etc they desire.
>
> However, I agree that there are compelling arguments for using the
> architecture you propose.  We would need to pick just a few board styles (I
> suggest quad DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board
> styles we would need to make several different variants with different
> analog front ends (3 types for DAC - low frequency, baseband RF,
> upconverted RF - and 2 types for ADC - baseband RF and downconverted RF,
> both likely including switchable gain).  So now we are looking at making 3
> types of quad DAC boards, 2 types of ADC board, and probably 3 types of
> DAC/ADC board (upconvert DAC/downconvert ADC, baseband RF DAC/baseband RF
> ADC, and low frequency DAC/baseband RF ADC).  So now there are 8 different
> daughterboard designs.  If we restrict ourselves to just quad DAC or quad
> ADC on a given daughtercard, then there are 5 designs, same as in the
> current proposal for analog-only daughtercards.  I would still want to have
> boards be partially stuffed (or stuffed in different configurations on
> demand) to allow users to choose the frequencies of interest for analog
> filters etc.
>
> If we proceed this way, we will need an external clock SMA for each FMC
> module, because we don't want the high-quality external clock going down
> one FMC connector, across the AMC, and up the other FMC connector for
> signal integrity/crosstalk reasons.
>
> Are we thinking we would try to implement the actual VITA 57 standard on
> these connectors?  Or just use them as convenient high-speed-capable
> connectors?  I agree with the second idea, but I don't like the first one.
>
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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

> On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed)
>  wrote:
> > Now, as you suggest we could just change the level at which we make this
> break from the AMC card, shift the DACs and ADCs onto the daughter card as
> well, and use FMC to communicate with the whole thing.  This makes it a bit
> more expensive/difficult to reconfigure the analog front end, but the DAC
> and ADC costs are not so high that it is impossible to do.  I had envisioned 
> the
> notion of making the daughtercards simple enough that end users could
> redesign/respin easily to accommodate their own applications, or we could
> ship unstuffed or partially stuffed boards that they could complete with the
> particular filters etc they desire.
> 
> It makes letting unused mezzanines collect dust on the shelf more
> expensive.

The point is you buy X number of daughtercards for Y AMC cards, where X>Y 
(perhaps X=2*Y or X=3*Y), and the daughtercards either do or don't have ADC/DAC 
on them.  If they do, it costs you more than if the ADC/DAC were on the AMC 
modules.  

> > However, I agree that there are compelling arguments for using the
> architecture you propose.  We would need to pick just a few board styles (I
> suggest quad DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board
> styles we would need to make several different variants with different
> analog front ends (3 types for DAC - low frequency, baseband RF,
> upconverted RF - and 2 types for ADC - baseband RF and downconverted RF,
> both likely including switchable gain).  So now we are looking at making 3
> types of quad DAC boards, 2 types of ADC board, and probably 3 types of
> DAC/ADC board (upconvert DAC/downconvert ADC, baseband RF
> DAC/baseband RF ADC, and low frequency DAC/baseband RF ADC).  So now
> there are 8 different daughterboard designs.  If we restrict ourselves to just
> quad DAC or quad ADC on a given daughtercard, then there are 5 designs,
> same as in the current proposal for analog-only daughtercards.  I would still
> want to have boards be partially stuffed (or stuffed in different
> configurations on demand) to allow users to choose the frequencies of
> interest for analog filters etc.
> >
> > If we proceed this way, we will need an external clock SMA for each FMC
> module, because we don't want the high-quality external clock going down
> one FMC connector, across the AMC, and up the other FMC connector for
> signal integrity/crosstalk reasons.
> 
> For a digital clock with fast edges 60 dB of crosstalk is _much_ less of a
> problem.

No!  The clock coming in will be a sine wave from a low phase noise oscillator 
somewhere.  The DACs and ADCs will threshold this clock to determine their 
sample times.  Any amount of crosstalk will distort the clock signal (adding or 
subtracting to the voltage at a given time), thus skewing the time at which the 
threshold is reached and thus inducing jitter into the sampling times.  This 
would also hold true even if you have an LVPECL clock signal, because at 
frequencies like 2.4 GHz the rise and fall times (~100-200 ps) are similar to 
that of a sine wave.  Unlike for digital data signals, any amount of crosstalk 
will degrade the jitter and/or edge time performance for a clock signal.  

> > Are we thinking we would try to implement the actual VITA 57 standard on
> these connectors?  Or just use them as convenient high-speed-capable
> connectors?  I agree with the second idea, but I don't like the first one.
> 
> What from the VITA 57 pin assignmend do you not like?

If you comply with VITA 57, we will need to use an HPC connector to get enough 
gigabit transceivers into the connector, and we will have to populate all the 
other digital lines.  We could use an HPC connector with the VITA 57 LPC 
connections, plus adding on the gigabit transceivers in the locations where 
they would go for an HPC connector, and thus have an LPC compliant connector 
with "extra features" for the needed gigabit transceivers.  I am just trying to 
reduce unnecessary complexity in routing the AMC board to the FMC connectors, 
since HPC is much more of a pain than LPC in this regard.  
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Re: [ARTIQ] Fwd: FW: initial specification of the project

[Grzegorz Kasprowicz]

Actually, we can fit a lot to single FMC
Look here:
https://scontent-waw1-1.xx.fbcdn.net/hphotos-xpa1/v/t1.0-9/66620_1649317561668_2595483_n.jpg?oh=982ee50c1a1d8ecc444346c9eae1fe1c=578FA78C
I managed to place there 16 AFEs, 16x130MHz ADCs, 16 buffers, FPGA, SDRAM, quad 
DAC with amplifier, SMPS supply. The PCB has 4 layers.
Of course in case of RF stuff we need shielding, but we can fit there 2 JESD 
ADC/DACs, which have very simple interface and half of the FMC will be still 
available for 2 RF up or downconverters and fitlers.
Here is example that presents how much space is taken by the shielding/heat sink
http://www.ohwr.org/attachments/3303/250M_top.jpg

-Original Message-
From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Robert Jördens
Sent: Wednesday, March 30, 2016 10:08 PM
To: artiq@lists.m-labs.hk
Subject: [ARTIQ] Fwd: FW: initial specification of the project

On Wed, Mar 30, 2016 at 9:53 PM, Grzegorz Kasprowicz  
wrote:
> Maybe we should come back to the roots:) What if we use standard FMCs 
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would be 
> fed externally.
> In this way we leave general purpose AMC board and define its 
> functionality by FMC boards If we make 3 flavours of FMCs: ADC+ADC, 
> ADC+DAC,DAC+DAC, we would cover several use cases:
> Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with 
> external sield.
> Look at this shield (my project)
> http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> In this way we could use existing AFCK for quick tests

I was about to suggest that we consider doing that as well.

In the end the DAC/ADC can be on the mezzanine. It doesn't matter much in terms 
of cost. It makes shielding much easier and much more efficient, gets rid of 
all coax board-to-board connectors (which saves a lot of space again), allows 
testing on other carrier platforms, allows usage of other mezzanines. The only 
downside is that a standard FMC does not have much space. But maybe that's fine.

Robert.
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Re: [ARTIQ] FW: initial specification of the project

[Robert Jördens]

On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed)
 wrote:
> Now, as you suggest we could just change the level at which we make this 
> break from the AMC card, shift the DACs and ADCs onto the daughter card as 
> well, and use FMC to communicate with the whole thing.  This makes it a bit 
> more expensive/difficult to reconfigure the analog front end, but the DAC and 
> ADC costs are not so high that it is impossible to do.  I had envisioned the 
> notion of making the daughtercards simple enough that end users could 
> redesign/respin easily to accommodate their own applications, or we could 
> ship unstuffed or partially stuffed boards that they could complete with the 
> particular filters etc they desire.

It makes letting unused mezzanines collect dust on the shelf more expensive.

> However, I agree that there are compelling arguments for using the 
> architecture you propose.  We would need to pick just a few board styles (I 
> suggest quad DAC, 2 DAC/2 ADC, and quad ADC), and for each of these board 
> styles we would need to make several different variants with different analog 
> front ends (3 types for DAC - low frequency, baseband RF, upconverted RF - 
> and 2 types for ADC - baseband RF and downconverted RF, both likely including 
> switchable gain).  So now we are looking at making 3 types of quad DAC 
> boards, 2 types of ADC board, and probably 3 types of DAC/ADC board 
> (upconvert DAC/downconvert ADC, baseband RF DAC/baseband RF ADC, and low 
> frequency DAC/baseband RF ADC).  So now there are 8 different daughterboard 
> designs.  If we restrict ourselves to just quad DAC or quad ADC on a given 
> daughtercard, then there are 5 designs, same as in the current proposal for 
> analog-only daughtercards.  I would still want to have boards be partially 
> stuffed (or stuffed in different configurations on demand) to allow users to 
> choose the frequencies of interest for analog filters etc.
>
> If we proceed this way, we will need an external clock SMA for each FMC 
> module, because we don't want the high-quality external clock going down one 
> FMC connector, across the AMC, and up the other FMC connector for signal 
> integrity/crosstalk reasons.

For a digital clock with fast edges 60 dB of crosstalk is _much_ less
of a problem.

> Are we thinking we would try to implement the actual VITA 57 standard on 
> these connectors?  Or just use them as convenient high-speed-capable 
> connectors?  I agree with the second idea, but I don't like the first one.

What from the VITA 57 pin assignmend do you not like?

Robert.
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Re: [ARTIQ] Fwd: FW: initial specification of the project

[Robert Jördens]

On Wed, Mar 30, 2016 at 10:22 PM, Grzegorz Kasprowicz
 wrote:
> Actually, we can fit a lot to single FMC
> Look here:
> https://scontent-waw1-1.xx.fbcdn.net/hphotos-xpa1/v/t1.0-9/66620_1649317561668_2595483_n.jpg?oh=982ee50c1a1d8ecc444346c9eae1fe1c=578FA78C
> I managed to place there 16 AFEs, 16x130MHz ADCs, 16 buffers, FPGA, SDRAM, 
> quad DAC with amplifier, SMPS supply. The PCB has 4 layers.
> Of course in case of RF stuff we need shielding, but we can fit there 2 JESD 
> ADC/DACs, which have very simple interface and half of the FMC will be still 
> available for 2 RF up or downconverters and fitlers.
> Here is example that presents how much space is taken by the shielding/heat 
> sink
> http://www.ohwr.org/attachments/3303/250M_top.jpg

Impressive. Yep. Looks doable then. For us it would probably be either
just filtering and amplification on four channels, or upconversion (on
two iq channels then i would think).
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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

We could also use a fuzz button interposer, which would do the same kind of 
task (low stacking height connection w/ high frequency compatibility), but I 
think once we start heading too far down this road the cost and complexity of 
making a robust solution starts to outweigh the cost of just making more types 
of boards.  We should consider carefully before we make too fancy a solution.  
The notion of the SMP connectors is that they are robust, high performance, 
suited for the task, and cheap.

It does seem that microwave-frequency castellated solutions are used by serious 
industry folks:

https://www.markimicrowave.com/Assets/appnotes/Marki_Surface_mount_Guide_V1.pdf


From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 3:09 PM
To: Slichter, Daniel H. (Fed) 
Cc: Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) 
; Sébastien Bourdeauducq ; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Well, it depends on trace width matching. We can simulate and characterize it 
even at much higher frequencies.
If we place them really close to the DAC and match widths, remove grounds under 
pads, we can match it not worse than SMA connectors.
We can even do even more crazy thing - try to make them mountable.
The only signals that would need to be transmitted is DAC output / ADC input.
We can use low profile board to board connectors for rest of the signals - I 
know ones that have 1mm stacking hight. For RF we could use PCB mounted UFL 
connectors.
This is just crazy idea that need to be verified.

On 30 March 2016 at 23:02, Slichter, Daniel H. (Fed) 
> wrote:
This is an interesting potential solution although I am not sure how the signal 
integrity is at ~3 GHz, for example.

From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 2:44 PM
To: Slichter, Daniel H. (Fed) 
>
Cc: Grzegorz Kasprowicz 
>; Leibrandt, David R. 
(Fed) >; Sébastien 
Bourdeauducq >; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Such assembly technique is called:
castellated PCB module
https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB

On 30 March 2016 at 22:40, Grzegorz Kasprowicz 
> wrote:
One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6 ones, 
we won't be able to screw them.
But we can install MMCX ones for clocks and fit in total of 7 RF connectors,
Look here
http://www.ohwr.org/attachments/3390/fmc_top.jpg
Greg

On 30 March 2016 at 22:38, Grzegorz Kasprowicz 
> wrote:
Well, we can do another crazy thing - solder small module with RF stuff on the 
FMC board, under same shield.
In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the 
functionality by soldering (automatic or manual) of just RF modules. WE can 
even design such modules to hold the front-end connectors of leave them on the 
FMC.
Such approach has also some attractive feature - we can make them using small 
pieces of Rogers material which is hell expensive and it's hard to make small 
vias and thin traces needed for JESD signals.
these modules could look like that
http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
You can mount them by pick and place or manually.
IT is also possible to manually disassemble them.
This is a form factor of popular RF modules, i.e. wifi, GPS and LTE modems.
http://www.emcfastpass.com/rf-modules/
And is simply works
Greg


On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) 
> wrote:
> Maybe we should come back to the roots:) What if we use standard FMCs
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would
> be fed externally.
> In this way we leave general purpose AMC board and define its functionality
> by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> ADC+DAC,DAC+DAC, we would cover several use cases:
> Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> external sield.
> Look at this shield (my project)
> http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> In this way we could use existing AFCK for 

Re: [ARTIQ] FW: initial specification of the project

[Robert Jördens]

On Wed, Mar 30, 2016 at 5:57 PM, Slichter, Daniel H. (Fed)
 wrote:
>> > What are you thinking for number of daughter cards?  I suppose that
>> > more would give us more flexibility, but less would be more economical
>> > in terms of cost and layout area.  Perhaps two daughter cards would be
>> reasonable:
>> > one for all of the inputs and one for all of the outputs?
>>
>> Just one, the space on the AMC is rather limited.
>
> We should be able to do two side by side.  I think it would be nice to be 
> able to select the input daughtercard separately from the output 
> daughtercard.  This would require having two sets of pin headers for sending 
> power and digital signals, but I think the input daughtercards would likely 
> have much less in terms of digital control signal requirements; there would 
> be two basic designs, one for baseband digitization and one for 
> downconversion before digitization.  Both designs would just have analog 
> components, no digital attenuators/switches/etc would be necessary or desired.

To be useful as a digital servo platform the analog inputs need to
have quite a bit of configurability to them e.g. switchable gain.
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Re: [ARTIQ] Fwd: FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

> Impressive. Yep. Looks doable then. For us it would probably be either just
> filtering and amplification on four channels, or upconversion (on two iq
> channels then i would think).

Agreed, seems doable.  Filtering plus amplification should fit in a suitable 
footprint pretty easily.  Two channels of IQ upconversion would also probably 
be good, but most likely the upconverting mixer would need to have larger RF 
bandwidth than is typically available in surface mount IQ modules (which 
typically go to ~ 6 GHz spec'ed max, might be rough making it out to 12 GHz for 
Yb).  Since we have full IQ control in the digital regime, we could do 
everything we want with just a regular mixer as long as filters are put in 
place to get rid of the second sideband on the output (these could be placed 
off-card as well, for example).  The bandwidth of the DACs is sufficiently high 
that this method for removing the second sideband is viable, as long as 
appropriate filters are placed in the IF signal path.  Just another potential 
way of generating things.  
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Re: [ARTIQ] FW: initial specification of the project

[Sébastien Bourdeauducq]

On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote:
> Well, you don't have to write it.
> It is already available for RTOS and linux.

We are not using RTOS or Linux.

> But it's true - it occupies MIO bank and dedicated DDR port. But this is axi
> and can be easily accessible from PL part.
> How many IOs do you need?

IO count is not the problem. The problem is you cannot switch between designs 
that use the fabric to talk directly to Ethernet and SDRAM, and designs that 
use those questionable hardened blocks.

Sébastien

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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

One further question: is there a plan to make a “TTL” card or a multichannel 
“slow” DAC card (e.g. for trap voltages), using a Centronics or d-sub type 
connector?  These could both be more readily accomplished with their own FMC 
modules if we go with this architecture.

From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 3:36 PM
To: Slichter, Daniel H. (Fed) 
Cc: Robert Jördens ; Grzegorz Kasprowicz 
; Leibrandt, David R. (Fed) 
; Sébastien Bourdeauducq ; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Here is example of CERN carrier with analogue voltages:
http://www.ohwr.org/projects/fmc-pci-carrier/wiki
"+5V, -2V, -5V2 and -12V optionally wired on HPC pins"
look here
https://edms.cern.ch/ui/file/1098639/1/EDA-02118-V1-1_sch.pdf
page 3

On 30 March 2016 at 23:17, Slichter, Daniel H. (Fed) 
> wrote:
We definitely need +/- 15V for the low frequency (e.g. trap electrode) 
amplifiers.  Many low noise amplifiers and RF components run off +5V or +/- 5V 
and have substantial current draws, so if you pull everything from +/- 15V 
rails you are tripling your power dissipation and you end up with very hot 
regulators.  The DACs and ADCs will be dissipating a fair amount of power 
already so we want to try to keep the power budget under control.  Other than 
that, I don’t see major reasons why one couldn’t run fewer analog rails.  I 
think we are better off with DC/DC converters on the AMC card making a number 
of rails, which then have some filtering/regulation on the AMC card and then a 
final stage of LDO regulation on the FMC daughtercard itself, as close to the 
amplifiers etc as possible.

Using the alternating grounds a la CERN seems like a suitable solution to me 
for sending in these additional analog rails.

From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 3:13 PM
To: Slichter, Daniel H. (Fed) 
>
Cc: Robert Jördens >; Grzegorz Kasprowicz 
>; Leibrandt, David R. 
(Fed) >; Sébastien 
Bourdeauducq >; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Well, CERN does it in their FMC carriers. They use HPC routed like LPC and then 
some of grounds are used as symmetrical analog supplies. In this way if you 
plug wrong board, it will short the supply but no damage will occur.
I assume that low nosie DC/DC converters + LDOs will be installed on the AMC 
board.
Do we need all these voltages, especially +/-5 and +/- 15? Won't single +/- 8 
or +/- 15V be sufficient?
Greg

On 30 March 2016 at 23:08, Slichter, Daniel H. (Fed) 
> wrote:

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration
So you have 34 LVDS pairs and 8 GTP links.

If this works for you then I don’t have major objections.  The other issue to 
consider is power rails, since for the analog circuitry we will probably want 
+/- 5V, +/- 15V as well as +3.3V, +1.8V, +12V.  Can we put these through on the 
FMC without breaking back compatibility?  For example, one rail on each of the 
4 VADJ pins?  I am sure this would not be VITA 57 compliant….and we don’t want 
switching converters on the FMC daughtercard for space and noise reasons both.


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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

Looks like one could get a pretty good start on things by just copying the 
designs used by marki microwave:

http://www.markimicrowave.com/assets/packages/CTG.pdf
http://www.markimicrowave.com/assets/appnotes/an-ct-pcb.pdf

On another note, I would recommend the MM1-0320HSM mixer as a good option for 
the upconversion board if we decide not to go with an IQ modulator (there the 
ADL5375 would be best but I haven’t tested it to 12 GHz).

http://www.markimicrowave.com/MM1-0320HSM-MMIC-Double-Balanced-Mixer-P782.aspx


From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 3:09 PM
To: Slichter, Daniel H. (Fed) 
Cc: Grzegorz Kasprowicz ; Leibrandt, David R. (Fed) 
; Sébastien Bourdeauducq ; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Well, it depends on trace width matching. We can simulate and characterize it 
even at much higher frequencies.
If we place them really close to the DAC and match widths, remove grounds under 
pads, we can match it not worse than SMA connectors.
We can even do even more crazy thing - try to make them mountable.
The only signals that would need to be transmitted is DAC output / ADC input.
We can use low profile board to board connectors for rest of the signals - I 
know ones that have 1mm stacking hight. For RF we could use PCB mounted UFL 
connectors.
This is just crazy idea that need to be verified.

On 30 March 2016 at 23:02, Slichter, Daniel H. (Fed) 
> wrote:
This is an interesting potential solution although I am not sure how the signal 
integrity is at ~3 GHz, for example.

From: Grzegorz Kasprowicz [mailto:kaspr...@gmail.com]
Sent: Wednesday, March 30, 2016 2:44 PM
To: Slichter, Daniel H. (Fed) 
>
Cc: Grzegorz Kasprowicz 
>; Leibrandt, David R. 
(Fed) >; Sébastien 
Bourdeauducq >; 
artiq@lists.m-labs.hk
Subject: Re: [ARTIQ] FW: initial specification of the project

Such assembly technique is called:
castellated PCB module
https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB

On 30 March 2016 at 22:40, Grzegorz Kasprowicz 
> wrote:
One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6 ones, 
we won't be able to screw them.
But we can install MMCX ones for clocks and fit in total of 7 RF connectors,
Look here
http://www.ohwr.org/attachments/3390/fmc_top.jpg
Greg

On 30 March 2016 at 22:38, Grzegorz Kasprowicz 
> wrote:
Well, we can do another crazy thing - solder small module with RF stuff on the 
FMC board, under same shield.
In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the 
functionality by soldering (automatic or manual) of just RF modules. WE can 
even design such modules to hold the front-end connectors of leave them on the 
FMC.
Such approach has also some attractive feature - we can make them using small 
pieces of Rogers material which is hell expensive and it's hard to make small 
vias and thin traces needed for JESD signals.
these modules could look like that
http://www.emcfastpass.com/wp-content/uploads/2014/09/rf_module_holes.gif
You can mount them by pick and place or manually.
IT is also possible to manually disassemble them.
This is a form factor of popular RF modules, i.e. wifi, GPS and LTE modems.
http://www.emcfastpass.com/rf-modules/
And is simply works
Greg


On 30 March 2016 at 22:25, Slichter, Daniel H. (Fed) 
> wrote:
> Maybe we should come back to the roots:) What if we use standard FMCs
> (LPC) with DAC/ADC channels and RF stuff _on_ them.
> JESD204B and some pins would go to the FPGA while DAC and RF clock would
> be fed externally.
> In this way we leave general purpose AMC board and define its functionality
> by FMC boards If we make 3 flavours of FMCs: ADC+ADC,
> ADC+DAC,DAC+DAC, we would cover several use cases:
> Quad ADC, quad DAC, 1xADC 3xDAC, 3xADC 1xDAC.
> FMCs with only DAC and RF stuff on it can be simple, 4 layer boards with
> external sield.
> Look at this shield (my project)
> http://www.ohwr.org/projects/fmc-adc-130m-16b-4cha/wiki
> In this way we could use existing AFCK for quick tests

We have been working with the notion that should be many possible front ends 
for each of the DACs or ADCs, depending on what the particular application 

Re: [ARTIQ] FW: initial specification of the project

[Sébastien Bourdeauducq]

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote:
> [GK] If you don't use ARM, you still get hardened SDRAM controller and GBE
> MACs.

Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins 
like other IOs). So you need to use the Zynq-specific features of Vivado, 
interface your design to the hardened AXI system, use some obscure Vivado 
"wizard" to set up the SDRAM, and write a software driver for Xilinx's GbE 
MAC. All doable, but annoying.

> > * we want to avoid RTMs and instead put the DAC/ADCs on the AMC card
> > and have analog plug-ins using the FMC form factor (see my document).
> > **Are you sure you would get noise performance from such setup that
> > satisfies you?
> 
> Unless the FMC connector is particularly bad with analog signals, I think it
> should not be worse than the current hardware. [GK] All depends how you
> deliver the clock for such DAC. This is the weakest point of such solution.

The DACs will be mounted on the DSP cards (AMC directly), not the RF 
daughtercards. And the DSP cards will have an external clocking option, that 
may use semi-rigid coax if need be.

Sébastien

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Re: [ARTIQ] FW: initial specification of the project

[Leibrandt, David R. (Fed)]

I like this plan.  I think 4 + 4 channels will also make the front panel 
connector density more reasonable.  What are you thinking for number of 
daughter cards?  I suppose that more would give us more flexibility, but less 
would be more economical in terms of cost and layout area.  Perhaps two 
daughter cards would be reasonable: one for all of the inputs and one for all 
of the outputs?

Best,
Dave

-Original Message-
From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Sébastien 
Bourdeauducq
Sent: Wednesday, March 30, 2016 5:50 AM
To: Grzegorz Kasprowicz 
Cc: 'Grzegorz Kasprowicz' ; artiq@lists.m-labs.hk; 
Slichter, Daniel H. (Fed) 
Subject: Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> - they can be used immediately with existing OSHW carriers like AFC/AFCK. 

AFCK may be overkill. We are still working on evaluating the FPGA resource 
requirements.

> - it could be hard to fit FPGA, supply, DACs and several RF modules, 
> all on single dual width AMC, especially when shielding is required. 
> RTM relaxes these constraints
> - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF 
> modules. In case of single AMC board it would be hard to achieve such 
> channels density.

How about this:
* we reduce the number of channels per AMC to 4 DACs + 4 ADCs
* we can therefore use a smaller FPGA. Communication lanes to the master board 
are relatively cheap if we put them on IOSERDES.
* the power density and cooling requirements are also reduced.
* for the RF daughter cards, we use a custom form factor that can use at least
2/3 of the AMC front panel
* connectors between the DSP card and the RF daughter card are 2mm header and 
8x SMP
* the rest of the AMC front panel used for (optional, runtime selectable) clock 
input and some TTLs.

Sébastien

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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

> I like this plan.  I think 4 + 4 channels will also make the front panel 
> connector
> density more reasonable.  What are you thinking for number of daughter
> cards?  I suppose that more would give us more flexibility, but less would be
> more economical in terms of cost and layout area.  Perhaps two daughter
> cards would be reasonable: one for all of the inputs and one for all of the
> outputs?

Agreed that ~ 8 front panel SMA connections, plus one clock SMA connection, is 
about what one can tolerate in a reasonable way in terms of physical footprint. 
 If we split this as 4 DAC + 4 ADC, it makes a nice symmetry although my 
suspicion is that most applications would prefer something more asymmetric with 
a few more DAC channels than ADC channels (6 DAC/2 ADC or 6 DAC/4 ADC, for 
example). One could go a simple as 4 DAC/2 ADC and make the space requirements 
even simpler to fulfill on the cards.  All of these modifications will increase 
the price per channel, even though we may be able to save on FPGA costs.  For 
example, if we do 4 DAC/2 ADC on a card with 1x AD9154 and 1x ADC16DX370 (our 
currently planned parts), we only need 10 GTX transceivers on the FPGA.  With 4 
DAC/4 ADC, this would be 12 GTX transceivers.  With these numbers we could look 
at the ZU5EV Zynq Ultrascale, instead of the ZU9EG, which we had been 
discussing.

To Greg's question on the RTM, we have had a number of extensive internal 
discussions about pros and cons of RTM and it seems that we don't want to 
pursue this avenue for a number of carefully considered reasons.  Let's just 
take it as a given that we will need to put everything on the AMC card or its 
analog daughtercards.  As stated, the DAC and ADC chips themselves will be on 
the AMC card, not the analog daughtercards.  

I am in favor of separate analog daughtercards for the inputs and the outputs, 
this seems sensible.  


> On Tuesday, 29 March 2016 11:55:19 PM HKT Grzegorz Kasprowicz wrote:
> > - they can be used immediately with existing OSHW carriers like AFC/AFCK.
> 
> AFCK may be overkill. We are still working on evaluating the FPGA resource
> requirements.
> 
> > - it could be hard to fit FPGA, supply, DACs and several RF modules,
> > all on single dual width AMC, especially when shielding is required.
> > RTM relaxes these constraints
> > - on AMC+RTM you can place 8 ADC channels + 8 DAC channels + 8 RF
> > modules. In case of single AMC board it would be hard to achieve such
> > channels density.
> 
> How about this:
> * we reduce the number of channels per AMC to 4 DACs + 4 ADCs
> * we can therefore use a smaller FPGA. Communication lanes to the master
> board are relatively cheap if we put them on IOSERDES.
> * the power density and cooling requirements are also reduced.
> * for the RF daughter cards, we use a custom form factor that can use at least
> 2/3 of the AMC front panel
> * connectors between the DSP card and the RF daughter card are 2mm
> header and 8x SMP
> * the rest of the AMC front panel used for (optional, runtime selectable)
> clock input and some TTLs.


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Re: [ARTIQ] FW: initial specification of the project

[Slichter, Daniel H. (Fed)]

> > What are you thinking for number of daughter cards?  I suppose that
> > more would give us more flexibility, but less would be more economical
> > in terms of cost and layout area.  Perhaps two daughter cards would be
> reasonable:
> > one for all of the inputs and one for all of the outputs?
> 
> Just one, the space on the AMC is rather limited.

We should be able to do two side by side.  I think it would be nice to be able 
to select the input daughtercard separately from the output daughtercard.  This 
would require having two sets of pin headers for sending power and digital 
signals, but I think the input daughtercards would likely have much less in 
terms of digital control signal requirements; there would be two basic designs, 
one for baseband digitization and one for downconversion before digitization.  
Both designs would just have analog components, no digital 
attenuators/switches/etc would be necessary or desired.  

This would especially hold true if we go to a 4 DAC / 2 ADC design, but a 4/4 
design should work fine too.
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