from:"Amy Kwan via Phabricator via cfe\-commits"

[PATCH] D155544: [AIX][TLS][clang] Add -maix-small-local-exec-tls clang option.

2023-09-07 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb1922e55ab3b: [AIX][TLS][clang] Add 
-maix-small-local-exec-tls clang option. (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D155544?vs=543818=556219#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155544/new/

https://reviews.llvm.org/D155544

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/aix-small-local-exec-tls.c

Index: clang/test/Driver/aix-small-local-exec-tls.c
===
--- /dev/null
+++ clang/test/Driver/aix-small-local-exec-tls.c
@@ -0,0 +1,30 @@
+// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
+
+// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S -emit-llvm \
+// RUN:%s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
+
+// RUN: not %clang -target powerpc-unknown-aix -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-AIX32 %s
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-LINUX %s
+// RUN: not %clang -target powerpc64-unknown-linux-gnu -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-LINUX %s
+
+int test(void) {
+  return 0;
+}
+
+// CHECK: test() #0 {
+// CHECK: attributes #0 = {
+// CHECK-SAME: -aix-small-local-exec-tls
+
+// CHECK-UNSUPPORTED-AIX32: option '-maix-small-local-exec-tls' cannot be specified on this target
+// CHECK-UNSUPPORTED-LINUX: option '-maix-small-local-exec-tls' cannot be specified on this target
+
+// CHECK-AIX_SMALL_LOCALEXEC_TLS: test() #0 {
+// CHECK-AIX_SMALL_LOCALEXEC_TLS: attributes #0 = {
+// CHECK-AIX_SMALL_LOCALEXEC_TLS-SAME: +aix-small-local-exec-tls
+
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -60,6 +60,7 @@
   bool HasMMA = false;
   bool HasROPProtect = false;
   bool HasPrivileged = false;
+  bool HasAIXSmallLocalExecTLS = false;
   bool HasVSX = false;
   bool UseCRBits = false;
   bool HasP8Vector = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -77,6 +77,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+aix-small-local-exec-tls") {
+  HasAIXSmallLocalExecTLS = true;
 } else if (Feature == "+isa-v206-instructions") {
   IsISA2_06 = true;
 } else if (Feature == "+isa-v207-instructions") {
@@ -541,6 +543,10 @@
   // Privileged instructions are off by default.
   Features["privileged"] = false;
 
+  // The code generated by the -maix-small-local-exec-tls option is turned
+  // off by default.
+  Features["aix-small-local-exec-tls"] = false;
+
   Features["spe"] = llvm::StringSwitch(CPU)
 .Case("8548", true)
 .Case("e500", true)
@@ -635,6 +641,14 @@
 return false;
   }
 
+  if (llvm::is_contained(FeaturesVec, "+aix-small-local-exec-tls")) {
+if (!getTriple().isOSAIX() || !getTriple().isArch64Bit()) {
+  Diags.Report(diag::err_opt_not_valid_on_target)
+ << "-maix-small-local-exec-tls";
+  return false;
+}
+  }
+
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
@@ -676,6 +690,7 @@
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("aix-small-local-exec-tls", HasAIXSmallLocalExecTLS)
   .Case("isa-v206-instructions", IsISA2_06)
   .Case("isa-v207-instructions", IsISA2_07)
   .Case("isa-v30-instructions", IsISA3_0)
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -4723,6 +4723,12 @@
 def mprivileged : Flag<["-"], "mprivileged">,
 Group;
 } // let Flags = [TargetSpecific]
+def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">,
+  Group,
+  HelpText<"Produce a faster access sequence for local-exec TLS variables "
+   "where the offset from the TLS base is encoded as an "
+

[PATCH] D155544: [AIX][TLS][clang] Add -maix-small-local-exec-tls clang option.

2023-07-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 543818.
amyk marked 5 inline comments as done.
amyk added a comment.

Address review comments from Hubert and update this patch to be only the clang 
portion of the option.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155544/new/

https://reviews.llvm.org/D155544

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/aix-small-local-exec-tls.c
  clang/test/OpenMP/target_data_map_codegen_hold.cpp

Index: clang/test/OpenMP/target_data_map_codegen_hold.cpp
===
--- clang/test/OpenMP/target_data_map_codegen_hold.cpp
+++ clang/test/OpenMP/target_data_map_codegen_hold.cpp
@@ -517,7 +517,7 @@
 
 #endif
 //.
-// CHECK-PPC64LE: attributes #[[ATTR0:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
+// CHECK-PPC64LE: attributes #[[ATTR0:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-aix-small-local-exec-tls,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
 // CHECK-PPC64LE: attributes #[[ATTR1:[0-9]+]] = { nounwind }
 // CHECK-PPC64LE: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
 //.
Index: clang/test/Driver/aix-small-local-exec-tls.c
===
--- /dev/null
+++ clang/test/Driver/aix-small-local-exec-tls.c
@@ -0,0 +1,30 @@
+// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s
+
+// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S -emit-llvm \
+// RUN:%s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
+
+// RUN: not %clang -target powerpc-unknown-aix -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-AIX32 %s
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-LINUX %s
+// RUN: not %clang -target powerpc64-unknown-linux-gnu -maix-small-local-exec-tls \
+// RUN:-fsyntax-only %s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-LINUX %s
+
+int test(void) {
+  return 0;
+}
+
+// CHECK: test() #0 {
+// CHECK: attributes #0 = {
+// CHECK-SAME: -aix-small-local-exec-tls
+
+// CHECK-UNSUPPORTED-AIX32: option '-maix-small-local-exec-tls' cannot be specified on this target
+// CHECK-UNSUPPORTED-LINUX: option '-maix-small-local-exec-tls' cannot be specified on this target
+
+// CHECK-AIX_SMALL_LOCALEXEC_TLS: test() #0 {
+// CHECK-AIX_SMALL_LOCALEXEC_TLS: attributes #0 = {
+// CHECK-AIX_SMALL_LOCALEXEC_TLS-SAME: +aix-small-local-exec-tls
+
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -60,6 +60,7 @@
   bool HasMMA = false;
   bool HasROPProtect = false;
   bool HasPrivileged = false;
+  bool HasAIXSmallLocalExecTLS = false;
   bool HasVSX = false;
   bool UseCRBits = false;
   bool HasP8Vector = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -77,6 +77,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+aix-small-local-exec-tls") {
+  HasAIXSmallLocalExecTLS = true;
 } else if (Feature == "+isa-v206-instructions") {
   IsISA2_06 = true;
 } else if (Feature == "+isa-v207-instructions") {
@@ -541,6 +543,10 @@
   // Privileged instructions are off by default.
   Features["privileged"] = false;
 
+  // The code generated by the -maix-small-local-exec-tls option is turned
+  // off by default.
+  Features["aix-small-local-exec-tls"] = false;
+
   Features["spe"] = llvm::StringSwitch(CPU)
 .Case("8548", true)
 .Case("e500", true)
@@ -635,6 +641,14 @@
 return false;
   }
 
+  if (llvm::is_contained(FeaturesVec,

[PATCH] D155544: [AIX][TLS] Add -maix-small-local-exec-tls option.

2023-07-21 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D155544#4523536 , 
@hubert.reinterpretcast wrote:

> Patch should not land before back-end patch. I also suggest having the patch 
> incorporate the new option into the Clang release notes before it lands.

I'm currently addressing reviews for the back-end patch but just wanted to 
clarify because I might be misunderstanding something.

Wouldn't this patch need to land before the back-end patch, because I introduce 
the option here, and then I use it in the backend patch?
In terms of checking for a 32-bit diagnostic within 
`check-aix-small-local-exec-tls-opt.ll`, the RUN lines in that test currently 
are 64-bit RUN lines. Perhaps in the backend patch, I should just add the 
32-bit lines to show the diagnostic?

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  rG LLVM Github Monorepo

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[PATCH] D155544: [AIX][TLS] Add -maix-small-local-exec-tls option.

2023-07-17 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, stefanp, kamaub, nemanjai, 
hubert.reinterpretcast.
amyk added a project: LLVM.
Herald added subscribers: kbarton, hiraditya.
Herald added a project: All.
amyk requested review of this revision.
Herald added a project: clang.
Herald added subscribers: llvm-commits, cfe-commits.

This patch adds an AIX-specific option to inform the compiler that it can use
a faster access sequence for the local-exec TLS model (formally named
`aix-small-local-exec-tls`).

This patch only adds the option, and the backend implementation for this option
will be added in a follow up patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155544

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/aix-small-local-exec-tls.c
  clang/test/OpenMP/target_data_map_codegen_hold.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/test/CodeGen/PowerPC/check-aix-small-local-exec-tls-opt.ll

Index: llvm/test/CodeGen/PowerPC/check-aix-small-local-exec-tls-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/check-aix-small-local-exec-tls-opt.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mattr=+aix-small-local-exec-tls \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: not llc -mtriple powerpc64le-unknown-linux-gnu -mattr=+aix-small-local-exec-tls \
+; RUN:   -ppc-asm-full-reg-names < %s 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-NOT-SUPPORTED
+
+define dso_local signext i32 @f() {
+entry:
+  ret i32 0
+}
+
+; Check that the -maix-small-local-exec-tls option is not supported on Linux.
+; CHECK-NOT-SUPPORTED: The aix-small-local-exec-tls attribute is only supported on AIX.
+
+; Make sure that the test was actually compiled successfully after using the
+; -maix-small-local-exec-tls option.
+; CHECK:li r3, 0
+; CHECK-NEXT:   blr
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -123,6 +123,11 @@
 
   // Determine endianness.
   IsLittleEndian = TM.isLittleEndian();
+
+  if ((!TargetTriple.isOSAIX()) && HasAIXSmallLocalExecTLS)
+report_fatal_error(
+  "The aix-small-local-exec-tls attribute is only supported on AIX.\n",
+  false);
 }
 
 bool PPCSubtarget::enableMachineScheduler() const { return true; }
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -318,6 +318,14 @@
   SubtargetFeature<"privileged", "HasPrivileged", "true",
"Add privileged instructions">;
 
+def FeatureAIXLocalExecTLS :
+  SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true",
+   "Produce a faster access sequence for local-exec TLS "
+   "variables where the offset from the thread pointer value "
+   "is encoded as an immediate operand (AIX 64-bit only). "
+   "This access sequence is not used for variables larger "
+   "than 32KB.">;
+
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
"PredictableSelectIsExpensive",
Index: clang/test/OpenMP/target_data_map_codegen_hold.cpp
===
--- clang/test/OpenMP/target_data_map_codegen_hold.cpp
+++ clang/test/OpenMP/target_data_map_codegen_hold.cpp
@@ -517,7 +517,7 @@
 
 #endif
 //.
-// CHECK-PPC64LE: attributes #[[ATTR0:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
+// CHECK-PPC64LE: attributes #[[ATTR0:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-aix-small-local-exec-tls,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-spe,-vsx" }
 // CHECK-PPC64LE: attributes #[[ATTR1:[0-9]+]] = { nounwind }
 // CHECK-PPC64LE: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
 //.
Index: clang/test/Driver/aix-small-local-exec-tls.c
===
--- /dev/null
+++ clang/test/Driver/aix-small-local-exec-tls.c
@@ -0,0 +1,29 @@
+// RUN: %clang -target powerpc64-unknown-aix -S

[PATCH] D149596: [AIX][TLS] Relax front end diagnostics to accept the local-exec TLS model

2023-06-19 Thread Amy Kwan via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG706b5472d897: [AIX][TLS] Relax front end diagnostics to 
accept the local-exec TLS model (authored by amyk).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149596/new/

https://reviews.llvm.org/D149596

Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/PowerPC/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c


Index: clang/test/Sema/aix-attr-tls_model.c
===
--- clang/test/Sema/aix-attr-tls_model.c
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -8,4 +8,4 @@
 static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
 static __thread int y __attribute((tls_model("local-dynamic"))); // 
expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
 static __thread int y __attribute((tls_model("initial-exec"))); // 
expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
-static __thread int y __attribute((tls_model("local-exec"))); // 
expected-error {{TLS model 'local-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("local-exec"))); // no-warning
Index: clang/test/CodeGen/PowerPC/aix-tls-model.cpp
===
--- clang/test/CodeGen/PowerPC/aix-tls-model.cpp
+++ clang/test/CodeGen/PowerPC/aix-tls-model.cpp
@@ -2,12 +2,12 @@
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 
 int z1 = 0;
 int z2;
@@ -23,4 +23,7 @@
 // CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
 // CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on 
AIX
 // CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
-// CHECK-LE-ERROR:  error: TLS model 'local-exec' is not yet supported on AIX
+// CHECK-LE: @z1 ={{.*}} global i32 0
+// CHECK-LE: @z2 ={{.*}} global i32 0
+// CHECK-LE: @x ={{.*}} thread_local(localexec) global i32 0
+// CHECK-LE: @_ZZ1fvE1y = internal thread_local(localexec) global i32 0
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -2039,7 +2039,7 @@
   }
 
   if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
-  Model != "global-dynamic") {
+  Model != "global-dynamic" && Model != "local-exec") {
 S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
 return;
   }
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1894,7 +1894,7 @@
   if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
 if (T.isOSAIX()) {
   StringRef Name = A->getValue();
-  if (Name != "global-dynamic")
+  if (Name != "global-dynamic" && Name != "local-exec")
 Diags.Report(diag::err_aix_unsupported_tls_model) << Name;
 }
   }


Index: clang/test/Sema/aix-attr-tls_model.c
===
--- clang/test/Sema/aix-attr-tls_model.c
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -8,4 +8,4 @@
 static __thread int y

[PATCH] D150520: [clang] Convert a few tests to opaque pointers

2023-05-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D150520#4342943 , @barannikov88 
wrote:

> In D150520#4342429 , @amyk wrote:
>
>> Hi, I just wanted to give a heads up that it appears that this patch is 
>> causing failures on some of the PPC buildbots.
>> In particular, the `const-str-array-decay.cl` appears to be failing. The 
>> failing build can be seen in: 
>> https://lab.llvm.org/buildbot/#/builders/36/builds/33110
>
> Should be fixed by 
> https://reviews.llvm.org/rGcc7dc90481d93734a56098470879189cb2e2c127

Thanks for the quick fix!


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[PATCH] D150520: [clang] Convert a few tests to opaque pointers

2023-05-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Hi, I just wanted to give a heads up that it appears that this patch is causing 
failures on some of the PPC buildbots.
In particular, the `const-str-array-decay.cl` appears to be failing. The 
failing build can be seen in: 
https://lab.llvm.org/buildbot/#/builders/36/builds/33110


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[PATCH] D149596: [AIX][TLS] Relax front end diagnostics to accept the local-exec TLS model

2023-05-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, stefanp, kamaub, nemanjai.
amyk added projects: LLVM, PowerPC, clang.
Herald added a reviewer: aaron.ballman.
Herald added a project: All.
amyk requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch relaxes the front end AIX diagnostics added in D102070 
 to accept the
local-exec TLS model, as we plan to support this model in a series of future 
patches.

The diagnostics are relaxed when `local-exec` is used as a compiler option to 
`-ftls-model=*`
and in the `__attribute__((tls_model("local-exec")))` attribute.


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Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/PowerPC/aix-tls-model.cpp
  clang/test/Sema/aix-attr-tls_model.c


Index: clang/test/Sema/aix-attr-tls_model.c
===
--- clang/test/Sema/aix-attr-tls_model.c
+++ clang/test/Sema/aix-attr-tls_model.c
@@ -8,4 +8,4 @@
 static __thread int y __attribute((tls_model("global-dynamic"))); // no-warning
 static __thread int y __attribute((tls_model("local-dynamic"))); // 
expected-error {{TLS model 'local-dynamic' is not yet supported on AIX}}
 static __thread int y __attribute((tls_model("initial-exec"))); // 
expected-error {{TLS model 'initial-exec' is not yet supported on AIX}}
-static __thread int y __attribute((tls_model("local-exec"))); // 
expected-error {{TLS model 'local-exec' is not yet supported on AIX}}
+static __thread int y __attribute((tls_model("local-exec"))); // no-warning
Index: clang/test/CodeGen/PowerPC/aix-tls-model.cpp
===
--- clang/test/CodeGen/PowerPC/aix-tls-model.cpp
+++ clang/test/CodeGen/PowerPC/aix-tls-model.cpp
@@ -2,12 +2,12 @@
 // RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
 // RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=global-dynamic -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-GD
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-dynamic -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LD-ERROR
 // RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=initial-exec -emit-llvm  2>&1 | FileCheck %s 
-check-prefix=CHECK-IE-ERROR
-// RUN: not %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm 2>&1 | FileCheck %s 
-check-prefix=CHECK-LE-ERROR
+// RUN: %clang_cc1 %s -triple powerpc64-unknown-aix -target-cpu pwr8 
-ftls-model=local-exec -emit-llvm -o - | FileCheck %s -check-prefix=CHECK-LE
 
 int z1 = 0;
 int z2;
@@ -23,4 +23,7 @@
 // CHECK-GD: @_ZZ1fvE1y = internal thread_local global i32 0
 // CHECK-LD-ERROR:  error: TLS model 'local-dynamic' is not yet supported on 
AIX
 // CHECK-IE-ERROR:  error: TLS model 'initial-exec' is not yet supported on AIX
-// CHECK-LE-ERROR:  error: TLS model 'local-exec' is not yet supported on AIX
+// CHECK-LE: @z1 ={{.*}} global i32 0
+// CHECK-LE: @z2 ={{.*}} global i32 0
+// CHECK-LE: @x ={{.*}} thread_local(localexec) global i32 0
+// CHECK-LE: @_ZZ1fvE1y = internal thread_local(localexec) global i32 0
Index: clang/lib/Sema/SemaDeclAttr.cpp
===
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -2033,7 +2033,7 @@
   }
 
   if (S.Context.getTargetInfo().getTriple().isOSAIX() &&
-  Model != "global-dynamic") {
+  Model != "global-dynamic" && Model != "local-exec") {
 S.Diag(LiteralLoc, diag::err_aix_attr_unsupported_tls_model) << Model;
 return;
   }
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1891,7 +1891,7 @@
   if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
 if (T.isOSAIX()) {
   StringRef Name = A->getValue();
-  if (Name != "global-dynamic")

[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

2023-03-31 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Overall looks OK to me, as well. I just had two questions that I wanted to ask.




Comment at: clang/include/clang/Basic/BuiltinsPPC.def:444
+TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector")
+TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "altivec")
+

Does this need to be `vsx`?



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:820
+TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector")
+TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "vsx")
 

Should this be `power10-vector`?


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[PATCH] D144967: [PowerPC] Recognize long CPU name for -mtune in Clang

2023-03-03 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D144967#4164858 , @nathanchance 
wrote:

> Could this be merged into `main` and backported to `release/16.x`? If this 
> makes 16.0.0 final, I think the kernel can avoid working around this issue 
> altogether, as `-mtune` was only wired up to do something on PowerPC in 
> during the 16 development cycle; in prior versions, it was ignored so any 
> value was accepted.

@nathanchance Just wanted to let you know that this patch is now backported 
into `release/16.x`.


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[PATCH] D144293: [PowerPC] Fix the implicit casting for the emulated intrinsics

2023-02-21 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/lib/Headers/ppc_wrappers/emmintrin.h:57
 typedef __vector unsigned char __v16qu;
+typedef __vector float __v2f;
 

nemanjai wrote:
> The name `__v2f` seems strange since `__vector float` is a vector of 4 
> `float` values. Should this be `__v4f`?
nit: Could we also put this to where we put the `double`?



Comment at: clang/lib/Headers/ppc_wrappers/smmintrin.h:310
   __charmask = vec_gb(__charmask);
-  __v8hu __shortmask = (__v8hu)vec_unpackh(__charmask);
+  __v8hu __shortmask = (__v8hu)vec_unpackh((__v16qi)__charmask);
 #ifdef __BIG_ENDIAN__

Potentially silly question, but is it intentionally for that mask for be signed?


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[PATCH] D143210: PowerPC] Include vector bool and pixel when emitting lax warning

2023-02-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/lib/Sema/SemaExpr.cpp:9845
 if (anyAltivecTypes(RHSType, LHSType) &&
-!areSameVectorElemTypes(RHSType, LHSType))
+!Context.areCompatibleVectorTypes(RHSType, LHSType))
   Diag(RHS.get()->getExprLoc(), diag::warn_deprecated_lax_vec_conv_all)

Might be a silly question, but what does it mean to be a "compatible" vector 
type?



Comment at: clang/test/CodeGen/SystemZ/zvector.c:1
-// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 -fzvector 
-emit-llvm -o - -W -Wall -Werror %s | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 -fzvector 
-emit-llvm -o - -W -Wall -Werror -Wno-error=deprecate-lax-vec-conv-all \
+// RUN: %s | opt -S -passes=mem2reg | FileCheck %s

Nit: I think this line is still over 80 characters.


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[PATCH] D138675: [flang] Add -ffast-math and -Ofast

2022-12-14 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D138675#3995282 , @probinson wrote:

> See D139967  for why `UNSUPPORTED: powerpc` 
> didn't work. That patch will put it back, and also update the lit config so 
> the check will work now.

Thank you for following up with this. I appreciate it!


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[PATCH] D138675: [flang] Add -ffast-math and -Ofast

2022-12-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D138675#3989997 , @tblah wrote:

> In D138675#3989826 , @amyk wrote:
>
>> Thanks for the follow up patch! I tested the patch locally and also saw the 
>> buildbot results, and it doesn't appear like the follow up patch marked 
>> `powerpc` as unsupported as the error still persists 
>> (https://lab.llvm.org/buildbot/#/builders/21/builds/57850). 
>> I was playing around with the test case locally and what appears to work is 
>> doing something like:
>>
>>   ! UNSUPPORTED: powerpc-registered-target
>
> Thanks 
> https://github.com/llvm/llvm-project/commit/9d86f2dc4f1d2e4e1a991be82384bbdb310f0618

Thanks for following up! The bot is now green 
(https://lab.llvm.org/buildbot/#/builders/21/builds/57857).


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[PATCH] D138675: [flang] Add -ffast-math and -Ofast

2022-12-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D138675#3989634 , @tblah wrote:

> In D138675#3989403 , @amyk wrote:
>
>> Hi,
>>
>> The ppc64le-flang-rhel-clang  
>> bot is also experiencing some failures with the `Driver/fast_math.f90` test 
>> case. In particular, `crtfastmath.o` is not found at all for `CHECK-CRT` as 
>> we can see in the failure details 
>> .
>>
>>   llvm-project/flang/test/Driver/fast_math.f90:64:19: error: CHECK-CRT-SAME: 
>> expected string not found in input
>>   ! CHECK-CRT-SAME: crtfastmath.o
>>
>> The output for the `CHECK-CRT` line on the bot looks like the following:
>>
>>   
>> "/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/bin/flang-new"
>>  "-fc1" "-triple" "powerpc64le-unknown-linux-gnu" "-emit-obj" 
>> "-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" "-ffast-math" 
>> "-target-cpu" "ppc64le" "-o" "/tmp/lit-tmp-x_okwzug/fast_math-e9ab49.o" "-x" 
>> "f95-cpp-input" 
>> "/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/llvm-project/flang/test/Driver/fast_math.f90"
>>  
>>   
>>   "/usr/bin/ld" "-pie" "--hash-style=gnu" "--eh-frame-hdr" "-m" "elf64lppc" 
>> "-dynamic-linker" "/lib64/ld64.so.2" "-o" 
>> "/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/tools/flang/test/Driver/Output/fast_math.f90.tmp"
>>  "/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/Scrt1.o" 
>> "/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/crti.o" 
>> "/usr/lib/gcc/ppc64le-redhat-linux/8/crtbeginS.o" 
>> "-L/usr/lib/gcc/ppc64le-redhat-linux/8" 
>> "-L/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64" "-L/lib/../lib64" 
>> "-L/usr/lib/../lib64" "-L/lib" "-L/usr/lib" 
>> "/tmp/lit-tmp-x_okwzug/fast_math-e9ab49.o" "-lFortran_main" 
>> "-lFortranRuntime" "-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" 
>> "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
>> "/usr/lib/gcc/ppc64le-redhat-linux/8/crtendS.o" 
>> "/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/crtn.o"   
>>  
>>
>> Would it be possible to follow up with a fix for this test case?
>
> Thanks for letting me know. I thought I had already disabled that test on 
> powerpc (in 
> https://github.com/llvm/llvm-project/commit/20cd3153f3775fcdc1eeeb54062849eead51e24a)
>  but apparently it didn't work. I don't have a powerpc system available to 
> test this. I have pushed a second attempt at 
> https://github.com/llvm/llvm-project/commit/6442b4da4e7018e8f264965768b9e4fdee393c8f.
>  Please let me know if that works.

Thanks for the follow up patch! I tested the patch locally and also saw the 
buildbot results, and it doesn't appear like the follow up patch marked 
`powerpc` as unsupported as the error still persists 
(https://lab.llvm.org/buildbot/#/builders/21/builds/57850). 
I was playing around with the test case locally and what appears to work is 
doing something like:

  ! UNSUPPORTED: powerpc-registered-target


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[PATCH] D138675: [flang] Add -ffast-math and -Ofast

2022-12-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Hi,

The ppc64le-flang-rhel-clang  bot 
is also experiencing some failures with the `Driver/fast_math.f90` test case. 
In particular, `crtfastmath.o` is not found at all for `CHECK-CRT` as we can 
see in the failure details 
.

  llvm-project/flang/test/Driver/fast_math.f90:64:19: error: CHECK-CRT-SAME: 
expected string not found in input
  ! CHECK-CRT-SAME: crtfastmath.o

The output for the `CHECK-CRT` line on the bot looks like the following:

  
"/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/bin/flang-new"
 "-fc1" "-triple" "powerpc64le-unknown-linux-gnu" "-emit-obj" 
"-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" "-ffast-math" 
"-target-cpu" "ppc64le" "-o" "/tmp/lit-tmp-x_okwzug/fast_math-e9ab49.o" "-x" 
"f95-cpp-input" 
"/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/llvm-project/flang/test/Driver/fast_math.f90"
 
  
  "/usr/bin/ld" "-pie" "--hash-style=gnu" "--eh-frame-hdr" "-m" "elf64lppc" 
"-dynamic-linker" "/lib64/ld64.so.2" "-o" 
"/home/buildbots/ppc64le-flang-rhel-test/ppc64le-flang-rhel-clang-build/build/tools/flang/test/Driver/Output/fast_math.f90.tmp"
 "/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/Scrt1.o" 
"/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/crti.o" 
"/usr/lib/gcc/ppc64le-redhat-linux/8/crtbeginS.o" 
"-L/usr/lib/gcc/ppc64le-redhat-linux/8" 
"-L/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64" "-L/lib/../lib64" 
"-L/usr/lib/../lib64" "-L/lib" "-L/usr/lib" 
"/tmp/lit-tmp-x_okwzug/fast_math-e9ab49.o" "-lFortran_main" "-lFortranRuntime" 
"-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" 
"-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
"/usr/lib/gcc/ppc64le-redhat-linux/8/crtendS.o" 
"/usr/lib/gcc/ppc64le-redhat-linux/8/../../../../lib64/crtn.o"  
  

Would it be possible to follow up with a fix for this test case?


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[PATCH] D139720: [clang][PPC] Checking Unknown Values Passed to -mcpu

2022-12-09 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

It might be good to add a test case to illustrate the 'unknown target CPU' 
error that is issued as a result of this patch.


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[PATCH] D135834: [PowerPC] Fix parameters for __builtin_crypto_vsbox

2022-10-14 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D135300: [PowerPC] Fix types for vcipher builtins.

2022-10-06 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D131622: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c

2022-08-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.
This revision is now accepted and ready to land.

I think this LGTM.


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[PATCH] D126291: [flang][Driver] Update link job on windows

2022-08-05 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Hi, 
I have come across a failure involving `flang/test/Driver/linker-flags.f90` 
that occurs when the default linker is lld. I have opened an external issue for 
it here: https://github.com/llvm/llvm-project/issues/56955


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[PATCH] D130224: [Clang][Attribute] Introduce maybe_undef attribute for function arguments which accepts undef values

2022-07-29 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D130224#3688034 , @skc7 wrote:

> In D130224#3687907 , @aaron.ballman 
> wrote:
>
>> In D130224#3687860 , @amyk wrote:
>>
>>> In D130224#3687487 , 
>>> @mubarizafzal wrote:
>>>
 Hi, the test cases that this patch introduces are failing on some ppc64le 
 (Linux on Power) buildbots:
 https://lab.llvm.org/buildbot/#/builders/57
 https://lab.llvm.org/buildbot/#/builders/230

 Would you mind taking a look please?
>>>
>>> Thanks for pinging this patch. It appears it's affecting both little endian 
>>> PPC:
>>> https://lab.llvm.org/buildbot/#/builders/230/builds/1079
>>> https://lab.llvm.org/buildbot/#/builders/121/builds/21978
>>> https://lab.llvm.org/buildbot/#/builders/57/builds/20484
>>> https://lab.llvm.org/buildbot/#/builders/36/builds/23702
>>>
>>> And big endian PPC bots:
>>> https://lab.llvm.org/buildbot/#/builders/231/builds/842
>>> https://lab.llvm.org/buildbot/#/builders/93/builds/10270
>>
>> If we don't hear from @skc7 in the next ~hour with a fix, feel free to 
>> revert to get the bots back to green.
>
> Issue is with missing target triple in the tests. Submitted D130790 
>  for review, which should fix the tests.

I realized I didn't happen to see this comment in time and had already reverted 
the patch. My apologies on this.


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[PATCH] D130224: [Clang][Attribute] Introduce maybe_undef attribute for function arguments which accepts undef values

2022-07-29 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D130224#3687907 , @aaron.ballman 
wrote:

> In D130224#3687860 , @amyk wrote:
>
>> In D130224#3687487 , @mubarizafzal 
>> wrote:
>>
>>> Hi, the test cases that this patch introduces are failing on some ppc64le 
>>> (Linux on Power) buildbots:
>>> https://lab.llvm.org/buildbot/#/builders/57
>>> https://lab.llvm.org/buildbot/#/builders/230
>>>
>>> Would you mind taking a look please?
>>
>> Thanks for pinging this patch. It appears it's affecting both little endian 
>> PPC:
>> https://lab.llvm.org/buildbot/#/builders/230/builds/1079
>> https://lab.llvm.org/buildbot/#/builders/121/builds/21978
>> https://lab.llvm.org/buildbot/#/builders/57/builds/20484
>> https://lab.llvm.org/buildbot/#/builders/36/builds/23702
>>
>> And big endian PPC bots:
>> https://lab.llvm.org/buildbot/#/builders/231/builds/842
>> https://lab.llvm.org/buildbot/#/builders/93/builds/10270
>
> If we don't hear from @skc7 in the next ~hour with a fix, feel free to revert 
> to get the bots back to green.

Thanks @aaron.ballman. I've reverted the patch for the time being: 
https://reviews.llvm.org/rG4e1fe968c9de73507a1bf0c8aa57e06be457816e


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[PATCH] D130224: [Clang][Attribute] Introduce maybe_undef attribute for function arguments which accepts undef values

2022-07-29 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D130224#3687487 , @mubarizafzal 
wrote:

> Hi, the test cases that this patch introduces are failing on some ppc64le 
> (Linux on Power) buildbots:
> https://lab.llvm.org/buildbot/#/builders/57
> https://lab.llvm.org/buildbot/#/builders/230
>
> Would you mind taking a look please?

Thanks for pinging this patch. It appears it's affecting both little endian PPC:
https://lab.llvm.org/buildbot/#/builders/230/builds/1079
https://lab.llvm.org/buildbot/#/builders/121/builds/21978
https://lab.llvm.org/buildbot/#/builders/57/builds/20484
https://lab.llvm.org/buildbot/#/builders/36/builds/23702

And big endian PPC bots:
https://lab.llvm.org/buildbot/#/builders/231/builds/842
https://lab.llvm.org/buildbot/#/builders/93/builds/10270

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[PATCH] D130066: [pseudo] Key guards by RuleID, add guards to literals (and 0).

2022-07-22 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D130066#3670875 , @sammccall wrote:

> In D130066#3670745 , @amyk wrote:
>
>> Hi!
>>
>> It appears that this patch is causing a build failure on a couple PPC bots 
>> that build with shared libraries:
>> https://lab.llvm.org/buildbot/#/builders/57/builds/20179
>> https://lab.llvm.org/buildbot/#/builders/121/builds/21678
>>
>> The specific error that occurs looks like this:
>>
>>   2.485 [936/22/19] Linking CXX shared library lib/libclangPseudoCXX.so.15git
>>   FAILED: lib/libclangPseudoCXX.so.15git 
>>   : && /home/buildbots/clang.11.0.0/bin/clang++ 
>> --gcc-toolchain=/opt/rh/devtoolset-7/root/usr -fPIC -fPIC 
>> -fvisibility-inlines-hidden -Werror -Werror=date-time 
>> -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter 
>> -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic 
>> -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough 
>> -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor 
>> -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion 
>> -Wmisleading-indentation -fdiagnostics-color -ffunction-sections 
>> -fdata-sections -fno-common -Woverloaded-virtual -Wno-nested-anon-types -O3 
>> -DNDEBUG  -Wl,-z,defs -Wl,-z,nodelete   
>> -Wl,-rpath-link,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/./lib
>>   -Wl,--gc-sections -shared -Wl,-soname,libclangPseudoCXX.so.15git -o 
>> lib/libclangPseudoCXX.so.15git 
>> tools/clang/tools/extra/pseudo/lib/cxx/CMakeFiles/obj.clangPseudoCXX.dir/CXX.cpp.o
>>   -Wl,-rpath,"\$ORIGIN/../lib"  lib/libclangPseudo.so.15git  
>> lib/libclangPseudoGrammar.so.15git  lib/libLLVMSupport.so.15git  
>> -Wl,-rpath-link,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib
>>  && :
>>   
>> tools/clang/tools/extra/pseudo/lib/cxx/CMakeFiles/obj.clangPseudoCXX.dir/CXX.cpp.o:(.toc+0x10):
>>  undefined reference to `clang::charinfo::InfoTable'
>>   clang++: error: linker command failed with exit code 1 (use -v to see 
>> invocation)
>>
>> Would you be able to take a look at this issue (or revert the patch if this 
>> requires more time to resolve)? Thank you in advance.
>
> Sorry about that. d26ee284ded30aff46 
>  links 
> in clangBasic for this dep.
> (I think it wasn't showing up in the non-shared builds because these 
> functions were always inlined)

Thank you for fixing the build failures, @sammccall, I appreciate it! The bots 
are back to green now. :-)


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[PATCH] D130066: [pseudo] Key guards by RuleID, add guards to literals (and 0).

2022-07-21 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Hi!

It appears that this patch is causing a build failure on a couple PPC bots that 
build with shared libraries:
https://lab.llvm.org/buildbot/#/builders/57/builds/20179
https://lab.llvm.org/buildbot/#/builders/121/builds/21678

The specific error that occurs looks like this:

  2.485 [936/22/19] Linking CXX shared library lib/libclangPseudoCXX.so.15git
  FAILED: lib/libclangPseudoCXX.so.15git 
  : && /home/buildbots/clang.11.0.0/bin/clang++ 
--gcc-toolchain=/opt/rh/devtoolset-7/root/usr -fPIC -fPIC 
-fvisibility-inlines-hidden -Werror -Werror=date-time 
-Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter 
-Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic 
-Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough 
-Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor 
-Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion 
-Wmisleading-indentation -fdiagnostics-color -ffunction-sections 
-fdata-sections -fno-common -Woverloaded-virtual -Wno-nested-anon-types -O3 
-DNDEBUG  -Wl,-z,defs -Wl,-z,nodelete   
-Wl,-rpath-link,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/./lib
  -Wl,--gc-sections -shared -Wl,-soname,libclangPseudoCXX.so.15git -o 
lib/libclangPseudoCXX.so.15git 
tools/clang/tools/extra/pseudo/lib/cxx/CMakeFiles/obj.clangPseudoCXX.dir/CXX.cpp.o
  -Wl,-rpath,"\$ORIGIN/../lib"  lib/libclangPseudo.so.15git  
lib/libclangPseudoGrammar.so.15git  lib/libLLVMSupport.so.15git  
-Wl,-rpath-link,/home/buildbots/docker-RHEL-buildbot/SetupBot/worker_env/ppc64le-clang-rhel-test/clang-ppc64le-rhel/build/lib
 && :
  
tools/clang/tools/extra/pseudo/lib/cxx/CMakeFiles/obj.clangPseudoCXX.dir/CXX.cpp.o:(.toc+0x10):
 undefined reference to `clang::charinfo::InfoTable'
  clang++: error: linker command failed with exit code 1 (use -v to see 
invocation)

Would you be able to take a look at this issue (or revert the patch if this 
requires more time to resolve)? Thank you in advance.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

2022-06-28 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/test/Driver/ppc-unsupported.c:12
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s

amyk wrote:
> Should we have a big endian Linux check, too?
Oh, sorry. I noticed there wasn't `powerpc64-unknown-linux` but I realized I 
think `powerpc64-unknown-freebsd` is supposed to be the big endian 64-bit Linux 
check, right?


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

2022-06-28 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

This patch makes sense. I had some questions regarding it.




Comment at: clang/include/clang/Driver/Options.td:3611
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only 
volatile vector registers.">;
+def maix_quadword_atomics : Flag<["-"], "maix64-quadword-atomics">,
+  Group, Flags<[CC1Option]>,

Would it be better if we called this `maix64-quadword-atomics` instead? 



Comment at: clang/test/Driver/ppc-unsupported.c:12
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s

Should we have a big endian Linux check, too?


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[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

2022-06-28 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

LGTM too. Thank you Lei.


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[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

2022-06-16 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

This patch also LGTM. Thank you Lei.


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[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

2022-06-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.
This revision is now accepted and ready to land.

Thanks for the updates. Unless @lei has any other additional comments, I think 
LGTM.


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[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

2022-06-15 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Some additional minor comments.




Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:7572
+  "Current bitcast for incompatible vector types (%0 and %1) are deprecated. "
+  "The default behaviour will change to what implied by the "
+  "-fno-lax-vector-conversions option">,

amyk wrote:
> 
nit: Update to 
>The default behaviour will change to what is implied by the



Comment at: clang/lib/Sema/SemaExpr.cpp:7715
 
+bool Sema::areAnyVectorTypesAltivec(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());

Can we add some brief documentation for this function, like what is done for 
other functions in this file?



Comment at: clang/lib/Sema/SemaExpr.cpp:7716
+bool Sema::areAnyVectorTypesAltivec(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());
+

Can we add a message to this `assert()`?



Comment at: clang/lib/Sema/SemaExpr.cpp:7722
+  if (SrcTy->isVectorType())
+  {
+VectorType::VectorKind SrcVecKind = 
SrcTy->castAs()->getVectorKind();

nit: Can we put braces on the same line? (And same goes for 7727)



Comment at: clang/lib/Sema/SemaExpr.cpp:7735
+
+bool Sema::areVectorTypesSameElmType(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());

Can we add some brief documentation for this function, like what is done for 
other functions in this file?



Comment at: clang/lib/Sema/SemaExpr.cpp:7736
+bool Sema::areVectorTypesSameElmType(QualType SrcTy, QualType DestTy) {
+  assert(DestTy->isVectorType() || SrcTy->isVectorType());
+

Can we add a message to this assert?



Comment at: clang/lib/Sema/SemaExpr.cpp:7762
   }
-
   return areLaxCompatibleVectorTypes(srcTy, destTy);

Unnecessary change?



Comment at: clang/lib/Sema/SemaOverload.cpp:13027
   // end up here.
+  //
   return SemaRef.BuildCallExpr(/*Scope*/ nullptr, NewFn.get(), LParenLoc,

amyk wrote:
> Unnecessary change?
Unnecessary change?


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[PATCH] D126540: PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions

2022-05-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:7572
+  "Current bitcast for incompatible vector types (%0 and %1) are deprecated. "
+  "The default behaviour will change to what implied by the "
+  "-fno-lax-vector-conversions option">,





Comment at: clang/lib/Sema/SemaOverload.cpp:1664
  !ToType->hasAttr(attr::ArmMveStrictPolymorphism))) {
+  if (!InOverloadResolution &&
+  FromType->castAs()->getVectorKind() ==

Just wanted to check, but is this case covered in the comment above? If it is 
not, can we add a comment for it?



Comment at: clang/lib/Sema/SemaOverload.cpp:13027
   // end up here.
+  //
   return SemaRef.BuildCallExpr(/*Scope*/ nullptr, NewFn.get(), LParenLoc,

Unnecessary change?


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[PATCH] D126302: [PowerPC] Diagnose invalid combination with Altivec, VSX and soft-float

2022-05-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:452
+  if (llvm::is_contained(FeaturesVec, "-hard-float") &&
+  llvm::is_contained(FeaturesVec, "+altivec"))
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float"

Do we also need a case to represent `-msoft-float` and `-mvsx`?


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[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D125506#3528380 , @nathanchance 
wrote:

> I bisected a crash when compiling the Linux kernel to this change.
>
> A reduced C reproducer:
>
>   enum {
> OP_CB_GETATTR = 3,
> OP_CB_RECALL,
> OP_CB_RECALL_ANY = 8,
> OP_CB_RECALL_SLOT = 10,
> OP_CB_NOTIFY_LOCK = 13,
> OP_CB_NOTIFY_DEVICEID,
> OP_CB_OFFLOAD
>   } static callback_ops_0;
>   int preprocess_nfs42_op_op_nr, preprocess_nfs42_op_op;
>   void preprocess_nfs42_op() {
> switch (preprocess_nfs42_op_op_nr)
> case OP_CB_GETATTR:
> case OP_CB_RECALL:
> case OP_CB_RECALL_ANY:
> case OP_CB_RECALL_SLOT:
> case OP_CB_NOTIFY_DEVICEID:
> case OP_CB_NOTIFY_LOCK:
>   preprocess_nfs42_op_op = preprocess_nfs42_op_op_nr;
> if (preprocess_nfs42_op_op_nr == OP_CB_OFFLOAD)
>   preprocess_nfs42_op_op = callback_ops_0;
>   }
>
>
>
>   $ clang --version | head -1
>   ClangBuiltLinux clang version 15.0.0 (https://github.com/llvm/llvm-project 
> 559b8fc17ef6f5a65ccf9a11fce5f91c0a011b00)
>   
>   $ clang --target=powerpc64le-linux-gnu -O2 -Wall -Wextra -c -o /dev/null 
> callback_xdr.i
>
>
>
>   $ clang --version | head -1
>   ClangBuiltLinux clang version 15.0.0 (https://github.com/llvm/llvm-project 
> c35ca3a1c78f693b749ad11742350b7fc6c5cd89)
>   
>   $ clang --target=powerpc64le-linux-gnu -O2 -Wall -Wextra -c -o /dev/null 
> callback_xdr.i
>   Impossible reg-to-reg copy
>   UNREACHABLE executed at 
> /home/nathan/cbl/src/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1861!
>   PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ 
> and include the crash backtrace, preprocessed source, and associated run 
> script.
>   Stack dump:
>   0.  Program arguments: clang --target=powerpc64le-linux-gnu -O2 -Wall 
> -Wextra -c -o /dev/null callback_xdr.i
>   1.   parser at end of file
>   2.  Code generation
>   3.  Running pass 'Function Pass Manager' on module 'callback_xdr.i'.
>   4.  Running pass 'Post-RA pseudo instruction expansion pass' on 
> function '@preprocess_nfs42_op'
>#0 0x55a3bcb4e583 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3351583)
>#1 0x55a3bcb4c50e llvm::sys::RunSignalHandlers() 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x334f50e)
>#2 0x55a3bcad2923 (anonymous 
> namespace)::CrashRecoveryContextImpl::HandleCrash(int, unsigned long) 
> CrashRecoveryContext.cpp:0:0
>#3 0x55a3bcad2a9e CrashRecoverySignalHandler(int) 
> CrashRecoveryContext.cpp:0:0
>#4 0x7f4af3152b00 __restore_rt (/lib64/libc.so.6+0x3eb00)
>#5 0x7f4af31a2d0c __pthread_kill_implementation 
> (/lib64/libc.so.6+0x8ed0c)
>#6 0x7f4af3152a56 gsignal (/lib64/libc.so.6+0x3ea56)
>#7 0x7f4af313c7f4 abort (/lib64/libc.so.6+0x287f4)
>#8 0x55a3bcad787f 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x32da87f)
>#9 0x55a3bb83b308 
> llvm::PPCInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, 
> llvm::MachineInstrBundleIterator, llvm::DebugLoc 
> const&, llvm::MCRegister, llvm::MCRegister, bool) const PPCInstrInfo.cpp:0:0
>   #10 0x55a3bc1242bb (anonymous 
> namespace)::ExpandPostRA::runOnMachineFunction(llvm::MachineFunction&) 
> ExpandPostRAPseudos.cpp:0:0
>   #11 0x55a3bbf62d4d 
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2765d4d)
>   #12 0x55a3bc3fc107 llvm::FPPassManager::runOnFunction(llvm::Function&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2bff107)
>   #13 0x55a3bc403b81 llvm::FPPassManager::runOnModule(llvm::Module&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2c06b81)
>   #14 0x55a3bc3fcafc llvm::legacy::PassManagerImpl::run(llvm::Module&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2bffafc)
>   #15 0x55a3bd2fd16d clang::EmitBackendOutput(clang::DiagnosticsEngine&, 
> clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, 
> clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, 
> llvm::Module*, clang::BackendAction, std::unique_ptr std::default_delete>) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3b0016d)
>   #16 0x55a3bd6a27ee 
> clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) 
> CodeGenAction.cpp:0:0
>   #17 0x55a3bdf46cb4 clang::ParseAST(clang::Sema&, bool, bool) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x4749cb4)
>   #18 0x55a3bd5f0f50 clang::FrontendAction::Execute() 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3df3f50)
>   #19 0x55a3bd565d1f 
> clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3d68d1f)
>   #20 0x55a3bd69be92 
> clang::ExecuteCompilerInvocation(clang::CompilerInstance*) 
>

[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D125506#3528380 , @nathanchance 
wrote:

> I bisected a crash when compiling the Linux kernel to this change.
>
> A reduced C reproducer:
>
>   enum {
> OP_CB_GETATTR = 3,
> OP_CB_RECALL,
> OP_CB_RECALL_ANY = 8,
> OP_CB_RECALL_SLOT = 10,
> OP_CB_NOTIFY_LOCK = 13,
> OP_CB_NOTIFY_DEVICEID,
> OP_CB_OFFLOAD
>   } static callback_ops_0;
>   int preprocess_nfs42_op_op_nr, preprocess_nfs42_op_op;
>   void preprocess_nfs42_op() {
> switch (preprocess_nfs42_op_op_nr)
> case OP_CB_GETATTR:
> case OP_CB_RECALL:
> case OP_CB_RECALL_ANY:
> case OP_CB_RECALL_SLOT:
> case OP_CB_NOTIFY_DEVICEID:
> case OP_CB_NOTIFY_LOCK:
>   preprocess_nfs42_op_op = preprocess_nfs42_op_op_nr;
> if (preprocess_nfs42_op_op_nr == OP_CB_OFFLOAD)
>   preprocess_nfs42_op_op = callback_ops_0;
>   }
>
>
>
>   $ clang --version | head -1
>   ClangBuiltLinux clang version 15.0.0 (https://github.com/llvm/llvm-project 
> 559b8fc17ef6f5a65ccf9a11fce5f91c0a011b00)
>   
>   $ clang --target=powerpc64le-linux-gnu -O2 -Wall -Wextra -c -o /dev/null 
> callback_xdr.i
>
>
>
>   $ clang --version | head -1
>   ClangBuiltLinux clang version 15.0.0 (https://github.com/llvm/llvm-project 
> c35ca3a1c78f693b749ad11742350b7fc6c5cd89)
>   
>   $ clang --target=powerpc64le-linux-gnu -O2 -Wall -Wextra -c -o /dev/null 
> callback_xdr.i
>   Impossible reg-to-reg copy
>   UNREACHABLE executed at 
> /home/nathan/cbl/src/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1861!
>   PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ 
> and include the crash backtrace, preprocessed source, and associated run 
> script.
>   Stack dump:
>   0.  Program arguments: clang --target=powerpc64le-linux-gnu -O2 -Wall 
> -Wextra -c -o /dev/null callback_xdr.i
>   1.   parser at end of file
>   2.  Code generation
>   3.  Running pass 'Function Pass Manager' on module 'callback_xdr.i'.
>   4.  Running pass 'Post-RA pseudo instruction expansion pass' on 
> function '@preprocess_nfs42_op'
>#0 0x55a3bcb4e583 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3351583)
>#1 0x55a3bcb4c50e llvm::sys::RunSignalHandlers() 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x334f50e)
>#2 0x55a3bcad2923 (anonymous 
> namespace)::CrashRecoveryContextImpl::HandleCrash(int, unsigned long) 
> CrashRecoveryContext.cpp:0:0
>#3 0x55a3bcad2a9e CrashRecoverySignalHandler(int) 
> CrashRecoveryContext.cpp:0:0
>#4 0x7f4af3152b00 __restore_rt (/lib64/libc.so.6+0x3eb00)
>#5 0x7f4af31a2d0c __pthread_kill_implementation 
> (/lib64/libc.so.6+0x8ed0c)
>#6 0x7f4af3152a56 gsignal (/lib64/libc.so.6+0x3ea56)
>#7 0x7f4af313c7f4 abort (/lib64/libc.so.6+0x287f4)
>#8 0x55a3bcad787f 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x32da87f)
>#9 0x55a3bb83b308 
> llvm::PPCInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, 
> llvm::MachineInstrBundleIterator, llvm::DebugLoc 
> const&, llvm::MCRegister, llvm::MCRegister, bool) const PPCInstrInfo.cpp:0:0
>   #10 0x55a3bc1242bb (anonymous 
> namespace)::ExpandPostRA::runOnMachineFunction(llvm::MachineFunction&) 
> ExpandPostRAPseudos.cpp:0:0
>   #11 0x55a3bbf62d4d 
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2765d4d)
>   #12 0x55a3bc3fc107 llvm::FPPassManager::runOnFunction(llvm::Function&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2bff107)
>   #13 0x55a3bc403b81 llvm::FPPassManager::runOnModule(llvm::Module&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2c06b81)
>   #14 0x55a3bc3fcafc llvm::legacy::PassManagerImpl::run(llvm::Module&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x2bffafc)
>   #15 0x55a3bd2fd16d clang::EmitBackendOutput(clang::DiagnosticsEngine&, 
> clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, 
> clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, 
> llvm::Module*, clang::BackendAction, std::unique_ptr std::default_delete>) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3b0016d)
>   #16 0x55a3bd6a27ee 
> clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) 
> CodeGenAction.cpp:0:0
>   #17 0x55a3bdf46cb4 clang::ParseAST(clang::Sema&, bool, bool) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x4749cb4)
>   #18 0x55a3bd5f0f50 clang::FrontendAction::Execute() 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3df3f50)
>   #19 0x55a3bd565d1f 
> clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) 
> (/home/nathan/tmp/build/llvm-bisect/stage1/bin/clang-15+0x3d68d1f)
>   #20 0x55a3bd69be92 
> clang::ExecuteCompilerInvocation(clang::CompilerInstance*) 
>

[PATCH] D124093: [PowerPC] Fixing implicit castings in altivec for -fno-lax-vector-conversions

2022-05-20 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

I was wondering where are the test cases in this patch. Did they get missed 
when updating the revision?


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[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-19 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc35ca3a1c78f: [PowerPC] Implement XL compat __fnabs and 
__fnabss builtins. (authored by amyk).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D125506

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr6 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mattr=+vsx < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)
+declare float @llvm.ppc.fnabss(float)
+
+define double @test_fnabs2(double %d) {
+; CHECK-DEFAULT-LABEL: test_fnabs2:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabs2:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.fnabs(double %d)
+  ret double %0
+}
+
+define float @test_fnabss(float %f) {
+; CHECK-DEFAULT-LABEL: test_fnabss:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabss:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnabss(float %f)
+  ret float %0
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -703,6 +703,11 @@
   (outs vsfrc:$XT), (ins vsfrc:$XB),
   "xsnabsdp $XT, $XB", IIC_VecFP,
   [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
+  let isCodeGenOnly = 1 in
+  def XSNABSDPs : XX2Form<60, 361,
+  (outs vssrc:$XT), (ins vssrc:$XB),
+  "xsnabsdp $XT, $XB", IIC_VecFP,
+  [(set f32:$XT, (fneg (fabs f32:$XB)))]>;
   def XSNEGDP : XX2Form<60, 377,
   (outs vsfrc:$XT), (ins vsfrc:$XB),
   "xsnegdp $XT, $XB", IIC_VecFP,
@@ -2871,6 +2876,8 @@
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
 def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+def : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>;
+def : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>;
 
 // XXMRG[LH]W is a direct replacement for

[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-19 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 430671.
amyk added a comment.

- Add a P6 +VSX run line and remove extra P7 
/P8  lines for 
backend test


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D125506

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr6 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mattr=+vsx < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)
+declare float @llvm.ppc.fnabss(float)
+
+define double @test_fnabs2(double %d) {
+; CHECK-DEFAULT-LABEL: test_fnabs2:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabs2:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.fnabs(double %d)
+  ret double %0
+}
+
+define float @test_fnabss(float %f) {
+; CHECK-DEFAULT-LABEL: test_fnabss:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabss:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnabss(float %f)
+  ret float %0
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -703,6 +703,11 @@
   (outs vsfrc:$XT), (ins vsfrc:$XB),
   "xsnabsdp $XT, $XB", IIC_VecFP,
   [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
+  let isCodeGenOnly = 1 in
+  def XSNABSDPs : XX2Form<60, 361,
+  (outs vssrc:$XT), (ins vssrc:$XB),
+  "xsnabsdp $XT, $XB", IIC_VecFP,
+  [(set f32:$XT, (fneg (fabs f32:$XB)))]>;
   def XSNEGDP : XX2Form<60, 377,
   (outs vsfrc:$XT), (ins vsfrc:$XB),
   "xsnegdp $XT, $XB", IIC_VecFP,
@@ -2871,6 +2876,8 @@
 def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (XSNMADDMDP $A, $B, $C)>;
 def : Pat<(int_ppc_fre f64:$A), (XSREDP $A)>;
 def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+def : Pat<(int_ppc_fnabs f64:$A), (XSNABSDP $A)>;
+def : Pat<(int_ppc_fnabss f32:$A), (XSNABSDPs $A)>;
 
 // XXMRG[LH]W is a direct replacement for VMRG[LH]W

[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-19 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:46
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)

lei wrote:
> nit: same as before no need to test all combination for both pwr7 and pwr8.  
> Just a mix of the 2 like in the clang test. What happens if we do pwr6 with 
> `+vsx`?  Is this a possible combination?
Thanks Lei, I'll update those lines. We also discussed outside of this review 
that adding a P6 and VSX line results in `xsnabsdp` and it wouldn't hurt to add 
it here too, so I'll add one line for that, as well. 


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[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-18 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 430249.
amyk added a comment.

Address review comments:

- Remove `-no-opaque-pointers` and updates CHECKs
- Simplify runs and checks of C and IR test files


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125506/new/

https://reviews.llvm.org/D125506

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr7 \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-DEFAULT
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-NOVSX
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)
+declare float @llvm.ppc.fnabss(float)
+
+define double @test_fnabs2(double %d) {
+; CHECK-DEFAULT-LABEL: test_fnabs2:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabs2:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.fnabs(double %d)
+  ret double %0
+}
+
+define float @test_fnabss(float %f) {
+; CHECK-DEFAULT-LABEL: test_fnabss:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp f1, f1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabss:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs f1, f1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnabss(float %f)
+  ret float %0
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -703,6

[PATCH] D125506: [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, power-llvm-team, nemanjai, lei.
amyk added a project: LLVM.
Herald added subscribers: shchenz, hiraditya.
Herald added a project: All.
amyk requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch implements the following floating point negative absolute value
builtins that required for compatibility with the XL compiler:

  double __fnabs(double);
  float __fnabss(float);


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125506

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr8 < %s |\
+; RUN:   FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix -mcpu=pwr7 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-DEFAULT
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr6 < %s | FileCheck %s --check-prefix=CHECK-PWR6
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr6 < %s | FileCheck %s --check-prefix=CHECK-PWR6
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr6 < %s | FileCheck %s --check-prefix=CHECK-PWR6
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr6 < %s | FileCheck %s --check-prefix=CHECK-PWR6
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+declare double @llvm.ppc.fnabs(double)
+declare float @llvm.ppc.fnabss(float)
+
+define double @test_fnabs2(double %d) {
+; CHECK-DEFAULT-LABEL: test_fnabs2:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp 1, 1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-PWR6-LABEL: test_fnabs2:
+; CHECK-PWR6:   # %bb.0: # %entry
+; CHECK-PWR6-NEXT:fnabs 1, 1
+; CHECK-PWR6-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabs2:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs 1, 1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call double @llvm.ppc.fnabs(double %d)
+  ret double %0
+}
+
+define float @test_fnabss(float %f) {
+; CHECK-DEFAULT-LABEL: test_fnabss:
+; CHECK-DEFAULT:   # %bb.0: # %entry
+; CHECK-DEFAULT-NEXT:xsnabsdp 1, 1
+; CHECK-DEFAULT-NEXT:blr
+;
+; CHECK-PWR6-LABEL: test_fnabss:
+; CHECK-PWR6:   # %bb.0: # %entry
+; CHECK-PWR6-NEXT:fnabs 1, 1
+; CHECK-PWR6-NEXT:blr
+;
+; CHECK-NOVSX-LABEL: test_fnabss:
+; CHECK-NOVSX:   # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:fnabs 1, 1
+; CHECK-NOVSX-NEXT:blr
+entry:
+  %0 = tail call float @llvm.ppc.fnabss(float %f)
+  ret float %0
+}
+
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -703,6 +703,11 @@
   (outs vsfrc:$XT), (ins vsfrc:$XB),
   "xsnabsdp $XT, $XB", IIC_VecFP,
   [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
+  let isCodeGenOnly = 1 in
+  def XSNABSDPs : XX2Form<60, 361,
+  (outs vssrc:$XT), (ins vssrc:$XB),
+

[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

2022-05-02 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.

Comment at: llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll:5
 ; CHECK-LABEL: TestULT:
-; CHECK: xscmpudp
+; CHECK: fcmpu
 ; CHECK: blr

nemanjai wrote:
> Why do we not emit the VSX instructions here any longer? How are crbits 
> related?
Nemanja and I discussed this outside of the revision. This test case is ran 
with FastISel by default.

It looks like for fcmp ULT/UEQ/UGT/OLE/ONE/OGE, we're not able to find a 
compare predicate, so we don't use FastIISel for these changed test cases.
With my patch (turning on CR bits), we end up matching to fcmpu in the td 
patterns, but when CR bits are not present, we match to the VSX instructions in 
PPCISelDAGToDAG. 
This should be something we investigate at a later date.

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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

2022-05-02 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
amyk marked an inline comment as done.
Closed by commit rG2534dc120a4c: [PowerPC] Enable CR bits support for Power8 
and above. (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D124060?vs=425417=426439#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-crbits.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/test/CodeGen/PowerPC/addegluecrash.ll
  llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
  llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
  llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
  llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll

Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
 ; CHECK-LE-LABEL: i32_ZextLoad_i1:
 ; CHECK-LE:   # %bb.0: # %entry
 ; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
 ; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
 ; CHECK-LE-NEXT:blr
 ;
@@ -53,6 +54,7 @@
 ; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
 ; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
 ; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
 ; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
 ; CHECK-BE-NEXT:blr
 entry:
@@ -77,11 +79,11 @@
 ; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
 ; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
 ; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-LE-NEXT:addi r1, r1, 32
 ; CHECK-LE-NEXT:ld r0, 16(r1)
 ; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
 ; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
 ; CHECK-BE-NEXT:bl Decl
 ; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-BE-NEXT:addi r1, r1, 112
 ; CHECK-BE-NEXT:ld r0, 16(r1)
 ; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xscvdpsxws 0, 1
 ; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
 ; CHECK-NEXT:blr
 entry:
   %conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
 define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; CHECK-LABEL: une_ppcf128:
 ; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-; CHECK-NEXT:rlwinm r5, r5, 31, 31, 31
-; CHECK-NEXT:xori r5, r5, 1
-; CHECK-NEXT:and r3, r3, r5
-; CHECK-NEXT:or r3, r3, r4
-; CHECK-NEXT:# kill: def $r4 killed $r3
+; CHECK-NEXT:fcmpu cr0, f1, f3
+; CHECK-NEXT:crmove 4*cr5+lt, eq
+; CHECK-NEXT:fcmpu cr1,

[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

2022-04-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk marked an inline comment as done.
amyk added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:519
 .Default(false);
+  Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)

shchenz wrote:
> If we set the `+crbits` by the arch name, do we still need the customization 
> (Turn on crbits for O2 and above) in `computeFSAdditions()`? 
Yeah, that's a good point. I looked into this previously, and it appears that 
addition of `-mcrbits` inside `computeFSAdditions()` may still be necessary. 

In particular, we have test cases that test pre-POWER8 with optimizations on 
(or, if no optimization level is provided, then -O2 is assumed the default). In 
these cases, much of the code changes if the customization inside 
`computeFSAdditions()` is removed because we would no longer be using crbits 
pre-P8.



Comment at: clang/test/Driver/ppc-crbits.cpp:50
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
+// RUN:   -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+

shchenz wrote:
> Do we need some cases for AIX?
Thanks, I've added some.


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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

2022-04-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 425417.
amyk added a comment.

Address review comments of adding documentation to 
`clang/docs/ClangCommandLineReference.rst` and adding AIX checks to 
`clang/test/Driver/ppc-crbits.cpp`.


Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-crbits.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/test/CodeGen/PowerPC/addegluecrash.ll
  llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
  llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
  llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
  llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll

Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
 ; CHECK-LE-LABEL: i32_ZextLoad_i1:
 ; CHECK-LE:   # %bb.0: # %entry
 ; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
 ; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
 ; CHECK-LE-NEXT:blr
 ;
@@ -53,6 +54,7 @@
 ; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
 ; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
 ; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
 ; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
 ; CHECK-BE-NEXT:blr
 entry:
@@ -77,11 +79,11 @@
 ; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
 ; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
 ; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-LE-NEXT:addi r1, r1, 32
 ; CHECK-LE-NEXT:ld r0, 16(r1)
 ; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
 ; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
 ; CHECK-BE-NEXT:bl Decl
 ; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-BE-NEXT:addi r1, r1, 112
 ; CHECK-BE-NEXT:ld r0, 16(r1)
 ; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xscvdpsxws 0, 1
 ; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
 ; CHECK-NEXT:blr
 entry:
   %conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
 define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; CHECK-LABEL: une_ppcf128:
 ; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-; CHECK-NEXT:rlwinm r5, r5, 31, 31, 31
-; CHECK-NEXT:xori r5, r5, 1
-; CHECK-NEXT:and r3, r3, r5
-; CHECK-NEXT:or r3, r3, r4
-; CHECK-NEXT:# kill: def $r4 killed $r3
+; CHECK-NEXT:fcmpu cr0, f1, f3
+; CHECK-NEXT:crmove 4*cr5+lt, eq
+; CHECK-NEXT:fcmpu cr1, f2, f4
+; CHECK-NEXT:crmove 4*cr5+gt, 4*cr1+eq
+; CHECK-NEXT:crnot 4*cr5+gt, 4*cr5+gt
+; CHECK-NEXT:crand 4*cr5+gt, 4*cr5+lt,

[PATCH] D119136: [clang] Implement Change scope of lambda trailing-return-type

2022-04-20 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

In D119136#3459738 , @alanphipps 
wrote:

> We've also been seeing failures in our downstream Arm compiler when running 
> the Perennial C++14 compliance tests related to this change.  Specifically, 
> the tests expect a diagnostic to be issued when the lambda capture variable 
> is outside of the lambda's {} scope. Another tests uses the lambda capture 
> variable in a decltype-style return type which is also outside of the scope.
>
> Do these failures sound like what others have run into?

Hi, I would just like to express that I am also seeing these two issues on 
Power, that are a result of the original patch (D119136 
) that @alanphipps has pointed out.


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[PATCH] D124060: [PowerPC] Enable CR bits support for Power8 and above.

2022-04-19 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, power-llvm-team.
amyk added projects: LLVM, clang, PowerPC.
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This patch turns on support for CR bit accesses for Power8 and above. The 
reason why CR bits are turned
on as the default for Power8 and above is that because later architectures make 
use of builtins and
instructions that require CR bit accesses (such as the use of `setbc` in the 
vector string isolate predicate
and bcd builtins on Power10).

This patch also adds the clang portion to allow for turning on CR bits in the 
front end if the user so desires to.


Repository:
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https://reviews.llvm.org/D124060

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-crbits.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/test/CodeGen/PowerPC/addegluecrash.ll
  llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
  llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
  llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
  llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll

Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
 ; CHECK-LE-LABEL: i32_ZextLoad_i1:
 ; CHECK-LE:   # %bb.0: # %entry
 ; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:clrldi r3, r3, 63
 ; CHECK-LE-NEXT:pstb r3, GlobSt1@PCREL(0), 1
 ; CHECK-LE-NEXT:blr
 ;
@@ -53,6 +54,7 @@
 ; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
 ; CHECK-BE-NEXT:addis r4, r2, GlobSt1@toc@ha
 ; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:clrldi r3, r3, 63
 ; CHECK-BE-NEXT:stb r3, GlobSt1@toc@l(r4)
 ; CHECK-BE-NEXT:blr
 entry:
@@ -77,11 +79,11 @@
 ; CHECK-LE-NEXT:paddi r3, 0, Glob1@PCREL, 1
 ; CHECK-LE-NEXT:paddi r4, 0, Glob2@PCREL, 1
 ; CHECK-LE-NEXT:bl Decl@notoc
-; CHECK-LE-NEXT:plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT:cmplwi r3, 0
-; CHECK-LE-NEXT:li r3, 1
-; CHECK-LE-NEXT:iseleq r3, 0, r3
-; CHECK-LE-NEXT:and r3, r3, r4
+; CHECK-LE-NEXT:cmpwi cr1, r3, 0
+; CHECK-LE-NEXT:plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT:andi. r3, r3, 1
+; CHECK-LE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-LE-NEXT:addi r1, r1, 32
 ; CHECK-LE-NEXT:ld r0, 16(r1)
 ; CHECK-LE-NEXT:mtlr r0
@@ -100,12 +102,12 @@
 ; CHECK-BE-NEXT:addi r4, r4, Glob2@toc@l
 ; CHECK-BE-NEXT:bl Decl
 ; CHECK-BE-NEXT:nop
-; CHECK-BE-NEXT:addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT:cmplwi r3, 0
-; CHECK-BE-NEXT:li r3, 1
-; CHECK-BE-NEXT:lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT:iseleq r3, 0, r3
-; CHECK-BE-NEXT:and r3, r3, r4
+; CHECK-BE-NEXT:cmpwi cr1, r3, 0
+; CHECK-BE-NEXT:addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT:lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT:andi. r3, r3, 1
+; CHECK-BE-NEXT:crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT:setbc r3, 4*cr5+lt
 ; CHECK-BE-NEXT:addi r1, r1, 112
 ; CHECK-BE-NEXT:ld r0, 16(r1)
 ; CHECK-BE-NEXT:mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:xscvdpsxws 0, 1
 ; CHECK-NEXT:mffprwz 3, 0
-; CHECK-NEXT:xori 3, 3, 65534
-; CHECK-NEXT:cntlzw 3, 3
-; CHECK-NEXT:srwi 4, 3, 5
-; CHECK-NEXT:# implicit-def: $x3
-; CHECK-NEXT:mr 3, 4
+; CHECK-NEXT:cmplwi 3, 65534
+; CHECK-NEXT:crmove 20, 2
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:isel 3, 3, 4, 20
 ; CHECK-NEXT:blr
 entry:
   %conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
 define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
 ; CHECK-LABEL: une_ppcf128:
 ; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xscmpudp cr7, f2, f4
-; CHECK-NEXT:mfocrf r4, 1
-; CHECK-NEXT:rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT:xori r4, r4, 1
-; CHECK-NEXT:and r4, r3, r4
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r3, 1
-; CHECK-NEXT:rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT:xori r3, r3, 1
-; CHECK-NEXT:xscmpudp cr7, f1, f3
-; CHECK-NEXT:mfocrf r5, 1
-;

[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

2022-04-04 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

Thanks Quinn. i think this overall LGTM.


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[PATCH] D121637: [PowerPC] Fix EmitPPCBuiltinExpr to emit arguments once

2022-03-28 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Overall this change looks good to me, although I do have one question.




Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15208
-  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
-if (E->getArg(i)->getType()->isArrayType())
-  Ops.push_back(EmitArrayToPointerDecay(E->getArg(i)).getPointer());

A question I have is do we not need to consider 
this/`EmitArrayToPointerDecay()` anymore? Was this not used for anything?


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[PATCH] D118753: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

2022-02-15 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5dc0a1657be1: [PowerPC] Fix __builtin_pdepd and 
__builtin_pextd to be 64-bit and P10 only. (authored by amyk).

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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
  llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll


Index: llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
===
--- llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -2,6 +2,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
 
 ; These test cases aim to test the bit manipulation operations on Power10.
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
@@ -0,0 +1,34 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+
+extern unsigned long long ull;
+
+unsigned long long test_builtin_pextd() {
+  // CHECK-LABEL:@test_builtin_pextd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pextd(ull, ull);
+}
+
+unsigned long long test_builtin_pdepd() {
+  // CHECK-LABEL:@test_builtin_pdepd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pdepd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pdepd(ull, ull);
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3604,6 +3604,8 @@
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_stdcx:
   case PPC::BI__builtin_ppc_tdw:
@@ -3763,6 +3765,10 @@
   case PPC::BI__builtin_pack_vector_int128:
 return SemaFeatureCheck(*this, TheCall, "vsx",
 diag::err_ppc_builtin_only_on_arch, "7");
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
+return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions",
+diag::err_ppc_builtin_only_on_arch, "10");
   case PPC::BI__builtin_altivec_vgnb:
  return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:


Index: llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
===
--- llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -2,6 +2,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
 
 ; These test cases aim to test the bit manipulation operations on Power10.
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c

[PATCH] D118753: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

2022-02-14 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Ping.


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[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

2022-02-10 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:432
   if (EnableTrapOptimization && TrapOpt) {
+bool IsVReg =
+(MI.getNumOperands() && MI.getOperand(0).isReg())

amyk wrote:
> Might be good to pull out `MI.getOperand(0).isReg()` into a separate variable 
> since you're using it three times here. 
I think you can disregard my comment. I realized later that there are both 
`isReg()` and `getReg()`, and the latter should be called only when `isReg()` 
is true. Sorry about that.


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[PATCH] D118753: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

2022-02-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, lei, kamaub, quinnp.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, kbarton.
amyk requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The `__builtin_pdepd` and `__builtin_pextd` are P10 
 builtins that are meant to
be used under 64-bit only. For instance, when the builtins are compiled under 
32-bit mode:

  $ cat t.c
  unsigned long long foo(unsigned long long a, unsigned long long b) {
return __builtin_pextd(a,b);
  }
  
  $ clang -c t.c -mcpu=pwr10 -m32
  ExpandIntegerResult #0: t31: i64 = llvm.ppc.pextd TargetConstant:i32<6928>, 
t28, t29
  
  fatal error: error in backend: Do not know how to expand the result of this 
operator!

This patch adds sema checking for these builtins to compile under 64-bit
mode only and on P10 . The builtins will emit a 
diagnostic when they are compiled on
non-P10 compilations and on 32-bit mode.


Repository:
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https://reviews.llvm.org/D118753

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
  llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll


Index: llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
===
--- llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -2,6 +2,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
 
 ; These test cases aim to test the bit manipulation operations on Power10.
 
Index: clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
@@ -0,0 +1,34 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+
+extern unsigned long long ull;
+
+unsigned long long test_builtin_pextd() {
+  // CHECK-LABEL:@test_builtin_pextd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pextd(ull, ull);
+}
+
+unsigned long long test_builtin_pdepd() {
+  // CHECK-LABEL:@test_builtin_pdepd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pdepd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pdepd(ull, ull);
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3576,6 +3576,8 @@
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_stdcx:
   case PPC::BI__builtin_ppc_tdw:
@@ -3735,6 +3737,10 @@
   case PPC::BI__builtin_pack_vector_int128:
 return SemaFeatureCheck(*this, TheCall, "vsx",
 diag::err_ppc_builtin_only_on_arch, "7");
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
+return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions",
+diag::err_ppc_builtin_only_on_arch, "10");
   case PPC::BI__builtin_altivec_vgnb:
  return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:


Index:

[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

2022-01-25 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:432
   if (EnableTrapOptimization && TrapOpt) {
+bool IsVReg =
+(MI.getNumOperands() && MI.getOperand(0).isReg())

Might be good to pull out `MI.getOperand(0).isReg()` into a separate variable 
since you're using it three times here. 



Comment at: llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir:1
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN:   -verify-machineinstrs -start-before=ppc-mi-peepholes \

Question: are AIX run lines necessary, too? 


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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

2021-11-16 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

Thanks for addressing the review comments and answering my question. This LGTM.


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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

2021-11-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1018
+unsigned Opcode2 = LiMI2->getOpcode();
+bool isOperand2Immeidate = MI.getOperand(2).isImm();
+// We can only do the optimization for the "reg + reg" form.





Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020
+// We can only do the optimization for the "reg + reg" form.
+if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8)))
+  break;

Do we still need to take into account of the lis+ori that Nemanja mentioned?



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1022
+  break;
+if (!isOperand2Immeidate &&
+!(LiMI2 && (Opcode2 == PPC::LI || Opcode2 == PPC::LI8)))





Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1028
+auto ImmOperand1 = LiMI1->getOperand(1).getImm();
+auto ImmOperand2 = isOperand2Immeidate ? MI.getOperand(2).getImm()
+   : LiMI2->getOperand(1).getImm();




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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

2021-11-05 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

Aside from Nemanja's comments, this patch LGTM. Thanks for addressing the 
comments!


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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

2021-11-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5001
+  case ISD::INTRINSIC_VOID: {
+if (N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ||
+N->getConstantOperandVal(1) == Intrinsic::ppc_tw) {

Might be a good idea to save `N->getConstantOperandVal(1)` since it is being 
accessed quite a few times here.



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5003
+N->getConstantOperandVal(1) == Intrinsic::ppc_tw) {
+  unsigned Opcode = 0;
+  int16_t SImmOperand2;

I see we emit TDI/TWI in 2/3 cases, so I was wondering if it make sense pull 
out setting the opcode in the second and third case to have the default opcode 
be:
```
Opcode = N->getConstantOperandVal(1) == Intrinsic::ppc_tdw ? PPC::TDI
   : PPC::TWI;
```
And then we just set the opcode to TD/TW in the first case?



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5038
+// when first and second bit of TO not same, swap them
+if ((TO & 0x1) != ((TO & 0x2) >> 1)) {
+  TO = (TO & 0x1) ? TO + 1 : TO - 1;

nit: Curly braces can be removed.



Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:5042
+// when third and fourth bit of TO not same, swap them
+if ((TO & 0x8) != ((TO & 0x10) >> 1)) {
+  TO = (TO & 0x8) ? TO + 8 : TO - 8;

nit: Curly braces can be removed.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:131
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdi 3, 3, 32767
+; CHECK-NEXT:blr

amyk wrote:
> nemanjai wrote:
> > Can we add `-ppc-asm-full-reg-names` to the RUN lines so it is more clear 
> > which operand is a register and which is an immediate. This works on AIX 
> > now since https://reviews.llvm.org/D94282 landed.
> Maybe it would be good to pre-commit the change with 
> `-ppc-asm-full-reg-names` added to the run lines so then this patch can only 
> contain the pertinent `td`/`tdi`/`tw`/`twi` changes.
I meant, maybe it is a better idea to commit the test cases with 
`-ppc-asm-full-reg-names` first, so then this revision does not contain the 
additional updates of adding the registers in places that is not affected by 
your patch. However, perhaps if Nemanja thinks adding the option to this patch 
is OK, then that's fine with me, too. 


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[PATCH] D112285: [PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions

2021-10-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:131
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tdi 3, 3, 32767
+; CHECK-NEXT:blr

nemanjai wrote:
> Can we add `-ppc-asm-full-reg-names` to the RUN lines so it is more clear 
> which operand is a register and which is an immediate. This works on AIX now 
> since https://reviews.llvm.org/D94282 landed.
Maybe it would be good to pre-commit the change with `-ppc-asm-full-reg-names` 
added to the run lines so then this patch can only contain the pertinent 
`td`/`tdi`/`tw`/`twi` changes.


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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions

2021-10-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1011
+  case PPC::TDI:
+  case PPC::TWI: {
+MachineInstr *LiMIA = getVRegDefOrNull((1), MRI);

nemanjai wrote:
> Seems that we should be able to handle all 4 in the same block:
> - Check that both operands are `LI[8]`/`LI[S][8]+ORI[8]` or an immediate
> - Set the variables for the three constants
> - Determine if this is an unconditional trap or never trap
> - Emit the correct instruction
+1



Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1013
+MachineInstr *LiMIA = getVRegDefOrNull((1), MRI);
+// will not optimize if no value set
+if (!(LiMIA && (LiMIA->getOpcode() == PPC::LI ||

nit: Capitalize and add a period (and for all other comments).


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[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-10-19 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5eaf5b916146: [PowerPC] Restrict various P10 options to P10 
only. (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D109652?vs=374990=380682#toc

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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-p10-features-support-check.c

Index: clang/test/Driver/ppc-p10-features-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-p10-features-support-check.c
@@ -0,0 +1,65 @@
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpaired-vector-memops %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+
+int test_p10_features() {
+  return 0;
+}
+
+// HASPAIRED: test_p10_features() #0 {
+// HASPAIRED: attributes #0 = {
+// HASPAIRED-SAME: +paired-vector-memops
+// NOPAIRED: option '-mpaired-vector-memops' cannot be specified without '-mcpu=pwr10'
+
+// HASPREFIXED: test_p10_features() #0 {
+// HASPREFIXED: attributes #0 = {
+// HASPREFIXED-SAME: +prefix-instrs
+// NOPREFIXED: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
+
+// HASPCREL: test_p10_features() #0 {
+// HASPCREL: attributes #0 = {
+// HASPCREL-SAME: +pcrelative-memops
+// NOPCREL: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
+
+// HASPCREL-PREFIX: test_p10_features() #0 {
+// HASPCREL-PREFIX: attributes #0 = {
+// HASPCREL-PREFIX-SAME: +pcrelative-memops
+// HASPCREL-PREFIX-SAME: +prefix-instrs
+// NOPCREL-PREFIX: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
+
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -568,11 +568,33 @@
 return false;
   }
 
-  if (!(ArchDefs & ArchDefinePwr10) &&
-  llvm::is_contained(FeaturesVec, "+mma")) {
-// We have MMA on PPC but not power 10 and above.
-Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
-return false;
+  if (!(ArchDefs & ArchDefinePwr10)) {
+if (llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
+  // MMA operations are not available pre-Power10.
+  Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
+  return false;
+}
+if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) {
+  // PC-Relative instructions are not available pre-Power10,
+  // and these instructions also require prefixed instructions support.
+  Diags.Report(diag::err_opt_not_valid_without_opt)
+  << "-mpcrel"
+  << "-mcpu=pwr10 -mprefixed";
+  return false;
+}
+if (llvm::find(FeaturesVec, "+prefixed") != FeaturesVec.end()) {
+  // Prefixed instructions are not available pre-Power10.
+  Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed"
+

[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

2021-10-12 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.

Aside from the comment made by Victor, also LGTM.


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[PATCH] D110935: [NFC] Update vec_extract builtin signatures to take signed int.

2021-10-08 Thread Amy Kwan via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG03bfddae5080: [NFC] Update vec_extract builtin signatures to 
take signed int. (authored by amyk).

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Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -13455,74 +13455,74 @@
 /* vec_extract */
 
 static __inline__ signed char __ATTRS_o_ai vec_extract(vector signed char __a,
-   unsigned int __b) {
+   signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai
-vec_extract(vector unsigned char __a, unsigned int __b) {
+vec_extract(vector unsigned char __a, signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai vec_extract(vector bool char __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ signed short __ATTRS_o_ai vec_extract(vector signed short 
__a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ unsigned short __ATTRS_o_ai
-vec_extract(vector unsigned short __a, unsigned int __b) {
+vec_extract(vector unsigned short __a, signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ unsigned short __ATTRS_o_ai vec_extract(vector bool short 
__a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ signed int __ATTRS_o_ai vec_extract(vector signed int __a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x3];
 }
 
 static __inline__ unsigned int __ATTRS_o_ai vec_extract(vector unsigned int 
__a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x3];
 }
 
 static __inline__ unsigned int __ATTRS_o_ai vec_extract(vector bool int __a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x3];
 }
 
 #ifdef __VSX__
 static __inline__ signed long long __ATTRS_o_ai
-vec_extract(vector signed long long __a, unsigned int __b) {
+vec_extract(vector signed long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ unsigned long long __ATTRS_o_ai
-vec_extract(vector unsigned long long __a, unsigned int __b) {
+vec_extract(vector unsigned long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ unsigned long long __ATTRS_o_ai
-vec_extract(vector bool long long __a, unsigned int __b) {
+vec_extract(vector bool long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ double __ATTRS_o_ai vec_extract(vector double __a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x1];
 }
 #endif
 
 static __inline__ float __ATTRS_o_ai vec_extract(vector float __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0x3];
 }
 


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -13455,74 +13455,74 @@
 /* vec_extract */
 
 static __inline__ signed char __ATTRS_o_ai vec_extract(vector signed char __a,
-   unsigned int __b) {
+   signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai
-vec_extract(vector unsigned char __a, unsigned int __b) {
+vec_extract(vector unsigned char __a, signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai vec_extract(vector bool char __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ signed short __ATTRS_o_ai vec_extract(vector signed short __a,
-

[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-10-08 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Ping @lei.


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[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

2021-10-07 Thread Amy Kwan via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG74b1ac7155a0: [NFC] Update return type of vec_popcnt to 
vector unsigned. (authored by amyk).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Headers/altivec.h


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -2482,7 +2482,7 @@
 #ifdef __POWER8_VECTOR__
 /* vec_popcnt */
 
-static __inline__ vector signed char __ATTRS_o_ai
+static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector signed char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
@@ -2490,7 +2490,7 @@
 vec_popcnt(vector unsigned char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
-static __inline__ vector signed short __ATTRS_o_ai
+static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector signed short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
@@ -2498,7 +2498,7 @@
 vec_popcnt(vector unsigned short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
-static __inline__ vector signed int __ATTRS_o_ai
+static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector signed int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
@@ -2506,7 +2506,7 @@
 vec_popcnt(vector unsigned int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
-static __inline__ vector signed long long __ATTRS_o_ai
+static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector signed long long __a) {
   return __builtin_altivec_vpopcntd(__a);
 }


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -2482,7 +2482,7 @@
 #ifdef __POWER8_VECTOR__
 /* vec_popcnt */
 
-static __inline__ vector signed char __ATTRS_o_ai
+static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector signed char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
@@ -2490,7 +2490,7 @@
 vec_popcnt(vector unsigned char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
-static __inline__ vector signed short __ATTRS_o_ai
+static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector signed short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
@@ -2498,7 +2498,7 @@
 vec_popcnt(vector unsigned short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
-static __inline__ vector signed int __ATTRS_o_ai
+static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector signed int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
@@ -2506,7 +2506,7 @@
 vec_popcnt(vector unsigned int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
-static __inline__ vector signed long long __ATTRS_o_ai
+static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector signed long long __a) {
   return __builtin_altivec_vpopcntd(__a);
 }
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[PATCH] D110428: [AIX] Define WCHAR_T_TYPE as unsigned short on AIX for wchar.c test case.

2021-10-06 Thread Amy Kwan via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG49dbde9c9e51: [AIX] Define WCHAR_T_TYPE as unsigned short on 
AIX for wchar.c test case. (authored by amyk).

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Files:
  clang/test/Sema/wchar.c


Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || (defined(_AIX) && !defined(__64BIT__))
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD 
non-NetBSD.


Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || (defined(_AIX) && !defined(__64BIT__))
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD non-NetBSD.
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[PATCH] D110428: [AIX] Define WCHAR_T_TYPE as unsigned short on AIX for wchar.c test case.

2021-10-02 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 376723.
amyk added a comment.

Addressed comment made by @daltenty.
Update the patch to account set the wchar type to `unsigned short` only on 
32-bit AIX.


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Files:
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Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || (defined(_AIX) && !defined(__64BIT__))
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD 
non-NetBSD.


Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || (defined(_AIX) && !defined(__64BIT__))
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD non-NetBSD.
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[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-10-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Ping.


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[PATCH] D110428: [AIX] Define WCHAR_T_TYPE as unsigned short on AIX for wchar.c test case.

2021-10-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Ping.


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[PATCH] D110935: [NFC] Update vec_extract builtin signatures to take signed int.

2021-10-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, stefanp.
amyk added projects: LLVM, PowerPC, clang.
amyk requested review of this revision.

This patch updates the vec_extract builtins to take a signed int as the second 
parameter, as defined by the Power Vector Intrinsics Programming Reference.
This patch is NFC and all existing tests pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110935

Files:
  clang/lib/Headers/altivec.h


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -13444,74 +13444,74 @@
 /* vec_extract */
 
 static __inline__ signed char __ATTRS_o_ai vec_extract(vector signed char __a,
-   unsigned int __b) {
+   signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai
-vec_extract(vector unsigned char __a, unsigned int __b) {
+vec_extract(vector unsigned char __a, signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai vec_extract(vector bool char __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ signed short __ATTRS_o_ai vec_extract(vector signed short 
__a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ unsigned short __ATTRS_o_ai
-vec_extract(vector unsigned short __a, unsigned int __b) {
+vec_extract(vector unsigned short __a, signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ unsigned short __ATTRS_o_ai vec_extract(vector bool short 
__a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x7];
 }
 
 static __inline__ signed int __ATTRS_o_ai vec_extract(vector signed int __a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x3];
 }
 
 static __inline__ unsigned int __ATTRS_o_ai vec_extract(vector unsigned int 
__a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x3];
 }
 
 static __inline__ unsigned int __ATTRS_o_ai vec_extract(vector bool int __a,
-unsigned int __b) {
+signed int __b) {
   return __a[__b & 0x3];
 }
 
 #ifdef __VSX__
 static __inline__ signed long long __ATTRS_o_ai
-vec_extract(vector signed long long __a, unsigned int __b) {
+vec_extract(vector signed long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ unsigned long long __ATTRS_o_ai
-vec_extract(vector unsigned long long __a, unsigned int __b) {
+vec_extract(vector unsigned long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ unsigned long long __ATTRS_o_ai
-vec_extract(vector bool long long __a, unsigned int __b) {
+vec_extract(vector bool long long __a, signed int __b) {
   return __a[__b & 0x1];
 }
 
 static __inline__ double __ATTRS_o_ai vec_extract(vector double __a,
-  unsigned int __b) {
+  signed int __b) {
   return __a[__b & 0x1];
 }
 #endif
 
 static __inline__ float __ATTRS_o_ai vec_extract(vector float __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0x3];
 }
 


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -13444,74 +13444,74 @@
 /* vec_extract */
 
 static __inline__ signed char __ATTRS_o_ai vec_extract(vector signed char __a,
-   unsigned int __b) {
+   signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai
-vec_extract(vector unsigned char __a, unsigned int __b) {
+vec_extract(vector unsigned char __a, signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__ unsigned char __ATTRS_o_ai vec_extract(vector bool char __a,
- unsigned int __b) {
+ signed int __b) {
   return __a[__b & 0xf];
 }
 
 static __inline__

[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

2021-10-01 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, stefanp.
amyk added projects: LLVM, PowerPC, clang.
amyk requested review of this revision.

This patch updates the vec_popcnt builtins to take a signed int as the second 
parameter, as defined by the Power Vector Intrinsics Programming Reference.
This patch is NFC and all existing tests pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110934

Files:
  clang/lib/Headers/altivec.h


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -2482,7 +2482,7 @@
 #ifdef __POWER8_VECTOR__
 /* vec_popcnt */
 
-static __inline__ vector signed char __ATTRS_o_ai
+static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector signed char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
@@ -2490,7 +2490,7 @@
 vec_popcnt(vector unsigned char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
-static __inline__ vector signed short __ATTRS_o_ai
+static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector signed short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
@@ -2498,7 +2498,7 @@
 vec_popcnt(vector unsigned short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
-static __inline__ vector signed int __ATTRS_o_ai
+static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector signed int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
@@ -2506,7 +2506,7 @@
 vec_popcnt(vector unsigned int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
-static __inline__ vector signed long long __ATTRS_o_ai
+static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector signed long long __a) {
   return __builtin_altivec_vpopcntd(__a);
 }


Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -2482,7 +2482,7 @@
 #ifdef __POWER8_VECTOR__
 /* vec_popcnt */
 
-static __inline__ vector signed char __ATTRS_o_ai
+static __inline__ vector unsigned char __ATTRS_o_ai
 vec_popcnt(vector signed char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
@@ -2490,7 +2490,7 @@
 vec_popcnt(vector unsigned char __a) {
   return __builtin_altivec_vpopcntb(__a);
 }
-static __inline__ vector signed short __ATTRS_o_ai
+static __inline__ vector unsigned short __ATTRS_o_ai
 vec_popcnt(vector signed short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
@@ -2498,7 +2498,7 @@
 vec_popcnt(vector unsigned short __a) {
   return __builtin_altivec_vpopcnth(__a);
 }
-static __inline__ vector signed int __ATTRS_o_ai
+static __inline__ vector unsigned int __ATTRS_o_ai
 vec_popcnt(vector signed int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
@@ -2506,7 +2506,7 @@
 vec_popcnt(vector unsigned int __a) {
   return __builtin_altivec_vpopcntw(__a);
 }
-static __inline__ vector signed long long __ATTRS_o_ai
+static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_popcnt(vector signed long long __a) {
   return __builtin_altivec_vpopcntd(__a);
 }
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Additional nits regarding comments.




Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:20
 ; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
 ; xscvdpsxws and uxws is only available on Power7 and above
 ; Codgen is different for LE Power7 and Power8





Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:21
 ; xscvdpsxws and uxws is only available on Power7 and above
 ; Codgen is different for LE Power7 and Power8
 




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[PATCH] D109178: [PowerPC] Disable vector types when not supported by subtarget features

2021-09-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

Overall LGTM.




Comment at: clang/test/CodeGen/builtins-ppc-int128.c:7
+// RUN:   -triple powerpc64le-unknown-unknown -target-cpu pwr8 \
+// RUN:   -emit-llvm %s -o - -U__XL_COMPAT_ALTIVEC__ | FileCheck %s 
-check-prefix=CHECK-LE
+#include 

nit: RUN line slightly too long.


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[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

2021-09-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Additional nit regarding the description and comment:

The signatures for the PowerPC builtins lharx and
lbarx are incorrect, and causes issues when in a function
that requiers the return of the builtin to be promoted.
This patch fixes these signatures.

Updated to:

The signatures for the PowerPC builtins lharx and
lbarx are incorrect, and causes issues when used in a function
that requires the return of the builtin to be promoted.
This patch fixes these signatures.




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:50
+
+// extra test cases that previously caused error during usage
+int test_lharx_intret(volatile short *a) {

nit: Capitalize the sentence and add a period. 


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[PATCH] D110431: Explicitly specify -fintegrated-as to clang/test/Driver/compilation_database.c test case.

2021-09-27 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f5b60ad47f1: Explicitly specify -fintegrated-as to 
clang/test/Driver/compilation_database.c… (authored by amyk).

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Files:
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Index: clang/test/Driver/compilation_database.c
===
--- clang/test/Driver/compilation_database.c
+++ clang/test/Driver/compilation_database.c
@@ -1,9 +1,9 @@
 // RUN: mkdir -p %t.workdir && cd %t.workdir
-// RUN: %clang -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - 
-no-canonical-prefixes 2>&1 | FileCheck %s
+// RUN: %clang -fintegrated-as -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s 
-Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
 // RUN: not %clang -c -x c %s -MJ %s/non-existant -no-canonical-prefixes 2>&1 
| FileCheck --check-prefix=ERROR %s
 
-// CHECK: { "directory": "{{[^"]*}}workdir",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", 
"[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
-// CHECK: { "directory": "{{.*}}",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", 
"[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{[^"]*}}workdir",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", 
"[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} 
"--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{.*}}",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", 
"[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} 
"--target={{[^"]+}}"]},
 // ERROR: error: compilation database '{{.*}}/non-existant' could not be 
opened:
 
 int main(void) {


Index: clang/test/Driver/compilation_database.c
===
--- clang/test/Driver/compilation_database.c
+++ clang/test/Driver/compilation_database.c
@@ -1,9 +1,9 @@
 // RUN: mkdir -p %t.workdir && cd %t.workdir
-// RUN: %clang -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
+// RUN: %clang -fintegrated-as -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
 // RUN: not %clang -c -x c %s -MJ %s/non-existant -no-canonical-prefixes 2>&1 | FileCheck --check-prefix=ERROR %s
 
-// CHECK: { "directory": "{{[^"]*}}workdir",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", "[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
-// CHECK: { "directory": "{{.*}}",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", "[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{[^"]*}}workdir",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", "[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{.*}}",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", "[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
 // ERROR: error: compilation database '{{.*}}/non-existant' could not be opened:
 
 int main(void) {
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[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-09-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk updated this revision to Diff 374990.
amyk edited the summary of this revision.
amyk added a comment.

Addressed Lei's review comments to output:

  error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'

when PC-Rel is specified pre-P10.

Also updated the comment for MMA on pre-P10 so it makes more sense and is more 
consistent with the comments I've added.


Repository:
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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-p10-features-support-check.c

Index: clang/test/Driver/ppc-p10-features-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-p10-features-support-check.c
@@ -0,0 +1,101 @@
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpaired-vector-memops %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPAIRED
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpaired-vector-memops %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPREFIXED
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpcrel %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL-PREFIX
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpcrel -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpcrel -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL-PREFIX
+
+int test_p10_features() {
+  return 0;
+}
+

[PATCH] D110431: Explicitly specify -fintegrated-as to clang/test/Driver/compilation_database.c test case.

2021-09-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: hubert.reinterpretcast, daltenty, sammccall.
amyk added a project: clang.
amyk requested review of this revision.

It appears that this test assumes that the toolchain utilizes the integrated 
assembler by default, 
since the expected output in the CHECKs are `compilation_database.o`.

However, this test fails on AIX as AIX does not utilize the integrated 
assembler. On AIX, the output
instead is of the form `/tmp/compilation_database-*.s`. Thus, this patch 
explicitly adds the 
`-fintegrated-as` option to match the assumption that the integrated assembler 
is used by default.


Repository:
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Files:
  clang/test/Driver/compilation_database.c


Index: clang/test/Driver/compilation_database.c
===
--- clang/test/Driver/compilation_database.c
+++ clang/test/Driver/compilation_database.c
@@ -1,9 +1,9 @@
 // RUN: mkdir -p %t.workdir && cd %t.workdir
-// RUN: %clang -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - 
-no-canonical-prefixes 2>&1 | FileCheck %s
+// RUN: %clang -fintegrated-as -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s 
-Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
 // RUN: not %clang -c -x c %s -MJ %s/non-existant -no-canonical-prefixes 2>&1 
| FileCheck --check-prefix=ERROR %s
 
-// CHECK: { "directory": "{{[^"]*}}workdir",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", 
"[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
-// CHECK: { "directory": "{{.*}}",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", 
"[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{[^"]*}}workdir",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", 
"[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} 
"--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{.*}}",  "file": 
"[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": 
"compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", 
"[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} 
"--target={{[^"]+}}"]},
 // ERROR: error: compilation database '{{.*}}/non-existant' could not be 
opened:
 
 int main(void) {


Index: clang/test/Driver/compilation_database.c
===
--- clang/test/Driver/compilation_database.c
+++ clang/test/Driver/compilation_database.c
@@ -1,9 +1,9 @@
 // RUN: mkdir -p %t.workdir && cd %t.workdir
-// RUN: %clang -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
+// RUN: %clang -fintegrated-as -MD -MP --sysroot=somewhere -c -x c %s -xc++ %s -Wall -MJ - -no-canonical-prefixes 2>&1 | FileCheck %s
 // RUN: not %clang -c -x c %s -MJ %s/non-existant -no-canonical-prefixes 2>&1 | FileCheck --check-prefix=ERROR %s
 
-// CHECK: { "directory": "{{[^"]*}}workdir",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", "[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
-// CHECK: { "directory": "{{.*}}",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", "[[SRC]]", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{[^"]*}}workdir",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc", "[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
+// CHECK: { "directory": "{{.*}}",  "file": "[[SRC:[^"]+[/|\\]compilation_database.c]]", "output": "compilation_database.o", "arguments": ["{{[^"]*}}clang{{[^"]*}}", "-xc++", "[[SRC]]", "-fintegrated-as", "--sysroot=somewhere", "-c", "-Wall",{{.*}} "--target={{[^"]+}}"]},
 // ERROR: error: compilation database '{{.*}}/non-existant' could not be opened:
 
 int main(void) {
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[PATCH] D110428: [AIX] Define WCHAR_T_TYPE as unsigned short on AIX for wchar.c test case.

2021-09-24 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: hubert.reinterpretcast, daltenty, thakis.
amyk added projects: clang, PowerPC.
amyk requested review of this revision.

The default wchar type is different on AIX vs. Linux. When this test is run on 
AIX,
WCHAR_T_TYPE ends up being set to `int`. This is incorrect as the default
wchar type on AIX is actually `unsigned short`, and setting the type 
incorrectly 
causes the expected errors to not be found.

This patch sets the type correctly (to `unsigned short`) for AIX.


Repository:
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Files:
  clang/test/Sema/wchar.c


Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || defined(_AIX)
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD 
non-NetBSD.


Index: clang/test/Sema/wchar.c
===
--- clang/test/Sema/wchar.c
+++ clang/test/Sema/wchar.c
@@ -4,7 +4,8 @@
 typedef __WCHAR_TYPE__ wchar_t;
 
 #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \
- || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR)
+ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) \
+ || defined(_AIX)
   #define WCHAR_T_TYPE unsigned short
 #elif defined(__aarch64__)
   // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD non-NetBSD.
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for addressing comments.


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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.

Thanks for updating the tests and description, Albion.


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[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.

LGTM as long as Lei's comment is addressed. Thanks Quinn!


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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2815
+def : Pat<(v4i32 (PPCSToV DblToUInt.A)),
+  (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;
 defm : ScalToVecWPermute<

This should be `XSCVDPUXWS`?



Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \

nit: Move this comment under the RUN lines.



Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:3
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE

I'm not sure why P8 is LE run only line, and P7 is BE run line only. 
Maybe we should have LE/BE run lines for both P7 and P8 for more coverage. 
Furthermore, if both the LE/BE checks end up the same, we can do `CHECK-P7` and 
`CHECK-P8`. 

Also, since this looks like it's a Linux test, please add 
`-ppc-asm-full-reg-names -ppc-vsr-nums-as-vr`.



Comment at: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll:16
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0

This is an unsigned test case, so should be `xscvdpuxws`, right?


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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c:13
+int testdarn_32(void) {
+  return __darn_32();
+}

Conanap wrote:
> amyk wrote:
> > lei wrote:
> > > Isn't this valid for both 32 and 64bit?
> > > Maybe change one of the run lines above to a 64bit test.
> > I agree. I thought __darn_32 is both 32-bit and 64-bit.
> It is indeed valid for both 32 bit and 64 bit; there is already a runline for 
> 64 bit in the `clang/test/CodeGen/builtins-ppc-xlcompat-darn.c` test case 
> (which includes `__darn_32`, which is why I didn't include it here.
You removed `__darn_32` from that file, so maybe we should add it back. And 
also, adjust the description of the patch to say that `__darn_32` is available 
for 32 and 64-bit.


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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c:13
+int testdarn_32(void) {
+  return __darn_32();
+}

lei wrote:
> Isn't this valid for both 32 and 64bit?
> Maybe change one of the run lines above to a 64bit test.
I agree. I thought __darn_32 is both 32-bit and 64-bit.


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[PATCH] D109710: [PowerPC] Add range checks for P10 Vector Builtins

2021-09-13 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

`builtins-ppc-p10vector.c` looks like it needs to be updated from the failing 
test case.




Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:1373
 vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: [[T0:%.+]]] = and %{{.+}}, i32 1
   // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}

Is the `i32` supposed to be on the first argument?


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[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

2021-09-13 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

A question I have is, I noticed there are some test case changes involving 
`xxspltidp` and `xxsplti32dx`, but are additional tests needed for `xxspltiw`?




Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1887
 
 // XXSPLI32DX needs extra flags to make sure the compiler does not attempt
 // to spill part of the instruction when the values are similar.

nit: Update this comment to include `xxspltiw` and `xxspltidp`.


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[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-09-11 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, stefanp.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, kbarton.
amyk requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch attempts to restrict the following P10 
 options:

  -mprefixed
  -mpcrel
  -mpaired-vector-memops

To P10  only. This will prevent the use of these 
options on P9  and earlier.

The behaviour of this patch looks like the following on pre-P10:

  $ clang -mcpu=pwr9 -mpaired-vector-memops test.c -o test
  error: option '-mpaired-vector-memops' cannot be specified without 
'-mcpu=pwr10'
  
  $ clang -mcpu=pwr9 -mprefixed test.c -o test
  error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
  
  $ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
  error: option '-mpcrel' cannot be specified without '-mprefixed'
  error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
  
  $ clang -mcpu=pwr9 -mpcrel test.c -o test
  error: option '-mpcrel' cannot be specified without '-mprefixed'


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-p10-features-support-check.c

Index: clang/test/Driver/ppc-p10-features-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-p10-features-support-check.c
@@ -0,0 +1,102 @@
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpaired-vector-memops %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPAIRED
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpaired-vector-memops %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpaired-vector-memops %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPAIRED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPREFIXED
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mprefixed %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPREFIXED
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpcrel %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr9 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr8 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mcpu=pwr7 -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN:   -mpcrel %s 2>&1 | FileCheck %s \
+// RUN:   --check-prefix=NOPCREL
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=pwr10 -mpcrel -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL-PREFIX
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm  \
+// RUN:   -mcpu=power10 -mpcrel -mprefixed %s -o - | FileCheck %s \
+// RUN:   --check-prefix=HASPCREL-PREFIX
+// RUN: not %clang

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

2021-08-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Please update the patch with full context.




Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1546
+  // into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg())) {
+return false;

nit: `uses a physical register`



Comment at: llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll:3
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 
-verify-machineinstrs | FileCheck %s
+target datalayout = 
"E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"

Are the  `target datalayout` and `target triple` necessary?


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[PATCH] D108702: [PowerPC][NFC] Rename P10 builtins vec_clrl, vec_clrr to vec_clr_first and vec_clr_last

2021-08-25 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.

We wanted `vec_clr_first` to translate to vclrrb for LE, and to vclrlb for BE, 
and the opposite mapping for `vec_clr_last`, so I think this LGTM.


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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-09 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux 
-mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux 
-mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE

nit: The RUN lines look a bit too long in this test.



Comment at: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll:21
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry

At a glance, it looks like `CHECK-64B-BE` and `CHECK-64B-AIX` looks like 
they're the same CHECKs.
Do you think it's a good idea to combine them into a single check/use 
check-prefixes? 


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[PATCH] D106959: [PowerPC] swdiv builtins for XL compatibility

2021-07-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1436
+
+def int_ppc_ftdivdp : Intrinsic<[llvm_i32_ty], [llvm_double_ty, 
llvm_double_ty], [IntrNoMem]>;
 }

Line too long?



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1724
+  Intrinsic<[llvm_double_ty], [llvm_double_ty, 
llvm_double_ty],
+  [IntrNoMem]>;
+  def int_ppc_swdivs : GCCBuiltin<"__builtin_ppc_swdivs">,

Minor indentation nit.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1727
+   Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty],
+   [IntrNoMem]>;
 }

Minor indentation nit.



Comment at: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:451
   TargetPassConfig::addIRPasses();
+
+  addPass(createPPCLowerCheckedFPArithPass());

Nit: Add a comment before creating the pass as the other pass calls also follow 
a comment.


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[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:35
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, 
ppc_fp128 %0, 0
+  // CHECK-NEXT: %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } 
%.fca.0.insert, ppc_fp128 %1, 1

I think it would probably be better not to hardcode the variable names in the 
tests.


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[PATCH] D106410: [PowerPC] Emit error for Altivec vector initializations when -faltivec-src-compat=gcc is specified

2021-07-30 Thread Amy Kwan via Phabricator via cfe-commits

amyk marked an inline comment as done.
amyk added a comment.

Addressed Nemanja's comment on the commit. 
https://reviews.llvm.org/rG5ea6117a9e9eae49ad1295fa422266ef3832e419


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[PATCH] D106410: [PowerPC] Emit error for Altivec vector initializations when -faltivec-src-compat=gcc is specified

2021-07-30 Thread Amy Kwan via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5ea6117a9e9e: [PowerPC] Emit error for Altivec vector 
initializations when -faltivec-src… (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D106410?vs=360312=363086#toc

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Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-bool-pixel-altivec-init-no-parentheses.c
  clang/test/CodeGen/vector-bool-pixel-altivec-init.c

Index: clang/test/CodeGen/vector-bool-pixel-altivec-init.c
===
--- clang/test/CodeGen/vector-bool-pixel-altivec-init.c
+++ clang/test/CodeGen/vector-bool-pixel-altivec-init.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
 // RUN:   -faltivec-src-compat=xl -triple powerpc64le-unknown-unknown -S \
 // RUN:   -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S \
+// RUN:   -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc64le-unknown-unknown -S \
+// RUN:   -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
 // RUN: %clang -mcpu=pwr8 -faltivec-src-compat=mixed --target=powerpc-unknown-unknown \
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=MIXED
 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=mixed --target=powerpc-unknown-unknown \
@@ -18,6 +24,10 @@
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown \
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
+// RUN: not %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown \
+// RUN:   -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
+// RUN: not %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown \
+// RUN:   -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
 
 // Vector bool type
 vector bool char vbi8_1;
@@ -41,6 +51,7 @@
   vbi8_1 = (vector bool char)('a');
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned char' (vector of 16 'unsigned char' values) and integer type 'unsigned char' of different size
   char c = 'c';
   vbi8_2 = (vector bool char)(c);
   // MIXED: [[INS:%.*]] = insertelement <16 x i8>
@@ -48,11 +59,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <16 x i8>
   // XL: [[SHUFF:%.*]] = shufflevector <16 x i8> [[INS_ELT]], <16 x i8> poison, <16 x i32> zeroinitializer
   // XL: store <16 x i8> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned char' (vector of 16 'unsigned char' values) and integer type 'unsigned char' of different size
 
   // vector bool short initialization
   vbi16_1 = (vector bool short)(5);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned short' (vector of 8 'unsigned short' values) and integer type 'unsigned short' of different size
   short si16 = 55;
   vbi16_2 = (vector bool short)(si16);
   // MIXED: [[INS:%.*]] = insertelement <8 x i16>
@@ -60,11 +73,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <8 x i16>
   // XL: [[SHUFF:%.*]] = shufflevector <8 x i16> [[INS_ELT]], <8 x i16> poison, <8 x i32> zeroinitializer
   // XL: store <8 x i16> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned short' (vector of 8 'unsigned short' values) and integer type 'unsigned short' of different size
 
   // vector bool int initialization
   vbi32_1 = (vector bool int)(9);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned int' (vector of 4 'unsigned int' values) and integer type 'unsigned int' of different size
   int si32 = 99;
   vbi32_2 = (vector bool int)(si32);
   // MIXED: [[INS:%.*]] = insertelement <4 x i32>
@@ -72,11 +87,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <4 x i32>
   // XL: [[SHUFF:%.*]] = shufflevector <4 x i32> [[INS_ELT]], <4 x i32> poison, <4 x i32> zeroinitializer
   // XL: store <4 x i32> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned int' (vector of 4 'unsigned int' values) and integer type 'unsigned int' of different size
 
   // vector bool long long initialization
   vbi64_1 = (vector bool long long)(13);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned long long' (vector of 2

[PATCH] D106410: [PowerPC] Emit error for Altivec vector initializations when -faltivec-src-compat=gcc is specified

2021-07-29 Thread Amy Kwan via Phabricator via cfe-commits

amyk added a comment.

Ping.


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[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

2021-07-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision as: amyk.
amyk added a comment.

LGTM.


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[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

2021-07-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk accepted this revision.
amyk added a comment.

Thanks for addressing the comment and adding back the tests! 
LGTM.


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[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

2021-07-26 Thread Amy Kwan via Phabricator via cfe-commits

amyk added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15111
+if (IsLE) {
+  Constant *Zero = llvm::Constant::getNullValue(ResTy);
+  SmallVector Consts;

Maybe we can pull out this line and do the following:
```
Constant *Zero = llvm::Constant::getNullValue(IsLE ? ResTy : 
AllElts->getType());
```



Comment at: clang/test/CodeGen/builtins-ppc-ld-st-rmb.c:1
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target

nemanjai wrote:
> The test case is quite verbose but the checks were produced by the script so 
> it should be easy to maintain. The reason I added so many checks is that the 
> produce code is very dependent on:
> - endianness
> - CPU
> - the number of bytes (in the store case)
The test is pretty verbose already, but do you think it is necessary to add 
checks for AIX, or is having just the Linux ones fine?


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[PATCH] D106410: [PowerPC] Emit error for Altivec vector initializations when -faltivec-src-compat=gcc is specified

2021-07-20 Thread Amy Kwan via Phabricator via cfe-commits

amyk created this revision.
amyk added reviewers: PowerPC, nemanjai, stefanp.
amyk added projects: PowerPC, LLVM, clang.
Herald added a subscriber: shchenz.
amyk requested review of this revision.

Under the `-faltivec-src-compat=gcc` option, AltiVec vector initialization 
should be treated
as if they were compiled with gcc - which is, to emit an error when the vectors 
are initialized
in the parenthesized or non-parenthesized manner. This patch implements this 
behaviour.


Repository:
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Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/CodeGen/vector-bool-pixel-altivec-init-no-parentheses.c
  clang/test/CodeGen/vector-bool-pixel-altivec-init.c

Index: clang/test/CodeGen/vector-bool-pixel-altivec-init.c
===
--- clang/test/CodeGen/vector-bool-pixel-altivec-init.c
+++ clang/test/CodeGen/vector-bool-pixel-altivec-init.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
 // RUN:   -faltivec-src-compat=xl -triple powerpc64le-unknown-unknown -S \
 // RUN:   -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -S \
+// RUN:   -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
+// RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -faltivec-src-compat=gcc -triple powerpc64le-unknown-unknown -S \
+// RUN:   -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
 // RUN: %clang -mcpu=pwr8 -faltivec-src-compat=mixed --target=powerpc-unknown-unknown \
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=MIXED
 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=mixed --target=powerpc-unknown-unknown \
@@ -18,6 +24,10 @@
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=xl --target=powerpc-unknown-unknown \
 // RUN:   -S -emit-llvm %s -o - | FileCheck %s --check-prefix=XL
+// RUN: not %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown \
+// RUN:   -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
+// RUN: not %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown \
+// RUN:   -S -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=GCC
 
 // Vector bool type
 vector bool char vbi8_1;
@@ -41,6 +51,7 @@
   vbi8_1 = (vector bool char)('a');
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned char' (vector of 16 'unsigned char' values) and integer type 'unsigned char' of different size
   char c = 'c';
   vbi8_2 = (vector bool char)(c);
   // MIXED: [[INS:%.*]] = insertelement <16 x i8>
@@ -48,11 +59,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <16 x i8>
   // XL: [[SHUFF:%.*]] = shufflevector <16 x i8> [[INS_ELT]], <16 x i8> poison, <16 x i32> zeroinitializer
   // XL: store <16 x i8> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned char' (vector of 16 'unsigned char' values) and integer type 'unsigned char' of different size
 
   // vector bool short initialization
   vbi16_1 = (vector bool short)(5);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned short' (vector of 8 'unsigned short' values) and integer type 'unsigned short' of different size
   short si16 = 55;
   vbi16_2 = (vector bool short)(si16);
   // MIXED: [[INS:%.*]] = insertelement <8 x i16>
@@ -60,11 +73,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <8 x i16>
   // XL: [[SHUFF:%.*]] = shufflevector <8 x i16> [[INS_ELT]], <8 x i16> poison, <8 x i32> zeroinitializer
   // XL: store <8 x i16> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned short' (vector of 8 'unsigned short' values) and integer type 'unsigned short' of different size
 
   // vector bool int initialization
   vbi32_1 = (vector bool int)(9);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned int' (vector of 4 'unsigned int' values) and integer type 'unsigned int' of different size
   int si32 = 99;
   vbi32_2 = (vector bool int)(si32);
   // MIXED: [[INS:%.*]] = insertelement <4 x i32>
@@ -72,11 +87,13 @@
   // XL: [[INS_ELT:%.*]] = insertelement <4 x i32>
   // XL: [[SHUFF:%.*]] = shufflevector <4 x i32> [[INS_ELT]], <4 x i32> poison, <4 x i32> zeroinitializer
   // XL: store <4 x i32> [[SHUFF]]
+  // GCC: error: invalid conversion between vector type '__vector __bool unsigned int' (vector of 4 'unsigned int' values) and integer type 'unsigned int' of different size
 
   // vector bool long long initialization
   vbi64_1 = (vector bool long long)(13);
   // MIXED: 
   // XL: 
+  // GCC: error: invalid conversion

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