Re: [edk2-devel] [PATCH v8 0/5] Cache Management Operations Support For RISC-V

[Sunil V L]

On Mon, Nov 06, 2023 at 08:23:51AM +0530, Dhaval wrote:
> Implementing code to support Cache Management Operations (CMO) defined by
> RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
> This is a re-write of original series v5.
> The patchset contains 5 patches- created based on V5 feedback.
> 1. Restructuring of existing code and move instruction declarations into 
> BaseLib
> 2. Renaming existing functions to denote type of instruction used to maanage 
> cache.
>This is useful for further patches where more cache management 
> instructions are added.
> 3. Add the new cache maintenance operations to BaseLib, including the
>new assembly instruction encodings.
> 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
> 5. Add platform level PCD to allow overriding of RISC-V features.
> 
> Code Link: https://github.com/tianocore/edk2/pull/5002
> 
> Cc: Ard Biesheuvel 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Gerd Hoffmann 
> Cc: Sunil V L 
> Cc: Andrei Warkentin 
> Cc: Laszlo Ersek 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: Daniel Schaefer 
> 
> Dhaval (5):
>   MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
>   MdePkg: Rename Cache Management Function To Clarify Fence Based Op
>   MdePkg: Implement RISC-V Cache Management Operations
>   MdePkg: Utilize Cache Management Operations Implementation For RISC-V
>   OvmfPkg/RiscVVirt: Override for RV CPU Features

If nobody objects,  I will merge this tomorrow  with or without ack from
MdePkg maintainers. The changes are related to RISC-V only anyway.

Thanks,
Sunil


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Re: [edk2-devel] [PATCH v2 09/30] UefiCpuPkg: Add LoongArch64 CPU Timer library

[Chao Li]

Hi Ray,

Could you please continue to review this patch set? You have Acked the 
patch 13, and patches 9, 10, 11, 12 and 14 placed the UefiCpuPkg. Note 
the patches 11 and 12 is the memory management library, these two 
patches are provide a method for the publicMmuLib, the other patches are 
LoongArch specific.



Thanks,
Chao
在 2023/11/6 11:28, Chao Li 写道:

Add the LoongArch64 CPU Timer library, using CPUCFG 0x4 and 0x5 for
Stable Counter frequency.

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
  .../BaseLoongArch64CpuTimerLib.inf|  30 +++
  .../BaseLoongArch64CpuTimerLib.uni|  15 ++
  .../BaseLoongArch64CpuTimerLib/CpuTimerLib.c  | 226 ++
  UefiCpuPkg/UefiCpuPkg.dsc |   3 +
  4 files changed, 274 insertions(+)
  create mode 100644 
UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
  create mode 100644 
UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
  create mode 100644 UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c

diff --git 
a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
new file mode 100644
index 00..c00c215aec
--- /dev/null
+++ 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.inf
@@ -0,0 +1,30 @@
+## @file
+#  Base CPU Timer Library
+#
+#  Provides base timer support using CPUCFG 0x4 and 0x5 stable counter 
frequency.
+#
+#  Copyright (c) 2023, Loongson Technology Corporation Limited. All rights 
reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION   = 0x00010005
+  BASE_NAME = BaseLoongArch64CpuTimerLib
+  FILE_GUID = 740389C7-CC44-4A2F-88DC-89D97D312E7C
+  MODULE_TYPE   = BASE
+  VERSION_STRING= 1.0
+  LIBRARY_CLASS = TimerLib
+  MODULE_UNI_FILE   = BaseLoongArch64CpuTimerLib.uni
+
+[Sources.common]
+  CpuTimerLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  DebugLib
diff --git 
a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
new file mode 100644
index 00..72d38ec679
--- /dev/null
+++ 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTimerLib.uni
@@ -0,0 +1,15 @@
+// /** @file
+// Base CPU Timer Library
+//
+// Provides base timer support using CPUCFG 0x4 and 0x5 stable counter 
frequency.
+//
+// Copyright (c) 2023, Loongson Technology Corporation Limited. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "LOONGARCH CPU Timer 
Library"
+
+#string STR_MODULE_DESCRIPTION  #language en-US "Provides basic timer 
support using CPUCFG 0x4 and 0x5 stable counter frequency."
diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c 
b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c
new file mode 100644
index 00..349b881cbc
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c
@@ -0,0 +1,226 @@
+/** @file
+  CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Library.
+
+  Copyright (c) 2023, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Calculate clock frequency using CPUCFG 0x4 and 0x5 registers.
+
+  @param  VOID.
+
+  @return The frequency in Hz.
+
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+  VOID
+  )
+{
+  UINT32 BaseFreq;
+  UINT32 ClockMultiplier;
+  UINT32 ClockDivide;
+  CPUCFG_REG4_INFO_DATA  CCFreq;
+  CPUCFG_REG5_INFO_DATA  CpucfgReg5Data;
+  UINT32 StableTimerFreq;
+
+  //
+  // Get the the crystal frequency corresponding to the constant
+  // frequency timer and the clock used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG4_INFO, );
+
+  //
+  // Get the multiplication factor and frequency division factor
+  // corresponding to the constant frequency timer and the clock
+  // used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG5_INFO, );
+
+  BaseFreq= CCFreq.Bits.CC_FREQ;
+  ClockMultiplier = CpucfgReg5Data.Bits.CC_MUL & 0xULL;
+  ClockDivide = CpucfgReg5Data.Bits.CC_DIV & 0xULL;
+
+  if (!BaseFreq || !ClockMultiplier || !ClockDivide) {
+DEBUG ((DEBUG_ERROR, "LoongArch Stable Timer is not available in the CPU, hence 
this library cannot be used.\n"));
+StableTimerFreq = 0;
+ASSERT (0);
+  } else {
+StableTimerFreq = (BaseFreq * 

[edk2-devel] [PATCH v2 2/2] FatPkg/EnhancedFatDxe: Fix OVERFLOW_BEFORE_WIDEN Coverity issue

[Ranbir Singh]

From: Ranbir Singh 

The function FatInitializeDiskCache evaluates an expression

FAT_DATACACHE_GROUP_COUNT << DiskCache[CacheData].PageAlignment

and assigns it to DataCacheSize which is of type UINTN.

As per Coverity report,
FAT_DATACACHE_GROUP_COUNT << DiskCache[CacheData].PageAlignment is a
potentially overflowing expression with type "int" (32 bits, signed)
evaluated using 32-bit arithmetic, and then used in a context that
expects an expression of type "UINTN" (64 bits, unsigned).

To avoid overflow, cast "FAT_DATACACHE_GROUP_COUNT" to type "UINTN".

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4249

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 FatPkg/EnhancedFatDxe/DiskCache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FatPkg/EnhancedFatDxe/DiskCache.c 
b/FatPkg/EnhancedFatDxe/DiskCache.c
index d1a34a6a646f..d56e338586d8 100644
--- a/FatPkg/EnhancedFatDxe/DiskCache.c
+++ b/FatPkg/EnhancedFatDxe/DiskCache.c
@@ -477,7 +477,7 @@ FatInitializeDiskCache (
   DiskCache[CacheFat].BaseAddress   = Volume->FatPos;
   DiskCache[CacheFat].LimitAddress  = Volume->FatPos + Volume->FatSize;
   FatCacheSize  = FatCacheGroupCount << 
DiskCache[CacheFat].PageAlignment;
-  DataCacheSize = FAT_DATACACHE_GROUP_COUNT << 
DiskCache[CacheData].PageAlignment;
+  DataCacheSize = (UINTN)FAT_DATACACHE_GROUP_COUNT << 
DiskCache[CacheData].PageAlignment;
   //
   // Allocate the Fat Cache buffer
   //
-- 
2.34.1



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[edk2-devel] [PATCH v2 1/2] FatPkg/EnhancedFatDxe: Fix SIGN_EXTENSION Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The functions FatGetDirEntInfo and FatOpenDirEnt contains the code
statements

  Cluster= (Entry->FileClusterHigh << 16) | Entry->FileCluster;
  and
  OFile->FileCluster = ((DirEnt->Entry.FileClusterHigh) << 16) | 
(DirEnt->Entry.FileCluster);

respectively. As per Coverity report, in both these statements, there is
an "Operand1" with type "UINT16" (16 bits, unsigned) which is promoted in
"(Operand1 << 16) | Operand2" to type "int" (32 bits, signed), then sign-
extended to type "unsigned long long" (64 bits, unsigned). If the result
of "(Operand1 << 16) | Operand2" is greater than 0x7FFF, the upper
bits of the result will all be 1.

So to avoid sign-extension, typecast the Operand1 and then the inter-
-mediate result after << 16 operation with UINTN. Note - UINTN is the
data type of the variable on the LHS of the assignment.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4249

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 FatPkg/EnhancedFatDxe/DirectoryManage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/FatPkg/EnhancedFatDxe/DirectoryManage.c 
b/FatPkg/EnhancedFatDxe/DirectoryManage.c
index 723fc35f38db..a21b7973cd21 100644
--- a/FatPkg/EnhancedFatDxe/DirectoryManage.c
+++ b/FatPkg/EnhancedFatDxe/DirectoryManage.c
@@ -474,7 +474,7 @@ FatGetDirEntInfo (
 Info   = Buffer;
 Info->Size = ResultSize;
 if ((Entry->Attributes & FAT_ATTRIBUTE_DIRECTORY) != 0) {
-  Cluster= (Entry->FileClusterHigh << 16) | Entry->FileCluster;
+  Cluster= (UINTN)((UINTN)(Entry->FileClusterHigh) << 16) | 
Entry->FileCluster;
   Info->PhysicalSize = FatPhysicalDirSize (Volume, Cluster);
   Info->FileSize = Info->PhysicalSize;
 } else {
@@ -1167,7 +1167,7 @@ FatOpenDirEnt (
   //
   Volume = Parent->Volume;
   OFile->FullPathLen = Parent->FullPathLen + 1 + StrLen 
(DirEnt->FileString);
-  OFile->FileCluster = ((DirEnt->Entry.FileClusterHigh) << 16) | 
(DirEnt->Entry.FileCluster);
+  OFile->FileCluster = (UINTN)((UINTN)(DirEnt->Entry.FileClusterHigh) << 
16) | (DirEnt->Entry.FileCluster);
   InsertTailList (>ChildHead, >ChildLink);
 } else {
   //
-- 
2.34.1



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[edk2-devel] [PATCH v2 0/2] BZ 4249: Fix FatPkg/EnhancedFatDxe issues pointed by Coverity

[Ranbir Singh]

v1 -> v2:
  - Rebased to latest master HEAD

Ranbir Singh (2):
  FatPkg/EnhancedFatDxe: Fix SIGN_EXTENSION Coverity issues
  FatPkg/EnhancedFatDxe: Fix OVERFLOW_BEFORE_WIDEN Coverity issue

 FatPkg/EnhancedFatDxe/DirectoryManage.c | 4 ++--
 FatPkg/EnhancedFatDxe/DiskCache.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.34.1



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[edk2-devel] [PATCH v2 5/5] MdeModulePkg/Bus/Pci/PciBusDxe: Fix UNUSED_VALUE Coverity issues

[Ranbir Singh]

The return value after calls to functions
gBS->UninstallMultipleProtocolInterfaces, StartPciDevicesOnBridge,
PciPciDeviceInfoCollector, BarExisted, PciRootBridgeIo->Pci.Write,
gPciHotPlugInit->InitializeRootHpc and PciRootBridgeP2CProcess is
stored in Status, but it is not made of any use and later Status
gets overridden.

Remove the return value storage in Status or add Status check as
seems appropriate at a particular point.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4239

Cc: Ray Ni 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 68 +++-
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 42 
 MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c   |  8 +++
 3 files changed, 72 insertions(+), 46 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 3de80d98370e..9b0587c94d05 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -544,12 +544,12 @@ DeRegisterPciDevice (
   EFI_OPEN_PROTOCOL_TEST_PROTOCOL
   );
   if (!EFI_ERROR (Status)) {
-Status = gBS->UninstallMultipleProtocolInterfaces (
-Handle,
-,
->LoadFile2,
-NULL
-);
+gBS->UninstallMultipleProtocolInterfaces (
+   Handle,
+   ,
+   >LoadFile2,
+   NULL
+   );
   }
 
   //
@@ -678,19 +678,21 @@ StartPciDevicesOnBridge (
ChildHandleBuffer
);
 
-PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationSupported,
- 0,
- 
- );
-Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
-PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+if (!EFI_ERROR (Status)) {
+  PciIoDevice->PciIo.Attributes (
+   &(PciIoDevice->PciIo),
+   EfiPciIoAttributeOperationSupported,
+   0,
+   
+   );
+  Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
+  PciIoDevice->PciIo.Attributes (
+   &(PciIoDevice->PciIo),
+   EfiPciIoAttributeOperationEnable,
+   Supports,
+   NULL
+   );
+}
 
 return Status;
   } else {
@@ -726,19 +728,21 @@ StartPciDevicesOnBridge (
ChildHandleBuffer
);
 
-PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationSupported,
- 0,
- 
- );
-Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
-PciIoDevice->PciIo.Attributes (
- &(PciIoDevice->PciIo),
- EfiPciIoAttributeOperationEnable,
- Supports,
- NULL
- );
+if (!EFI_ERROR (Status)) {
+  PciIoDevice->PciIo.Attributes (
+   &(PciIoDevice->PciIo),
+   EfiPciIoAttributeOperationSupported,
+   0,
+   
+   );
+  Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
+  PciIoDevice->PciIo.Attributes (
+   &(PciIoDevice->PciIo),
+   EfiPciIoAttributeOperationEnable,
+   Supports,
+   NULL
+   );
+}
   }
 
   CurrentLink = CurrentLink->ForwardLink;
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index eda97285ee18..636885dd189d 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -2796,6 +2796,20 @@ IsPciDeviceRejected (
   // Test its high 32-Bit BAR
   //
   Status = BarExisted (PciIoDevice, BarOffset, , );
+  if (EFI_ERROR (Status)) {
+//
+// Not sure if it is correct to skip the below if (TestValue == 
OldValue) check in 

[edk2-devel] [PATCH v2 4/5] MdeModulePkg/Bus/Pci/PciBusDxe: Fix NULL_RETURNS Coverity issue

[Ranbir Singh]

From: Ranbir Singh 

The function StartPciDevices has a check

ASSERT (RootBridge != NULL);

but this comes into play only in DEBUG mode. In Release mode, there
is no handling if the RootBridge value is NULL and the code proceeds
to unconditionally dereference "RootBridge" which will lead to CRASH.

Hence, for safety add NULL pointer checks always and return
EFI_NOT_READY if RootBridge value is NULL which is one of the return
values as mentioned in the function description header.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4239

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 581e9075ad41..3de80d98370e 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -772,7 +772,10 @@ StartPciDevices (
   LIST_ENTRY *CurrentLink;
 
   RootBridge = GetRootBridgeByHandle (Controller);
-  ASSERT (RootBridge != NULL);
+  if (RootBridge == NULL) {
+return EFI_NOT_READY;
+  }
+
   ThisHostBridge = RootBridge->PciRootBridgeIo->ParentHandle;
 
   CurrentLink = mPciDevicePool.ForwardLink;
-- 
2.34.1



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[edk2-devel] [PATCH v2 3/5] MdeModulePkg/Bus/Pci/PciBusDxe: Fix ARRAY_VS_SINGLETON Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The function PciHostBridgeResourceAllocator is not making use of the
generic approach as is used in one of the other function namely -
DumpResourceMap. As a result, the following warnings can be seen as
reported by Coverity e.g.

(30) Event address_of:  Taking address with "" yields a
 singleton pointer.
(31) Event callee_ptr_arith:Passing "" to function
 "FindResourceNode" which uses it as an array. This might corrupt
 or misinterpret adjacent memory locations.

Hence, adopt the generic approach to fix the issues at relevant points.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4239

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 37 
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index 84fc0161a19c..71767d3793d4 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -485,6 +485,8 @@ PciHostBridgeResourceAllocator (
   UINT64 Mem64ResStatus;
   UINT64 PMem64ResStatus;
   UINT32 MaxOptionRomSize;
+  PCI_RESOURCE_NODE  **ChildResources;
+  UINTN  ChildResourceCount;
   PCI_RESOURCE_NODE  *IoBridge;
   PCI_RESOURCE_NODE  *Mem32Bridge;
   PCI_RESOURCE_NODE  *PMem32Bridge;
@@ -895,16 +897,39 @@ PciHostBridgeResourceAllocator (
 // Create the entire system resource map from the information collected by
 // enumerator. Several resource tree was created
 //
-FindResourceNode (RootBridgeDev, , );
-FindResourceNode (RootBridgeDev, , );
-FindResourceNode (RootBridgeDev, , );
-FindResourceNode (RootBridgeDev, , );
-FindResourceNode (RootBridgeDev, , );
-
+ChildResourceCount = FindResourceNode (RootBridgeDev, , NULL);
+ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * 
ChildResourceCount);
+ASSERT (ChildResources != NULL);
+FindResourceNode (RootBridgeDev, , [0]);
+IoBridge = ChildResources[0];
 ASSERT (IoBridge != NULL);
+
+ChildResourceCount = FindResourceNode (RootBridgeDev, , NULL);
+ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * 
ChildResourceCount);
+ASSERT (ChildResources != NULL);
+FindResourceNode (RootBridgeDev, , [0]);
+Mem32Bridge = ChildResources[0];
 ASSERT (Mem32Bridge  != NULL);
+
+ChildResourceCount = FindResourceNode (RootBridgeDev, , NULL);
+ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * 
ChildResourceCount);
+ASSERT (ChildResources != NULL);
+FindResourceNode (RootBridgeDev, , [0]);
+PMem32Bridge = ChildResources[0];
 ASSERT (PMem32Bridge != NULL);
+
+ChildResourceCount = FindResourceNode (RootBridgeDev, , NULL);
+ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * 
ChildResourceCount);
+ASSERT (ChildResources != NULL);
+FindResourceNode (RootBridgeDev, , [0]);
+Mem64Bridge = ChildResources[0];
 ASSERT (Mem64Bridge  != NULL);
+
+ChildResourceCount = FindResourceNode (RootBridgeDev, , NULL);
+ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * 
ChildResourceCount);
+ASSERT (ChildResources != NULL);
+FindResourceNode (RootBridgeDev, , [0]);
+PMem64Bridge = ChildResources[0];
 ASSERT (PMem64Bridge != NULL);
 
 //
-- 
2.34.1



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[edk2-devel] [PATCH v2 2/5] MdeModulePkg/Bus/Pci/PciBusDxe: Fix MISSING_BREAK Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The function UpdatePciInfo has switch-case code in which there are fall
through from case 32: to case 64:. While this is seeemingly intentional,
it is not evident to any general code reader why there is no break; in
between. Adding

// No break; here as this is an intentional fallthrough.

as comment in between makes it explicit. Incidentally, the comment
satisfies Coverity as well.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4239

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 6594b8eae83f..eda97285ee18 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -1428,6 +1428,9 @@ UpdatePciInfo (
   switch (Ptr->AddrSpaceGranularity) {
 case 32:
   PciIoDevice->PciBar[BarIndex].BarType = PciBarTypeMem32;
+  //
+  // No break; here as this is an intentional fall through.
+  //
 case 64:
   PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
   break;
@@ -1440,6 +1443,9 @@ UpdatePciInfo (
   switch (Ptr->AddrSpaceGranularity) {
 case 32:
   PciIoDevice->PciBar[BarIndex].BarType = PciBarTypePMem32;
+  //
+  // No break; here as this is an intentional fall through.
+  //
 case 64:
   PciIoDevice->PciBar[BarIndex].BarTypeFixed = TRUE;
   break;
-- 
2.34.1



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[edk2-devel] [PATCH v2 1/5] MdeModulePkg/Bus/Pci/PciBusDxe: Fix DEADCODE Coverity issue

[Ranbir Singh]

From: Ranbir Singh 

The function PciHotPlugRequestNotify has two if blocks towards the end
of function both containing return. Due to the parameter checks ensured
at the beginning of the function, one of the two if blocks is bound to
come in execution flow. Hence, the return EFI_SUCCESS; at line 2112 is
redundant/deadcode.

To fix it, either of line 2109 or 2112 can be deleted.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4239

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
index 3f8c6e6da7dc..5b71e152f3ea 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
@@ -2106,7 +2106,6 @@ PciHotPlugRequestNotify (
 //
 // End for
 //
-return EFI_SUCCESS;
   }
 
   return EFI_SUCCESS;
-- 
2.34.1



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[edk2-devel] [PATCH v2 0/5] BZ 4239: Fix MdeModulePkg/Bus/Pci/PciBusDxe issues pointed by Coverity

[Ranbir Singh]

v1 -> v2:
  - Rebased to latest master HEAD
  - Updated Cc list
  - Updated the commit message wrt MISSING_BREAK issues
  - Removed the ASSERT wrt NULL_RETURNS issue

Ranbir Singh (5):
  MdeModulePkg/Bus/Pci/PciBusDxe: Fix DEADCODE Coverity issue
  MdeModulePkg/Bus/Pci/PciBusDxe: Fix MISSING_BREAK Coverity issues
  MdeModulePkg/Bus/Pci/PciBusDxe: Fix ARRAY_VS_SINGLETON Coverity issues
  MdeModulePkg/Bus/Pci/PciBusDxe: Fix NULL_RETURNS Coverity issue
  MdeModulePkg/Bus/Pci/PciBusDxe: Fix UNUSED_VALUE Coverity issues

 MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 73 +++-
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c|  1 -
 MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 48 +
 MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c   | 45 ++--
 4 files changed, 113 insertions(+), 54 deletions(-)

-- 
2.34.1



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[edk2-devel] [PATCH v2 2/2] MdeModulePkg/Bus/Pci/XhciDxe: Fix MISSING_BREAK Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The functions
XhcInitializeEndpointContext and XhcInitializeEndpointContext64 has
a switch-case code in which the case USB_ENDPOINT_CONTROL: falls
through to default:

While this may be intentional, it is not evident to any general code
reader why there is no break; in between. Adding

// No break; here as this is an intentional fallthrough.

as comment in between makes it explicit. Incidentally, the comment
satisfies Coverity as well.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4221

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c 
b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 05528a478baf..2afecd40cab0 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2979,6 +2979,9 @@ XhcInitializeEndpointContext (
 // Do not support control transfer now.
 //
 DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unsupport Control 
EP found, Transfer ring is not allocated.\n"));
+//
+// No break; here as this is an intentional fall through.
+//
   default:
 DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext: Unknown EP found, 
Transfer ring is not allocated.\n"));
 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
@@ -3182,6 +3185,9 @@ XhcInitializeEndpointContext64 (
 // Do not support control transfer now.
 //
 DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unsupport Control 
EP found, Transfer ring is not allocated.\n"));
+//
+// No break; here as this is an intentional fall through.
+//
   default:
 DEBUG ((DEBUG_INFO, "XhcInitializeEndpointContext64: Unknown EP found, 
Transfer ring is not allocated.\n"));
 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
-- 
2.34.1



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[edk2-devel] [PATCH v2 1/2] MdeModulePkg/Bus/Pci/XhciDxe: Fix FORWARD_NULL Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The functions UsbHcGetHostAddrForPciAddr, UsbHcGetPciAddrForHostAddr
and UsbHcFreeMem do have

ASSERT ((Block != NULL));

statements after for loop, but these are applicable only in DEBUG mode.
In RELEASE mode, if for whatever reasons there is no match inside for
loop and the loop exits because of Block != NULL; condition, then there
is no "Block" NULL pointer check afterwards and the code proceeds to do
dereferencing "Block" which will lead to CRASH.

Hence, for safety add NULL pointer checks always.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4221

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c 
b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
index b54187ec228e..b0654f148c4f 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
@@ -267,6 +267,11 @@ UsbHcGetPciAddrForHostAddr (
   }
 
   ASSERT ((Block != NULL));
+
+  if (Block == NULL) {
+return 0;
+  }
+
   //
   // calculate the pci memory address for host memory address.
   //
@@ -322,6 +327,11 @@ UsbHcGetHostAddrForPciAddr (
   }
 
   ASSERT ((Block != NULL));
+
+  if (Block == NULL) {
+return 0;
+  }
+
   //
   // calculate the pci memory address for host memory address.
   //
@@ -603,6 +613,10 @@ UsbHcFreeMem (
   //
   ASSERT (Block != NULL);
 
+  if (Block == NULL) {
+return;
+  }
+
   //
   // Release the current memory block if it is empty and not the head
   //
-- 
2.34.1



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[edk2-devel] [PATCH v2 0/2] BZ 4221: Fix MdeModulePkg/Bus/Pci/XhciDxe issues pointed by Coverity

[Ranbir Singh]

v1 -> v2:
  - Rebased to latest master HEAD
  - Updated Cc list
  - Updated the commit message wrt MISSING_BREAK issues

Ranbir Singh (2):
  MdeModulePkg/Bus/Pci/XhciDxe: Fix FORWARD_NULL Coverity issues
  MdeModulePkg/Bus/Pci/XhciDxe: Fix MISSING_BREAK Coverity issues

 MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c  | 14 ++
 MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c |  6 ++
 2 files changed, 20 insertions(+)

-- 
2.34.1



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Re: [edk2-devel] [PATCH v5 1/1] MdePkg: Add Cxl20.h into IndustryStandard

[Huang, Yanbo]

Hi Chris,

It seems the mode of cxl.h change from 100644 to 100755, is this change 
expected?

Best Regards,
Yanbo Huang

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Chris Li OS via 
groups.io
Sent: Thursday, October 26, 2023 3:10 PM
To: devel@edk2.groups.io; Kinney, Michael D ; Nong, 
Foster ; Gao, Liming 
Cc: Yao, Jiewen ; Ni, Ray 
Subject: Re: [edk2-devel] [PATCH v5 1/1] MdePkg: Add Cxl20.h into 
IndustryStandard

Thanks a lot Liming!


From: devel@edk2.groups.io  on behalf of gaoliming via 
groups.io 
Sent: Thursday, October 26, 2023 8:56 AM
To: devel@edk2.groups.io; Chris Li OS; 'Kinney, Michael D'; 'Nong, Foster'
Cc: 'Yao, Jiewen'; 'Ni, Ray'; Open Source Submission
Subject: 回复: [ ** SPAMMAIL ** ][edk2-devel] [PATCH v5 1/1] MdePkg: Add Cxl20.h 
into IndustryStandard

Chris:
  I just add push label for this PR
https://github.com/tianocore/edk2/pull/4932.

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Chris Li OS via 
> groups.io
> 发送时间: 2023年10月20日 17:22
> 收件人: devel@edk2.groups.io; 'Kinney, Michael D'
> ; 'Nong, Foster' ; 
> gaolim...@byosoft.com.cn
> 抄送: 'Yao, Jiewen' ; 'Ni, Ray' 
> ; Open Source Submission 
> 
> 主题: [ ** SPAMMAIL ** ][edk2-devel] [PATCH v5 1/1] MdePkg: Add Cxl20.h 
> into IndustryStandard
>
> @Liming,
>
> The CI looks good (see https://github.com/tianocore/edk2/pull/4932), 
> and this v5 patch only contains space adjustment compared with v4 to 
> make CI happy.
> Kindly help merge this patch. Thanks a lot!
>
>

--
>
> 1) Add CXL 2.0 header file to comply with CXL 2.0 specification
> 2) CXL 2.0 header will embed Cxl11.h
> 3) Updated Cxl.h to point to 2.0 header file
>
> Signed-off-by: Chris Li 
> Reviewed-by: Liming Gao 
> Cc: Ray Ni 
> Cc: Yao, Jiewen 
> Cc: Nong, Foster 
> Cc: Kinney, Michael D 
> ---
>  MdePkg/Include/IndustryStandard/Cxl.h   |   2 +-
>  MdePkg/Include/IndustryStandard/Cxl20.h | 463
> 
>  2 files changed, 464 insertions(+), 1 deletion(-)  mode change 100644 
> => 100755 MdePkg/Include/IndustryStandard/Cxl.h
>  create mode 100755 MdePkg/Include/IndustryStandard/Cxl20.h
>
> diff --git a/MdePkg/Include/IndustryStandard/Cxl.h
> b/MdePkg/Include/IndustryStandard/Cxl.h
> old mode 100644
> new mode 100755
> index 06c1230e3e..9ad3242e25
> --- a/MdePkg/Include/IndustryStandard/Cxl.h
> +++ b/MdePkg/Include/IndustryStandard/Cxl.h
> @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent  
> #ifndef _CXL_MAIN_H_  #define _CXL_MAIN_H_
>
> -#include 
> +#include 
>  //
>  // CXL assigned new Vendor ID
>  //
> diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h
> b/MdePkg/Include/IndustryStandard/Cxl20.h
> new file mode 100755
> index 00..574f786881
> --- /dev/null
> +++ b/MdePkg/Include/IndustryStandard/Cxl20.h
> @@ -0,0 +1,463 @@
> +/** @file
> +  CXL 2.0 Register definitions
> +
> +  This file contains the register definitions based on the Compute
Express
> Link
> +  (CXL) Specification Revision 2.0.
> +
> +  Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef CXL20_H_
> +#define CXL20_H_
> +
> +#include 
> +
> +//
> +// CXL DVSEC IDs
> +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 //
> +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE 0x0
> +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP  0x2
> +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS  0x3
> +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS   0x4
> +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES 0x5
> +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT  0x7
> +#define CXL_DVSEC_ID_REGISTER_LOCATOR  0x8
> +#define CXL_DVSEC_ID_MLD   0x9
> +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY0xA
> +
> +//
> +// Register Block ID
> +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 
> +//
> +#define CXL_REGISTER_BLOCK_ID_EMPTY   0x0
> +#define CXL_REGISTER_BLOCK_ID_COMPONENT   0x1
> +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL  0x2
> +#define CXL_REGISTER_BLOCK_ID_DEVICE  0x3
> +
> +//
> +// CXL component register layout
> +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 // 
> +// ||
> +// |- Range & Type -| // 
> +|| IO Base - 0KB
> +// | (0KB - 4KB)IO Regs |
> +// || Cache and Mem Base - 4KB
> +// | {4KB - 8KB)Cache & Mem Regs|
> +// || Implementation Spec Regs 
> +Base -
8KB
> +// | (8KB - 56KB)Implement Spec Regs|
> +// || ARB/Mux Regs Base - 56KB
> +// | (56KB - 57KB)ARBMUX Regs   |
> +// 

Re: [edk2-devel] [PATCH v1] OvmfPkg/PlatformInitLib: Don't override user specified PciMmio64Size

[Vivek Kasireddy]

Hi Gerd,

> 
>   Hi,
> 
> > > I agree that the proposed patch can function as a stop-gap, but the QEMU
> > > command line hack is already a stop-gap. And for the long term, this
> > > patch is not good enough. We should enhance the dynamic sizing, now
> that
> > > Gerd has put it into place.
> >
> > ... I do agree however that the current behavior is strange -- the user
> > specifies an explicit fw_cfg knob for OVMF, and OVMF ignores it (for
> > whatever reason).
> >
> > I'd like to know what Gerd thinks of this.
> 
> The current code effectively considers the user-specified PciMmio64Size
> as a lower limit, it will never be smaller but might be larger in case
> OVMF figures it has enough space.
> 
> Being more strict here and use the user-specified PciMmio64Size as-is no
> matter what is fine with me.
> 
> The independent but related question is where the window should be
> placed in case we have a valid vcpu address space size and PciMmio64Size
> specified by the user.
> 
> > (b) there were a promise to enhance QEMU and OVMF as I suggest above.
> 
> Fully agree.  We should explicitly communicate requirements (in this
> case: iommu address space size) instead of depending on side effects
> of unrelated config options.
> 
> Strictly speaking you don't care that much about the size of the mmio
> window, but where it gets placed.  Moving it to the end of the vcpu
> address space is what breaks your use case in case the iommu address
> space happens to be too small for that.
Right, the crux of the problem is indeed the placement of the window
and not the size. Given this, do you see any problem if the mmio window
were to be placed at the lower end of the address space? Or, do you think
ensuring that PhysMemAddressWidth = 
automatically via Qemu/OVMF like Laszlo suggested is a better solution
for this problem?

Thanks,
Vivek

> 
> take care,
>   Gerd



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[edk2-devel] [PATCH v3 2/2] MdeModulePkg/Bus/Usb/UsbMouseDxe: Fix MISSING_BREAK Coverity issues

[Ranbir Singh]

The function GetNextHidItem has a switch-case block in which the case 1:
falls through to case 2: and then case 2: falls through to case 3:.

There is no possibility of the if blocks within case 2: and case 3: to
succeed later and not succeed in the original case and hence the fall
throughs even if it hypothetically happens are redundant as the code
still will eventually return NULL only at the function end point.

Better introduce straight forward break; statement within actual cases.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4222

Cc: Ray Ni 
Signed-off-by: Ranbir Singh 
Reviewed-by: Laszlo Ersek 
---
 MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c 
b/MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c
index acc19acd98e0..f07e48774a34 100644
--- a/MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c
+++ b/MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c
@@ -89,6 +89,8 @@ GetNextHidItem (
   return StartPos;
 }
 
+break;
+
   case 2:
 //
 // 2-byte data
@@ -99,6 +101,8 @@ GetNextHidItem (
   return StartPos;
 }
 
+break;
+
   case 3:
 //
 // 4-byte data, adjust size
@@ -109,6 +113,8 @@ GetNextHidItem (
   StartPos += 4;
   return StartPos;
 }
+
+break;
 }
   }
 
-- 
2.34.1



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[edk2-devel] [PATCH v3 1/2] MdeModulePkg/Bus/Usb/UsbMouseDxe: Fix REVERSE_INULL Coverity issue

[Ranbir Singh]

From: Ranbir Singh 

The function USBMouseDriverBindingStart do have

ASSERT (UsbMouseDevice != NULL);

after AllocateZeroPool, but it is applicable only in DEBUG mode.
In RELEASE mode, if for whatever reasons UsbMouseDevice is NULL
at this point, the code proceeds to dereference "UsbMouseDevice"
afterwards which will lead to CRASH.

Hence, for safety add NULL pointer checks always.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4222

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
Reviewed-by: Laszlo Ersek 
---
 MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c 
b/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c
index 451d4b934f4c..67072d476196 100644
--- a/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c
+++ b/MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c
@@ -160,7 +160,10 @@ USBMouseDriverBindingStart (
   }
 
   UsbMouseDevice = AllocateZeroPool (sizeof (USB_MOUSE_DEV));
-  ASSERT (UsbMouseDevice != NULL);
+  if (UsbMouseDevice == NULL) {
+Status = EFI_OUT_OF_RESOURCES;
+goto ErrorExit;
+  }
 
   UsbMouseDevice->UsbIo = UsbIo;
   UsbMouseDevice->Signature = USB_MOUSE_DEV_SIGNATURE;
-- 
2.34.1



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[edk2-devel] [PATCH v3 0/2] BZ 4222: Fix MdeModulePkg/Bus/Usb/UsbMouseDxe issues pointed by Coverity

[Ranbir Singh]

v2 -> v3:
  - Dropped the ASSERT wrt REVERSE_INULL issue as suggested
  - Added Reviewed-by: tags
  - Rebased to latest master HEAD

v1 -> v2:
  - Rebased to latest master HEAD
  - Changed the solution wrt MISSING_BREAK issues

Ranbir Singh (2):
  MdeModulePkg/Bus/Usb/UsbMouseDxe: Fix REVERSE_INULL Coverity issue
  MdeModulePkg/Bus/Usb/UsbMouseDxe: Fix MISSING_BREAK Coverity issues

 MdeModulePkg/Bus/Usb/UsbMouseDxe/MouseHid.c | 6 ++
 MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouse.c | 5 -
 2 files changed, 10 insertions(+), 1 deletion(-)

-- 
2.34.1



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[edk2-devel] [PATCH v2 2/2] MdeModulePkg/Bus/Pci/PciHostBridgeDxe: Fix MISSING_BREAK Coverity issue

[Ranbir Singh]

From: Ranbir Singh 

The function SubmitResources has a switch-case code in which the
case ACPI_ADDRESS_SPACE_TYPE_MEM: which falls through to
case ACPI_ADDRESS_SPACE_TYPE_IO: if there is no scenario of
return EFI_INVALID_PARAMETER;

While this may be intentional, it is not evident to any general code
reader why there is no break; in between. Adding

// No break; here as this is an intentional fallthrough.

as comment in between makes it explicit. Incidentally, the comment
satisfies Coverity as well.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4212

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index 519e1369f85e..3bd91e2787fd 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -1531,6 +1531,10 @@ SubmitResources (
   return EFI_INVALID_PARAMETER;
 }
 
+//
+// No break; here as this is an intentional fall through.
+//
+
   case ACPI_ADDRESS_SPACE_TYPE_IO:
 //
 // Check aligment, it should be of the form 2^n-1
-- 
2.34.1



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[edk2-devel] [PATCH v2 1/2] MdeModulePkg/Bus/Pci/PciHostBridgeDxe: Fix OVERRUN Coverity issues

[Ranbir Singh]

From: Ranbir Singh 

The function NotifyPhase has a check

ASSERT (Index < TypeMax);

but this comes into play only in DEBUG mode. In Release mode, there is
no handling if the Index value is within array limits or not. If for
whatever reasons, the Index does not get re-assigned to Index2 at line
137, then it remains at TypeMax as assigned earlier at line 929. This
poses array overrun risk at lines 942 and 943. It is better to deploy
a safety check on Index limit before accessing array elements.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4212

Cc: Ray Ni 
Co-authored-by: Veeresh Sangolli 
Signed-off-by: Ranbir Singh 
Signed-off-by: Ranbir Singh 
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
index d573e532bac8..519e1369f85e 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
@@ -939,6 +939,11 @@ NotifyPhase (
 }
 
 ASSERT (Index < TypeMax);
+
+if (Index >= TypeMax) {
+continue;
+}
+
 ResNodeHandled[Index] = TRUE;
 Alignment = RootBridge->ResAllocNode[Index].Alignment;
 BitsOfAlignment   = LowBitSet64 (Alignment + 1);
-- 
2.34.1



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[edk2-devel] [PATCH v2 0/2] BZ 4212: Fix MdeModulePkg/Bus/Pci/PciHostBridgeDxe issues pointed by Coverity

[Ranbir Singh]

v1 -> v2:
  - Rebased to latest master HEAD
  - Changed the commit message wrt MISSING_BREAK issues
  - Cc update

Ranbir Singh (2):
  MdeModulePkg/Bus/Pci/PciHostBridgeDxe: Fix OVERRUN Coverity issues
  MdeModulePkg/Bus/Pci/PciHostBridgeDxe: Fix MISSING_BREAK Coverity
issue

 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 9 +
 1 file changed, 9 insertions(+)

-- 
2.34.1



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Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

[Igor Kulchytskyy via groups.io]

I changed TestForRequiredProtocols function as Mike suggested.
I also kept GetHiIpProtocolType function without STATIC.
Resend pull request with those changes.
Thank you,
Igor

From: devel@edk2.groups.io  On Behalf Of Igor Kulchytskyy 
via groups.io
Sent: Monday, November 6, 2023 9:37 PM
To: Chang, Abner ; devel@edk2.groups.io; M M 

Cc: Nickle Wang 
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**
Hi Abner,
Thanks for the explanation!
Will keep it without static.
Best regards,
Igor


Get Outlook for Android

From: Chang, Abner mailto:abner.ch...@amd.com>>
Sent: Monday, November 6, 2023 8:51:18 PM
To: Igor Kulchytskyy mailto:ig...@ami.com>>; 
devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>; M M 
mailto:mike.maslen...@gmail.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Subject: RE: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: 
RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx


[AMD Official Use Only - General]


I would say to have static for a function used by module is a good coding 
practice and reduce the compile errors for the duplicated function naming, and 
maybe other advantages I am not quite sure.

But from edk2 C coding standard spec perspective, in 5.4.2.2.2, it says 
function should not be declared STATIC.

So my opinion is just keep the function without STATIC.



Abner





From: Igor Kulchytskyy mailto:ig...@ami.com>>
Sent: Tuesday, November 7, 2023 2:54 AM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>; M M 
mailto:mike.maslen...@gmail.com>>
Cc: Chang, Abner mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: RE: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: 
RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx



Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.



Hi Nickle and Abner,

What is your opinion – should we have GetHiIpProtocolType fuction as a static 
one?

Thank you,

Igor



From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Igor 
Kulchytskyy via groups.io
Sent: Monday, November 6, 2023 9:14 AM
To: M M mailto:mike.maslen...@gmail.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx





**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Mike,

See my comments below.

Thank you,

Igor

P.S.

“There is no limits to perfection”



From: M M mailto:mike.maslen...@gmail.com>>
Sent: Sunday, November 05, 2023 9:30 PM
To: Igor Kulchytskyy mailto:ig...@ami.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx



Hi Igor



I want to return to my initial comments regarding this patch.

Please, find my comments below.





On 1. 11. 2023., at 06:24, Igor Kulchytskyy 
mailto:ig...@ami.com>> wrote:



Hi Mike,
Thank you for review.
Please see my answers below the text.

-Original Message-
From: Mike Maslenkin mailto:mike.maslen...@gmail.com>>
Sent: Tuesday, October 31, 2023 9:00 PM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>
Cc: Abner Chang mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Igor

please find my comments below.

On Tue, Oct 31, 2023 at 8:56 PM Igor Kulchytskyy via 
groups.io
mailto:igork=ami@groups.io>> wrote:

Supported function of the driver changed to wait for all newtwork
interface to be installed.
Filer out the network interfaces which are not supported by
Redfish Host Interface.

Cc: Abner Chang mailto:abner.ch...@amd.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Cc: Igor Kulchytskyy mailto:ig...@ami.com>>
Signed-off-by: Igor Kulchytskyy mailto:ig...@ami.com>>
---
RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c | 96 ++--
1 file changed, 89 insertions(+), 7 deletions(-)

diff --git 

[edk2-devel] [PATCH v3] MdePkg:Add NVME Sanitize command support to Nvme.h

[Tina Chen]

PATCH v3 change: Update the Nvme.h file header that the version being used is 
2.0c.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591

1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition.
2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related 
definition for Sanitize status support.

Cc: Xiao X Chen 
Cc: Arthur Chen 
Cc: Ray Ni 
Cc: Liming Gao 
Cc: Michael D Kinney 
Signed-off-by: Tina Chen 
---
 MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c|   1 +
 MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c |   1 +
 MdePkg/Include/IndustryStandard/Nvme.h| 109 
++--
 3 files changed, 100 insertions(+), 11 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index b90c48731c..2ecaa2bbbe 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -908,6 +908,7 @@ NvmeControllerInit (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", Private->ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)Private->ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", 
Private->ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", 
Private->ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", 
Private->ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", 
Private->ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", Private->ControllerData->Nn));

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
index fc7b684940..61ef06e42f 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
@@ -436,6 +436,7 @@ NvmeDumpControllerData (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", ControllerData->Nn));

diff --git a/MdePkg/Include/IndustryStandard/Nvme.h 
b/MdePkg/Include/IndustryStandard/Nvme.h
index 8b8a1bb7f3..2c269ee987 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -1,5 +1,5 @@
 /** @file

-  Definitions based on NVMe spec. version 1.1.

+  Definitions based on NVMe spec. version 2.0c.

 

   (C) Copyright 2016 Hewlett Packard Enterprise Development LP

   Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.

@@ -9,6 +9,7 @@
   NVMe Specification 1.1

   NVMe Specification 1.4

   NVMe Specification 2.0

+  NVMe Specification 2.0c

 

 **/

 

@@ -403,7 +404,15 @@ typedef struct {
   UINT16   Edstt;   /* Extended Device Self-test Time */

   UINT8Dsto;/* Device Self-test Options  */

   UINT8Fwug;/* Firmware Update Granularity */

-  UINT8Rsvd2[192];  /* Reserved as of Nvm Express 1.4 Spec */

+  UINT16   Kas; /* Keep Alive Support */

+  UINT16   Hctma;   /* Host Controlled Thermal Management 
Attributes */

+  UINT16   Mntmt;   /* Minimum Thermal Management Temperature 
*/

+  UINT16   Mxtmt;   /* Maximum Thermal Management Temperature 
*/

+  UINT32   Sanicap; /* Sanitize Capabilities */

+  #define SANITIZE_OVERWRITE_ERASE_SUPPORTED  BIT2

+  #define SANITIZE_BLOCK_ERASE_SUPPORTED  BIT1

+  #define SANITIZE_CRYPTO_ERASE_SUPPORTED BIT0

+  UINT8Rsvd2[180];  /* Reserved as of Nvm Express 1.4 Spec */

   //

   // NVM Command Set Attributes

   //

@@ -687,10 +696,11 @@ typedef struct {
   // CDW 10

   //

   UINT32Lid   : 8;/* Log Page Identifier */

-  #define LID_ERROR_INFO0x1

-  #define LID_SMART_INFO0x2

-  #define LID_FW_SLOT_INFO  0x3

-  #define LID_BP_INFO   0x15

+  #define LID_ERROR_INFO0x1

+  #define LID_SMART_INFO0x2

+  #define LID_FW_SLOT_INFO  0x3

+  #define LID_BP_INFO   0x15

+  #define LID_SANITIZE_STATUS_INFO  0x81

   UINT32Rsvd1 : 8;

   UINT32Numd  : 12;   /* Number of Dwords */

   UINT32Rsvd2 : 4;/* Reserved as of Nvm Express 1.1 Spec */

@@ -708,6 +718,25 @@ typedef struct {
   UINT32Sv: 1;/* Save */

 } NVME_ADMIN_SET_FEATURES;

 

+//

+// NvmExpress Admin Sanitize Command

+//

+typedef struct {

+  //

+  // CDW 10

+  //

+  UINT32Sanact : 3;   /* Sanitize Action */

[edk2-devel] [PATCH v2] MdePkg:Add NVME Sanitize command support to Nvme.h

[Tina Chen]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591

1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition.
2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related 
definition for Sanitize status support.

Cc: Xiao X Chen 
Cc: Arthur Chen 
Cc: Ray Ni 
Cc: Liming Gao 
Signed-off-by: Tina Chen 
---
 MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c|   1 +
 MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c |   1 +
 MdePkg/Include/IndustryStandard/Nvme.h| 109 
++--
 3 files changed, 100 insertions(+), 11 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index b90c48731c..2ecaa2bbbe 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -908,6 +908,7 @@ NvmeControllerInit (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", Private->ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)Private->ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", 
Private->ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", 
Private->ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", 
Private->ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", 
Private->ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", Private->ControllerData->Nn));

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
index fc7b684940..61ef06e42f 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
@@ -436,6 +436,7 @@ NvmeDumpControllerData (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", ControllerData->Nn));

diff --git a/MdePkg/Include/IndustryStandard/Nvme.h 
b/MdePkg/Include/IndustryStandard/Nvme.h
index 8b8a1bb7f3..32a2b4515d 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -1,5 +1,5 @@
 /** @file

-  Definitions based on NVMe spec. version 1.1.

+  Definitions based on NVMe spec. version 2.0c.

 

   (C) Copyright 2016 Hewlett Packard Enterprise Development LP

   Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.

@@ -9,6 +9,7 @@
   NVMe Specification 1.1

   NVMe Specification 1.4

   NVMe Specification 2.0

+  NVMe Specification 2.c

 

 **/

 

@@ -403,7 +404,15 @@ typedef struct {
   UINT16   Edstt;   /* Extended Device Self-test Time */

   UINT8Dsto;/* Device Self-test Options  */

   UINT8Fwug;/* Firmware Update Granularity */

-  UINT8Rsvd2[192];  /* Reserved as of Nvm Express 1.4 Spec */

+  UINT16   Kas; /* Keep Alive Support */

+  UINT16   Hctma;   /* Host Controlled Thermal Management 
Attributes */

+  UINT16   Mntmt;   /* Minimum Thermal Management Temperature 
*/

+  UINT16   Mxtmt;   /* Maximum Thermal Management Temperature 
*/

+  UINT32   Sanicap; /* Sanitize Capabilities */

+  #define SANITIZE_OVERWRITE_ERASE_SUPPORTED  BIT2

+  #define SANITIZE_BLOCK_ERASE_SUPPORTED  BIT1

+  #define SANITIZE_CRYPTO_ERASE_SUPPORTED BIT0

+  UINT8Rsvd2[180];  /* Reserved as of Nvm Express 1.4 Spec */

   //

   // NVM Command Set Attributes

   //

@@ -687,10 +696,11 @@ typedef struct {
   // CDW 10

   //

   UINT32Lid   : 8;/* Log Page Identifier */

-  #define LID_ERROR_INFO0x1

-  #define LID_SMART_INFO0x2

-  #define LID_FW_SLOT_INFO  0x3

-  #define LID_BP_INFO   0x15

+  #define LID_ERROR_INFO0x1

+  #define LID_SMART_INFO0x2

+  #define LID_FW_SLOT_INFO  0x3

+  #define LID_BP_INFO   0x15

+  #define LID_SANITIZE_STATUS_INFO  0x81

   UINT32Rsvd1 : 8;

   UINT32Numd  : 12;   /* Number of Dwords */

   UINT32Rsvd2 : 4;/* Reserved as of Nvm Express 1.1 Spec */

@@ -708,6 +718,25 @@ typedef struct {
   UINT32Sv: 1;/* Save */

 } NVME_ADMIN_SET_FEATURES;

 

+//

+// NvmExpress Admin Sanitize Command

+//

+typedef struct {

+  //

+  // CDW 10

+  //

+  UINT32Sanact : 3;   /* Sanitize Action */

+  UINT32Ause   : 1;   /* Allow Unrestricted Sanitize Exit */

+  UINT32Owpass : 4;   /* 

Re: [edk2-devel] [PATCH v2 08/30] MdePkg: Add IOCSR operation for LoongArch

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: Chao Li 
> Sent: Sunday, November 5, 2023 7:28 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [PATCH v2 08/30] MdePkg: Add IOCSR operation for LoongArch
> 
> Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8,
> IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR
> registers
> of LoongArch architecture.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/BaseLib.h   | 112 +++
>  MdePkg/Library/BaseLib/BaseLib.inf |   1 +
>  MdePkg/Library/BaseLib/LoongArch64/IoCsr.S | 120
> +
>  3 files changed, 233 insertions(+)
>  create mode 100644 MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 234f3065c2..88ee6e9d51 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -338,6 +338,118 @@ CsrXChg (
>IN UINTN   Mask
>);
> 
> +/**
> +  IO CSR read byte operation.
> +
> +  @param[in]  Select   IO CSR read instruction select values.
> +
> +  @return The return value of iocsrrd.b instruction.
> +
> +**/
> +UINT8
> +IoCsrRead8 (
> +  IN UINTN  Select
> +  );
> +
> +/**
> +  IO CSR read half word operation.
> +
> +  @param[in]  Select   IO CSR read instruction select values.
> +
> +  @return The return value of iocsrrd.h instruction.
> +
> +**/
> +UINT16
> +IoCsrRead16 (
> +  IN UINTN  Select
> +  );
> +
> +/**
> +  IO CSR read word operation.
> +
> +  @param[in]  Select   IO CSR read instruction select values.
> +
> +  @return The return value of iocsrrd.w instruction.
> +
> +**/
> +UINT32
> +IoCsrRead32 (
> +  IN UINTN  Select
> +  );
> +
> +/**
> +  IO CSR read double word operation. Only for LoongArch64.
> +
> +  @param[in]  Select   IO CSR read instruction select values.
> +
> +  @return The return value of iocsrrd.d instruction.
> +
> +**/
> +UINT64
> +IoCsrRead64 (
> +  IN UINTN  Select
> +  );
> +
> +/**
> +  IO CSR write byte operation.
> +
> +  @param[in]  Select   IO CSR write instruction select values.
> +  @param[in]  ValueThe iocsrwr.b will write the value.
> +
> +  @return VOID.
> +
> +**/
> +VOID
> +IoCsrWrite8 (
> +  IN UINTN  Select,
> +  IN UINT8  Value
> +  );
> +
> +/**
> +  IO CSR write half word operation.
> +
> +  @param[in]  Select   IO CSR write instruction select values.
> +  @param[in]  ValueThe iocsrwr.h will write the value.
> +
> +  @return VOID.
> +
> +**/
> +VOID
> +IoCsrWrite16 (
> +  IN UINTN   Select,
> +  IN UINT16  Value
> +  );
> +
> +/**
> +  IO CSR write word operation.
> +
> +  @param[in]  Select   IO CSR write instruction select values.
> +  @param[in]  ValueThe iocsrwr.w will write the value.
> +
> +  @return VOID.
> +
> +**/
> +VOID
> +IoCsrWrite32 (
> +  IN UINTN   Select,
> +  IN UINT32  Value
> +  );
> +
> +/**
> +  IO CSR write double word operation. Only for LoongArch64.
> +
> +  @param[in]  Select   IO CSR write instruction select values.
> +  @param[in]  ValueThe iocsrwr.d will write the value.
> +
> +  @return VOID.
> +
> +**/
> +VOID
> +IoCsrWrite64 (
> +  IN UINTN   Select,
> +  IN UINT64  Value
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 74a323c798..e72724c1c1 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -412,6 +412,7 @@
>LoongArch64/Csr.c
>LoongArch64/InternalSwitchStack.c
>LoongArch64/AsmCsr.S  | GCC
> +  LoongArch64/IoCsr.S   | GCC
>LoongArch64/GetInterruptState.S   | GCC
>LoongArch64/EnableInterrupts.S| GCC
>LoongArch64/DisableInterrupts.S   | GCC
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> new file mode 100644
> index 00..4c0009b93a
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/LoongArch64/IoCsr.S
> @@ -0,0 +1,120 @@
> +#
> --
> +#
> +# LoongArch ASM IO CSR operation functions
> +#
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> --
> +
> +ASM_GLOBAL ASM_PFX (IoCsrRead8)
> +ASM_GLOBAL ASM_PFX (IoCsrRead16)
> +ASM_GLOBAL ASM_PFX (IoCsrRead32)
> +ASM_GLOBAL ASM_PFX (IoCsrRead64)
> +
> +ASM_GLOBAL ASM_PFX (IoCsrWrite8)
> +ASM_GLOBAL ASM_PFX (IoCsrWrite16)
> +ASM_GLOBAL ASM_PFX (IoCsrWrite32)
> +ASM_GLOBAL ASM_PFX (IoCsrWrite64)
> +
> +#/**
> +#  IO CSR read byte operation.
> +#
> +#  @param[in]  Select   IO CSR read 

Re: [edk2-devel] [PATCH v2 03/30] MdePkg: Add LoongArch64 exception function set into BaseLib

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: Chao Li 
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [PATCH v2 03/30] MdePkg: Add LoongArch64 exception function
> set into BaseLib
> 
> Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions
> for LoongArch64.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/BaseLib.h  | 20 +
>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>  .../BaseLib/LoongArch64/ExceptionBase.S   | 41
> +++
>  3 files changed, 62 insertions(+)
>  create mode 100644 MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 5d7067ee85..a9a69c734c 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -229,6 +229,26 @@ typedef struct {
> 
>  #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT  8
> 
> +/*
> + * Set the exception base address for LoongArch.
> + *
> + * @param  ExceptionBaseAddress   The exception base address, must be
> aligned greater than or qeual to 4K .
> + */
> +VOID
> +SetExceptionBaseAddress (
> +  IN UINT64
> +  );
> +
> +/*
> + * Set the TlbRebase address for LoongArch.
> + *
> + * @param  TlbRebaseAddress   The TlbRebase address, must be aligned
> greater than or qeual to 4K .
> + */
> +VOID
> +SetTlbRebaseAddress (
> +  IN UINT64
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 03c7b02e82..a18fe5efb4 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -419,6 +419,7 @@
>LoongArch64/CpuPause.S| GCC
>LoongArch64/SetJumpLongJump.S | GCC
>LoongArch64/SwitchStack.S | GCC
> +  LoongArch64/ExceptionBase.S   | GCC
> 
>  [Packages]
>MdePkg/MdePkg.dec
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> new file mode 100644
> index 00..36c6ca7ca8
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/LoongArch64/ExceptionBase.S
> @@ -0,0 +1,41 @@
> +#
> --
> +#
> +# LoongArch set exception base address operations
> +#
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> --
> +
> +#include 
> +#include 
> +
> +ASM_GLOBAL ASM_PFX(SetExceptionBaseAddress)
> +ASM_GLOBAL ASM_PFX(SetTlbRebaseAddress)
> +
> +#/**
> +#  Set the exception base address for LoongArch.
> +#
> +#  @param  ExceptionBaseAddress   The exception base address, must be
> aligned greater than or qeual to 4K .
> +#**/
> +ASM_PFX(SetExceptionBaseAddress):
> +  csrrd   $t0, LOONGARCH_CSR_ECFG
> +  li.d$t1, ~(BIT16 | BIT17 | BIT18)
> +  and $t0, $t0, $t1
> +  csrwr   $t0, LOONGARCH_CSR_ECFG
> +
> +  move$t0, $a0
> +  csrwr   $t0, LOONGARCH_CSR_EBASE
> +  jirl$zero, $ra, 0
> +
> +#/**
> +#  Set the TlbRebase address for LoongArch.
> +#
> +#  @param  TlbRebaseAddress   The TlbRebase address, must be aligned
> greater than or qeual to 4K .
> +#**/
> +ASM_PFX(SetTlbRebaseAddress):
> +  move$t0, $a0
> +  csrwr   $t0, LOONGARCH_CSR_TLBREBASE
> +  jirl$zero, $ra, 0
> +.end
> --
> 2.27.0



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Re: [edk2-devel] [PATCH v2 07/30] MdePkg: Add CSR operation for LoongArch

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Chao Li
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ;
> Bibo Mao 
> Subject: [edk2-devel] [PATCH v2 07/30] MdePkg: Add CSR operation for
> LoongArch
> 
> Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use
> them
> to operate the CSR register of LoongArch architecture.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> Co-authored-by: Bibo Mao 
> ---
>  MdePkg/Include/Library/BaseLib.h|  45 +++
>  MdePkg/Library/BaseLib/BaseLib.inf  |   2 +
>  MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422
> 
>  MdePkg/Library/BaseLib/LoongArch64/Csr.c|  81 
>  4 files changed, 550 insertions(+)
>  create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
>  create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 55d53c75a0..234f3065c2 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -293,6 +293,51 @@ AsmReadStableCounter (
>VOID
>);
> 
> +/**
> +  CSR read operation.
> +
> +  @param[in]  Select   CSR read instruction select values.
> +
> +  @return The return value of csrrd instruction, return -1 means
> no CSR instruction
> +  is found.
> +**/
> +UINTN
> +CsrRead (
> +  IN UINT16  Select
> +  );
> +
> +/**
> +  CSR write operation.
> +
> +  @param[in]  Select   CSR write instruction select values.
> +  @param[in]  ValueThe csrwr will write the value.
> +
> +  @return The return value of csrwr instruction, that is, store
> the old value of
> +  the register, return -1 means no CSR instruction is
> found.
> +**/
> +UINTN
> +CsrWrite (
> +  IN UINT16  Select,
> +  IN UINTN   Value
> +  );
> +
> +/**
> +  CSR exchange operation.
> +
> +  @param[in]  Select   CSR exchange instruction select values.
> +  @param[in]  ValueThe csrxchg will write the value.
> +  @param[in]  Mask The csrxchg mask value.
> +
> +  @return The return value of csrxchg instruction, that is, store
> the old value of
> +  the register, return -1 means no CSR instruction is
> found.
> +**/
> +UINTN
> +CsrXChg (
> +  IN UINT16  Select,
> +  IN UINTN   Value,
> +  IN UINTN   Mask
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index aaf221822b..74a323c798 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -409,7 +409,9 @@
>  [Sources.LOONGARCH64]
>Math64.c
>Unaligned.c
> +  LoongArch64/Csr.c
>LoongArch64/InternalSwitchStack.c
> +  LoongArch64/AsmCsr.S  | GCC
>LoongArch64/GetInterruptState.S   | GCC
>LoongArch64/EnableInterrupts.S| GCC
>LoongArch64/DisableInterrupts.S   | GCC
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
> b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
> new file mode 100644
> index 00..25dd060ede
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
> @@ -0,0 +1,422 @@
> +#
> --
> +#
> +# LoongArch ASM CSR operation functions
> +#
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> --
> +
> +#include 
> +
> +ASM_GLOBAL ASM_PFX (AsmCsrRead)
> +ASM_GLOBAL ASM_PFX (AsmCsrWrite)
> +ASM_GLOBAL ASM_PFX (AsmCsrXChg)
> +
> +.macro AsmCsrRd Sel
> +  csrrd   $a0, \Sel
> +  jirl$zero, $ra, 0
> +.endm
> +
> +.macro AsmCsrWr Sel
> +  csrwr   $a0, \Sel
> +  jirl$zero, $ra, 0
> +.endm
> +
> +.macro AsmCsrXChange Sel
> +  csrxchg $a0, $a1, \Sel
> +  jirl$zero, $ra, 0
> +.endm
> +
> +ASM_PFX(AsmCsrRead):
> +  blt  $a0, $zero, ReadSelNumErr
> +  li.w $t0, LOONGARCH_CSR_EBASE
> +  bltu $t0, $a0, TlbCsrRd
> +
> +BasicCsrRd:
> +  la.pcrel $t0, BasicCsrRead
> +  alsl.d   $t0, $a0, $t0, 3
> +  jirl $zero, $t0, 0
> +
> +TlbCsrRd:
> +  li.w $t0, LOONGARCH_CSR_TLBIDX
> +  bltu $a0, $t0, ReadSelNumErr
> +  li.w $t0, LOONGARCH_CSR_RVACFG
> +  bltu $t0, $a0, CfgCsrRd
> +  la.pcrel $t0, TlbCsrRead
> +  addi.w   $t1, $a0, -LOONGARCH_CSR_TLBIDX
> +  alsl.d   $t0, $t1, $t0, 3
> +  jirl $zero, $t0, 0
> +
> +CfgCsrRd:
> +  li.w $t0, LOONGARCH_CSR_CPUNUM
> +  bltu $a0, $t0, ReadSelNumErr
> +  li.w $t0, LOONGARCH_CSR_PRCFG3
> +  bltu $t0, $a0, KcsCsrRd
> +  la.pcrel $t0, CfgCsrRead
> +  addi.w   $t1, $a0, -LOONGARCH_CSR_CPUNUM
> +  alsl.d   $t0, $t1, $t0, 3
> +  jirl $zero, 

Re: [edk2-devel] [PATCH v2 06/30] MdePkg: Add read stable counter operation for LoongArch

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: Chao Li 
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [PATCH v2 06/30] MdePkg: Add read stable counter operation
> for LoongArch
> 
> Add LoongArch gets stable counter ASM function.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/BaseLib.h  | 12 ++
>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>  .../BaseLib/LoongArch64/ReadStableCounter.S   | 24
> +++
>  3 files changed, 37 insertions(+)
>  create mode 100644
> MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 3adf4d0042..55d53c75a0 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -281,6 +281,18 @@ AsmCpucfg (
>OUT UINT32  *Data
>);
> 
> +/**
> +  Gets the timer count value.
> +
> +  @param[] VOID
> +  @retval  timer count value.
> +
> +**/
> +UINTN
> +AsmReadStableCounter (
> +  VOID
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index a427aa9359..aaf221822b 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -421,6 +421,7 @@
>LoongArch64/SwitchStack.S | GCC
>LoongArch64/ExceptionBase.S   | GCC
>LoongArch64/Cpucfg.S  | GCC
> +  LoongArch64/ReadStableCounter.S   | GCC
> 
>  [Packages]
>MdePkg/MdePkg.dec
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> new file mode 100644
> index 00..59c877211d
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/LoongArch64/ReadStableCounter.S
> @@ -0,0 +1,24 @@
> +#
> --
> +#
> +# LoongArch Read Stable Counter
> +#
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> --
> +
> +ASM_GLOBAL ASM_PFX(AsmReadStableCounter)
> +
> +#/**
> +#  Gets the timer count value.
> +#
> +#  @param[] VOID
> +#  @retval  timer count value.
> +#
> +#**/
> +
> +ASM_PFX(AsmReadStableCounter):
> +  rdtime.d   $a0, $zero
> +  jirl   $zero, $ra, 0
> +  .end
> --
> 2.27.0



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Re: [edk2-devel] [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: Chao Li 
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function
> 
> Add LoongArch AsmCpucfg function and Cpucfg definitions.
> 
> Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of
> EccCheck.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/BaseLib.h |  12 +
>  MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565
> +++
>  MdePkg/Library/BaseLib/BaseLib.inf   |   1 +
>  MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S  |  26 +
>  MdePkg/MdePkg.ci.yaml|   3 +-
>  5 files changed, 606 insertions(+), 1 deletion(-)
>  create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h
>  create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 93a014cd49..3adf4d0042 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -269,6 +269,18 @@ DisableLocalInterrupts (
>IN UINT16
>);
> 
> +/**
> +  Read CPUCFG register.
> +
> +  @param  Index  Specifies the register number of the CPUCFG to read
> the data.
> +  @param  Data   A pointer to the variable used to store the CPUCFG
> register value.
> +**/
> +VOID
> +AsmCpucfg (
> +  IN  UINT32  Index,
> +  OUT UINT32  *Data
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Include/Register/LoongArch64/Cpucfg.h
> b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
> new file mode 100644
> index 00..841885dc70
> --- /dev/null
> +++ b/MdePkg/Include/Register/LoongArch64/Cpucfg.h
> @@ -0,0 +1,565 @@
> +/** @file
> +  CPUCFG definitions.
> +
> +  Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef CPUCFG_H_
> +#define CPUCFG_H_
> +
> +/**
> +  CPUCFG REG0 Information
> +
> +  @code
> +  CPUCFG_REG0_INFO_DATA
> + **/
> +#define CPUCFG_REG0_INFO  0x0
> +
> +/**
> +  CPUCFG REG0 Information returned data.
> +  #CPUCFG_REG0_INFO
> + **/
> +typedef union {
> +  struct {
> +///
> +/// [Bit 31:0] Processor Identity.
> +///
> +UINT32PRID : 32;
> +  } Bits;
> +  ///
> +  /// All bit fields as a 32-bit value
> +  ///
> +  UINT32Uint32;
> +} CPUCFG_REG0_INFO_DATA;
> +
> +/**
> +  CPUCFG REG1 Information
> +
> +  @code
> +  CPUCFG_REG1_INFO_DATA
> + **/
> +#define CPUCFG_REG1_INFO  0x1
> +
> +/**
> +  CPUCFG REG1 Information returned data.
> +  #CPUCFG_REG1_INFO
> + **/
> +typedef union {
> +  struct {
> +///
> +/// [Bit 1:0] Architecture:
> +///   2'b00 indicates the implementation of simplified
> LoongAarch32;
> +///   2'b01 indicates the implementation of LoongAarch32;
> +///   2'b10 indicates the implementation of LoongAarch64;
> +///   2'b11 reserved;
> +///
> +UINT32ARCH  : 2;
> +///
> +/// [Bit 2] Paging mapping mode. A value of 1 indicates the
> processor MMU supports
> +/// page mapping mode.
> +///
> +UINT32PGMMU : 1;
> +///
> +/// [Bit 3] A value of 1 indicates the processor supports the
> IOCSR instruction.
> +///
> +UINT32IOCSR : 1;
> +///
> +/// [Bit 11:4] Physical address bits. The supported physical
> address bits PALEN value
> +/// minus 1.
> +///
> +UINT32PALEN : 8;
> +///
> +/// [Bit 19:12] Virtual address bits. The supported virtual
> address bits VALEN value
> +/// minus 1.
> +///
> +UINT32VALEN : 8;
> +///
> +/// [Bit 20] Non-aligned Memory Access. A value of 1 indicates
> the processor supports
> +/// non-aligned memory access.
> +///
> +UINT32UAL   : 1;
> +///
> +/// [Bit 21] Page Read Inhibit. A value of 1 indicates the
> processor supports page
> +/// attribute of "Read Inhibit".
> +///
> +UINT32RI: 1;
> +///
> +/// [Bit 22] Page Execution Protection. A value of 1 indicates
> the processor supports
> +/// page attribute of "Execution Protection".
> +///
> +UINT32EP: 1;
> +///
> +/// [Bit 23] A value of 1 indicates the processor supports for
> page attributes of RPLV.
> +///
> +UINT32RPLV  : 1;
> +///
> +/// [Bit 24] Huge Page. A value of 1 indicates the processor
> supports page attribute
> +/// of huge page.
> +///
> +UINT32HP: 1;
> +///
> +/// [Bit 25] A value of 1 indicates that the string of processor
> product information
> +/// is recorded at address 0 of the IOCSR access space.
> +///
> +UINT32

Re: [edk2-devel] [PATCH v2 02/30] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Chao Li
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [edk2-devel] [PATCH v2 02/30] MdePkg: Add LoongArch64 FPU
> function set into BaseCpuLib
> 
> Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and
> DisableFloatingPointUnits functions for LoongArch64.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/CpuLib.h   | 37 +++---
>  MdePkg/Library/BaseCpuLib/BaseCpuLib.inf  |  7 ++-
>  .../Library/BaseCpuLib/LoongArch/DisableFpu.S | 17 +++
>  .../Library/BaseCpuLib/LoongArch/EnableFpu.S  | 17 +++
>  .../BaseCpuLib/LoongArch/InitializeFpu.S  | 51
> +++
>  5 files changed, 121 insertions(+), 8 deletions(-)
>  create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
>  create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
>  create mode 100644
> MdePkg/Library/BaseCpuLib/LoongArch/InitializeFpu.S
> 
> diff --git a/MdePkg/Include/Library/CpuLib.h
> b/MdePkg/Include/Library/CpuLib.h
> index 3f29937dc7..42da55ca69 100644
> --- a/MdePkg/Include/Library/CpuLib.h
> +++ b/MdePkg/Include/Library/CpuLib.h
> @@ -8,6 +8,7 @@
>As a result, these services could not be defined in the Base
> Library.
> 
>  Copyright (c) 2006 - 2018, Intel Corporation. All rights
> reserved.
> +Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -41,14 +42,14 @@ CpuFlushTlb (
>VOID
>);
> 
> -#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
> -
>  /**
> +  Initialize the CPU floating point units.
> +
>Initializes floating point units for requirement of UEFI
> specification.
> -  This function initializes floating-point control word to 0x027F
> (all exceptions
> -  masked,double-precision, round-to-nearest) and multimedia-
> extensions control word
> -  (if supported) to 0x1F80 (all exceptions masked, round-to-nearest,
> flush to zero
> -  for masked underflow).
> +  For IA32 and X64, this function initializes floating-point control
> word to 0x027F
> +  (all exceptions masked,double-precision, round-to-nearest) and
> multimedia-extensions
> +  control word (if supported) to 0x1F80 (all exceptions masked,
> round-to-nearest,
> +  flush to zero for masked underflow).
>  **/
>  VOID
>  EFIAPI
> @@ -56,6 +57,30 @@ InitializeFloatingPointUnits (
>VOID
>);
> 
> +/**
> +  Enable the CPU floating point units.
> +
> +  Enable the CPU floating point units.
> +**/
> +VOID
> +EFIAPI
> +EnableFloatingPointUnits (
> +  VOID
> +  );
> +
> +/**
> +  Disable the CPU floating point units.
> +
> +  Disable the CPU floating point units.
> +**/
> +VOID
> +EFIAPI
> +DisableFloatingPointUnits (
> +  VOID
> +  );
> +
> +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
> +
>  /**
>Determine if the standard CPU signature is "AuthenticAMD".
>@retval TRUE  The CPU signature matches.
> diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> index 9a162afe6d..89f6272f11 100644
> --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> @@ -65,8 +65,11 @@
>RiscV/Cpu.S
> 
>  [Sources.LOONGARCH64]
> -  LoongArch/CpuFlushTlb.S | GCC
> -  LoongArch/CpuSleep.S| GCC
> +  LoongArch/CpuFlushTlb.S   | GCC
> +  LoongArch/CpuSleep.S  | GCC
> +  LoongArch/InitializeFpu.S | GCC
> +  LoongArch/EnableFpu.S | GCC
> +  LoongArch/DisableFpu.S| GCC
> 
>  [Packages]
>MdePkg/MdePkg.dec
> diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
> b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
> new file mode 100644
> index 00..6cb253a416
> --- /dev/null
> +++ b/MdePkg/Library/BaseCpuLib/LoongArch/DisableFpu.S
> @@ -0,0 +1,17 @@
> +#
> --
> +#
> +# DisableFloatingPointUnits() for LoongArch64
> +#
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> --
> +ASM_GLOBAL ASM_PFX(DisableFloatingPointUnits)
> +
> +ASM_PFX(DisableFloatingPointUnits):
> +  li.w$t0, 0x1
> +  csrxchg $zero, $t0, 0x2
> +
> +  jirl $zero, $ra, 0
> +  .end
> diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
> b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
> new file mode 100644
> index 00..27d8243a59
> --- /dev/null
> +++ b/MdePkg/Library/BaseCpuLib/LoongArch/EnableFpu.S
> @@ -0,0 +1,17 @@
> +#
> --
> +#
> +# 

Re: [edk2-devel] [PATCH v2 04/30] MdePkg: Add LoongArch64 local interrupt function set into BaseLib

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Chao Li
> Sent: Sunday, November 5, 2023 7:27 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [edk2-devel] [PATCH v2 04/30] MdePkg: Add LoongArch64 local
> interrupt function set into BaseLib
> 
> Adding LoongArch local interrupt function set, which is used to
> control
> the opening or closing of the local interrupt when the global
> interrupt
> is enabled.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Library/BaseLib.h  | 20 +
>  .../BaseLib/LoongArch64/DisableInterrupts.S   | 22 ++
> -
>  .../BaseLib/LoongArch64/EnableInterrupts.S| 22 ++
> -
>  3 files changed, 54 insertions(+), 10 deletions(-)
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index a9a69c734c..93a014cd49 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -249,6 +249,26 @@ SetTlbRebaseAddress (
>IN UINT64
>);
> 
> +/**
> +  Enables local CPU interrupts.
> +
> +  @param  Needs to enable local interrupt bit.
> +**/
> +VOID
> +EnableLocalInterrupts (
> +  IN UINT16
> +  );
> +
> +/**
> +  Disables local CPU interrupts.
> +
> +  @param  Needs to disable local interrupt bit.
> +**/
> +VOID
> +DisableLocalInterrupts (
> +  IN UINT16
> +  );
> +
>  #endif // defined (MDE_CPU_LOONGARCH64)
> 
>  //
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
> b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
> index 0f228339af..5de10e9e7a 100644
> --- a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
> +++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
> @@ -1,21 +1,33 @@
>  #
> --
>  #
> -# LoongArch interrupt disable
> +# LoongArch interrupt disable operations
>  #
> -# Copyright (c) 2022, Loongson Technology Corporation Limited. All
> rights reserved.
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
>  #
> --
> 
> +#include 
> +#include 
> +
> +ASM_GLOBAL ASM_PFX(DisableLocalInterrupts)
>  ASM_GLOBAL ASM_PFX(DisableInterrupts)
> 
>  #/**
> -#  Disables CPU interrupts.
> +#  Disables local CPU interrupts.
> +#
> +#  @param  Needs to disable local interrupt bit.
>  #**/
> +ASM_PFX(DisableLocalInterrupts):
> +  csrxchg $zero, $a0, LOONGARCH_CSR_ECFG
> +  jirl$zero, $ra, 0
> 
> +#/**
> +#  Disables global CPU interrupts.
> +#**/
>  ASM_PFX(DisableInterrupts):
> -  li.w$t0, 0x4
> -  csrxchg $zero, $t0, 0x0
> +  li.w$t0, BIT2
> +  csrxchg $zero, $t0, LOONGARCH_CSR_CRMD
>jirl$zero, $ra, 0
>.end
> diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
> b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
> index 3c34fb2cdd..73adcd7b0c 100644
> --- a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
> +++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
> @@ -1,21 +1,33 @@
>  #
> --
>  #
> -# LoongArch interrupt enable
> +# LoongArch interrupt enable operations
>  #
> -# Copyright (c) 2022, Loongson Technology Corporation Limited. All
> rights reserved.
> +# Copyright (c) 2023, Loongson Technology Corporation Limited. All
> rights reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
>  #
> --
> 
> +#include 
> +#include 
> +
> +ASM_GLOBAL ASM_PFX(EnableLocalInterrupts)
>  ASM_GLOBAL ASM_PFX(EnableInterrupts)
> 
>  #/**
> -#  Enables CPU interrupts.
> +#  Enables local CPU interrupts.
> +#
> +#  @param  Needs to enable local interrupt bit.
>  #**/
> +ASM_PFX(EnableLocalInterrupts):
> +  csrxchg $a0, $a0, LOONGARCH_CSR_ECFG
> +  jirl$zero, $ra, 0
> 
> +#/**
> +#  Enables global CPU interrupts.
> +#**/
>  ASM_PFX(EnableInterrupts):
> -  li.w$t0, 0x4
> -  csrxchg $t0, $t0, 0x0
> +  li.w$t0, BIT2
> +  csrxchg $t0, $t0, LOONGARCH_CSR_CRMD
>jirl$zero, $ra, 0
>.end
> --
> 2.27.0
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH v2 01/30] MdePkg: Add the header file named Csr.h for LoongArch64

[Michael D Kinney]

Acked-by: Michael D Kinney 

> -Original Message-
> From: Chao Li 
> Sent: Sunday, November 5, 2023 7:26 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang 
> Subject: [PATCH v2 01/30] MdePkg: Add the header file named Csr.h for
> LoongArch64
> 
> Adding Csr.h for LoongArch64, it is use for accessing the CSR
> registers.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Chao Li 
> ---
>  MdePkg/Include/Register/LoongArch64/Csr.h | 221
> ++
>  1 file changed, 221 insertions(+)
>  create mode 100644 MdePkg/Include/Register/LoongArch64/Csr.h
> 
> diff --git a/MdePkg/Include/Register/LoongArch64/Csr.h
> b/MdePkg/Include/Register/LoongArch64/Csr.h
> new file mode 100644
> index 00..b78d766b42
> --- /dev/null
> +++ b/MdePkg/Include/Register/LoongArch64/Csr.h
> @@ -0,0 +1,221 @@
> +/** @file
> +
> +  Copyright (c) 2023 Loongson Technology Corporation Limited. All
> rights reserved.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Glossary:
> +- EXC - Exception
> +- CSR - CPU Status Register
> +**/
> +
> +#ifndef LOONGARCH_CSR_H_
> +#define LOONGARCH_CSR_H_
> +
> +#include 
> +
> +//
> +// CSR register numbers
> +//
> +
> +//
> +// Basic CSR registers
> +//
> +#define LOONGARCH_CSR_CRMD 0x0
> +#define LOONGARCH_CSR_PRMD 0x1
> +#define LOONGARCH_CSR_EUEN 0x2
> +#define CSR_EUEN_LBTEN_SHIFT   3
> +#define CSR_EUEN_LBTEN (0x1ULL << CSR_EUEN_LBTEN_SHIFT)
> +#define CSR_EUEN_LASXEN_SHIFT  2
> +#define CSR_EUEN_LASXEN(0x1ULL << CSR_EUEN_LASXEN_SHIFT)
> +#define CSR_EUEN_LSXEN_SHIFT   1
> +#define CSR_EUEN_LSXEN (0x1ULL << CSR_EUEN_LSXEN_SHIFT)
> +#define CSR_EUEN_FPEN_SHIFT0
> +#define CSR_EUEN_FPEN  (0x1ULL << CSR_EUEN_FPEN_SHIFT)
> +#define LOONGARCH_CSR_MISC 0x3
> +#define LOONGARCH_CSR_ECFG 0x4
> +
> +#define LOONGARCH_CSR_ESTAT   0x5
> +#define CSR_ESTAT_ESUBCODE_SHIFT  22
> +#define CSR_ESTAT_ESUBCODE_WIDTH  9
> +#define CSR_ESTAT_ESUBCODE(0x1ffULL <<
> CSR_ESTAT_ESUBCODE_SHIFT)
> +#define CSR_ESTAT_EXC_SHIFT   16
> +#define CSR_ESTAT_EXC_WIDTH   6
> +#define CSR_ESTAT_EXC (0x3FULL << CSR_ESTAT_EXC_SHIFT)
> +#define CSR_ESTAT_IS_SHIFT0
> +#define CSR_ESTAT_IS_WIDTH15
> +#define CSR_ESTAT_IS  (0x7FFFULL << CSR_ESTAT_IS_SHIFT)
> +
> +#define LOONGARCH_CSR_ERA0x6
> +#define LOONGARCH_CSR_BADV   0x7
> +#define LOONGARCH_CSR_BADI   0x8
> +#define LOONGARCH_CSR_EBASE  0xC // Exception entry base address
> +
> +//
> +// TLB related CSR registers
> +//
> +#define LOONGARCH_CSR_TLBIDX  0x10  // TLB Index, EHINV,
> PageSize, NP
> +#define LOONGARCH_CSR_TLBEHI  0x11  // TLB EntryHi
> +#define LOONGARCH_CSR_TLBELO0 0x12  // TLB EntryLo0
> +#define LOONGARCH_CSR_TLBELO1 0x13  // TLB EntryLo1
> +#define LOONGARCH_CSR_ASID0x18  // ASID
> +#define LOONGARCH_CSR_PGDL0x19  // Page table base
> address when VA[47] = 0
> +#define LOONGARCH_CSR_PGDH0x1A  // Page table base
> address when VA[47] = 1
> +#define LOONGARCH_CSR_PGD 0x1B  // Page table base
> +#define LOONGARCH_CSR_PWCTL0  0x1C  // PWCtl0
> +#define LOONGARCH_CSR_PWCTL1  0x1D  // PWCtl1
> +#define LOONGARCH_CSR_STLBPGSIZE  0x1E
> +#define LOONGARCH_CSR_RVACFG  0x1F
> +
> +//
> +// Config CSR registers
> +//
> +#define LOONGARCH_CSR_CPUNUM  0x20// CPU core number
> +#define LOONGARCH_CSR_PRCFG1  0x21// Config1
> +#define LOONGARCH_CSR_PRCFG2  0x22// Config2
> +#define LOONGARCH_CSR_PRCFG3  0x23// Config3
> +
> +//
> +// Kscratch registers
> +//
> +#define LOONGARCH_CSR_KS0  0x30
> +#define LOONGARCH_CSR_KS1  0x31
> +#define LOONGARCH_CSR_KS2  0x32
> +#define LOONGARCH_CSR_KS3  0x33
> +#define LOONGARCH_CSR_KS4  0x34
> +#define LOONGARCH_CSR_KS5  0x35
> +#define LOONGARCH_CSR_KS6  0x36
> +#define LOONGARCH_CSR_KS7  0x37
> +#define LOONGARCH_CSR_KS8  0x38
> +
> +//
> +// Stable timer registers
> +//
> +#define LOONGARCH_CSR_TMID   0x40  // Timer ID
> +#define LOONGARCH_CSR_TMCFG  0x41
> +#define LOONGARCH_CSR_TMCFG_EN   (1ULL << 0)
> +#define LOONGARCH_CSR_TMCFG_PERIOD   (1ULL << 1)
> +#define LOONGARCH_CSR_TMCFG_TIMEVAL  (0x3FFFULL << 2)
> +#define LOONGARCH_CSR_TVAL   0x42// Timer value
> +#define LOONGARCH_CSR_CNTC   0x43// Timer offset
> +#define LOONGARCH_CSR_TINTCLR0x44// Timer interrupt clear
> +
> +//
> +// TLB refill exception base address
> +//
> +#define LOONGARCH_CSR_TLBREBASE  0x88// TLB refill exception
> entry
> +#define LOONGARCH_CSR_TLBRBADV   0x89// TLB refill badvaddr
> +#define LOONGARCH_CSR_TLBRERA0x8a// TLB refill ERA
> +#define LOONGARCH_CSR_TLBRSAVE   0x8b// KScratch for TLB refill
> exception
> +#define LOONGARCH_CSR_TLBRELO0   0x8c// 

Re: [edk2-devel] [PATCH v1 0/7] CryptoPkg: Enable Openssl native instruction support for AARCH64

[Yao, Jiewen]

Hi Leif/Ard/Sami
I would expect ARM/AARCH64 maintainers to review the ARM specific files, even 
they are in CryptoPkg. Please help on that.

Thank you
Yao, Jiewen


> -Original Message-
> From: Li, Yi1 
> Sent: Tuesday, November 7, 2023 10:39 AM
> To: Pierre Gondois ; devel@edk2.groups.io
> Cc: Yao, Jiewen ; Lu, Xiaoyu1 ;
> Jiang, Guomin ; Leif Lindholm
> ; Ard Biesheuvel ;
> Sami Mujawar ; Gerd Hoffmann
> 
> Subject: RE: [PATCH v1 0/7] CryptoPkg: Enable Openssl native instruction 
> support
> for AARCH64
> 
> Hi Pierre,
> 
> Could you share what tests you did and the test results?
> 
> Regards,
> Yi
> 
> -Original Message-
> From: Pierre Gondois 
> Sent: Thursday, November 2, 2023 9:54 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen ; Li, Yi1 ; Lu, 
> Xiaoyu1
> ; Jiang, Guomin ; Leif Lindholm
> ; Ard Biesheuvel ;
> Sami Mujawar ; Gerd Hoffmann
> 
> Subject: [PATCH v1 0/7] CryptoPkg: Enable Openssl native instruction support 
> for
> AARCH64
> 
> Various OpensslLib implementations are available in edk2. The
> OpensslLibAccel.inf and OpensslLibFullAccel.inf ones use architecture specific
> instructions, e.g. AESE, PMULL, SHA256H, ..., allowing to improve speed.
> 
> Enable support for Aarch64's native instructions:
> - Add ArmReadCntPctReg() and ArmReadIdAA64Isar0Reg() to
>   Aarch64's BaseLib.
> - Generate Aarch64's specific Openssl functions.
> - Add a OpensslStub/AArch64Cap.c file to allow Openssl
>   to probe Aarch64 native instruction support.
> 
> This patch-set only enable support for GCC for now (MSFT support not added).
> 
> Pierre Gondois (7):
>   MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()
>   MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()
>   MdePkg/BaseRngLib: Prefer ArmReadIdAA64Isar0Reg() over
> ArmReadIdIsar0()
>   CryptoPkg/OpensslLib: Add native instruction support for AARCH64
>   CryptoPkg/OpensslLib: Generate files for AARCH64 native support
>   CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
>   CryptoPkg: Enable Openssl Accel builds for AARCH64
> 
>  CryptoPkg/CryptoPkg.dsc   |   23 +-
>  .../AARCH64-GCC/crypto/aes/aesv8-armx.S   | 3180 
>  .../AARCH64-GCC/crypto/aes/vpaes-armv8.S  | 1196 +++
>  .../AARCH64-GCC/crypto/arm64cpuid.S   |  129 +
>  .../AARCH64-GCC/crypto/bn/armv8-mont.S| 2124 ++
>  .../crypto/ec/ecp_nistz256-armv8.S| 4242 +++
>  .../crypto/modes/aes-gcm-armv8_64.S   | 6389 +
>  .../AARCH64-GCC/crypto/modes/ghashv8-armx.S   |  552 ++
>  .../AARCH64-GCC/crypto/sha/keccak1600-armv8.S | 1009 +++
>  .../AARCH64-GCC/crypto/sha/sha1-armv8.S   | 1211 
>  .../AARCH64-GCC/crypto/sha/sha256-armv8.S | 2051 ++
>  .../AARCH64-GCC/crypto/sha/sha512-armv8.S | 1606 +
>  .../Library/OpensslLib/OpensslLibAccel.inf|  642 +-
>  .../OpensslLib/OpensslLibFullAccel.inf|  691 +-
>  .../OpensslLib/OpensslStub/AArch64Cap.c   |  107 +
>  CryptoPkg/Library/OpensslLib/UefiAsm.conf |6 +
>  CryptoPkg/Library/OpensslLib/configure.py |5 +-
>  CryptoPkg/Readme.md   |   14 +-
>  MdePkg/Include/Library/BaseLib.h  |   86 +
>  .../BaseLib/AArch64/ArmReadCntPctReg.S|   30 +
>  .../BaseLib/AArch64/ArmReadCntPctReg.asm  |   30 +
>  .../AArch64/ArmReadIdAA64Isar0Reg.S}  |   10 +-
>  .../AArch64/ArmReadIdAA64Isar0Reg.asm}|   10 +-
>  MdePkg/Library/BaseLib/BaseLib.inf|6 +-
>  MdePkg/Library/BaseRngLib/AArch64/ArmRng.h|   12 -
>  MdePkg/Library/BaseRngLib/AArch64/Rndr.c  |   14 +-
>  MdePkg/Library/BaseRngLib/BaseRngLib.inf  |2 -
>  27 files changed, 25320 insertions(+), 57 deletions(-)  create mode 100644
> CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-
> armx.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/aes/vpaes-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/arm64cpuid.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/bn/armv8-mont.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/ec/ecp_nistz256-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/modes/aes-gcm-armv8_64.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/modes/ghashv8-armx.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/sha/keccak1600-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/sha/sha1-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/sha/sha256-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-
> GCC/crypto/sha/sha512-armv8.S
>  create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
>  create mode 100644 

[edk2-devel] [PATCH v1] UefiCpuPkg/PiSmmCpuDxeSmm: Use processor extended information

[Wu, Jiaxin]

Processor extended information is filled when
CPU_V2_EXTENDED_TOPOLOGY is set in parameter ProcessorNumber
from GetProcessorInfo() (See commit: 1fadd18d).

This filed value is retrieved from CPUID leaf 1FH, which is
a preferred superset to leaf 0BH.

Since Intel recommends first use the CPUID leaf 1FH instead of
leaf 0BH, this patch change to use the processor extended
information, which can reflect the value from CPUID leaf 1FH.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Star Zeng 
Signed-off-by: Jiaxin Wu 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 10 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c  |  6 +++---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 391b64e9f2..c0485b0519 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -169,10 +169,20 @@ SmmAddProcessor (
 >ProcessorInfo[Index].Location.Package,
 >ProcessorInfo[Index].Location.Core,
 >ProcessorInfo[Index].Location.Thread
 );
 
+  GetProcessorLocation2ByApicId (
+(UINT32)ProcessorId,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Package,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Die,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Tile,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Module,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Core,
+
>ProcessorInfo[Index].ExtendedInformation.Location2.Thread
+);
+
   *ProcessorNumber = Index;
   gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
   return EFI_SUCCESS;
 }
   }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 25d058c5b9..c61562c867 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -177,11 +177,11 @@ IsPackageFirstThread (
   IN UINTN  CpuIndex
   )
 {
   UINT32  PackageIndex;
 
-  PackageIndex =  gSmmCpuPrivate->ProcessorInfo[CpuIndex].Location.Package;
+  PackageIndex =  
gSmmCpuPrivate->ProcessorInfo[CpuIndex].ExtendedInformation.Location2.Package;
 
   ASSERT (mPackageFirstThreadIndex != NULL);
 
   //
   // Set the value of mPackageFirstThreadIndex[PackageIndex].
@@ -1834,12 +1834,12 @@ InitPackageFirstThreadIndexInfo (
 
   //
   // Count the number of package, set to max PackageId + 1
   //
   for (Index = 0; Index < mNumberOfCpus; Index++) {
-if (PackageId < gSmmCpuPrivate->ProcessorInfo[Index].Location.Package) {
-  PackageId = gSmmCpuPrivate->ProcessorInfo[Index].Location.Package;
+if (PackageId < 
gSmmCpuPrivate->ProcessorInfo[Index].ExtendedInformation.Location2.Package) {
+  PackageId = 
gSmmCpuPrivate->ProcessorInfo[Index].ExtendedInformation.Location2.Package;
 }
   }
 
   PackageCount = PackageId + 1;
 
-- 
2.16.2.windows.1



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Re: [edk2-devel] [PATCH v1 0/7] CryptoPkg: Enable Openssl native instruction support for AARCH64

[Li, Yi]

Hi Pierre,

Could you share what tests you did and the test results?

Regards,
Yi

-Original Message-
From: Pierre Gondois  
Sent: Thursday, November 2, 2023 9:54 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen ; Li, Yi1 ; Lu, Xiaoyu1 
; Jiang, Guomin ; Leif Lindholm 
; Ard Biesheuvel ; Sami 
Mujawar ; Gerd Hoffmann 
Subject: [PATCH v1 0/7] CryptoPkg: Enable Openssl native instruction support 
for AARCH64

Various OpensslLib implementations are available in edk2. The 
OpensslLibAccel.inf and OpensslLibFullAccel.inf ones use architecture specific 
instructions, e.g. AESE, PMULL, SHA256H, ..., allowing to improve speed.

Enable support for Aarch64's native instructions:
- Add ArmReadCntPctReg() and ArmReadIdAA64Isar0Reg() to
  Aarch64's BaseLib.
- Generate Aarch64's specific Openssl functions.
- Add a OpensslStub/AArch64Cap.c file to allow Openssl
  to probe Aarch64 native instruction support.

This patch-set only enable support for GCC for now (MSFT support not added).

Pierre Gondois (7):
  MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()
  MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()
  MdePkg/BaseRngLib: Prefer ArmReadIdAA64Isar0Reg() over
ArmReadIdIsar0()
  CryptoPkg/OpensslLib: Add native instruction support for AARCH64
  CryptoPkg/OpensslLib: Generate files for AARCH64 native support
  CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
  CryptoPkg: Enable Openssl Accel builds for AARCH64

 CryptoPkg/CryptoPkg.dsc   |   23 +-
 .../AARCH64-GCC/crypto/aes/aesv8-armx.S   | 3180 
 .../AARCH64-GCC/crypto/aes/vpaes-armv8.S  | 1196 +++
 .../AARCH64-GCC/crypto/arm64cpuid.S   |  129 +
 .../AARCH64-GCC/crypto/bn/armv8-mont.S| 2124 ++
 .../crypto/ec/ecp_nistz256-armv8.S| 4242 +++
 .../crypto/modes/aes-gcm-armv8_64.S   | 6389 +
 .../AARCH64-GCC/crypto/modes/ghashv8-armx.S   |  552 ++
 .../AARCH64-GCC/crypto/sha/keccak1600-armv8.S | 1009 +++
 .../AARCH64-GCC/crypto/sha/sha1-armv8.S   | 1211 
 .../AARCH64-GCC/crypto/sha/sha256-armv8.S | 2051 ++
 .../AARCH64-GCC/crypto/sha/sha512-armv8.S | 1606 +
 .../Library/OpensslLib/OpensslLibAccel.inf|  642 +-
 .../OpensslLib/OpensslLibFullAccel.inf|  691 +-
 .../OpensslLib/OpensslStub/AArch64Cap.c   |  107 +
 CryptoPkg/Library/OpensslLib/UefiAsm.conf |6 +
 CryptoPkg/Library/OpensslLib/configure.py |5 +-
 CryptoPkg/Readme.md   |   14 +-
 MdePkg/Include/Library/BaseLib.h  |   86 +
 .../BaseLib/AArch64/ArmReadCntPctReg.S|   30 +
 .../BaseLib/AArch64/ArmReadCntPctReg.asm  |   30 +
 .../AArch64/ArmReadIdAA64Isar0Reg.S}  |   10 +-
 .../AArch64/ArmReadIdAA64Isar0Reg.asm}|   10 +-
 MdePkg/Library/BaseLib/BaseLib.inf|6 +-
 MdePkg/Library/BaseRngLib/AArch64/ArmRng.h|   12 -
 MdePkg/Library/BaseRngLib/AArch64/Rndr.c  |   14 +-
 MdePkg/Library/BaseRngLib/BaseRngLib.inf  |2 -
 27 files changed, 25320 insertions(+), 57 deletions(-)  create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S
 create mode 100644 
CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S
 create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
 create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S
 create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm
 rename MdePkg/Library/{BaseRngLib/AArch64/ArmReadIdIsar0.S => 
BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S} (70%)  rename 
MdePkg/Library/{BaseRngLib/AArch64/ArmReadIdIsar0.asm => 
BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm} (72%)

--
2.25.1



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Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

[Igor Kulchytskyy via groups.io]

Hi Abner,
Thanks for the explanation!
Will keep it without static.
Best regards,
Igor


Get Outlook for Android

From: Chang, Abner 
Sent: Monday, November 6, 2023 8:51:18 PM
To: Igor Kulchytskyy ; devel@edk2.groups.io 
; M M 
Cc: Nickle Wang 
Subject: RE: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: 
RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx


[AMD Official Use Only - General]


I would say to have static for a function used by module is a good coding 
practice and reduce the compile errors for the duplicated function naming, and 
maybe other advantages I am not quite sure.

But from edk2 C coding standard spec perspective, in 5.4.2.2.2, it says 
function should not be declared STATIC.

So my opinion is just keep the function without STATIC.



Abner





From: Igor Kulchytskyy 
Sent: Tuesday, November 7, 2023 2:54 AM
To: devel@edk2.groups.io; Igor Kulchytskyy ; M M 

Cc: Chang, Abner ; Nickle Wang 
Subject: RE: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: 
RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx



Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.



Hi Nickle and Abner,

What is your opinion – should we have GetHiIpProtocolType fuction as a static 
one?

Thank you,

Igor



From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Igor 
Kulchytskyy via groups.io
Sent: Monday, November 6, 2023 9:14 AM
To: M M mailto:mike.maslen...@gmail.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx





**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Mike,

See my comments below.

Thank you,

Igor

P.S.

“There is no limits to perfection”



From: M M mailto:mike.maslen...@gmail.com>>
Sent: Sunday, November 05, 2023 9:30 PM
To: Igor Kulchytskyy mailto:ig...@ami.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx



Hi Igor



I want to return to my initial comments regarding this patch.

Please, find my comments below.





On 1. 11. 2023., at 06:24, Igor Kulchytskyy 
mailto:ig...@ami.com>> wrote:



Hi Mike,
Thank you for review.
Please see my answers below the text.

-Original Message-
From: Mike Maslenkin mailto:mike.maslen...@gmail.com>>
Sent: Tuesday, October 31, 2023 9:00 PM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>
Cc: Abner Chang mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Igor

please find my comments below.

On Tue, Oct 31, 2023 at 8:56 PM Igor Kulchytskyy via 
groups.io
mailto:igork=ami@groups.io>> wrote:

Supported function of the driver changed to wait for all newtwork
interface to be installed.
Filer out the network interfaces which are not supported by
Redfish Host Interface.

Cc: Abner Chang mailto:abner.ch...@amd.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Cc: Igor Kulchytskyy mailto:ig...@ami.com>>
Signed-off-by: Igor Kulchytskyy mailto:ig...@ami.com>>
---
RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c | 96 ++--
1 file changed, 89 insertions(+), 7 deletions(-)

diff --git a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c 
b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
index 23da3b968f..a88ad55938 100644
--- a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
+++ b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
@@ -322,9 +322,15 @@ GetTargetNetworkInterfaceInternal (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+
  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
-if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0) 
{
+if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0 
&&
+((TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp6) ||
+(!TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp4))) {
  

[edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - Tuesday, November 7, 2023 #cal-reminder

[Group Notification]

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[edk2-devel] [PATCH v2] MdeModulePkg/PciHostBridgeDxe: Add readback after final Cfg-Write

[Joe L]

From: joelopez333 

REF:https://edk2.groups.io/g/devel/topic/102310377#110456

Problem Report:

On AARCH64, there is no ordering guarantee between configuration
space (ECAM) writes and memory space reads (MMIO). ARM AMBA CHI
only guarantees ordering for reads and writes within a single address 
region,
however, on some systems MMIO and ECAM may be split into separate
address regions.

A problem may arise when an ECAM write is issued a completion before a 
subsequent
MMIO read is issued and receives a completion.

For example, a typical PCI software flow is the following:

1. ECAM write to device command register to enable memory space
2. MMIO read from device memory space for which access was enabled
in step 1.

There is no guarantee that step 2. will not begin before the completion of 
step 1.
on systems where ECAM/MMIO are specified as separate address regions, even
if both spaces have the memory attributes device-nGnRnE.

Fix:

- Add a read after the final PCI Configuration space write
  in RootBridgeIoPciAccess.

- When configuration space is strongly ordered, this ensures
  that program execution cannot continue until the completion
  is received for the previous Cfg-Write, which may have side-effects.

- Risk of reading a "write-only" register and causing a CA which leaves the 
device
  unresponsive. The expectation based on the PCI Base Spec v6.1 section 7.4 
is that
  all PCI Spec-defined registers will be readable, however, there may exist
  design-specific registers that fall into this category.

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Cc: Jian J Wang 
Cc: Liming Gao 
Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Pedro Falcato 
Cc: Michael Brown 
Signed-off-by: Joe Lopez 
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 157a0ada80..c2dc2018d6 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -1238,6 +1238,14 @@ RootBridgeIoPciAccess (
 }
   }
 
+  //
+  // Perform readback after write to confirm completion was received for the 
last write
+  // before subsequent memory operations can be issued.
+  //
+  if (!Read) {
+PciSegmentRead8 (Address - InStride);
+  }
+
   return EFI_SUCCESS;
 }
 
-- 
2.25.1



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Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

I would say to have static for a function used by module is a good coding 
practice and reduce the compile errors for the duplicated function naming, and 
maybe other advantages I am not quite sure.
But from edk2 C coding standard spec perspective, in 5.4.2.2.2, it says 
function should not be declared STATIC.
So my opinion is just keep the function without STATIC.

Abner


From: Igor Kulchytskyy 
Sent: Tuesday, November 7, 2023 2:54 AM
To: devel@edk2.groups.io; Igor Kulchytskyy ; M M 

Cc: Chang, Abner ; Nickle Wang 
Subject: RE: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: 
RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.

Hi Nickle and Abner,
What is your opinion – should we have GetHiIpProtocolType fuction as a static 
one?
Thank you,
Igor

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Igor 
Kulchytskyy via groups.io
Sent: Monday, November 6, 2023 9:14 AM
To: M M mailto:mike.maslen...@gmail.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**
Hi Mike,
See my comments below.
Thank you,
Igor
P.S.
“There is no limits to perfection”

From: M M mailto:mike.maslen...@gmail.com>>
Sent: Sunday, November 05, 2023 9:30 PM
To: Igor Kulchytskyy mailto:ig...@ami.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx

Hi Igor

I want to return to my initial comments regarding this patch.
Please, find my comments below.


On 1. 11. 2023., at 06:24, Igor Kulchytskyy 
mailto:ig...@ami.com>> wrote:

Hi Mike,
Thank you for review.
Please see my answers below the text.

-Original Message-
From: Mike Maslenkin mailto:mike.maslen...@gmail.com>>
Sent: Tuesday, October 31, 2023 9:00 PM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>
Cc: Abner Chang mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Igor

please find my comments below.

On Tue, Oct 31, 2023 at 8:56 PM Igor Kulchytskyy via 
groups.io
mailto:igork=ami@groups.io>> wrote:

Supported function of the driver changed to wait for all newtwork
interface to be installed.
Filer out the network interfaces which are not supported by
Redfish Host Interface.

Cc: Abner Chang mailto:abner.ch...@amd.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Cc: Igor Kulchytskyy mailto:ig...@ami.com>>
Signed-off-by: Igor Kulchytskyy mailto:ig...@ami.com>>
---
RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c | 96 ++--
1 file changed, 89 insertions(+), 7 deletions(-)

diff --git a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c 
b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
index 23da3b968f..a88ad55938 100644
--- a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
+++ b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
@@ -322,9 +322,15 @@ GetTargetNetworkInterfaceInternal (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+
  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
-if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0) 
{
+if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0 
&&
+((TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp6) ||
+(!TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp4))) {
  return ThisNetworkInterface;
}

@@ -354,6 +360,10 @@ GetTargetNetworkInterfaceInternalByController (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+

I also have these two hunks in my pending list.
But I suggest to add ASSERT to GetTargetNetworkInterfaceInternal, just
because currently it is really impossible situation,
and mEfiRedfishDiscoverNetworkInterface was checked before in 

[edk2-devel] [PATCH v4] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET enable

[Wu, Jiaxin]

Root cause:
1. Before DisableReadonlyPageWriteProtect() is called, the return
address (#1) is pushed in shadow stack.
2. CET is disabled.
3. DisableReadonlyPageWriteProtect() returns to #1.
4. Page table is modified.
5. EnableReadonlyPageWriteProtect() is called, but the return
address (#2) is not pushed in shadow stack.
6. CET is enabled.
7. EnableReadonlyPageWriteProtect() returns to #2.
#CP exception happens because the actual return address (#2)
doesn't match the return address stored in shadow stack (#1).

Analysis:
Shadow stack will stop update after CET disable (DisableCet() in
DisableReadOnlyPageWriteProtect), but normal smi stack will be
continue updated with the function called and return
(DisableReadOnlyPageWriteProtect & EnableReadOnlyPageWriteProtect),
thus leading stack mismatch after CET re-enabled (EnableCet() in
EnableReadOnlyPageWriteProtect).

According SDM Vol 3, 6.15-Control Protection Exception:
Normal smi stack and shadow stack must be matched when CET enable,
otherwise CP Exception will happen, which is caused by a near RET
instruction.

CET is disabled in DisableCet(), while can be enabled in
EnableCet(). This way won't cause the problem because they are
implemented in a way that return address of DisableCet() is
poped out from shadow stack (Incsspq performs a pop to increases
the shadow stack) and EnableCet() doesn't use "RET" but "JMP" to
return to caller. So calling EnableCet() and DisableCet() doesn't
have the same issue as calling DisableReadonlyPageWriteProtect()
and EnableReadonlyPageWriteProtect().

With above root cause & analysis, define below 2 macros instead of
functions for WP & CET operation:
WRITE_UNPROTECT_RO_PAGES (Wp, Cet)
WRITE_PROTECT_RO_PAGES (Wp, Cet)
Because DisableCet() & EnableCet() must be in the same function
to avoid shadow stack and normal SMI stack mismatch.

Note: WRITE_UNPROTECT_RO_PAGES () must be called pair with
WRITE_PROTECT_RO_PAGES () in same function.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Zeng Star 
Cc: Gerd Hoffmann 
Cc: Rahul Kumar 
Cc: Laszlo Ersek 
Signed-off-by: Jiaxin Wu 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 59 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 73 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  7 ++-
 3 files changed, 81 insertions(+), 58 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 654935dc76..20ada465c2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1551,29 +1551,64 @@ VOID
 SmmWaitForApArrival (
   VOID
   );
 
 /**
-  Disable Write Protect on pages marked as read-only if Cr0.Bits.WP is 1.
+  Write unprotect read-only pages if Cr0.Bits.WP is 1.
+
+  @param[out]  WriteProtect  If Cr0.Bits.WP is enabled.
 
-  @param[out]  WpEnabled  If Cr0.WP is enabled.
-  @param[out]  CetEnabled If CET is enabled.
 **/
 VOID
-DisableReadOnlyPageWriteProtect (
-  OUT BOOLEAN  *WpEnabled,
-  OUT BOOLEAN  *CetEnabled
+SmmWriteUnprotectReadOnlyPage (
+  OUT BOOLEAN  *WriteProtect
   );
 
 /**
-  Enable Write Protect on pages marked as read-only.
+  Write protect read-only pages.
+
+  @param[in]  WriteProtect  If Cr0.Bits.WP should be enabled.
 
-  @param[out]  WpEnabled  If Cr0.WP should be enabled.
-  @param[out]  CetEnabled If CET should be enabled.
 **/
 VOID
-EnableReadOnlyPageWriteProtect (
-  BOOLEAN  WpEnabled,
-  BOOLEAN  CetEnabled
+SmmWriteProtectReadOnlyPage (
+  IN  BOOLEAN  WriteProtect
   );
 
+///
+/// Define macros to encapsulate the write unprotect/protect
+/// read-only pages.
+/// Below pieces of logic are defined as macros and not functions
+/// because "CET" feature disable & enable must be in the same
+/// function to avoid shadow stack and normal SMI stack mismatch,
+/// thus WRITE_UNPROTECT_RO_PAGES () must be called pair with
+/// WRITE_PROTECT_RO_PAGES () in same function.
+///
+/// @param[in,out] Wp   A BOOLEAN variable local to the containing
+/// function, carrying write protection status from
+/// WRITE_UNPROTECT_RO_PAGES() to
+/// WRITE_PROTECT_RO_PAGES().
+///
+/// @param[in,out] Cet  A BOOLEAN variable local to the containing
+/// function, carrying control flow integrity
+/// enforcement status from
+/// WRITE_UNPROTECT_RO_PAGES() to
+/// WRITE_PROTECT_RO_PAGES().
+///
+#define WRITE_UNPROTECT_RO_PAGES(Wp, Cet) \
+  do { \
+Cet = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0); \
+if (Cet) { \
+  DisableCet (); \
+} \
+SmmWriteUnprotectReadOnlyPage (); \
+  } while (FALSE)
+
+#define WRITE_PROTECT_RO_PAGES(Wp, Cet) \
+  do { \
+SmmWriteProtectReadOnlyPage (Wp); \
+if (Cet) { \
+  EnableCet (); \
+} \
+  } while (FALSE)
+
 #endif
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c 

Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg/MpInitLib: Use AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY leaf

[Michael D Kinney]

Hi Tom,

It likely would have been better to define AsmCpuid() to
set ECX=0.

However, how would new source code know if the BaseLib they 
linking against has this new behavior or not?

It is probably safer to do what you propose which is to use
AsmCpuidEx() that specifies exactly how ECX is set.

Mike


> -Original Message-
> From: Tom Lendacky 
> Sent: Monday, November 6, 2023 3:16 PM
> To: devel@edk2.groups.io; Kinney, Michael D
> ; Gao, Liming ; Liu,
> Zhiguang 
> Cc: Dong, Eric ; Ni, Ray ;
> Kumar, Rahul R ; Gerd Hoffmann
> ; Ard Biesheuvel ;
> Michael Roth 
> Subject: Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg/MpInitLib: Use
> AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY leaf
> 
> On 11/6/23 16:45, Lendacky, Thomas via groups.io wrote:
> > The CPUID_EXTENDED_TOPOLOGY CPUID leaf takes a subleaf as input when
> > returning CPUID information. However, the AsmCpuid() function does
> not
> > zero out ECX before the CPUID instruction, so the input leaf is used
> as
> > the sub-leaf for the CPUID request and returns erroneous/invalid
> CPUID
> > data, since the intent of the request was to get data related to
> sub-leaf
> > 0. Instead, use AsmCpuidEx() for the CPUID_EXTENDED_TOPOLOGY leaf.
> 
> Alternatively, the AsmCpuid() function could be changed to XOR ECX
> before
> invoking the CPUID instruction. This would ensure that the 0 sub-leaf
> is
> returned for any CPUID leaves that support sub-leaves. Thoughts?
> 
> Adding some additional maintainers for their thoughts, too.
> 
> Thanks,
> Tom
> 
> >
> > Fixes: d4d7c9ad5fe5 ("UefiCpuPkg/MpInitLib: use BSP to do extended
> ...")
> > Signed-off-by: Tom Lendacky 
> > ---
> >   UefiCpuPkg/Library/MpInitLib/AmdSev.c | 9 -
> >   1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
> b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
> > index bda4960f6fd3..d34f9513e002 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
> > @@ -256,7 +256,14 @@ FillExchangeInfoDataSevEs (
> > if (StdRangeMax >= CPUID_EXTENDED_TOPOLOGY) {
> >   CPUID_EXTENDED_TOPOLOGY_EBX  ExtTopoEbx;
> >
> > -AsmCpuid (CPUID_EXTENDED_TOPOLOGY, NULL, ,
> NULL, NULL);
> > +AsmCpuidEx (
> > +  CPUID_EXTENDED_TOPOLOGY,
> > +  0,
> > +  NULL,
> > +  ,
> > +  NULL,
> > +  NULL
> > +  );
> >   ExchangeInfo->ExtTopoAvail =
> !!ExtTopoEbx.Bits.LogicalProcessors;
> > }
> >   }


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Re: [edk2-devel] [PATCH v3 0/5] Designware MMCDXE changes and enhancement

[John Chew]

Hi Leif, Ard,

By any chance you have time to review this series of patches?

Thank you.

Regards,

John


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Re: [edk2-devel] [PATCH v4 0/8] Use CodeQL CLI

[Sean]

for the series

Reviewed-by: Sean Brogan 

Thanks

Sean

On 11/2/2023 1:03 PM, Michael Kubacki wrote:

From: Michael Kubacki 

CodeQL currently runs via the codeql-analysis.yml GitHub workflow
which uses the github/codeql-action/init@v2 action (pre-build)
and the github/codeql-action/analyze@v2 action (post-build) to
setup the CodeQL environment and extract results.

This infrastructure is removed in preparation for a new design that
will directly run the CodeQL CLI as part of the build. This will
allow CodeQL to be run locally as part of the normal build process
with results that match 1:1 with CI builds.

The CodeQL CLI design is automatically driven by a set of CodeQL
plugins:

   1. `CodeQlBuildPlugin` - Used to produce a CodeQL database from a
   build.
   2. `CodeQlAnalyzePlugin` - Used to analyze a CodeQL database.

This approach offers the following advantages:

   1. Provides exactly the same results locally as on a CI server.
   2. Integrates very well into IDEs such as VS Code.
   3. Very simple to use - just use normal Stuart update and build
  commands.
   4. Very simple to understand - minimally wraps the official CodeQL
  CLI.
   5. Very simple to integrate - works like any other Stuart build
  plugin.
   6. Portable - not tied to Azure DevOps specific, GitHub specific,
  or other host infrastructure.
   7. Versioned - the query and filters are versioned in source
  control so easy to find and track.

The appropriate CodeQL CLI is downloaded for the host OS by passing
the `--codeql` argument to the update command.

   `stuart_update -c .pytool/CISettings.py --codeql`

After that, CodeQL can be run in a build by similarly passing the
`--codeql` argument to the build command. For example:

   `stuart_ci_build -c .pytool/CISettings.py --codeql`

Going forward, CI will simply use those commands in CodeQL builds
to get results instead of the CodeQL GitHub actions.

When `--codeql` is specified in the build command, each package will
contain two main artifacts in the Build directory.

   1. The CodeQL database for the package
   2. The CodeQL SARIF (result) file for the package

The CodeQL database (1) can be used to run queries against without
rebuilding any code. The SARIF result file (2) is the result of
running enabled queries against the database.

SARIF stands for Static Analysis Results Interchange Format and it
is an industry standard format for output from static analysis tools.

https://sarifweb.azurewebsites.net/

The SARIF file can be opened with any standard SARIF file viewer
such as this one for VS Code:

https://marketplace.visualstudio.com/items?itemName=MS-SarifVSCode.sarif-viewer

That includes the ability to jump directly to issues in the source
code file with relevant code highlighted and suggestions included.

This means that after simply adding `--codeql` to the normal build
commands, a database will be present for future querying and a SARIF
result file will be present to allow the developer to immediately
start fixing issues.

More details about the location of these and usage is in the
BaseTools/Plugin/CodeQL/Readme.md included in this patch series.

The CI process pushes the SARIF file to GitHub Code Scanning so the
results are generated exactly the same way they are locally.

All build logs and the SARIF file for each package are uploaded to
the GitHub action run as artifacts. If a CodeQL issue is found, a
developer can download the SARIF file directly from the GitHub action
run to fix the problem without needing to rebuild locally.

An example run of these changes showing the packages built and output
logs and SARIF files is available here:

https://github.com/tianocore/edk2/actions/runs/6317077528

The series enables a new set of CodeQL queries that helps find useful
issues in the codebase. So, new CodeQL results will appear in the edk2
GitHub Code Scanning area after the change. It is expected that the
community will work together to prioritize and resolve issues to improve
the quality of the codebase.

V4 changes:

1. BaseTools/Plugin/CodeQL/analyze - Remove BSD-2-Clause Plus Patent
license. Drop Microsoft copyright. Clean up the licensing header
so its easier to read and follows the declaration provided in
https://www.apache.org/licenses/LICENSE-2.0.
2. Add a new patch to add the "analyze" directory under the list of
paths in the project with an acceptable but different license
than BSD-2-Clause Plus Patent.

V3 changes:

1. Add a "Resolution Guidelines" section to the CodeQL plugin readme
file based on feedback in the October 16, 2023 Tianocore Tools &
CI meeting to capture some notes useful in solving issues in the
file.

V2 Changes:

1. Enable CodeQL audit mode. This is because a new patch also enables
queries that will result in unresolved issues so audit mode is needed
for the build to succeed.
2. Enable new CodeQL queries. This will enable new CodeQL queries so the
issues are easier to find 

Re: [edk2-devel] [PATCH v4 6/8] .pytool/CISettings: Enable CodeQL audit mode

[Sean]

Reviewed-by: Sean Brogan 

On 11/2/2023 1:03 PM, Michael Kubacki wrote:

From: Michael Kubacki 

Since a large number of CodeQL queries are being enabled to identify
issues that the community can collectively resolve, audit mode needs to
be enabled to prevent the build from failing.

In the future, this global audit mode can be disabled and individual
packages can enable/disable audit mode in their package CI YAML file
using the instructions in the CodeQL plugin readme.

Cc: Sean Brogan 
Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Michael Kubacki 
Acked-by: Michael D Kinney 
---
  .pytool/CISettings.py | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py
index b8b8080439c1..ec3beb0dcf9d 100644
--- a/.pytool/CISettings.py
+++ b/.pytool/CISettings.py
@@ -196,6 +196,12 @@ class Settings(CiBuildSettingsManager, 
UpdateSettingsManager, SetupSettingsManag
  
  try:

  scopes += codeql_helpers.get_scopes(self.codeql)
+
+if self.codeql:
+shell_environment.GetBuildVars().SetValue(
+"STUART_CODEQL_AUDIT_ONLY",
+"TRUE",
+"Set in CISettings.py")
  except NameError:
  pass
  



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Re: [edk2-devel] [PATCH v4 7/8] BaseTools/Plugin/CodeQL: Enable 30 queries

[Sean]

Reviewed-by: Sean Brogan 

On 11/2/2023 1:03 PM, Michael Kubacki wrote:

From: Michael Kubacki 

Updates the CodeQL queries opted into by edk2 to a set of queries from
the standard CodeQL query package `codeql/cpp-queries`.

After testing a large number of queries the included set here were
found to be the most useful with the least number of false positives.
Some queries had a number of issues that led to them being placed on
the exclusion list so that they are not considered in the future
without the notes there being taken into account.

General details about queries available in the pack are available here:
https://codeql.github.com/codeql-query-help/cpp/

The issues found by these queries will need to be fixed over time. In
the meantime, the results will show to those that have permission in
the repo's GitHub Code Scanning area. The build will not fail due to
CodeQL issues (since they are not all fixed) but that can be enabled in
the future.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Rebecca Cran 
Cc: Sean Brogan 
Cc: Yuwei Chen 
Signed-off-by: Michael Kubacki 
Acked-by: Michael D Kinney 
---
  BaseTools/Plugin/CodeQL/CodeQlQueries.qls | 57 +---
  1 file changed, 50 insertions(+), 7 deletions(-)

diff --git a/BaseTools/Plugin/CodeQL/CodeQlQueries.qls 
b/BaseTools/Plugin/CodeQL/CodeQlQueries.qls
index 3f97bcd583d5..1a5098322193 100644
--- a/BaseTools/Plugin/CodeQL/CodeQlQueries.qls
+++ b/BaseTools/Plugin/CodeQL/CodeQlQueries.qls
@@ -8,28 +8,71 @@
  # Queries
  
##
  
-## Enable When Time is Available to Fix Issues

-# Hundreds of issues. Most appear valid. Type: Recommendation.
-#- include:
-#id: cpp/missing-null-test
-
  ## Errors
  - include:
-id: cpp/overrunning-write
+id: cpp/badoverflowguard
  - include:
-id: cpp/overrunning-write-with-float
+id: cpp/infiniteloop
+- include:
+id: 
cpp/likely-bugs/memory-management/v2/conditionally-uninitialized-variable
+- include:
+id: cpp/missing-null-test
+- include:
+id: cpp/missing-return
+- include:
+id: cpp/no-space-for-terminator
  - include:
  id: cpp/pointer-overflow-check
+- include:
+id: cpp/redundant-null-check-simple
+- include:
+id: cpp/sizeof/const-int-argument
+- include:
+id: cpp/sizeof/sizeof-or-operation-as-argument
+- include:
+id: cpp/unguardednullreturndereferenc
  - include:
  id: cpp/very-likely-overrunning-write
  
  ## Warnings

+- include:
+id: cpp/comparison-with-wider-type
  - include:
  id: cpp/conditionallyuninitializedvariable
+- include:
+id: cpp/comparison-precedence
+- include:
+id: cpp/implicit-bitfield-downcast
  - include:
  id: cpp/infinite-loop-with-unsatisfiable-exit-condition
+- include:
+id: cpp/offset-use-before-range-check
  - include:
  id: cpp/overflow-buffer
+- include:
+id: cpp/overflow-calculated
+- include:
+id: cpp/overflow-destination
+- include:
+id: cpp/paddingbyteinformationdisclosure
+- include:
+id: cpp/return-stack-allocated-memory
+- include:
+id: cpp/static-buffer-overflow
+- include:
+id: cpp/unsigned-comparison-zero
+- include:
+id: cpp/uselesstest
+
+## Recommendations
+- include:
+id: cpp/missing-header-guard
+- include:
+id: cpp/unused-local-variable
+- include:
+id: cpp/unused-static-function
+- include:
+id: cpp/unused-static-variable
  
  # Note: Some queries above are not active by default with the below filter.

  #   Update the filter and run the queries again to get all results.



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[edk2-devel] Now: Tools, CI, Code base construction meeting series - Monday, November 6, 2023 #cal-notice

[Group Notification]

*Tools, CI, Code base construction meeting series*

*When:*
Monday, November 6, 2023
4:30pm to 5:30pm
(UTC-08:00) America/Los Angeles

*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f988bf-86f1-41af-91ab-2d7cd011db47%22%2c%22Oid%22%3a%2223af6561-6e1c-450d-b917-d9d674eb3cb6%22%7d

View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=2072477 )

*Description:*

TianoCore community,

Microsoft and Intel will be hosting a series of open meetings to discuss build, 
CI, tools, and other related topics. If you are interested, have ideas/opinions 
please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft 
Teams.

MS Teams Link in following discussion: * 
https://github.com/tianocore/edk2/discussions/2614

Anyone is welcome to join.

* tianocore/edk2: EDK II (github.com)
* tianocore/edk2-basetools: EDK II BaseTools Python tools as a PIP module 
(github.com) https://github.com/tianocore/edk2-basetools
* tianocore/edk2-pytool-extensions: Extensions to the edk2 build system 
allowing for a more robust and plugin based build system and tool execution 
environment (github.com) https://github.com/tianocore/edk2-pytool-extensions
* tianocore/edk2-pytool-library: Python library package that supports UEFI 
development (github.com) https://github.com/tianocore/edk2-pytool-library

MS Teams Browser Clients * 
https://docs.microsoft.com/en-us/microsoftteams/get-clients?tabs=Windows#browser-client


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[edk2-devel] Event: Tools, CI, Code base construction meeting series - Monday, November 6, 2023 #cal-reminder

[Group Notification]

*Reminder: Tools, CI, Code base construction meeting series*

*When:*
Monday, November 6, 2023
4:30pm to 5:30pm
(UTC-08:00) America/Los Angeles

*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f988bf-86f1-41af-91ab-2d7cd011db47%22%2c%22Oid%22%3a%2223af6561-6e1c-450d-b917-d9d674eb3cb6%22%7d

View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=2072477 )

*Description:*

TianoCore community,

Microsoft and Intel will be hosting a series of open meetings to discuss build, 
CI, tools, and other related topics. If you are interested, have ideas/opinions 
please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft 
Teams.

MS Teams Link in following discussion: * 
https://github.com/tianocore/edk2/discussions/2614

Anyone is welcome to join.

* tianocore/edk2: EDK II (github.com)
* tianocore/edk2-basetools: EDK II BaseTools Python tools as a PIP module 
(github.com) https://github.com/tianocore/edk2-basetools
* tianocore/edk2-pytool-extensions: Extensions to the edk2 build system 
allowing for a more robust and plugin based build system and tool execution 
environment (github.com) https://github.com/tianocore/edk2-pytool-extensions
* tianocore/edk2-pytool-library: Python library package that supports UEFI 
development (github.com) https://github.com/tianocore/edk2-pytool-library

MS Teams Browser Clients * 
https://docs.microsoft.com/en-us/microsoftteams/get-clients?tabs=Windows#browser-client


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Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg/MpInitLib: Use AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY leaf

[Lendacky, Thomas via groups.io]

On 11/6/23 16:45, Lendacky, Thomas via groups.io wrote:

The CPUID_EXTENDED_TOPOLOGY CPUID leaf takes a subleaf as input when
returning CPUID information. However, the AsmCpuid() function does not
zero out ECX before the CPUID instruction, so the input leaf is used as
the sub-leaf for the CPUID request and returns erroneous/invalid CPUID
data, since the intent of the request was to get data related to sub-leaf
0. Instead, use AsmCpuidEx() for the CPUID_EXTENDED_TOPOLOGY leaf.


Alternatively, the AsmCpuid() function could be changed to XOR ECX before 
invoking the CPUID instruction. This would ensure that the 0 sub-leaf is 
returned for any CPUID leaves that support sub-leaves. Thoughts?


Adding some additional maintainers for their thoughts, too.

Thanks,
Tom



Fixes: d4d7c9ad5fe5 ("UefiCpuPkg/MpInitLib: use BSP to do extended ...")
Signed-off-by: Tom Lendacky 
---
  UefiCpuPkg/Library/MpInitLib/AmdSev.c | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c 
b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
index bda4960f6fd3..d34f9513e002 100644
--- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
+++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
@@ -256,7 +256,14 @@ FillExchangeInfoDataSevEs (
if (StdRangeMax >= CPUID_EXTENDED_TOPOLOGY) {
  CPUID_EXTENDED_TOPOLOGY_EBX  ExtTopoEbx;
  
-AsmCpuid (CPUID_EXTENDED_TOPOLOGY, NULL, , NULL, NULL);

+AsmCpuidEx (
+  CPUID_EXTENDED_TOPOLOGY,
+  0,
+  NULL,
+  ,
+  NULL,
+  NULL
+  );
  ExchangeInfo->ExtTopoAvail = !!ExtTopoEbx.Bits.LogicalProcessors;
}
  }



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Re: [edk2-devel] [PATCH v3 0/2] Automatically set NXCOMPAT bit if requirements are met

[Joey Vagedes via groups.io]

Thank you, Rebecca!


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Re: [edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify make error

[Joey Vagedes via groups.io]

I made a recent change to how I use git send-email:

I follow Laszlo's unkempt git guide for edk2 contributors and maintainers. 
There was a recent update to add --transfer-encoding=base64 to the git 
send-email command. My guess is that caused the random data. I do not see that 
data on the "send" side in my outbox, however.

https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers/_compare/385073186afb8dd7cb8af4c9fcd96d86423fd9d3

Joey

-Original Message-
From: Kinney, Michael D  
Sent: Monday, November 6, 2023 1:54 PM
To: devel@edk2.groups.io; Joey Vagedes 
Cc: Kinney, Michael D 
Subject: [EXTERNAL] RE: [edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify 
make error

What is the random data at the end of your path emails???

Thanks,

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Joey 
> Vagedes via groups.io
> Sent: Monday, November 6, 2023 12:09 PM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify make 
> error
> 
> When make or nmake fails to build the basetools, Edk2ToolsBuild.py 
> currently prints a generic error message "Failed to build." and raises 
> an exception. This has two issues: The first is that it raises an 
> exception, which leads people to believe it is a python issue, and not 
> a build issue. The second is that users don't necessarily know to 
> check the build log if this error occurs.
> 
> This has been reported many times through many different avenues:
> 
> https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Ftianocore%2Fedk2%2Fdiscussions%2F4611=05%7C01%7Cjoeyvage
> des%40microsoft.com%7C271dfa9b91c844696b5808dbdf12e82c%7C72f988bf86f14
> 1af91ab2d7cd011db47%7C1%7C0%7C638349044524508743%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000%7C%7C%7C=5aewZruHiYbB9dBtbVegXeJmDdMre5oWasFWCnSmYDc%3D
> eserved=0
> https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fstac
> koverflow.com%2Fquestions%2F77421168%2Fedkii-base-tools-fails-=05
> %7C01%7Cjoeyvagedes%40microsoft.com%7C271dfa9b91c844696b5808dbdf12e82c
> %7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C638349044524515634%7CUnk
> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWw
> iLCJXVCI6Mn0%3D%7C3000%7C%7C%7C=P2GDkAZrpm1pZHE9Vl4RKLszDTEzAGW7
> xF5Wh%2Byakkw%3D=0
> to-build
> https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Ftianocore%2Fedk2-pytool-extensions%2Fissues%2F180=05%7C0
> 1%7Cjoeyvagedes%40microsoft.com%7C271dfa9b91c844696b5808dbdf12e82c%7C7
> 2f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C638349044524521511%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ
> XVCI6Mn0%3D%7C3000%7C%7C%7C=uahh%2FKPyyLsf19R0WLszjkWGRg6x3jVLq7
> GDGuBdS4o%3D=0
> https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Ftianocore%2Fedk2-pytool-extensions%2Fissues%2F207=05%7C0
> 1%7Cjoeyvagedes%40microsoft.com%7C271dfa9b91c844696b5808dbdf12e82c%7C7
> 2f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C638349044524526191%7CUnknown
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ
> XVCI6Mn0%3D%7C3000%7C%7C%7C=MvX3P5bYPvwI7z%2BDiy%2Bbezj0kBEx51RQ
> GTkoS6WUiDI%3D=0
> 
> This patch series changes the exception to a error log so that the 
> invocable completes and returns a non-zero exit code and also logs a 
> more descriptive error that informs the user to review the build log, 
> and where to find it.
> 
> Joey Vagedes (1):
>   BaseTools: Edk2ToolsBuild.py: Clarify make error
> 
>  BaseTools/Source/C/Common/BinderFuncs.c | 2 +-
>  BaseTools/Edk2ToolsBuild.py | 8 ++--
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> --
> 2.34.1
> 
> ®‹©²*
> Šy,b‹«yÇ¢½æ¥–g¬±¨²Ç§¶Ú-†+ ®‹©V'°ý©—#§–)Þ×];çˆm¶›?ýçdÚ èº›"£ø?uëÞ— 
> ùž²Æ {ýuÓ¾x2ë^N¬NŠbrm¦Ïÿ‚º.¦È¨þk×M¸ÛÎüïýzã~=èj躓°êÝz÷¥úŒ'z·“h+¢ê
> lŠ…'²æìr¸›zm¦ÏÿyÙ6‚º.¦È¨þÝz÷¥þéì¹¹¢rž•Ù"žw²Š{^•Ê&


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[edk2-devel] [PATCH 2/2] UefiCpuPkg/MpInitLib: Copy SEV-ES save area pointer during APIC ID sorting

[Lendacky, Thomas via groups.io]

With SEV-SNP, the SEV-ES save area for a vCPU should be unique to that
vCPU. After commit 3323359a811a, the VMSA allocation was re-used, but when
sorting the CPUs by APIC ID, the save area was not updated to follow the
original CPU. Similar to the StartupApSignal address, the SevEsSaveArea
address should be updated when sorting the CPUs.

This does not cause an issue at this time because all APs are in HLT state
and then are (re)started at the same time, with the same VMSA contents.
However, this should be fixed to account for any change in future
behavior.

Fixes: 3323359a811a ("UefiCpuPkg/MpInitLib: Reuse VMSA allocation to ...")
Signed-off-by: Tom Lendacky 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 9a6ec5db5ce9..a41b9e5701af 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -370,6 +370,7 @@ SortApicId (
   UINT32   ApCount;
   CPU_INFO_IN_HOB  *CpuInfoInHob;
   volatile UINT32  *StartupApSignal;
+  VOID *SevEsSaveArea;
 
   ApCount  = CpuMpData->CpuCount - 1;
   CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
@@ -397,12 +398,17 @@ SortApicId (
 CopyMem ([Index1], , sizeof (CPU_INFO_IN_HOB));
 
 //
-// Also exchange the StartupApSignal.
+// Also exchange the StartupApSignal and SevEsSaveArea.
 //
 StartupApSignal= 
CpuMpData->CpuData[Index3].StartupApSignal;
 CpuMpData->CpuData[Index3].StartupApSignal =
   CpuMpData->CpuData[Index1].StartupApSignal;
 CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal;
+
+SevEsSaveArea= 
CpuMpData->CpuData[Index3].SevEsSaveArea;
+CpuMpData->CpuData[Index3].SevEsSaveArea =
+  CpuMpData->CpuData[Index1].SevEsSaveArea;
+CpuMpData->CpuData[Index1].SevEsSaveArea = SevEsSaveArea;
   }
 }
 
-- 
2.42.0



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[edk2-devel] [PATCH 1/2] UefiCpuPkg/MpInitLib: Use AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY leaf

[Lendacky, Thomas via groups.io]

The CPUID_EXTENDED_TOPOLOGY CPUID leaf takes a subleaf as input when
returning CPUID information. However, the AsmCpuid() function does not
zero out ECX before the CPUID instruction, so the input leaf is used as
the sub-leaf for the CPUID request and returns erroneous/invalid CPUID
data, since the intent of the request was to get data related to sub-leaf
0. Instead, use AsmCpuidEx() for the CPUID_EXTENDED_TOPOLOGY leaf.

Fixes: d4d7c9ad5fe5 ("UefiCpuPkg/MpInitLib: use BSP to do extended ...")
Signed-off-by: Tom Lendacky 
---
 UefiCpuPkg/Library/MpInitLib/AmdSev.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/AmdSev.c 
b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
index bda4960f6fd3..d34f9513e002 100644
--- a/UefiCpuPkg/Library/MpInitLib/AmdSev.c
+++ b/UefiCpuPkg/Library/MpInitLib/AmdSev.c
@@ -256,7 +256,14 @@ FillExchangeInfoDataSevEs (
   if (StdRangeMax >= CPUID_EXTENDED_TOPOLOGY) {
 CPUID_EXTENDED_TOPOLOGY_EBX  ExtTopoEbx;
 
-AsmCpuid (CPUID_EXTENDED_TOPOLOGY, NULL, , NULL, NULL);
+AsmCpuidEx (
+  CPUID_EXTENDED_TOPOLOGY,
+  0,
+  NULL,
+  ,
+  NULL,
+  NULL
+  );
 ExchangeInfo->ExtTopoAvail = !!ExtTopoEbx.Bits.LogicalProcessors;
   }
 }
-- 
2.42.0



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[edk2-devel] [PATCH 0/2] SEV-SNP guest support fixes

[Lendacky, Thomas via groups.io]

This patch series provides fixes around AP startup and sorting:

- The CPUID_EXTENDED_TOPOLOGY CPUID leaf takes a sub-leaf as input. The
  current SEV-SNP support is attempting to retrieve the this leaf with
  sub-leaf 0, but is calling AsmCpuid(), which does not clear ECX before
  invoking the CPUID instruction. Therefore, because of the calling
  convention, the leaf value becomes the sub-leaf value and ends up
  returning incorrect information. Change the call from AsmCpuid() to
  AsmCpuidEx().

- When sorting the CPUs by APIC ID, the VMSA associated with the vCPU
  should follow the APIC ID. Update the sorting code to swap the VMSA
  pointer during the sort.

---

These patches are based on commit:
da219919538b ("BaseTools: GenFw: auto-set nxcompat flag")

Tom Lendacky (2):
  UefiCpuPkg/MpInitLib: Use AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY
leaf
  UefiCpuPkg/MpInitLib: Copy SEV-ES save area pointer during APIC ID
sorting

 UefiCpuPkg/Library/MpInitLib/AmdSev.c | 9 -
 UefiCpuPkg/Library/MpInitLib/MpLib.c  | 8 +++-
 2 files changed, 15 insertions(+), 2 deletions(-)

-- 
2.42.0



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Re: [edk2-devel] [PATCH V1] MdePkg:Add NVME Sanitize command support to Nvme.h

[Michael D Kinney]

Please update the Nvme.h file header that the version being
used is 2.0c.

Thanks,

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Tina
> Chen
> Sent: Monday, November 6, 2023 6:01 AM
> To: devel@edk2.groups.io
> Cc: Chen, Tina ; Chen, Xiao X
> ; Chen, Arthur G ; Ni,
> Ray ; Gao, Liming 
> Subject: [edk2-devel] [PATCH V1] MdePkg:Add NVME Sanitize command
> support to Nvme.h
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591
> 
> 1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related
> definition.
> 2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related
> definition for Sanitize status support.
> 
> Cc: Xiao X Chen 
> Cc: Arthur Chen 
> Cc: Ray Ni 
> Cc: Liming Gao 
> Signed-off-by: Tina Chen 
> ---
>  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c|   1 +
>  MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c |   1 +
>  MdePkg/Include/IndustryStandard/Nvme.h| 106
> ++--
>  3 files changed, 98 insertions(+), 10 deletions(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
> b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
> index b90c48731c..2ecaa2bbbe 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
> @@ -908,6 +908,7 @@ NvmeControllerInit (
>DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", Private-
> >ControllerData->Rab));
> 
>DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 *)Private-
> >ControllerData->Ieee_oui));
> 
>DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", Private-
> >ControllerData->Aerl));
> 
> +  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", Private-
> >ControllerData->Sanicap));
> 
>DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", Private-
> >ControllerData->Sqes));
> 
>DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", Private-
> >ControllerData->Cqes));
> 
>DEBUG ((DEBUG_INFO, "NN: 0x%x\n", Private-
> >ControllerData->Nn));
> 
> diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
> b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
> index fc7b684940..61ef06e42f 100644
> --- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
> +++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
> @@ -436,6 +436,7 @@ NvmeDumpControllerData (
>DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", ControllerData-
> >Rab));
> 
>DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32
> *)ControllerData->Ieee_oui));
> 
>DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", ControllerData-
> >Aerl));
> 
> +  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", ControllerData-
> >Sanicap));
> 
>DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", ControllerData-
> >Sqes));
> 
>DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", ControllerData-
> >Cqes));
> 
>DEBUG ((DEBUG_INFO, "NN: 0x%x\n", ControllerData->Nn));
> 
> diff --git a/MdePkg/Include/IndustryStandard/Nvme.h
> b/MdePkg/Include/IndustryStandard/Nvme.h
> index 8b8a1bb7f3..d158d6c267 100644
> --- a/MdePkg/Include/IndustryStandard/Nvme.h
> +++ b/MdePkg/Include/IndustryStandard/Nvme.h
> @@ -403,7 +403,15 @@ typedef struct {
>UINT16   Edstt;   /* Extended Device Self-test Time
> */
> 
>UINT8Dsto;/* Device Self-test Options  */
> 
>UINT8Fwug;/* Firmware Update Granularity */
> 
> -  UINT8Rsvd2[192];  /* Reserved as of Nvm Express 1.4
> Spec */
> 
> +  UINT16   Kas; /* Keep Alive Support */
> 
> +  UINT16   Hctma;   /* Host Controlled Thermal
> Management Attributes */
> 
> +  UINT16   Mntmt;   /* Minimum Thermal Management
> Temperature */
> 
> +  UINT16   Mxtmt;   /* Maximum Thermal Management
> Temperature */
> 
> +  UINT32   Sanicap; /* Sanitize Capabilities */
> 
> +  #define SANITIZE_OVERWRITE_ERASE_SUPPORTED  BIT2
> 
> +  #define SANITIZE_BLOCK_ERASE_SUPPORTED  BIT1
> 
> +  #define SANITIZE_CRYPTO_ERASE_SUPPORTED BIT0
> 
> +  UINT8Rsvd2[180];  /* Reserved as of Nvm Express 1.4
> Spec */
> 
>//
> 
>// NVM Command Set Attributes
> 
>//
> 
> @@ -687,10 +695,11 @@ typedef struct {
>// CDW 10
> 
>//
> 
>UINT32Lid   : 8;/* Log Page Identifier */
> 
> -  #define LID_ERROR_INFO0x1
> 
> -  #define LID_SMART_INFO0x2
> 
> -  #define LID_FW_SLOT_INFO  0x3
> 
> -  #define LID_BP_INFO   0x15
> 
> +  #define LID_ERROR_INFO0x1
> 
> +  #define LID_SMART_INFO0x2
> 
> +  #define LID_FW_SLOT_INFO  0x3
> 
> +  #define LID_BP_INFO   0x15
> 
> +  #define LID_SANITIZE_STATUS_INFO  0x81
> 
>UINT32Rsvd1 : 8;
> 
>UINT32Numd  : 12;   /* Number of Dwords */
> 
>UINT32Rsvd2 : 4;/* Reserved as of Nvm Express 1.1 Spec
> */
> 
> @@ -708,6 +717,25 @@ typedef struct {
>UINT32Sv: 1; 

Re: [edk2-devel] [PATCH 1/1] ShellPkg: Fix typos

[Michael D Kinney]

Reviewed-by: Michael D Kinney 


> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Page
> Chen via groups.io
> Sent: Monday, November 6, 2023 12:43 PM
> To: devel@edk2.groups.io
> Cc: Page Chen ; Gao, Zhichao
> ; Andrew Fish 
> Subject: [edk2-devel] [PATCH 1/1] ShellPkg: Fix typos
> 
> begining->beginning
> dirve->drive
> duplicat->duplicate
> fuly->fully
> Funciton->Function
> Functino->Function
> optioanl->optional
> poitners->pointers
> rountine->routine
> sucessful->successful
> sucessfully->successfully
> 
> Signed-off-by: Page Chen 
> Cc: Zhichao Gao 
> Cc: Andrew Fish 
> ---
>  .../HttpDynamicCommand/HttpApp.c  |  2 +-
>  .../HttpDynamicCommand/HttpDynamicCommand.c   |  4 +-
>  ShellPkg/Include/Library/BcfgCommandLib.h |  2 +-
>  ShellPkg/Include/Library/HandleParsingLib.h   |  2 +-
>  ShellPkg/Include/Library/ShellCommandLib.h|  6 +--
>  ShellPkg/Include/Library/ShellLib.h   | 30 +++---
>  .../Include/Protocol/EfiShellEnvironment2.h   | 10 ++---
>  .../UefiHandleParsingLib.c| 16 
>  .../UefiShellBcfgCommandLib.c | 20 +-
>  .../UefiShellCommandLib/UefiShellCommandLib.c |  6 +--
>  .../UefiShellDebug1CommandsLib/Compress.c |  2 +-
>  .../UefiShellDebug1CommandsLib/Compress.h |  2 +-
>  .../UefiShellDebug1CommandsLib.c  |  2 +-
>  .../UefiShellDriver1CommandsLib.c |  2 +-
>  .../UefiShellInstall1CommandsLib.c|  2 +-
>  .../UefiShellLevel1CommandsLib.c  |  4 +-
>  .../UefiShellLevel1CommandsLib.h  |  2 +-
>  .../Library/UefiShellLevel2CommandsLib/Cd.c   |  4 +-
>  .../Library/UefiShellLevel2CommandsLib/Ls.c   |  2 +-
>  .../Library/UefiShellLevel2CommandsLib/Map.c  |  2 +-
>  .../Library/UefiShellLevel2CommandsLib/Mv.c   |  6 +--
>  .../Library/UefiShellLevel2CommandsLib/Set.c  |  2 +-
>  .../UefiShellLevel2CommandsLib.c  |  8 ++--
>  .../UefiShellLevel2CommandsLib.h  |  6 +--
>  .../Library/UefiShellLevel2CommandsLib/Vol.c  |  2 +-
>  .../UefiShellLevel3CommandsLib/Alias.c|  4 +-
>  .../UefiShellLevel3CommandsLib/Touch.c|  4 +-
>  .../Library/UefiShellLevel3CommandsLib/Type.c |  4 +-
>  .../UefiShellLevel3CommandsLib.c  |  2 +-
>  ShellPkg/Library/UefiShellLib/UefiShellLib.c  | 40 +-
> -
>  .../UefiShellNetwork1CommandsLib/Ping.c   |  2 +-
>  .../UefiShellNetwork1CommandsLib.c|  2 +-
>  .../UefiShellNetwork2CommandsLib/Ping6.c  |  2 +-
>  .../UefiShellNetwork2CommandsLib.c|  2 +-
>  34 files changed, 104 insertions(+), 104 deletions(-)
> 
> diff --git a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
> b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
> index 6622e058aab6..ea41417fc3d6 100644
> --- a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
> +++ b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
> @@ -28,7 +28,7 @@ EFI_STRING_ID  mStringHelpTokenId = STRING_TOKEN
> (STR_GET_HELP_HTTP);
>@param ImageHandleThe image handle of the process.
> 
>@param SystemTableThe EFI System Table pointer.
> 
> 
> 
> -  @retval EFI_SUCCESS   Http command is executed sucessfully.
> 
> +  @retval EFI_SUCCESS   Http command is executed
> successfully.
> 
>@retval EFI_ABORTED   HII package was failed to initialize.
> 
>@retval othersOther errors when executing http
> command.
> 
>  **/
> 
> diff --git
> a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
> b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
> index 45aeaac347ad..d3c384dc8b8a 100644
> --- a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
> +++ b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
> @@ -22,7 +22,7 @@
>@param[in] Shell  The instance of the shell protocol
> used in
> 
>  the context of processing this
> command.
> 
> 
> 
> -  @return EFI_SUCCESS   the operation was sucessful
> 
> +  @return EFI_SUCCESS   the operation was successful
> 
>@return other the operation failed.
> 
>  **/
> 
>  SHELL_STATUS
> 
> @@ -78,7 +78,7 @@ EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL
> mHttpDynamicCommand = {
>@param ImageHandleThe image handle of the process.
> 
>@param SystemTableThe EFI System Table pointer.
> 
> 
> 
> -  @retval EFI_SUCCESS   Http command is executed sucessfully.
> 
> +  @retval EFI_SUCCESS   Http command is executed
> successfully.
> 
>@retval EFI_ABORTED   HII package was failed to initialize.
> 
>@retval othersOther errors when executing http
> command.
> 
>  **/
> 
> diff --git a/ShellPkg/Include/Library/BcfgCommandLib.h
> b/ShellPkg/Include/Library/BcfgCommandLib.h
> index ec5579ce614a..649fe00f98a2 100644
> --- 

Re: [edk2-devel] [PATCH v3 0/2] Automatically set NXCOMPAT bit if requirements are met

[Rebecca Cran]

Committed as:
e53c618ea4928820eea5a6d778395ce1e6145cbc
da219919538b679d5cf7387f4eba6c20384bf868


On 7/13/2023 9:24 AM, Joey Vagedes via groups.io wrote:

v3: Updates function to be Doxygen compliant
v3: Updates commit message

v2: Adds --nonxcompat flag to GenFw; updates man page
v2: Updates PeImage.h to reference spec 9.3 rather then 8.3

Utilize GenFw to automatically set the NXCOMPAT bit of the DLL Characteristics
field of the Optional Header if the following requirements are met:

1. It is a 64bit PE
2. The section alignment is evently divisible by 4K
3. No section is both EFI_IMAGE_SCN_MEM_EXECUTE and EFI_IMAGE_SCN_MEM_WRITE

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 

Joey Vagedes (2):
   MdePkg: IndustryStandard: Add DLL Characteristics
   BaseTools: GenFw: auto-set nxcompat flag

  MdePkg/Include/IndustryStandard/PeImage.h|  17 +-
  BaseTools/Source/C/GenFw/GenFw.c |  69 
  BaseTools/UserManuals/GenFw_Utility_Man_Page.rtf | 420 +++-
  3 files changed, 308 insertions(+), 198 deletions(-)





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Re: [edk2-devel] [PATCH v2 0/1] Edk2ToolsBuild.py: Clarify make error

[Michael D Kinney]

Series Reviewed-by: Michael D Kinney 


> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Joey
> Vagedes via groups.io
> Sent: Monday, November 6, 2023 12:12 PM
> To: devel@edk2.groups.io
> Cc: Rebecca Cran ; Gao, Liming
> ; Feng, Bob C ; Chen,
> Christine 
> Subject: [edk2-devel] [PATCH v2 0/1] Edk2ToolsBuild.py: Clarify make
> error
> 
> When make or nmake fails to build the basetools, Edk2ToolsBuild.py
> currently prints a generic error message "Failed to build." and
> raises an exception. This has two issues: The first is that it raises
> an exception, which leads people to believe it is a python issue, and
> not a build issue. The second is that users don't necessarily know to
> check the build log if this error occurs.
> 
> This has been reported many times through many different avenues:
> 
> https://github.com/tianocore/edk2/discussions/4611
> https://stackoverflow.com/questions/77421168/edkii-base-tools-fails-
> to-build
> https://github.com/tianocore/edk2-pytool-extensions/issues/180
> https://github.com/tianocore/edk2-pytool-extensions/issues/207
> 
> This patch series changes the exception to a error log so that the
> invocable
> completes and returns a non-zero exit code and also logs a more
> descriptive
> error that informs the user to review the build log, and where to find
> it.
> 
> Cc: Rebecca Cran 
> Cc: Liming Gao 
> Cc: Bob Feng 
> Cc: Yuwei Chen 
> 
> Joey Vagedes (1):
>   BaseTools: Edk2ToolsBuild.py: Clarify make error
> 
>  BaseTools/Edk2ToolsBuild.py | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> --
> 2.34.1
> 
> º.¦È¨.)䱊.­çŠ÷š–
> Yž²Æ zËžÛh¶¬‚º.¥XžÃô^¦\ŽžX§{]tïž¡¶Úlÿ÷“h+¢êlŠàýׯz_æzˁïõ×NùèË­y8
> b±:)‰Èm¶›?þ
> 躛"£ù­ÿ]6ão<ë_õëø÷¡«¢êNÂw«uëÞ—ê0êÞvM ®‹©²*žË›±Êâmèm¶›?ýçdÚ
> 躛"£ø?uëÞ—û§²ææ‰ÈZzWdŠyÞÊ)ízW(


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Re: [edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify make error

[Michael D Kinney]

What is the random data at the end of your path emails???

Thanks,

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Joey
> Vagedes via groups.io
> Sent: Monday, November 6, 2023 12:09 PM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify make
> error
> 
> When make or nmake fails to build the basetools, Edk2ToolsBuild.py
> currently prints a generic error message "Failed to build." and
> raises an exception. This has two issues: The first is that it raises
> an exception, which leads people to believe it is a python issue, and
> not a build issue. The second is that users don't necessarily know to
> check the build log if this error occurs.
> 
> This has been reported many times through many different avenues:
> 
> https://github.com/tianocore/edk2/discussions/4611
> https://stackoverflow.com/questions/77421168/edkii-base-tools-fails-
> to-build
> https://github.com/tianocore/edk2-pytool-extensions/issues/180
> https://github.com/tianocore/edk2-pytool-extensions/issues/207
> 
> This patch series changes the exception to a error log so that the
> invocable
> completes and returns a non-zero exit code and also logs a more
> descriptive
> error that informs the user to review the build log, and where to find
> it.
> 
> Joey Vagedes (1):
>   BaseTools: Edk2ToolsBuild.py: Clarify make error
> 
>  BaseTools/Source/C/Common/BinderFuncs.c | 2 +-
>  BaseTools/Edk2ToolsBuild.py | 8 ++--
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> --
> 2.34.1
> 
> ®‹©²*
> Šy,b‹«yÇ¢½æ¥–g¬±¨²Ç§¶Ú-†+ ®‹©V'°ý©—#§–)Þ×];çˆm¶›?ýçdÚ
> 躛"£ø?uëÞ—
> ùž²Æ {ýuÓ¾x2ë^N¬NŠbrm¦Ïÿ‚º.¦È¨þk×M¸ÛÎüïýzã~=èj躓°êÝz÷¥úŒ'z·“h+¢ê
> lŠ…'²æìr¸›zm¦ÏÿyÙ6‚º.¦È¨þÝz÷¥þéì¹¹¢rž•Ù"žw²Š{^•Ê&


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Re: [edk2-devel] Request for access for edk2-staging branch creation

[Michael D Kinney]

Hi,

Can you please follow up with your Github ID and the additional details in a 
patch email wit Readme.MD content?

https://github.com/tianocore/edk2-staging/blob/about/README

4) Process to add a new feature to edk2-staging
a) Maintainer sends patch email to edk2-devel mailing list 
announcing the creation of a new
feature branch in edk2-staging with Readme.MD.  Readme.MD is in root of 
feature branch
with summary, owners, timeline, links to related materials.
b) Maintainer creates feature branch in edk2-staging
c) Maintainer is responsible for making sure feature is 
frequently synced to edk2/master

Thanks,

Mike


From: Czajkowski, Maciej 
Sent: Thursday, October 19, 2023 6:48 AM
To: devel@edk2.groups.io; Kinney, Michael D 
Subject: [edk2-devel] Request for access for edk2-staging branch creation

Hello,

I would like to request for a write access to edk2-staging repository to create 
a new branch for DeviceSimPkg. Its goal is to provide an environment to write 
OS-executable tests for code that interacts directly with devices.

Regards,
Maciej Czajkowski


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Re: [edk2-devel] [PATCH v1 1/1] BaseTools: Edk2ToolsBuild.py: Clarify make error

[Rebecca Cran]

Reviewed-by: Rebecca Cran 

--
Rebecca Cran

On 11/6/2023 1:12 PM, Joey Vagedes wrote:

Clarify to users that they should review the build log when make
(POSIX-like system) or nmake (Windows) fails to compile basetools.

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 
Signed-off-by: Joey Vagedes 
---
  BaseTools/Edk2ToolsBuild.py | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Edk2ToolsBuild.py b/BaseTools/Edk2ToolsBuild.py
index 425bb1b63963..4776c583080f 100644
--- a/BaseTools/Edk2ToolsBuild.py
+++ b/BaseTools/Edk2ToolsBuild.py
@@ -141,7 +141,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
  for level, problem in problems:
  logging.log(level, problem)
  if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run nmake.exe. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for nmake.exe error."
+logging.error(e)
+return ret
  
  self.WritePathEnvFile(self.OutputDir)

  return ret
@@ -156,7 +158,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
  for level, problem in problems:
  logging.log(level, problem)
  if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run make. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for make error."
+logging.error(e)
+return ret
  
  self.OutputDir = os.path.join(

  shell_env.get_shell_var("EDK_TOOLS_PATH"), "Source", "C", 
"bin")





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[edk2-devel] [PATCH 1/1] ShellPkg: Fix typos

[Page Chen via groups.io]

begining->beginning
dirve->drive
duplicat->duplicate
fuly->fully
Funciton->Function
Functino->Function
optioanl->optional
poitners->pointers
rountine->routine
sucessful->successful
sucessfully->successfully

Signed-off-by: Page Chen 
Cc: Zhichao Gao 
Cc: Andrew Fish 
---
 .../HttpDynamicCommand/HttpApp.c  |  2 +-
 .../HttpDynamicCommand/HttpDynamicCommand.c   |  4 +-
 ShellPkg/Include/Library/BcfgCommandLib.h |  2 +-
 ShellPkg/Include/Library/HandleParsingLib.h   |  2 +-
 ShellPkg/Include/Library/ShellCommandLib.h|  6 +--
 ShellPkg/Include/Library/ShellLib.h   | 30 +++---
 .../Include/Protocol/EfiShellEnvironment2.h   | 10 ++---
 .../UefiHandleParsingLib.c| 16 
 .../UefiShellBcfgCommandLib.c | 20 +-
 .../UefiShellCommandLib/UefiShellCommandLib.c |  6 +--
 .../UefiShellDebug1CommandsLib/Compress.c |  2 +-
 .../UefiShellDebug1CommandsLib/Compress.h |  2 +-
 .../UefiShellDebug1CommandsLib.c  |  2 +-
 .../UefiShellDriver1CommandsLib.c |  2 +-
 .../UefiShellInstall1CommandsLib.c|  2 +-
 .../UefiShellLevel1CommandsLib.c  |  4 +-
 .../UefiShellLevel1CommandsLib.h  |  2 +-
 .../Library/UefiShellLevel2CommandsLib/Cd.c   |  4 +-
 .../Library/UefiShellLevel2CommandsLib/Ls.c   |  2 +-
 .../Library/UefiShellLevel2CommandsLib/Map.c  |  2 +-
 .../Library/UefiShellLevel2CommandsLib/Mv.c   |  6 +--
 .../Library/UefiShellLevel2CommandsLib/Set.c  |  2 +-
 .../UefiShellLevel2CommandsLib.c  |  8 ++--
 .../UefiShellLevel2CommandsLib.h  |  6 +--
 .../Library/UefiShellLevel2CommandsLib/Vol.c  |  2 +-
 .../UefiShellLevel3CommandsLib/Alias.c|  4 +-
 .../UefiShellLevel3CommandsLib/Touch.c|  4 +-
 .../Library/UefiShellLevel3CommandsLib/Type.c |  4 +-
 .../UefiShellLevel3CommandsLib.c  |  2 +-
 ShellPkg/Library/UefiShellLib/UefiShellLib.c  | 40 +--
 .../UefiShellNetwork1CommandsLib/Ping.c   |  2 +-
 .../UefiShellNetwork1CommandsLib.c|  2 +-
 .../UefiShellNetwork2CommandsLib/Ping6.c  |  2 +-
 .../UefiShellNetwork2CommandsLib.c|  2 +-
 34 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c 
b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
index 6622e058aab6..ea41417fc3d6 100644
--- a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
+++ b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
@@ -28,7 +28,7 @@ EFI_STRING_ID  mStringHelpTokenId = STRING_TOKEN 
(STR_GET_HELP_HTTP);
   @param ImageHandleThe image handle of the process.
   @param SystemTableThe EFI System Table pointer.
 
-  @retval EFI_SUCCESS   Http command is executed sucessfully.
+  @retval EFI_SUCCESS   Http command is executed successfully.
   @retval EFI_ABORTED   HII package was failed to initialize.
   @retval othersOther errors when executing http command.
 **/
diff --git a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c 
b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
index 45aeaac347ad..d3c384dc8b8a 100644
--- a/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
+++ b/ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
@@ -22,7 +22,7 @@
   @param[in] Shell  The instance of the shell protocol used in
 the context of processing this command.
 
-  @return EFI_SUCCESS   the operation was sucessful
+  @return EFI_SUCCESS   the operation was successful
   @return other the operation failed.
 **/
 SHELL_STATUS
@@ -78,7 +78,7 @@ EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL  mHttpDynamicCommand = {
   @param ImageHandleThe image handle of the process.
   @param SystemTableThe EFI System Table pointer.
 
-  @retval EFI_SUCCESS   Http command is executed sucessfully.
+  @retval EFI_SUCCESS   Http command is executed successfully.
   @retval EFI_ABORTED   HII package was failed to initialize.
   @retval othersOther errors when executing http command.
 **/
diff --git a/ShellPkg/Include/Library/BcfgCommandLib.h 
b/ShellPkg/Include/Library/BcfgCommandLib.h
index ec5579ce614a..649fe00f98a2 100644
--- a/ShellPkg/Include/Library/BcfgCommandLib.h
+++ b/ShellPkg/Include/Library/BcfgCommandLib.h
@@ -18,7 +18,7 @@
   @param[in] SystemTablethe EFI System Table pointer
   @param[in] Name   the profile name to use
 
-  @retval EFI_SUCCESSthe shell command handlers were installed 
sucessfully
+  @retval EFI_SUCCESSthe shell command handlers were installed 
successfully
   @retval EFI_UNSUPPORTEDthe shell level required was not found.
 **/
 EFI_STATUS
diff --git a/ShellPkg/Include/Library/HandleParsingLib.h 
b/ShellPkg/Include/Library/HandleParsingLib.h
index 8193be94a478..b86d69cb0ef5 

[edk2-devel] [PATCH v1 1/1] BaseTools: Edk2ToolsBuild.py: Clarify make error

[Joey Vagedes via groups.io]

Clarify to users that they should review the build log when make
(POSIX-like system) or nmake (Windows) fails to compile basetools.

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 
Signed-off-by: Joey Vagedes 
---
 BaseTools/Edk2ToolsBuild.py | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Edk2ToolsBuild.py b/BaseTools/Edk2ToolsBuild.py
index 425bb1b63963..4776c583080f 100644
--- a/BaseTools/Edk2ToolsBuild.py
+++ b/BaseTools/Edk2ToolsBuild.py
@@ -141,7 +141,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
 for level, problem in problems:
 logging.log(level, problem)
 if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run nmake.exe. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for nmake.exe error."
+logging.error(e)
+return ret
 
 self.WritePathEnvFile(self.OutputDir)
 return ret
@@ -156,7 +158,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
 for level, problem in problems:
 logging.log(level, problem)
 if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run make. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for make error."
+logging.error(e)
+return ret
 
 self.OutputDir = os.path.join(
 shell_env.get_shell_var("EDK_TOOLS_PATH"), "Source", "C", 
"bin")
-- 
2.34.1

[edk2-devel] [PATCH v2 0/1] Edk2ToolsBuild.py: Clarify make error

[Joey Vagedes via groups.io]

When make or nmake fails to build the basetools, Edk2ToolsBuild.py
currently prints a generic error message "Failed to build." and
raises an exception. This has two issues: The first is that it raises
an exception, which leads people to believe it is a python issue, and
not a build issue. The second is that users don't necessarily know to
check the build log if this error occurs.

This has been reported many times through many different avenues:

https://github.com/tianocore/edk2/discussions/4611
https://stackoverflow.com/questions/77421168/edkii-base-tools-fails-to-build
https://github.com/tianocore/edk2-pytool-extensions/issues/180
https://github.com/tianocore/edk2-pytool-extensions/issues/207

This patch series changes the exception to a error log so that the invocable
completes and returns a non-zero exit code and also logs a more descriptive
error that informs the user to review the build log, and where to find it.

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 

Joey Vagedes (1):
  BaseTools: Edk2ToolsBuild.py: Clarify make error

 BaseTools/Edk2ToolsBuild.py | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

-- 
2.34.1

[edk2-devel] [PATCH v1 1/1] BaseTools: Edk2ToolsBuild.py: Clarify make error

[Joey Vagedes via groups.io]

Clarify to users that they should review the build log when make
(POSIX-like system) or nmake (Windows) fails to compile basetools.

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 
Signed-off-by: Joey Vagedes 
---
 BaseTools/Source/C/Common/BinderFuncs.c | 2 +-
 BaseTools/Edk2ToolsBuild.py | 8 ++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Source/C/Common/BinderFuncs.c 
b/BaseTools/Source/C/Common/BinderFuncs.c
index de835287e95c..8c08bef7a0f0 100644
--- a/BaseTools/Source/C/Common/BinderFuncs.c
+++ b/BaseTools/Source/C/Common/BinderFuncs.c
@@ -21,7 +21,7 @@ CommonLibBinderAllocate (
   )
 {
   return (VOID *) malloc (Size);
-}
+}asdf
 
 VOID
 CommonLibBinderFree (
diff --git a/BaseTools/Edk2ToolsBuild.py b/BaseTools/Edk2ToolsBuild.py
index 425bb1b63963..4776c583080f 100644
--- a/BaseTools/Edk2ToolsBuild.py
+++ b/BaseTools/Edk2ToolsBuild.py
@@ -141,7 +141,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
 for level, problem in problems:
 logging.log(level, problem)
 if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run nmake.exe. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for nmake.exe error."
+logging.error(e)
+return ret
 
 self.WritePathEnvFile(self.OutputDir)
 return ret
@@ -156,7 +158,9 @@ class Edk2ToolsBuild(BaseAbstractInvocable):
 for level, problem in problems:
 logging.log(level, problem)
 if ret != 0:
-raise Exception("Failed to build.")
+e = "Failed to run make. Review Buildlog at 
BaseTools/BaseToolsBuild/BASETOOLS_BUILD.txt for make error."
+logging.error(e)
+return ret
 
 self.OutputDir = os.path.join(
 shell_env.get_shell_var("EDK_TOOLS_PATH"), "Source", "C", 
"bin")
-- 
2.34.1

[edk2-devel] [PATCH v1 0/1] Edk2ToolsBuild.py: Clarify make error

[Joey Vagedes via groups.io]

When make or nmake fails to build the basetools, Edk2ToolsBuild.py
currently prints a generic error message "Failed to build." and 
raises an exception. This has two issues: The first is that it raises
an exception, which leads people to believe it is a python issue, and
not a build issue. The second is that users don't necessarily know to
check the build log if this error occurs. 

This has been reported many times through many different avenues:

https://github.com/tianocore/edk2/discussions/4611
https://stackoverflow.com/questions/77421168/edkii-base-tools-fails-to-build
https://github.com/tianocore/edk2-pytool-extensions/issues/180
https://github.com/tianocore/edk2-pytool-extensions/issues/207

This patch series changes the exception to a error log so that the invocable
completes and returns a non-zero exit code and also logs a more descriptive
error that informs the user to review the build log, and where to find it.

Joey Vagedes (1):
  BaseTools: Edk2ToolsBuild.py: Clarify make error

 BaseTools/Source/C/Common/BinderFuncs.c | 2 +-
 BaseTools/Edk2ToolsBuild.py | 8 ++--
 2 files changed, 7 insertions(+), 3 deletions(-)

-- 
2.34.1

Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

[Igor Kulchytskyy via groups.io]

Hi Nickle and Abner,
What is your opinion – should we have GetHiIpProtocolType fuction as a static 
one?
Thank you,
Igor

From: devel@edk2.groups.io  On Behalf Of Igor Kulchytskyy 
via groups.io
Sent: Monday, November 6, 2023 9:14 AM
To: M M 
Cc: devel@edk2.groups.io; Abner Chang ; Nickle Wang 

Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**
Hi Mike,
See my comments below.
Thank you,
Igor
P.S.
“There is no limits to perfection”

From: M M mailto:mike.maslen...@gmail.com>>
Sent: Sunday, November 05, 2023 9:30 PM
To: Igor Kulchytskyy mailto:ig...@ami.com>>
Cc: devel@edk2.groups.io; Abner Chang 
mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx

Hi Igor

I want to return to my initial comments regarding this patch.
Please, find my comments below.


On 1. 11. 2023., at 06:24, Igor Kulchytskyy 
mailto:ig...@ami.com>> wrote:

Hi Mike,
Thank you for review.
Please see my answers below the text.

-Original Message-
From: Mike Maslenkin mailto:mike.maslen...@gmail.com>>
Sent: Tuesday, October 31, 2023 9:00 PM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>
Cc: Abner Chang mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Igor

please find my comments below.

On Tue, Oct 31, 2023 at 8:56 PM Igor Kulchytskyy via 
groups.io
mailto:igork=ami@groups.io>> wrote:

Supported function of the driver changed to wait for all newtwork
interface to be installed.
Filer out the network interfaces which are not supported by
Redfish Host Interface.

Cc: Abner Chang mailto:abner.ch...@amd.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Cc: Igor Kulchytskyy mailto:ig...@ami.com>>
Signed-off-by: Igor Kulchytskyy mailto:ig...@ami.com>>
---
RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c | 96 ++--
1 file changed, 89 insertions(+), 7 deletions(-)

diff --git a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c 
b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
index 23da3b968f..a88ad55938 100644
--- a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
+++ b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
@@ -322,9 +322,15 @@ GetTargetNetworkInterfaceInternal (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+
  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
-if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0) 
{
+if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0 
&&
+((TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp6) ||
+(!TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp4))) {
  return ThisNetworkInterface;
}

@@ -354,6 +360,10 @@ GetTargetNetworkInterfaceInternalByController (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+

I also have these two hunks in my pending list.
But I suggest to add ASSERT to GetTargetNetworkInterfaceInternal, just
because currently it is really impossible situation,
and mEfiRedfishDiscoverNetworkInterface was checked before in scope of
ValidateTargetNetworkInterface().

Igor: Agree.
I also just noticed that even if GetTargetNetworkInterfaceInternal function may 
return NULL, the return value is not verified on NULL in 
RedfishServiceAcquireService function.
I think we should add this verification.


Also I wonder why check patch doesn't complain about missed spaces in
"IsListEmpty ()" call for example.

  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
if (ThisNetworkInterface->OpenDriverControllerHandle == ControllerHandle) {
@@ -476,6 +486,38 @@ CheckIsIpVersion6 (
  return FALSE;
}

+/**
+  This function returns the  IP type supported by the Host Interface
+
+  @retval IP Type
+  //  Unknown=00h,
+  //  Ipv4=01h,
+  //  Ipv6=02h,
+
+**/
+UINT8

STATIC ?
Igor: WHY?

I remembered discussion about STATIC functions usage and why it isn't common in 
edk2.
AFAIR it was because of difficulties with source level debugging for the case 
when it 

Re: [edk2-devel] [PATCH 1/2] EmbeddedPkg: Fix Android Boot Command Line Length Bug

[Ashish Singhal via groups.io]

Hello,

Hoping to get some feedback on these 2 patches this week.

Thanks
Ashish

From: Ashish Singhal 
Sent: Monday, October 30, 2023 2:24 PM
To: devel@edk2.groups.io ; quic_llind...@quicinc.com 
; ardb+tianoc...@kernel.org 
; abner.ch...@amd.com ; 
g...@danielschaefer.me ; Jeff Brasen 

Cc: Ashish Singhal 
Subject: [PATCH 1/2] EmbeddedPkg: Fix Android Boot Command Line Length Bug

Curently, AndroidBootImgLib expects input kernel command line
to never exceed 256 unicode characters where the image header
allows for 512 ascii characters. If image header allows 512
ascii characters, similar number of unicode characters should be
allowed at the minimum.

Signed-off-by: Ashish Singhal 
---
 .../AndroidBootImgLib/AndroidBootImgLib.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c 
b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
index 1359a66db2..02769cd0df 100644
--- a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
+++ b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
@@ -321,8 +321,9 @@ AndroidBootImgGetFdt (

 EFI_STATUS
 AndroidBootImgUpdateArgs (
-  IN  VOID  *BootImg,
-  OUT VOID  *KernelArgs
+  IN  VOID*BootImg,
+  OUT VOID*KernelArgs,
+  IN  UINT32  KernelArgsSize
   )
 {
   CHAR8   ImageKernelArgs[ANDROID_BOOTIMG_KERNEL_ARGS_SIZE];
@@ -337,13 +338,13 @@ AndroidBootImgUpdateArgs (
   AsciiStrToUnicodeStrS (
 ImageKernelArgs,
 KernelArgs,
-ANDROID_BOOTIMG_KERNEL_ARGS_SIZE >> 1
+KernelArgsSize
 );
   // Append platform kernel arguments
   if (mAndroidBootImg->AppendArgs) {
 Status = mAndroidBootImg->AppendArgs (
 KernelArgs,
-ANDROID_BOOTIMG_KERNEL_ARGS_SIZE
+KernelArgsSize
 );
   }

@@ -611,11 +612,16 @@ AndroidBootImgBoot (
   MEMORY_DEVICE_PATH KernelDevicePath;
   EFI_HANDLE ImageHandle;
   VOID   *NewKernelArg;
+  UINT32 NewKernelArgSize;
   EFI_LOADED_IMAGE_PROTOCOL  *ImageInfo;
   VOID   *RamdiskData;
   UINTN  RamdiskSize;
   IN  VOID   *FdtBase;

+  if ((Buffer == NULL) || (BufferSize == 0)) {
+return EFI_INVALID_PARAMETER;
+  }
+
   NewKernelArg = NULL;
   ImageHandle  = NULL;

@@ -637,14 +643,15 @@ AndroidBootImgBoot (
 goto Exit;
   }

-  NewKernelArg = AllocateZeroPool (ANDROID_BOOTIMG_KERNEL_ARGS_SIZE);
+  NewKernelArgSize = ANDROID_BOOTIMG_KERNEL_ARGS_SIZE;
+  NewKernelArg = AllocateZeroPool (sizeof (CHAR16) * NewKernelArgSize);
   if (NewKernelArg == NULL) {
 DEBUG ((DEBUG_ERROR, "Fail to allocate memory\n"));
 Status = EFI_OUT_OF_RESOURCES;
 goto Exit;
   }

-  Status = AndroidBootImgUpdateArgs (Buffer, NewKernelArg);
+  Status = AndroidBootImgUpdateArgs (Buffer, NewKernelArg, NewKernelArgSize);
   if (EFI_ERROR (Status)) {
 goto Exit;
   }
--
2.17.1



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[edk2-devel] [PATCH V1] MdePkg:Add NVME Sanitize command support to Nvme.h

[Tina Chen]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4591

1. Refer NVME spec 2.0c chapter 5.24, add Sanitize Command related definition.
2. Refer NVME spec 2.0c chapter 5.16, add Get Log Page Command related 
definition for Sanitize status support.

Cc: Xiao X Chen 
Cc: Arthur Chen 
Cc: Ray Ni 
Cc: Liming Gao 
Signed-off-by: Tina Chen 
---
 MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c|   1 +
 MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c |   1 +
 MdePkg/Include/IndustryStandard/Nvme.h| 106 
++--
 3 files changed, 98 insertions(+), 10 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
index b90c48731c..2ecaa2bbbe 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
@@ -908,6 +908,7 @@ NvmeControllerInit (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", Private->ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)Private->ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", 
Private->ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", 
Private->ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", 
Private->ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", 
Private->ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", Private->ControllerData->Nn));

diff --git a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c 
b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
index fc7b684940..61ef06e42f 100644
--- a/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
+++ b/MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.c
@@ -436,6 +436,7 @@ NvmeDumpControllerData (
   DEBUG ((DEBUG_INFO, "RAB   : 0x%x\n", ControllerData->Rab));

   DEBUG ((DEBUG_INFO, "IEEE  : 0x%x\n", *(UINT32 
*)ControllerData->Ieee_oui));

   DEBUG ((DEBUG_INFO, "AERL  : 0x%x\n", ControllerData->Aerl));

+  DEBUG ((DEBUG_INFO, "Sanicap   : 0x%x\n", ControllerData->Sanicap));

   DEBUG ((DEBUG_INFO, "SQES  : 0x%x\n", ControllerData->Sqes));

   DEBUG ((DEBUG_INFO, "CQES  : 0x%x\n", ControllerData->Cqes));

   DEBUG ((DEBUG_INFO, "NN: 0x%x\n", ControllerData->Nn));

diff --git a/MdePkg/Include/IndustryStandard/Nvme.h 
b/MdePkg/Include/IndustryStandard/Nvme.h
index 8b8a1bb7f3..d158d6c267 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -403,7 +403,15 @@ typedef struct {
   UINT16   Edstt;   /* Extended Device Self-test Time */

   UINT8Dsto;/* Device Self-test Options  */

   UINT8Fwug;/* Firmware Update Granularity */

-  UINT8Rsvd2[192];  /* Reserved as of Nvm Express 1.4 Spec */

+  UINT16   Kas; /* Keep Alive Support */

+  UINT16   Hctma;   /* Host Controlled Thermal Management 
Attributes */

+  UINT16   Mntmt;   /* Minimum Thermal Management Temperature 
*/

+  UINT16   Mxtmt;   /* Maximum Thermal Management Temperature 
*/

+  UINT32   Sanicap; /* Sanitize Capabilities */

+  #define SANITIZE_OVERWRITE_ERASE_SUPPORTED  BIT2

+  #define SANITIZE_BLOCK_ERASE_SUPPORTED  BIT1

+  #define SANITIZE_CRYPTO_ERASE_SUPPORTED BIT0

+  UINT8Rsvd2[180];  /* Reserved as of Nvm Express 1.4 Spec */

   //

   // NVM Command Set Attributes

   //

@@ -687,10 +695,11 @@ typedef struct {
   // CDW 10

   //

   UINT32Lid   : 8;/* Log Page Identifier */

-  #define LID_ERROR_INFO0x1

-  #define LID_SMART_INFO0x2

-  #define LID_FW_SLOT_INFO  0x3

-  #define LID_BP_INFO   0x15

+  #define LID_ERROR_INFO0x1

+  #define LID_SMART_INFO0x2

+  #define LID_FW_SLOT_INFO  0x3

+  #define LID_BP_INFO   0x15

+  #define LID_SANITIZE_STATUS_INFO  0x81

   UINT32Rsvd1 : 8;

   UINT32Numd  : 12;   /* Number of Dwords */

   UINT32Rsvd2 : 4;/* Reserved as of Nvm Express 1.1 Spec */

@@ -708,6 +717,25 @@ typedef struct {
   UINT32Sv: 1;/* Save */

 } NVME_ADMIN_SET_FEATURES;

 

+//

+// NvmExpress Admin Sanitize Command

+//

+typedef struct {

+  //

+  // CDW 10

+  //

+  UINT32Sanact : 3;   /* Sanitize Action */

+  UINT32Ause   : 1;   /* Allow Unrestricted Sanitize Exit */

+  UINT32Owpass : 4;   /* Overwrite Pass Count */

+  UINT32Oipbp  : 1;   /* Overwrite Invert Pattern Between Passes */

+  UINT32Nodas  : 1;   /* No-Deallocate After Sanitize */

+  UINT32Rsvd1  : 22;

+  //

+  // CDW 11

+  //

+  UINT32Ovrpat;   /* Overwrite Pattern */

+} NVME_ADMIN_SANITIZE;

+

 //

 // NvmExpress Admin Format NVM Command

 //

@@ -770,6 +798,7 @@ typedef union {
   

Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: Fix issue if IPv4 installed after RestEx

[Igor Kulchytskyy via groups.io]

Hi Mike,
See my comments below.
Thank you,
Igor
P.S.
“There is no limits to perfection”

From: M M 
Sent: Sunday, November 05, 2023 9:30 PM
To: Igor Kulchytskyy 
Cc: devel@edk2.groups.io; Abner Chang ; Nickle Wang 

Subject: Re: [EXTERNAL] [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx

Hi Igor

I want to return to my initial comments regarding this patch.
Please, find my comments below.



On 1. 11. 2023., at 06:24, Igor Kulchytskyy 
mailto:ig...@ami.com>> wrote:

Hi Mike,
Thank you for review.
Please see my answers below the text.

-Original Message-
From: Mike Maslenkin mailto:mike.maslen...@gmail.com>>
Sent: Tuesday, October 31, 2023 9:00 PM
To: devel@edk2.groups.io; Igor Kulchytskyy 
mailto:ig...@ami.com>>
Cc: Abner Chang mailto:abner.ch...@amd.com>>; Nickle Wang 
mailto:nick...@nvidia.com>>
Subject: [EXTERNAL] Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: 
Fix issue if IPv4 installed after RestEx


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

Hi Igor

please find my comments below.

On Tue, Oct 31, 2023 at 8:56 PM Igor Kulchytskyy via 
groups.io
mailto:igork=ami@groups.io>> wrote:


Supported function of the driver changed to wait for all newtwork
interface to be installed.
Filer out the network interfaces which are not supported by
Redfish Host Interface.

Cc: Abner Chang mailto:abner.ch...@amd.com>>
Cc: Nickle Wang mailto:nick...@nvidia.com>>
Cc: Igor Kulchytskyy mailto:ig...@ami.com>>
Signed-off-by: Igor Kulchytskyy mailto:ig...@ami.com>>
---
RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c | 96 ++--
1 file changed, 89 insertions(+), 7 deletions(-)

diff --git a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c 
b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
index 23da3b968f..a88ad55938 100644
--- a/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
+++ b/RedfishPkg/RedfishDiscoverDxe/RedfishDiscoverDxe.c
@@ -322,9 +322,15 @@ GetTargetNetworkInterfaceInternal (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+
  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
-if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0) 
{
+if (CompareMem ((VOID *)>MacAddress, 
>MacAddress, ThisNetworkInterface->HwAddressSize) == 0 
&&
+((TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp6) ||
+(!TargetNetworkInterface->IsIpv6 && 
ThisNetworkInterface->NetworkProtocolType == ProtocolTypeTcp4))) {
  return ThisNetworkInterface;
}

@@ -354,6 +360,10 @@ GetTargetNetworkInterfaceInternalByController (
{
  EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL  *ThisNetworkInterface;

+  if (IsListEmpty()) {
+return NULL;
+  }
+

I also have these two hunks in my pending list.
But I suggest to add ASSERT to GetTargetNetworkInterfaceInternal, just
because currently it is really impossible situation,
and mEfiRedfishDiscoverNetworkInterface was checked before in scope of
ValidateTargetNetworkInterface().

Igor: Agree.
I also just noticed that even if GetTargetNetworkInterfaceInternal function may 
return NULL, the return value is not verified on NULL in 
RedfishServiceAcquireService function.
I think we should add this verification.


Also I wonder why check patch doesn't complain about missed spaces in
"IsListEmpty ()" call for example.


  ThisNetworkInterface = (EFI_REDFISH_DISCOVER_NETWORK_INTERFACE_INTERNAL 
*)GetFirstNode ();
  while (TRUE) {
if (ThisNetworkInterface->OpenDriverControllerHandle == ControllerHandle) {
@@ -476,6 +486,38 @@ CheckIsIpVersion6 (
  return FALSE;
}

+/**
+  This function returns the  IP type supported by the Host Interface
+
+  @retval IP Type
+  //  Unknown=00h,
+  //  Ipv4=01h,
+  //  Ipv6=02h,
+
+**/
+UINT8

STATIC ?
Igor: WHY?

I remembered discussion about STATIC functions usage and why it isn't common in 
edk2.
AFAIR it was because of difficulties with source level debugging for the case 
when it could be inlined.
BTW I won't insist on this here.



+GetHiIpProtocolType()
+{
+  EFI_STATUS Status;
+  REDFISH_OVER_IP_PROTOCOL_DATA  *Data;
+  REDFISH_INTERFACE_DATA *DeviceDescriptor;
+
+  Data = NULL;
+  DeviceDescriptor = NULL;
+  if (mSmbios == NULL) {
+Status = gBS->LocateProtocol (, NULL, (VOID 
**));
+if (EFI_ERROR (Status)) {
+  return 0;

In this driver REDFISH_HOST_INTERFACE_HOST_IP_ADDRESS_FORMAT_IP{4,6}
used and accessible.
so, 0 means  REDFISH_HOST_INTERFACE_HOST_IP_ADDRESS_FORMAT_UNKNOWN
And these values actually checked in scope of BuildupNetworkInterface() below.
Igor: Thank you. Missed that macro.


+}
+  }
+  Status = 

Re: [edk2-devel] [PATCH v3] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET enable

[Wu, Jiaxin]

Yes, ray, the flow is right, and I confirmed with CET feature owner about the 
EnableCet() & DisableCet() behavior before patch out.

Incsspq in DisableCet() performs a pop to increases the shadow stack, while POP 
& JMP in EnableCet() make sure return to caller without check failure.

I will refine the commit log to include your great suggestion. Thank you very 
much!

Jiaxin





From: Ni, Ray 
Sent: Monday, November 6, 2023 5:41 PM
To: Wu, Jiaxin ; devel@edk2.groups.io
Cc: Dong, Eric ; Zeng, Star ; Gerd 
Hoffmann ; Kumar, Rahul R ; Laszlo 
Ersek 
Subject: Re: [PATCH v3] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET 
enable

The commit message doesn't explain the root cause of the issue very clearly.
(I am sure that you understand the issue very clearly. But I see improvements 
in explaining it.)

I guess the root cause is due to the code flow as follows:
1. Before DisableReadonlyPageWriteProtect() is called, the return address (#1) 
is pushed in shadow stack.
2. CET is disabled.
3. DisableReadonlyPageWriteProtect() returns to #1.
4. Page table is modified.
5. EnableReadonlyPageWriteProtect() is called, but the return address (#2) is 
not pushed in shadow stack.
6. CET is enabled.
7. EnableReadonlyPageWriteProtect() returns to #2.
#CP exception happens because the actual return address (#2) doesn't match the 
return address stored in shadow stack (#1).

If yes, can you update the commit to explain in above way?

Also, please emphasize  that EnableCet() and DisableCet() is implemented in a 
way that return address of DisableCet() is poped  out
from shadow stack and EnableCet() doesn't use "RET" but "JMP" to return to 
caller. So calling EnableCet() and DisableCet() doesn't
have the same issue as calling DisableReadonlyPageWriteProtect() and 
EnableReadonlyPageWriteProtect().

Thanks,
Ray


From: Wu, Jiaxin mailto:jiaxin...@intel.com>>
Sent: Monday, November 6, 2023 10:46 AM
To: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>
Cc: Dong, Eric mailto:eric.d...@intel.com>>; Ni, Ray 
mailto:ray...@intel.com>>; Zeng, Star 
mailto:star.z...@intel.com>>; Gerd Hoffmann 
mailto:kra...@redhat.com>>; Kumar, Rahul R 
mailto:rahul.r.ku...@intel.com>>; Laszlo Ersek 
mailto:ler...@redhat.com>>
Subject: [PATCH v3] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET enable

Shadow stack will stop update after CET disable (DisableCet in
DisableReadOnlyPageWriteProtect), but normal smi stack will be
continue updated with the function return and enter
(DisableReadOnlyPageWriteProtect & EnableReadOnlyPageWriteProtect),
thus leading stack mismatch after CET re-enabled (EnableCet in
EnableReadOnlyPageWriteProtect).

Normal smi stack and shadow stack must be matched when CET enable,
otherwise CP Exception will happen, which is caused by a near RET
instruction (See SDM Vol 3, 6.15-Control Protection Exception).

With above requirement, define below 2 macros instead of functions
for WP & CET operation:
WRITE_UNPROTECT_RO_PAGES (Wp, Cet)
WRITE_PROTECT_RO_PAGES (Wp, Cet)
Because "CET" feature disable & enable must be in the same
function to avoid shadow stack and normal SMI stack mismatch.

Note: WRITE_UNPROTECT_RO_PAGES () must be called pair with
WRITE_PROTECT_RO_PAGES () in same function.

Cc: Eric Dong mailto:eric.d...@intel.com>>
Cc: Ray Ni mailto:ray...@intel.com>>
Cc: Zeng Star mailto:star.z...@intel.com>>
Cc: Gerd Hoffmann mailto:kra...@redhat.com>>
Cc: Rahul Kumar mailto:rahul1.ku...@intel.com>>
Cc: Laszlo Ersek mailto:ler...@redhat.com>>
Signed-off-by: Jiaxin Wu mailto:jiaxin...@intel.com>>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 59 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 73 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  7 ++-
 3 files changed, 81 insertions(+), 58 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 654935dc76..20ada465c2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1551,29 +1551,64 @@ VOID
 SmmWaitForApArrival (
   VOID
   );

 /**
-  Disable Write Protect on pages marked as read-only if Cr0.Bits.WP is 1.
+  Write unprotect read-only pages if Cr0.Bits.WP is 1.
+
+  @param[out]  WriteProtect  If Cr0.Bits.WP is enabled.

-  @param[out]  WpEnabled  If Cr0.WP is enabled.
-  @param[out]  CetEnabled If CET is enabled.
 **/
 VOID
-DisableReadOnlyPageWriteProtect (
-  OUT BOOLEAN  *WpEnabled,
-  OUT BOOLEAN  *CetEnabled
+SmmWriteUnprotectReadOnlyPage (
+  OUT BOOLEAN  *WriteProtect
   );

 /**
-  Enable Write Protect on pages marked as read-only.
+  Write protect read-only pages.
+
+  @param[in]  WriteProtect  If Cr0.Bits.WP should be enabled.

-  @param[out]  WpEnabled  If Cr0.WP should be enabled.
-  @param[out]  CetEnabled If CET should be enabled.
 **/
 VOID
-EnableReadOnlyPageWriteProtect (
-  BOOLEAN  

Re: [edk2-devel] [PATCH v1] OvmfPkg/PlatformInitLib: Don't override user specified PciMmio64Size

[Gerd Hoffmann]

  Hi,

> > I agree that the proposed patch can function as a stop-gap, but the QEMU
> > command line hack is already a stop-gap. And for the long term, this
> > patch is not good enough. We should enhance the dynamic sizing, now that
> > Gerd has put it into place.
> 
> ... I do agree however that the current behavior is strange -- the user
> specifies an explicit fw_cfg knob for OVMF, and OVMF ignores it (for
> whatever reason).
> 
> I'd like to know what Gerd thinks of this.

The current code effectively considers the user-specified PciMmio64Size
as a lower limit, it will never be smaller but might be larger in case
OVMF figures it has enough space.

Being more strict here and use the user-specified PciMmio64Size as-is no
matter what is fine with me.

The independent but related question is where the window should be
placed in case we have a valid vcpu address space size and PciMmio64Size
specified by the user.

> (b) there were a promise to enhance QEMU and OVMF as I suggest above.

Fully agree.  We should explicitly communicate requirements (in this
case: iommu address space size) instead of depending on side effects
of unrelated config options.

Strictly speaking you don't care that much about the size of the mmio
window, but where it gets placed.  Moving it to the end of the vcpu
address space is what breaks your use case in case the iommu address
space happens to be too small for that.

take care,
  Gerd



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Re: [edk2-devel] question about cxl device enumeration in pci bus driver

[Yoshinoya]

Hi,
I have a question about cxl memory device hot-plug.


For example:
1. When cold boot, the platform has only 512GB cxl type-3 memory
2. During OS runtime, user hot-plug another cxl type-3  memory device expanding 
to 1TB.


So, how did OS identify another 512GB space newly added without a reboot?


Could anyone help to explain the procedure draftly?



Thanks










在 2023-10-27 09:29:31，"Yoshinoya"  写道：




Hi,
Thanks for reply!


I download code from this git https://github.com/SayantaP-arm/edk2-platforms/


For this ARM edk2 sample package, it provided cxldxe driver which being 
executed after UEFI DXE PciBus enumeration finishes.
This ppt (https://lpc.events/event/16/contributions/1254/) describes good.


Intel also provied a CXL Type 3 memory device software guide.
This guide also describes system firmware boot sequence and uefi boot sequence.
But i could not match these describes with standard UEFI BIOS Boot flow, such 
as dxe phase's standard pci enumeration driver.
It sees needing add some cxl discovery code into dxe pci bus driver.


Thanks
















At 2023-10-26 21:35:38, "Jonathan Cameron via groups.io" 
 wrote:
>On Thu, 26 Oct 2023 11:49:28 +0200
>"Laszlo Ersek"  wrote:
>
>> On 10/26/23 10:33, Gerd Hoffmann wrote:
>> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
>> >   
>> >> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Config, 
>> >> maybe could be integrated into pci drivers stack.  
>> > 
>> > Point being?  Can or should the firmware do anything useful with
>> > the CXL hardware?  If so, what exactly and why?
>> > 
>> > Current state of affairs is that the PCI stack does the usual PCI
>> > initialization (enumerate, assign resources to PCI bars) and leaves
>> > everything else to the OS.  
>> 
>> (I don't know what "HDM Config" stands for.)
>> 
>> The only utility for driving CXL devices from the firmware could be, AFAICT:
>> 
>> - booting off of such a device (or at least "supporting OS boot" in some
>> manner)
>> 
>> - using such a device for UEFI console purposes
>
>There are different models for how to use CXL devices and what's possible 
>depends on the
>version of CXL.  CXL 1.1 wasn't great for standards defined discovery, so
>EDK2 platform logic basically has to do everything.
>
>The one mostly expected for early CXL servers, for backwards compatibility, 
>makes
>setting up the CXL memory decoders (Host managed Device Memory - HDM) in all 
>the
>components in the path to memory + locking them down an EDK2 problem.  They 
>are then
>presented in the memory map and in SRAT, HMAT etc the same as normal DDR 
>memory.
>Idea being that an old OS will be fine with that and doesn't have to be CXL 
>aware
>at all.  Note this also involves walking the CDAT tables via DOE mailboxes in 
>PCI
>config space to get the magic numbers needed to compute HMAT.
>
>The other model is to do very little in EDK2 and make entirely a problem for 
>the OS.
>The logic is necessary anyway if you want to support hotplug etc, so use it 
>for the
>cold plug paths 2.  That's all we've currently supported on QEMU.
>
>There was a presentation at Linux Plumbers last year on some out of tree 
>support
>from ARM for doing the setup on a CXL 2.0 platform (I think) in EDK2 
>https://lpc.events/event/16/contributions/1254/
>But I guess it never went upstream.
>https://github.com/SayantaP-arm/edk2-platforms/tree/cxl-type-3
>
>+CC Sayanta
>
>Jonathan
>> 
>> Laszlo
>> 
>> 
>> 
>> 
>> 
>> 
>
>
>
>
>



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Re: [edk2-devel] [PATCH v3] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET enable

[Ni, Ray]

The commit message doesn't explain the root cause of the issue very clearly.
(I am sure that you understand the issue very clearly. But I see improvements 
in explaining it.)

I guess the root cause is due to the code flow as follows:
1. Before DisableReadonlyPageWriteProtect() is called, the return address (#1) 
is pushed in shadow stack.
2. CET is disabled.
3. DisableReadonlyPageWriteProtect() returns to #1.
4. Page table is modified.
5. EnableReadonlyPageWriteProtect() is called, but the return address (#2) is 
not pushed in shadow stack.
6. CET is enabled.
7. EnableReadonlyPageWriteProtect() returns to #2.
#CP exception happens because the actual return address (#2) doesn't match the 
return address stored in shadow stack (#1).

If yes, can you update the commit to explain in above way?

Also, please emphasize  that EnableCet() and DisableCet() is implemented in a 
way that return address of DisableCet() is poped  out
from shadow stack and EnableCet() doesn't use "RET" but "JMP" to return to 
caller. So calling EnableCet() and DisableCet() doesn't
have the same issue as calling DisableReadonlyPageWriteProtect() and 
EnableReadonlyPageWriteProtect().

Thanks,
Ray


From: Wu, Jiaxin 
Sent: Monday, November 6, 2023 10:46 AM
To: devel@edk2.groups.io 
Cc: Dong, Eric ; Ni, Ray ; Zeng, Star 
; Gerd Hoffmann ; Kumar, Rahul R 
; Laszlo Ersek 
Subject: [PATCH v3] UefiCpuPkg/PiSmmCpuDxeSmm: Fix CP Exception when CET enable

Shadow stack will stop update after CET disable (DisableCet in
DisableReadOnlyPageWriteProtect), but normal smi stack will be
continue updated with the function return and enter
(DisableReadOnlyPageWriteProtect & EnableReadOnlyPageWriteProtect),
thus leading stack mismatch after CET re-enabled (EnableCet in
EnableReadOnlyPageWriteProtect).

Normal smi stack and shadow stack must be matched when CET enable,
otherwise CP Exception will happen, which is caused by a near RET
instruction (See SDM Vol 3, 6.15-Control Protection Exception).

With above requirement, define below 2 macros instead of functions
for WP & CET operation:
WRITE_UNPROTECT_RO_PAGES (Wp, Cet)
WRITE_PROTECT_RO_PAGES (Wp, Cet)
Because "CET" feature disable & enable must be in the same
function to avoid shadow stack and normal SMI stack mismatch.

Note: WRITE_UNPROTECT_RO_PAGES () must be called pair with
WRITE_PROTECT_RO_PAGES () in same function.

Cc: Eric Dong 
Cc: Ray Ni 
Cc: Zeng Star 
Cc: Gerd Hoffmann 
Cc: Rahul Kumar 
Cc: Laszlo Ersek 
Signed-off-by: Jiaxin Wu 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 59 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 73 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c |  7 ++-
 3 files changed, 81 insertions(+), 58 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 654935dc76..20ada465c2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1551,29 +1551,64 @@ VOID
 SmmWaitForApArrival (
   VOID
   );

 /**
-  Disable Write Protect on pages marked as read-only if Cr0.Bits.WP is 1.
+  Write unprotect read-only pages if Cr0.Bits.WP is 1.
+
+  @param[out]  WriteProtect  If Cr0.Bits.WP is enabled.

-  @param[out]  WpEnabled  If Cr0.WP is enabled.
-  @param[out]  CetEnabled If CET is enabled.
 **/
 VOID
-DisableReadOnlyPageWriteProtect (
-  OUT BOOLEAN  *WpEnabled,
-  OUT BOOLEAN  *CetEnabled
+SmmWriteUnprotectReadOnlyPage (
+  OUT BOOLEAN  *WriteProtect
   );

 /**
-  Enable Write Protect on pages marked as read-only.
+  Write protect read-only pages.
+
+  @param[in]  WriteProtect  If Cr0.Bits.WP should be enabled.

-  @param[out]  WpEnabled  If Cr0.WP should be enabled.
-  @param[out]  CetEnabled If CET should be enabled.
 **/
 VOID
-EnableReadOnlyPageWriteProtect (
-  BOOLEAN  WpEnabled,
-  BOOLEAN  CetEnabled
+SmmWriteProtectReadOnlyPage (
+  IN  BOOLEAN  WriteProtect
   );

+///
+/// Define macros to encapsulate the write unprotect/protect
+/// read-only pages.
+/// Below pieces of logic are defined as macros and not functions
+/// because "CET" feature disable & enable must be in the same
+/// function to avoid shadow stack and normal SMI stack mismatch,
+/// thus WRITE_UNPROTECT_RO_PAGES () must be called pair with
+/// WRITE_PROTECT_RO_PAGES () in same function.
+///
+/// @param[in,out] Wp   A BOOLEAN variable local to the containing
+/// function, carrying write protection status from
+/// WRITE_UNPROTECT_RO_PAGES() to
+/// WRITE_PROTECT_RO_PAGES().
+///
+/// @param[in,out] Cet  A BOOLEAN variable local to the containing
+/// function, carrying control flow integrity
+/// enforcement status from
+/// WRITE_UNPROTECT_RO_PAGES() to
+/// WRITE_PROTECT_RO_PAGES().
+///
+#define WRITE_UNPROTECT_RO_PAGES(Wp, 

[edk2-devel] [PATCH v2 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: Set mSmmInterruptSspTables initial value

[Sheng Wei]

Initial the value of mSmmInterruptSspTables to 0.

Signed-off-by: Sheng Wei 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Wu Jiaxin 
Cc: Tan Dun 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index c4f21e2155..6c53213b0b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -20,7 +20,7 @@ UINT32mCetPl0Ssp;
 UINT32mCetInterruptSsp;
 UINT32mCetInterruptSspTable;
 
-UINTN  mSmmInterruptSspTables;
+UINTN  mSmmInterruptSspTables = 0;
 
 /**
   Initialize IDT IST Field.
-- 
2.26.2.windows.1



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[edk2-devel] [PATCH v2 2/3] UefiCpuPkg/PiSmmCpuDxeSmm: Change CR4.CET bit only

[Sheng Wei]

Do not use fixed CR4 value 0x668, change CR4.CET bit only.

Signed-off-by: Sheng Wei 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Wu Jiaxin 
Cc: Tan Dun 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 9 ++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 3 ++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 68332e2c3f..a087576a54 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -260,7 +260,8 @@ CetInterruptDone:
 bts ecx, 16 ; set WP
 mov cr0, ecx
 
-mov eax, 0x668 | CR4_CET
+mov eax, cr4
+bts eax, CR4_CET_BIT
 mov cr4, eax
 
 setssbsy
@@ -292,8 +293,10 @@ CetDone:
 xor edx, edx
 wrmsr
 
-mov eax, 0x668
-mov cr4, eax   ; disable CET
+; clear CR4.CET bit
+mov eax, cr4
+btr eax, CR4_CET_BIT
+mov cr4, eax
 
 mov ecx, MSR_IA32_PL0_SSP
 pop eax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 007fbff640..7aed7c8dda 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -287,7 +287,8 @@ CetInterruptDone:
 bts ecx, 16 ; set WP
 mov cr0, rcx
 
-mov eax, 0x668 | CR4_CET
+mov rax, cr4
+bts rax, CR4_CET_BIT
 mov cr4, rax
 
 setssbsy
-- 
2.26.2.windows.1



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[edk2-devel] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR4.CET before restoring MSR IA32_S_CET

[Sheng Wei]

Clear CR4.CET bit before restoring MSR IA32_S_CET.
Backup/restore MSR IA32_U_CET in SMI.

Signed-off-by: Sheng Wei 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Wu Jiaxin 
Cc: Tan Dun 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 53 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 69 
 2 files changed, 98 insertions(+), 24 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 19de5f614e..68332e2c3f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -16,18 +16,19 @@
 %include "StuffRsbNasm.inc"
 %include "Nasm.inc"
 
+%define MSR_IA32_U_CET 0x6A0
 %define MSR_IA32_S_CET 0x6A2
-%define   MSR_IA32_CET_SH_STK_EN 0x1
-%define   MSR_IA32_CET_WR_SHSTK_EN   0x2
-%define   MSR_IA32_CET_ENDBR_EN  0x4
-%define   MSR_IA32_CET_LEG_IW_EN 0x8
-%define   MSR_IA32_CET_NO_TRACK_EN   0x10
-%define   MSR_IA32_CET_SUPPRESS_DIS  0x20
-%define   MSR_IA32_CET_SUPPRESS  0x400
-%define   MSR_IA32_CET_TRACKER   0x800
+%define MSR_IA32_CET_SH_STK_EN 0x1
+%define MSR_IA32_CET_WR_SHSTK_EN   0x2
+%define MSR_IA32_CET_ENDBR_EN  0x4
+%define MSR_IA32_CET_LEG_IW_EN 0x8
+%define MSR_IA32_CET_NO_TRACK_EN   0x10
+%define MSR_IA32_CET_SUPPRESS_DIS  0x20
+%define MSR_IA32_CET_SUPPRESS  0x400
+%define MSR_IA32_CET_TRACKER   0x800
 %define MSR_IA32_PL0_SSP   0x6A4
 
-%define CR4_CET0x80
+%define CR4_CET_BIT23
 
 %define MSR_IA32_MISC_ENABLE 0x1A0
 %define MSR_EFER  0xc080
@@ -214,11 +215,21 @@ ASM_PFX(mPatchCetSupported):
 pushedx
 pusheax
 
+mov ecx, MSR_IA32_U_CET
+rdmsr
+pushedx
+pusheax
+
 mov ecx, MSR_IA32_PL0_SSP
 rdmsr
 pushedx
 pusheax
 
+mov ecx, MSR_IA32_U_CET
+xor eax, eax
+xor edx, edx
+wrmsr
+
 mov ecx, MSR_IA32_S_CET
 mov eax, MSR_IA32_CET_SH_STK_EN
 xor edx, edx
@@ -276,6 +287,11 @@ CetDone:
 cmp al, 0
 jz  CetDone2
 
+mov ecx, MSR_IA32_S_CET
+xor eax, eax
+xor edx, edx
+wrmsr
+
 mov eax, 0x668
 mov cr4, eax   ; disable CET
 
@@ -284,10 +300,15 @@ CetDone:
 pop edx
 wrmsr
 
-mov ecx, MSR_IA32_S_CET
+mov ecx, MSR_IA32_U_CET
 pop eax
 pop edx
 wrmsr
+
+mov ecx, MSR_IA32_S_CET
+pop eax
+pop edx
+mov ebx, eax
 CetDone2:
 
 mov eax, ASM_PFX(mXdSupported)
@@ -305,6 +326,18 @@ CetDone2:
 .7:
 
 StuffRsb32
+
+mov eax, ASM_PFX(mCetSupported)
+mov al, [eax]
+cmp al, 0
+jz  CetDone3
+
+mov ecx, MSR_IA32_S_CET
+mov eax, ebx
+xor edx, edx
+wrmsr
+CetDone3:
+
 rsm
 
 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index d302ca8d01..007fbff640 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -20,19 +20,20 @@
 ; Variables referenced by C code
 ;
 
+%define MSR_IA32_U_CET 0x6A0
 %define MSR_IA32_S_CET 0x6A2
-%define   MSR_IA32_CET_SH_STK_EN 0x1
-%define   MSR_IA32_CET_WR_SHSTK_EN   0x2
-%define   MSR_IA32_CET_ENDBR_EN  0x4
-%define   MSR_IA32_CET_LEG_IW_EN 0x8
-%define   MSR_IA32_CET_NO_TRACK_EN   0x10
-%define   MSR_IA32_CET_SUPPRESS_DIS  0x20
-%define   MSR_IA32_CET_SUPPRESS  0x400
-%define   MSR_IA32_CET_TRACKER   0x800
+%define MSR_IA32_CET_SH_STK_EN 0x1
+%define MSR_IA32_CET_WR_SHSTK_EN   0x2
+%define MSR_IA32_CET_ENDBR_EN  0x4
+%define MSR_IA32_CET_LEG_IW_EN 0x8
+%define MSR_IA32_CET_NO_TRACK_EN   0x10
+%define MSR_IA32_CET_SUPPRESS_DIS  0x20
+%define MSR_IA32_CET_SUPPRESS  0x400
+%define MSR_IA32_CET_TRACKER   0x800
 %define MSR_IA32_PL0_SSP   0x6A4
 %define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR  0x6A8
 
-%define CR4_CET0x80
+%define CR4_CET_BIT23
 
 %define MSR_IA32_MISC_ENABLE 0x1A0
 %define MSR_EFER  0xc080
@@ -230,6 +231,11 @@ ASM_PFX(mPatchCetSupported):
 pushrdx
 pushrax
 
+mov ecx, MSR_IA32_U_CET
+rdmsr
+pushrdx
+pushrax
+
 mov ecx, MSR_IA32_PL0_SSP
 rdmsr
 pushrdx
@@ -240,6 +246,11 @@ ASM_PFX(mPatchCetSupported):
 pushrdx
 pushrax
 
+mov ecx, MSR_IA32_U_CET
+xor eax, eax
+xor edx, edx
+

[edk2-devel] [PATCH v2 0/3] UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR4.CET before

[Sheng Wei]

Patch V2:
  No function change with Patch V1.
  Split the patch to into 3 separate patches.

Sheng Wei (3):
  UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR4.CET before restoring MSR
IA32_S_CET
  UefiCpuPkg/PiSmmCpuDxeSmm: Change CR4.CET bit only
  UefiCpuPkg/PiSmmCpuDxeSmm: Set mSmmInterruptSspTables initial value

 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 62 +
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 72 
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c |  2 +-
 3 files changed, 107 insertions(+), 29 deletions(-)

-- 
2.26.2.windows.1



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