from:"Ashraf Ali S"

Re: [edk2-devel] [PATCH] IntelFsp2Pkg/PatchFv.py: FIX for GCC 32BIT build error

2024-04-22 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Duggapu, Chinni B  
Sent: Tuesday, April 23, 2024 9:33 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; S, Ashraf Ali ; Kuo, Ted 

Subject: [PATCH] IntelFsp2Pkg/PatchFv.py: FIX for GCC 32BIT build error

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4762

Map file generating 8 byte address offset is not matched with the pattern 
defined in patchFv tool resulting build error.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ashraf Ali S 
Cc: Ted Kuo 

Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py 
index bd9aa71e3c..d35aa1dc9f 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -432,7 +432,7 @@ class Symbols:
 if reportLine.strip().find("Archive member included") != -1:   
  #GCC #0x1d55IoRead8-  
  patchMapFileMatchString = 
r"\s+(0x[0-9a-fA-F]{16})\s+([^\s][^0x][_a-zA-Z0-9\-]+)\s"+
patchMapFileMatchString = 
r"\s+(0x[0-9a-fA-F]{8,16})\s+([^\s][^0x][_a-zA-Z0-9\-]+)\s" 
matchKeyGroupIndex = 2 matchSymbolGroupIndex  = 1 
prefix = '_'-- 
2.44.0.windows.1



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Re: [edk2-devel] [PATCH v1 2/2] IntelFsp2Pkg/PatchFv.py: Python 3.12 support

2024-04-22 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Guo, Gua  
Sent: Monday, April 22, 2024 7:07 AM
To: devel@edk2.groups.io
Cc: Guo, Gua ; Chiu, Chasel ; 
Desimone, Nathaniel L ; Duggapu, Chinni B 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Susovan Mohapatra 

Subject: [PATCH v1 2/2] IntelFsp2Pkg/PatchFv.py: Python 3.12 support

From: Gua Guo 

Ref to https://docs.python.org/3/whatsnew/3.12.html
A backslash-character pair that is not a valid escape sequence now generates

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Gua Guo 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py 
index 73ab877c71..bd9aa71e3c 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -143,7 +143,7 @@ class Symbols:
 fdIn.close() fvInfo['Base'] = 0 for rptLine in 
rptLines:-match = 
re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", rptLine)+match 
= re.match(r"^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", rptLine) if 
match: fvInfo['Base'] = int(match.group(1), 16) 
break@@ -312,7 +312,7 @@ class Symbols:
 self.fdBase = 0x while (rptLine != "" ): 
#EFI_BASE_ADDRESS = 0xFFFDF400-match = 
re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", rptLine)+match 
= re.match(r"^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", rptLine) if 
match is not None: self.fdBase = int(match.group(1), 16) - 
fvOffset break@@ -340,7 +340,7 @@ class Symbols:
 fdIn = open(fvTxtFile, "r") rptLine  = fdIn.readline() 
while (rptLine != "" ):-match = 
re.match("(0x[a-fA-F0-9]+)\s([0-9a-fA-F\-]+)", rptLine)+match = 
re.match(r"(0x[a-fA-F0-9]+)\s([0-9a-fA-F\-]+)", rptLine) if match 
is not None: if match.group(2) in self.dictFfsOffset:   
  self.dictFfsOffset[fvName + ':' + match.group(2)] = "0x%08X" % 
(int(match.group(1), 16) + fvOffset)@@ -374,10 +374,10 @@ class Symbols:
 while (rptLine != "" ): if rptLine[0] != ' ':  
   #DxeIpl (Fixed Flash Address, BaseAddress=0x00fffb4310, 
EntryPoint=0x00fffb4958,Type=PE)-match = 
re.match("([_a-zA-Z0-9\-]+)\s\(.+BaseAddress=(0x[0-9a-fA-F]+),\s+EntryPoint=(0x[0-9a-fA-F]+),\s*Type=\w+\)",
 rptLine)+match = 
re.match(r"([_a-zA-Z0-9\-]+)\s\(.+BaseAddress=(0x[0-9a-fA-F]+),\s+EntryPoint=(0x[0-9a-fA-F]+),\s*Type=\w+\)",
 rptLine) if match is None: #DxeIpl (Fixed 
Flash Address, BaseAddress=0x00fffb4310, EntryPoint=0x00fffb4958)-  
  match = 
re.match("([_a-zA-Z0-9\-]+)\s\(.+BaseAddress=(0x[0-9a-fA-F]+),\s+EntryPoint=(0x[0-9a-fA-F]+)\)",
 rptLine)+match = 
re.match(r"([_a-zA-Z0-9\-]+)\s\(.+BaseAddress=(0x[0-9a-fA-F]+),\s+EntryPoint=(0x[0-9a-fA-F]+)\)",
 rptLine) if match is not None: foundModHdr 
= True modName = match.group(1)@@ -386,7 +386,7 @@ class 
Symbols:
 self.dictModBase['%s:BASE'  % modName] = int 
(match.group(2), 16) self.dictModBase['%s:ENTRY' % modName] 
= int (match.group(3), 16) 
#(GUID=86D70125-BAA3-4296-A62F-602BEBBB9081 .textbaseaddress=0x00fffb4398 
.databaseaddress=0x00fffb4178)-match = 
re.match("\(GUID=([A-Z0-9\-]+)\s+\.textbaseaddress=(0x[0-9a-fA-F]+)\s+\.databaseaddress=(0x[0-9a-fA-F]+)\)",
 rptLine)+match = 
re.match(r"\(GUID=([A-Z0-9\-]+)\s+\.textbaseaddress=(0x[0-9a-fA-F]+)\s+\.databaseaddress=(0x[0-9a-fA-F]+)\)",
 rptLine) if match is not None: if 
foundModHdr: foundModHdr = False@@ -399,7 +399,7 @@ 
class Symbols:
 else: #   0x00fff8016c__ModuleEntryPoint   
  foundModHdr = False-match = 
re.match("^\s+(0x[a-z0-9]+)\s+([_a-zA-Z0-9]+)", rptLine)+match 
= re.match(r"^\s+(0x[a-z0-9]+)\s+([_a-zA-Z0-9]+)", rptLine) if 
match is not None: self.dictSymbolAddress["%s:%s"%(modName, 
match.group(2))] = match.group(1) rptLine  = fdIn.readline()@@ 
-432,14 +432,14 @@ class Symbols:
 if reportLine.strip().find("Archive member included") != -1:   
  #GCC #0x1d55IoRead8-  
  patchMa

Re: [edk2-devel] [PATCH v1 1/2] IntelFsp2Pkg/GenCfgOpt.py: Python 3.12 support

2024-04-22 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Guo, Gua  
Sent: Monday, April 22, 2024 7:07 AM
To: devel@edk2.groups.io
Cc: Guo, Gua ; Chiu, Chasel ; 
Desimone, Nathaniel L ; Duggapu, Chinni B 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Susovan Mohapatra 

Subject: [PATCH v1 1/2] IntelFsp2Pkg/GenCfgOpt.py: Python 3.12 support

From: Gua Guo 

Ref to https://docs.python.org/3/whatsnew/3.12.html
A backslash-character pair that is not a valid escape sequence now generates

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Gua Guo 
---
 IntelFsp2Pkg/Tools/GenCfgOpt.py | 96 -
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py 
index 13be81ddbc..79923c07ed 100644
--- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
+++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
@@ -136,7 +136,7 @@ class CLogicalExpression:
 var = var.strip() if   re.match('^0x[a-fA-F0-9]+$', var):  
   value = int(var, 16)-elif re.match('^[+-]?\d+$', var):+
elif re.match(r'^[+-]?\d+$', var): value = int(var, 10) 
else: value = None@@ -147,7 +147,7 @@ class CLogicalExpression:
 var = '' while not self.isLast(): char = 
self.getCurr()-if re.match('^[\w.]', char):+if 
re.match(r'^[\w.]', char): var += char 
self.moveNext() else:@@ -161,7 +161,7 @@ class CLogicalExpression:
  def parseSingleOp(self): self.skipSpace()-if 
re.match('^NOT\W', self.getCurr(-1)):+if re.match(r'^NOT\W', 
self.getCurr(-1)): self.moveNext(3) op  = 
self.parseBrace() val = self.getNumber (op)@@ -225,7 +225,7 @@ 
class CLogicalExpression:
 value = self.parseCompare() while True: 
self.skipSpace()-if re.match('^AND\W', self.getCurr(-1)):+  
  if re.match(r'^AND\W', self.getCurr(-1)): self.moveNext(3)
 result = self.parseCompare() test = 
self.getNonNumber(result, value)@@ -243,10 +243,10 @@ class CLogicalExpression:
 while True: self.skipSpace() op = None-
if re.match('^XOR\W', self.getCurr(-1)):+if re.match(r'^XOR\W', 
self.getCurr(-1)): self.moveNext(3) op = '^'-   
 elif re.match('^OR\W', self.getCurr(-1)):+elif 
re.match(r'^OR\W', self.getCurr(-1)): self.moveNext(2)  
   op = '|' else:@@ -330,11 +330,11 @@ EndList
 continue if IsExpression: 
IsExpression = False-Match = re.match("(\w+)=(.+)", Macro)+ 
   Match = re.match(r"(\w+)=(.+)", Macro) if Match: 
self._MacroDict[Match.group(1)] = Match.group(2)
 else:-Match = re.match("(\w+)", Macro)+
Match = re.match(r"(\w+)", Macro) if Match: 
self._MacroDict[Match.group(1)] = '' if len(self._MacroDict) == 
0:@@ -355,7 +355,7 @@ EndList
  def ExpandMacros (self, Input, Preserve = False): Line = Input-   
 Match = re.findall("\$\(\w+\)", Input)+Match = 
re.findall(r"\$\(\w+\)", Input) if Match: for Each in 
Match:   Variable = Each[2:-1]@@ -370,7 +370,7 @@ EndList
  def ExpandPcds (self, Input): Line = Input-Match = 
re.findall("(\w+\.\w+)", Input)+Match = re.findall(r"(\w+\.\w+)", 
Input) if Match: for PcdName in Match:   if 
PcdName in self._PcdsDict:@@ -390,7 +390,7 @@ EndList
 return Result  def ValueToByteArray (self, ValueStr, Length):- 
   Match = re.match("\{\s*FILE:(.+)\}", ValueStr)+Match = 
re.match(r"\{\s*FILE:(.+)\}", ValueStr) if Match:   FileList = 
Match.group(1).split(',')   Result  = bytearray()@@ -427,7 +427,7 @@ 
EndList
 if Each[0] in ['"', "'"]: 
Result.extend(list(bytearray(Each[1:-1], 'utf-8'))) elif 
':' in Each:-Match= re.match("(.+):(\d+)b", Each)+  
  Match= re.match(r"(.+):(\d+)b", Each) 
if Match is None: raise Exception("Invald 
value list format '%s' !" % Each) InBitField = True@@ 
-539,7 +539,7 @@ EndList
   continue  Handle   = False-Match= 
re.match(

Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while parsing FMMTConfig.ini

2024-04-17 Thread Ashraf Ali S

Hi @Liming Gao @Rebecca Cran

Is this patch already pushed? As its been already reviewed.

Thanks.,
S, Ashraf Ali

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Ashraf Ali S
Sent: Monday, March 11, 2024 5:01 PM
To: devel@edk2.groups.io; Chen, Christine 
Cc: Rebecca Cran ; Liming Gao ; 
Feng, Bob C ; Chaganty, Rangasai V 

Subject: Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while 
parsing FMMTConfig.ini

Thanks for the review.

I have triggered the PR under basetools : 
https://github.com/tianocore/edk2-basetools/pull/122

Thanks.,
S, Ashraf Ali

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Yuwei Chen
Sent: Monday, March 11, 2024 1:22 PM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Rebecca Cran ; Liming Gao ; 
Feng, Bob C ; Chaganty, Rangasai V 

Subject: Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while 
parsing FMMTConfig.ini

Ali, please also create PR in BaseTools repo.
Reviewed-by: Yuwei Chen 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Wednesday, February 28, 2024 5:57 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Rebecca Cran 
> ; Liming Gao ; Feng, Bob 
> C ; Chen, Christine ; 
> Chaganty, Rangasai V 
> Subject: [PATCH] BaseTools: FMMT Skip empty Lines while parsing 
> FMMTConfig.ini
> 
> When the FMMTConf.ini file has empty lines then it used to throw 
> errors GuidTool load error!, this patch is to skip checking for empty 
> lines in the ini file
> 
> Cc: Rebecca Cran 
> Cc: Liming Gao 
> Cc: Bob Feng 
> Cc: Yuwei Chen 
> Cc: Chen Christine 
> Cc: Chaganty Rangasai V 
> 
> Signed-off-by: Ashraf Ali 
> ---
>  BaseTools/Source/Python/FMMT/core/GuidTools.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> index f6bdeffa50..f9cfd4ead0 100644
> --- a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> +++ b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> @@ -153,7 +153,7 @@ class GUIDTools:
>  config_data = fd.readlines()
>  for line in config_data:
>  try:
> -if not line.startswith("#"):
> +if not line.startswith("#") and line.strip():
>  guid, short_name, command = line.split()
>  new_format_guid =
> struct2stream(ModifyGuidFormat(guid.strip()))
>  self.tooldef[new_format_guid] = GUIDTool(
> --
> 2.42.0.windows.2













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Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore Rebasing

2024-04-10 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 
mailto:ashraf.al...@intel.com>>

Thanks.,
S, Ashraf Ali

From: Ni, Ray 
Sent: Wednesday, April 10, 2024 1:27 PM
To: Liu, Zhiguang ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Susovan Mohapatra 

Subject: Re: [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore 
Rebasing

Reviewed-by: Ray Ni mailto:ray...@intel.com>>

Thanks,
Ray

From: Liu, Zhiguang mailto:zhiguang@intel.com>>
Sent: Wednesday, April 10, 2024 15:08
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> 
mailto:devel@edk2.groups.io>>
Cc: Liu, Zhiguang mailto:zhiguang@intel.com>>; 
Chiu, Chasel mailto:chasel.c...@intel.com>>; Desimone, 
Nathaniel L 
mailto:nathaniel.l.desim...@intel.com>>; 
Duggapu, Chinni B 
mailto:chinni.b.dugg...@intel.com>>; Zeng, Star 
mailto:star.z...@intel.com>>; Kuo, Ted 
mailto:ted@intel.com>>; S, Ashraf Ali 
mailto:ashraf.al...@intel.com>>; Susovan Mohapatra 
mailto:susovan.mohapa...@intel.com>>; Ni, Ray 
mailto:ray...@intel.com>>
Subject: [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore 
Rebasing

Note this plugin only applies to 64-bit PSP
This optional plugin is designed to execute before the FSP SecCore to
rebase SecCore and PeiCore during runtime. If the FSP binary requires
rebasing at runtime, this module should be included within the FSP
binary. Additionally, specific patches must be applied to ensure proper
functionality. In the absence of this module, manual patching of API
offsets within the FSP header is necessary. To illustrate, let's
consider a scenario within FSP-S where 'FspSiliconInitEntry' is the
initial API to be executed post-rebase. Rather than directly inputting
the 'FspSiliconInit' offset into the 'FspSiliconInitEntryOffset' field
of the FSP header, the entry point of this module should be used.
Furthermore, the 'FspSiliconInit' offset should be placed into
'AsmGetFspOriginalEntry', which signifies the address to which this
module will jump.
It is also essential to patch the image bases of SecCore and PeiCore
to enable the rebasing functionality of this module.
The following is an example of how to apply the necessary patches:
Patch Address   Patch Value
 PreFspSec:_ModuleEntryPoint - [0x]
PreFspSec:SecCoreRelativeOffPreFspSec:AsmGetFspSecCoreImageBase
 - Fsp24SecCoreS:BASE
PreFspSec:PeiCoreRelativeOffPreFspSec:AsmGetFspPeiCoreImageBase
 - PeiCore:BASE
PreFspSec:SecEntryRelativeOff   PreFspSec:AsmGetFspOriginalEntry
 - Fsp24SecCoreS:FspSiliconInitApi

Cc: Chasel Chiu mailto:chasel.c...@intel.com>>
Cc: Nate DeSimone 
mailto:nathaniel.l.desim...@intel.com>>
Cc: Duggapu Chinni B 
mailto:chinni.b.dugg...@intel.com>>
Cc: Star Zeng mailto:star.z...@intel.com>>
Cc: Ted Kuo mailto:ted@intel.com>>
Cc: Ashraf Ali S mailto:ashraf.al...@intel.com>>
Cc: Susovan Mohapatra 
mailto:susovan.mohapa...@intel.com>>
Cc: Ray Ni mailto:ray...@intel.com>>
Signed-off-by: Zhiguang Liu 
mailto:zhiguang@intel.com>>
---
 IntelFsp2Pkg/IntelFsp2Pkg.dsc |   5 +
 IntelFsp2Pkg/PreFspSec/PreFspSec.c| 115 ++
 IntelFsp2Pkg/PreFspSec/PreFspSec.inf  |  62 ++
 .../PreFspSec/X64/PreFspSecCommon.nasm|  94 ++
 4 files changed, 276 insertions(+)
 create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.c
 create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.inf
 create mode 100644 IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm

diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
index f236a7010b..a2cc29c940 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
@@ -33,6 +33,8 @@
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
   
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
   
DebugDeviceLib|IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf

   # FSP override
   
DebugLib|IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
@@ -75,6 +77,9 @@
   IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf
   IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf

+[Components.X64]
+  IntelFsp2Pkg/PreFspSec/PreFspSec.inf
+
 [PcdsFixedAtBuild.common]
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
diff --git a/IntelFsp2Pkg/PreFspSec/PreFspSec.c 
b/IntelFsp2Pkg/PreFspSec/PreFspSec.c
new file mode 100644
index 00..b3b5

Re: [edk2-devel] [PATCH] IntelFsp2Pkg/Tools: Let PatchFv support to get Image Base.

2024-03-24 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Liu, Zhiguang  
Sent: Monday, March 18, 2024 2:39 PM
To: devel@edk2.groups.io
Cc: Liu, Zhiguang ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Mohapatra, Susovan 

Subject: [PATCH] IntelFsp2Pkg/Tools: Let PatchFv support to get Image Base.

Now, the value params of PatchFv support below value getting from map
file:
  ModuleName:FunctionName
  ModuleName:GlobalVariableName
  ModuleGuid:Offset
This patch add a new type ModuleName:KeyWord KeyWord now supports "BASE", 
indicating the address of the Image base.
For example, ModuleName:BASE will be the address of the Image base.
This will simplify the flow when user want to patch the Image base in the 
binary.

In the future, we can let the KeyWord support more based on future usage.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Zhiguang Liu 
---
 IntelFsp2Pkg/Tools/PatchFv.py   | 1 +
 IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py 
index 73ab877c71..0cab73255d 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -384,6 +384,7 @@ class Symbols:
 if len(modName) == 36:
modName = self.dictGuidNameXref[modName.upper()]
 self.dictModBase['%s:BASE'  % modName] = int 
(match.group(2), 16)
+self.dictSymbolAddress['%s:BASE'  % modName] = 
+ match.group(2)
 self.dictModBase['%s:ENTRY' % modName] = int 
(match.group(3), 16)
 #(GUID=86D70125-BAA3-4296-A62F-602BEBBB9081 
.textbaseaddress=0x00fffb4398 .databaseaddress=0x00fffb4178)
 match = 
re.match("\(GUID=([A-Z0-9\-]+)\s+\.textbaseaddress=(0x[0-9a-fA-F]+)\s+\.databaseaddress=(0x[0-9a-fA-F]+)\)",
 rptLine) diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index 205ad57773..b59e82c872 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -89,9 +89,10 @@ The entire argument includes the quote marks like in the 
example argument below:
 | 0x00BC   | 0xFFA2   | 188  | -94 
 |
 
 ```
-ModuleName:FunctionName | ModuleName:GlobalVariableName
+ModuleName:FunctionName | ModuleName:GlobalVariableName | 
+ModuleName:KeyWord
 ModuleGuid:Offset
 ```
+Note: KeyWord only supports "BASE" now, indicating the address of the PE Image 
base.
 
 ### Operators:
 
--
2.31.1.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/Tools: Updated iterator usage for Python 3 compatibility

2024-03-24 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Liu, Zhiguang  
Sent: Monday, March 18, 2024 2:39 PM
To: devel@edk2.groups.io
Cc: Liu, Zhiguang ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Mohapatra, Susovan 

Subject: [PATCH] IntelFsp2Pkg/Tools: Updated iterator usage for Python 3 
compatibility

Updated iterator usage for Python 3 compatibility
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Zhiguang Liu 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py 
index 0cab73255d..fd7476d576 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -720,7 +720,7 @@ class Symbols:
 def getModGuid(self, var):
 guid = (guid for guid,name in self.dictGuidNameXref.items() if 
name==var)
 try:
-value = guid.next()
+value = next(guid)
 except Exception:
 raise Exception("Unknown module name %s !" % var)
 return value
--
2.31.1.windows.1



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Re: [edk2-devel] [PATCH v2] IntelFsp2WrapperPkg: Error handling of FspmWrapperInit()

2024-03-14 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Ni, Ray  
Sent: Thursday, March 14, 2024 8:22 AM
To: devel@edk2.groups.io; Lin, Du 
Cc: S, Ashraf Ali ; Chiu, Chasel 
; Chen, Gang C ; Duggapu, Chinni 
B ; Desimone, Nathaniel L 
; Zeng, Star ; Mohapatra, 
Susovan ; Kuo, Ted 
Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2WrapperPkg: Error handling of 
FspmWrapperInit()

Reviewed-by: Ray Ni 

Thanks,
Ray
> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Du Lin
> Sent: Thursday, March 14, 2024 10:02 AM
> To: devel@edk2.groups.io
> Cc: Lin, Du ; S, Ashraf Ali 
> ; Chiu, Chasel ; Chen, 
> Gang C ; Duggapu, Chinni B 
> ; Desimone, Nathaniel L 
> ; Zeng, Star ; 
> Mohapatra, Susovan ; Kuo, Ted 
> 
> Subject: [edk2-devel] [PATCH v2] IntelFsp2WrapperPkg: Error handling 
> of
> FspmWrapperInit()
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4701
> 
> The error handling of FspmWrapperInit() is limited to ASSERT 
> statements only, which only works in debug builds, but not in release 
> builds.
> Fix the issue by enhancing the error handling of FspmWrapperInit() to 
> cover both debug builds and release builds.
> 
> Signed-off-by: Du Lin 
> Cc: Ashraf Ali S 
> Cc: Chasel Chiu 
> Cc: Chen Gang C 
> Cc: Duggapu Chinni B 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Susovan Mohapatra 
> Cc: Ted Kuo 
> ---
>  IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 8
> 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> index ba0c742fea..7f1deb9542 100644
> --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> @@ -197,12 +197,20 @@ FspmWrapperInit (
> 
>MeasurementExcludedFvPpi = AllocatePool (sizeof 
> (*MeasurementExcludedFvPpi));
>ASSERT (MeasurementExcludedFvPpi != NULL);
> +  if (MeasurementExcludedFvPpi == NULL) {
> +return EFI_OUT_OF_RESOURCES;
> +  }
> +
>MeasurementExcludedFvPpi->Count  = 1;
>MeasurementExcludedFvPpi->Fv[0].FvBase   = PcdGet32
> (PcdFspmBaseAddress);
>MeasurementExcludedFvPpi->Fv[0].FvLength = 
> ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
> (PcdFspmBaseAddress))->FvLength;
> 
>MeasurementExcludedPpiList = AllocatePool (sizeof 
> (*MeasurementExcludedPpiList));
>ASSERT (MeasurementExcludedPpiList != NULL);
> +  if (MeasurementExcludedPpiList == NULL) {
> +return EFI_OUT_OF_RESOURCES;
> +  }
> +
>MeasurementExcludedPpiList->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | 
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
>MeasurementExcludedPpiList->Guid  = 
> 
>MeasurementExcludedPpiList->Ppi   = MeasurementExcludedFvPpi;
> --
> 2.44.0.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Error handling of FspmWrapperInit()

2024-03-13 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Lin, Du  
Sent: Tuesday, March 12, 2024 2:58 PM
To: devel@edk2.groups.io
Cc: Lin, Du ; S, Ashraf Ali ; Chiu, 
Chasel ; Chen, Gang C ; Duggapu, 
Chinni B ; Desimone, Nathaniel L 
; Zeng, Star ; Mohapatra, 
Susovan ; Kuo, Ted 
Subject: [PATCH] IntelFsp2WrapperPkg: Error handling of FspmWrapperInit()

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4701

The error handling of FspmWrapperInit() is limited to ASSERT statements only, 
which only works in debug builds, but not in release builds.
Fix the issue by enhancing the error handling of FspmWrapperInit() to cover 
both debug builds and release builds.

Signed-off-by: Du Lin 
Cc: Ashraf Ali S 
Cc: Chasel Chiu 
Cc: Chen Gang C 
Cc: Duggapu Chinni B 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Susovan Mohapatra 
Cc: Ted Kuo 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c| 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index ba0c742fea..356baeeccf 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -196,13 +196,21 @@ FspmWrapperInit (
   EFI_PEI_PPI_DESCRIPTOR 
*MeasurementExcludedPpiList;
 
   MeasurementExcludedFvPpi = AllocatePool (sizeof (*MeasurementExcludedFvPpi));
-  ASSERT (MeasurementExcludedFvPpi != NULL);
+  if (MeasurementExcludedFvPpi == NULL) {
+ASSERT (FALSE);
+return EFI_OUT_OF_RESOURCES;
+  }
+
   MeasurementExcludedFvPpi->Count  = 1;
   MeasurementExcludedFvPpi->Fv[0].FvBase   = PcdGet32 (PcdFspmBaseAddress);
   MeasurementExcludedFvPpi->Fv[0].FvLength = ((EFI_FIRMWARE_VOLUME_HEADER 
*)(UINTN)PcdGet32 (PcdFspmBaseAddress))->FvLength;
 
   MeasurementExcludedPpiList = AllocatePool (sizeof 
(*MeasurementExcludedPpiList));
-  ASSERT (MeasurementExcludedPpiList != NULL);
+  if (MeasurementExcludedPpiList == NULL) {
+ASSERT (FALSE);
+return EFI_OUT_OF_RESOURCES;
+  }
+
   MeasurementExcludedPpiList->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
   MeasurementExcludedPpiList->Guid  = 

   MeasurementExcludedPpiList->Ppi   = MeasurementExcludedFvPpi;
--
2.44.0.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Error handling of TpmMeasureAndLogDataWithFlags()

2024-03-13 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Lin, Du  
Sent: Tuesday, March 12, 2024 2:50 PM
To: devel@edk2.groups.io
Cc: Lin, Du ; S, Ashraf Ali ; Chiu, 
Chasel ; Chen, Gang C ; Duggapu, 
Chinni B ; Desimone, Nathaniel L 
; Zeng, Star ; Mohapatra, 
Susovan ; Kuo, Ted 
Subject: [PATCH] IntelFsp2WrapperPkg: Error handling of 
TpmMeasureAndLogDataWithFlags()

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4700

TpmMeasureAndLogDataWithFlags() computes the measure the code and log it into 
PCR 0. TpmMeasureAndLogData() computes the hash for the configuration. The same 
"Status" variable is used to store the return values for both of the functions. 
There is no error handling if
TpmMeasureAndLogDataWithFlags() returns an error Status.
Fix the issue by adding error handling for TpmMeasureAndLogDataWithFlags().

Signed-off-by: Du Lin 
Cc: Ashraf Ali S 
Cc: Chasel Chiu 
Cc: Chen Gang C 
Cc: Duggapu Chinni B 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Susovan Mohapatra 
Cc: Ted Kuo 
---
 .../Library/BaseFspMeasurementLib/FspMeasurementLib.c | 4 
 1 file changed, 4 insertions(+)

diff --git 
a/IntelFsp2WrapperPkg/Library/BaseFspMeasurementLib/FspMeasurementLib.c 
b/IntelFsp2WrapperPkg/Library/BaseFspMeasurementLib/FspMeasurementLib.c
index 2c017a4250..228277649b 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspMeasurementLib/FspMeasurementLib.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspMeasurementLib/FspMeasurementLi
+++ b.c
@@ -197,6 +197,10 @@ MeasureFspFirmwareBlobWithCfg (
  (UINTN)sizeof (DigestList),
  EDKII_TCG_PRE_HASH_LOG_ONLY
  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "TpmMeasureAndLogDataWithFlags failed - %r\n", 
Status));
+return Status;
+  }
 
   Status = TpmMeasureAndLogData (
  1,
--
2.26.2.windows.1



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Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while parsing FMMTConfig.ini

2024-03-11 Thread Ashraf Ali S

Thanks for the review.

I have triggered the PR under basetools : 
https://github.com/tianocore/edk2-basetools/pull/122

Thanks.,
S, Ashraf Ali

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Yuwei Chen
Sent: Monday, March 11, 2024 1:22 PM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Rebecca Cran ; Liming Gao ; 
Feng, Bob C ; Chaganty, Rangasai V 

Subject: Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while 
parsing FMMTConfig.ini

Ali, please also create PR in BaseTools repo.
Reviewed-by: Yuwei Chen 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Wednesday, February 28, 2024 5:57 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Rebecca Cran 
> ; Liming Gao ; Feng, Bob 
> C ; Chen, Christine ; 
> Chaganty, Rangasai V 
> Subject: [PATCH] BaseTools: FMMT Skip empty Lines while parsing 
> FMMTConfig.ini
> 
> When the FMMTConf.ini file has empty lines then it used to throw 
> errors GuidTool load error!, this patch is to skip checking for empty 
> lines in the ini file
> 
> Cc: Rebecca Cran 
> Cc: Liming Gao 
> Cc: Bob Feng 
> Cc: Yuwei Chen 
> Cc: Chen Christine 
> Cc: Chaganty Rangasai V 
> 
> Signed-off-by: Ashraf Ali 
> ---
>  BaseTools/Source/Python/FMMT/core/GuidTools.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> index f6bdeffa50..f9cfd4ead0 100644
> --- a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> +++ b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> @@ -153,7 +153,7 @@ class GUIDTools:
>  config_data = fd.readlines()
>  for line in config_data:
>  try:
> -if not line.startswith("#"):
> +if not line.startswith("#") and line.strip():
>  guid, short_name, command = line.split()
>  new_format_guid =
> struct2stream(ModifyGuidFormat(guid.strip()))
>  self.tooldef[new_format_guid] = GUIDTool(
> --
> 2.42.0.windows.2








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[edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while parsing FMMTConfig.ini

2024-02-28 Thread Ashraf Ali S

When the FMMTConf.ini file has empty lines then it used to throw errors
GuidTool load error!, this patch is to skip checking for empty lines in
the ini file

Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Yuwei Chen 
Cc: Chen Christine 
Cc: Chaganty Rangasai V 

Signed-off-by: Ashraf Ali 
---
 BaseTools/Source/Python/FMMT/core/GuidTools.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/FMMT/core/GuidTools.py 
b/BaseTools/Source/Python/FMMT/core/GuidTools.py
index f6bdeffa50..f9cfd4ead0 100644
--- a/BaseTools/Source/Python/FMMT/core/GuidTools.py
+++ b/BaseTools/Source/Python/FMMT/core/GuidTools.py
@@ -153,7 +153,7 @@ class GUIDTools:
 config_data = fd.readlines()
 for line in config_data:
 try:
-if not line.startswith("#"):
+if not line.startswith("#") and line.strip():
 guid, short_name, command = line.split()
 new_format_guid = 
struct2stream(ModifyGuidFormat(guid.strip()))
 self.tooldef[new_format_guid] = GUIDTool(
-- 
2.42.0.windows.2



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Re: [edk2-devel] [PATCH] BaseTools: Optimize GenerateByteArrayValue and CollectPlatformGuids APIs

2024-01-21 Thread Ashraf Ali S

Hi., @Kinney, Michael D

The main API which is modified in this Patch is GenerateByteArrayValue.

This API is used to return the list of SKUID.TokenSpaceGuid.VpdName|VPD 
STRUCT|Binary Data which will be stored in Output.txt
Example: 
SAMPLESKUID.STANDARD.gEfiMdePkgTokenSpaceGuid.SampleVpd|SAMPLE_STRUCT[]|{0x01,0x01,0x05,0x09,0x02}

This VPD/PCD is coming from either the DEC file or the DSC file.

GenerateByteArrayValue API is used to create the PcdValueInit.exe and it's 
equivalent C and Make File.

When there is no change in DEC or DSC VPD/PCD still it used to do the same 
process again in the incremental build which is time consuming.
In my project this API is used to take 3min of time with High end server 
(64Threads) and 3.5Min in Laptop (16 threads with performance mode enabled) 
only for GenerateByteArrayValue API.

This  patch will check if there are any change in the DEC/DSC VPDs/PCDs2, if 
there is any change in VPD the current flow is not affect. (it will create the 
PcdRecordList.json and copy Output.txt for Arch folder with the project. Ex: 
Build\{Project}Pkg\DEBUG_VS2019\PcdValueInit\{IA32/X64/Any}\PcdRecordList.json 
and Build\{Project}Pkg\DEBUG_VS2019\PcdValueInit\{IA32/X64/Any}\Output.txt)
If there is no change the DSC/DEC VPDs it will read the data from Output.txt 
and return the same data. (we will compare the Input structure and 
PcdRecordList.json) if there is any mismatch then it there change in VPDs if 
not then no change in VPDs).

Unit testing from my side as follows:
* Build the Firmware.
* PcdRecordList.json and Output.txt will be created based on the Arch.
* Build the Firmware again without any change.
* It will read the Output.txt and return the data. (it will match Input 
PCD/VPD list and compare with existing PcdRecordList.json)
* I verified the return length and content GenerateByteArrayValue (it's 
same with and without my changes)
* Build the Firmware again my modifying the VPDs in DSC file
* Change in VPDs, it will regenerate PcdRecordList.json file
*  it will create the Exe file and Output.txt
* New Output.txt will be copied to above path.
* Build the Firmware again by modifying the VPDs in DEC file.
* Change in VPDs, it will regenerate PcdRecordList.json file
*  it will create the Exe file and Output.txt
* New Output.txt will be copied to above path.
* Build the Firmware again without modifying the code.
* It will read the Output.txt and return the data.
* I verified the return length and content GenerateByteArrayValue (it's 
same with and without my changes)


There is no impact on the Boot/cache.
This patch is used to reduce the incremental build time by checking if the 
VPDs/PCDs are changed or not, if not changed then it will return the previous 
stored data.

Thanks.,
S, Ashraf Ali

-Original Message-
From: Kinney, Michael D  
Sent: Saturday, January 20, 2024 7:36 AM
To: devel@edk2.groups.io; S, Ashraf Ali 
Cc: Chen, Christine ; Rebecca Cran ; 
Liming Gao ; Feng, Bob C ; 
Chan, Amy ; Chaganty, Rangasai V 
; Solanki, Digant H 
; Kinney, Michael D 
Subject: RE: [edk2-devel] [PATCH] BaseTools: Optimize GenerateByteArrayValue 
and CollectPlatformGuids APIs

Hi Ashraf,

What is captured in the file?

What PCD/VPD changes will invalidate the cache?  Just the number and type of 
PCD/VPD elements or their default values/sizes?

How was this tested?  Were all conditions that invalidate the cache tested?  I 
ask because incremental build is a very important feature and if there is any 
logic error in the cache management of a file like this, it will cause 
unexpected behavior and developers will not trust incremental builds.

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Ashraf 
> Ali S
> Sent: Tuesday, January 16, 2024 11:55 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Chen, Christine 
> ; Rebecca Cran ; Liming Gao 
> ; Feng, Bob C ; Chan, 
> Amy ; Chaganty, Rangasai V 
> ; Solanki, Digant H 
> 
> Subject: [edk2-devel] [PATCH] BaseTools: Optimize 
> GenerateByteArrayValue and CollectPlatformGuids APIs
> 
> During the Incremental build GenerateByteArrayValue used to generate 
> the ByteArrayValue even when there is no change in the PCD/VPDs. which 
> is time consuming API based on the number of PCD/VPDs and SKU IDs.
> 
> The optimization is that GenerateByteArrayValue is used to store the 
> PcdRecordList in a JSON file for each of the arch. and during the 
> Incremental build this API will check if there is any change in the 
> PCD /VPDs then rest of the flow remains the same. if there is no 
> change then it will return the provious build data.
> 
> Flow:
> during the 1st build PcdRecordList.json is not exists, PcdRecordList 
> will be dumped to json file. and it will copy the output.txt as well.
> Note: as the output.txt are different for different Ar

[edk2-devel] [PATCH] BaseTools: Optimize GenerateByteArrayValue and CollectPlatformGuids APIs

2024-01-16 Thread Ashraf Ali S

During the Incremental build GenerateByteArrayValue used to generate the
ByteArrayValue even when there is no change in the PCD/VPDs. which is
time consuming API based on the number of PCD/VPDs and SKU IDs.

The optimization is that GenerateByteArrayValue is used to store the
PcdRecordList in a JSON file for each of the arch. and during the
Incremental build this API will check if there is any change in the PCD
/VPDs then rest of the flow remains the same. if there is no change then
it will return the provious build data.

Flow:
during the 1st build PcdRecordList.json is not exists, PcdRecordList
will be dumped to json file. and it will copy the output.txt as well.
Note: as the output.txt are different for different Arch, so it will be
stored in the Arch folder.
During the Incremental build check if there is any change in PCD/VPD.
if there is a change in VPD/PCD then recreate the PcdRecordList.json.
and rest of the flow remains same.
if there is no change in VPD/PCD read the output.txt and return the data

Cc: Yuwei Chen 
Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Amy Chan 
Cc: Sai Chaganty 
Cc: Digant H Solanki 
Signed-off-by: Ashraf Ali S 
---
 .../Source/Python/AutoGen/WorkspaceAutoGen.py | 16 ++---
 .../Source/Python/Workspace/DscBuildData.py   | 72 +++
 2 files changed, 64 insertions(+), 24 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py 
b/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
index 160e3a3cd3..eec9280c8e 100644
--- a/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
@@ -160,22 +160,18 @@ class WorkspaceAutoGen(AutoGen):
 
 def CollectPlatformGuids(self):
 oriInfList = []
-oriPkgSet = set()
-PlatformPkg = set()
+pkgSet = set()
 for Arch in self.ArchList:
 Platform = self.BuildDatabase[self.MetaFile, Arch, 
self.BuildTarget, self.ToolChain]
 oriInfList = Platform.Modules
 for ModuleFile in oriInfList:
 ModuleData = self.BuildDatabase[ModuleFile, Platform._Arch, 
Platform._Target, Platform._Toolchain]
-oriPkgSet.update(ModuleData.Packages)
-for Pkg in oriPkgSet:
-Guids = Pkg.Guids
-GlobalData.gGuidDict.update(Guids)
+pkgSet.update(ModuleData.Packages)
 if Platform.Packages:
-PlatformPkg.update(Platform.Packages)
-for Pkg in PlatformPkg:
-Guids = Pkg.Guids
-GlobalData.gGuidDict.update(Guids)
+pkgSet.update(Platform.Packages)
+for Pkg in pkgSet:
+Guids = Pkg.Guids
+GlobalData.gGuidDict.update(Guids)
 
 @cached_property
 def FdfProfile(self):
diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py 
b/BaseTools/Source/Python/Workspace/DscBuildData.py
index 4768099343..740b8e22be 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -37,6 +37,8 @@ from functools import reduce
 from Common.Misc import SaveFileOnChange
 from Workspace.BuildClassObject import PlatformBuildClassObject, StructurePcd, 
PcdClassObject, ModuleBuildClassObject
 from collections import OrderedDict, defaultdict
+import json
+import shutil
 
 def _IsFieldValueAnArray (Value):
 Value = Value.strip()
@@ -56,6 +58,7 @@ def _IsFieldValueAnArray (Value):
 
 PcdValueInitName = 'PcdValueInit'
 PcdValueCommonName = 'PcdValueCommon'
+PcdRecordListName = 'PcdRecordList.json'
 
 PcdMainCHeader = '''
 /**
@@ -1599,7 +1602,7 @@ class DscBuildData(PlatformBuildClassObject):
 S_pcd_set = DscBuildData.OverrideByComm(S_pcd_set)
 
 # Create a tool to caculate structure pcd value
-Str_Pcd_Values = self.GenerateByteArrayValue(S_pcd_set)
+Str_Pcd_Values = self.GenerateByteArrayValue(S_pcd_set, RecordList)
 
 if Str_Pcd_Values:
 for (skuname, StoreName, PcdGuid, PcdName, PcdValue) in 
Str_Pcd_Values:
@@ -2750,12 +2753,61 @@ class DscBuildData(PlatformBuildClassObject):
 ccflags.add(item)
 i +=1
 return ccflags
-def GenerateByteArrayValue (self, StructuredPcds):
+
+def GetStructurePcdSet (self, OutputValueFile):
+if not os.path.isfile(OutputValueFile):
+EdkLogger.error("GetStructurePcdSet", FILE_NOT_FOUND, "Output.txt 
doesn't exist", ExtraData=OutputValueFile)
+return []
+File = open (OutputValueFile, 'r')
+FileBuffer = File.readlines()
+File.close()
+
+#start update structure pcd final value
+StructurePcdSet = []
+for Pcd in FileBuffer:
+PcdValue = Pcd.split ('|')
+PcdInfo = PcdValue[0].split ('.')
+StructurePcdSet.append((PcdInfo[0], PcdInfo[1], PcdInfo[2], 
PcdInfo[3], PcdValue[2].strip()))
+re

[edk2-devel] [PATCH] BaseTools: Remove Duplicate sets of SkuName and SkuId from allskuset

2023-12-25 Thread Ashraf Ali S

Currently when the platform has many SKUs then allskuset will be having
so many duplicate. and while parsing the allskuset will take longer
time while assing Pcd.SkuInfoList.
This patch is to eliminate those duplicate entires to reduce the
build time

Cc: Yuwei Chen 
Cc: Rebecca Cran 
Cc: Liming Gao 
Cc: Bob Feng 
Cc: Amy Chan 
Cc: Sai Chaganty 
Signed-off-by: Ashraf Ali S 
---
 BaseTools/Source/Python/AutoGen/PlatformAutoGen.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py 
b/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
index 592d4824a4..dac81454a9 100644
--- a/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
@@ -707,6 +707,8 @@ class PlatformAutoGen(AutoGen):
 self._DynamicPcdList.extend(list(OtherPcdArray))
 self._DynamicPcdList.sort()
 allskuset = [(SkuName, Sku.SkuId) for pcd in self._DynamicPcdList for 
(SkuName, Sku) in pcd.SkuInfoList.items()]
+# Remove duplicate sets in the list
+allskuset = list(set(allskuset))
 for pcd in self._DynamicPcdList:
 if len(pcd.SkuInfoList) == 1:
 for (SkuName, SkuId) in allskuset:
-- 
2.39.1.windows.1



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Re: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64

2023-12-18 Thread Ashraf Ali S

Reviewed-by:  S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Kuo, Ted  
Sent: Monday, December 18, 2023 9:33 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Dong, Eric ; S, Ashraf 
Ali ; Duggapu, Chinni B ; 
Gao, Liming 
Subject: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support 
SecFspWrapperPlatformSecLib in X64

https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revsions and X64 feature.
 - PcdFspWrapperResetVectorInFsp
 - PcdFspWrapperBfvforResetVectorInFsp
 - PcdFsptUpdHeaderRevision
 - PcdFsptArchUpdHeaderRevision

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Eric Dong 
Cc: Ashraf Ali S 
Cc: Chinni B Duggapu 
Cc: Liming Gao 
Signed-off-by: Ted Kuo 
---
 .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h |  25 +-
 .../Ia32/SecEntry.nasm|   4 +-
 .../SecFspWrapperPlatformSecLib.inf   |  12 +-
 .../SecGetPerformance.c   |  11 +-
 .../SecPlatformInformation.c  |   8 +-
 .../SecRamInitData.c  |  56 -
 .../X64/PeiCoreEntry.nasm | 224 ++
 .../X64/SecEntry.nasm | 214 +
 .../X64/Stack.nasm|  72 ++
 .../Ia32 => Include}/Fsp.h|   4 +-
 .../Intel/MinPlatformPkg/MinPlatformPkg.dec   |  21 ++
 11 files changed, 629 insertions(+), 22 deletions(-)  create mode 100644 
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
 create mode 100644 
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
 create mode 100644 
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
 rename 
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
 => Include}/Fsp.h (86%)

diff --git 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
 
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..7c4ddc09a8 100644
--- 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
 /** @file -Copyright (c) 2017, Intel Corporation. All rights 
reserved.+Copyright (c) 2017 - 2023, Intel Corporation. All rights 
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -10,6 +10,28 
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
  #pragma pack(1) +#if defined (MDE_CPU_X64)+/** Fsp T Core UPD+**/+typedef 
struct {++/** Offset 0x0040+**/+  EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+  UINT64  
MicrocodeRegionSize;++/** Offset 0x0050+**/+  EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+  UINT64  
CodeRegionSize;+} FSPT_CORE_UPD;+#else /** Fsp T Core UPD **/ typedef struct 
{@@ -34,6 +56,7 @@ typedef struct {
 **/   UINT8   Reserved[16]; } FSPT_CORE_UPD;+#endif  
#pragma pack() diff --git 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
 
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
--- 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
 
;-- 
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright 
(c) 2019 - 2023, Intel Corporation. All rights reserved. ; 
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@  
; 
;-- 
-#include "Fsp.h"+#include   SECTION .text diff --git 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
 
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..99a04cc264 100644
--- 
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
 ## @file #  Provide FSP wrapper platform sec related function. #-#  Copyright 
(c) 2017 - 2021, Intel Corporation. All rights reserved.+#  Copyright (c) 
2017 - 2023, Intel Corpora

Re: [edk2-devel] [PATCH] UefiCpuPkg/ResetVector: Option for 1G Page Table Size increase

2023-11-30 Thread Ashraf Ali S

Hi., Ray

Yes, I agree. But if any device which needs to map above 512GB in Pre Memory 
(Early PreMem). 

if any device mapped any device below 512GB. And if the DRAM has 512GB then it 
would create a conflict.

So we are not changing the default page table size, keeping 512GB only. So that 
it will give room to decide the reset vector size based on the platform needs.

Sizes mentioned below:
512GB - 16KB
1TB  - 20KB
2TB  - 28KB

Thanks.,
S, Ashraf Ali

-Original Message-
From: Ni, Ray  
Sent: Friday, December 1, 2023 10:58 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul R ; West, Catharine 
; V, Sangeetha 
Subject: RE: [PATCH] UefiCpuPkg/ResetVector: Option for 1G Page Table Size 
increase

Ashraf,
When we implement the reset vector, we assume that 512GB page table occupies 
minimal flash size and also sufficient for XIP code.
Any code that wants more page table coverage should create a new page table, 
either in the temporary ram (when physical mem is not ready) or in physical ram.

Why does this patch increase the default 512 GB coverage?

Thanks,
Ray
> -Original Message-
> From: S, Ashraf Ali 
> Sent: Friday, December 1, 2023 1:35 AM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Kumar, Rahul R 
> ; Ni, Ray ; West, Catharine 
> ; V, Sangeetha 
> Subject: [PATCH] UefiCpuPkg/ResetVector: Option for 1G Page Table Size 
> increase
> 
> Currently 1G Page table is restricted 512GB. this patch can help to 
> increase the page table size based on the input. default will be 512GB 
> build option PAGE_TABLE_1G_SIZE is used to increase the page table 
> size
> 
> Cc: Rahul Kumar 
> Cc: Ray Ni 
> Cc: Catharine West 
> Cc: V Sangeetha 
> Signed-off-by: Ashraf Ali S 
> ---
>  UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt |  4 ++--
>  UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf   |  2 ++
>  UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm | 13 +++--
>  3 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
> b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
> index 4fcb15c3b1..4d153fc1a7 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
> +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
> @@ -1,10 +1,10 @@
> 
>  === HOW TO USE VTF0 ===
>  Add this line to your DSC [Components.IA32] or [Components.X64] section:
> -  UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
> +  UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> 
>  Add this line to your FDF FV section:
> -  INF  RuleOverride=RESET_VECTOR
> UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
> +  INF  RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> 
>  In your FDF FFS file rules sections add:
>[Rule.Common.SEC.RESET_VECTOR]
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> index 6b406163db..96106a4b11 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
> @@ -53,5 +53,7 @@
>  #   -DARCH_X64, -DARCH_IA32
>  #   * for using 1G page table:
>  #   -DPAGE_TABLE_1G
> +#   * for incresing the 1G page table size (Size in GBs):
> +#   -DPAGE_TABLE_1G_SIZE=1024
>  #   * for different debug channels:
>  #   -DDEBUG_SERIAL, -DDEBUG_PORT80, or not specify any debug channel
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
> b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
> index 7960b141be..b080dc5296 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
> @@ -1,7 +1,7 @@
>  
> ;-
> -
>  ; @file
>  ; Emits Page Tables for 1:1 mapping.
> -; If using 1G page table, map addresses 0 - 0x80 (512GB),
> +; If using 1G page table, map addresses 0 - 0x80 (512GB, Size 
> +can
> be increse via PAGE_TABLE_1G_SIZE),
>  ; else, map addresses 0 - 0x1 (4GB)  ;  ; Copyright (c) 2021 
> - 2023, Intel Corporation. All rights reserved.
> @@ -39,6 +39,15 @@ BITS64
>  %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)  %define 
> PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
> 
> +%ifdef PAGE_TABLE_1G_SIZE
> +  %define PAGE_PDPTE_1GB_SIZE PAGE_TABLE_1G_SIZE %else
> +  ;
> +  ; Default 512GB of 1G Page Table
> +  ;
> +  %define PAGE_PDPTE_1GB_SIZE 512
> +%endif
> +
>  ALIGN 16
> 
>  %ifdef PAGE_TABLE_1G
> @@ -47,7 +56,7 @@ Pdp:
>  ; Page-directory pointer table (512 * 1GB entries => 512GB)
>  ;
>  %assign i 0
> -%rep  512
> +%rep  PAGE_PDPTE_1GB_SIZE
>  DQPAGE_PDPTE_1GB(i)
>  %assign i i+1
>  %endrep
> --
> 2.39.1.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/PatchFv: Fix syntax issue in markdown manual

2023-11-30 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Desimone, Nathaniel L  
Sent: Friday, December 1, 2023 7:26 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chiu, Chasel ; Duggapu, 
Chinni B ; Ng, Ray Han Lim 
; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Mohapatra, Susovan 

Subject: [PATCH] IntelFsp2Pkg/PatchFv: Fix syntax issue in markdown manual

From: Ray Ni 

According to the markdown language syntax, headings should be after number 
signs (#). The number of number signs correspond to the heading level.
But current PatchFvUserManual.md doesn't insert a space between the number 
signs and the heading title, resulting the markdown file is not rendered well 
in markdown viewers.

The patch doesn't change any content but only adds spaces to ensure the 
headings are correctly recognized.

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Reviewed-by: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ray Han Lim Ng 
Cc: Star Zeng 
Cc: Ted Kuo 
Reviewed-by: Ashraf Ali S 
Cc: Susovan Mohapatra 
---
 .../Tools/UserManuals/PatchFvUserManual.md| 38 +--
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index f28eedf625..205ad57773 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,9 +1,9 @@
-#Name
+# Name
 **_PatchFv.py_** - The python script that patches the firmware volumes 
(**FV**)  with in the flash device (**FD**) file post FSP build.
 From version 0.60, script is capable of patching flash device (**FD**) 
directly.
 
-#Synopsis
+# Synopsis
 
 ```
 PatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch ["Offset, Value"]+ 
@@ -18,32 +18,32 @@ PatchFv FdFileDir FdFileName ["Offset, Value"]+
   | ["Offset, Value, $Command, @Comment"]+  ```
 
-#Description
+# Description
 The **_PatchFv.py_** tool allows the developer to fix up FD images to follow 
the  Intel FSP Architecture specification.  It also makes the FD image 
relocatable.
 The tool is written in Python and uses Python 2.7 or later to run.
 Consider using the tool in a build script.
 
-#FvBuildDir (Argument 1)
+# FvBuildDir (Argument 1)
 This is the first argument that **_PatchFv.py_** requires.  It is the build  
directory for all firmware volumes created during the FSP build. The path must  
be either an absolute path or a relevant path, relevant to the top level of the 
 FSP tree.
 
-Example usage:
+ Example usage:
 ```
  Build\YouPlatformFspPkg\%BD_TARGET%_%VS_VERSION%%VS_X86%\FV
 ```
 
 The example used contains Windows batch script %VARIABLES%.
 
-#FvFileBaseNames (Argument 2: Optional Part 1)
+# FvFileBaseNames (Argument 2: Optional Part 1)
 The firmware volume file base names (**_FvFileBaseNames_**) are the 
independent -Fv?s that are to be patched within the FD. (0 or more in the form
-**FVFILEBASENAME:**) The colon **:** is used for delimiting the single
+FVs that are to be patched within the FD. (0 or more in the form
+**FvFileBaseNames:**) The colon **:** is used for delimiting the single
 argument and must be appended to the end of each (**_FvFileBaseNames_**).
 
-Example usage:
+ Example usage:
 ```
 STAGE1:STAGE2:MANIFEST:YOURPLATFORM
 ```
@@ -55,14 +55,14 @@ In the example **STAGE1** is **STAGE1.Fv** in 
**YOURPLATFORM.fd**.
 Firmware device file name to patch (**_FdFileNameToPatch_**) is the base name 
of  the FD file that is to be patched. (1 only, in the form **YOURPLATFORM**)
 
-Example usage:
+ Example usage:
 ```
 STAGE1:STAGE2:MANIFEST:YOURPLATFORM
 ```
 
 In the example **YOURPLATFORM** is from **_YOURPLATFORM.fd_**
 
-#"Offset, Value[, Command][, Comment]" (Argument 3)
+# "Offset, Value[, Command][, Comment]" (Argument 3)
 The **_Offset_** can be a positive or negative number and represents where the
 **_Value_** to be patched is located within the FD. The **_Value_** is what  
will be written at the given **_Offset_** in the FD. Constants may be used for 
@@ -79,10 +79,10 @@ The entire argument includes the quote marks like in the 
example argument below:
 0xFFC0, SomeCore:__EntryPoint - [0x00F0],@SomeCore Entry  ```
 
-###Constants:
+### Constants:
  Hexadecimal (use **0x** as prefix) | Decimal
 
-Examples:
+ Examples:
 
 | **Positive Hex** | **Negative Hex** | **Positive Decimal** | **Negative 
Decimal** |  | ---: | ---: | ---: | 
---: | @@ -93,7 +93,7 @@ ModuleName:FunctionName | 
ModuleName:GlobalVariableName  ModuleGuid:Offset  ```
 
-###Operators:
+### Operators:
 
 ```
 
@@ -113,7 +113,7 @@ From version 0.60 tool allows to pass flash device file 
path as Argument 1 and  flash device name as Argument 2 and rules for passing 
offset & value are same  as explained in the previous sections.
 
-Example usage:
+ Example usage:
 Argu

[edk2-devel] [PATCH] UefiCpuPkg/ResetVector: Option for 1G Page Table Size increase

2023-11-30 Thread Ashraf Ali S

Currently 1G Page table is restricted 512GB. this patch can help to
increase the page table size based on the input. default will be 512GB
build option PAGE_TABLE_1G_SIZE is used to increase the page table size

Cc: Rahul Kumar 
Cc: Ray Ni 
Cc: Catharine West 
Cc: V Sangeetha 
Signed-off-by: Ashraf Ali S 
---
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt |  4 ++--
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf   |  2 ++
 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm | 13 +++--
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt 
b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
index 4fcb15c3b1..4d153fc1a7 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
+++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
@@ -1,10 +1,10 @@
 
 === HOW TO USE VTF0 ===
 Add this line to your DSC [Components.IA32] or [Components.X64] section:
-  UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
+  UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
 
 Add this line to your FDF FV section:
-  INF  RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
+  INF  RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
 
 In your FDF FFS file rules sections add:
   [Rule.Common.SEC.RESET_VECTOR]
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf 
b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
index 6b406163db..96106a4b11 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
@@ -53,5 +53,7 @@
 #   -DARCH_X64, -DARCH_IA32
 #   * for using 1G page table:
 #   -DPAGE_TABLE_1G
+#   * for incresing the 1G page table size (Size in GBs):
+#   -DPAGE_TABLE_1G_SIZE=1024
 #   * for different debug channels:
 #   -DDEBUG_SERIAL, -DDEBUG_PORT80, or not specify any debug channel
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm 
b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
index 7960b141be..b080dc5296 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -1,7 +1,7 @@
 ;--
 ; @file
 ; Emits Page Tables for 1:1 mapping.
-; If using 1G page table, map addresses 0 - 0x80 (512GB),
+; If using 1G page table, map addresses 0 - 0x80 (512GB, Size can be 
increse via PAGE_TABLE_1G_SIZE),
 ; else, map addresses 0 - 0x1 (4GB)
 ;
 ; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
@@ -39,6 +39,15 @@ BITS64
 %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
 %define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
 
+%ifdef PAGE_TABLE_1G_SIZE
+  %define PAGE_PDPTE_1GB_SIZE PAGE_TABLE_1G_SIZE
+%else
+  ;
+  ; Default 512GB of 1G Page Table
+  ;
+  %define PAGE_PDPTE_1GB_SIZE 512
+%endif
+
 ALIGN 16
 
 %ifdef PAGE_TABLE_1G
@@ -47,7 +56,7 @@ Pdp:
 ; Page-directory pointer table (512 * 1GB entries => 512GB)
 ;
 %assign i 0
-%rep  512
+%rep  PAGE_PDPTE_1GB_SIZE
 DQPAGE_PDPTE_1GB(i)
 %assign i i+1
 %endrep
-- 
2.39.1.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function

2023-11-13 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Ni, Ray  
Sent: Monday, November 13, 2023 1:09 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Zeng, 
Star ; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan 
Subject: [PATCH] IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function

FspMultiPhaseWorker() is a local function that's called from
FspMultiPhaseMemInitApiHandler()
and FspMultiPhaseSiInitApiHandlerV2().

Remove "EFIAPI" from its function header.

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ray Han Lim Ng 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
---
 IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c 
b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c
index 3786da91b1..4fc4104226 100644
--- a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c
@@ -1,7 +1,7 @@
 /** @file

   FSP MultiPhase library.

 

-  Copyright (c) 2022, Intel Corporation. All rights reserved.

+  Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.

   SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

@@ -58,7 +58,6 @@ FspVariableRequestSwitchStack (
   @retval EFI_DEVICE_ERRORFSP initialization failed.

 **/

 EFI_STATUS

-EFIAPI

 FspMultiPhaseWorker (

   IN UINT32  ApiIdx,

   IN VOID*ApiParam

-- 
2.39.1.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Add variable initialization

2023-11-09 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Chen, Gang C  
Sent: Thursday, November 9, 2023 3:42 PM
To: Guo, Gua ; Hsu, JasonX ; 
devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star 
; Chiu, Chasel ; Duggapu, Chinni B 
; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan ; Lu, 
James 
Subject: RE: [PATCH] IntelFsp2WrapperPkg: Add variable initialization

Reviewed-by: Chen Gang C 

BR
Gang

-Original Message-
From: Guo, Gua  
Sent: Thursday, November 9, 2023 6:07 PM
To: Hsu, JasonX ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star 
; Chiu, Chasel ; Chen, Gang C 
; Duggapu, Chinni B ; Kuo, 
Ted ; S, Ashraf Ali ; Mohapatra, 
Susovan ; Lu, James 
Subject: RE: [PATCH] IntelFsp2WrapperPkg: Add variable initialization

Reviewed-by: Gua Guo 

-Original Message-
From: Hsu, JasonX  
Sent: Thursday, November 9, 2023 6:01 PM
To: devel@edk2.groups.io
Cc: Hsu, JasonX ; Desimone, Nathaniel L 
; Zeng, Star ; Chiu, 
Chasel ; Chen, Gang C ; Duggapu, 
Chinni B ; Kuo, Ted ; S, Ashraf 
Ali ; Mohapatra, Susovan ; 
Lu, James ; Guo, Gua 
Subject: [PATCH] IntelFsp2WrapperPkg: Add variable initialization

From: "JasonX.Hsu" 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4595

Fix build error when remove "-Wno-sometimes-uninitialized" option, Add variable 
"FspMultiPhaseApiOffset" initialization.

Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Chasel Chiu 
Cc: Chen Gang C 
Cc: Duggapu Chinni B 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Jason Hsu 
---
 .../PeiFspWrapperMultiPhaseProcessLib.c  | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
 
b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
index 834dca07a9..224c24881d 100644
--- 
a/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
+++ b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspW
+++ rapperMultiPhaseProcessLib.c
@@ -80,6 +80,7 @@ CallFspMultiPhaseEntry (
   BOOLEAN IsVariableServiceRequest;   FSP_MULTI_PHASE_PARAMS  
*FspMultiPhaseParamsPtr; +  FspMultiPhaseApiOffset   = 0;   
FspMultiPhaseParamsPtr   = (FSP_MULTI_PHASE_PARAMS *)FspMultiPhaseParams;   
IsVariableServiceRequest = FALSE;   if 
((FspMultiPhaseParamsPtr->MultiPhaseAction == 
EnumMultiPhaseGetVariableRequestInfo) ||-- 
2.39.1.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/PatchFv: Fix syntax issue in markdown manual

2023-11-01 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Ni, Ray  
Sent: Wednesday, November 1, 2023 3:00 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Zeng, 
Star ; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan 
Subject: [PATCH] IntelFsp2Pkg/PatchFv: Fix syntax issue in markdown manual

According to the markdown language syntax, headings should be after number 
signs (#). The number of number signs correspond to the heading level.
But current PatchFvUserManual.md doesn't insert a space between the number 
signs and the heading title, resulting the markdown file is not rendered well 
in markdown viewers.

The patch doesn't change any content but only adds spaces to ensure the 
headings are correctly recognized.

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc:  Duggapu Chinni B 
Cc: Ray Han Lim Ng 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
---
 .../Tools/UserManuals/PatchFvUserManual.md| 38 +--
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md 
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index f28eedf625..205ad57773 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,9 +1,9 @@
-#Name+# Name **_PatchFv.py_** - The python script that patches the firmware 
volumes (**FV**) with in the flash device (**FD**) file post FSP build. From 
version 0.60, script is capable of patching flash device (**FD**) directly. 
-#Synopsis+# Synopsis  ``` PatchFv FvBuildDir 
[FvFileBaseNames:]FdFileBaseNameToPatch ["Offset, Value"]+@@ -18,32 +18,32 @@ 
PatchFv FdFileDir FdFileName ["Offset, Value"]+
   | ["Offset, Value, $Command, @Comment"]+ ``` -#Description+# Description The 
**_PatchFv.py_** tool allows the developer to fix up FD images to follow the 
Intel FSP Architecture specification.  It also makes the FD image relocatable. 
The tool is written in Python and uses Python 2.7 or later to run. Consider 
using the tool in a build script. -#FvBuildDir (Argument 1)+# FvBuildDir 
(Argument 1) This is the first argument that **_PatchFv.py_** requires.  It is 
the build directory for all firmware volumes created during the FSP build. The 
path must be either an absolute path or a relevant path, relevant to the top 
level of the FSP tree. -Example usage:+ Example usage: ```  
Build\YouPlatformFspPkg\%BD_TARGET%_%VS_VERSION%%VS_X86%\FV ```  The example 
used contains Windows batch script %VARIABLES%. -#FvFileBaseNames (Argument 2: 
Optional Part 1)+# FvFileBaseNames (Argument 2: Optional Part 1) The firmware 
volume file base names (**_FvFileBaseNames_**) are the independent-Fv?s that 
are to be patched within the FD. (0 or more in the form-**FVFILEBASENAME:**) 
The colon **:** is used for delimiting the single+FVs that are to be patched 
within the FD. (0 or more in the form+**FvFileBaseNames:**) The colon **:** is 
used for delimiting the single argument and must be appended to the end of each 
(**_FvFileBaseNames_**). -Example usage:+ Example usage: ``` 
STAGE1:STAGE2:MANIFEST:YOURPLATFORM ```@@ -55,14 +55,14 @@ In the example 
**STAGE1** is **STAGE1.Fv** in **YOURPLATFORM.fd**.
 Firmware device file name to patch (**_FdFileNameToPatch_**) is the base name 
of the FD file that is to be patched. (1 only, in the form **YOURPLATFORM**) 
-Example usage:+ Example usage: ``` STAGE1:STAGE2:MANIFEST:YOURPLATFORM 
```  In the example **YOURPLATFORM** is from **_YOURPLATFORM.fd_** -#"Offset, 
Value[, Command][, Comment]" (Argument 3)+# "Offset, Value[, Command][, 
Comment]" (Argument 3) The **_Offset_** can be a positive or negative number 
and represents where the **_Value_** to be patched is located within the FD. 
The **_Value_** is what will be written at the given **_Offset_** in the FD. 
Constants may be used for@@ -79,10 +79,10 @@ The entire argument includes the 
quote marks like in the example argument below:
 0xFFC0, SomeCore:__EntryPoint - [0x00F0],@SomeCore Entry ``` 
-###Constants:+### Constants:  Hexadecimal (use **0x** as prefix) | Decimal 
-Examples:+ Examples:  | **Positive Hex** | **Negative Hex** | 
**Positive Decimal** | **Negative Decimal** | | ---: | 
---: | ---: | ---: |@@ -93,7 +93,7 
@@ ModuleName:FunctionName | ModuleName:GlobalVariableName  ModuleGuid:Offset 
``` -###Operators:+### Operators:  ``` @@ -113,7 +113,7 @@ From version 0.60 
tool allows to pass flash device file path as Argument 1 and  flash device name 
as Argument 2 and rules for passing offset & value are same as explained in the 
previous sections. -Example usage:+ Example usage: Argument 1 ```  
YouPlatformFspBinPkg\@@ -123,21 +123,21 @@ Argument 2
  Fsp_Rebased_T ``` -###Special Comm

Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bit

2023-10-31 Thread Ashraf Ali S

Reviewed-by: mailto:ashraf.al...@intel.com>>;

Thanks.,
S, Ashraf Ali

From: Kuo, Ted 
Sent: Tuesday, October 31, 2023 2:06 PM
To: Ni, Ray ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Zeng, 
Star ; S, Ashraf Ali ; Mohapatra, 
Susovan 
Subject: RE: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when 
calling C function in 64bit


Reviewed-by: Ted Kuo mailto:ted@intel.com>>

From: Ni, Ray mailto:ray...@intel.com>>
Sent: Tuesday, October 31, 2023 4:26 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Ni, Ray 
mailto:ray...@intel.com>>
Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>; 
Desimone, Nathaniel L 
mailto:nathaniel.l.desim...@intel.com>>; 
Duggapu, Chinni B 
mailto:chinni.b.dugg...@intel.com>>; Ng, Ray Han 
Lim mailto:ray.han.lim...@intel.com>>; Zeng, Star 
mailto:star.z...@intel.com>>; Kuo, Ted 
mailto:ted@intel.com>>; S, Ashraf Ali 
mailto:ashraf.al...@intel.com>>; Mohapatra, Susovan 
mailto:susovan.mohapa...@intel.com>>
Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when 
calling C function in 64bit

Sorry, I copied the maintainers from Maintainers.txt but forgot to change all 
M/R to "Cc". That caused not all the maintainers/reviewers are CCed.
I will fix the commit message before merging.

Thanks,
Ray

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> 
mailto:devel@edk2.groups.io>> on behalf of Ni, Ray 
mailto:ray...@intel.com>>
Sent: Tuesday, October 31, 2023 4:22 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> 
mailto:devel@edk2.groups.io>>
Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>
Subject: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when 
calling C function in 64bit

When FSP runs in API mode, it saves the IDTR in its own stack then
switches to bootloader's stack before it returns from FspMemoryInit.
Next time when the bootloader calls TempRamExit, FSP switches to
its own stack and restores IDTR from its stack saved earlier.

However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on
FSP's stack might be corrupted that results the following TempRamExit
call fails inside FSP due to PeiServices pointer cannot be retrieved
from IDT.base - 8.

The bug is the assembly code doesn't reserve 32 bytes before calling
the C routine in 64bit. According to the x86-64 calling convention,
caller is responsible for allocating 32 bytes of "shadow space" on the
stack right before calling the function (regardless of the actual
number of parameters used).

When FSP is built in optimization-off mode, the C routine makes use
of the 32-byte "shadow space" which is not reserved by the assembly
caller. That causes the IDTR saved on the stack is corrupted by the
C routine.
The patch fixes so by reserving the 32 bytes before calling C routine.

Signed-off-by: Ray Ni mailto:ray...@intel.com>>
Cc: Chasel Chiu mailto:chasel.c...@intel.com>>
M: Nate DeSimone 
mailto:nathaniel.l.desim...@intel.com>>
M: Duggapu Chinni B 
mailto:chinni.b.dugg...@intel.com>>
M: Ray Han Lim Ng mailto:ray.han.lim...@intel.com>>
R: Star Zeng mailto:star.z...@intel.com>>
R: Ted Kuo mailto:ted@intel.com>>
R: Ashraf Ali S mailto:ashraf.al...@intel.com>>
R: Susovan Mohapatra 
mailto:susovan.mohapa...@intel.com>>
---
 IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm 
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
index 1ea1220608..e3a7cf002f 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
@@ -1,6 +1,6 @@
 ;--

 ;

-; Copyright (c) 2022, Intel Corporation. All rights reserved.

+; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ; Abstract:

@@ -60,7 +60,9 @@ ASM_PFX(FspSwitchStack):


 ; Load new stack

 mov rcx, rsp

+sub rsp, 0x20

 callASM_PFX(SwapStack)

+add rsp, 0x20

 mov rsp, rax



 ; Restore previous contexts

--
2.39.1.windows.1



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Re: [edk2-devel] [edk2-platforms PATCH] Maintainers.txt: remove Isaac Oram's email address

2023-10-25 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Laszlo Ersek  
Sent: Wednesday, October 25, 2023 2:06 PM
To: edk2-devel-groups-io 
Cc: Abdul Lateef Attar ; Abner Chang 
; S, Ashraf Ali ; Chiu, Chasel 
; Dong, Eric ; Gao, Liming 
; Desimone, Nathaniel L 
; Nickle Wang ; Pedro 
Falcato ; Chaganty, Rangasai V 
; Ni, Ray ; Theo Jehl 

Subject: [edk2-platforms PATCH] Maintainers.txt: remove Isaac Oram's email 
address

Email to Isaac's address  bounces ("5.1.0 Address 
rejected"); remove that address.

Cc: Abdul Lateef Attar 
Cc: Abner Chang 
Cc: Ashraf Ali S 
Cc: Chasel Chiu 
Cc: Eric Dong 
Cc: Liming Gao 
Cc: Nate DeSimone 
Cc: Nickle Wang 
Cc: Pedro Falcato 
Cc: Rangasai V Chaganty 
Cc: Ray Ni 
Cc: Sai Chaganty 
Cc: Theo Jehl 
Signed-off-by: Laszlo Ersek 
---
 Maintainers.txt | 11 ---
 1 file changed, 11 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt index 3e72f53afa0d..affb2632e0db 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -148,7 +148,6 @@ R: Marvin Häuser   Features/Intel
 F: Features/Intel/
 M: Sai Chaganty 
-M: Isaac Oram 
 M: Nate DeSimone 
 R: Liming Gao 
 
@@ -159,7 +158,6 @@ R: Liming Gao 
 
 Features/Intel/OutOfBandManagement/IpmiFeaturePkg
 F: Features/Intel/OutOfBandManagement/IpmiFeaturePkg
-M: Isaac Oram 
 M: Nate DeSimone 
 R: Liming Gao 
 
@@ -171,14 +169,12 @@ R: Liming Gao   
Features/ManageabilityPkg
 F: Features/ManageabilityPkg/
 M: Abner Chang 
-M: Isaac Oram 
 R: Abdul Lateef Attar 
 R: Nickle Wang 
 
 Platform/Intel
 F: Platform/Intel/
 M: Sai Chaganty 
-M: Isaac Oram 
 M: Nate DeSimone 
 
 Platform/Intel/QuarkPlatformPkg
@@ -196,7 +192,6 @@ R: Nate DeSimone   
Platform/Intel/BoardModulePkg
 F: Platform/Intel/BoardModulePkg/
 M: Eric Dong 
-M: Isaac Oram 
 R: Liming Gao 
 
 Platform/Intel/KabylakeOpenBoardPkg
@@ -216,7 +211,6 @@ Platform/Intel/MinPlatformPkg
 F: Platform/Intel/MinPlatformPkg/
 M: Chasel Chiu 
 M: Nate DeSimone 
-M: Isaac Oram 
 R: Liming Gao 
 R: Eric Dong 
 
@@ -253,7 +247,6 @@ R: Saloni Kasbekar 
 
 Platform/Intel/WhitleyOpenBoardPkg
 F: Platform/Intel/WhitleyOpenBoardPkg/
-M: Isaac Oram 
 M: Nate DeSimone 
 M: Chasel Chiu 
 
@@ -279,14 +272,12 @@ M: Daniel Schaefer   Silicon/Intel
 F: Silicon/Intel/
 M: Rangasai V Chaganty 
-M: Isaac Oram 
 M: Nate DeSimone 
 
 Silicon/Intel/IntelSiliconPkg
 F: Silicon/Intel/IntelSiliconPkg/
 M: Ray Ni 
 M: Rangasai V Chaganty 
-M: Isaac Oram 
 R: Ashraf Ali S 
 
 Silicon/Intel/QuarkSocPkg
@@ -331,7 +322,6 @@ R: Saloni Kasbekar 
 
 Silicon/Intel/WhitleySiliconPkg
 F: Silicon/Intel/WhitleySiliconPkg/
-M: Isaac Oram 
 M: Nate DeSimone 
 M: Chasel Chiu 
 
@@ -377,7 +367,6 @@ R: Meenakshi Aggarwal 
 
 QEMU EDK II Minimum Platform Specification implementation
 F: Platform/Qemu/QemuOpenBoardPkg/
-M: Isaac Oram 
 M: Pedro Falcato 
 R: Theo Jehl 
 


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Re: [edk2-devel] [PATCH v1] IntelFsp2Pkg: Add get and set FspSmmInit upd data pointer functions

2023-08-24 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Thanks.,
S, Ashraf Ali

-Original Message-
From: Chiu, Chasel  
Sent: Friday, August 25, 2023 9:37 AM
To: Zhang, Hongbin1 ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Zeng, 
Star ; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan 
Subject: RE: [PATCH v1] IntelFsp2Pkg: Add get and set FspSmmInit upd data 
pointer functions

Reviewed-by: Chasel Chiu 

Thanks,
Chasel


> -Original Message-
> From: Zhang, Hongbin1 
> Sent: Thursday, August 24, 2023 8:15 PM
> To: devel@edk2.groups.io
> Cc: Zhang, Hongbin1 ; Chiu, Chasel 
> ; Desimone, Nathaniel L 
> ; Duggapu, Chinni B 
> ; Ng, Ray Han Lim 
> ; Zeng, Star ; Kuo, Ted 
> ; S, Ashraf Ali ; 
> Mohapatra, Susovan 
> Subject: [PATCH v1] IntelFsp2Pkg: Add get and set FspSmmInit upd data 
> pointer functions
> 
> FSP-SMM module need get and set FspSmmInit upd data pointer functions 
> to get and set upd settings.
> 
> Signed-off-by: Hongbin1 Zhang 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Duggapu Chinni B 
> Cc: Ray Han Lim Ng 
> Cc: Star Zeng 
> Cc: Ted Kuo 
> Cc: Ashraf Ali S 
> Cc: Susovan Mohapatra 
> ---
>  IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c | 41
> 
>  IntelFsp2Pkg/Include/Library/FspCommonLib.h  | 22 +++
>  2 files changed, 63 insertions(+)
> 
> diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> index 6f6a086111..d33d01fe22 100644
> --- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> +++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
> @@ -372,6 +372,47 @@ GetFspSiliconInitUpdDataPointer (
>return FspData->SiliconInitUpdPtr;
>  }
> 
> +/**
> +  This function sets the FspSmmInit UPD data pointer.
> +
> +  @param[in] SmmInitUpdPtr   FspSmmInit UPD data pointer.
> +**/
> +VOID
> +EFIAPI
> +SetFspSmmInitUpdDataPointer (
> +  IN VOID  *SmmInitUpdPtr
> +  )
> +{
> +  FSP_GLOBAL_DATA  *FspData;
> +
> +  //
> +  // Get the FSP Global Data Pointer
> +  //
> +  FspData = GetFspGlobalDataPointer ();
> +
> +  //
> +  // Set the FspSmmInit UPD data pointer.
> +  //
> +  FspData->SmmInitUpdPtr = SmmInitUpdPtr; }
> +
> +/**
> +  This function gets the FspSmmInit UPD data pointer.
> +
> +  @return FspSmmInit UPD data pointer.
> +**/
> +VOID *
> +EFIAPI
> +GetFspSmmInitUpdDataPointer (
> +  VOID
> +  )
> +{
> +  FSP_GLOBAL_DATA  *FspData;
> +
> +  FspData = GetFspGlobalDataPointer ();
> +  return FspData->SmmInitUpdPtr;
> +}
> +
>  /**
>Set FSP measurement point timestamp.
> 
> diff --git a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
> b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
> index 13b67f8822..12d993b7cc 100644
> --- a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
> +++ b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
> @@ -192,6 +192,28 @@ GetFspSiliconInitUpdDataPointer (
>VOID
>);
> 
> +/**
> +  This function sets the smm init UPD data pointer.
> +
> +  @param[in] SmmInitUpdPtr   smm init UPD data pointer.
> +**/
> +VOID
> +EFIAPI
> +SetFspSmmInitUpdDataPointer (
> +  IN VOID  *SmmInitUpdPtr
> +  );
> +
> +/**
> +  This function gets the smm init UPD data pointer.
> +
> +  @return smm init UPD data pointer.
> +**/
> +VOID *
> +EFIAPI
> +GetFspSmmInitUpdDataPointer (
> +  VOID
> +  );
> +
>  /**
>Set FSP measurement point timestamp.
> 
> --
> 2.37.0.windows.1



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Re: [edk2-devel] [PATCH] MdeModulePkg: AllocatePages for TranslateBmpToGopBlt

2023-07-23 Thread Ashraf Ali S

Hi.,

The observation is based on if the Library consumed in the PEI Phase (PostMem).

Thanks.,
S, Ashraf Ali

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Ard Biesheuvel
Sent: Friday, July 21, 2023 10:49 PM
To: devel@edk2.groups.io; Ck, Chitralekha 
Cc: Ni, Ray ; Gao, Zhichao ; S, Ashraf 
Ali ; Duggapu, Chinni B 
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg: AllocatePages for 
TranslateBmpToGopBlt

On Fri, 21 Jul 2023 at 17:38, chitralekha ck  wrote:
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4507
> AllocatePool limits to allocate memory of 64 KB at most.

What is the basis for this observation? In DXE, pool allocations are unbounded 
afaik.



> if the the image size is higher than that it will fail to allocate.
> change the function debug string to __func__
>

Please don't mix unrelated changes in the same patch.

> Cc: Ray Ni 
> Cc: Zhichao Gao 
> Cc: Ashraf Ali S 
> Cc: Chinni B Duggapu 
> Signed-off-by: chitralekha ck 
> ---
>  .../Library/BaseBmpSupportLib/BmpSupportLib.c | 58 
> +++
>  1 file changed, 33 insertions(+), 25 deletions(-)
>
> diff --git a/MdeModulePkg/Library/BaseBmpSupportLib/BmpSupportLib.c 
> b/MdeModulePkg/Library/BaseBmpSupportLib/BmpSupportLib.c
> index c5e885d7a6..d0833a721f 100644
> --- a/MdeModulePkg/Library/BaseBmpSupportLib/BmpSupportLib.c
> +++ b/MdeModulePkg/Library/BaseBmpSupportLib/BmpSupportLib.c
> @@ -52,7 +52,7 @@ const BMP_IMAGE_HEADER  mBmpImageHeaderTemplate = {
>  /**
>Translate a *.BMP graphics image to a GOP blt buffer. If a NULL Blt buffer
>is passed in a GopBlt buffer will be allocated by this routine 
> using
> -  EFI_BOOT_SERVICES.AllocatePool(). If a GopBlt buffer is passed in 
> it will be
> +  EFI_BOOT_SERVICES.AllocatePages(). If a GopBlt buffer is passed in 
> + it will be
>used if it is big enough.
>
>@param[in]   BmpImage  Pointer to BMP file.
> @@ -113,14 +113,14 @@ TranslateBmpToGopBlt (
>}
>
>if (BmpImageSize < sizeof (BMP_IMAGE_HEADER)) {
> -DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt: BmpImageSize too small\n"));
> +DEBUG ((DEBUG_ERROR, "%a: BmpImageSize too small\n", __func__));
>  return RETURN_UNSUPPORTED;
>}
>
>BmpHeader = (BMP_IMAGE_HEADER *)BmpImage;
>
>if ((BmpHeader->CharB != 'B') || (BmpHeader->CharM != 'M')) {
> -DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt: BmpHeader->Char fields 
> incorrect\n"));
> +DEBUG ((DEBUG_ERROR, "%a: BmpHeader->Char fields incorrect\n", 
> + __func__));
>  return RETURN_UNSUPPORTED;
>}
>
> @@ -128,12 +128,12 @@ TranslateBmpToGopBlt (
>// Doesn't support compress.
>//
>if (BmpHeader->CompressionType != 0) {
> -DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt: Compression Type 
> unsupported.\n"));
> +DEBUG ((DEBUG_ERROR, "%a: Compression Type unsupported\n", 
> + __func__));
>  return RETURN_UNSUPPORTED;
>}
>
>if ((BmpHeader->PixelHeight == 0) || (BmpHeader->PixelWidth == 0)) {
> -DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt: BmpHeader->PixelHeight or 
> BmpHeader->PixelWidth is 0.\n"));
> +DEBUG ((DEBUG_ERROR, "%a: BmpHeader PixelHeight or PixelWidth is 
> + 0\n", __func__));
>  return RETURN_UNSUPPORTED;
>}
>
> @@ -144,7 +144,8 @@ TranslateBmpToGopBlt (
>if (BmpHeader->HeaderSize != sizeof (BMP_IMAGE_HEADER) - OFFSET_OF 
> (BMP_IMAGE_HEADER, HeaderSize)) {
>  DEBUG ((
>DEBUG_ERROR,
> -  "TranslateBmpToGopBlt: BmpHeader->Headership is not as expected.  
> Headersize is 0x%x\n",
> +  "%a: BmpHeader->Headership is not as expected. Headersize is 0x%x\n",
> +  __func__,
>BmpHeader->HeaderSize
>));
>  return RETURN_UNSUPPORTED;
> @@ -161,7 +162,8 @@ TranslateBmpToGopBlt (
>if (EFI_ERROR (Status)) {
>  DEBUG ((
>DEBUG_ERROR,
> -  "TranslateBmpToGopBlt: invalid BmpImage... PixelWidth:0x%x 
> BitPerPixel:0x%x\n",
> +  "%a: invalid BmpImage. PixelWidth:0x%x BitPerPixel:0x%x\n",
> +  __func__,
>BmpHeader->PixelWidth,
>BmpHeader->BitPerPixel
>));
> @@ -172,7 +174,8 @@ TranslateBmpToGopBlt (
>if (EFI_ERROR (Status)) {
>  DEBUG ((
>DEBUG_ERROR,
> -  "TranslateBmpToGopBlt: invalid BmpImage... DataSizePerLine:0x%x\n",
> +  "%a: invalid BmpImage. DataSizePerLine:0x%x\n",
> +  __func__,
>DataSizePerLine
>));
>
> @@ -189,7 +192,8 @@ TranslateBmpToGopBlt (
>if (EFI_ERROR (Status)) {
>  DEBUG ((
>DEBUG_ERROR,
>

Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/SpiFvbService: Non-functional cleanup

2023-06-30 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Michael Kubacki
Sent: Friday, June 30, 2023 8:03 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V 
; Oram, Isaac W ; S, 
Ashraf Ali 
Subject: [edk2-devel] [edk2-platforms][PATCH v1 1/1] 
IntelSiliconPkg/SpiFvbService: Non-functional cleanup

From: Michael Kubacki 

During a review of this driver a number of improvements were noted such as 
strengthening function input validation, checking return values, making debug 
print error levels consistent in certain code blocks, etc.

These type of changes are made with no explicit change to driver functionality.

Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
 |  35 ++-
 
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c 
| 248 
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
 |  54 +++--
 
Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.h 
|  31 ++-
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.h
 |   6 +-
 5 files changed, 239 insertions(+), 135 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
index ab1cb2ef1622..ebbd9edaada3 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.
+++ c
@@ -2,16 +2,17 @@
   Defines data structure that is the volume header found.
   These data is intent to decouple FVB driver with FV header.
 
-Copyright (c) 2017, Intel Corporation. All rights reserved. -Copyright (c) 
Microsoft Corporation.
-SPDX-License-Identifier: BSD-2-Clause-Patent
+  Copyright (c) 2017, Intel Corporation. All rights reserved.  
+ Copyright (c) Microsoft Corporation.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #include "SpiFvbServiceCommon.h"
 
-#define FIRMWARE_BLOCK_SIZE 0x1
+#define FIRMWARE_BLOCK_SIZE SIZE_64KB
 #define FVB_MEDIA_BLOCK_SIZEFIRMWARE_BLOCK_SIZE
+
 typedef struct {
   EFI_PHYSICAL_ADDRESSBaseAddress;
   EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;
@@ -19,7 +20,7 @@ typedef struct {
 } EFI_FVB2_MEDIA_INFO;
 
 /**
-  Returns FVB media information for NV variable storage.
+  Returns FVB media information for a firmware volume.
 
   @return   FvbMediaInfo  A pointer to an instance of FVB media 
info produced by this function.
   The buffer is allocated internally to 
this function and it is the caller's @@ -100,8 +101,21 @@ 
FVB_MEDIA_INFO_GENERATOR mFvbMediaInfoGenerators[] = {
   GenerateNvStorageFvbMediaInfo
 };
 
+/**
+  Returns an empty firmware volume for the firmware volume at the given base 
address.
+
+  @param[in]FvBaseAddress   The base address of the firmware volume 
requested.
+  @param[out]   FvbInfo A pointer that will be set to a buffer for 
the firmware volume header
+at the given base address. The buffer is a 
pool allocation made in this function.
+
+  @retval EFI_SUCCESS   The firmware volume was returned 
successfully.
+  @retval EFI_INVALID_PARAMETER The FvbInfo pointer argument is NULL.
+  @retval EFI_NOT_FOUND The firmware volume was not found for the 
given base address.
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory to allocate a buffer 
to the hold the firmware volume.
+
+**/
 EFI_STATUS
-GetFvbInfo (
+GetGeneratedFvByAddress (
   IN  EFI_PHYSICAL_ADDRESS FvBaseAddress,
   OUT EFI_FIRMWARE_VOLUME_HEADER   **FvbInfo
   )
@@ -111,11 +125,19 @@ GetFvbInfo (
   UINTN   Index;
   EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;
 
+  if (FvbInfo == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
   for (Index = 0; Index < ARRAY_SIZE (mFvbMediaInfoGenerators); Index++) {
 Status = mFvbMediaInfoGenerators[Index]();
 ASSERT_EFI_ERROR (Status);
 if (!EFI_ERROR (Status) && (FvbMediaInfo.BaseAddress == FvBaseAddress)) {
   FvHeader = AllocateCopyPool (FvbMediaInfo.FvbInfo.HeaderLength, 
);
+  if (FvHeader == NULL) {
+ASSERT (FvHeader != NULL);
+return EFI_OUT_OF_RESOURCES;
+  }
 
   //
   // Update the checksum value of FV header.
@@ -136,5 +158,6 @@ GetFvbInfo (
   return EFI_SUCCESS;
 }
   }
+
   return EFI_NOT_FOUND;
 }
diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
 
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
index fcdc715263f2..e21113682f4f 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceCommon.c
+++ b/Silicon/Intel/IntelSil

[edk2-devel] Need help to add me to the edk-ii-reviewers team

2023-06-19 Thread Ashraf Ali S

HI All

I signed up to work as Reviewer for InteFsp2Pkg and IntelFsp2WrapperPkg
Maintainer file has been already updated : 
https://github.com/tianocore/edk2/blob/master/Maintainers.txt
Need help to add me to the edk-ii-reviewers team.

Ashraf Ali S ashraf.al...@intel.com<mailto:ashraf.al...@intel.com> [AshrafAliS]

Reviewer: https://github.com/orgs/tianocore/teams/edk-ii-reviewers

Thanks.,
S, Ashraf Ali


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Re: [edk2-devel] [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC file

2023-06-13 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

-Original Message-
From: Chang, Hunter  
Sent: Tuesday, June 13, 2023 6:10 PM
To: devel@edk2.groups.io
Cc: Chang, Hunter ; Ni, Ray ; 
Chaganty, Rangasai V ; Oram, Isaac W 
; S, Ashraf Ali ; Chen, Tina 
; Chen, Arthur G 
Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC 
file

From: Hunter Chang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371

Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec gEndOfSiInitPpiGuid 
indicates the end of all of the silicon init.
Add it to IntellSiliconPkg for AFP improvement.

Signed-off-by: Hunter Chang 

Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
Cc: Tina Chen 
Cc: Arthur Chen 
---
 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec 
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index ec8690a8d6..c540ef40ad 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -113,6 +113,7 @@
   gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 
0xaf, 0x2b, 0x25, 0x68, 0x4a } }   gEdkiiVTdNullRootEntryTableGuid = { 
0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } 
}   gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, 
0x10, 0x38, 0xF3, 0x68, 0xF2 }}+  gEndOfSiInitPpiGuid  = { 0xE2E3D5D1, 0x8356, 
0x4F96, { 0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88 }}  [Protocols]   ## 
Protocols that provide services for the Intel(R) PCH SPI Host Controller 
Compatibility Interface-- 
2.26.2.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the Multiphase FSPS

2023-06-11 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

-Original Message-
From: Aishwarya, KurugoduMelmatamX  
Sent: Monday, June 12, 2023 10:54 AM
To: devel@edk2.groups.io
Cc: Aishwarya, KurugoduMelmatamX ; Chiu, 
Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Chen, Gang C ; Zeng, Star 
; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan 
Subject: [PATCH] IntelFsp2WrapperPkg: Get HobListPtr before calling the 
Multiphase FSPS

REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480

In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and 
FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will 
be able to get the correct FspHobListPtr value

Signed-off-by: kurugodx 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Chen Gang C 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
---
 .../FspsWrapperPeim/FspsWrapperPeim.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 08fe0fdb7e..1d4dd60577 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -336,6 +336,14 @@ PeiMemoryDiscoveredNotify (
 
   DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));
 
+  //
+  // Get FspHobList
+  //
+  GuidHob = GetFirstGuidHob ();  ASSERT (GuidHob != NULL);  
+ FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);  DEBUG 
+ ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
+
   if (Status == FSP_STATUS_VARIABLE_REQUEST) {
 //
 // call to Variable request handler @@ -356,13 +364,6 @@ 
PeiMemoryDiscoveredNotify (
 DEBUG ((DEBUG_ERROR, "ERROR - TestFspSiliconInitApiOutput () fail, Status 
= %r\n", Status));
   }
 
-  //
-  // Now FspHobList complete, process it
-  //
-  GuidHob = GetFirstGuidHob ();
-  ASSERT (GuidHob != NULL);
-  FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
-  DEBUG ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
   PostFspsHobProcess (FspHobListPtr);
 
   //
--
2.41.0.windows.1



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Re: [edk2-devel] [PATCH] Get HobListPtr before calling the Multiphase FSPS

2023-06-09 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

-Original Message-
From: Aishwarya, KurugoduMelmatamX  
Sent: Friday, June 9, 2023 7:10 PM
To: devel@edk2.groups.io
Cc: Aishwarya, KurugoduMelmatamX ; Chiu, 
Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Chen, Gang C ; Zeng, Star 
; Kuo, Ted ; S, Ashraf Ali 
; Mohapatra, Susovan 
Subject: [PATCH] Get HobListPtr before calling the Multiphase FSPS

REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480

In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler and 
FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so that BL will 
be able to get the correct FspHobListPtr value

Signed-off-by: kurugodx 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Chen Gang C 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
---
 .../FspsWrapperPeim/FspsWrapperPeim.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 08fe0fdb7e..1d4dd60577 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -336,6 +336,14 @@ PeiMemoryDiscoveredNotify (
 
   DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));
 
+  //
+  // Get FspHobList
+  //
+  GuidHob = GetFirstGuidHob ();  ASSERT (GuidHob != NULL);  
+ FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);  DEBUG 
+ ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
+
   if (Status == FSP_STATUS_VARIABLE_REQUEST) {
 //
 // call to Variable request handler @@ -356,13 +364,6 @@ 
PeiMemoryDiscoveredNotify (
 DEBUG ((DEBUG_ERROR, "ERROR - TestFspSiliconInitApiOutput () fail, Status 
= %r\n", Status));
   }
 
-  //
-  // Now FspHobList complete, process it
-  //
-  GuidHob = GetFirstGuidHob ();
-  ASSERT (GuidHob != NULL);
-  FspHobListPtr = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
-  DEBUG ((DEBUG_INFO, "FspHobListPtr - 0x%x\n", FspHobListPtr));
   PostFspsHobProcess (FspHobListPtr);
 
   //
--
2.41.0.windows.1



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Re: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use FFS3

2023-05-22 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Tan, Ming
Sent: Monday, May 22, 2023 11:43 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Duggapu, Chinni B 

Subject: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use 
FFS3

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4458

Original code call PeiServicesInstallFvInfoPpi() with NULL for the FvFormat 
parameter, then PeiServicesInstallFvInfoPpi() will assume it use FFS2, then 
ASSERT if FSP-S/M use FFS3.
Now set the FvFormat to the info got from FvHeader.

Cc: Chasel Chiu 
Cc: Duggapu Chinni B 
Signed-off-by: Ming Tan 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 2 +-  
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index ea206a7960..ba0c742fea 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -217,7 +217,7 @@ FspmWrapperInit (
 ASSERT_EFI_ERROR (Status);  PeiServicesInstallFvInfoPpi (-  NULL,+ 
 &((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspmBaseAddress))->FileSystemGuid,   (VOID *)(UINTN)PcdGet32 
(PcdFspmBaseAddress),   (UINT32)((EFI_FIRMWARE_VOLUME_HEADER 
*)(UINTN)PcdGet32 (PcdFspmBaseAddress))->FvLength,   NULL,diff --git 
a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 091ddb697a..08fe0fdb7e 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -438,7 +438,7 @@ FspsWrapperInitDispatchMode (
   // FSP-S Wrapper running in Dispatch mode and reports FSP-S FV to PEI 
dispatcher.   //   PeiServicesInstallFvInfoPpi (-NULL,+
&((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspsBaseAddress))->FileSystemGuid, (VOID *)(UINTN)PcdGet32 
(PcdFspsBaseAddress), (UINT32)((EFI_FIRMWARE_VOLUME_HEADER 
*)(UINTN)PcdGet32 (PcdFspsBaseAddress))->FvLength, NULL,-- 
2.31.1.windows.1



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Re: [edk2-devel] [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg.

2023-04-24 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

From: Chiu, Chasel 
Sent: Monday, April 24, 2023 11:50:35 PM
To: devel@edk2.groups.io 
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Duggapu, Chinni B 
; Ng, Ray Han Lim ; Chen, 
Gang C ; Zeng, Star ; Kuo, Ted 
; S, Ashraf Ali ; Mohapatra, Susovan 

Subject: [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and 
IntelFsp2WrapperPkg.

Add more maintainers and reviewers for these 2 packages.

Cc: Nate DeSimone 
Cc: Duggapu Chinni B 
Cc: Ray Han Lim Ng 
Cc: Chen Gang C 
Cc: Star Zeng 
Cc: Ted Kuo 
Cc: Ashraf Ali S 
Cc: Susovan Mohapatra 
Signed-off-by: Chasel Chiu 
---
 Maintainers.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 455afdbc69..09d04af27a 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -237,14 +237,24 @@ F: IntelFsp2Pkg/
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg

 M: Chasel Chiu  [ChaselChiu]

 M: Nate DeSimone  [nate-desimone]

+M: Duggapu Chinni B  [cbduggap]

+M: Ray Han Lim Ng  [rayhanlimng]

 R: Star Zeng  [lzeng14]

+R: Ted Kuo  [tedkuo1]

+R: Ashraf Ali S  [AshrafAliS]

+R: Susovan Mohapatra  [susovanmohapatra]



 IntelFsp2WrapperPkg

 F: IntelFsp2WrapperPkg/

 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg

 M: Chasel Chiu  [ChaselChiu]

 M: Nate DeSimone  [nate-desimone]

+M: Duggapu Chinni B  [cbduggap]

+M: Chen Gang C  [chengangc]

 R: Star Zeng  [lzeng14]

+R: Ted Kuo  [tedkuo1]

+R: Ashraf Ali S  [AshrafAliS]

+R: Susovan Mohapatra  [susovanmohapatra]



 MdeModulePkg

 F: MdeModulePkg/

--
2.35.0.windows.1



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Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

2023-03-19 Thread Ashraf Ali S

Yes, you are right. Tested on the H/W, It clears the upper 32bits. 

From: devel@edk2.groups.io  On Behalf Of Marvin Häuser
Sent: Sunday, March 19, 2023 3:07 PM
To: S, Ashraf Ali 
Cc: devel@edk2.groups.io; Chiu, Chasel ; Desimone, 
Nathaniel L ; Zeng, Star 
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

Yes - it does. Most (if not all?) operations on 32-bit registers zero-extend 
the corresponding 64-bit register. This is an AMD64 / Intel 64 design to combat 
partial register stall. Please consult the SDM (or at least try it out).

What I didn’t realize is that “mov eax, eax” apparently defeats register 
renaming optimisations: https://stackoverflow.com/a/45660140

Best regards,
Marvin

On 19. Mar 2023, at 10:07, S, Ashraf Ali 
mailto:ashraf.al...@intel.com>> wrote:

Hi.,

Nope, it will not clear the upper 32bit right.

From: Marvin Häuser mailto:mhaeu...@posteo.de>>
Sent: Sunday, March 19, 2023 3:38 AM
To: S, Ashraf Ali mailto:ashraf.al...@intel.com>>; 
devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

Hi Ashraf,

”mov eax, eax” does clear the high 32 Bits of rax.

Best regards,
Marvin

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Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

2023-03-19 Thread Ashraf Ali S

Hi.,

Nope, it will not clear the upper 32bit right.

From: Marvin Häuser 
Sent: Sunday, March 19, 2023 3:38 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

Hi Ashraf,

”mov eax, eax” does clear the high 32 Bits of rax.

Best regards,
Marvin

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Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

2023-03-18 Thread Ashraf Ali S

Hi., Chasel

RAX holds the FsptImageBaseAddress, the AND operation is performed to clear the 
upper 32bits of RAX registers.
Don't we have to clear the upper 32bit of RAX registers?

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Chiu, Chasel
Sent: Friday, March 17, 2023 10:51 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Zeng, Star 
Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377

Fix below warnings generated by NASM X64 build:
/X64/FspHelper.iii:26: warning: signed dword value exceeds bounds
/X64/FspHelper.iii:35: warning: signed dword value exceeds bounds
/X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 4 ++--
 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index cdebe90fab..56d6abaea6 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -317,7 +317,7 @@ Done:
xor   eax, eaxcmp   edx, 0jnz   Exit2-   mov   eax, 
0800Eh+   mov   rax, 0800Eh  Exit2:jmp   rbp@@ 
-464,7 +464,7 @@ ParamValid:
   ; Sec Platform Init   ;   CALL_YMM  ASM_PFX(SecPlatformInit)-  cmp   
eax, 0+  cmp   rax, 0   jnz   TempRamInitExit; Load microcodediff 
--git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm 
b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
index 71624a3aad..ec9140b73c 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
@@ -23,7 +23,7 @@ ASM_PFX(AsmGetFspInfoHeader):
 global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff):
DD0x12345678   ; This value must be patched by the build 
script-   and   rax, 0x+   mov   eax, eax ; equal to 
and rax, 0xret  global ASM_PFX(AsmGetFspInfoHeaderNoStack)@@ -32,5 
+32,5 @@ ASM_PFX(AsmGetFspInfoHeaderNoStack):
lea   rcx, [ASM_PFX(FspInfoHeaderRelativeOff)]mov   ecx, [rcx]sub   
rax, rcx-   and   rax, 0x+   mov   eax, eax ; equal to 
and rax, 0xjmp   rdi-- 
2.35.0.windows.1



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[edk2-devel] [PATCH] [IntelFsp2Pkg]: Fix GCC Compiler warning

2023-03-09 Thread Ashraf Ali S

Function defination should match with declaration.
[-Wlto-type-mismatch]

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Sai Chaganty 
Cc: Star Zeng 

Signed-off-by: Ashraf Ali S 
---
 IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c 
b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
index 795bb28c0f..a5a51c804c 100644
--- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
+++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
@@ -296,6 +296,7 @@ FspTempRamExitDone2 (
 
 **/
 VOID
+EFIAPI
 FspWaitForNotify (
   VOID
   )
-- 
2.38.1.windows.1



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Re: [edk2-devel] [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.

2023-02-07 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

-Original Message-
From: Chiu, Chasel  
Sent: Tuesday, February 7, 2023 12:20 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; S, Ashraf Ali 
; Oram, Isaac W ; Chaganty, 
Rangasai V ; Ni, Ray ; 
Kubacki, Michael 
Subject: [edk2-platforms: PATCH v2] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite 
VariableStore header.

When invalid VariableStore FV header detected, current SpiFvbService will erase 
both FV and VariableStore headers from flash, however, it will only rewrite FV 
header back and cause invalid VariableStore header.

This patch adding the support for rewriting both FV header and VariableStore 
header when VariableStore corruption happened.

Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which 
VariableStoreType should be rewritten.

Cc: Ashraf Ali S 
Cc: Isaac Oram 
Cc: Rangasai V Chaganty 
Cc: Ray Ni 
Cc: Michael Kubacki 
Signed-off-by: Chasel Chiu 
---
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 174 
++
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf 
|   4 
 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec  
|   8 
 3 files changed, 134 insertions(+), 52 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..6af2dfac10 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
+++ rviceMm.c
@@ -12,6 +12,7 @@
 #include  #include 
 #include 
+#include   /**   The 
function installs EFI_FIRMWARE_VOLUME_BLOCK protocol@@ -25,12 +26,12 @@
 **/ VOID InstallFvbProtocol (-  IN  EFI_FVB_INSTANCE   
*FvbInstance+  IN  EFI_FVB_INSTANCE  *FvbInstance   ) {-  
EFI_FIRMWARE_VOLUME_HEADER*FvHeader;-  EFI_STATUS   
 Status;-  EFI_HANDLEFvbHandle;+  
EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;+  EFI_STATUS  Status;+  
EFI_HANDLE  FvbHandle;ASSERT (FvbInstance != NULL);   if 
(FvbInstance == NULL) {@@ -52,19 +53,21 @@ InstallFvbProtocol (
 // // FV does not contains extension header, then produce 
MEMMAP_DEVICE_PATH //-FvbInstance->DevicePath = 
(EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof 
(FV_MEMMAP_DEVICE_PATH), );+
FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)AllocateRuntimeCopyPool 
(sizeof (FV_MEMMAP_DEVICE_PATH), ); if 
(FvbInstance->DevicePath == NULL) {   DEBUG ((DEBUG_INFO, 
"SpiFvbServiceSmm.c: Memory allocation for MEMMAP_DEVICE_PATH failed\n"));  
 return; }-((FV_MEMMAP_DEVICE_PATH *) 
FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;- 
   ((FV_MEMMAP_DEVICE_PATH *) 
FvbInstance->DevicePath)->MemMapDevPath.EndingAddress   = FvbInstance->FvBase + 
FvHeader->FvLength - 1;++((FV_MEMMAP_DEVICE_PATH 
*)FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = 
FvbInstance->FvBase;+((FV_MEMMAP_DEVICE_PATH 
*)FvbInstance->DevicePath)->MemMapDevPath.EndingAddress   = FvbInstance->FvBase 
+ FvHeader->FvLength - 1;   } else {-FvbInstance->DevicePath = 
(EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof 
(FV_PIWG_DEVICE_PATH), );+FvbInstance->DevicePath 
= (EFI_DEVICE_PATH_PROTOCOL *)AllocateRuntimeCopyPool (sizeof 
(FV_PIWG_DEVICE_PATH), ); if 
(FvbInstance->DevicePath == NULL) {   DEBUG ((DEBUG_INFO, 
"SpiFvbServiceSmm.c: Memory allocation for FV_PIWG_DEVICE_PATH failed\n")); 
  return; }+ CopyGuid (   &((FV_PIWG_DEVICE_PATH 
*)FvbInstance->DevicePath)->FvDevPath.FvName,   (GUID 
*)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset)@@ -103,17 +106,21 @@ 
FvbInitialize (
   VOID   ) {-  EFI_FVB_INSTANCE  *FvbInstance;-  
EFI_FIRMWARE_VOLUME_HEADER*FvHeader;-  EFI_FV_BLOCK_MAP_ENTRY   
 *PtrBlockMapEntry;-  EFI_PHYSICAL_ADDRESS  
BaseAddress;-  EFI_STATUSStatus;-  UINTN
 BufferSize;-  UINTN Idx;-  
UINT32MaxLbaSize;-  UINT32  
  BytesWritten;-  UINTN BytesErased;-  
UINT64NvStorageFvSize;+  EFI_FVB_INSTANCE   
 *FvbInstance;+  EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;+  
EFI_FV_BLOCK_MAP_ENTRY  *PtrBlockMapEntry;+  EFI_PHYSICAL_ADDRESS
BaseAddress;+  EFI_STATUS

Re: [edk2-devel] [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite VariableStore header.

2023-02-04 Thread Ashraf Ali S

Hi., Chasel

If the NvStoreBuffer AllocateZeroPool failed then Status variable needs to 
updated.
Can we have some meaning full debug message rather than just printing the GUID 
name.
ExpectedBytesWritten will be uninitialed when NvStoreBuffer allocation fails. 
Due to which comparison of BytesWritten and ExpectedBytesWritten will be 
incorrect.


-Original Message-
From: Chiu, Chasel  
Sent: Saturday, February 4, 2023 3:25 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; S, Ashraf Ali 
; Oram, Isaac W ; Chaganty, 
Rangasai V ; Ni, Ray ; 
Kubacki, Michael 
Subject: [edk2-platforms: PATCH] IntelSiliconPkg/SpiFvbServiceSmm: Rewrite 
VariableStore header.

When invalid VariableStore FV header detected, current SpiFvbService will erase 
both FV and VariableStore headers from flash, however, it will only rewrite FV 
header back and cause invalid VariableStore header.

This patch adding the support for rewriting both FV header and VariableStore 
header when VariableStore corruption happened.

Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which 
VariableStoreType should be rewritten.

Cc: Ashraf Ali S 
Cc: Isaac Oram 
Cc: Rangasai V Chaganty 
Cc: Ray Ni 
Cc: Michael Kubacki 
Signed-off-by: Chasel Chiu 
---
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
| 172 

 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf 
|   4 
 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec  
|   8 
 3 files changed, 132 insertions(+), 52 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
index 6b4bcdcfe3..f29540c62c 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceMm.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSe
+++ rviceMm.c
@@ -12,6 +12,7 @@
 #include  #include 
 #include 
+#include   /**   The 
function installs EFI_FIRMWARE_VOLUME_BLOCK protocol@@ -25,12 +26,12 @@
 **/ VOID InstallFvbProtocol (-  IN  EFI_FVB_INSTANCE   
*FvbInstance+  IN  EFI_FVB_INSTANCE  *FvbInstance   ) {-  
EFI_FIRMWARE_VOLUME_HEADER*FvHeader;-  EFI_STATUS   
 Status;-  EFI_HANDLEFvbHandle;+  
EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;+  EFI_STATUS  Status;+  
EFI_HANDLE  FvbHandle;ASSERT (FvbInstance != NULL);   if 
(FvbInstance == NULL) {@@ -52,19 +53,21 @@ InstallFvbProtocol (
 // // FV does not contains extension header, then produce 
MEMMAP_DEVICE_PATH //-FvbInstance->DevicePath = 
(EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof 
(FV_MEMMAP_DEVICE_PATH), );+
FvbInstance->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)AllocateRuntimeCopyPool 
(sizeof (FV_MEMMAP_DEVICE_PATH), ); if 
(FvbInstance->DevicePath == NULL) {   DEBUG ((DEBUG_INFO, 
"SpiFvbServiceSmm.c: Memory allocation for MEMMAP_DEVICE_PATH failed\n"));  
 return; }-((FV_MEMMAP_DEVICE_PATH *) 
FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = FvbInstance->FvBase;- 
   ((FV_MEMMAP_DEVICE_PATH *) 
FvbInstance->DevicePath)->MemMapDevPath.EndingAddress   = FvbInstance->FvBase + 
FvHeader->FvLength - 1;++((FV_MEMMAP_DEVICE_PATH 
*)FvbInstance->DevicePath)->MemMapDevPath.StartingAddress = 
FvbInstance->FvBase;+((FV_MEMMAP_DEVICE_PATH 
*)FvbInstance->DevicePath)->MemMapDevPath.EndingAddress   = FvbInstance->FvBase 
+ FvHeader->FvLength - 1;   } else {-FvbInstance->DevicePath = 
(EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof 
(FV_PIWG_DEVICE_PATH), );+FvbInstance->DevicePath 
= (EFI_DEVICE_PATH_PROTOCOL *)AllocateRuntimeCopyPool (sizeof 
(FV_PIWG_DEVICE_PATH), ); if 
(FvbInstance->DevicePath == NULL) {   DEBUG ((DEBUG_INFO, 
"SpiFvbServiceSmm.c: Memory allocation for FV_PIWG_DEVICE_PATH failed\n")); 
  return; }+ CopyGuid (   &((FV_PIWG_DEVICE_PATH 
*)FvbInstance->DevicePath)->FvDevPath.FvName,   (GUID 
*)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset)@@ -103,17 +106,21 @@ 
FvbInitialize (
   VOID   ) {-  EFI_FVB_INSTANCE  *FvbInstance;-  
EFI_FIRMWARE_VOLUME_HEADER*FvHeader;-  EFI_FV_BLOCK_MAP_ENTRY   
 *PtrBlockMapEntry;-  EFI_PHYSICAL_ADDRESS  
BaseAddress;-  EFI_STATUSStatus;-  UINTN
 BufferSize;-  UINTN Idx;-  
UINT32MaxLbaSize;-  UINT32  
  BytesWritten;-  UINTN

Re: [edk2-devel] [PATCH v1] IntelSiliconPkg: Add FVI_SMBIOS_TYPE definition in FirmwareVersionInfo.h

2023-01-04 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

-Original Message-
From: Chang, Hunter  
Sent: Wednesday, January 4, 2023 1:17 PM
To: devel@edk2.groups.io
Cc: Chang, Hunter ; Ni, Ray ; 
Chaganty, Rangasai V ; Oram, Isaac W 
; S, Ashraf Ali 
Subject: [PATCH v1] IntelSiliconPkg: Add FVI_SMBIOS_TYPE definition in 
FirmwareVersionInfo.h

From: Hunter Chang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4242

Define a macro for SmbiosFeaturePkg usage which named INTEL_FVI_SMBIOS_TYPE and 
initialized to 0xDD in IndustryStandard/FirmwareVersionInfo.h

Signed-off-by: Hunter Chang 

Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
---
 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h | 
1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h 
b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h
index b30bc3f9e7..466cb8e7d2 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVer
+++ sionInfo.h
@@ -18,6 +18,7 @@
 #include   #define 
INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME"Firmware Version Info"+#define 
INTEL_FVI_SMBIOS_TYPE 0xDD  #pragma pack(1) -- 
2.26.2.windows.1



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[edk2-devel] [PATCH v2] FIX MinPlatformPkg PCIE Base typecasting error.

2022-12-25 Thread Ashraf Ali S

PCIE Base Address is 64bit PCD and the Mem Limit UINT64.
so typecasting to 32bit is not needed.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Isaac Oram 
Cc: Liming Gao 
Cc: Eric Dong 
---
 .../Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
 
b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
index 0e3fee28b5..e38975eee5 100644
--- 
a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
+++ 
b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
@@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges (
   if (PcdGet32(PcdPciReservedMemLimit) != 0) {
 mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit);
   } else {
-mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 
(PcdPciExpressBaseAddress) - 1;
+mRootBridgeTemplate.Mem.Limit = PcdGet64 (PcdPciExpressBaseAddress) - 1;
   }
 
   mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 
(PcdPciReservedMemAbove4GBBase);
-- 
2.33.0.windows.1



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Re: [edk2-devel] [Patch] IntelSiliconPkg/IntelVTdDmarPei: Fix CLANG detected incorrect return

2022-11-16 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Kinney, Michael D  
Sent: Wednesday, November 16, 2022 1:54 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V 
; Oram, Isaac W ; S, 
Ashraf Ali 
Subject: [Patch] IntelSiliconPkg/IntelVTdDmarPei: Fix CLANG detected incorrect 
return

CreateSecondLevelPagingEntryTable() has a return type of 
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to address CLANG compiler 
detection of incorrect return type.

Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
Signed-off-by: Michael D Kinney 
---
 .../Feature/VTd/IntelVTdDmarPei/TranslationTable.c  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
index a806c4c000..bb121a608e 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat
+++ ionTable.c
@@ -109,7 +109,7 @@ CreateSecondLevelPagingEntryTable (
   BOOLEAN   Is5LevelPaging;
 
   if (MemoryLimit == 0) {
-return EFI_SUCCESS;
+return NULL;
   }
 
   Lvl4PagesStart = 0;
--
2.37.1.windows.1



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Re: [edk2-devel] [Patch edk2-platforms] IntelSiliconPkg/IntelVTdDxe: Fix CLANG detected incorrect return

2022-11-10 Thread Ashraf Ali S

Reviewed-by: S, Ashraf Ali 


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Kinney, Michael D  
Sent: Thursday, November 10, 2022 11:54 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V 
; Oram, Isaac W ; S, 
Ashraf Ali 
Subject: [Patch edk2-platforms] IntelSiliconPkg/IntelVTdDxe: Fix CLANG detected 
incorrect return

CreateSecondLevelPagingEntryTable() has a return type of 
VTD_SECOND_LEVEL_PAGING_ENTRY * and an error condition returns a value of NULL.

Change return value of EFI_SUCCESS (value 0) to NULL to address CLANG compiler 
detection of incorrect return type.

Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
Signed-off-by: Michael D Kinney 
---
 .../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index 3220789080..6788c86531 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT
+++ able.c
@@ -196,7 +196,7 @@ CreateSecondLevelPagingEntryTable (
   UINT64 EndAddress;
 
   if (MemoryLimit == 0) {
-return EFI_SUCCESS;
+return NULL;
   }
 
   Lvl4PagesStart = 0;
--
2.37.1.windows.1



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Re: [edk2-devel][PATCH v1] IntelFsp2Pkg: Adding FspHelperLib

2022-11-07 Thread Ashraf Ali S

Hi.,

Instead of Hardcoded FSP ImageBase as 0x1C in FspHelper.nasm, can we have 
struct from there we can get it. So that in future if the Header is changing 
assembly code will not get impacted.

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Kuo, Ted  
Sent: Monday, November 7, 2022 2:14 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Zeng, Star ; S, Ashraf 
Ali ; Duggapu, Chinni B ; 
Chan, Amy 
Subject: [edk2-devel][PATCH v1] IntelFsp2Pkg: Adding FspHelperLib

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4128
Adding FspHelperLib for platform code to consume. There will be another patch 
raised later for FspSecCore to consume FspHelperLib.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Ashraf Ali S 
Cc: Chinni B Duggapu 
Cc: Amy Chan 
Signed-off-by: Ted Kuo 
---
 IntelFsp2Pkg/FspSecCore/SecFsp.h  | 25 +-
 IntelFsp2Pkg/Include/Library/FspHelperLib.h   | 35 +
 IntelFsp2Pkg/IntelFsp2Pkg.dsc |  2 +
 .../BaseFspHelperLib/BaseFspHelperLib.inf | 50 +++
 .../BaseFspHelperLib/Ia32/FspHelper.nasm  | 35 +
 .../BaseFspHelperLib/X64/FspHelper.nasm   | 34 +
 6 files changed, 157 insertions(+), 24 deletions(-)  create mode 100644 
IntelFsp2Pkg/Include/Library/FspHelperLib.h
 create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
 create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.nasm
 create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index d7a5976c12..f12769890f 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -17,6 +17,7 @@
 #include  #include  #include 
+#include   #define 
FSP_MCUD_SIGNATURE  SIGNATURE_32 ('M', 'C', 'U', 'D') #define 
FSP_PER0_SIGNATURE  SIGNATURE_32 ('P', 'E', 'R', '0')@@ -64,28 +65,4 @@ 
FspDataPointerFixUp (
   IN UINTN  OffsetGap   ); -/**-  This interface returns the base address of 
FSP binary.--  @return   FSP binary base 
address.--**/-UINTN-EFIAPI-AsmGetFspBaseAddress (-  VOID-  );--/**-  This 
interface gets FspInfoHeader pointer--  @return   FSP binary base 
address.--**/-UINTN-EFIAPI-AsmGetFspInfoHeader (-  VOID-  );- #endifdiff --git 
a/IntelFsp2Pkg/Include/Library/FspHelperLib.h 
b/IntelFsp2Pkg/Include/Library/FspHelperLib.h
new file mode 100644
index 00..84b74fa7aa
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Library/FspHelperLib.h
@@ -0,0 +1,35 @@
+/** @file+  Header file for FSP Helper Library.++  Copyright (c) 2022, Intel 
Corporation. All rights reserved.+  SPDX-License-Identifier: 
BSD-2-Clause-Patent++**/++#ifndef _FSP_HELPER_LIB_H_+#define 
_FSP_HELPER_LIB_H_++/**+  This interface returns the base address of FSP 
binary.++  @return   FSP binary base 
address.++**/+UINTN+EFIAPI+AsmGetFspBaseAddress (+  VOID+  );++/**+  This 
interface gets FspInfoHeader pointer++  @return   FSP info 
header.+**/+UINTN+EFIAPI+AsmGetFspInfoHeader (+  VOID+  );++#endif // 
_FSP_HELPER_LIB_H_diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc 
b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
index 0713f0028d..09893d70e8 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
@@ -46,6 +46,7 @@
   
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
   
FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
   
FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf+
  FspHelperLib|IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf  
[LibraryClasses.common.PEIM]   
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf@@ -66,6 +67,7 @@
   IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf   
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf   
IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf+  
IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   
IntelFsp2Pkg/FspSecCore/FspSecCoreM.infdiff --git 
a/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf 
b/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
new file mode 100644
index 00..318ad65330
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
@@ -0,0 +1,50 @@
+## @file+#  FSP Helper Library.+#+#  Copyright (c) 2022, Intel Corporation. 
All rights reserved.+#+#  SPDX-License-Identifier: 
BSD-2-Clause-Patent+#+##+++#+#
 Defines Section - statements that will be processed to create a 
Makefile.+#+++[Defines]+
  INF_VERSION= 0x00010005+  BASE_NAME  
= FspHelperLib+  FILE_GUID  = 
65746991

Re: [edk2-devel] [edk2-platforms][PATCH v1 1/1] IntelSiliconPkg/SpiFvbService: Read FV header length from header

2022-10-10 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Michael Kubacki
Sent: Wednesday, October 5, 2022 8:53 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali ; Oram, Isaac W 
; Chaganty, Rangasai V ; 
Ni, Ray 
Subject: [edk2-devel] [edk2-platforms][PATCH v1 1/1] 
IntelSiliconPkg/SpiFvbService: Read FV header length from header

From: Michael Kubacki 

Bug Fix: Read the FV header length from the Firmware Volume Block
(FVB) information structure as opposed to EFI_FIRMWARE_VOLUME_HEADER to account 
for a variable number of block map entries.

Cc: Ashraf Ali S 
Cc: Isaac Oram 
Cc: Rangasai V Chaganty 
Cc: Ray Ni 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
index 634a44218c7a..ab1cb2ef1622 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.
+++ c
@@ -115,7 +115,7 @@ GetFvbInfo (
 Status = mFvbMediaInfoGenerators[Index]();
 ASSERT_EFI_ERROR (Status);
 if (!EFI_ERROR (Status) && (FvbMediaInfo.BaseAddress == FvBaseAddress)) {
-  FvHeader = AllocateCopyPool (sizeof (EFI_FIRMWARE_VOLUME_HEADER), 
);
+  FvHeader = AllocateCopyPool (FvbMediaInfo.FvbInfo.HeaderLength, 
+ );
 
   //
   // Update the checksum value of FV header.
--
2.28.0.windows.1



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[edk2-devel] [PATCH] FIX MinPlatformPkg PCIE Base Addess avoid thunking operation.

2022-09-18 Thread Ashraf Ali S

thunking the PCIE base address will cause the distruption in the
execution flow when the PCIE base address is 64bit bit.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Isaac Oram 
Cc: Liming Gao 
Cc: Eric Dong 
---
 .../Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
 
b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
index 0e3fee28b5..e38975eee5 100644
--- 
a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
+++ 
b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
@@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges (
   if (PcdGet32(PcdPciReservedMemLimit) != 0) {
 mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit);
   } else {
-mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 
(PcdPciExpressBaseAddress) - 1;
+mRootBridgeTemplate.Mem.Limit = PcdGet64 (PcdPciExpressBaseAddress) - 1;
   }
 
   mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 
(PcdPciReservedMemAbove4GBBase);
-- 
2.30.2.windows.1



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Re: [edk2-devel] [PATCH] IntelSiliconPkg: Fix DEBUG macros having incorrect number of arguments

2022-08-23 Thread Ashraf Ali S

Reviewed-by: Ashraf Ali S 


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Singh, DeepakX  
Sent: Tuesday, August 23, 2022 3:42 PM
To: devel@edk2.groups.io
Cc: Singh, DeepakX ; Ni, Ray ; 
Chaganty, Rangasai V ; Oram, Isaac W 
; S, Ashraf Ali ; Pir, Ovais F 

Subject: [PATCH] IntelSiliconPkg: Fix DEBUG macros having incorrect number of 
arguments

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4027

Signed-off-by: Deepak Singh 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
Cc: Ashraf Ali S 
Cc: Ovais F Pir 
---
 .../IntelPciDeviceSecurityDxe/IntelPciDeviceSecurityDxe.c   | 2 +-
 .../Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c  | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/PcieSecurity/IntelPciDeviceSecurityDxe/IntelPciDeviceSecurityDxe.c
 
b/Silicon/Intel/IntelSiliconPkg/Feature/PcieSecurity/IntelPciDeviceSecurityDxe/IntelPciDeviceSecurityDxe.c
index aa2bf14fa8..7a70dc7aea 100644
--- 
a/Silicon/Intel/IntelSiliconPkg/Feature/PcieSecurity/IntelPciDeviceSecurityDxe/IntelPciDeviceSecurityDxe.c
+++ 
b/Silicon/Intel/IntelSiliconPkg/Feature/PcieSecurity/IntelPciDeviceSecurityDxe/IntelPciDeviceSecurityDxe.c
@@ -488,7 +488,7 @@ DoMeasurementsFromDigestRegister (
   DEBUG((DEBUG_INFO, "\n"));
 }
 
-DEBUG((DEBUG_INFO, "ExtendDigestRegister...\n", ExtendDigestRegister));
+DEBUG((DEBUG_INFO, "ExtendDigestRegister...\n"));
 ExtendDigestRegister (PciIo, DeviceSecurityPolicy, TcgAlgId, DigestSel, 
Digest, DeviceSecurityState);
   }
 }
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index c7a56cf571..ef1737b1b6 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -642,7 +642,7 @@ DumpVtdVerRegs (
   IN VTD_VER_REG*VerReg
   )
 {
-  DEBUG ((DEBUG_INFO, "  VerReg:\n", VerReg->Uint32));
+  DEBUG ((DEBUG_INFO, "   VerReg - 0x%x\n", VerReg->Uint32));
   DEBUG ((DEBUG_INFO, "Major - 0x%x\n", VerReg->Bits.Major));
   DEBUG ((DEBUG_INFO, "Minor - 0x%x\n", VerReg->Bits.Minor));
 }
@@ -657,7 +657,7 @@ DumpVtdCapRegs (
   IN VTD_CAP_REG *CapReg
   )
 {
-  DEBUG((DEBUG_INFO, "  CapReg:\n", CapReg->Uint64));
+  DEBUG((DEBUG_INFO, "  CapReg   - 0x%x\n", CapReg->Uint64));
   DEBUG((DEBUG_INFO, "ND - 0x%x\n", CapReg->Bits.ND));
   DEBUG((DEBUG_INFO, "AFL- 0x%x\n", CapReg->Bits.AFL));
   DEBUG((DEBUG_INFO, "RWBF   - 0x%x\n", CapReg->Bits.RWBF));
@@ -688,7 +688,7 @@ DumpVtdECapRegs (
   IN VTD_ECAP_REG *ECapReg
   )
 {
-  DEBUG((DEBUG_INFO, "  ECapReg:\n", ECapReg->Uint64));
+  DEBUG((DEBUG_INFO, "  ECapReg  - 0x%x\n", ECapReg->Uint64));
   DEBUG((DEBUG_INFO, "C  - 0x%x\n", ECapReg->Bits.C));
   DEBUG((DEBUG_INFO, "QI - 0x%x\n", ECapReg->Bits.QI));
   DEBUG((DEBUG_INFO, "DT - 0x%x\n", ECapReg->Bits.DT));
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH V2] Maintainers.txt: Update reviewers for IntelSiliconPkg

2022-08-23 Thread Ashraf Ali S

Add Ashraf Ali S as IntelSiliconPkg reviewers

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
---
 Maintainers.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 5e403ce851..3fe5dc21a8 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -277,6 +277,7 @@ F: Silicon/Intel/IntelSiliconPkg/
 M: Ray Ni 
 M: Rangasai V Chaganty 
 M: Isaac Oram 
+R: Ashraf Ali S 
 
 Silicon/Intel/QuarkSocPkg
 F: Silicon/Intel/QuarkSocPkg/
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] Maintainers.txt: Update reviewers for IntelSiliconPkg

2022-08-23 Thread Ashraf Ali S

Add Ashraf Ali S as IntelSiliconPkg reviewers

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Isaac Oram 
---
 Maintainers.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 5e403ce851..e2ca67a0f2 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -277,6 +277,7 @@ F: Silicon/Intel/IntelSiliconPkg/
 M: Ray Ni 
 M: Rangasai V Chaganty 
 M: Isaac Oram 
+M: Ashraf Ali S 
 
 Silicon/Intel/QuarkSocPkg
 F: Silicon/Intel/QuarkSocPkg/
-- 
2.30.2.windows.1



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Re: [edk2-devel] [PATCH v2 1/2] UefiPayloadPkg: Implement a new SerialPortLib instance

2022-07-19 Thread Ashraf Ali S

Hi,

For the register offset doing the division operation of having a size UINTN in 
below code,

I think we should use DivU64x32 function for Division operation right, correct 
me if I'm wrong.


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of kavya
Sent: Tuesday, July 19, 2022 12:37 PM
To: devel@edk2.groups.io
Cc: Sravanthi, K KavyaX ; Dong, Guo 
; Ni, Ray ; Maurice Ma 
; You, Benjamin ; Rhodes, Sean 

Subject: [edk2-devel] [PATCH v2 1/2] UefiPayloadPkg: Implement a new 
SerialPortLib instance

Add new Serial port library instance that consumes the HOB defined in 
MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h to support multiple 
UART's.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 
Cc: Sean Rhodes 
Signed-off-by: Kavya 
---
 UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c   | 794 
++
 UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.inf |  40 

 2 files changed, 834 insertions(+)

diff --git a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c 
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
new file mode 100644
index 00..8c39befafe
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
@@ -0,0 +1,794 @@
+/** @file
+  UART Serial Port library functions.
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include  #include  
+#include 
+
+//
+// 16550 UART register offsets and bitfields //
+#define R_UART_RXBUF 0// LCR_DLAB = 0
+#define R_UART_TXBUF 0// LCR_DLAB = 0
+#define R_UART_BAUD_LOW  0// LCR_DLAB = 1
+#define R_UART_BAUD_HIGH 1// LCR_DLAB = 1
+#define R_UART_IER   1// LCR_DLAB = 0
+#define R_UART_FCR   2
+#define   B_UART_FCR_FIFOE   BIT0
+#define   B_UART_FCR_FIFO64  BIT5
+#define R_UART_LCR   3
+#define   B_UART_LCR_DLABBIT7
+#define R_UART_MCR   4
+#define   B_UART_MCR_DTRCBIT0
+#define   B_UART_MCR_RTS BIT1
+#define R_UART_LSR   5
+#define   B_UART_LSR_RXRDY   BIT0
+#define   B_UART_LSR_TXRDY   BIT5
+#define   B_UART_LSR_TEMTBIT6
+#define R_UART_MSR   6
+#define   B_UART_MSR_CTS BIT4
+#define   B_UART_MSR_DSR BIT5
+#define   B_UART_MSR_RI  BIT6
+#define   B_UART_MSR_DCD BIT7
+
+typedef struct {
+  UINTNBaseAddress;
+  BOOLEAN  UseMmio;
+  UINT32   BaudRate;
+} UART_INFO;
+
+UART_INFO   **mUartInfo;
+UINT8   mUartCount;
+
+/**
+  Reads an 8-bit register. If UseMmio is TRUE, then the value is read 
+from
+  MMIO space. If UseMmio is FALSE, then the value is read from I/O 
+space. The
+  parameter Offset is added to the base address of the register.
+
+  @param  Base The base address register of UART device.
+  @param  Offset   The offset of the register to read.
+  @param  UseMmio  Check if value has to be read from MMIO space or IO space.
+
+  @return The value read from the register.
+
+**/
+UINT8
+SerialPortReadRegister (
+  UINTNBase,
+  UINTNOffset,
+  BOOLEAN  UseMmio
+  )
+{
+  if (UseMmio) {
+return MmioRead8 (Base + Offset/4);
+  } else {
+return IoRead8 (Base + Offset);
+  }
+}
+
+/**
+  Writes an 8-bit register.. If UseMmio is TRUE, then the value is 
+written to
+  MMIO space. If UseMmio is FALSE, then the value is written to I/O 
+space. The
+  parameter Offset is added to the base address of the registers.
+
+  @param  Base The base address register of UART device.
+  @param  Offset   The offset of the register to write.
+  @param  ValueValue to be written.
+  @param  UseMmio  Check if value has to be written to MMIO space or IO space.
+
+  @return The value written to the register.
+
+**/
+UINT8
+SerialPortWriteRegister (
+  UINTNBase,
+  UINTNOffset,
+  UINT8Value,
+  BOOLEAN  UseMmio
+  )
+{
+  if (UseMmio) {
+return MmioWrite8 (Base + Offset/4, Value);
+  } else {
+return

[edk2-devel] [PATCH] IntelFsp2Pkg: BaseFspDebugLibSerialPort Support for X64 Build

2022-02-13 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3833

Move FspDebug to the root of BaseFspDebugLibSerialPort since the current
nasm support for both IA32 and X64 Build, remove IA32 from INF file.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 

Signed-off-by: Ashraf Ali S 
---
 .../BaseFspDebugLibSerialPort.inf |  8 ++-
 .../{Ia32 => }/FspDebug.nasm  | 50 +--
 2 files changed, 28 insertions(+), 30 deletions(-)
 rename IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/{Ia32 => }/FspDebug.nasm 
(86%)

diff --git 
a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf 
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
index 14b1899e6c..0024edf2dc 100644
--- 
a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
+++ 
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Instance of BaseFspDebugLib
 #
-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -16,14 +16,12 @@
   LIBRARY_CLASS  = DebugLib
 
 #
-#  VALID_ARCHITECTURES   = IA32
+#  VALID_ARCHITECTURES   = IA32 X64
 #
 
 [Sources]
   DebugLib.c
-
-[Sources.Ia32]
-  Ia32/FspDebug.nasm
+  FspDebug.nasm
 
 [Packages]
   MdePkg/MdePkg.dec
diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/Ia32/FspDebug.nasm 
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/FspDebug.nasm
similarity index 86%
rename from IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/Ia32/FspDebug.nasm
rename to IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/FspDebug.nasm
index 997e375c8c..ffacaa239d 100644
--- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/Ia32/FspDebug.nasm
+++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/FspDebug.nasm
@@ -1,25 +1,25 @@
-;--
-;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Abstract:
-;
-;   FSP Debug functions
-;
-;--
-
-SECTION .text
-
-;--
-; UINT32 *
-; EFIAPI
-; GetStackFramePointer (
-;   VOID
-;   );
-;--
-global ASM_PFX(GetStackFramePointer)
-ASM_PFX(GetStackFramePointer):
-mov eax, ebp
-ret
-
+;--
+;
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+;   FSP Debug functions
+;
+;--
+
+SECTION .text
+
+;--
+; UINT32 *
+; EFIAPI
+; GetStackFramePointer (
+;   VOID
+;   );
+;--
+global ASM_PFX(GetStackFramePointer)
+ASM_PFX(GetStackFramePointer):
+mov eax, ebp
+ret
+
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: BaseFspSwitchStackLib Support for X64 Build

2022-02-13 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3832

BaseFspSwitchStackLib Currently Support for IA32 build only, adding
support for X64 build, fix typecasting issues for X64 build.
0x_ will be replaced by MAX_ADDRESS which is set based on the
type of Library which is it building.
if it's a IA32 MAX_ADDRESS = 0x_
for X64MAX_ADDRESS = 0x___ULL

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 

Signed-off-by: Ashraf Ali S 
---
 IntelFsp2Pkg/FspSecCore/SecFsp.h  |   3 +-
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|  10 +-
 .../BaseFspSwitchStackLib.inf |   7 +-
 .../BaseFspSwitchStackLib/X64/Stack.nasm  | 124 ++
 4 files changed, 136 insertions(+), 8 deletions(-)
 create mode 100644 IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index aacd32f7f7..9a6fc14d23 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -10,6 +10,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c 
b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index 7d6ef11fe7..b70d3ffcf1 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -31,7 +31,7 @@ FspApiCallingCheck (
 //
 // NotifyPhase check
 //
-if ((FspData == NULL) || ((UINT32)FspData == 0x)) {
+if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS)) {
   Status = EFI_UNSUPPORTED;
 } else {
   if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
@@ -42,7 +42,7 @@ FspApiCallingCheck (
 //
 // FspMemoryInit check
 //
-if ((UINT32)FspData != 0x) {
+if ((UINTN)FspData != MAX_ADDRESS) {
   Status = EFI_UNSUPPORTED;
 } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
   Status = EFI_INVALID_PARAMETER;
@@ -51,7 +51,7 @@ FspApiCallingCheck (
 //
 // TempRamExit check
 //
-if ((FspData == NULL) || ((UINT32)FspData == 0x)) {
+if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS)) {
   Status = EFI_UNSUPPORTED;
 } else {
   if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
@@ -62,7 +62,7 @@ FspApiCallingCheck (
 //
 // FspSiliconInit check
 //
-if ((FspData == NULL) || ((UINT32)FspData == 0x)) {
+if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS)) {
   Status = EFI_UNSUPPORTED;
 } else {
   if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
diff --git 
a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf 
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
index 3dcf3b9598..cd7d89e43a 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Instance of BaseFspSwitchStackLib
 #
-#  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -15,12 +15,15 @@
   VERSION_STRING = 1.0
   LIBRARY_CLASS  = FspSwitchStackLib
 
-[Sources.IA32]
+[Sources]
   FspSwitchStackLib.c
 
 [Sources.IA32]
   Ia32/Stack.nasm
 
+[Sources.X64]
+  X64/Stack.nasm
+
 [Packages]
   MdePkg/MdePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm 
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
new file mode 100644
index 00..f94f39fc13
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
@@ -0,0 +1,124 @@
+;--
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+;   Switch the stack from temporary memory to permanent memory.
+;
+;--
+
+SECTION .text
+
+extern ASM_PFX(SwapStack)
+
+;-
+;  Macro:PUSHA_64
+;
+;  Description:  Saves all registers on stack
+;
+;  Input:None
+;
+;  Output:

Re: [edk2-devel] [PATCH] Update Graphics Info Hob FrameBufferSize Based on UEFI Spec 2.0

2022-01-02 Thread Ashraf Ali S

Hi., Michael

The issue was coming due to assign UINTN to UINT32  (warning C4244: '=': 
conversion from 'UINTN' to 'UINT32', possible loss of data)

I will fix this in my code instead of changing in the EDK2.

Closing this bug, Thanks

Happy New Year 

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Kinney, Michael D  
Sent: Monday, January 3, 2022 1:55 AM
To: S, Ashraf Ali ; devel@edk2.groups.io; Kinney, 
Michael D 
Cc: Chaganty, Rangasai V ; Solanki, Digant H 
; V, Sangeetha ; Ni, Ray 
; Gao, Liming ; Liu, Zhiguang 

Subject: RE: [PATCH] Update Graphics Info Hob FrameBufferSize Based on UEFI 
Spec 2.0

Hi Ashraf,

HOBs must never use UINTN or pointer fields.  HOBs must always be the same size 
no matter what CPU or CPU mode the structure is compiler for.

This is also a non-backwards compatible change to a HOB structure.

For the case where the GraphicsOutputProtocol is build for X64 and uses this 
HOB as input, the UINT32 value from the HOB can be cast to UINTN for the 
protocol.

Given that the cast is from UINT32 -> UINT32 for IA32 builds and UINT32->UINT64 
for X64 builds, I do not see any case where there would be possible loss of 
data.  The cast would always be to a type that is the same size or larger.

Can you please verify the compiler error you observed?

Thanks,

Mike

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Sunday, January 2, 2022 8:34 AM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Chaganty, Rangasai V 
> ; Solanki, Digant H 
> ; V, Sangeetha ; 
> Ni, Ray ; Kinney, Michael D 
> ; Gao, Liming ; 
> Liu, Zhiguang 
> Subject: [PATCH] Update Graphics Info Hob FrameBufferSize Based on 
> UEFI Spec 2.0
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3793
> Basede on UEFI Spec 2.0 section 17.7.1 structure 
> EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE say FrameBufferSize should be size 
> of UINTN, in MdePkg\Include\Guid\GraphicsInfoHob.h
> EFI_PEI_GRAPHICS_INFO_HOB FrameBufferSize  is UINT32,
> 
> UefiPayloadPkg\GraphicsOutputDxe\GraphicsOutput.c
> MdeModulePkg\Universal\Console\GraphicsOutputDxe\GraphicsOutput.c
> 
> Private->GraphicsOutputMode.FrameBufferSize = \
> GraphicsInfo->FrameBufferSize;
> 
> UINT32 value is getting assigned to UINTN, in X64 build compiler will 
> throw possible loss of data error.
> 
> so update the EFI_PEI_GRAPHICS_INFO_HOB  based on UEFI Spec 2.0
> 
> Signed-off-by: Ashraf Ali S 
> Cc: Rangasai V Chaganty 
> Cc: Digant H Solanki 
> Cc: Sangeetha V 
> Cc: Ray Ni 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> ---
>  MdePkg/Include/Guid/GraphicsInfoHob.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/MdePkg/Include/Guid/GraphicsInfoHob.h 
> b/MdePkg/Include/Guid/GraphicsInfoHob.h
> index 237911e63a..92bd907f20 100644
> --- a/MdePkg/Include/Guid/GraphicsInfoHob.h
> +++ b/MdePkg/Include/Guid/GraphicsInfoHob.h
> @@ -26,7 +26,7 @@
> 
>  typedef struct {
>EFI_PHYSICAL_ADDRESSFrameBufferBase;
> -  UINT32  FrameBufferSize;
> +  UINTN   FrameBufferSize;
>EFI_GRAPHICS_OUTPUT_MODE_INFORMATIONGraphicsMode;
>  } EFI_PEI_GRAPHICS_INFO_HOB;
> 
> --
> 2.30.2.windows.1



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[edk2-devel] [PATCH] Update Graphics Info Hob FrameBufferSize Based on UEFI Spec 2.0

2022-01-02 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3793
Basede on UEFI Spec 2.0 section 17.7.1 structure
EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE say FrameBufferSize should be size of
UINTN, in MdePkg\Include\Guid\GraphicsInfoHob.h
EFI_PEI_GRAPHICS_INFO_HOB FrameBufferSize  is UINT32,

UefiPayloadPkg\GraphicsOutputDxe\GraphicsOutput.c
MdeModulePkg\Universal\Console\GraphicsOutputDxe\GraphicsOutput.c

Private->GraphicsOutputMode.FrameBufferSize = \
GraphicsInfo->FrameBufferSize;

UINT32 value is getting assigned to UINTN,
in X64 build compiler will throw possible loss of data error.

so update the EFI_PEI_GRAPHICS_INFO_HOB  based on UEFI Spec 2.0

Signed-off-by: Ashraf Ali S 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
---
 MdePkg/Include/Guid/GraphicsInfoHob.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MdePkg/Include/Guid/GraphicsInfoHob.h 
b/MdePkg/Include/Guid/GraphicsInfoHob.h
index 237911e63a..92bd907f20 100644
--- a/MdePkg/Include/Guid/GraphicsInfoHob.h
+++ b/MdePkg/Include/Guid/GraphicsInfoHob.h
@@ -26,7 +26,7 @@
 
 typedef struct {
   EFI_PHYSICAL_ADDRESSFrameBufferBase;
-  UINT32  FrameBufferSize;
+  UINTN   FrameBufferSize;
   EFI_GRAPHICS_OUTPUT_MODE_INFORMATIONGraphicsMode;
 } EFI_PEI_GRAPHICS_INFO_HOB;
 
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] Update FvLength to UINTN from UINT32 in FirmwareVolumeInfo

2021-12-31 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3792

Pi/PiFirmwareVolume FvLength has been assigned as UINT64, and
Ppi/FirmwareVolumeInfo FvLength has mentioned as UINT32 which will
break the X64 build, updating the FvLenth to UINTN will support for both

Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Cc: Dandan Bi  [dandanbi]
Cc: Liming Gao  [lgao4]
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Star Zeng 
Cc: Andrew Fish 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Rebecca Cran 
Cc: Peter Grehan 

Signed-off-by: Ashraf Ali S 
---
 EmulatorPkg/Library/SecPeiServicesLib/PeiServicesLib.c| 2 +-
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 2 +-
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 2 +-
 MdeModulePkg/Core/Pei/FwVol/FwVol.c   | 8 
 MdeModulePkg/Core/Pei/FwVol/FwVol.h   | 2 +-
 MdeModulePkg/Core/Pei/PeiMain.h   | 2 +-
 MdePkg/Include/Library/PeiServicesLib.h   | 4 ++--
 MdePkg/Include/Ppi/FirmwareVolumeInfo.h   | 2 +-
 MdePkg/Include/Ppi/FirmwareVolumeInfo2.h  | 2 +-
 MdePkg/Library/PeiServicesLib/PeiServicesLib.c| 6 +++---
 OvmfPkg/Bhyve/PlatformPei/Fv.c| 2 +-
 OvmfPkg/PlatformPei/Fv.c  | 2 +-
 OvmfPkg/XenPlatformPei/Fv.c   | 2 +-
 SecurityPkg/FvReportPei/FvReportPei.c | 2 +-
 .../RecoveryModuleLoadPei/RecoveryModuleLoadPei.c | 2 +-
 15 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/EmulatorPkg/Library/SecPeiServicesLib/PeiServicesLib.c 
b/EmulatorPkg/Library/SecPeiServicesLib/PeiServicesLib.c
index 9409cbdb66..4cbe02a627 100644
--- a/EmulatorPkg/Library/SecPeiServicesLib/PeiServicesLib.c
+++ b/EmulatorPkg/Library/SecPeiServicesLib/PeiServicesLib.c
@@ -545,7 +545,7 @@ EFIAPI
 PeiServicesInstallFvInfoPpi (
   IN CONST EFI_GUID  *FvFormat  OPTIONAL,
   IN CONST VOID  *FvInfo,
-  IN   UINT32FvInfoSize,
+  IN   UINTN FvInfoSize,
   IN CONST EFI_GUID  *ParentFvName  OPTIONAL,
   IN CONST EFI_GUID  *ParentFileName OPTIONAL
   )
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index b0c6b2f8a6..f5f3836635 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -195,7 +195,7 @@ FspmWrapperInit (
 PeiServicesInstallFvInfoPpi (
   NULL,
   (VOID *)(UINTN)PcdGet32 (PcdFspmBaseAddress),
-  (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspmBaseAddress))->FvLength,
+  (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspmBaseAddress))->FvLength,
   NULL,
   NULL
   );
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index fadadd40e6..25a13e78fd 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -426,7 +426,7 @@ FspsWrapperInitDispatchMode (
   PeiServicesInstallFvInfoPpi (
 NULL,
 (VOID *)(UINTN)PcdGet32 (PcdFspsBaseAddress),
-(UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspsBaseAddress))->FvLength,
+(UINTN)((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 
(PcdFspsBaseAddress))->FvLength,
 NULL,
 NULL
 );
diff --git a/MdeModulePkg/Core/Pei/FwVol/FwVol.c 
b/MdeModulePkg/Core/Pei/FwVol/FwVol.c
index 60bbe57332..28c0c5d4da 100644
--- a/MdeModulePkg/Core/Pei/FwVol/FwVol.c
+++ b/MdeModulePkg/Core/Pei/FwVol/FwVol.c
@@ -1542,7 +1542,7 @@ ProcessFvFile (
 PeiServicesInstallFvInfo2Ppi (
   >FileSystemGuid,
   (VOID **)FvHeader,
-  (UINT32)FvHeader->FvLength,
+  (UINTN)FvHeader->FvLength,
   ,
   ,
   AuthenticationStatus
@@ -1551,7 +1551,7 @@ ProcessFvFile (
 PeiServicesInstallFvInfoPpi (
   >FileSystemGuid,
   (VOID **)FvHeader,
-  (UINT32)FvHeader->FvLength,
+  (UINTN)FvHeader->FvLength,
   ,
   
   );
@@ -2293,7 +2293,7 @@ FindUnknownFormatFvInfo (
   IN  PEI_CORE_INSTANCE  *PrivateData,
   IN  EFI_GUID   *Format,
   OUT VOID   **FvInfo,
-  OUT UINT32 *FvInfoSize,
+  OUT UINTN  *FvInfoSize,
   OUT UINT32 *AuthenticationStatus
   )
 {
@@ -2350,7 +2350,7 @@ ThirdPartyFvPpiNotifyCallback (
   PEI_CORE_INSTANCE*PrivateData;
   EFI_PEI_FIRMWARE_VOLUME_PPI  *FvPpi;
   VOID *FvInfo;
-  UINT32   FvInfoSize;
+  UINTNFvInfoSize;
   UINT32   AuthenticationStatus;
   EFI_STATUS   Status;
   EFI_PEI_FV_HANDLEFvHandle;
diff --git a/MdeModulePkg/Core/Pei/FwVol/FwVol.h 
b/MdeModulePkg/Core/Pei/FwVol/FwVol.h
index

[edk2-devel] [PATCH v8] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-12-16 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to building
error. when a module built-in X64 function pointer will be the size of
64bit width which cannot be fit in 32bit address which will lead to
error. to overcome this issue introducing the 2 new PCD's for the 64bit
modules can consume it. based on the which pcd platform set, use that.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c | 25 ---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   |  3 ++-
 .../FspsWrapperPeim/FspsWrapperPeim.c | 25 ---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   |  3 ++-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 5 files changed, 50 insertions(+), 8 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 287e7f9159..49fbb27eca 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -38,6 +38,25 @@
 
 extern EFI_GUID  gFspHobGuid;
 
+/**
+  Get the FSP M UPD Data address
+
+  @return FSP-M UPD Data Address
+**/
+
+UINTN
+EFIAPI
+GetFspmUpdDataAddress (
+  VOID
+  )
+{
+  if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
+return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
+  } else {
+return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
+  }
+}
+
 /**
   Call FspMemoryInit API.
 
@@ -67,7 +86,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize != 0) 
&& (FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -79,7 +98,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..5d0e021401 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -60,6 +60,7 @@
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
 
 [Sources]
   FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index f7459a90b5..ddee9cd029 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList (
   }
 }
 
+/**
+  Get the FSP S UPD Data address
+
+  @return FSP-S UPD Data Address
+**/
+
+UINTN
+EFIAPI
+GetFspsUpdDataAddress (
+  VOID
+  )
+{
+  if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
+return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
+  } else {
+return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
+  }
+}
+
 /**
   This function is for FSP dispatch mode to perform post FSP-S process.
 
@@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify (
 return EFI_DEVICE_ERROR;
   }
 
-  if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRe

Re: [edk2-devel] [PATCH v7] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-27 Thread Ashraf Ali S

Hi., @Zeng, Star

Creating a single function is doable, but the problem with that is 
If someone set the PCD  PcdFspmUpdDataAddress64 accidentally which should be 
applicable only in X64. Since the PCD has some junk value, it will return the 
false data in IA32 case. Which will break everything with respect to FSP-S/M.

To Avoid Such cases separating the IA32 vs X64 is more feasible. And easily 
differentiating with IA32 and X64. 

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Zeng, Star  
Sent: Monday, September 27, 2021 2:15 PM
To: Chiu, Chasel ; S, Ashraf Ali 
; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Kuo, Ted 
; Duggapu, Chinni B ; Chaganty, 
Rangasai V ; Solanki, Digant H 
; V, Sangeetha ; Ni, Ray 
; Zeng, Star 
Subject: RE: [PATCH v7] IntelFsp2WrapperPkg : FSPM/S UPD data address based on 
Build Type

Curious: It does not work to have one function implementation like below?

UINTN
EFIAPI
GetFspmUpdDataAddress (
  VOID
  )
{
  if (PcdGet64 (PcdFspmUpdDataAddress) != 0) {
return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
  } else {
return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
  }
}

Thanks,
Star

-Original Message-
From: Chiu, Chasel  
Sent: Monday, September 27, 2021 9:10 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star 
; Kuo, Ted ; Duggapu, Chinni B 
; Chaganty, Rangasai V 
; Solanki, Digant H 
; V, Sangeetha ; Ni, Ray 

Subject: RE: [PATCH v7] IntelFsp2WrapperPkg : FSPM/S UPD data address based on 
Build Type


Reviewed-by: Chasel Chiu 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Friday, September 24, 2021 7:43 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Chiu, Chasel 
> ; Desimone, Nathaniel L 
> ; Zeng, Star ; 
> Kuo, Ted ; Duggapu, Chinni B 
> ; Chaganty, Rangasai V 
> ; Solanki, Digant H 
> ; V, Sangeetha ; 
> Ni, Ray 
> Subject: [PATCH v7] IntelFsp2WrapperPkg : FSPM/S UPD data address 
> based on Build Type
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
> when the module is not building in IA32 mode which will lead to building 
> error.
> when a module built-in X64 function pointer will be the size of 64bit 
> width which cannot be fit in 32bit address which will lead to error. 
> to overcome this issue introducing the 2 new PCD's for the 64bit modules can 
> consume it.
> Creating the API's to support different architecture
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> Cc: Kuo Ted 
> Cc: Duggapu Chinni B 
> Cc: Rangasai V Chaganty 
> Cc: Digant H Solanki 
> Cc: Sangeetha V 
> Cc: Ray Ni 
> Signed-off-by: Ashraf Ali S 
> ---
>  .../FspmWrapperPeim/FspmWrapperPeim.c | 19 +++---
>  .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
>  .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
>  .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
>  .../FspsWrapperPeim/FspsWrapperPeim.c | 17 +---
>  .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
>  .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
>  .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
>  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
>  9 files changed, 162 insertions(+), 10 deletions(-)  create mode 
> 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
>  create mode 100644
> IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
>  create mode 100644
> IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
>  create mode 100644 
> IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c
> 
> diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> index 24ab534620..4a15136c39 100644
> --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
> @@ -3,7 +3,7 @@
>register TemporaryRamDonePpi to call TempRamExit API, and register 
> MemoryDiscoveredPpi
>notify to call FspSiliconInit API.
> 
> -  Copyright (c) 2014 - 2020, Intel Corporation. All rights 
> reserved.
> +  Copyright (c) 2014 - 2021, Intel Corporation. All rights 
> + reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -39,6 +39,17 @@
> 
>  extern EFI_GUID gFspHobGuid;
> 
> +/**
> +  Get the Fspm Upd Data Address from the PCD
> +
> +  @return FSPM UPD Data Address
> +**/
> +UINTN
> +EFIAPI
> +GetFspmUpdDataAddress (
> +  VOID
> +  );
> +
>  /**
>Call FspMemoryInit API.
> 
> @@ -59,7 +70,7 @@ PeiFspMemoryInit (
> 
>DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
> 
> -  FspHobListPtr = NULL;
> +  FspHobListPtr  =

[edk2-devel] [PATCH v7] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-24 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c | 19 +++---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
 .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
 .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
 .../FspsWrapperPeim/FspsWrapperPeim.c | 17 +---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
 .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
 .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 9 files changed, 162 insertions(+), 10 deletions(-)
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..4a15136c39 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -39,6 +39,17 @@
 
 extern EFI_GUID gFspHobGuid;
 
+/**
+  Get the Fspm Upd Data Address from the PCD
+
+  @return FSPM UPD Data Address
+**/
+UINTN
+EFIAPI
+GetFspmUpdDataAddress (
+  VOID
+  );
+
 /**
   Call FspMemoryInit API.
 
@@ -59,7 +70,7 @@ PeiFspMemoryInit (
 
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
-  FspHobListPtr = NULL;
+  FspHobListPtr  = NULL;
   FspmUpdDataPtr = NULL;
 
   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
@@ -68,7 +79,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +91,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..5b4ad531e7 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -45,6 +45,7 @@
   FspWrapperApiLib
   FspWrapperApiTestLib
   FspMeasurementLib
+  PcdLib
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -56,14 +57,25 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
 
+[Pcd.IA32]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+
+[Pcd.X64]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
+
 [Sources]
   FspmWrapperPeim.c
 
+[Sources.IA32]
+  IA32/FspmHelper.c
+
+[Sources.X64]
+  X64/FspmHelper.c
+
 [Guids]
   gFspHobGuid   ## PRODUCES ## HOB
   gFspApiPerformanceGuid## SOMETIMES_CONSUMES ##

[edk2-devel] [PATCH v6] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-24 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c | 19 +++---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
 .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
 .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
 .../FspsWrapperPeim/FspsWrapperPeim.c | 17 +---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
 .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
 .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
 .../Include/Library/FspWrapperPlatformLib.h   |  2 +-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 10 files changed, 163 insertions(+), 11 deletions(-)
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..4a15136c39 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -39,6 +39,17 @@
 
 extern EFI_GUID gFspHobGuid;
 
+/**
+  Get the Fspm Upd Data Address from the PCD
+
+  @return FSPM UPD Data Address
+**/
+UINTN
+EFIAPI
+GetFspmUpdDataAddress (
+  VOID
+  );
+
 /**
   Call FspMemoryInit API.
 
@@ -59,7 +70,7 @@ PeiFspMemoryInit (
 
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
-  FspHobListPtr = NULL;
+  FspHobListPtr  = NULL;
   FspmUpdDataPtr = NULL;
 
   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
@@ -68,7 +79,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +91,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..5b4ad531e7 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -45,6 +45,7 @@
   FspWrapperApiLib
   FspWrapperApiTestLib
   FspMeasurementLib
+  PcdLib
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -56,14 +57,25 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
 
+[Pcd.IA32]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+
+[Pcd.X64]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
+
 [Sources]
   FspmWrapperPeim.c
 
+[Sources.IA32]
+  IA32/FspmHelper.c
+
+[Sources.X64]
+  X64/FspmHelper.c
+
 [Guids]
   gFspHobGuid   ## PRODUCES ## HOB
   gFspA

[edk2-devel] [PATCH v5] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-22 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c |  8 +++---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
 .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
 .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
 .../FspsWrapperPeim/FspsWrapperPeim.c |  6 ++---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
 .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
 .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
 .../Include/Library/FspWrapperPlatformLib.h   | 24 -
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 10 files changed, 163 insertions(+), 11 deletions(-)
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..6f2f0018ac 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -59,7 +59,7 @@ PeiFspMemoryInit (
 
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
-  FspHobListPtr = NULL;
+  FspHobListPtr  = NULL;
   FspmUpdDataPtr = NULL;
 
   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
@@ -68,7 +68,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +80,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..5b4ad531e7 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -45,6 +45,7 @@
   FspWrapperApiLib
   FspWrapperApiTestLib
   FspMeasurementLib
+  PcdLib
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -56,14 +57,25 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
 
+[Pcd.IA32]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+
+[Pcd.X64]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
+
 [Sources]
   FspmWrapperPeim.c
 
+[Sources.IA32]
+  IA32/FspmHelper.c
+
+[Sources.X64]
+  X64/FspmHelper.c
+
 [Guids]
   gFspHobGuid   ## PRODUCES ## HOB
   gFspApiPerformanceGuid## SOMETIMES_CONSUMES ## GUID
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
new file mode 100644
index

[edk2-devel] [PATCH v4] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-22 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 ...Pkg-FSPM-S-UPD-data-address-based-on.patch | 383 ++
 .../FspmWrapperPeim/FspmWrapperPeim.c |   8 +-
 .../FspmWrapperPeim/FspmWrapperPeim.inf   |  16 +-
 .../FspmWrapperPeim/IA32/FspmHelper.c |  26 ++
 .../FspmWrapperPeim/X64/FspmHelper.c  |  26 ++
 .../FspsWrapperPeim/FspsWrapperPeim.c |   6 +-
 .../FspsWrapperPeim/FspsWrapperPeim.inf   |  14 +-
 .../FspsWrapperPeim/IA32/FspsHelper.c |  26 ++
 .../FspsWrapperPeim/X64/FspsHelper.c  |  26 ++
 .../Include/Library/FspWrapperPlatformLib.h   |  24 +-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |   2 +
 11 files changed, 546 insertions(+), 11 deletions(-)
 create mode 100644 
0001-IntelFsp2WrapperPkg-FSPM-S-UPD-data-address-based-on.patch
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c

diff --git a/0001-IntelFsp2WrapperPkg-FSPM-S-UPD-data-address-based-on.patch 
b/0001-IntelFsp2WrapperPkg-FSPM-S-UPD-data-address-based-on.patch
new file mode 100644
index 00..abf76ebfc0
--- /dev/null
+++ b/0001-IntelFsp2WrapperPkg-FSPM-S-UPD-data-address-based-on.patch
@@ -0,0 +1,383 @@
+From d03b2a23908985d767a32592c9b4e4b4d0fa9e7d Mon Sep 17 00:00:00 2001
+Message-Id: 

+From: Ashraf Ali S 
+Date: Sun, 19 Sep 2021 23:10:18 +0530
+Subject: [PATCH v3] IntelFsp2WrapperPkg : FSPM/S UPD data address based on
+ Build Type
+
+REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
+when the module is not building in IA32 mode which will lead to
+building error. when a module built-in X64 function pointer will be the
+size of 64bit width which cannot be fit in 32bit address which will lead
+to error. to overcome this issue introducing the 2 new PCD's
+for the 64bit modules can consume it.
+Creating the API's to support different architecture
+
+Cc: Chasel Chiu 
+Cc: Nate DeSimone 
+Cc: Star Zeng 
+Cc: Kuo Ted 
+Cc: Duggapu Chinni B 
+Cc: Rangasai V Chaganty 
+Cc: Digant H Solanki 
+Cc: Sangeetha V 
+Cc: Ray Ni 
+Signed-off-by: Ashraf Ali S 
+---
+ .../FspmWrapperPeim/FspmWrapperPeim.c |  8 +++---
+ .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
+ .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
+ .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
+ .../FspsWrapperPeim/FspsWrapperPeim.c |  6 ++---
+ .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
+ .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
+ .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
+ .../Include/Library/FspWrapperPlatformLib.h   | 24 -
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
+ 10 files changed, 163 insertions(+), 11 deletions(-)
+ create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
+ create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
+ create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
+ create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c
+
+diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+index 24ab534620..6f2f0018ac 100644
+--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
 b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+@@ -3,7 +3,7 @@
+   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
+   notify to call FspSiliconInit API.
+ 
+-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
++  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+ 
+ **/
+@@ -59,7 +59,7 @@ PeiFspMemoryInit (
+ 
+   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
+ 
+-  FspHobListPtr = NULL;
++  FspHobListPtr  = NULL;
+   FspmUpdDataPtr = NULL;
+ 
+   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
+@@ -68,7 +68,7 @@ PeiFspMemoryInit (
+ return EFI_DEVICE_ERROR;
+   }
+ 
+-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHe

[edk2-devel] [PATCH v3] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-22 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c |  8 +++---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   | 16 ++--
 .../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
 .../FspmWrapperPeim/X64/FspmHelper.c  | 26 +++
 .../FspsWrapperPeim/FspsWrapperPeim.c |  6 ++---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   | 14 +-
 .../FspsWrapperPeim/IA32/FspsHelper.c | 26 +++
 .../FspsWrapperPeim/X64/FspsHelper.c  | 26 +++
 .../Include/Library/FspWrapperPlatformLib.h   | 24 -
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 10 files changed, 163 insertions(+), 11 deletions(-)
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspmHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspsHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspsHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..6f2f0018ac 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -59,7 +59,7 @@ PeiFspMemoryInit (
 
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
-  FspHobListPtr = NULL;
+  FspHobListPtr  = NULL;
   FspmUpdDataPtr = NULL;
 
   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
@@ -68,7 +68,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +80,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..e22eae4dd6 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -45,6 +45,7 @@
   FspWrapperApiLib
   FspWrapperApiTestLib
   FspMeasurementLib
+  PcdLib
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -56,14 +57,25 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
 
+[Pcd.IA32]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+
+[Pcd.X64]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
+
 [Sources]
   FspmWrapperPeim.c
 
+[Sources.IA32]
+  IA32/FspmHelper.c
+
+[Sources.X64]
+  IA32/FspmHelper.c
+
 [Guids]
   gFspHobGuid   ## PRODUCES ## HOB
   gFspApiPerformanceGuid## SOMETIMES_CONSUMES ## GUID
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspmHelper.c
new file mode 100644
index

[edk2-devel] [PATCH v2] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-22 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c |  8 +++---
 .../FspmWrapperPeim/FspmWrapperPeim.inf   | 10 +--
 .../FspmWrapperPeim/IA32/FspHelper.c  | 27 +++
 .../FspmWrapperPeim/X64/FspHelper.c   | 27 +++
 .../FspsWrapperPeim/FspsWrapperPeim.c |  6 ++---
 .../FspsWrapperPeim/FspsWrapperPeim.inf   |  8 +-
 .../FspsWrapperPeim/IA32/FspHelper.c  | 26 ++
 .../FspsWrapperPeim/X64/FspHelper.c   | 26 ++
 .../Include/Library/FspWrapperPlatformLib.h   | 24 -
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 ++
 10 files changed, 153 insertions(+), 11 deletions(-)
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspmWrapperPeim/X64/FspHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/IA32/FspHelper.c
 create mode 100644 IntelFsp2WrapperPkg/FspsWrapperPeim/X64/FspHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..6f2f0018ac 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -59,7 +59,7 @@ PeiFspMemoryInit (
 
   DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
 
-  FspHobListPtr = NULL;
+  FspHobListPtr  = NULL;
   FspmUpdDataPtr = NULL;
 
   FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 
(PcdFspmBaseAddress));
@@ -68,7 +68,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +80,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..10f92e8a33 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -45,6 +45,7 @@
   FspWrapperApiLib
   FspWrapperApiTestLib
   FspMeasurementLib
+  PcdLib
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -56,11 +57,16 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
 
+[Pcd.IA32]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+
+[Pcd.X64]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64  ## CONSUMES
+
 [Sources]
   FspmWrapperPeim.c
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspHelper.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspHelper.c
new file mode 100644
index 00..3663a4aaad
--- /dev/null
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/IA32/FspHelper.c
@@ -0,0 +1,27 @@
+/** @file
+  Sample to provide FSP wrapper related function.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-Licens

[edk2-devel] [PATCH] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

2021-09-21 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to
building error. when a module built-in X64 function pointer will be the
size of 64bit width which cannot be fit in 32bit address which will lead
to error. to overcome this issue introducing the 2 new PCD's
for the 64bit modules can consume it.
Creating the API's to support different architecture

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c |  6 +--
 .../FspmWrapperPeim/FspmWrapperPeim.inf   |  3 +-
 .../FspsWrapperPeim/FspsWrapperPeim.c |  6 +--
 .../FspsWrapperPeim/FspsWrapperPeim.inf   |  1 -
 .../Include/Library/FspWrapperPlatformLib.h   | 24 ++-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 +
 .../BaseFspWrapperPlatformLibSample.inf   | 17 +++-
 .../IA32/FspHelper.c  | 40 +++
 .../X64/FspHelper.c   | 40 +++
 9 files changed, 128 insertions(+), 11 deletions(-)
 create mode 100644 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/IA32/FspHelper.c
 create mode 100644 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/X64/FspHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..77e172e459 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -68,7 +68,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +80,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..95317fb70d 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -56,7 +56,6 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 9d4f279e81..5875cc0fdc 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -283,7 +283,7 @@ PeiMemoryDiscoveredNotify (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspsUpdDataAddress) == 0 && (FspsHeaderPtr->CfgRegionSize 
!= 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspsUpdDataAddress () == 0 && (FspsHeaderPtr->CfgRegionSize != 0) && 
(FspsHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-S UPD data from Flash
 //
@@ -292,7 +292,7 @@ PeiMemoryDiscoveredNotify (
 SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + 
(UINTN)FspsHeaderPtr->C

[edk2-devel] [PATCH] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642 when the module is not building in IA32 mode which will l

2021-09-21 Thread Ashraf Ali S

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Kuo Ted 
Cc: Duggapu Chinni B 
Cc: Rangasai V Chaganty 
Cc: Digant H Solanki 
Cc: Sangeetha V 
Cc: Ray Ni 
Signed-off-by: Ashraf Ali S 
---
 .../FspmWrapperPeim/FspmWrapperPeim.c |  6 +--
 .../FspmWrapperPeim/FspmWrapperPeim.inf   |  3 +-
 .../FspsWrapperPeim/FspsWrapperPeim.c |  6 +--
 .../FspsWrapperPeim/FspsWrapperPeim.inf   |  1 -
 .../Include/Library/FspWrapperPlatformLib.h   | 24 ++-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec   |  2 +
 .../BaseFspWrapperPlatformLibSample.inf   | 17 +++-
 .../IA32/FspHelper.c  | 40 +++
 .../X64/FspHelper.c   | 40 +++
 9 files changed, 128 insertions(+), 11 deletions(-)
 create mode 100644 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/IA32/FspHelper.c
 create mode 100644 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/X64/FspHelper.c

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 24ab534620..77e172e459 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -68,7 +68,7 @@ PeiFspMemoryInit (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize 
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspmUpdDataAddress () == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && 
(FspmHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-M UPD data from Flash
 //
@@ -80,7 +80,7 @@ PeiFspMemoryInit (
 //
 // External UPD is ready, get the buffer from PCD pointer.
 //
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress ();
 ASSERT (FspmUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..95317fb70d 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
 # register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
 # notify to call FspSiliconInit API.
 #
-#  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -56,7 +56,6 @@
 
 [Pcd]
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress   ## CONSUMES
-  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection  ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress   ## CONSUMES
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig  ## CONSUMES
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index 9d4f279e81..5875cc0fdc 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
   register TemporaryRamDonePpi to call TempRamExit API, and register 
MemoryDiscoveredPpi
   notify to call FspSiliconInit API.
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -283,7 +283,7 @@ PeiMemoryDiscoveredNotify (
 return EFI_DEVICE_ERROR;
   }
 
-  if (PcdGet32 (PcdFspsUpdDataAddress) == 0 && (FspsHeaderPtr->CfgRegionSize 
!= 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
+  if (GetFspsUpdDataAddress () == 0 && (FspsHeaderPtr->CfgRegionSize != 0) && 
(FspsHeaderPtr->CfgRegionOffset != 0)) {
 //
 // Copy default FSP-S UPD data from Flash
 //
@@ -292,7 +292,7 @@ PeiMemoryDiscoveredNotify (
 SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + 
(UINTN)FspsHeaderPtr->CfgRegionOffset);
 CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
   } else {
-FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);
+FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress ();
 ASSERT (FspsUpdDataPtr != NULL);
   }
 
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf

[edk2-devel] [PATCH v2] UefiCpuPkg: SecCoreNative without ResetVector

2021-09-16 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492

Currently SecCore.inf having the resetvector code under IA32. if the
user wants to use both SecCore and UefiCpuPkg ResetVector it's not
possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf)
are sharing the same GUID which is BFV. to overcome this issue we can
create the Duplicate version of the SecCore.inf as SecCoreNative.inf
which contains pure SecCore Native functionality without resetvector.
SecCoreNative.inf should have the Unique GUID so that it can be used
along with UefiCpuPkg ResetVector in there implementation.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Digant H Solanki 
Cc: Sangeetha V 

Signed-off-by: Ashraf Ali S 
---
 UefiCpuPkg/SecCore/SecCoreNative.inf | 80 
 UefiCpuPkg/UefiCpuPkg.dsc|  1 +
 2 files changed, 81 insertions(+)
 create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf

diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf 
b/UefiCpuPkg/SecCore/SecCoreNative.inf
new file mode 100644
index 00..b528c59879
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCoreNative.inf
@@ -0,0 +1,80 @@
+## @file
+#  SecCoreNative module that implements the SEC phase.
+#
+# This is the first module taking control after the reset vector.
+# The entry point function is _ModuleEntryPoint in PlatformSecLib.
+# The entry point function starts in 32bit protected mode or 64bit
+# mode depending on how resetvector is implemented, enables
+# temporary memory and calls into SecStartup().
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = SecCoreNative
+  MODULE_UNI_FILE= SecCore.uni
+  FILE_GUID  = 43CA74CA-7D29-49A0-B3B9-20F84015B27D
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#
+
+[Sources]
+  SecMain.c
+  SecMain.h
+  FindPeiCore.c
+  SecBist.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  PlatformSecLib
+  PcdLib
+  DebugAgentLib
+  UefiCpuLib
+  PeCoffGetEntryPointLib
+  PeCoffExtraActionLib
+  CpuExceptionHandlerLib
+  ReportStatusCodeLib
+  PeiServicesLib
+  PeiServicesTablePointerLib
+  HobLib
+
+[Ppis]
+  ## SOMETIMES_CONSUMES
+  ## PRODUCES
+  gEfiSecPlatformInformationPpiGuid
+  ## SOMETIMES_CONSUMES
+  ## SOMETIMES_PRODUCES
+  gEfiSecPlatformInformation2PpiGuid
+  gEfiTemporaryRamDonePpiGuid  ## PRODUCES
+  ## NOTIFY
+  ## SOMETIMES_CONSUMES
+  gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
+  ## CONSUMES
+  gRepublishSecPpiPpiGuid
+
+[Guids]
+  ## SOMETIMES_PRODUCES   ## HOB
+  gEfiFirmwarePerformanceGuid
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes  ## 
CONSUMES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  SecCoreExtra.uni
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 699c91626b..870b452840 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -161,6 +161,7 @@
   UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
   UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
   UefiCpuPkg/SecCore/SecCore.inf
+  UefiCpuPkg/SecCore/SecCoreNative.inf
   UefiCpuPkg/SecMigrationPei/SecMigrationPei.inf
   UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
   UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
-- 
2.30.2.windows.1



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Re: [edk2-devel] [PATCH v7] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-16 Thread Ashraf Ali S

Hi., Ray

We cannot add ResetVector1G.inf in the DSC file since FILE_GUID should be the 
VTF GUID.
So it's better to be added in the YAML file as we were doing for 
FixupVtf/Vtf.inf.

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Ni, Ray  
Sent: Thursday, September 16, 2021 6:10 PM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul1 ; De, Debkumar 
; Han, Harry ; West, Catharine 
; V, Sangeetha ; Chaganty, 
Rangasai V ; Dureja, Sahil 

Subject: RE: [PATCH v7] UefiCpuPkg: VTF0 Linear-Address Translation to a 
1-GByte Page till 512GB

Reviewed-by: Ray Ni 

-Original Message-
From: S, Ashraf Ali  
Sent: Thursday, September 16, 2021 8:07 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali ; Ni, Ray ; Kumar, 
Rahul1 ; De, Debkumar ; Han, 
Harry ; West, Catharine ; V, 
Sangeetha ; Chaganty, Rangasai V 
; Dureja, Sahil 
Subject: [PATCH v7] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte 
Page till 512GB

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 ++
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M}/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
 .../{ => X64/PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../PageTable2M}/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  | 101 --
 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc|  20 
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   8 +-
 .../ResetVector/Vtf0/X64/PageTables1G.asm |  53 +
 .../X64/{PageTables.asm => PageTables2M.asm}  |  14 +--
 UefiCpuPkg/UefiCpuPkg.ci.yaml |   3 +-
 21 files changed, 187 insertions(+), 49 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.serial.raw (56%)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => PageTables2M.asm} 
(74%)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
new file mode 100644
index 
..79b

[edk2-devel] [PATCH v7] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-16 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 ++
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M}/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
 .../{ => X64/PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../PageTable2M}/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  | 101 --
 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc|  20 
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   8 +-
 .../ResetVector/Vtf0/X64/PageTables1G.asm |  53 +
 .../X64/{PageTables.asm => PageTables2M.asm}  |  14 +--
 UefiCpuPkg/UefiCpuPkg.ci.yaml |   3 +-
 21 files changed, 187 insertions(+), 49 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.serial.raw (56%)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => PageTables2M.asm} 
(74%)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
new file mode 100644
index 
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GIT binary patch
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[edk2-devel] [PATCH v6] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-15 Thread Ashraf Ali S

[edk2-devel] [PATCH V5]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 ++
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M}/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
 .../{ => X64/PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../PageTable2M}/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  | 101 --
 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc|  20 
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   8 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  53 +
 .../X64/{PageTables.asm => 2MPageTables.asm}  |  14 +--
 20 files changed, 185 insertions(+), 48 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.serial.raw (56%)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(74%)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
new file mode 100644
index 
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GIT binary patch
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[edk2-devel] [PATCH v5] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-15 Thread Ashraf Ali S

[edk2-devel] [PATCH V5]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
 .../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 0 -> 868 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 ++
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Bin/X64/PageTable1G/ResetVector.x64.raw   | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M}/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
 .../{ => X64/PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../PageTable2M}/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  | 101 --
 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc|  20 
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   8 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  53 +
 .../X64/{PageTables.asm => 2MPageTables.asm}  |  14 +--
 20 files changed, 185 insertions(+), 48 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
X64/PageTable2M}/ResetVector.x64.serial.raw (56%)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(74%)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
new file mode 100644
index 
..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d
GIT binary patch
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[edk2-devel] [PATCH v4] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-14 Thread Ashraf Ali S

[edk2-devel] [PATCH V4]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page.

Build Tool: if the nasm is not found it will throw Build errors like
FileNotFoundError: [WinError 2]The system cannot find the file specified
run the command wil try except block to get meaningful error message

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../PageTable1G/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable1G/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.x64.raw  | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable2M/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable2M/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../ResetVector.x64.port80.raw| Bin 28676 -> 28676 bytes
 .../Bin/{ => PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../ResetVector.x64.serial.raw| Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 ++
 UefiCpuPkg/ResetVector/Vtf0/Build.py  |  91 --
 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc|  20 
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   8 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  53 ++
 .../X64/{PageTables.asm => 2MPageTables.asm}  |  14 +--
 23 files changed, 177 insertions(+), 46 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.raw 
(56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.serial.raw (56%)
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/PageTables.inc
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(74%)

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
new file mode 100644
index 
..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d
GIT binary patch
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zk=?RqHTShwDri

[edk2-devel] [PATCH v3] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-11 Thread Ashraf Ali S

[edk2-devel] [PATCH V3]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../PageTable1G/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable1G/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.x64.raw  | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable2M/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable2M/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../ResetVector.x64.port80.raw| Bin 28676 -> 28676 bytes
 .../Bin/{ => PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../ResetVector.x64.serial.raw| Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 +++
 UefiCpuPkg/ResetVector/Vtf0/Build.py  |  83 --
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   6 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  66 ++
 .../X64/{PageTables.asm => 2MPageTables.asm}  |   0
 22 files changed, 159 insertions(+), 33 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.raw 
(56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.serial.raw (56%)
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(100%)

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
new file mode 100644
index 
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GIT binary patch
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zh~X?JL3WDg3C>QkuOy(Cz2D+G0r_U~$nfcMX3da8daJ0-dS5O=A1WLXmNL1lC1Y<`
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zio}TkTR*G5^X{9FA5UXrek_f(Dm%ge{zcRKQTBarR}@zApFT*{1~02#Vb0G@fokrZCZ#4rO<$dgqlM|B1ucd5-YJ)(Sw+Slu!}T!yY`YJFv$tYmjZq
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zZaI

[edk2-devel] [PATCH v2] UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GB

2021-09-11 Thread Ashraf Ali S

[edk2-devel] [PATCH V2]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte via Linear-
Address Translation to a 1-GByte Page

Test Result: Tested in both Simulation environment and Hardware
both works fine without any issues.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Cc: Rangasai V Chaganty 
Cc: Sahil Dureja 
Signed-off-by: Ashraf Ali S 
---
 .../PageTable1G/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable1G/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../PageTable1G/ResetVector.x64.port80.raw| Bin 0 -> 12292 bytes
 .../Vtf0/Bin/PageTable1G/ResetVector.x64.raw  | Bin 0 -> 12292 bytes
 .../PageTable1G/ResetVector.x64.serial.raw| Bin 0 -> 12292 bytes
 .../PageTable2M/ResetVector.ia32.port80.raw   | Bin 0 -> 484 bytes
 .../Vtf0/Bin/PageTable2M/ResetVector.ia32.raw | Bin 0 -> 468 bytes
 .../PageTable2M/ResetVector.ia32.serial.raw   | Bin 0 -> 868 bytes
 .../ResetVector.x64.port80.raw| Bin 28676 -> 28676 bytes
 .../Bin/{ => PageTable2M}/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
 .../ResetVector.x64.serial.raw| Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 0 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 0 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.inf  |   4 +-
 .../ResetVector/Vtf0/Bin/ResetVector1G.inf|  31 +++
 UefiCpuPkg/ResetVector/Vtf0/Build.py  |  83 --
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   6 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  66 ++
 .../X64/{PageTables.asm => 2MPageTables.asm}  |   0
 22 files changed, 159 insertions(+), 33 deletions(-)
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.x64.serial.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.port80.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.raw
 create mode 100644 
UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable2M/ResetVector.ia32.serial.raw
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.port80.raw (56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => PageTable2M}/ResetVector.x64.raw 
(56%)
 rename UefiCpuPkg/ResetVector/Vtf0/Bin/{ => 
PageTable2M}/ResetVector.x64.serial.raw (56%)
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
 delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.serial.raw
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector1G.inf
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(100%)

diff --git 
a/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/PageTable1G/ResetVector.ia32.port80.raw
new file mode 100644
index 
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GIT binary patch
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zZaI

Re: [edk2-devel] [PATCH v2 2/2] UefiCpuPkg: ResetVector Tool additional debug prints

2021-08-15 Thread Ashraf Ali S

Hi.,

Is this Patch Uploaded in GitHub?

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Ni, Ray  
Sent: Tuesday, July 27, 2021 10:42 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul1 ; De, Debkumar 
; Han, Harry ; West, Catharine 
; V, Sangeetha 
Subject: RE: [PATCH v2 2/2] UefiCpuPkg: ResetVector Tool additional debug prints

Reviewed-by: Ray Ni 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Friday, July 23, 2021 4:40 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Ni, Ray 
> ; Kumar, Rahul1 ; De, 
> Debkumar ; Han, Harry ; 
> West, Catharine ; V, Sangeetha 
> 
> Subject: [PATCH v2 2/2] UefiCpuPkg: ResetVector Tool additional debug 
> prints
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506
> 
> Before executing the nasm command, added print statement to know what 
> commands are executing.
> before printing the output file need check the status of command which 
> is executed. if the status is 0 then only print the output file name.
> 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Debkumar De 
> Cc: Harry Han 
> Cc: Catharine West 
> Cc: Sangeetha V 
> Signed-off-by: Ashraf Ali S 
> ---
>  UefiCpuPkg/ResetVector/Vtf0/Build.py | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py 
> b/UefiCpuPkg/ResetVector/Vtf0/Build.py
> index 55f4edd87b..b791d32762 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
> @@ -32,9 +32,12 @@ for arch in ('ia32', 'x64'):
>  '-o', output,
>  'Vtf0.nasmb',
>  )
> +print(f"Command : {' '.join(commandLine)}")
>  ret = RunCommand(commandLine)
> +if ret != 0:
> +print(f"something went wrong while executing {commandLine[-1]}")
> +sys.exit()
>  print('\tASM\t' + output)
> -if ret != 0: sys.exit(ret)
> 
>  commandLine = (
>  'python',
> --
> 2.30.2.windows.1



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Re: [edk2-devel] [PATCH] UefiCpuPkg: ResetVector Tool Support for Python 3

2021-07-23 Thread Ashraf Ali S

Hi., 
Based on Ray Feedback.

I have sent the patchset includes 1 and 2.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3506

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Ni, Ray  
Sent: Friday, July 23, 2021 8:03 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul1 ; De, Debkumar 
; Han, Harry ; West, Catharine 
; V, Sangeetha 
Subject: RE: [PATCH] UefiCpuPkg: ResetVector Tool Support for Python 3

Ashraf,
I assume that your previous ResetVector patch can be dropped, and we just 
review this one that supports python3 first, right?
Since this patch is for the feedbacks of patch separation, can you help to do 
it further?
1. only do minimal update to the python script to make it python3 capable. No 
additional printing.
2. add additional printing in 2nd patch
3. submit new .raw binary in a new patch serial because this binary update is 
not because of python3 but the out-of-dated binary.

To make it clear, 1 and 2 are two patches that belong to the same patch set.
3 is a separate patch.

Thanks,
Ray


> -Original Message-
> From: S, Ashraf Ali 
> Sent: Friday, July 23, 2021 12:41 AM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Ni, Ray 
> ; Kumar, Rahul1 ; De, 
> Debkumar ; Han, Harry ; 
> West, Catharine ; V, Sangeetha 
> 
> Subject: [PATCH] UefiCpuPkg: ResetVector Tool Support for Python 3
> 
> [edk2-devel] [PATCH]
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506
> 
> Build Scrips for Reset Vector currently based on Python 2 which is 
> already EOL, needs to modify the build script based on Python 3, 
> update the Binary accordingly.
> 
> Change-Id: I2cfef08177951f2f29ee168ac4a9de9b10769ea1
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Debkumar De 
> Cc: Harry Han 
> Cc: Catharine West 
> Cc: Sangeetha V 
> Signed-off-by: Ashraf Ali S 
> ---
>  .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 484 bytes
>  .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
>  .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 868 bytes
>  .../Vtf0/Bin/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
>  .../ResetVector/Vtf0/Bin/ResetVector.x64.raw  | Bin 28676 -> 28676 bytes
>  .../Vtf0/Bin/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
>  UefiCpuPkg/ResetVector/Vtf0/Build.py  |  11 +++
>  .../Vtf0/Tools/FixupForRawSection.py  |   4 ++--
>  8 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git 
> a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
> index 
> 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9ae
> ae21ff04d91d 100644 GIT binary patch delta 410
> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>PEYMB8#X*^*s
> zI*-2o*Lifq#%B#L{TUe;3~zVd>wJ;c9c#dNqsaO-vqOwyxZ<^$|Sx+*`qBE-KP
> zRw#MZ?IF_m@c;k+44fxR?lK-MVJf=bP$9%z%Jy2m^*||G=ZV*+3=ec3YyDQrw
> zhLV39>OTT4_yTke(6spG0}_@eiX$2-m<39tfuvB0QMW|nV~~MBTOFDYFc(>?{CR!5
> z`2b5=qlIr@Ka2ph)3jn)CK3=F06%+4CG<$;o!=g(0n4LMA4`}djk7m=n
> z@tSo9&>Du9B|zggh&^lgwVUBX-))iIZU6Ps_!-61b|^D2IPfbSNPCqzIiFFU^R?Xs
> zd4>r<#gi8>%0vL2z`!uOpJBgKz-zAkjsdS((>jm5W_tbeb@R)JfB*l#TmvLJAN+p?
> a3S}hl`Z9zAvN|lpjbXxs*L#qpCjbB+6v6TU
> 
> delta 442
> zcmX9)O-lk%6n)b;mb6f61Fgs7G?G=i3EW`h#0jTXjjt=xN`<_@e*RfKhRH@
> zRthehQp z2#|b@Yi!yt8wAow*Da-71;Y*UMJdG%{oGQ>0fSK3#P_%@6n3VVmKY~2sF%gXydlkT
> zz2J+}fsf;~_pRoa+J(fR`Ut;~>qat}3#muERkA!QyT~Xg^M>rg%^bM|McBYs`8V0A
> zcP(O;ogKlFmCBIg5bqJ
> zBhR=?>3OE6Mw4r>-vk>Al5t4>DR50tqp6HM5M^V1To7n?Y1=u`A{@A7c!=ymHGRlZ
> zJ}anuVpcRdDYzN0P#%MY-J^!^vR_OvBRp9GvF1f*Ah$29X~lhJI8j|qcKWL;$
> mb+{6FrzA&7=!a5r41gb~Ws5tejhbe+Ol`#xF!g`tAAbQ#M!vED
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw 
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
> index 
> e34780a3a2c9b22bd10a1d5a405e344faaff94f3..ce7faa502b858e99908bcdb397b7
> 76258205e1d5 100644 GIT binary patch delta 421 
> zcmaFDe1%zP0uUG;&}9%{V6bIiVEA8TJW)uczPUn$q4ZSeVde;h(!;MgckBm(
> zbsl}`)Ec)Rmn=Zm!NSOdlzMb@vG9g56a50n@+A7C%iRr%2sA^z>KLdmOc50S=)
> z|NsAI;5=D!m+@c;Q_=N?3L)lFw%6jV2TIvGPrN>5c%buG>$g&-l7BD10Br{v65o74
> z!m|EEaYRD}vp|V7kQ6F0>XvAH3^E94n?v<|1pAKd)~$A7DvqwD658)#cwFVZ(U1
> z(K^7DfuU5M*;(VYJW#Upa9X2vSX3z=volBY0S*4`(QKMGUbF51+Qaa&258)`-3%Z4
> zZtt%9ub0NpD4w=MnSsH9U+F;FtJKNSjMDY5-6qI0OaQ6_1rZE@G=l)pF$@fo_h
> zFuI>%zf-_#uKkVyuUXSNkGy7j{quG6%Zz{j|G(S NFyZwchzJ{m0sv1?z^?!R
> 
> literal 484
> zcmX9*OG_g`5Uz2YXi!K{AwfI@4Wb8^4I;k92Z}6+5k#W02QLkK9j9Rq9_
> zqIePigaaNjIzCSdixLS)RFt&2cybqA?5!~cU5~H6s_N>tZQD+`9S{Z>1OTb`GBa#G
> zt*_G(GaClinx^RkGo#yGe2LyNvnlO${H9mTj3XK78TZswjJl#0BPWZ(PsE3m63x5<
> zkj

[edk2-devel] [PATCH v2 2/2] UefiCpuPkg: ResetVector Tool additional debug prints

2021-07-23 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506

Before executing the nasm command, added print statement to know what
commands are executing.
before printing the output file need check the status of command which
is executed. if the status is 0 then only print the output file name.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Signed-off-by: Ashraf Ali S 
---
 UefiCpuPkg/ResetVector/Vtf0/Build.py | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py 
b/UefiCpuPkg/ResetVector/Vtf0/Build.py
index 55f4edd87b..b791d32762 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
@@ -32,9 +32,12 @@ for arch in ('ia32', 'x64'):
 '-o', output,
 'Vtf0.nasmb',
 )
+print(f"Command : {' '.join(commandLine)}")
 ret = RunCommand(commandLine)
+if ret != 0:
+print(f"something went wrong while executing {commandLine[-1]}")
+sys.exit()
 print('\tASM\t' + output)
-if ret != 0: sys.exit(ret)
 
 commandLine = (
 'python',
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH v2 1/2] UefiCpuPkg: ResetVector Tool Support for Python 3

2021-07-23 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506

Build Scrips for Reset Vector currently based on Python 2
which is already EOL, needs to modify the build script based on
Python 3

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 

Signed-off-by: Ashraf Ali S 
---
 UefiCpuPkg/ResetVector/Vtf0/Build.py| 6 +++---
 UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py 
b/UefiCpuPkg/ResetVector/Vtf0/Build.py
index 343c53b5ff..55f4edd87b 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
@@ -1,7 +1,7 @@
 ## @file
 #  Automate the process of building the various reset vector types
 #
-#  Copyright (c) 2009, Intel Corporation. All rights reserved.
+#  Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -33,7 +33,7 @@ for arch in ('ia32', 'x64'):
 'Vtf0.nasmb',
 )
 ret = RunCommand(commandLine)
-print '\tASM\t' + output
+print('\tASM\t' + output)
 if ret != 0: sys.exit(ret)
 
 commandLine = (
@@ -41,7 +41,7 @@ for arch in ('ia32', 'x64'):
 'Tools/FixupForRawSection.py',
 output,
 )
-print '\tFIXUP\t' + output
+print('\tFIXUP\t' + output)
 ret = RunCommand(commandLine)
 if ret != 0: sys.exit(ret)
 
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py 
b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
index c77438a0ce..de771eba22 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
@@ -1,7 +1,7 @@
 ## @file
 #  Apply fixup to VTF binary image for FFS Raw section
 #
-#  Copyright (c) 2008, Intel Corporation. All rights reserved.
+#  Copyright (c) 2008 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4
 if c > len(d):
 c -= len(d)
 f = open(sys.argv[1], 'wb')
-f.write('\x90' * c)
+f.write(b'\x90' * c)
 f.write(d)
 f.close()
-- 
2.30.2.windows.1



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Re: [edk2-devel] [PATCH] UefiCpuPkg: ResetVector Tool Support for Python 3

2021-07-22 Thread Ashraf Ali S

Hi., Michael

Even If we generate the binaries using the Python2 also, it's getting changed.

Can you confirm from your end by generating the binaries using the build.py in 
Python2


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Kinney, Michael D  
Sent: Thursday, July 22, 2021 10:15 PM
To: devel@edk2.groups.io; S, Ashraf Ali 
Cc: Ni, Ray ; Kumar, Rahul1 ; De, 
Debkumar ; Han, Harry ; West, 
Catharine ; V, Sangeetha 
Subject: RE: [edk2-devel] [PATCH] UefiCpuPkg: ResetVector Tool Support for 
Python 3

Hi Ashraf,

Why would an update to the Python script to Python3 cause any changes to the 
binary images the script produces.

If they are different, then that would seem to imply that the change was not 
compatible from a behavior perspective.

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Ashraf 
> Ali S
> Sent: Thursday, July 22, 2021 9:41 AM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Ni, Ray 
> ; Kumar, Rahul1 ; De, 
> Debkumar ; Han, Harry ; 
> West, Catharine ; V, Sangeetha 
> 
> Subject: [edk2-devel] [PATCH] UefiCpuPkg: ResetVector Tool Support for 
> Python 3
> 
> [edk2-devel] [PATCH]
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506
> 
> Build Scrips for Reset Vector currently based on Python 2 which is 
> already EOL, needs to modify the build script based on Python 3, 
> update the Binary accordingly.
> 
> Change-Id: I2cfef08177951f2f29ee168ac4a9de9b10769ea1
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Cc: Debkumar De 
> Cc: Harry Han 
> Cc: Catharine West 
> Cc: Sangeetha V 
> Signed-off-by: Ashraf Ali S 
> ---
>  .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 484 bytes
>  .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
>  .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 868 bytes
>  .../Vtf0/Bin/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
>  .../ResetVector/Vtf0/Bin/ResetVector.x64.raw  | Bin 28676 -> 28676 bytes
>  .../Vtf0/Bin/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
>  UefiCpuPkg/ResetVector/Vtf0/Build.py  |  11 +++
>  .../Vtf0/Tools/FixupForRawSection.py  |   4 ++--
>  8 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git 
> a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
> index 
> 2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9ae
> ae21ff04d91d 100644 GIT binary patch delta 410
> zcmZo+dBQ9-0SF8a=rRZ}FxWCMF#Invo+zYJ-&~=>PEYMB8#X*^*s
> zI*-2o*Lifq#%B#L{TUe;3~zVd>wJ;c9c#dNqsaO-vqOwyxZ<^$|Sx+*`qBE-KP
> zRw#MZ?IF_m@c;k+44fxR?lK-MVJf=bP$9%z%Jy2m^*||G=ZV*+3=ec3YyDQrw
> zhLV39>OTT4_yTke(6spG0}_@eiX$2-m<39tfuvB0QMW|nV~~MBTOFDYFc(>?{CR!5
> z`2b5=qlIr@Ka2ph)3jn)CK3=F06%+4CG<$;o!=g(0n4LMA4`}djk7m=n
> z@tSo9&>Du9B|zggh&^lgwVUBX-))iIZU6Ps_!-61b|^D2IPfbSNPCqzIiFFU^R?Xs
> zd4>r<#gi8>%0vL2z`!uOpJBgKz-zAkjsdS((>jm5W_tbeb@R)JfB*l#TmvLJAN+p?
> a3S}hl`Z9zAvN|lpjbXxs*L#qpCjbB+6v6TU
> 
> delta 442
> zcmX9)O-lk%6n)b;mb6f61Fgs7G?G=i3EW`h#0jTXjjt=xN`<_@e*RfKhRH@
> zRthehQp z2#|b@Yi!yt8wAow*Da-71;Y*UMJdG%{oGQ>0fSK3#P_%@6n3VVmKY~2sF%gXydlkT
> zz2J+}fsf;~_pRoa+J(fR`Ut;~>qat}3#muERkA!QyT~Xg^M>rg%^bM|McBYs`8V0A
> zcP(O;ogKlFmCBIg5bqJ
> zBhR=?>3OE6Mw4r>-vk>Al5t4>DR50tqp6HM5M^V1To7n?Y1=u`A{@A7c!=ymHGRlZ
> zJ}anuVpcRdDYzN0P#%MY-J^!^vR_OvBRp9GvF1f*Ah$29X~lhJI8j|qcKWL;$
> mb+{6FrzA&7=!a5r41gb~Ws5tejhbe+Ol`#xF!g`tAAbQ#M!vED
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw 
> b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
> index 
> e34780a3a2c9b22bd10a1d5a405e344faaff94f3..ce7faa502b858e99908bcdb397b7
> 76258205e1d5 100644 GIT binary patch delta 421 
> zcmaFDe1%zP0uUG;&}9%{V6bIiVEA8TJW)uczPUn$q4ZSeVde;h(!;MgckBm(
> zbsl}`)Ec)Rmn=Zm!NSOdlzMb@vG9g56a50n@+A7C%iRr%2sA^z>KLdmOc50S=)
> z|NsAI;5=D!m+@c;Q_=N?3L)lFw%6jV2TIvGPrN>5c%buG>$g&-l7BD10Br{v65o74
> z!m|EEaYRD}vp|V7kQ6F0>XvAH3^E94n?v<|1pAKd)~$A7DvqwD658)#cwFVZ(U1
> z(K^7DfuU5M*;(VYJW#Upa9X2vSX3z=volBY0S*4`(QKMGUbF51+Qaa&258)`-3%Z4
> zZtt%9ub0NpD4w=MnSsH9U+F;FtJKNSjMDY5-6qI0OaQ6_1rZE@G=l)pF$@fo_h
> zFuI>%zf-_#uKkVyuUXSNkGy7j{quG6%Zz{j|G(S NFyZwchzJ{m0sv1?z^?!R
> 
> literal 484
> zcmX9*OG_g`5Uz2YXi!K{AwfI@4Wb8^4I;k92Z}6+5k#W02QLkK9j9Rq9_
> zqIePigaaNjIzCSdixLS)RFt&2cybqA?5!~cU5~H6s_N>tZQD+`9S{Z>1OTb`GBa#G
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> zkjV2pUL={H-<6y`Ayi}y>qBYR=+mmu*E{2X*HV!;FJ=@olMU=1D z>r@*9G|11z5fTzEKTW^U3gc6Jd}Rz>i=xwezWi&|RKrFLb)7MgiLyt(A5Nap
> z{K@){_&;%jkXDHiVLej|v^%t)8c;mepB%?^+SRc((Td402KNZ-pIe~y>R7ebhG=Mi
>

Re: [edk2-devel] [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity

2021-07-22 Thread Ashraf Ali S

Hi. Ray
Based on Dov Murik  Comments to take the python script 
changes separately, 
I have filed the Bugzilla for that separately.
https://bugzilla.tianocore.org/show_bug.cgi?id=3506

verified the binary. More details are in Bugzilla.

Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Ni, Ray  
Sent: Wednesday, July 21, 2021 3:00 PM
To: Dov Murik ; Ard Biesheuvel ; 
Brijesh Singh ; James Bottomley ; 
Erdem Aktas ; Tom Lendacky ; 
Xu, Min M 
Cc: S, Ashraf Ali ; devel@edk2.groups.io; Ard 
Biesheuvel ; Justen, Jordan L 
; Agyeman, Prince ; Kumar, 
Rahul1 ; De, Debkumar ; Han, 
Harry ; West, Catharine ; V, 
Sangeetha 
Subject: RE: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page 
Granularity

OVMF's ResetVector is including the UefiCpuPkg's ResetVector. So, OVMF owners 
please do evaluate the impact.

I think this change assumes platform owner knows which format of page table 
should be chosen in build time.

-Original Message-
From: Dov Murik  
Sent: Tuesday, July 20, 2021 4:02 AM
To: Ard Biesheuvel ; Ni, Ray ; Brijesh Singh 
; James Bottomley ; Erdem Aktas 
; Tom Lendacky 
Cc: S, Ashraf Ali ; devel@edk2.groups.io; Ard 
Biesheuvel ; Justen, Jordan L 
; Agyeman, Prince ; Kumar, 
Rahul1 ; De, Debkumar ; Han, 
Harry ; West, Catharine ; V, 
Sangeetha 
Subject: Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page 
Granularity



On 19/07/2021 10:09, Ard Biesheuvel wrote:
> On Mon, 19 Jul 2021 at 05:14, Ni, Ray  wrote:
>>
>> This change generates the reset vector binary which only contains 1G page 
>> table. If a platform doesn't support 1G page table, this will cause system 
>> hang.
>>
>> To Ard and Jordan,
>> Can you evaluate whether this change impacts OVMF?
>>
> 
> I don't have a clue, sorry, and I wouldn't know where to begin looking.
> 
> Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be 
> needing help reviewing OVMF patches that are highly specific to 
> SEV/SNP or x86 in general.

Adding Tom too - I think he modified the OVMF reset vector lately and might 
know.

> 
> Please take a look.


I'm not an expert, but I think that OVMF has its own reset vector in 
OvmfPkg/ResetVector, and therefore the changes in uefiCpuPkg will not affect 
OVMF.


Regarding the patch itself:

(1) I suggest separating the python tooling changes to one patch, verifying 
that the new python scripts generate the same binary files as the original 
python scripts.  Then add another patch which introduces the reset vector 
changes.

(2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need to 
check this capability somewhere?


-Dov


> 
> 
>> To Prince,
>> Can you evaluate whether this change impacts SimicsOpenBoardPkg?
>>
>> Thanks,
>> Ray
>>
>> -Original Message-
>> From: S, Ashraf Ali 
>> Sent: Friday, July 2, 2021 8:25 PM
>> To: devel@edk2.groups.io
>> Cc: S, Ashraf Ali ; Ni, Ray 
>> ; Kumar, Rahul1 ; De, 
>> Debkumar ; Han, Harry ; 
>> West, Catharine ; V, Sangeetha 
>> 
>> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte 
>> Page Granularity
>>
>> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473
>>
>> X64 Reset Vector Code can access the memory range till 4GB using the 
>> Linear-Address Translation to a 2-MByte Page, when user wants to use more 
>> than 4G using 2M Page it will leads to use more number of Page table 
>> entries. using the 1-GByte Page table user can use more than 4G Memory by 
>> reducing the page table entries using 1-GByte Page, this patch attached can 
>> access memory range till 512GByte.
>> Build Scrips for Reset Vector currently based on Python 2 which is already 
>> EOL, needs to modify the build script based on Python 3, update the Binary 
>> accordingly.
>>
>> Cc: Ray Ni 
>> Cc: Rahul Kumar 
>> Cc: Debkumar De 
>> Cc: Harry Han 
>> Cc: Catharine West 
>> Cc: Sangeetha V 
>> Signed-off-by: Ashraf Ali S 
>> ---
>>  .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 484 bytes
>>  .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
>>  .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 868 bytes
>>  .../Vtf0/Bin/ResetVector.x64.port80.raw   | Bin 28676 -> 12292 bytes
>>  .../ResetVector/Vtf0/Bin/ResetVector.x64.raw  | Bin 28676 -> 12292 bytes
>>  .../Vtf0/Bin/ResetVector.x64.serial.raw   | Bin 28676 -> 12292 bytes
>>  UefiCpuPkg/ResetVector/Vtf0/Build.py  |  11 +--
>>  .../ResetVector/Vtf0/Ia32/PageTables64.asm|   2 +-
>>  UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
>>  .../Vtf0/Tools/FixupForRawSec

[edk2-devel] [PATCH] UefiCpuPkg: ResetVector Tool Support for Python 3

2021-07-22 Thread Ashraf Ali S

[edk2-devel] [PATCH]
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506

Build Scrips for Reset Vector currently based on Python 2
which is already EOL, needs to modify the build script based on
Python 3, update the Binary accordingly.

Change-Id: I2cfef08177951f2f29ee168ac4a9de9b10769ea1
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 484 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 868 bytes
 .../Vtf0/Bin/ResetVector.x64.port80.raw   | Bin 28676 -> 28676 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.x64.raw  | Bin 28676 -> 28676 bytes
 .../Vtf0/Bin/ResetVector.x64.serial.raw   | Bin 28676 -> 28676 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  |  11 +++
 .../Vtf0/Tools/FixupForRawSection.py  |   4 ++--
 8 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
index 
2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d
 100644
GIT binary patch
delta 410
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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
index 
e34780a3a2c9b22bd10a1d5a405e344faaff94f3..ce7faa502b858e99908bcdb397b776258205e1d5
 100644
GIT binary patch
delta 421
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zl^%U$aKcjfs4rQRn_>~T%y|SO&#

Re: [edk2-devel] [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

2021-07-19 Thread Ashraf Ali S

Hi., Ray

BIOS boot to OS verified in Simics Successfully with the following changes.
1. SecCoreNative.inf with new GUID.
2. Removed IA32 resetvector code from SecCoreNative.
3. Removed the ResetVector Code from PlatformSecLib
4. Consumed the ResetVector Code from UefiCpuPkg/ResetVector

The reason for this change:
Currently SecCore and ResetVector are using the Same GUID (BFV guid), which 
will block the usage of both SecCore and UefiCpuPkg/ResetVector at a same time.

Advantage of this patch:
1. Provided the Backward compatibility by keeping the original SecCore
2. User can use both SecCoreNative and ResetVector at a same time.
3. User can choose to avoid resetvector code maintenance at the platform level.


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd. 

-Original Message-
From: Ni, Ray  
Sent: Monday, July 19, 2021 8:13 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul1 ; De, Debkumar 
; Han, Harry ; West, Catharine 
; Solanki, Digant H ; V, 
Sangeetha 
Subject: RE: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

Ashraf,
What unit tests have you performed with this native SecCore?

Thanks,
Ray

-Original Message-
From: S, Ashraf Ali 
Sent: Wednesday, July 14, 2021 5:48 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali ; Ni, Ray ; Kumar, 
Rahul1 ; De, Debkumar ; Han, 
Harry ; West, Catharine ; 
Solanki, Digant H ; V, Sangeetha 

Subject: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492

Currently SecCore.inf having the resetvector code under IA32. if the user wants 
to use both SecCore and UefiCpuPkg ResetVector it's not possible, since SecCore 
and ResetVector(VTF0.INF/ResetVector.inf)
are sharing the same GUID which is BFV. to overcome this issue we can create 
the Duplicate version of the SecCore.inf as SecCoreNative.inf which contains 
pure SecCore Native functionality without resetvector.
SecCoreNative.inf should have the Unique GUID so that it can be used along with 
UefiCpuPkg ResetVector in there implementation.

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Digant H Solanki 
Cc: Sangeetha V 
---
 UefiCpuPkg/SecCore/SecCoreNative.inf | 80 
 1 file changed, 80 insertions(+)
 create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf

diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf 
b/UefiCpuPkg/SecCore/SecCoreNative.inf
new file mode 100644
index 00..f89a0e5f38
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCoreNative.inf
@@ -0,0 +1,80 @@
+## @file
+#  SecCoreNative module that implements the SEC phase.
+#
+#  This is the first module taking control after the reset vector.
+#  The entry point function is _ModuleEntryPoint in PlatformSecLib.
+#  The entry point function will start with protected mode, since the # 
+the transistion to flat mode it done by the resetvector, enable # 
+temporary memory and call into SecStartup().
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved. #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = SecCore
+  MODULE_UNI_FILE= SecCore.uni
+  FILE_GUID  = 43CA74CA-7D29-49A0-B3B9-20F84015B27D
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#
+
+[Sources]
+  SecMain.c
+  SecMain.h
+  FindPeiCore.c
+  SecBist.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  PlatformSecLib
+  PcdLib
+  DebugAgentLib
+  UefiCpuLib
+  PeCoffGetEntryPointLib
+  PeCoffExtraActionLib
+  CpuExceptionHandlerLib
+  ReportStatusCodeLib
+  PeiServicesLib
+  PeiServicesTablePointerLib
+  HobLib
+
+[Ppis]
+  ## SOMETIMES_CONSUMES
+  ## PRODUCES
+  gEfiSecPlatformInformationPpiGuid
+  ## SOMETIMES_CONSUMES
+  ## SOMETIMES_PRODUCES
+  gEfiSecPlatformInformation2PpiGuid
+  gEfiTemporaryRamDonePpiGuid  ## PRODUCES
+  ## NOTIFY
+  ## SOMETIMES_CONSUMES
+  gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
+  ## CONSUMES
+  gRepublishSecPpiPpiGuid
+
+[Guids]
+  ## SOMETIMES_PRODUCES   ## HOB
+  gEfiFirmwarePerformanceGuid
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes
+## CONSUMES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  SecCoreExtra.uni
--
2.30.2.windows.1



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[edk2-devel] [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

2021-07-14 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492

Currently SecCore.inf having the resetvector code under IA32. if the
user wants to use both SecCore and UefiCpuPkg ResetVector it's not
possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf)
are sharing the same GUID which is BFV. to overcome this issue we can
create the Duplicate version of the SecCore.inf as SecCoreNative.inf
which contains pure SecCore Native functionality without resetvector.
SecCoreNative.inf should have the Unique GUID so that it can be used
along with UefiCpuPkg ResetVector in there implementation.

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Digant H Solanki 
Cc: Sangeetha V 
---
 UefiCpuPkg/SecCore/SecCoreNative.inf | 80 
 1 file changed, 80 insertions(+)
 create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf

diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf 
b/UefiCpuPkg/SecCore/SecCoreNative.inf
new file mode 100644
index 00..f89a0e5f38
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCoreNative.inf
@@ -0,0 +1,80 @@
+## @file
+#  SecCoreNative module that implements the SEC phase.
+#
+#  This is the first module taking control after the reset vector.
+#  The entry point function is _ModuleEntryPoint in PlatformSecLib.
+#  The entry point function will start with protected mode, since the
+#  the transistion to flat mode it done by the resetvector, enable
+#  temporary memory and call into SecStartup().
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = SecCore
+  MODULE_UNI_FILE= SecCore.uni
+  FILE_GUID  = 43CA74CA-7D29-49A0-B3B9-20F84015B27D
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#
+
+[Sources]
+  SecMain.c
+  SecMain.h
+  FindPeiCore.c
+  SecBist.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  PlatformSecLib
+  PcdLib
+  DebugAgentLib
+  UefiCpuLib
+  PeCoffGetEntryPointLib
+  PeCoffExtraActionLib
+  CpuExceptionHandlerLib
+  ReportStatusCodeLib
+  PeiServicesLib
+  PeiServicesTablePointerLib
+  HobLib
+
+[Ppis]
+  ## SOMETIMES_CONSUMES
+  ## PRODUCES
+  gEfiSecPlatformInformationPpiGuid
+  ## SOMETIMES_CONSUMES
+  ## SOMETIMES_PRODUCES
+  gEfiSecPlatformInformation2PpiGuid
+  gEfiTemporaryRamDonePpiGuid  ## PRODUCES
+  ## NOTIFY
+  ## SOMETIMES_CONSUMES
+  gPeiSecPerformancePpiGuid
+  gEfiPeiCoreFvLocationPpiGuid
+  ## CONSUMES
+  gRepublishSecPpiPpiGuid
+
+[Guids]
+  ## SOMETIMES_PRODUCES   ## HOB
+  gEfiFirmwarePerformanceGuid
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize  ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes  ## 
CONSUMES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  SecCoreExtra.uni
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: BaseCacheLib EfiProgramMtrr MtrrNumber Should be UINT32

2021-07-09 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3485

CacheLib EfiProgramMtrr Function takes MTRR number as a input parameter,
in the function the parameter is defined as UINTN were as the caller
calling MTTR number in UINT32.

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
Cc: Digant H Solanki 
Cc: Sangeetha V 
---
 IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf | 4 ++--
 IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf 
b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
index d9034bcbaf..9a513fb6df 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/BaseCacheLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  Instance of BaseCache.
 #
-#  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+#  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -15,7 +15,7 @@
   VERSION_STRING = 1.0
   LIBRARY_CLASS  = CacheLib
 
-[Sources.IA32]
+[Sources]
   CacheLib.c
   CacheLibInternal.h
 
diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c 
b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
index 17e895c345..2365f7514e 100644
--- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
+++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -164,7 +164,7 @@ EfiRecoverCacheMtrr (
 **/
 VOID
 EfiProgramMtrr (
-  IN  UINTN MtrrNumber,
+  IN  UINT32MtrrNumber,
   IN  EFI_PHYSICAL_ADDRESS  MemoryAddress,
   IN  UINT64MemoryLength,
   IN  EFI_MEMORY_CACHE_TYPE MemoryCacheType,
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelSiliconPkg/Include/IndustryStandard: Add IgdOpRegion30.h to support IGD Opregion spec version 3.0

2021-07-08 Thread Ashraf Ali S

From: Digant H Solanki 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426

- There are many OpRegion fields obsoleted in MBOX1
- MBOX2 is re-purposed for Backlight related fields for dual LFP.
- Backlight related fields moved to MBOX2 from MBOX3 and some fields are 
obsoleted in MBOX3.

Signed-off-by: Digant H Solanki 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Ashraf Ali S 
---
 .../Include/IndustryStandard/IgdOpRegion30.h  | 100 ++
 1 file changed, 100 insertions(+)
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h 
b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
new file mode 100644
index 00..422a60bdbd
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
@@ -0,0 +1,100 @@
+/** @file
+  IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
+  Specification based on version 3.0.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _IGD_OPREGION_3_0_H_
+#define _IGD_OPREGION_3_0_H_
+
+#include "IgdOpRegion.h"
+
+#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5
+
+///
+/// OpRegion Mailbox 1 - Public ACPI Methods
+/// Offset 0x100, Size 0x100
+///
+typedef struct {
+  UINT32 DRDY;  ///< Offset 0x100 Driver Readiness
+  UINT32 CSTS;  ///< Offset 0x104 Status
+  UINT32 CEVT;  ///< Offset 0x108 Current Event
+  UINT8  RM11[0x14];///< Offset 0x10C Reserved Must be Zero
+  UINT32 DIDL[8];   ///< Offset 0x120 Supported Display Devices ID List
+  UINT32 CPDL[8];   ///< Offset 0x140 obsolete
+  UINT32 CADL[8];   ///< Offset 0x160 obsolete
+  UINT32 NADL[8];   ///< Offset 0x180 obsolete
+  UINT32 ASLP;  ///< Offset 0x1A0 ASL Sleep Time Out
+  UINT32 TIDX;  ///< Offset 0x1A4 obsolete
+  UINT32 CHPD;  ///< Offset 0x1A8 obsolete
+  UINT32 CLID;  ///< Offset 0x1AC Current Lid State Indicator
+  UINT32 CDCK;  ///< Offset 0x1B0 Current Docking State Indicator
+  UINT32 SXSW;  ///< Offset 0x1B4 obsolete
+  UINT32 EVTS;  ///< Offset 0x1B8 obsolete
+  UINT32 CNOT;  ///< Offset 0x1BC obsolete
+  UINT32 NRDY;  ///< Offset 0x1C0 Driver Status
+  UINT8  DID2[0x1C];///< Offset 0x1C4 Extended Supported Devices ID List 
(DOD)
+  UINT8  CPD2[0x1C];///< Offset 0x1E0 obsolete
+  UINT8  RM12[4];   ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1_VER_3_0;
+
+///
+/// OpRegion Mailbox 2 - Backlight communication
+/// Offset 0x200, Size 0x100
+///
+typedef struct {
+  UINT32 BCL1;  ///< Offset 0x200 Backlight Brightness for LFP1
+  UINT32 BCL2;  ///< Offset 0x204 Backlight Brightness for LFP2
+  UINT32 CBL1;  ///< Offset 0x208 Current User Brightness Level for 
LFP1
+  UINT32 CBL2;  ///< Offset 0x20C Current User Brightness Level for 
LFP2
+  UINT32 BCM1[0x1E];///< Offset 0x210 Backlight Brightness Levels Duty 
Cycle Mapping Table for LFP1
+  UINT32 BCM2[0x1E];///< Offset 0x288 Backlight Brightness Levels Duty 
Cycle Mapping Table for LFP2
+} IGD_OPREGION_MBOX2_VER_3_0;
+
+///
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support
+/// Offset 0x300, Size 0x100
+///
+typedef struct {
+  UINT32 ARDY;  ///< Offset 0x300 obsolete
+  UINT32 ASLC;  ///< Offset 0x304 obsolete
+  UINT32 TCHE;  ///< Offset 0x308 obsolete
+  UINT32 ALSI;  ///< Offset 0x30C obsolete
+  UINT32 BCLP;  ///< Offset 0x310 obsoleted in ver 3.0, moved to 
Mailbox 2.
+  UINT32 PFIT;  ///< Offset 0x314 obsolete
+  UINT32 CBLV;  ///< Offset 0x318 obsoleted in ver 3.0, moved to 
Mailbox 2.
+  UINT16 BCLM[0x14];///< Offset 0x31C obsoleted in ver 3.0, moved to 
Mailbox 2.
+  UINT32 CPFM;  ///< Offset 0x344 obsolete
+  UINT32 EPFM;  ///< Offset 0x348 obsolete
+  UINT8  PLUT[0x4A];///< Offset 0x34C obsolete
+  UINT32 PFMB;  ///< Offset 0x396 obsolete
+  UINT32 CCDV;  ///< Offset 0x39A obsolete
+  UINT32 PCFT;  ///< Offset 0x39E obsolete
+  UINT32 SROT;  ///< Offset 0x3A2 obsolete
+  UINT32 IUER;  ///< Offset 0x3A6 obsolete
+  UINT64 FDSS;  ///< Offset 0x3AA obsolete
+  UINT32 FDSP;  ///< Offset 0x3B2 obsolete
+  UINT32 STAT;  ///< Offset 0x3B6 obsolete
+  UINT64 RVDA;  ///< Offset 0x3BA Physical address of Raw VBT data. 
Added from Spec Version 0.90 to support VBT greater than 6KB.
+  UINT32 RVDS;  ///< Offset 0x3C2 Size of Raw VBT data. Added from 
Spec Version 0.90 to support VBT greater than 6KB.
+  UINT8  VRSR;  ///< Offset 0x3C6 Video RAM Self Refres

[edk2-devel] [PATCH v3] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-06 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required

verification : Working Fine

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..eb130049b5 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -304,10 +304,11 @@ class Symbols:
 match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
+break
 rptLine  = fdIn.readline()
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +403,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +428,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -455,7 +457,13 @@ class Symbols:
 continue
 
 if not moduleEntryPoint in modSymbols:
-return 1
+if matchSymbolGroupIndex == 2:
+if not '_ModuleEntryPoint' in modSymbols:
+return 1
+else:
+moduleEntryPoint = "_ModuleEntryPoint"
+else:
+return 1
 
 modEntry = '%s:%s' % (moduleName,moduleEntryPoint)
 if not modEntry in self.dictSymbolAddress:
@@ -498,7 +506,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH v2] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-05 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..64b4e927a0 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -304,10 +304,11 @@ class Symbols:
 match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
+break
 rptLine  = fdIn.readline()
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +403,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +428,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -455,7 +457,13 @@ class Symbols:
 continue
 
 if not moduleEntryPoint in modSymbols:
-return 1
+if matchSymbolGroupIndex == 1:
+if not '_ModuleEntryPoint' in modSymbols:
+return 1
+else:
+moduleEntryPoint = "_ModuleEntryPoint"
+else:
+return 1
 
 modEntry = '%s:%s' % (moduleName,moduleEntryPoint)
 if not modEntry in self.dictSymbolAddress:
@@ -498,7 +506,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-05 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..64b4e927a0 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -304,10 +304,11 @@ class Symbols:
 match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
+break
 rptLine  = fdIn.readline()
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +403,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +428,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -455,7 +457,13 @@ class Symbols:
 continue
 
 if not moduleEntryPoint in modSymbols:
-return 1
+if matchSymbolGroupIndex == 1:
+if not '_ModuleEntryPoint' in modSymbols:
+return 1
+else:
+moduleEntryPoint = "_ModuleEntryPoint"
+else:
+return 1
 
 modEntry = '%s:%s' % (moduleName,moduleEntryPoint)
 if not modEntry in self.dictSymbolAddress:
@@ -498,7 +506,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-05 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..623eeb55b8 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -297,17 +297,18 @@ class Symbols:
 #
 fvOffset= self.getFvOffsetInFd(infFile[0:-4] + ".Fv")
 fdIn= open(infFile, "r")
-rptLine = fdIn.readline()
+rptLine = fdIn.readlines()
 self.fdBase = 0x
 while (rptLine != "" ):
 #EFI_BASE_ADDRESS = 0xFFFDF400
 match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
+break
 rptLine  = fdIn.readline()
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +403,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +428,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -455,7 +457,13 @@ class Symbols:
 continue
 
 if not moduleEntryPoint in modSymbols:
-return 1
+if matchSymbolGroupIndex == 1:
+if not '_ModuleEntryPoint' in modSymbols:
+return 1
+else:
+moduleEntryPoint = "_ModuleEntryPoint"
+else:
+return 1
 
 modEntry = '%s:%s' % (moduleName,moduleEntryPoint)
 if not modEntry in self.dictSymbolAddress:
@@ -498,7 +506,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-04 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
it can be update the X64 in future.
modification of few typo errors in parseModMapFile, getCurr function
required

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..236019b62d 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -297,17 +297,17 @@ class Symbols:
 #
 fvOffset= self.getFvOffsetInFd(infFile[0:-4] + ".Fv")
 fdIn= open(infFile, "r")
-rptLine = fdIn.readline()
+rptLines = fdIn.readlines()
 self.fdBase = 0x
-while (rptLine != "" ):
+for line in rptLines:
 #EFI_BASE_ADDRESS = 0xFFFDF400
-match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
+match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", line)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
-rptLine  = fdIn.readline()
+break
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +402,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +427,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -498,7 +499,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.30.2.windows.1



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[edk2-devel] [PATCH] IntelFsp2Pkg: PatchFv parseInfFile function modification

2021-07-04 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3476

parseInfFile currently reading the EFI_BASE_ADDRESS from INF, once the
address found still it's continues to read the complete inf file which
is not required. once the EFI_BASE_ADDRESS read from the INF no need to
read the INF further.
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
it can be update the X64 in future.
modification of few typo errors in parseModMapFile, getCurr function
required

Signed-off-by: Ashraf Ali S 
Cc: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/Tools/PatchFv.py | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..765dfed8ef 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -1,6 +1,6 @@
 ## @ PatchFv.py
 #
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -297,17 +297,16 @@ class Symbols:
 #
 fvOffset= self.getFvOffsetInFd(infFile[0:-4] + ".Fv")
 fdIn= open(infFile, "r")
-rptLine = fdIn.readline()
+rptLines = fdIn.readlines()
 self.fdBase = 0x
-while (rptLine != "" ):
-#EFI_BASE_ADDRESS = 0xFFFDF400
-match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", 
rptLine)
+for line in rptLines:
+match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", line)
 if match is not None:
 self.fdBase = int(match.group(1), 16) - fvOffset
-rptLine  = fdIn.readline()
+break
 fdIn.close()
 if self.fdBase == 0x:
-raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
fvFile)
+raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % 
infFile)
 return 0
 
 #
@@ -402,6 +401,7 @@ class Symbols:
 #
 #  retval  0   Parsed MOD MAP file successfully
 #  retval  1   There is no moduleEntryPoint in modSymbols
+#  retval  2   There is no offset for moduleEntryPoint in 
modSymbols
 #
 def parseModMapFile(self, moduleName, mapFile):
 #
@@ -426,7 +426,7 @@ class Symbols:
 else:
 #MSFT
 #0003:0190   _gComBase  7a50 
SerialPo
-patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
+patchMapFileMatchString =  
"^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8,16}\s+)"
 matchKeyGroupIndex = 1
 matchSymbolGroupIndex  = 2
 prefix = ''
@@ -498,7 +498,7 @@ class Symbols:
 #
 #  Get current character
 #
-#  retval  elf.string[self.index]
+#  retval  self.string[self.index]
 #  retval  ''   Exception
 #
 def getCurr(self):
-- 
2.26.2.windows.1



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[edk2-devel] [PATCH 1/1] UefiCpuPkg: Empty change for test

2021-07-02 Thread Ashraf Ali S

Signed-off-by: Ashraf Ali S 
---
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 1 +
 1 file changed, 1 insertion(+)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf 
b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
index 9922cb27558c..8507275a92ae 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
@@ -15,6 +15,7 @@ [Defines]
   VERSION_STRING = 1.1
   MODULE_UNI_FILE= ResetVector.uni
 
+
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-- 
2.26.2.windows.1



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[edk2-devel] [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity

2021-07-02 Thread Ashraf Ali S

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the
Linear-Address Translation to a 2-MByte Page, when user wants to use
more than 4G using 2M Page it will leads to use more number of Page
table entries. using the 1-GByte Page table user can use more than
4G Memory by reducing the page table entries using 1-GByte Page,
this patch attached can access memory range till 512GByte.
Build Scrips for Reset Vector currently based on Python 2
which is already EOL, needs to modify the build script based on
Python 3, update the Binary accordingly.

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Debkumar De 
Cc: Harry Han 
Cc: Catharine West 
Cc: Sangeetha V 
Signed-off-by: Ashraf Ali S 
---
 .../Vtf0/Bin/ResetVector.ia32.port80.raw  | Bin 516 -> 484 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
 .../Vtf0/Bin/ResetVector.ia32.serial.raw  | Bin 884 -> 868 bytes
 .../Vtf0/Bin/ResetVector.x64.port80.raw   | Bin 28676 -> 12292 bytes
 .../ResetVector/Vtf0/Bin/ResetVector.x64.raw  | Bin 28676 -> 12292 bytes
 .../Vtf0/Bin/ResetVector.x64.serial.raw   | Bin 28676 -> 12292 bytes
 UefiCpuPkg/ResetVector/Vtf0/Build.py  |  11 +--
 .../ResetVector/Vtf0/Ia32/PageTables64.asm|   2 +-
 UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt|   2 +-
 .../Vtf0/Tools/FixupForRawSection.py  |   4 +-
 UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb|   4 +-
 .../ResetVector/Vtf0/X64/1GPageTables.asm |  64 ++
 .../X64/{PageTables.asm => 2MPageTables.asm}  |   0
 13 files changed, 77 insertions(+), 10 deletions(-)
 create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
 rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} 
(100%)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw
index 
2c6ff655ded2a5855ca8f4428d559a7727eb6983..79b23c047bdc6e552d77d5c9e9aeae21ff04d91d
 100644
GIT binary patch
delta 410
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a3S}hl`Z9zAvN|lpjbXxs*L#qpCjbB+6v6TU

delta 442
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zRthehQp0fSK3#P_%@6n3VVmKY~2sF%gXydlkT
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zcP(O;ogKlFmCBIg5bqJ
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mb+{6FrzA&7=!a5r41gb~Ws5tejhbe+Ol`#xF!g`tAAbQ#M!vED

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw 
b/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw
index 
e34780a3a2c9b22bd10a1d5a405e344faaff94f3..ce7faa502b858e99908bcdb397b776258205e1d5
 100644
GIT binary patch
delta 421
zcmaFDe1%zP0uUG;&}9%{V6bIiVEA8TJW)uczPUn$q4ZSeVde;h(!;MgckBm(
zbsl}`)Ec)Rmn=Zm!NSOdlzMb@vG9g56a50n@+A7C%iRr%2sA^z>KLdmOc50S=)
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z^8pFV6U7k?70d!9(m+zE#Hd@M@iE8{piK_V2bhbjRsOub-F$#0tIvx!s|Uq(h~riBD@{|

delta 425
zcmaFD_JwVNtbi=D;Q?I+0R{$J1_p-zMV1qFRYV|Y(?nnIjZR54`jN@+Ky@
zv%mcP|NsBaqZ1S4CZ1G|2xMYlFudJ)uk%G(cdP;9jUu;~%s_<>MRu(RN~~Dff$Sn<
zl^%U$aKcjfs4rQRn_>~T%y|SO&#

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