Re: [edk2] [edk2-test] SctPkg compilation is failing

[Meenakshi Aggarwal]

Hi Supreeth,

I am able to compile SctPkg with your suggested changes.

Yes, we are trying eith UDK2017 as this is what mentioned in How To Build".

I tried with edk2's master branch today and faced following error:


build.py...
/home/meenakshi/SCT/edk2/SctPkg/Library/SctGuidLib/SctGuidLib.inf(...): error 
5000: MODULE_TYPE is not given


Thanks,
Meenakshi

From: Supreeth Venkatesh 
Sent: Wednesday, March 20, 2019 8:49 AM
To: Meenakshi Aggarwal ; edk2-devel@lists.01.org
Cc: Dong Wei ; Jin, Eric ; Udit Kumar 
; Varun Sethi 
Subject: RE: [edk2-test] SctPkg compilation is failing

Hi Meenakshi,

I was able to reproduce this error.
This is because a change in the edk2 file 
BaseTools/Source/C/Makefiles/app.makefile
which was using relative path to make it work with absolute path.
This fix is present in latest edk2 versions already.
Hence, as indicated earlier I will update build instructions so as to point to 
edk2-stable201903 tag in the next few days.

Assuming you are using UDK2017 still, please replace relative path to absolute 
path in your edk2 source and you will be able to compile.

Diff details below.

tmp/sct_workspace/edk2$ git diff

diff --git a/BaseTools/Source/C/Makefiles/app.makefile 
b/BaseTools/Source/C/Makefiles/app.makefile
index e414551b4a..6017b2dd59 100644
--- a/BaseTools/Source/C/Makefiles/app.makefile
+++ b/BaseTools/Source/C/Makefiles/app.makefile
@@ -23,6 +23,6 @@ all: $(MAKEROOT)/bin $(APPLICATION)
$(APPLICATION): $(OBJECTS)
$(LINKER) -o $(APPLICATION) $(BUILD_LFLAGS) $(OBJECTS) 
-L$(MAKEROOT)/libs $(LIBS)

-$(OBJECTS): ../Include/Common/BuildVersion.h
+$(OBJECTS): $(MAKEROOT)/Include/Common/BuildVersion.h

Thanks,
Supreeth
From: Meenakshi Aggarwal 
mailto:meenakshi.aggar...@nxp.com>>
Sent: Tuesday, March 19, 2019 12:19 AM
To: Supreeth Venkatesh 
mailto:supreeth.venkat...@arm.com>>; 
edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
Cc: Dong Wei mailto:dong@arm.com>>; Jin, Eric 
mailto:eric@intel.com>>; Udit Kumar 
mailto:udit.ku...@nxp.com>>; Varun Sethi 
mailto:v.se...@nxp.com>>
Subject: RE: [edk2-test] SctPkg compilation is failing

Hi Supreeth,

I tried the step suggested by you, but still facing error:

meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ export 
EDK_TOOLS_PATH="/home/meenakshi/SCT/edk2/BaseTools"
meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ rm -f 
$EDK_TOOLS_PATH/Source/C/bin/GenBin
meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ cd ..
meenakshi@uefi-OptiPlex-790:~/SCT/edk2$ ./SctPkg/build.sh AARCH64 GCC
Target: AARCH64
Build: other
TOOLCHAIN is GCC49
Toolchain prefix: GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
Building from: /home/meenakshi/SCT/edk2
using prebuilt tools
Building GenBin
make: Entering directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
make: *** No rule to make target `../Include/Common/BuildVersion.h', needed by 
`GenBin.o'.  Stop.
make: Leaving directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
Error while building GenBin


Also, i can't see any update in compilation steps in edk2-test repository.
Please update latest steps.


Thanks,
Meenakshi

From: Supreeth Venkatesh 
mailto:supreeth.venkat...@arm.com>>
Sent: Monday, March 18, 2019 9:37 PM
To: Meenakshi Aggarwal 
mailto:meenakshi.aggar...@nxp.com>>; 
edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
Cc: Dong Wei mailto:dong@arm.com>>; Jin, Eric 
mailto:eric@intel.com>>
Subject: RE:[edk2-test] SctPkg compilation is failing

Changing Subject line to append [edk2-test].

If the source code for edk2 and/or edk2-test is stale, this may happen,
as GenBin is no longer a pre-built binary but it is getting built from the 
source.

Please try this with the existing build and recompile.
rm -f $EDK_TOOLS_PATH/Source/C/bin/GenBin

Also,
Build instructions need update, since UTWG decided to use edk2 stable releases 
tag.
I will update the instructions today.

Thanks,
Supreeth
From: Meenakshi Aggarwal 
mailto:meenakshi.aggar...@nxp.com>>
Sent: Monday, March 18, 2019 1:42 AM
To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>; Supreeth Venkatesh 
mailto:supreeth.venkat...@arm.com>>
Subject: SctPkg compilation is failing

Hi,


I followed below steps to compile SctPkg:

Refer to SctPkg/Tools/Source/GenBin/HowTo.txt to gen the GenBin and copy it to 
Home/Dev/SctWorkspace/Bin/BaseTools/BinWrappers/PosixLike

Build Instructions for UEFI SCTII AARCH64 (Linux)
   1) mkdir "sct_workspace"
   2) cd sct_workspace
   3) git clone 
https://github.com/tianocore/edk2-test.git<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2-test.git=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cb63c62842126422b188208d6ace2c138%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636886487253128518=hH6juyFTjHaUwfYq4WLFms6NyQk7YMYywLWyFi0bN%2BE%3D=0>
   4) git clone 
https://github.c

Re: [edk2] [edk2-test] SctPkg compilation is failing

[Meenakshi Aggarwal]

Hi Supreeth,

I tried the step suggested by you, but still facing error:

meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ export 
EDK_TOOLS_PATH="/home/meenakshi/SCT/edk2/BaseTools"
meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ rm -f 
$EDK_TOOLS_PATH/Source/C/bin/GenBin
meenakshi@uefi-OptiPlex-790:~/SCT/edk2/SctPkg$ cd ..
meenakshi@uefi-OptiPlex-790:~/SCT/edk2$ ./SctPkg/build.sh AARCH64 GCC
Target: AARCH64
Build: other
TOOLCHAIN is GCC49
Toolchain prefix: GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
Building from: /home/meenakshi/SCT/edk2
using prebuilt tools
Building GenBin
make: Entering directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
make: *** No rule to make target `../Include/Common/BuildVersion.h', needed by 
`GenBin.o'.  Stop.
make: Leaving directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
Error while building GenBin


Also, i can't see any update in compilation steps in edk2-test repository.
Please update latest steps.


Thanks,
Meenakshi

From: Supreeth Venkatesh 
Sent: Monday, March 18, 2019 9:37 PM
To: Meenakshi Aggarwal ; edk2-devel@lists.01.org
Cc: Dong Wei ; Jin, Eric 
Subject: RE:[edk2-test] SctPkg compilation is failing

Changing Subject line to append [edk2-test].

If the source code for edk2 and/or edk2-test is stale, this may happen,
as GenBin is no longer a pre-built binary but it is getting built from the 
source.

Please try this with the existing build and recompile.
rm -f $EDK_TOOLS_PATH/Source/C/bin/GenBin

Also,
Build instructions need update, since UTWG decided to use edk2 stable releases 
tag.
I will update the instructions today.

Thanks,
Supreeth
From: Meenakshi Aggarwal 
mailto:meenakshi.aggar...@nxp.com>>
Sent: Monday, March 18, 2019 1:42 AM
To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>; Supreeth Venkatesh 
mailto:supreeth.venkat...@arm.com>>
Subject: SctPkg compilation is failing

Hi,


I followed below steps to compile SctPkg:

Refer to SctPkg/Tools/Source/GenBin/HowTo.txt to gen the GenBin and copy it to 
Home/Dev/SctWorkspace/Bin/BaseTools/BinWrappers/PosixLike

Build Instructions for UEFI SCTII AARCH64 (Linux)
   1) mkdir "sct_workspace"
   2) cd sct_workspace
   3) git clone 
https://github.com/tianocore/edk2-test.git<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2-test.git=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cccf889fbbad24313a6e408d6a03f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636885219941288860=fePIVsPrXuJamaijqMwzC7ofb5e9zOSbwE5KXIrI%2Faw%3D=0>
   4) git clone 
https://github.com/tianocore/edk2<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cccf889fbbad24313a6e408d6a03f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636885219941288860=gUtGod9T7GC4RWAvn5DrpnzIF2%2Bwp09DvcumXJFneBs%3D=0>
   5) cd edk2
   6) git checkout UDK2017
   7) ln -s ../edk2-test/uefi-sct/SctPkg SctPkg
   8) cd ..
   9) mkdir -p "tools/gcc"
  10) cd "tools/gcc"
  11) wget -nv 
"https://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/aarch64-linux-gnu/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz<https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Freleases.linaro.org%2Fcomponents%2Ftoolchain%2Fbinaries%2F4.9-2016.02%2Faarch64-linux-gnu%2Fgcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cccf889fbbad24313a6e408d6a03f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636885219941298869=GJwSfTJu7XijioKuXANSpUhBKu7KLcM7K650IHIP2i0%3D=0>"
  12) tar -xf gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz
  13) cd ../..
  14) export 
PATH=$PATH:"$PWD/tools/gcc/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin"
  15) export 
CROSS_COMPILE="$PWD/tools/gcc/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-"
  16) ./SctPkg/build.sh AARCH64 GCC


But I am facing below error:

meenakshi@uefi-OptiPlex-790:~/SCT/edk2$ ./SctPkg/build.sh AARCH64 GCC
Target: AARCH64
Build: other
TOOLCHAIN is GCC49
Toolchain prefix: GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
Building from: /home/meenakshi/SCT/edk2
using prebuilt tools
Building GenBin
make: Entering directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
make: *** No rule to make target `../Include/Common/BuildVersion.h', needed by 
`GenBin.o'.  Stop.
make: Leaving directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
Error while building GenBin


Please help in compiling SctPkg.


Thanks,
Meenakshi
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[edk2] SctPkg compilation is failing

[Meenakshi Aggarwal]

Hi,


I followed below steps to compile SctPkg:

Refer to SctPkg/Tools/Source/GenBin/HowTo.txt to gen the GenBin and copy it to 
Home/Dev/SctWorkspace/Bin/BaseTools/BinWrappers/PosixLike

Build Instructions for UEFI SCTII AARCH64 (Linux)
   1) mkdir "sct_workspace"
   2) cd sct_workspace
   3) git clone https://github.com/tianocore/edk2-test.git
   4) git clone https://github.com/tianocore/edk2
   5) cd edk2
   6) git checkout UDK2017
   7) ln -s ../edk2-test/uefi-sct/SctPkg SctPkg
   8) cd ..
   9) mkdir -p "tools/gcc"
  10) cd "tools/gcc"
  11) wget -nv 
"https://releases.linaro.org/components/toolchain/binaries/4.9-2016.02/aarch64-linux-gnu/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz;
  12) tar -xf gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu.tar.xz
  13) cd ../..
  14) export 
PATH=$PATH:"$PWD/tools/gcc/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin"
  15) export 
CROSS_COMPILE="$PWD/tools/gcc/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-"
  16) ./SctPkg/build.sh AARCH64 GCC


But I am facing below error:

meenakshi@uefi-OptiPlex-790:~/SCT/edk2$ ./SctPkg/build.sh AARCH64 GCC
Target: AARCH64
Build: other
TOOLCHAIN is GCC49
Toolchain prefix: GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
Building from: /home/meenakshi/SCT/edk2
using prebuilt tools
Building GenBin
make: Entering directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
make: *** No rule to make target `../Include/Common/BuildVersion.h', needed by 
`GenBin.o'.  Stop.
make: Leaving directory 
`/home/meenakshi/SCT/edk2-test/uefi-sct/SctPkg/Tools/Source/GenBin'
Error while building GenBin


Please help in compiling SctPkg.


Thanks,
Meenakshi
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Re: [edk2] [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm 
> Sent: Wednesday, December 19, 2018 6:56 PM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar ; Varun Sethi
> 
> Subject: Re: [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib
> 
> On Wed, Nov 28, 2018 at 08:31:27PM +0530, Meenakshi Aggarwal wrote:
> > Add support of IfcLib, it will be used to perform any operation on IFC
> > controller.
> 
> Expand acronym.
> 
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  Silicon/NXP/Include/Library/IfcLib.h  |  26 +
> >  Silicon/NXP/Library/IfcLib/IfcLib.c   | 150 +++
> >  Silicon/NXP/Library/IfcLib/IfcLib.h   | 190
> ++
> >  Silicon/NXP/Library/IfcLib/IfcLib.inf |  38 +++
> 
> Names Ifc -> NxpIfc please.
> 
Is this renaming really needed for IfcLib, I can change the guard and header 
file name.

Please suggest?

> >  Silicon/NXP/NxpQoriqLs.dec|   1 +
> >  5 files changed, 405 insertions(+)
> >  create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> >  create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> >  create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> >  create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
> >
> > diff --git a/Silicon/NXP/Include/Library/IfcLib.h
> > b/Silicon/NXP/Include/Library/IfcLib.h
> > new file mode 100644
> > index 000..8d2c151
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/IfcLib.h
> > @@ -0,0 +1,26 @@
> > +/** @IfcLib.h
> > +
> > +  The integrated flash controller (IFC) is used to interface with
> > + external asynchronous  NAND flash, asynchronous NOR flash, SRAM, generic
> ASIC memories and EPROM.
> > +
> > +  Copyright 2018 NXP
> > +
> > +  This program and the accompanying materials  are licensed and made
> > + available under the terms and conditions of the BSD License  which
> > + accompanies this distribution.  The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.phpdata=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C62c0401c65ac481e650508d665b57ea9%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636808227519182943sdata=4
> UMgN
> > + 7laz86jDwTlvJrHWkqdum8qmZPGWrhESvjHBMQ%3Dreserved=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS,  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __IFC_LIB_H__
> > +#define __IFC_LIB_H__
> 
> Header guard NXP_ (and/or QORIQ_) prefix.
> 
> > +
> > +VOID
> > +IfcInit (
> > +  VOID
> > +  );
> > +
> > +#endif //__IFC_LIB_H__
> > diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c
> > b/Silicon/NXP/Library/IfcLib/IfcLib.c
> > new file mode 100644
> > index 000..8cf02ae
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
> > @@ -0,0 +1,150 @@
> > +/** @IfcLib.c
> > +
> > +  The integrated flash controller (IFC) is used to interface with
> > + external asynchronous/  synchronous NAND flash, asynchronous NOR
> > + flash, SRAM, generic ASIC memory and  EPROM.
> > +  It has eight chip-selects, to which a maximum of eight flash
> > + devices can be attached,  although only one of these can be accessed at 
> > any
> given time.
> > +
> > +  Copyright 2018 NXP
> > +
> > +  This program and the accompanying materials  are licensed and made
> > + available under the terms and conditions of the BSD License  which
> > + accompanies this distribution.  The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.phpdata=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C62c0401c65ac481e650508d665b57ea9%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636808227519182943sdata=4
> UMgN
> > + 7laz86jDwTlvJrHWkqdum8qmZPGWrhESvjHBMQ%3Dreserved=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS,  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include 
> > +#in

Re: [edk2] [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm 
> Sent: Wednesday, December 19, 2018 12:16 AM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar ; Varun Sethi
> 
> Subject: Re: [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC
> controller
> 
> On Wed, Nov 28, 2018 at 08:31:25PM +0530, Meenakshi Aggarwal wrote:
> > This header file contain IFC controller timing structure, chip select
> > enum and other IFC macros.
> 
> Please expand the IFC acronym here (like is done in file header below).
> 
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  Silicon/NXP/Include/Ifc.h | 423
> > ++
> 
> Please Update at least filename Ifc.h->NxpIfc.h
> 
> >  1 file changed, 423 insertions(+)
> >  create mode 100644 Silicon/NXP/Include/Ifc.h
> >
> > diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h new
> > file mode 100644 index 000..6babb22
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Ifc.h
> > @@ -0,0 +1,423 @@
> > +/** @Ifc.h
> > +
> > +  The integrated flash controller (IFC) is used to interface with
> > + external asynchronous  NAND flash, asynchronous NOR flash, SRAM, generic
> ASIC memories and EPROM.
> > +
> > +  Copyright 2017 NXP
> > +
> > +  This program and the accompanying materials  are licensed and made
> > + available under the terms and conditions of the BSD License  which
> > + accompanies this distribution.  The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.phpdata=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7Cf5720bda0a8c4ab0dd6708d6651904fb%7C686ea1d
> 3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636807555468004917sdata=df
> OWZ
> > + Z2yXCKi55Cl94sAEGYx739%2FXCiK1yX3Wm6lTow%3Dreserved=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS,  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __IFC_H__
> > +#define __IFC_H__
> 
> Please add NXP_ prefix.
> 
> (I am less concerned about the actual defines below.)
> 
> > +
> > +#include 
> 
> Is BaseLib.h really used by this file?

Yes, it is needed for HighBitSet32() used in this file.

> If not, please drop it.
> 
> > +#include 
> > +
> > +#define IFC_BANK_COUNT4
> > +
> > +#define IFC_CSPR_REG_LEN  148
> > +#define IFC_AMASK_REG_LEN 144
> > +#define IFC_CSOR_REG_LEN  144
> > +#define IFC_FTIM_REG_LEN  576
> > +
> > +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
> > +  IFC_BANK_COUNT
> > +
> > +#define IFC_AMASK_USED_LENsizeof (IFC_AMASK) * \
> > +  IFC_BANK_COUNT
> > +
> > +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
> > +  IFC_BANK_COUNT
> > +
> > +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
> > +  IFC_BANK_COUNT
> > +
> > +/* List of commands */
> > +#define IFC_NAND_CMD_RESET0xFF
> > +#define IFC_NAND_CMD_READID   0x90
> > +#define IFC_NAND_CMD_STATUS   0x70
> > +#define IFC_NAND_CMD_READ00x00
> > +#define IFC_NAND_CMD_READSTART0x30
> > +#define IFC_NAND_CMD_ERASE1   0x60
> > +#define IFC_NAND_CMD_ERASE2   0xD0
> > +#define IFC_NAND_CMD_SEQIN0x80
> > +#define IFC_NAND_CMD_PAGEPROG 0x10
> > +#define MAX_RETRY_COUNT   15
> > +
> > +
> > +#define IFC_NAND_SEQ_STRT_FIR_STRT  0x8000
> > +
> > +/*
> > + * NAND Event and Error Status Register (NAND_EVTER_STAT)  */
> > +
> > +/* Operation Complete */
> > +#define IFC_NAND_EVTER_STAT_OPC 0x8000
> > +
> > +/* Flash Timeout Error */
> > +#define IFC_NAND_EVTER_STAT_FTOER   0x0800
> > +
> > +/* Write Protect Error */
> > +#define IFC_NAND_EVTER_STAT_WPER0x0400
> > +
> > +/* ECC Error */
> > +#define IFC_NAND_EVTER_STAT_ECCER   0x0200
> > +
> > +/*
> > + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
> > +*/
> > +
> > +/* NAND Machine specific opcodes OP0-OP14*/
> > +#define IFC_NAND_

Re: [edk2] [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm 
> Sent: Wednesday, December 19, 2018 12:11 AM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar ; Varun Sethi
> 
> Subject: Re: [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.
> 
> On Wed, Nov 28, 2018 at 08:31:24PM +0530, Meenakshi Aggarwal wrote:
> > Readme.md to explain how to build NXP board packages.
> >
> 
> Could you add a link to this file from top-level Readme.md (towards the very
> end)?
> 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  Platform/NXP/Readme.md | 24 
> >  1 file changed, 24 insertions(+)
> >  create mode 100644 Platform/NXP/Readme.md
> >
> > diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md new file
> > mode 100644 index 000..902bafe
> > --- /dev/null
> > +++ b/Platform/NXP/Readme.md
> > @@ -0,0 +1,24 @@
> > +Support for all NXP boards is available in this directory.
> > +
> > +# How to build
> > +
> > +1. Set toolchain path.
> > +
> > +   export
> > + PATH=/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-
> gn
> > + u/bin/:$PATH
> > +
> > +2. Export following variables needed for compilation.
> > +
> > +   export CROSS_COMPILE=aarch64-linux-gnu-
> > +   export GCC_ARCH_PREFIX=GCC49_AARCH64_PREFIX
> > +   export GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
> > +   export PACKAGES_PATH=/edk2/edk2-platforms
> > +
> 
> Can you check whether you are happy with the generic build instructions in the
> top-level Readme.md and improve those if not?
> Then you could reference those rather than repeating.
> 
Ok, will check the common Readme.md

> /
> Leif
> 
> > +3. Build desired board package
> > +
> > +   source edksetup.sh
> > +   build -p "path to package's description (.dsc) file" -a AARCH64 -t
> > + GCC49 -b DEBUG/RELEASE clean
> > +
> > +   e.g.
> > +   build -p
> "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a
> AARCH64 -t GCC49 -b DEBUG clean
> > +   build -p
> > + "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a
> > + AARCH64 -t GCC49 -b DEBUG
> > +
> > --
> > 1.9.1
> >
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Re: [edk2] [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W operation.

[Meenakshi Aggarwal]

Any comments?

> -Original Message-
> From: Meenakshi Aggarwal
> Sent: Tuesday, January 29, 2019 10:13 AM
> To: Meenakshi Aggarwal ;
> ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-devel@lists.01.org;
> jun@linaro.org; haojian.zhu...@linaro.org
> Subject: RE: [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W
> operation.
> 
> Hi,
> 
> Please share review comments.
> 
> Thanks,
> Meenakshi
> 
> > -Original Message-
> > From: Meenakshi Aggarwal 
> > Sent: Thursday, January 24, 2019 7:35 PM
> > To: ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > de...@lists.01.org; jun@linaro.org; haojian.zhu...@linaro.org
> > Cc: Meenakshi Aggarwal 
> > Subject: [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W
> > operation.
> >
> > Issue : SD read failure for high capacity cards e.g. 64 GB i Reason :
> > Command argument value exceeds 32 bit for block number 0x3787FFF and
> > cant be fit into
> > 32 bit wide SD host controller register.
> >
> > Fix :
> > AccessMode bits [29:30] of OCR is a valid definition to calculate data
> > address for eMMC cards.
> >
> > For SD cards, data address is calculated on the basis of card capacity
> > status bit[30] of OCR.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  EmbeddedPkg/Universal/MmcDxe/Mmc.h|  2 ++
> >  EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 21 
> -
> >  2 files changed, 18 insertions(+), 5 deletions(-)
> >
> > diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> > b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> > index a77ba41..62de2c8 100644
> > --- a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> > +++ b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> > @@ -70,6 +70,8 @@
> >  #define SD_HIGH_SPEED   5000
> >  #define SWITCH_CMD_SUCCESS_MASK 0x0f00
> >
> > +#define SD_CARD_CAPACITY0x0002
> > +
> >  #define BUSWIDTH_4  4
> >
> >  typedef enum {
> > diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > index a2b9232..1dea7d3 100644
> > --- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > +++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > @@ -148,12 +148,23 @@ MmcTransferBlock (
> >MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This);
> >MmcHost = MmcHostInstance->MmcHost;
> >
> > -  //Set command argument based on the card access mode (Byte mode or
> > Block
> > mode)
> > -  if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> > MMC_OCR_ACCESS_MASK) ==
> > -  MMC_OCR_ACCESS_SECTOR) {
> > -CmdArg = Lba;
> > +  if (MmcHostInstance->CardInfo.CardType != EMMC_CARD) {
> > +//Set command argument based on the card capacity
> > +//if 0 : SDSC card
> > +//if 1 : SDXC/SDHC
> > +if (MmcHostInstance->CardInfo.OCRData.AccessMode &
> > SD_CARD_CAPACITY) {
> > +  CmdArg = Lba;
> > +} else {
> > +  CmdArg = Lba * This->Media->BlockSize;
> > +}
> >} else {
> > -CmdArg = Lba * This->Media->BlockSize;
> > +//Set command argument based on the card access mode (Byte mode
> > + or
> > Block mode)
> > +if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> > MMC_OCR_ACCESS_MASK) ==
> > +MMC_OCR_ACCESS_SECTOR) {
> > +  CmdArg = Lba;
> > +} else {
> > +  CmdArg = Lba * This->Media->BlockSize;
> > +}
> >}
> >
> >Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg);
> > --
> > 1.9.1

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Re: [edk2] [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm 
> Sent: Monday, December 17, 2018 11:06 PM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar ; Varun Sethi
> 
> Subject: Re: [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for
> Watchdog driver
> 
> Starting with this one, since that was the biggest pain point last time 
> around.
> 
> On Wed, Nov 28, 2018 at 08:31:16PM +0530, Meenakshi Aggarwal wrote:
> > Installs watchdog timer arch protocol
> 
> As per the email I just cc:d you on: unless the hardware supports 
> configuration in
> a mode where it could be used for a compliant
> EFI_WATCHDOG_TIMER_ARCH_PROTOCOL (i.e., trigger a software event rather
> than a hardware reset), please rewrite this driver such that it does not 
> register as
> that protocol.
> 
Decided to use watchdog driver from MdeModulePkg.

> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  Silicon/NXP/Drivers/WatchDog/WatchDog.c  | 402
> +++
> >  Silicon/NXP/Drivers/WatchDog/WatchDog.h  |  39 +++
> >  Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf |  47 
> >  3 files changed, 488 insertions(+)
> >  create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> >  create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> >  create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> 
> I would appreciate if you could follow
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%27s-unkempt-git-
> guide-for-edk2-contributors-and-maintainers%23contrib-
> 23data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cc5cb603bead
> b4855f07608d6644624a1%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C636806649758902154sdata=NSs8taX%2F4oV0yhHmNEWVR%2Btzp3
> TqzuLnIy97t2R8dvs%3Dreserved=0
> when submitting the next revision. It greatly assists with reviewing.
> 
Ok, will do.

> > diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > new file mode 100644
> > index 000..1b1a3b5
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > @@ -0,0 +1,402 @@
> > +/** WatchDog.c
> > +*
> > +*  Based on Watchdog driver implemenation available in
> > +*  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
> > +*
> > +*  Copyright 2017 NXP
> 
> May want to change this to 2017-2018
> Also, format should be
> Copyright (c) ... NXP. All rights reserved.
> 
Will change the year to 2017-2019,
but I cant add (c) as it will not be approved by NXP's TAs.
 
> > +*
> > +*  This program and the accompanying materials
> > +*  are licensed and made available under the terms and conditions of
> > +the BSD License
> > +*  which accompanies this distribution.  The full text of the license
> > +may be found at
> > +*
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.phpdata=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7Cc5cb603beadb4855f07608d6644624a1%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636806649758902154sdata=RLV
> E%2Bxi
> > +qQaQnHRKR7Spc6QYdx1pHPnKyqheLBqIinU4%3Dreserved=0
> > +*
> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "WatchDog.h"
> > +
> > +STATIC EFI_EVENT  EfiExitBootServicesEvent; STATIC EFI_EVENT
> > +WdogFeedEvent;
> 
> m-prefix for both above please.
> 
> Can you do a search-and-replace Wdog -> Watchdog and WDOG -> WATCHDOG
> please?
> 
> > +STATIC MMIO_OPERATIONS_16 *mMmioOps;
> > +
> > +
> > +STATIC
> > +VOID
> > +WdogPing (
> > +  VOID
> > +  )
> > +{
> > +  //
> > +  // To reload a timeout value to the counter the proper service
> > +sequence begins by
> > +  // writing 0x_ followed by 0x_ to the Watchdog Service Register
> (WDOG_WSR).
> > +  // This service sequence will reload the counter with the timeout
> > +value WT[7:0] of
> > +  // Watchdog Control Register (WDOG_WCR).
> > +  //
> > +
> > +  mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) 

Re: [edk2] [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W operation.

[Meenakshi Aggarwal]

Hi,

Please share review comments.

Thanks,
Meenakshi

> -Original Message-
> From: Meenakshi Aggarwal 
> Sent: Thursday, January 24, 2019 7:35 PM
> To: ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> de...@lists.01.org; jun@linaro.org; haojian.zhu...@linaro.org
> Cc: Meenakshi Aggarwal 
> Subject: [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W
> operation.
> 
> Issue : SD read failure for high capacity cards e.g. 64 GB i Reason : Command
> argument value exceeds 32 bit for block number 0x3787FFF and cant be fit into
> 32 bit wide SD host controller register.
> 
> Fix :
> AccessMode bits [29:30] of OCR is a valid definition to calculate data 
> address for
> eMMC cards.
> 
> For SD cards, data address is calculated on the basis of card capacity status
> bit[30] of OCR.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal 
> ---
>  EmbeddedPkg/Universal/MmcDxe/Mmc.h|  2 ++
>  EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 21 -
>  2 files changed, 18 insertions(+), 5 deletions(-)
> 
> diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> index a77ba41..62de2c8 100644
> --- a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> +++ b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
> @@ -70,6 +70,8 @@
>  #define SD_HIGH_SPEED   5000
>  #define SWITCH_CMD_SUCCESS_MASK 0x0f00
> 
> +#define SD_CARD_CAPACITY0x0002
> +
>  #define BUSWIDTH_4  4
> 
>  typedef enum {
> diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> index a2b9232..1dea7d3 100644
> --- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> +++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> @@ -148,12 +148,23 @@ MmcTransferBlock (
>MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This);
>MmcHost = MmcHostInstance->MmcHost;
> 
> -  //Set command argument based on the card access mode (Byte mode or Block
> mode)
> -  if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> MMC_OCR_ACCESS_MASK) ==
> -  MMC_OCR_ACCESS_SECTOR) {
> -CmdArg = Lba;
> +  if (MmcHostInstance->CardInfo.CardType != EMMC_CARD) {
> +//Set command argument based on the card capacity
> +//if 0 : SDSC card
> +//if 1 : SDXC/SDHC
> +if (MmcHostInstance->CardInfo.OCRData.AccessMode &
> SD_CARD_CAPACITY) {
> +  CmdArg = Lba;
> +} else {
> +  CmdArg = Lba * This->Media->BlockSize;
> +}
>} else {
> -CmdArg = Lba * This->Media->BlockSize;
> +//Set command argument based on the card access mode (Byte mode or
> Block mode)
> +if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> MMC_OCR_ACCESS_MASK) ==
> +MMC_OCR_ACCESS_SECTOR) {
> +  CmdArg = Lba;
> +} else {
> +  CmdArg = Lba * This->Media->BlockSize;
> +}
>}
> 
>Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg);
> --
> 1.9.1

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[edk2] [PATCH v2] SD/eMMC : Fix Command Argument for SD/eMMC R/W operation.

[Meenakshi Aggarwal]

Issue : SD read failure for high capacity cards e.g. 64 GB
i
Reason : Command argument value exceeds 32 bit for block number 0x3787FFF
and cant be fit into 32 bit wide SD host controller register.

Fix :
AccessMode bits [29:30] of OCR is a valid definition to calculate
data address for eMMC cards.

For SD cards, data address is calculated on the basis of
card capacity status bit[30] of OCR.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 EmbeddedPkg/Universal/MmcDxe/Mmc.h|  2 ++
 EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 21 -
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h 
b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
index a77ba41..62de2c8 100644
--- a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
+++ b/EmbeddedPkg/Universal/MmcDxe/Mmc.h
@@ -70,6 +70,8 @@
 #define SD_HIGH_SPEED   5000
 #define SWITCH_CMD_SUCCESS_MASK 0x0f00
 
+#define SD_CARD_CAPACITY0x0002
+
 #define BUSWIDTH_4  4
 
 typedef enum {
diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c 
b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
index a2b9232..1dea7d3 100644
--- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
+++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
@@ -148,12 +148,23 @@ MmcTransferBlock (
   MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This);
   MmcHost = MmcHostInstance->MmcHost;
 
-  //Set command argument based on the card access mode (Byte mode or Block 
mode)
-  if ((MmcHostInstance->CardInfo.OCRData.AccessMode & MMC_OCR_ACCESS_MASK) ==
-  MMC_OCR_ACCESS_SECTOR) {
-CmdArg = Lba;
+  if (MmcHostInstance->CardInfo.CardType != EMMC_CARD) {
+//Set command argument based on the card capacity
+//if 0 : SDSC card
+//if 1 : SDXC/SDHC
+if (MmcHostInstance->CardInfo.OCRData.AccessMode & SD_CARD_CAPACITY) {
+  CmdArg = Lba;
+} else {
+  CmdArg = Lba * This->Media->BlockSize;
+}
   } else {
-CmdArg = Lba * This->Media->BlockSize;
+//Set command argument based on the card access mode (Byte mode or Block 
mode)
+if ((MmcHostInstance->CardInfo.OCRData.AccessMode & MMC_OCR_ACCESS_MASK) ==
+MMC_OCR_ACCESS_SECTOR) {
+  CmdArg = Lba;
+} else {
+  CmdArg = Lba * This->Media->BlockSize;
+}
   }
 
   Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg);
-- 
1.9.1

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Re: [edk2] [PATCH] SD/eMMC : Fix Command Argument for SD/eMMC R/W operation.

[Meenakshi Aggarwal]

Hi Jun, Haojian,

Please review the patch.

Thanks,
Meenakshi

> -Original Message-
> From: Leif Lindholm 
> Sent: Thursday, January 17, 2019 4:54 PM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Jun Nie
> ; Haojian Zhuang 
> Subject: Re: [PATCH] SD/eMMC : Fix Command Argument for SD/eMMC R/W
> operation.
> 
> Jun, Haojian - any comments?
> 
> On Wed, Jan 16, 2019 at 06:51:36PM +0530, Meenakshi Aggarwal wrote:
> > Issue : SD read failure for high capacity cards e.g. 64 GB i Reason :
> > Command argument value exceeds 32 bit for block number 0x3787FFF and
> > cant be fit into 32 bit wide SD host controller register.
> >
> > Fix :
> > AccessMode bits [29:30] of OCR is a valid definition to calculate data
> > address for eMMC cards.
> >
> > For SD cards, data address is calculated on the basis of card capacity
> > status bit[30] of OCR.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 19 ++-
> >  1 file changed, 14 insertions(+), 5 deletions(-)
> >
> > diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > index a2b9232..625a59e 100644
> > --- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > +++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
> > @@ -148,12 +148,21 @@ MmcTransferBlock (
> >MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This);
> >MmcHost = MmcHostInstance->MmcHost;
> >
> > -  //Set command argument based on the card access mode (Byte mode or
> > Block mode)
> > -  if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> MMC_OCR_ACCESS_MASK) ==
> > -  MMC_OCR_ACCESS_SECTOR) {
> > -CmdArg = Lba;
> > +  if (MmcHostInstance->CardInfo.CardType != EMMC_CARD) {
> > +//Set command argument based on the card capacity (SDSC or SDXC/SDHC)
> > +if (MmcHostInstance->CardInfo.OCRData.AccessMode & BIT1) {
> > +  CmdArg = Lba;
> > +} else {
> > +  CmdArg = Lba * This->Media->BlockSize;
> > +}
> >} else {
> > -CmdArg = Lba * This->Media->BlockSize;
> > +//Set command argument based on the card access mode (Byte mode or
> Block mode)
> > +if ((MmcHostInstance->CardInfo.OCRData.AccessMode &
> MMC_OCR_ACCESS_MASK) ==
> > +MMC_OCR_ACCESS_SECTOR) {
> > +  CmdArg = Lba;
> > +} else {
> > +  CmdArg = Lba * This->Media->BlockSize;
> > +}
> >}
> >
> >Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg);
> > --
> > 1.9.1
> >
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[edk2] [PATCH] SD/eMMC : Fix Command Argument for SD/eMMC R/W operation.

[Meenakshi Aggarwal]

Issue : SD read failure for high capacity cards e.g. 64 GB
i
Reason : Command argument value exceeds 32 bit for block number 0x3787FFF
and cant be fit into 32 bit wide SD host controller register.

Fix :
AccessMode bits [29:30] of OCR is a valid definition to calculate
data address for eMMC cards.

For SD cards, data address is calculated on the basis of
card capacity status bit[30] of OCR.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c 
b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
index a2b9232..625a59e 100644
--- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
+++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c
@@ -148,12 +148,21 @@ MmcTransferBlock (
   MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This);
   MmcHost = MmcHostInstance->MmcHost;
 
-  //Set command argument based on the card access mode (Byte mode or Block 
mode)
-  if ((MmcHostInstance->CardInfo.OCRData.AccessMode & MMC_OCR_ACCESS_MASK) ==
-  MMC_OCR_ACCESS_SECTOR) {
-CmdArg = Lba;
+  if (MmcHostInstance->CardInfo.CardType != EMMC_CARD) {
+//Set command argument based on the card capacity (SDSC or SDXC/SDHC)
+if (MmcHostInstance->CardInfo.OCRData.AccessMode & BIT1) {
+  CmdArg = Lba;
+} else {
+  CmdArg = Lba * This->Media->BlockSize;
+}
   } else {
-CmdArg = Lba * This->Media->BlockSize;
+//Set command argument based on the card access mode (Byte mode or Block 
mode)
+if ((MmcHostInstance->CardInfo.OCRData.AccessMode & MMC_OCR_ACCESS_MASK) ==
+MMC_OCR_ACCESS_SECTOR) {
+  CmdArg = Lba;
+} else {
+  CmdArg = Lba * This->Media->BlockSize;
+}
   }
 
   Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg);
-- 
1.9.1

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Re: [edk2] [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer

[Meenakshi Aggarwal]

Thank you Ard and Leif for all the comments, we  will work on your review 
comments and share the next version soon.

> -Original Message-
> From: Leif Lindholm 
> Sent: Saturday, December 22, 2018 12:48 AM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar ; Varun Sethi
> 
> Subject: Re: [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return
> Mmio APIs pointer
> 
> On Wed, Nov 28, 2018 at 08:31:15PM +0530, Meenakshi Aggarwal wrote:
> > This library add supports to return pointer to MMIO APIs on basis of
> > Swap flag.
> > If Flag is True then MMION APIs returened in which data swapped after
> > reading from MMIO and before write using MMIO.
> 
> I conspicuously left this one for last.
> 
> First thing I would like to see is splitting the setting up of function 
> pointers bit
> from the actual I/O accesses (separate patches).
> 
> The I/O functions belong in edk2 MdeModulePkg (or possibly EmbeddedPkg, of
> for some reason they don't want it in MdePkg).
> But regardless, please send that as a separate patch, preceding the edk2-
> platforms set.
> 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal 
> > ---
> >  Silicon/NXP/Include/Library/IoAccessLib.h   | 332 +++
> >  Silicon/NXP/Library/IoAccessLib/IoAccessLib.c   | 410
> 
> >  Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf |  32 ++
> >  3 files changed, 774 insertions(+)
> >  create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> >  create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> >  create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> >
> > diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h
> > b/Silicon/NXP/Include/Library/IoAccessLib.h
> > new file mode 100644
> > index 000..f7372a5
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/IoAccessLib.h
> > @@ -0,0 +1,332 @@
> > +/** @file
> > + *
> > + *  Copyright 2017 NXP
> > + *
> > + *  This program and the accompanying materials
> > + *  are licensed and made available under the terms and conditions of
> > +the BSD License
> > + *  which accompanies this distribution.  The full text of the
> > +license may be found at
> > + *
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.phpdata=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7C7d85cd38d02e4e6bbdc208d6677905c6%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636810166817008412sdata=OU
> EJ2URy5
> > +LX7wpvNs9f%2BK01Q1nahX2nWPNO67yOT57M%3Dreserved=0
> > + *
> > + *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > + *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > + *
> > + **/
> > +
> > +#ifndef __IO_ACCESS_LIB_H__
> > +#define __IO_ACCESS_LIB_H__
> > +
> > +#include 
> > +
> > +///
> > +///  Structure to have pointer to R/W ///  Mmio operations for 16
> > +bits.
> > +///
> > +typedef struct _MMIO_OPERATIONS_16 {
> > +  UINT16 (*Read) (UINTN Address);
> > +  UINT16 (*Write) (UINTN Address, UINT16 Value);
> > +  UINT16 (*Or) (UINTN Address, UINT16 Or);
> > +  UINT16 (*And) (UINTN Address, UINT16 AND);
> > +  UINT16 (*AndThenOr) (UINTN Address, UINT16 And, UINT16 Or); }
> > +MMIO_OPERATIONS_16;
> 
> I have sort of hinted at this in earlier comments on this set:
> 
> Why separate structs for different access sizes?
> I don't expect there will be a noticeable image size or performance 
> difference if
> they are all put into one structure. And if there is. we can conditionalise 
> the
> inclusion of different widths with FixedPcds.
> 
> So I would like for just a single GetMmioOperations() function that returns a
> single struct. And I would like for the member functions to have the access 
> size
> as the suffix to their names, just like the regular IoLib functions.
> 
> > +
> > +///
> > +///  Structure to have pointer to R/W ///  Mmio operations for 32
> > +bits.
> > +///
> > +typedef struct _MMIO_OPERATIONS_32 {
> > +  UINT32 (*Read) (UINTN Address);
> > +  UINT32 (*Write) (UINTN Address, UINT32 Value);
> > +  UINT32 (*Or) (UINTN Address, UINT32 Or);
> > +  UINT32 (*And) (UINTN Address, UINT32 AND);
> > +  UINT32 (*AndThenOr) (UINTN Address, UINT32 And, UINT32 Or); }
> > +MMIO_OPER

[edk2] EmbeddedPkg : Corrected flow for setting Buswidth for eMMC

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c 
b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
index f661a0c..9118eb2 100755
--- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
+++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
@@ -309,11 +309,14 @@ InitializeEmmcDevice (
   }
   Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus 
width, Status:%r\n", Status));
+continue;
+  } else {
+DEBUG ((DEBUG_INFO, "InitializeEmmcDevice(): Set EXTCSD bus width %d 
successfully\n", BusMode));
+break;
   }
-  return Status;
 }
   }
+
   return Status;
 }
 
-- 
1.9.1

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[edk2] [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB

[Meenakshi Aggarwal]

From: Vabhav 

Compilation: Update the fdf, dsc and dec files.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc| 17 +
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf|  7 +++
 .../Library/PlatformLib/ArmPlatformLib.inf  |  2 ++
 .../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c   |  6 ++
 Silicon/NXP/LS2088A/LS2088A.dsc.inc |  3 +++
 5 files changed, 35 insertions(+)

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index e074991..aefc214 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -43,6 +43,8 @@
   BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
   FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
   NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+  PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+  PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
 
 [PcdsFixedAtBuild.common]
 
@@ -92,6 +94,13 @@
   gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x58000
   gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x58030
 
+  #
+  # PCI PCDs.
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x8
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
+
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -111,3 +120,11 @@
   Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
   Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
   Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+  Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 62f084d..d32c5a0 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -129,6 +129,13 @@ READ_LOCK_STATUS   = TRUE
   INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
 
   #
+  # PCI
+  #
+  INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
   # Network modules
   #
   INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f5e5abd..0b836a8 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -44,6 +44,8 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCore
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdRomSize
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c 
b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index ccb49f6..8b2145b 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdCcsrSize);
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // ROM Space
+  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdRomSize);
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   // IFC region 1
   //
   // A-009241   : Unaligned write transactions to IFC may result in corruption 
of data
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc 
b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 0d8fd82..831edea 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -69,5 +69,8 @@
   gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
   gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0224
   gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
+  gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
+  gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x
+  gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0010
 
 ##
-- 
1.9.1

[edk2] [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB

[Meenakshi Aggarwal]

From: Vabhav 

Compilation: Update the fdf, dsc and dec files.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc  | 15 +++
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf  |  7 +++
 .../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf  |  2 ++
 .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c |  6 ++
 Silicon/NXP/LS1046A/LS1046A.dsc.inc   |  3 +++
 5 files changed, 33 insertions(+)

diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
index 7eb08a9..57f2043 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -41,6 +41,8 @@
   IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
   BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
   FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+  PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+  PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
 
 [PcdsFixedAtBuild.common]
 
@@ -65,6 +67,7 @@
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
   gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
   gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
 
   #
   # RTC Pcds
@@ -72,6 +75,12 @@
   gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
   gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|10
 
+  #
+  # PCI PCDs.
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x8
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -85,6 +94,12 @@
 
   Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
   Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+  Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
 
   Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
  ##
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
index 443b561..887f386 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -124,6 +124,13 @@ READ_LOCK_STATUS   = TRUE
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
+  # PCI
+  #
+  INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
   # Network modules
   #
   INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 49b57fc..5e09757 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -42,6 +42,8 @@
   gArmTokenSpaceGuid.PcdArmPrimaryCore
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdRomSize
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
   gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdCcsrSize);
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // ROM Space
+  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdRomSize);
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   // IFC region 1
   //
   // A-009241   : Unaligned write transactions to IFC may result in corruption 
of data
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 9f87028..59a6150 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -64,5 +64,8 @@
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x4000
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x2000
   gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr

[edk2] [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver.

[Meenakshi Aggarwal]

Add support of DWC3 controller driver which
Performs DWC3 controller initialization and
Register itself as NonDiscoverableMmioDevice

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c   | 218 +++
 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h   | 144 ++
 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf |  48 ++
 Silicon/NXP/NxpQoriqLs.dec   |   5 +
 4 files changed, 415 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
 create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
 create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf

diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c 
b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
new file mode 100644
index 000..0a9c821
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
@@ -0,0 +1,218 @@
+/** @file
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+
+#include "UsbHcd.h"
+
+STATIC
+VOID
+XhciSetBeatBurstLength (
+  IN  UINTN  UsbReg
+  )
+{
+  DWC3   *Dwc3Reg;
+
+  Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+  MmioAndThenOr32 ((UINTN)>GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
+  USB3_ENABLE_BEAT_BURST);
+  MmioOr32 ((UINTN)>GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
+
+  return;
+}
+
+STATIC
+VOID
+Dwc3SetFladj (
+  IN  DWC3   *Dwc3Reg,
+  IN  UINT32 Val
+  )
+{
+  MmioOr32 ((UINTN)>GFLAdj, GFLADJ_30MHZ_REG_SEL |
+GFLADJ_30MHZ(Val));
+}
+
+VOID
+Dwc3SetMode (
+  IN  DWC3   *Dwc3Reg,
+  IN  UINT32 Mode
+  )
+{
+  MmioAndThenOr32 ((UINTN)>GCtl,
+   ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+   DWC3_GCTL_PRTCAPDIR(Mode));
+}
+
+STATIC
+VOID
+Dwc3CoreSoftReset (
+  IN  DWC3   *Dwc3Reg
+  )
+{
+  MmioOr32 ((UINTN)>GCtl, DWC3_GCTL_CORESOFTRESET);
+  MmioOr32 ((UINTN)>GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+  MmioOr32 ((UINTN)>GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GCtl, ~DWC3_GCTL_CORESOFTRESET);
+
+  return;
+}
+
+STATIC
+EFI_STATUS
+Dwc3CoreInit (
+  IN  DWC3   *Dwc3Reg
+  )
+{
+  UINT32 Revision;
+  UINT32 Reg;
+  UINTN  Dwc3Hwparams1;
+
+  Revision = MmioRead32 ((UINTN)>GSnpsId);
+  //
+  // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision 
number
+  //
+  if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) {
+DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
+return EFI_NOT_FOUND;
+  }
+
+  Dwc3CoreSoftReset (Dwc3Reg);
+
+  Reg = MmioRead32 ((UINTN)>GCtl);
+  Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+  Reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
+  Dwc3Hwparams1 = MmioRead32 ((UINTN)>GHwParams1);
+
+  if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == 
DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
+Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+  } else {
+DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
+  }
+
+  if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
+Reg |= DWC3_GCTL_U2RSTECN;
+  }
+
+  MmioWrite32 ((UINTN)>GCtl, Reg);
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+XhciCoreInit (
+  IN  UINTN  UsbReg
+  )
+{
+  EFI_STATUS Status;
+  DWC3   *Dwc3Reg;
+
+  Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+  Status = Dwc3CoreInit (Dwc3Reg);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
+  UsbReg, Status));
+return Status;
+  }
+
+  Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
+
+  Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
+
+  return Status;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+InitializeUsbController (
+  IN  UINTN  UsbReg
+  )
+{
+  EFI_STATUS Status;
+
+  Status = XhciCoreInit (UsbReg);
+
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  //
+  // Change beat burst and outstanding pipelined transfers requests
+  //
+  XhciSetBeatBurstLength (UsbReg);
+
+  return Status;
+}
+
+/**
+  The Entry Point of module. It follows the standard UEFI driver model.
+
+  @param[in] ImageHandle   The firmware allocated handle for the EFI image.
+  @param[in] SystemTable   A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS  The entry point is executed successfully.
+  @retval other   

[edk2] [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller

[Meenakshi Aggarwal]

Enable support of USB drives on ls2088 board.
LS2088 has DWC3 controller

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc |  1 +
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +
 Platform/NXP/NxpQoriqLs.dsc.inc  | 12 
 Silicon/NXP/LS2088A/LS2088A.dsc.inc  |  1 +
 4 files changed, 27 insertions(+)

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index e788581..e074991 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -110,3 +110,4 @@
   Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
   Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
   Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+  Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 61bb160..62f084d 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -153,6 +153,19 @@ READ_LOCK_STATUS   = TRUE
   INF  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
 !endif
 
+  INF 
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # USB Support
+  #
+  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
   #
   # FAT filesystem + GPT/MBR partitioning
   #
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 063d0b8..3236b02 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -100,6 +100,7 @@
   VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
   NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
 
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -368,6 +369,17 @@
 !endif
 
   #
+  # USB Support
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
   # FAT filesystem + GPT/MBR partitioning
   #
   MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc 
b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 2cff40f..0d8fd82 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -68,5 +68,6 @@
   gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x1
   gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
   gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0224
+  gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
 
 ##
-- 
1.9.1

___
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[edk2] [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files.

[Meenakshi Aggarwal]

LS1043A PCIe compilation and update firmware device,
description and declaration files.Defining Embedded Package
PCD which should be at least 20 for 64K PCIe IO size required
for CPU hob during PEI phase to Add IO space post PEI phase.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf |  7 +++
 .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf |  2 ++
 .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c|  6 ++
 Platform/NXP/NxpQoriqLs.dsc.inc  |  2 ++
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  |  4 
 Silicon/NXP/NxpQoriqLs.dec   | 10 ++
 7 files changed, 47 insertions(+)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index b69ffa2..b43c81a 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -42,6 +42,8 @@
   BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
   FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
   NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+  PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+  PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
 
 [PcdsFixedAtBuild.common]
 
@@ -74,6 +76,13 @@
   gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x06000
   gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x6030
 
+  #
+  # PCI PCDs.
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x1
+  gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
+
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -94,4 +103,11 @@
   Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
   Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
 
+  Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
  ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 6b27aed..d02b3cc 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -131,6 +131,13 @@ READ_LOCK_STATUS   = TRUE
   INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
 
   #
+  # PCI
+  #
+  INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  #
   # Network modules
   #
   INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 7feac56..f2c8b66 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -65,3 +65,5 @@
   gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+  gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdRomSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c 
b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdCcsrSize);
   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // ROM Space
+  VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].VirtualBase  = FixedPcdGet64 (PcdRomBaseAddr);
+  VirtualMemoryTable[Index].Length   = FixedPcdGet64 (PcdRomSize);
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   // IFC region 1
   //
   // A-009241   : Unaligned write transactions to IFC may result in corruption 
of data
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 5529a04..063d0b8 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -245,6 +245,8 @@
 
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
 
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
+
   #
   # Optional feature to help prevent EFI memory map fragments
   # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
diff --git

[edk2] [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL

[Meenakshi Aggarwal]

From: Vabhav 

NXP SOC has mutiple PCIe RCs,Adding respective implementation of
EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
used by generic Host Bridge Driver including correct value for
the translation offset during MMIO accesses

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c   | 633 ++
 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf |  49 ++
 2 files changed, 682 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
 create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf

diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c 
b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 000..b5c175b
--- /dev/null
+++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,633 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+  Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.
+  Copyright 2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_IO_PORT_ADDRESS PCI_SEG_PORTIO_LIMIT
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is 
responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
+  @param[in] Width  Signifies the width of the I/O or Memory operation.
+  @param[in] AddressThe base address of the I/O operation.
+  @param[in] Count  The number of I/O operations to perform. The 
number of
+bytes moved is Width size * Count, starting at 
Address.
+  @param[in] Buffer For read operations, the destination buffer to 
store the results.
+For write operations, the source buffer from which 
to write data.
+
+  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEANMmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64 Address,
+  IN UINTN  Count,
+  IN VOID   *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ASSERT (FALSE);
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+Count = 

[edk2] [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support

[Meenakshi Aggarwal]

From: Vabhav 

Implement the library that exposes the PCIe root complexes to the
generic PCI host bridge driver,Putting SoC Specific low level init
code for the RCs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
---
 .../Library/PciHostBridgeLib/PciHostBridgeLib.c| 639 +
 .../Library/PciHostBridgeLib/PciHostBridgeLib.inf  |  51 ++
 2 files changed, 690 insertions(+)
 create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
 create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c 
b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 000..a543d7d
--- /dev/null
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,639 @@
+/** @file
+  PCI Host Bridge Library instance for NXP SoCs
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack(1)
+typedef struct {
+  ACPI_HID_DEVICE_PATH AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  PCI_SEG0_NUM
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  },
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  PCI_SEG1_NUM
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  },
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  PCI_SEG2_NUM
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  },
+  {
+{
+  {
+ACPI_DEVICE_PATH,
+ACPI_DP,
+{
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+  (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+}
+  },
+  EISA_PNP_ID (0x0A08), // PCI Express
+  PCI_SEG3_NUM
+},
+
+{
+  END_DEVICE_PATH_TYPE,
+  END_ENTIRE_DEVICE_PATH_SUBTYPE,
+  {
+END_DEVICE_PATH_LENGTH,
+0
+  }
+}
+  }
+};
+
+STATIC
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+  L"Mem", L"I/O", L"Bus"
+};
+
+#define PCI_ALLOCATION_ATTRIBUTES   EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
\
+EFI_PCI_HOST_BRIDGE_MEM64_DECODE
+
+#define PCI_SUPPORT_ATTRIBUTES  EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
+EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | 
\
+EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+EFI_PCI_ATTRIBUTE_VGA_IO_16  | \
+EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
+
+PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER];
+
+/**
+  Function to set-up iATU outbound window for PCIe controller
+
+  @param Dbi Address of PCIe host controller.
+  @param Idx Index of iATU outbound window.
+  @param TypeType(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
+  @param PhysPCIe controller phy address for outbound window.
+  @param BusAdr  PCIe controller bus address for outbound window.
+  @param PcieSize of PCIe controller space(Cfg0/Cfg1/Mem/IO).
+
+**/
+STATIC
+VOID
+PcieIatuOutboundSet (
+  IN EFI_PHYSICAL_ADDRESS Dbi,
+  IN UINT32 Idx,
+  IN UINT32 Type,
+  IN UINT64 Phys,
+  IN UINT64 BusAddr,
+  IN UINT64 Size
+  )
+{
+  MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
+  (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
+  MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
+  

[edk2] [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs

[Meenakshi Aggarwal]

From: Vabhav 

Multiple root complex support is not provided by standard library
PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
function for reading/writing into PCIe configuration Space.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/NxpPcie.h  | 146 +
 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c  | 611 +
 .../NXP/Library/PciSegmentLib/PciSegmentLib.inf|  41 ++
 3 files changed, 798 insertions(+)
 create mode 100644 Silicon/NXP/Include/NxpPcie.h
 create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
 create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf

diff --git a/Silicon/NXP/Include/NxpPcie.h b/Silicon/NXP/Include/NxpPcie.h
new file mode 100644
index 000..a0beefe
--- /dev/null
+++ b/Silicon/NXP/Include/NxpPcie.h
@@ -0,0 +1,146 @@
+/** @file
+  PCI memory configuration for NXP
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NXP_PCIE_H__
+#define __NXP_PCIE_H__
+
+// Segment 0
+#define PCI_SEG0_NUM  0
+#define PCI_SEG0_MMIO32_MIN   0x4000
+#define PCI_SEG0_MMIO32_MAX   0x4fff
+#define PCI_SEG0_MMIO64_MIN   PCI_SEG0_MMIO_MEMBASE + \
+  SEG_MEM_SIZE + \
+  MEM64_BASE
+#define PCI_SEG0_MMIO64_MAX   PCI_SEG0_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
+#define PCI_SEG0_DBI_BASE 0x0340
+#define PCI_SEG0_MMIO_OFFSET  0x0
+#define PCI_SEG0_PORTIO_MEMBASE   PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG0_PORTIO_OFFSET0x0
+
+// Segment 1
+#define PCI_SEG1_NUM  1
+#define PCI_SEG1_MMIO32_MIN   0x4000
+#define PCI_SEG1_MMIO32_MAX   0x4fff
+#define PCI_SEG1_MMIO64_MIN   PCI_SEG1_MMIO_MEMBASE + \
+  SEG_MEM_SIZE + \
+  MEM64_BASE
+#define PCI_SEG1_MMIO64_MAX   PCI_SEG1_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
+#define PCI_SEG1_DBI_BASE 0x0350
+#define PCI_SEG1_MMIO_OFFSET  0x1000
+#define PCI_SEG1_PORTIO_MEMBASE   PCI_SEG1_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG1_PORTIO_OFFSET0x1
+
+// Segment 2
+#define PCI_SEG2_NUM  2
+#define PCI_SEG2_MMIO32_MIN   0x4000
+#define PCI_SEG2_MMIO32_MAX   0x4fff
+#define PCI_SEG2_MMIO64_MIN   PCI_SEG2_MMIO_MEMBASE + \
+  SEG_MEM_SIZE + \
+  MEM64_BASE
+#define PCI_SEG2_MMIO64_MAX   PCI_SEG2_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
+#define PCI_SEG2_DBI_BASE 0x0360
+#define PCI_SEG2_MMIO_OFFSET  0x2000
+#define PCI_SEG2_PORTIO_MEMBASE   PCI_SEG2_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG2_PORTIO_OFFSET0x2
+
+// Segment 3
+#define PCI_SEG3_NUM  3
+#define PCI_SEG3_MMIO32_MIN   0x4000
+#define PCI_SEG3_MMIO32_MAX   0x4fff
+#define PCI_SEG3_MMIO64_MIN   PCI_SEG3_MMIO_MEMBASE + \
+  SEG_MEM_SIZE + \
+  MEM64_BASE
+#define PCI_SEG3_MMIO64_MAX   PCI_SEG3_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
+#define PCI_SEG3_DBI_BASE 0x0370
+#define PCI_SEG3_MMIO_OFFSET  0x3000
+#define PCI_SEG3_PORTIO_MEMBASE   PCI_SEG3_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG3_PORTIO_OFFSET0x3
+
+// Segment configuration
+#define PCI_SEG_BUSNUM_MIN0x0
+#define PCI_SEG_BUSNUM_MAX0xff
+#define PCI_SEG_PORTIO_MIN0x0
+#define PCI_SEG_PORTIO_MAX0x
+#define PCI_SEG_MMIO32_MIN0x4000
+#define PCI_SEG_MMIO32_MAX0x4fff
+#define PCI_SEG_MMIO32_DIFF   0x1000
+#define PCI_SEG_MMIO64_MAX_DIFF   0x3fff
+#define SEG_CFG_SIZE  0x1000
+#define SEG_CFG_BUS   0x
+#define SEG_MEM_SIZE  0x4000
+#define SEG_MEM_LIMIT 0x7fff
+#define SEG_MEM_BUS   0x4000
+#define SEG_IO_SIZE   0x0001
+#define SEG_IO_BUS0x
+#define PCI_SEG_PORTIO_LIMIT  (NUM_PCIE_CONTROLLER * SEG_IO_SIZE) + \
+  PCI_SEG_PORTIO_MAX
+#define PCI_BASE_DIFF 0x8
+#define PCI_DBI

[edk2] [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support

[Meenakshi Aggarwal]

From: Wasim Khan 

Add Maxim DS3232 RTC Library support

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h |  49 +++
 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c  | 420 +
 .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec|  34 ++
 .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf|  50 +++
 4 files changed, 553 insertions(+)
 create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
 create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
 create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
 create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf

diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h 
b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
new file mode 100644
index 000..cd1a321
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
@@ -0,0 +1,49 @@
+/** Ds3232Rtc.h
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __DS3232RTC_H__
+#define __DS3232RTC_H__
+
+//RTC time register
+#define DS3232_SEC_REG_ADDR0x00
+#define DS3232_MIN_REG_ADDR0x01
+#define DS3232_HR_REG_ADDR 0x02
+#define DS3232_DAY_REG_ADDR0x03
+#define DS3232_DATE_REG_ADDR   0x04
+#define DS3232_MON_REG_ADDR0x05
+#define DS3232_YR_REG_ADDR 0x06
+
+#define DS3232_SEC_BIT_CH  0x80  // Clock Halt (in Register 0)
+
+//RTC control register
+#define DS3232_CTL_REG_ADDR0x0e
+#define DS3232_STAT_REG_ADDR   0x0f
+
+#define START_YEAR 1970
+#define END_YEAR   2070
+
+//TIME MASKS
+#define MASK_SEC   0x7F
+#define MASK_MIN   0x7F
+#define MASK_HOUR  0x3F
+#define MASK_DAY   0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+  UINTN   OperationCount;
+  EFI_I2C_OPERATION   SetAddressOp;
+  EFI_I2C_OPERATION   GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS3232RTC_H__
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c 
b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
new file mode 100644
index 000..3ab94a8
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
@@ -0,0 +1,420 @@
+/** Ds3232RtcLib.c
+*  Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
+*
+*  Based on RTC implementation available in
+*  EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+*
+*  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Ds3232Rtc.h"
+
+STATIC VOID   *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL*mI2cMaster;
+
+/**
+  Read RTC register.
+
+  @param  SlaveDeviceAddress   Slave device address offset of RTC to be read.
+  @param  RtcRegAddr   Register offset of RTC to be read.
+
+  @retval  Register Value read
+
+**/
+STATIC
+UINT8
+RtcRead (
+  IN  UINT8SlaveDeviceAddress,
+  IN  UINT8RtcRegAddr
+  )
+{
+  RTC_I2C_REQUEST  Req;
+  EFI_STATUS   Status;
+  UINT8Val;
+
+  Val = 0;
+
+  Req.OperationCount = 2;
+
+  Req.SetAddressOp.Flags = 0;
+  Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+  Req.SetAddressOp.Buffer = 
+
+  Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+  Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+  Req.GetSetDateTimeOp.Buffer = 
+
+  Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *),
+ NULL,  NULL);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+  }
+
+  return Val;
+}
+
+/**
+  Write RTC register.
+
+  @param  Slave

[edk2] [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files

[Meenakshi Aggarwal]

The firmware device, description and declaration files for LS2088 board

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec |  29 
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc |  96 +
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 200 +++
 Silicon/NXP/LS2088A/LS2088A.dec  |  22 +++
 Silicon/NXP/LS2088A/LS2088A.dsc.inc  |  71 ++
 Silicon/NXP/NxpQoriqLs.dec   |  13 ++
 6 files changed, 431 insertions(+)
 create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
 create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
 create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
 create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
 create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc.inc

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
new file mode 100644
index 000..93d2e5a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
@@ -0,0 +1,29 @@
+#  LS2088aRdbPkg.dec
+#  LS2088a board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available 
under
+#  the terms and conditions of the BSD License which accompanies this 
distribution.
+#  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+[Defines]
+  PACKAGE_NAME   = LS2088aRdbPkg
+  PACKAGE_GUID   = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
new file mode 100755
index 000..465c59e
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -0,0 +1,96 @@
+#  LS2088aRdbPkg.dsc
+#
+#  LS2088ARDB Board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS2088aRdbPkg
+  PLATFORM_GUID  = be06d8bc-05eb-44d6-b39f-191e93617ebd
+  OUTPUT_DIRECTORY   = Build/LS2088aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+  DEFINE MC_HIGH_MEM = TRUE
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS2088A/LS2088A.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
+  
ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+  
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+  IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+  RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+!if $(MC_HIGH_MEM) == TRUE# Management 
Complex loaded at the end of DDR2
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x008000 # Actual 
base address (0x008000)
+  gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x008000 # 2 GB
+  gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x8000  # 2GB 
(PcdDpaa2McRamSize must be 512MB aligned)
+  gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x008000 # Actual base
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x008000

[edk2] [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services

[Meenakshi Aggarwal]

Enable NOR driver and Runtime Services for LS2088ARDB Platform

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 -
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf |  6 +-
 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc  | 99 
 3 files changed, 118 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 76d51a2..e788581 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -42,6 +42,7 @@
   IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
   BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
   FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
+  NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
 
 [PcdsFixedAtBuild.common]
 
@@ -84,6 +85,13 @@
   gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
   gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
 
+  #
+  # NV Storage PCDs
+  #
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x58000
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x58030
+
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -93,7 +101,12 @@
   #
   # Architectural Protocols
   #
-  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
+ 
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
   Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
   Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+  Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index b526be1..61bb160 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -55,6 +55,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
@@ -103,7 +104,8 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
   INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
-  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
   INF Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -124,6 +126,8 @@ READ_LOCK_STATUS   = TRUE
   INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
+  INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
   #
   # Network modules
   #
diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 000..7d35042
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,99 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017-2018 NXP.
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+##
+
+[FD.LS2088aRdbNv_EFI]
+
+BaseAddress = 0x58030|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base 
address of the FLASH device
+Size = 0x000C|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of 
the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VAR

[edk2] [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 .../Drivers/PlatformDxe/PlatformDxe.c  | 119 +
 .../Drivers/PlatformDxe/PlatformDxe.inf|  58 ++
 2 files changed, 177 insertions(+)
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
 create mode 100644 
Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf

diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c 
b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 000..667e750
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+  LS2088 RDB board DXE platform driver.
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+  UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+  IN  EFI_GUID*TypeGuid,
+  IN  ADDRESS_SPACE_DESCRIPTOR*Desc,
+  OUT EFI_HANDLE  *Handle
+  )
+{
+  NON_DISCOVERABLE_DEVICE *Device;
+  EFI_STATUS  Status;
+
+  Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+  if (Device == NULL) {
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  Device->Type = TypeGuid;
+  Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+  Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+  , Device,
+  NULL);
+  if (EFI_ERROR (Status)) {
+goto FreeDevice;
+  }
+  return EFI_SUCCESS;
+
+FreeDevice:
+  FreePool (Device);
+
+  return Status;
+}
+
+VOID
+PopulateI2cInformation (
+  IN VOID
+  )
+{
+  UINT32 Index;
+
+  for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) 
- 3;
+mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+mI2cDesc[Index].StartDesc.GenFlag = 0;
+mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 
(PcdI2cSize));
+mI2cDesc[Index].StartDesc.AddrRangeMax = 
mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+  }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  Handle = NULL;
+
+  PopulateI2cInformation ();
+
+  Status = RegisterDevice (,
+ [0], );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Install the DS3232 I2C Master protocol on this handle so the RTC driver
+  // can identify it as the I2C master it can invoke directly.
+  //
+  Status = gBS->InstallProtocolInterface (,
+  ,
+  EFI_NATIVE_INTERFACE, NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf 
b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 000..1972022
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  Component description file for LS2088 DXE platform driver.
+#
+#  Copyright 2018 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION   

[edk2] [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB

[Meenakshi Aggarwal]

From: Wasim Khan 

Add support of ArmPlatformLib for NXP LS2088ARDB board

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 .../Library/PlatformLib/ArmPlatformLib.c   | 106 
 .../Library/PlatformLib/ArmPlatformLib.inf |  77 +
 .../Library/PlatformLib/NxpQoriqLsHelper.S |  35 
 .../Library/PlatformLib/NxpQoriqLsMem.c| 189 +
 4 files changed, 407 insertions(+)
 create mode 100644 
Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 
Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 
Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 000..90f14ba
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+*  Contains board initialization functions.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+
+extern VOID SocInit (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Placeholder for Platform Initialization
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN   MpId
+  )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  *CoreCount= sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+  *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof (gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+  IN UINTN MpId
+  )
+{
+  return 1;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000..f5e5abd
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,77 @@
+#/**  @file
+#
+#  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#**/
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = d1361285-8a47-421c-9efd-6b262c9093fc
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  SocLib
+
+[Sources.common]
+  ArmPlatformLib.c
+  NxpQoriqLsHelper.S| GCC
+  NxpQoriqLsMem.c
+
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gNxpQoriqLsTokenSpace

[edk2] [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library

[Meenakshi Aggarwal]

From: Wasim Khan 

Library to provide board specific timings for LS2088ARDB
board with interfacing to IFC controller for accessing
NOR, NAND and FPGA.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Reviewed-by: Leif Lindholm 
---
 .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h   | 114 +
 .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c  |  69 +
 .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf|  28 +
 3 files changed, 211 insertions(+)
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf

diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h 
b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 000..174a242
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,114 @@
+/** IfcBoardSpecificLib.h
+
+  IFC Flash Board Specific Macros and structure
+
+  Copyright 2017-2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include 
+
+// On board flash support
+#define IFC_NAND_BUF_BASE0x53000ULL
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CSIFC_CS0
+#define IFC_NAND_CS   IFC_CS2
+#define IFC_FPGA_CS   IFC_CS3
+
+
+/* board-specific NAND timing */
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \
+   IFC_FTIM0_NAND_TWP(0x30)   | \
+   IFC_FTIM0_NAND_TWCHT(0x0e) | \
+   IFC_FTIM0_NAND_TWH(0x14))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \
+   IFC_FTIM1_NAND_TWBE(0xab)  | \
+   IFC_FTIM1_NAND_TRR(0x1c)   | \
+   IFC_FTIM1_NAND_TRP(0x30))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \
+   IFC_FTIM2_NAND_TREH(0x14) | \
+   IFC_FTIM2_NAND_TWHRE(0x3c))
+
+#define NAND_FTIM3 0x0
+
+#define IFC_NAND_BASE_PHYS0x3000
+#define NAND_CSPR  (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \
+   | IFC_CSPR_PORT_SIZE_8 \
+   | IFC_CSPR_MSEL_NAND \
+   | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT  0x0
+#define NAND_AMASK 0x
+
+#define NAND_CSOR  (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+   | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+   | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+   | IFC_CSOR_NAND_RAL_3   /* RAL = 3 Bytes */ \
+   | IFC_CSOR_NAND_PGS_4K  /* Page Size = 4K */ \
+   | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+   | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0  (IFC_FTIM0_NOR_TACSE(0x4) | \
+   IFC_FTIM0_NOR_TEADC(0x5) | \
+   IFC_FTIM0_NOR_TEAHC(0x5))
+
+#define NOR_FTIM1  (IFC_FTIM1_NOR_TACO(0x35) | \
+   IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \
+   IFC_FTIM1_NOR_TSEQRAD_NOR(0x13))
+
+#define NOR_FTIM2  (IFC_FTIM2_NOR_TCS(0x4) | \
+   IFC_FTIM2_NOR_TCH(0x4) | \
+   IFC_FTIM2_NOR_TWPH(0xe) | \
+   IFC_FTIM2_NOR_TWP(0x1c))
+
+#define NOR_FTIM3  0x0400
+
+#define IFC_FLASH_BASE_PHYS   0x8000
+#define NOR_CSPR   (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \
+   | IFC_CSPR_PORT_SIZE_16 \
+   | IFC_CSPR_MSEL_NOR\
+   | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT   0x0
+#define NOR_AMASK  IFC_AMASK(128*1024*1024)
+#define NOR_CSOR   IFC_CSOR_NOR_ADM_SHIFT(12)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x2000
+#define FPGA_CSPR_EXT  0x0
+#define FPGA_CSPR  (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+   IFC_CSPR_PORT_SIZE_8 | \
+   IFC_CSPR_MSEL_GPCM | \
+   IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR  IFC_CSOR_NOR_ADM_SHIFT(12)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \
+   IFC_FTIM0_GPCM_TEADC(0xe) | \
+   IFC_FTIM0_GPCM_TEAHC(0xe))
+
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+   

[edk2] [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library

[Meenakshi Aggarwal]

From: Wasim Khan 

Library to provide functions for accessing FPGA
on LS2088ARDB board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
---
 .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h| 166 +
 .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c| 115 ++
 .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf  |  31 
 3 files changed, 312 insertions(+)
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
 create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf

diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h 
b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
new file mode 100644
index 000..84d1f02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
@@ -0,0 +1,166 @@
+/** FpgaLib.h
+*  Header defining the LS2088a Fpga specific constants (Base addresses, sizes, 
flags)
+*
+*  Copyright 2017-2018 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __LS2088A_FPGA_H__
+#define __LS2088A_FPGA_H__
+
+typedef enum {
+  CLK_66,
+  CLK_83,
+  CLK_100,
+  CLK_125,
+  CLK_133
+} SYSTEM_CLOCK;
+
+/*
+ * FPGA register set of LS2088ARDB board-specific.
+ */
+typedef struct {
+  UINT8 Id;   // ID value uniquely identifying each QorIQ board type
+  UINT8 Arch; // Board Version
+  UINT8 Ver;  // FPGA Version
+  UINT8 Model;// Programming Model
+  UINT8 Minor;// Minor Revision Number
+  UINT8 CtlSys;
+  UINT8 Aux;
+  UINT8 ClkSpd;
+  UINT8 StatDut;
+  UINT8 StatSys;
+  UINT8 StatAlrm;
+  UINT8 Present;
+  UINT8 Present2;
+  UINT8 RcwCtl;
+  UINT8 CtlLed;
+  UINT8 I2cBlk;
+  UINT8 RcfgCtl;
+  UINT8 RcfgSt;
+  UINT8 DcmAd;
+  UINT8 DcmDa;
+  UINT8 Dcmd;
+  UINT8 Dmsg;
+  UINT8 Gdc;
+  UINT8 Gdd;
+  UINT8 Dmack;
+  UINT8 Res1[6];
+  UINT8 Watch;
+  UINT8 PwrCtl[2];
+  UINT8 Res2[2];
+  UINT8 PwrStat[4];
+  UINT8 Res3[8];
+  UINT8 ClkSpd2[2];
+  UINT8 Res4[2];
+  UINT8 Sclk[3];
+  UINT8 Res5;
+  UINT8 Dclk[3];
+  UINT8 Res6;
+  UINT8 ClkDspd[3];
+  UINT8 Res7;
+  UINT8 RstCtl;
+  UINT8 RstStat;
+  UINT8 RstRsn;
+  UINT8 RstFrc[2];
+  UINT8 Res8[11];
+  UINT8 BrdCfg[16];
+  UINT8 DutCfg[16];
+  UINT8 RcwAd[2];
+  UINT8 RcwData;
+  UINT8 Res9[5];
+  UINT8 PostCtl;
+  UINT8 PostStat;
+  UINT8 PostDat[2];
+  UINT8 Pid[4];
+  UINT8 GpioIo[4];
+  UINT8 GpioDir[4];
+  UINT8 Res10[20];
+  UINT8 RjtagCtl;
+  UINT8 RjtagDat;
+  UINT8 Res11[2];
+  UINT8 TrigSrc[4];
+  UINT8 TrigDst[4];
+  UINT8 TrigStat;
+  UINT8 Res12[3];
+  UINT8 TrigCtr[4];
+  UINT8 Res13[16];
+  UINT8 ClkFreq[6];
+  UINT8 ResC6[8];
+  UINT8 ClkBase[2];
+  UINT8 ResD0[8];
+  UINT8 Cms[2];
+  UINT8 ResC0[6];
+  UINT8 Aux2[4];
+  UINT8 Res14[10];
+  UINT8 AuxAd;
+  UINT8 AuxDa;
+  UINT8 Res15[16];
+} FPGA_REG_SET;
+
+/**
+   Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+  UINTN  Reg
+  );
+
+/**
+   Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+  UINTN  Reg,
+  UINT8  Value
+  );
+
+/**
+   Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+  VOID
+  );
+
+/**
+   Function to get system clock frequency.
+**/
+UINTN
+GetBoardSysClk (
+  VOID
+  );
+
+/**
+   Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+  VOID
+  );
+
+#define FPGA_BASE_PHYS   0x52000
+
+//SYSCLK
+#define FPGA_CLK_MASK0x0F // FPGA Clock Mask
+#define SYSCLK_66_MHZ6600
+#define SYSCLK_83_MHZ8300
+#define SYSCLK_100_MHZ   1
+#define SYSCLK_125_MHZ   12500
+#define SYSCLK_133_MHZ   13300
+
+#define FPGA_VBANK_MASK  0x07
+#define FPGA_CS_MASK 0x08
+
+#define FPGA_READ(Reg)   FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value)   FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), 
Value)
+
+#endif // __LS2088A_FPGA_H__
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c 
b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 000..8948c21
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,115 @@
+/** @FpgaLib.c
+  Fpga Library for LS2088A-RDB board, containing functions to
+  program and read the Fpga registers.
+
+  FPGA is connected to IFC Controller and so MMIO APIs are used
+  to read/write FPGA registers
+
+  Copyright 2017-2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+ 

[edk2] [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Signed-off-by: Wasim Khan 
Reviewed-by: Leif Lindholm 
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc |  3 +++
 Silicon/NXP/Include/Chassis3/Soc.h   |  1 -
 Silicon/NXP/LS2088A/LS2088A.dsc.inc  |  1 +
 Silicon/NXP/Library/SocLib/Chassis3/Soc.c| 13 -
 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf |  2 ++
 5 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 465c59e..76d51a2 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -39,6 +39,9 @@
   SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
   IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
   RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+  IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+  BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
+  FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
 
 [PcdsFixedAtBuild.common]
 
diff --git a/Silicon/NXP/Include/Chassis3/Soc.h 
b/Silicon/NXP/Include/Chassis3/Soc.h
index 8d967e7..0dd9eee 100644
--- a/Silicon/NXP/Include/Chassis3/Soc.h
+++ b/Silicon/NXP/Include/Chassis3/Soc.h
@@ -22,7 +22,6 @@
 #define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
 #define TP_CLUSTER_EOC_MASK0x8000  /* Mask for End of clusters 
*/
 #define NUM_CC_PLLS6
-#define CLK_FREQ   1
 #define MAX_CPUS   16
 #define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != 
TP_CLUSTER_EOC_MASK)
 
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc 
b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 8f7dbb5..2cff40f 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -67,5 +67,6 @@
   gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0200
   gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x1
   gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0224
 
 ##
diff --git a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c 
b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
index 0fc92f4..d334bb7 100644
--- a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
@@ -19,11 +19,15 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 
+extern VOID PrintBoardPersonality (VOID);
+extern UINTN GetBoardSysClk (VOID);
+
 VOID
 GetSysInfo (
   OUT SYS_INFO *PtrSysInfo
@@ -82,7 +86,7 @@ GetSysInfo (
 
   GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
   ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
-  SysClk = CLK_FREQ;
+  SysClk = GetBoardSysClk ();
 
   PtrSysInfo->FreqSystemBus = SysClk;
   PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
@@ -151,6 +155,8 @@ SocInit (
   //
   SmmuInit ();
 
+  IfcInit ();
+
   //
   //  Initialize the Serial Port.
   //  Early serial port initialization is required to print RCW,
@@ -177,4 +183,9 @@ SocInit (
   // Print Soc Personality information
   //
   PrintSoc ();
+
+  //
+  // Print Board Personality information
+  //
+  PrintBoardPersonality ();
 }
diff --git a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
index 3d9237d..9547f5a 100644
--- a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
@@ -29,6 +29,8 @@
 [LibraryClasses]
   BaseLib
   DebugLib
+  FpgaLib
+  IfcLib
   IoAccessLib
   SerialPortLib
 
-- 
1.9.1

___
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[edk2] [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 .../Drivers/PlatformDxe/PlatformDxe.c  | 119 +
 .../Drivers/PlatformDxe/PlatformDxe.inf|  58 ++
 2 files changed, 177 insertions(+)
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
 create mode 100644 
Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf

diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c 
b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 000..b74818e
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+  LS1046 RDB board DXE platform driver.
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+  UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+  IN  EFI_GUID*TypeGuid,
+  IN  ADDRESS_SPACE_DESCRIPTOR*Desc,
+  OUT EFI_HANDLE  *Handle
+  )
+{
+  NON_DISCOVERABLE_DEVICE *Device;
+  EFI_STATUS  Status;
+
+  Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+  if (Device == NULL) {
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  Device->Type = TypeGuid;
+  Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+  Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+  , Device,
+  NULL);
+  if (EFI_ERROR (Status)) {
+goto FreeDevice;
+  }
+  return EFI_SUCCESS;
+
+FreeDevice:
+  FreePool (Device);
+
+  return Status;
+}
+
+VOID
+PopulateI2cInformation (
+  IN VOID
+  )
+{
+  UINT32 Index;
+
+  for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) 
- 3;
+mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+mI2cDesc[Index].StartDesc.GenFlag = 0;
+mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 
(PcdI2cSize));
+mI2cDesc[Index].StartDesc.AddrRangeMax = 
mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+  }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  Handle = NULL;
+
+  PopulateI2cInformation ();
+
+  Status = RegisterDevice (,
+ [3], );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Install the DS1307 I2C Master protocol on this handle so the RTC driver
+  // can identify it as the I2C master it can invoke directly.
+  //
+  Status = gBS->InstallProtocolInterface (,
+  ,
+  EFI_NATIVE_INTERFACE, NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf 
b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 000..2556af2
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  Component description file for LS1046 DXE platform driver.
+#
+#  Copyright 2018 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION   

[edk2] [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A

[Meenakshi Aggarwal]

From: Vabhav 

Adding support of ArmPlatformLib for NXP LS1046ARDB board

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Reviewed-by: Leif Lindholm 
---
 .../Library/PlatformLib/ArmPlatformLib.c   | 105 ++
 .../Library/PlatformLib/ArmPlatformLib.inf |  66 +
 .../Library/PlatformLib/NxpQoriqLsHelper.S |  35 +
 .../Library/PlatformLib/NxpQoriqLsMem.c| 152 +
 4 files changed, 358 insertions(+)
 create mode 100644 
Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 
Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 
Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 000..c59a06a
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+*  Contains board initialization functions.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+
+extern VOID SocInit (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN   MpId
+  )
+{
+  SocInit ();
+
+  return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  *CoreCount= sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+  *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof (gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+  IN UINTN MpId
+  )
+{
+  return 1;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000..49b57fc
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,66 @@
+#  @file
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = 05a9029b-266f-421d-bb46-0e8385c64aa0
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  SocLib
+
+[Sources.common]
+  NxpQoriqLsHelper.S| GCC
+  NxpQoriqLsMem.c
+  ArmPlatformLib.c
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+  

[edk2] [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board

[Meenakshi Aggarwal]

From: Vabhav 

Adding firmware device,description and declaration files to enable
compilation for NXP LS1046ARDB board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec |  29 
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc |  90 
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 198 +++
 3 files changed, 317 insertions(+)
 create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
 create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
 create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf

diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
new file mode 100644
index 000..a872ade
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
@@ -0,0 +1,29 @@
+#  LS1046aRdbPkg.dec
+#  LS1046a board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available 
under
+#  the terms and conditions of the BSD License which accompanies this 
distribution.
+#  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+[Defines]
+  PACKAGE_NAME   = LS1046aRdbPkg
+  PACKAGE_GUID   = c0c8d5e4-f63b-4470-89bc-73c13c13b247
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
new file mode 100644
index 000..7eb08a9
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -0,0 +1,90 @@
+#  LS1046aRdbPkg.dsc
+#
+#  LS1046ARDB Board package.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  PLATFORM_NAME  = LS1046aRdbPkg
+  PLATFORM_GUID  = 43920156-3f3b-4199-9b29-c6db1fb792b0
+  OUTPUT_DIRECTORY   = Build/LS1046aRdbPkg
+  FLASH_DEFINITION   = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+  SocLib|Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
+  
ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+  
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+  SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+  IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+  RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
+  IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+  BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
+  FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+
+[PcdsFixedAtBuild.common]
+
+  #
+  # LS1046a board Specific PCDs
+  # XX (DRAM - Region 1 2GB)
+  # (NOR - IFC Region 1 512MB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x8000
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x0200
+
+  #
+  # Board Specific Pcds
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+
+  #
+  # Big Endian IPs
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+
+  #
+  # RTC Pcds
+  #
+  gPcf2129RtcLibTokenSpaceGuid.Pcd

[edk2] [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals

[Meenakshi Aggarwal]

From: Wasim Khan 

Added SocInit function that initializes peripherals
and print board and soc information for LS2088ARDB Board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan 
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Chassis3/SerDes.h|  91 ++
 Silicon/NXP/Include/Chassis3/Soc.h   | 144 +
 Silicon/NXP/LS2088A/Include/SocSerDes.h  |  67 ++
 Silicon/NXP/Library/SocLib/Chassis.c |  38 ++
 Silicon/NXP/Library/SocLib/Chassis.h |  17 +++
 Silicon/NXP/Library/SocLib/Chassis3/Soc.c| 180 +++
 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf |  50 
 Silicon/NXP/Library/SocLib/SerDes.c  |   3 +
 8 files changed, 590 insertions(+)
 create mode 100644 Silicon/NXP/Include/Chassis3/SerDes.h
 create mode 100644 Silicon/NXP/Include/Chassis3/Soc.h
 create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
 create mode 100644 Silicon/NXP/Library/SocLib/Chassis3/Soc.c
 create mode 100644 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf

diff --git a/Silicon/NXP/Include/Chassis3/SerDes.h 
b/Silicon/NXP/Include/Chassis3/SerDes.h
new file mode 100644
index 000..a77ddd5
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis3/SerDes.h
@@ -0,0 +1,91 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 3
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD 
License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include 
+
+#define SRDS_MAX_LANES8
+
+//
+// SerDes lane protocols/devices
+//
+typedef enum {
+  NONE = 0,
+  PCIE1,
+  PCIE2,
+  PCIE3,
+  PCIE4,
+  SATA1,
+  SATA2,
+  XAUI1,
+  XAUI2,
+  XFI1,
+  XFI2,
+  XFI3,
+  XFI4,
+  XFI5,
+  XFI6,
+  XFI7,
+  XFI8,
+  SGMII1,
+  SGMII2,
+  SGMII3,
+  SGMII4,
+  SGMII5,
+  SGMII6,
+  SGMII7,
+  SGMII8,
+  SGMII9,
+  SGMII10,
+  SGMII11,
+  SGMII12,
+  SGMII13,
+  SGMII14,
+  SGMII15,
+  SGMII16,
+  QSGMII_A,
+  QSGMII_B,
+  QSGMII_C,
+  QSGMII_D,
+  // Number of entries in this enum
+  SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+  SRDS_1  = 0,
+  SRDS_2,
+  SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+  UINT16 Protocol;
+  UINT8  SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+  IN SERDES_PROTOCOL LaneProtocol,
+  IN VOID *Arg
+  );
+
+VOID
+SerDesProbeLanes(
+  IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+  IN VOID *Arg
+  );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Include/Chassis3/Soc.h 
b/Silicon/NXP/Include/Chassis3/Soc.h
new file mode 100644
index 000..8d967e7
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis3/Soc.h
@@ -0,0 +1,144 @@
+/** Soc.h
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define FSL_CLK_GRPA_ADDR  0x0130
+#define FSL_CLK_GRPB_ADDR  0x0131
+
+#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
+#define TP_CLUSTER_EOC_MASK0x8000  /* Mask for End of clusters 
*/
+#define NUM_CC_PLLS6
+#define CLK_FREQ   1
+#define MAX_CPUS   16
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != 
TP_CLUSTER_EOC_MASK)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX28
+#define RCWSR_SRDS1_PRTCL_MASK 0x00ff
+#define RCWSR_SRDS1_PRTCL_SHIFT16
+#define RCWSR_SRDS2_PRTCL_MASK 0xff00
+#define RCWSR_SRDS2_PRTCL_SHIFT24
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x0500
+#define SMMU_REG_SCR0  (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR  (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1  (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK   0x0400
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SACR_PAGESIZE_MASK 0x0001
+
+typedef struct {
+  UINTN FreqProcessor[MAX_CPUS];
+  UINTN FreqSystemBus;
+  UI

[edk2] [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib.

[Meenakshi Aggarwal]

BoardLib will contain functions specific for LS1043aRdb board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h   | 109 +
 .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c  |  69 +
 .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf|  31 ++
 3 files changed, 209 insertions(+)
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf

diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h 
b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 000..261867a
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,109 @@
+/** IfcBoardSpecificLib.h
+
+  IFC Flash Board Specific Macros and structure
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include 
+
+// On board flash support
+#define IFC_NAND_BUF_BASE0x7E80
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CSIFC_CS0
+#define IFC_NAND_CS   IFC_CS1
+#define IFC_FPGA_CS   IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0(IFC_FTIM0_NAND_TCCST(0x7) | \
+  IFC_FTIM0_NAND_TWP(0x18)   | \
+  IFC_FTIM0_NAND_TWCHT(0x7) | \
+  IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1(IFC_FTIM1_NAND_TADLE(0x32) | \
+  IFC_FTIM1_NAND_TWBE(0x39)  | \
+  IFC_FTIM1_NAND_TRR(0xe)   | \
+  IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2(IFC_FTIM2_NAND_TRAD(0xf) | \
+  IFC_FTIM2_NAND_TREH(0xa) | \
+  IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM30x0
+
+#define NAND_CSPR   (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+| IFC_CSPR_PORT_SIZE_8 \
+| IFC_CSPR_MSEL_NAND \
+| IFC_CSPR_V)
+
+#define NAND_CSPR_EXT   0x0
+#define NAND_AMASK  0x
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+  | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+  | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+  | IFC_CSOR_NAND_RAL_3   /* RAL = 3 Bytes */ \
+  | IFC_CSOR_NAND_PGS_2K  /* Page Size = 2K */ \
+  | IFC_CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+  | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \
+  IFC_FTIM0_NOR_TEADC(0x1) | \
+  IFC_FTIM0_NOR_TAVDS(0x0) | \
+  IFC_FTIM0_NOR_TEAHC(0xc))
+#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \
+  IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
+  IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \
+  IFC_FTIM2_NOR_TCH(0x4) | \
+  IFC_FTIM2_NOR_TWPH(0x8) | \
+  IFC_FTIM2_NOR_TWP(0x10))
+#define NOR_FTIM3 0x0
+
+#define NOR_CSPR  (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 
(PcdIfcRegion1BaseAddr)) \
+  | IFC_CSPR_PORT_SIZE_16 \
+  | IFC_CSPR_MSEL_NOR\
+  | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT  0x0
+#define NOR_AMASK IFC_AMASK(128*1024*1024)
+#define NOR_CSOR  (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+  IFC_CSOR_NOR_TRHZ_80)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS  0x7fb0
+#define FPGA_CSPR_EXT   0x0
+#define FPGA_CSPR   (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+IFC_CSPR_PORT_SIZE_8 | \
+IFC_CSPR_MSEL_GPCM | \
+IFC_CSPR_V)
+
+#define FPGA_AMASK  IFC_AMASK(64 * 1024)
+#define FPGA_CSOR   (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
+IFC_CSOR_NOR_TRHZ_80)
+
+#define FPGA_FTIM0  (IFC_FTIM0_GPCM_TACSE(0xf) | \
+IFC_FTIM0_GPCM_TEADC(0xf) | \
+IFC_FTIM0_GPCM_TEAHC(0xf))
+#define FPGA_FTIM1  (IFC_FTIM1_GPCM

[edk2] [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver.

[Meenakshi Aggarwal]

Add NOR DXE phase driver, it installs BlockIO and Fvp
protocol.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc|  98 +++
 .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c   | 252 +++
 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c  | 503 +
 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h  | 146 
 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf|  65 ++
 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c   | 816 +
 6 files changed, 1880 insertions(+)
 create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
 create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
 create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
 create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
 create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
 create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c

diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc 
b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 000..e254337
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,98 @@
+## @file
+#  FDF include file with FD definition that defines an empty variable store.
+#
+#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+#  Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+##
+
+[FD.LS1043aRdbNv_EFI]
+BaseAddress   = 0x6030  #The base address of the FLASH device
+Size  = 0x000C  #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE= 0x
+DEFINE NVRAM_AREA_VARIABLE_SIZE= 0x0004
+DEFINE FTW_WORKING_BASE= $(NVRAM_AREA_VARIABLE_BASE) + 
$(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE= 0x0004
+DEFINE FTW_SPARE_BASE  = $(FTW_WORKING_BASE) + 
$(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE  = 0x0004
+
+#
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0xC
+  0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"   # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x3 Blocks * 0x4 Bytes / Block
+  0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+  # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+  # Signature: gEfiAuthenticatedVariableGuid =
+  #   { 0xaaf32c78, 0x947b, 0x439a,
+  # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+  # Size: 0x4 
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvS

[edk2] [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library

[Meenakshi Aggarwal]

From: Vabhav 

Library to provide functions for NXP pcf2129 real time clock library

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/NxpQoriqLs.dsc.inc|   1 +
 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h |  52 +++
 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c  | 389 +
 .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec|  29 ++
 .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf|  47 +++
 5 files changed, 518 insertions(+)
 create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
 create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
 create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
 create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 972dadc..5529a04 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -34,6 +34,7 @@
   ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
   
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
   
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
   
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h 
b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
new file mode 100644
index 000..c862954
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
@@ -0,0 +1,52 @@
+/** Pcf2129Rtc.h
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __PCF2129RTC_H__
+#define __PCF2129RTC_H__
+
+/*
+ * RTC register addresses
+ */
+#define PCF2129_CTRL1_REG_ADDR  0x00  // Control Register 1
+#define PCF2129_CTRL2_REG_ADDR  0x01  // Control Register 2
+#define PCF2129_CTRL3_REG_ADDR  0x02  // Control Register 3
+#define PCF2129_SEC_REG_ADDR0x03
+#define PCF2129_MIN_REG_ADDR0x04
+#define PCF2129_HR_REG_ADDR 0x05
+#define PCF2129_DAY_REG_ADDR0x06
+#define PCF2129_WEEKDAY_REG_ADDR0x07
+#define PCF2129_MON_REG_ADDR0x08
+#define PCF2129_YR_REG_ADDR 0x09
+
+#define PCF2129_CTRL3_BIT_BLF   BIT2/* Battery Low Flag*/
+
+/*
+ * Masks for RTC registers
+ */
+#define PCF2129_SECONDS_MASK0x7F
+#define PCF2129_MINUTES_MASK0x7F
+#define PCF2129_HOURS_MASK  0x3F
+#define PCF2129_DAYS_MASK   0x3F
+#define PCF2129_MONTHS_MASK 0x1F
+
+#define EPOCH_BASE_1990 1990
+#define EPOCH_BASE_2000 2000
+
+typedef struct {
+  UINTN   OperationCount;
+  EFI_I2C_OPERATION   SetAddressOp;
+  EFI_I2C_OPERATION   GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __PCF2129RTC_H__
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c 
b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
new file mode 100644
index 000..90bad66
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
@@ -0,0 +1,389 @@
+/** @PCF2129RtcLib.c
+  Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 
RTC.
+
+  Based on RTC implementation available in
+  EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Pcf2129Rtc.h"
+
+STATIC VOID   *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL*mI2cMaster;
+
+/**
+  Write RTC register.
+
+  @param  RtcRegAddr   Register offset of RTC to write.
+  @param  Val  Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+  IN  U

[edk2] [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package.

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 15 ++-
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf |  9 -
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 48a7b5a..9a68cfd 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -41,6 +41,7 @@
   IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
   BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
   FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+  NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
 
 [PcdsFixedAtBuild.common]
 
@@ -65,6 +66,13 @@
   gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
   gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|10
 
+  #
+  # NV Storage PCDs
+  #
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x06000
+  gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x6030
+
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -74,10 +82,15 @@
   #
   # Architectural Protocols
   #
-  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+
+NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
 
   Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
   Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
   Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+  Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
 
  ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 417303d..6b27aed 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -55,6 +55,7 @@ 
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
 !include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
 

 #
 # FV Section
@@ -104,7 +105,8 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
   INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
-  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
   INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
 
   INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -124,6 +126,11 @@ READ_LOCK_STATUS   = TRUE
   INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
 
   #
+  # NOR Driver
+  #
+  INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+  #
   # Network modules
   #
   INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
-- 
1.9.1

___
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[edk2] [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library

[Meenakshi Aggarwal]

Library to provide board specific timings for LS1046ARDB
board with interfacing to IFC controller for accessing
FPGA and NAND.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Reviewed-by: Leif Lindholm 
---
 .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h   | 83 ++
 .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c  | 61 
 .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf| 31 
 3 files changed, 175 insertions(+)
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
 create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf

diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h 
b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 000..e15100d
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,83 @@
+/** IfcBoardSpecificLib.h
+
+  IFC Flash Board Specific Macros and structure
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include 
+
+// On board flash support
+#define IFC_NAND_BUF_BASE0x7E80
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CSIFC_CS_MAX
+#define IFC_NAND_CS   IFC_CS0
+#define IFC_FPGA_CS   IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0(IFC_FTIM0_NAND_TCCST(0x7) | \
+  IFC_FTIM0_NAND_TWP(0x18)   | \
+  IFC_FTIM0_NAND_TWCHT(0x7) | \
+  IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1(IFC_FTIM1_NAND_TADLE(0x32) | \
+  IFC_FTIM1_NAND_TWBE(0x39)  | \
+  IFC_FTIM1_NAND_TRR(0xe)   | \
+  IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2(IFC_FTIM2_NAND_TRAD(0xf) | \
+  IFC_FTIM2_NAND_TREH(0xa) | \
+  IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM30x0
+
+#define NAND_CSPR   (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+| IFC_CSPR_PORT_SIZE_8 \
+| IFC_CSPR_MSEL_NAND \
+| IFC_CSPR_V)
+
+#define NAND_CSPR_EXT   0x0
+#define NAND_AMASK  0x
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+  | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+  | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
+  | IFC_CSOR_NAND_RAL_3   /* RAL = 3 Bytes */ \
+  | IFC_CSOR_NAND_PGS_4K  /* Page Size = 4K */ \
+  | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+  | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS  0x7fb0
+#define FPGA_CSPR_EXT   0x0
+#define FPGA_CSPR   (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+IFC_CSPR_PORT_SIZE_8 | \
+IFC_CSPR_MSEL_GPCM | \
+IFC_CSPR_V)
+
+#define FPGA_AMASK  IFC_AMASK(64 * 1024)
+#define FPGA_CSOR   IFC_CSOR_NOR_ADM_SHIFT(16)
+
+#define FPGA_FTIM0  (IFC_FTIM0_GPCM_TACSE(0x0e) | \
+IFC_FTIM0_GPCM_TEADC(0x0e) | \
+IFC_FTIM0_GPCM_TEAHC(0x0e))
+#define FPGA_FTIM1  (IFC_FTIM1_GPCM_TACO(0xff) | \
+IFC_FTIM1_GPCM_TRAD(0x3f))
+#define FPGA_FTIM2  (IFC_FTIM2_GPCM_TCS(0xf) | \
+IFC_FTIM2_GPCM_TCH(0xf) | \
+IFC_FTIM2_GPCM_TWP(0x3E))
+#define FPGA_FTIM3  0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c 
b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 000..0971935
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,61 @@
+/** @file
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+
+VOID
+GetIfcNorFlashTimings (
+  IN IFC_TIMINGS * NorIfcTimings
+  )
+{
+  

[edk2] [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files.

[Meenakshi Aggarwal]

The firmware device, description and declaration files.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/FVRules.fdf.inc |  99 +++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec |  29 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc |  80 ++
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 198 +
 Platform/NXP/NxpQoriqLs.dsc.inc  | 412 +++
 Silicon/NXP/LS1043A/LS1043A.dec  |  22 ++
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  |  73 +
 Silicon/NXP/NxpQoriqLs.dec   | 117 
 8 files changed, 1030 insertions(+)
 create mode 100644 Platform/NXP/FVRules.fdf.inc
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
 create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
 create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
 create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
 create mode 100644 Silicon/NXP/NxpQoriqLs.dec

diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
new file mode 100644
index 000..d0e17cb
--- /dev/null
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -0,0 +1,99 @@
+#  FvRules.fdf.inc
+#
+#  Rules for creating FD.
+#
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the 
default
+# rules for the different module type. User can add the customized rules to 
define the
+# content of the FFS file.
+#
+
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+TE  TEAlign = 32$(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+TE TE   $(INF_OUTPUT)/$(MODULE_NAME).efi
+UI STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional   $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32  PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI   STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+PEI_DEPEX PEI_DEPEX Optional$(INF_OUTPUT)/$(MODULE_NAME).depex
+GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+  PE32  PE32$(INF_OUTPUT)/$(MODULE_NAME).efi
+  UISTRING="$(MODULE_NAME)" Optional
+}
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
+UI   STRING="$(MODULE_NAME)" Optional
+  }
+
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+DXE_DEPEXDXE_DEPEX  Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
+PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
+UI   STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+DXE_DEPEXDXE_DEPEX  Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
+PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
+UI   STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+DXE_DEPEXDXE_DEPEX  Optional 
$(INF_OUTPUT)/$(MODULE_NAME).depex
+PE32 PE32   $(INF_OUTPUT)/$(MODULE_NAME).efi
+UI   STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+UI STRING ="$(MODULE_NAME)" Optional
+PE32   PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+DXE_DEPEX DXE_DEPEX Optional  |.depex
+PE32  PE32|.efi
+UISTRING="$(MODULE_NAME)" Optional
+VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+PE32  PE32|

[edk2] [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib

[Meenakshi Aggarwal]

NorFlashLib interacts with the underlying IFC NOR controller.
This will be used by NOR driver for any information
exchange with NOR controller.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Library/NorFlashLib.h|  77 +++
 Silicon/NXP/Include/NorFlash.h   |  44 ++
 Silicon/NXP/Library/NorFlashLib/CfiCommand.h |  99 
 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 210 +++
 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h |  53 ++
 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c| 696 +++
 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf  |  43 ++
 7 files changed, 1222 insertions(+)
 create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
 create mode 100644 Silicon/NXP/Include/NorFlash.h
 create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
 create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
 create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
 create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
 create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf

diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h 
b/Silicon/NXP/Include/Library/NorFlashLib.h
new file mode 100644
index 000..defdc61
--- /dev/null
+++ b/Silicon/NXP/Include/Library/NorFlashLib.h
@@ -0,0 +1,77 @@
+/** @file
+
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+ Copyright 2017 NXP
+
+This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD 
License
+ which accompanies this distribution.  The full text of the license may be 
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef _NOR_FLASH_LIB_H_
+#define _NOR_FLASH_LIB_H_
+
+#include 
+
+#define NOR_FLASH_DEVICE_COUNT  1
+
+typedef struct {
+  UINTN  DeviceBaseAddress;   // Start address of the Device Base Address (DBA)
+  UINTN  RegionBaseAddress;   // Start address of one single region
+  UINTN  Size;
+  UINTN  BlockSize;
+  UINTN  MultiByteWordCount;  // Maximum Word count that can be written to Nor 
Flash in multi byte write
+  UINTN  WordWriteTimeOut;// single byte/word timeout usec
+  UINTN  BufferWriteTimeOut;  // buffer write timeout usec
+  UINTN  BlockEraseTimeOut;   // block erase timeout usec
+  UINTN  ChipEraseTimeOut;// chip erase timeout usec
+} NorFlashDescription;
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+  OUT NorFlashDescription **NorFlashDevices,
+  OUT UINT32  *Count
+  );
+
+EFI_STATUS
+NorFlashPlatformFlashGetAttributes (
+  OUT NorFlashDescription *NorFlashDevices,
+  IN  UINT32  Count
+  );
+
+EFI_STATUS
+NorFlashPlatformWriteBuffer (
+  IN NOR_FLASH_INSTANCE *Instance,
+  IN EFI_LBALba,
+  INUINTN   Offset,
+  IN OUTUINTN   *NumBytes,
+  INUINT8   *Buffer
+  );
+
+EFI_STATUS
+NorFlashPlatformEraseSector (
+  IN NOR_FLASH_INSTANCE *Instance,
+  IN UINTN  SectorAddress
+  );
+
+EFI_STATUS
+NorFlashPlatformRead (
+  IN NOR_FLASH_INSTANCE   *Instance,
+  IN EFI_LBA  Lba,
+  IN UINTNOffset,
+  IN UINTNBufferSizeInBytes,
+  OUT UINT8   *Buffer
+  );
+
+EFI_STATUS
+NorFlashPlatformReset (
+  IN UINTN Instance
+  );
+
+#endif /* _NOR_FLASH_LIB_H_ */
diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h
new file mode 100644
index 000..8fa41d8
--- /dev/null
+++ b/Silicon/NXP/Include/NorFlash.h
@@ -0,0 +1,44 @@
+/** @NorFlash.h
+
+  Contains data structure shared by both NOR Library and Driver.
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_H__
+#define __NOR_FLASH_H__
+
+#include 
+#include 
+
+typedef struct _NOR_FLASH_INSTANCENOR_FLASH_INSTANCE;
+
+typedef struct {
+  VENDOR_DEVICE_PATH  Vendor;
+  EFI_DEVICE_PATH_PROTOCOLEnd;
+} NOR_FLASH_DEVICE_PATH;
+
+struct _NOR_FLASH_INSTANCE {
+  UINT32  Signature;
+  EFI_HANDLE  Handle;
+  UINTN   DeviceBaseAddress;
+  UINTN   RegionBaseAddress;
+  UINTN   Size;
+  EFI_LBA 

[edk2] [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support

[Meenakshi Aggarwal]

Provide Functions to initialize peripherals,
print board and soc information.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav 
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc |  1 +
 Silicon/NXP/LS1046A/Include/SocSerDes.h  | 55 ++
 Silicon/NXP/LS1046A/LS1046A.dec  | 22 +
 Silicon/NXP/LS1046A/LS1046A.dsc.inc  | 68 
 Silicon/NXP/Library/SocLib/Chassis.c |  1 +
 Silicon/NXP/Library/SocLib/Chassis.h |  1 +
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c| 48 
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf |  2 +
 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++
 Silicon/NXP/NxpQoriqLs.dec   |  1 +
 10 files changed, 252 insertions(+)
 create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
 create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
 create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 9a68cfd..b69ffa2 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -59,6 +59,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
   gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
   gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+  gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
 
   #
   # RTC Pcds
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h 
b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 000..957db0f
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD 
License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __LS1046A_SERDES_H__
+#define __LS1046A_SERDES_H__
+
+#include 
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+  /* SerDes 1 */
+  {0x, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, 
SGMII_FM1_DTSEC6 } },
+  {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } 
},
+  {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, 
SGMII_FM1_DTSEC6 } },
+  {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, 
SGMII_FM1_DTSEC6 } },
+  {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, 
SGMII_FM1_DTSEC6 } },
+  {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
+  {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
+  {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
+  {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, 
SGMII_FM1_DTSEC6 } },
+  {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
+  {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, 
SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+  {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+  /* SerDes 2 */
+  {0x, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+  {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
+  {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+  {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
+  {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
+  {0x0559, {NONE, PCIE2, PCIE3, SATA } },
+  {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
+  {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
+  {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+  SerDes1ConfigTbl,
+  SerDes2ConfigTbl
+};
+
+#endif /* __LS1046A_SERDES_H */
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 000..93fc80d
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,22 @@
+# LS1046A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available 
under
+# the terms and conditions of the BSD License which accompanies this 
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+  DEC_SPECIFICATION  = 0x0001000A
+
+[Guids.common]
+  gNxpLs1046ATokenSpaceGuid  = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 
0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
+
+[Includes]
+  Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc 
b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 000..9f87028
--- /dev/null
+++ b

[edk2] [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib.

[Meenakshi Aggarwal]

FpgaLib export FPGA_READ and FPGA_WRITE function and
provide a function to print Board personality.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Library/FpgaLib.h   |  97 +
 Silicon/NXP/Library/FpgaLib/FpgaLib.c   | 145 
 Silicon/NXP/Library/FpgaLib/FpgaLib.inf |  34 
 3 files changed, 276 insertions(+)
 create mode 100644 Silicon/NXP/Include/Library/FpgaLib.h
 create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.c
 create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.inf

diff --git a/Silicon/NXP/Include/Library/FpgaLib.h 
b/Silicon/NXP/Include/Library/FpgaLib.h
new file mode 100644
index 000..847689c
--- /dev/null
+++ b/Silicon/NXP/Include/Library/FpgaLib.h
@@ -0,0 +1,97 @@
+/** FpgaLib.h
+*  Header defining the Fpga specific constants (Base addresses, sizes, flags)
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __LS1_FPGA_H__
+#define __LS1_FPGA_H__
+
+/*
+ * FPGA register set of board.
+ */
+typedef struct {
+  UINT8  FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */
+  UINT8  FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */
+  UINT8  PcbaVersion;  /* 0x2 - PCBA Revision Register */
+  UINT8  SystemReset;  /* 0x3 - system reset register */
+  UINT8  SoftMuxOn;/* 0x4 - Switch Control Enable Register */
+  UINT8  RcwSource1;   /* 0x5 - Reset config word 1 */
+  UINT8  RcwSource2;   /* 0x6 - Reset config word 2 */
+  UINT8  Vbank;/* 0x7 - Flash bank selection Control */
+  UINT8  SysclkSelect; /* 0x8 - System clock selection Control */
+  UINT8  UartSel;  /* 0x9 - Uart selection Control */
+  UINT8  Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control 
*/
+  UINT8  TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */
+  UINT8  SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */
+  UINT8  StatusLed;/* 0xD - Status Led */
+  UINT8  GlobalReset;  /* 0xE - Global reset */
+  UINT8  SdEmmc;   /* 0xF - SD or EMMC Interface Control Regsiter */
+  UINT8  VddEn;/* 0x10 - VDD Voltage Control Enable Register */
+  UINT8  VddSel;   /* 0x11 - VDD Voltage Control Register */
+} FPGA_REG_SET;
+
+/**
+   Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+  UINTN  Reg
+  );
+
+/**
+   Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+  UINTN  Reg,
+  UINT8  Value
+  );
+
+/**
+   Function to read FPGA revision.
+**/
+VOID
+FpgaRevBit (
+  UINT8  *Value
+  );
+
+/**
+   Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+  VOID
+  );
+
+/**
+   Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+  VOID
+  );
+
+#define FPGA_BASE_PHYS  0x7fb0
+
+#define SRC_VBANK   0x25
+#define SRC_NAND0x106
+#define SRC_QSPI0x44
+#define SRC_SD  0x40
+
+#define SERDES_FREQ1"100.00 MHz"
+#define SERDES_FREQ2"156.25 MHz"
+
+#define FPGA_READ(Reg)  FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value)  FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), 
Value)
+
+#endif
diff --git a/Silicon/NXP/Library/FpgaLib/FpgaLib.c 
b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 000..93e9a90
--- /dev/null
+++ b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,145 @@
+/** @FpgaLib.c
+  Fpga Library containing functions to program and read the Fpga registers.
+
+  FPGA is connected to IFC Controller and so MMIO APIs are used
+  to read/write FPGA registers
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+   Function to read FPGA register.
+
+   @param  Reg  Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+  IN  UINTN  Reg
+  )
+{
+  VOID   *Base;
+
+  Base = (VOID *)FPGA_BASE_PHYS;
+
+  return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+   Function to write FPGA register.
+
+   @param  Reg   Register offset of FPGA to write.
+   @param 

[edk2] [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib

[Meenakshi Aggarwal]

Add support of IfcLib, it will be used to perform
any operation on IFC controller.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Library/IfcLib.h  |  26 +
 Silicon/NXP/Library/IfcLib/IfcLib.c   | 150 +++
 Silicon/NXP/Library/IfcLib/IfcLib.h   | 190 ++
 Silicon/NXP/Library/IfcLib/IfcLib.inf |  38 +++
 Silicon/NXP/NxpQoriqLs.dec|   1 +
 5 files changed, 405 insertions(+)
 create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
 create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
 create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
 create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf

diff --git a/Silicon/NXP/Include/Library/IfcLib.h 
b/Silicon/NXP/Include/Library/IfcLib.h
new file mode 100644
index 000..8d2c151
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IfcLib.h
@@ -0,0 +1,26 @@
+/** @IfcLib.h
+
+  The integrated flash controller (IFC) is used to interface with external 
asynchronous
+  NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_LIB_H__
+#define __IFC_LIB_H__
+
+VOID
+IfcInit (
+  VOID
+  );
+
+#endif //__IFC_LIB_H__
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c 
b/Silicon/NXP/Library/IfcLib/IfcLib.c
new file mode 100644
index 000..8cf02ae
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
@@ -0,0 +1,150 @@
+/** @IfcLib.c
+
+  The integrated flash controller (IFC) is used to interface with external 
asynchronous/
+  synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
+  EPROM.
+  It has eight chip-selects, to which a maximum of eight flash devices can be 
attached,
+  although only one of these can be accessed at any given time.
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include "IfcLib.h"
+
+STATIC MMIO_OPERATIONS_32 *mMmioOps;
+
+STATIC UINT8 mNandCS;
+STATIC UINT8 mNorCS;
+STATIC UINT8 mFpgaCS;
+
+VOID
+SetTimings (
+  IN  UINT8CS,
+  IN  IFC_TIMINGS  IfcTimings
+  )
+{
+  IFC_REGS*IfcRegs;
+
+  IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
+
+  // Configure Extended chip select property registers
+  mMmioOps->Write ((UINTN)>CsprCs[CS].CsprExt, IfcTimings.CsprExt);
+
+  // Configure Fpga timing registers
+  mMmioOps->Write ((UINTN)>FtimCs[CS].Ftim[IFC_FTIM0], 
IfcTimings.Ftim[0]);
+  mMmioOps->Write ((UINTN)>FtimCs[CS].Ftim[IFC_FTIM1], 
IfcTimings.Ftim[1]);
+  mMmioOps->Write ((UINTN)>FtimCs[CS].Ftim[IFC_FTIM2], 
IfcTimings.Ftim[2]);
+  mMmioOps->Write ((UINTN)>FtimCs[CS].Ftim[IFC_FTIM3], 
IfcTimings.Ftim[3]);
+
+  // Configure chip select option registers
+  mMmioOps->Write ((UINTN)>CsprCs[CS].Cspr, IfcTimings.Cspr);
+
+  // Configure address mask registers
+  mMmioOps->Write ((UINTN)>AmaskCs[CS].Amask, IfcTimings.Amask);
+
+  // Configure chip select property registers
+  mMmioOps->Write ((UINTN)>CsorCs[CS].Csor, IfcTimings.Csor);
+
+  return;
+}
+
+VOID
+NandInit(
+  VOID
+  )
+{
+  IFC_REGS*   IfcRegs;
+  IFC_TIMINGS NandIfcTimings;
+
+  IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
+
+  // Get Nand Flash Timings
+  GetIfcNandFlashTimings ();
+
+  // Validate chip select
+  if (NandIfcTimings.CS < IFC_CS_MAX) {
+mNandCS = NandIfcTimings.CS;
+
+// clear event registers
+mMmioOps->Write ((UINTN)>IfcNand.PgrdcmplEvtStat, ~0U);
+
+mMmioOps->Write ((UINTN)>IfcNand.NandEvterStat, ~0U);
+
+// Enable error and event for any detected errors
+mMmioOps->Write ((UINTN)>IfcNand.NandEvterEn,
+  IFC_NAND_EVTER_EN_OPC_EN |
+  IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+  IFC_NAND_EVTER_EN_FTOER_EN |
+  IFC_NAND_EVTER_EN_WPER_EN);
+mMmioOps->Write ((UINTN)>IfcNand.Ncfgr, 0x0);
+
+SetTimings (mNandCS, NandIfcTimings);
+  }
+
+  return;
+}
+
+VOID
+FpgaInit (
+  VOID
+  )
+{
+  IFC_TIMINGS FpgaIfcTimings;
+
+  // Get Fpga Flash Timings
+  GetIfcFpgaTimings ();
+
+  // Validate chip select
+  if (FpgaIfcTimings.CS <

[edk2] [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller

[Meenakshi Aggarwal]

This header file contain IFC controller timing structure,
chip select enum and other IFC macros.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Ifc.h | 423 ++
 1 file changed, 423 insertions(+)
 create mode 100644 Silicon/NXP/Include/Ifc.h

diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h
new file mode 100644
index 000..6babb22
--- /dev/null
+++ b/Silicon/NXP/Include/Ifc.h
@@ -0,0 +1,423 @@
+/** @Ifc.h
+
+  The integrated flash controller (IFC) is used to interface with external 
asynchronous
+  NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_H__
+#define __IFC_H__
+
+#include 
+#include 
+
+#define IFC_BANK_COUNT4
+
+#define IFC_CSPR_REG_LEN  148
+#define IFC_AMASK_REG_LEN 144
+#define IFC_CSOR_REG_LEN  144
+#define IFC_FTIM_REG_LEN  576
+
+#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
+  IFC_BANK_COUNT
+
+#define IFC_AMASK_USED_LENsizeof (IFC_AMASK) * \
+  IFC_BANK_COUNT
+
+#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
+  IFC_BANK_COUNT
+
+#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
+  IFC_BANK_COUNT
+
+/* List of commands */
+#define IFC_NAND_CMD_RESET0xFF
+#define IFC_NAND_CMD_READID   0x90
+#define IFC_NAND_CMD_STATUS   0x70
+#define IFC_NAND_CMD_READ00x00
+#define IFC_NAND_CMD_READSTART0x30
+#define IFC_NAND_CMD_ERASE1   0x60
+#define IFC_NAND_CMD_ERASE2   0xD0
+#define IFC_NAND_CMD_SEQIN0x80
+#define IFC_NAND_CMD_PAGEPROG 0x10
+#define MAX_RETRY_COUNT   15
+
+
+#define IFC_NAND_SEQ_STRT_FIR_STRT  0x8000
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC 0x8000
+
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER   0x0800
+
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER0x0400
+
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER   0x0200
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0   0xFC00
+#define IFC_NAND_FIR0_OP0_SHIFT 26
+#define IFC_NAND_FIR0_OP1   0x03F0
+#define IFC_NAND_FIR0_OP1_SHIFT 20
+#define IFC_NAND_FIR0_OP2   0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT 14
+#define IFC_NAND_FIR0_OP3   0x3F00
+#define IFC_NAND_FIR0_OP3_SHIFT 8
+#define IFC_NAND_FIR0_OP4   0x00FC
+#define IFC_NAND_FIR0_OP4_SHIFT 2
+#define IFC_NAND_FIR1_OP5   0xFC00
+#define IFC_NAND_FIR1_OP5_SHIFT 26
+#define IFC_NAND_FIR1_OP6   0x03F0
+#define IFC_NAND_FIR1_OP6_SHIFT 20
+#define IFC_NAND_FIR1_OP7   0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT 14
+#define IFC_NAND_FIR1_OP8   0x3F00
+#define IFC_NAND_FIR1_OP8_SHIFT 8
+#define IFC_NAND_FIR1_OP9   0x00FC
+#define IFC_NAND_FIR1_OP9_SHIFT 2
+#define IFC_NAND_FIR2_OP10  0xFC00
+#define IFC_NAND_FIR2_OP10_SHIFT26
+#define IFC_NAND_FIR2_OP11  0x03F0
+#define IFC_NAND_FIR2_OP11_SHIFT20
+#define IFC_NAND_FIR2_OP12  0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT14
+#define IFC_NAND_FIR2_OP13  0x3F00
+#define IFC_NAND_FIR2_OP13_SHIFT8
+#define IFC_NAND_FIR2_OP14  0x00FC
+#define IFC_NAND_FIR2_OP14_SHIFT2
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0  0xFF00
+#define IFC_NAND_FCR0_CMD0_SHIFT24
+#define IFC_NAND_FCR0_CMD1  0x00FF
+#define IFC_NAND_FCR0_CMD1_SHIFT16
+#define IFC_NAND_FCR0_CMD2  0xFF00
+#define IFC_NAND_FCR0_CMD2_SHIFT8
+#define IFC_NAND_FCR0_CMD3  0x00FF
+#define IFC_NAND_FCR0_CMD3_SHIFT0
+#define IFC_NAND_FCR1_CMD4  0xFF00
+#define IFC_NAND_FCR1_CMD4_SHIFT24
+#define IFC_NAND_FCR1_CMD5  0x00FF
+#define IFC_NAND_FCR1_CMD5_SHIFT16
+#define IFC_NAND_FCR1_CMD6  0xFF00
+#define IFC_NAND_FCR1_CMD6_SHIFT8
+#define IFC_NAND_FCR1_CMD7  0x00FF
+#define IFC_NAND_FCR1_CMD7_SHIFT0
+
+/* Timing registers for NAND Flash */

[edk2] [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib.

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +++
 Silicon/NXP/LS1043A/LS1043A.dsc.inc  | 2 ++
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c| 5 +
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 2 ++
 4 files changed, 12 insertions(+)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc 
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c2701fe..48a7b5a 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -38,6 +38,9 @@
   SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
   IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
   RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+  IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+  BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
+  FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
 
 [PcdsFixedAtBuild.common]
 
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc 
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 8395dfd..a4eb117 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -63,11 +63,13 @@
   gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x4000
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x2000
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x153
 
   #
   # Big Endian IPs
   #
   gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
   gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
 
 ##
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c 
b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 1875c3b..e79728e 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -19,11 +19,14 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 
+extern VOID PrintBoardPersonality (VOID);
+
 /**
   Calculate the frequency of various controllers and
   populate the passed structure with frequuencies.
@@ -162,6 +165,8 @@ SocInit (
   //
   PrintRCW ();
   PrintSoc ();
+  IfcInit ();
+  PrintBoardPersonality ();
 
   return;
 }
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf 
b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index d16288a..af0790f 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -29,6 +29,8 @@
 [LibraryClasses]
   BaseLib
   DebugLib
+  FpgaLib
+  IfcLib
   IoAccessLib
   SerialPortLib
 
-- 
1.9.1

___
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[edk2] [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver

[Meenakshi Aggarwal]

Installs watchdog timer arch protocol

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Drivers/WatchDog/WatchDog.c  | 402 +++
 Silicon/NXP/Drivers/WatchDog/WatchDog.h  |  39 +++
 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf |  47 
 3 files changed, 488 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf

diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c 
b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
new file mode 100644
index 000..1b1a3b5
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
@@ -0,0 +1,402 @@
+/** WatchDog.c
+*
+*  Based on Watchdog driver implemenation available in
+*  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "WatchDog.h"
+
+STATIC EFI_EVENT  EfiExitBootServicesEvent;
+STATIC EFI_EVENT  WdogFeedEvent;
+STATIC MMIO_OPERATIONS_16 *mMmioOps;
+
+
+STATIC
+VOID
+WdogPing (
+  VOID
+  )
+{
+  //
+  // To reload a timeout value to the counter the proper service sequence 
begins by
+  // writing 0x_ followed by 0x_ to the Watchdog Service Register 
(WDOG_WSR).
+  // This service sequence will reload the counter with the timeout value 
WT[7:0] of
+  // Watchdog Control Register (WDOG_WCR).
+  //
+
+  mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ1);
+  mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ2);
+}
+
+/**
+  Stop the Wdog watchdog timer from counting down.
+**/
+STATIC
+VOID
+WdogStop (
+  VOID
+  )
+{
+  // Watchdog cannot be disabled by software once started.
+  // At best, we can keep reload counter with maximum value
+
+  mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+(UINT16)(~WDOG_WCR_WT),
+(WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+  WdogPing ();
+}
+
+/**
+  Starts the Wdog counting down by feeding Service register with
+  desired pattern.
+  The count down will start from the value stored in the Load register,
+  not from the value where it was previously stopped.
+**/
+STATIC
+VOID
+WdogStart (
+  VOID
+  )
+{
+  //Reload the timeout value
+  WdogPing ();
+}
+
+/**
+On exiting boot services we must make sure the Wdog Watchdog Timer
+is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+ExitBootServicesEvent (
+  IN EFI_EVENT  Event,
+  IN VOID   *Context
+  )
+{
+  WdogStop ();
+}
+
+/**
+  This function registers the handler NotifyFunction so it is called every time
+  the watchdog timer expires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.
+  If NotifyFunction is not NULL and a handler is not already registered,
+  then the new handler is registered and EFI_SUCCESS is returned.
+  If NotifyFunction is NULL, and a handler is already registered,
+  then that handler is unregistered.
+  If an attempt is made to register a handler when a handler is already 
registered,
+  then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.
+
+  @param  This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param  NotifyFunction   The function to call when a timer interrupt fires. 
This
+   function executes at TPL_HIGH_LEVEL. The DXE Core 
will
+   register a handler for the timer interrupt, so it 
can know
+   how much time has passed. This information is used 
to
+   signal timer based events. NULL will unregister the 
handler.
+
+  @retval EFI_SUCCESS   The watchdog timer handler was registered.
+  @retval EFI_ALREADY_STARTED   NotifyFunction is not NULL, and a handler is 
already
+registered.
+  @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+previously registered.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogRegisterHandler (
+  IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL   *This,
+  IN EFI_WATCHDOG_TIMER_NOTIFY  NotifyFunction
+  )
+{
+  // ERROR: This function is not supported.
+  // The hardware watchd

[edk2] [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver

[Meenakshi Aggarwal]

I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 185 
 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 241 ++
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c| 693 +
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h|  96 
 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf  |  64 +++
 5 files changed, 1279 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
 create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
 create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
 create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
 create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf

diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c 
b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
new file mode 100644
index 000..efed6b9
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
@@ -0,0 +1,185 @@
+/** @file
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "I2cDxe.h"
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] = {
+  {
+"en",
+(CHAR16 *)L"Nxp I2C Driver"
+  },
+  { }
+};
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] = {
+  {
+"en",
+(CHAR16 *)L"Nxp I2C Controller"
+  },
+  { }
+};
+
+/**
+  Retrieves a Unicode string that is the user readable name of the driver.
+
+  This function retrieves the user readable name of a driver in the form of a
+  Unicode string. If the driver specified by This has a user readable name in
+  the language specified by Language, then a pointer to the driver name is
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+  by This does not support the language specified by Language,
+  then EFI_UNSUPPORTED is returned.
+
+  @param  This[in]  A pointer to the EFI_COMPONENT_NAME2_PROTOCOL 
or
+EFI_COMPONENT_NAME_PROTOCOL instance.
+
+  @param  Language[in]  A pointer to a Null-terminated ASCII string
+array indicating the language. This is the
+language of the driver name that the caller is
+requesting, and it must match one of the
+languages specified in SupportedLanguages. The
+number of languages supported by a driver is up
+to the driver writer. Language is specified
+in RFC 4646 or ISO 639-2 language code format.
+
+  @param  DriverName[out]   A pointer to the Unicode string to return.
+This Unicode string is the name of the
+driver specified by This in the language
+specified by Language.
+
+  @retval EFI_SUCCESS   The Unicode string for the Driver specified by
+This and the language specified by Language was
+returned in DriverName.
+
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+  @retval EFI_UNSUPPORTED   The driver specified by This does not support
+the language specified by Language.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NxpI2cGetDriverName (
+  IN  EFI_COMPONENT_NAME2_PROTOCOL  *This,
+  IN  CHAR8 *Language,
+  OUT CHAR16**DriverName
+  )
+{
+  return LookupUnicodeString2 (Language,
+   This->SupportedLanguages,
+   mNxpI2cDriverNameTable,
+   DriverName,
+   FALSE);
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by a driver.
+
+  This function retrieves the user readable name of the controller specified by
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the
+  driver specified by This has a user readable name in the language specified 
by
+  Language, then a pointer to the controller name is returned in 
ControllerName,
+  and EFI_SUCCESS is returned.  If the driver specified by This is not 
currently
+  managing the controller specified by ControllerHandle and ChildHandle,
+  then EFI_UNSUPPORTED is

[edk2] [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 .../Library/PlatformLib/ArmPlatformLib.c   | 105 ++
 .../Library/PlatformLib/ArmPlatformLib.inf |  67 +
 .../Library/PlatformLib/NxpQoriqLsHelper.S |  38 ++
 .../Library/PlatformLib/NxpQoriqLsMem.c| 152 +
 4 files changed, 362 insertions(+)
 create mode 100644 
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
 create mode 100644 
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
 create mode 100644 
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
 create mode 100644 
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c

diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c 
b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 000..ab4815d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+*  Contains board initialization functions.
+*
+*  Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+
+extern VOID SocInit (VOID);
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+  IN  UINTN   MpId
+  )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
+  {
+// Cluster 0, Core 0
+0x0, 0x0,
+
+// MP Core MailBox Set/Get/Clear Addresses and Clear Value
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(EFI_PHYSICAL_ADDRESS)0,
+(UINT64)0x
+  },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN   *CoreCount,
+  OUT ARM_CORE_INFO   **ArmCoreTable
+  )
+{
+  *CoreCount= sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
+  *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
+
+  return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR  gPlatformPpiTable[] = {
+  {
+EFI_PEI_PPI_DESCRIPTOR_PPI,
+,
+
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof (gPlatformPpiTable);
+  *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+  IN UINTN MpId
+  )
+{
+  return 1;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000..7feac56
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,67 @@
+#  @file
+#
+#  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+#  Copyright 2017 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = PlatformLib
+  FILE_GUID  = 736343a0-1d96-11e0--0002a5d5c51b
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+  ArmLib
+  SocLib
+
+[Sources.common]
+  NxpQoriqLsHelper.S| GCC
+  NxpQoriqLsMem.c
+  ArmPlatformLib.c
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+  gNxpQoriqLsTokenSpaceGuid.P

[edk2] [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 .../Drivers/PlatformDxe/PlatformDxe.c  | 119 +
 .../Drivers/PlatformDxe/PlatformDxe.inf|  58 ++
 2 files changed, 177 insertions(+)
 create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
 create mode 100644 
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf

diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c 
b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 000..7ce7318
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+  LS1043 DXE platform driver.
+
+  Copyright 2018 NXP
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+  UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+  IN  EFI_GUID*TypeGuid,
+  IN  ADDRESS_SPACE_DESCRIPTOR*Desc,
+  OUT EFI_HANDLE  *Handle
+  )
+{
+  NON_DISCOVERABLE_DEVICE *Device;
+  EFI_STATUS  Status;
+
+  Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+  if (Device == NULL) {
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  Device->Type = TypeGuid;
+  Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+  Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+  , Device,
+  NULL);
+  if (EFI_ERROR (Status)) {
+goto FreeDevice;
+  }
+  return EFI_SUCCESS;
+
+FreeDevice:
+  FreePool (Device);
+
+  return Status;
+}
+
+VOID
+PopulateI2cInformation (
+  IN VOID
+  )
+{
+  UINT32 Index;
+
+  for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) 
- 3;
+mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+mI2cDesc[Index].StartDesc.GenFlag = 0;
+mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 
(PcdI2cSize));
+mI2cDesc[Index].StartDesc.AddrRangeMax = 
mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+  }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_HANDLE  Handle;
+
+  Handle = NULL;
+
+  PopulateI2cInformation ();
+
+  Status = RegisterDevice (,
+ [0], );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Install the DS1307 I2C Master protocol on this handle so the RTC driver
+  // can identify it as the I2C master it can invoke directly.
+  //
+  Status = gBS->InstallProtocolInterface (,
+  ,
+  EFI_NATIVE_INTERFACE, NULL);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf 
b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 000..91d6ad3
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  Component description file for LS1043 DXE platform driver.
+#
+#  Copyright 2018 NXP
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION   

[edk2] [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals

[Meenakshi Aggarwal]

Add SocInit function that initializes peripherals
and print board and soc information.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Chassis2/SerDes.h|  68 +
 Silicon/NXP/Include/Chassis2/Soc.h   | 367 ++
 Silicon/NXP/LS1043A/Include/SocSerDes.h  |  57 
 Silicon/NXP/Library/SocLib/Chassis.c | 372 +++
 Silicon/NXP/Library/SocLib/Chassis.h | 144 +++
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c| 167 
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf |  49 
 Silicon/NXP/Library/SocLib/SerDes.c  | 271 +++
 8 files changed, 1495 insertions(+)
 create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h
 create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h
 create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
 create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
 create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h
 create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
 create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
 create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c

diff --git a/Silicon/NXP/Include/Chassis2/SerDes.h 
b/Silicon/NXP/Include/Chassis2/SerDes.h
new file mode 100644
index 000..4c874aa
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/SerDes.h
@@ -0,0 +1,68 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD 
License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include 
+
+#define SRDS_MAX_LANES 4
+
+typedef enum {
+  NONE = 0,
+  PCIE1,
+  PCIE2,
+  PCIE3,
+  SATA,
+  SGMII_FM1_DTSEC1,
+  SGMII_FM1_DTSEC2,
+  SGMII_FM1_DTSEC5,
+  SGMII_FM1_DTSEC6,
+  SGMII_FM1_DTSEC9,
+  SGMII_FM1_DTSEC10,
+  QSGMII_FM1_A,
+  XFI_FM1_MAC9,
+  XFI_FM1_MAC10,
+  SGMII_2500_FM1_DTSEC2,
+  SGMII_2500_FM1_DTSEC5,
+  SGMII_2500_FM1_DTSEC9,
+  SGMII_2500_FM1_DTSEC10,
+  SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+  SRDS_1  = 0,
+  SRDS_2,
+  SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+  UINT16 Protocol;
+  UINT8  SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+  IN SERDES_PROTOCOL LaneProtocol,
+  IN VOID *Arg
+  );
+
+VOID
+SerDesProbeLanes(
+  IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+  IN VOID *Arg
+  );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Include/Chassis2/Soc.h 
b/Silicon/NXP/Include/Chassis2/Soc.h
new file mode 100644
index 000..10e99ab
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/Soc.h
@@ -0,0 +1,367 @@
+/** Soc.h
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define HWA_CGA_M1_CLK_SEL 0xe000
+#define HWA_CGA_M1_CLK_SHIFT   29
+
+#define TP_CLUSTER_EOC_MASK0xc000  /* end of clusters mask */
+#define NUM_CC_PLLS2
+#define CLK_FREQ   1
+#define MAX_CPUS   4
+#define NUM_FMAN   1
+#define CHECK_CLUSTER(Cluster)((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX4
+#define RCWSR_SRDS1_PRTCL_MASK 0x
+#define RCWSR_SRDS1_PRTCL_SHIFT16
+#define RCWSR_SRDS2_PRTCL_MASK 0x
+#define RCWSR_SRDS2_PRTCL_SHIFT0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x0900
+#define SMMU_REG_SCR0  (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR  (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1  (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK   0x0400
+#define SCR0_CLIENTPD_MASK 0x0001
+#define SACR_PAGESIZE_MASK 0x0001
+#define IDR1_PAGESIZE_MASK 0x8000
+
+typedef struct {
+  UINTN FreqProcessor[MAX_CPUS];
+  UINTN FreqSystemBus;
+  UINTN FreqDdrBus;
+  UINTN FreqLocalBus;
+  

[edk2] [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.

[Meenakshi Aggarwal]

Readme.md to explain how to build NXP board packages.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Platform/NXP/Readme.md | 24 
 1 file changed, 24 insertions(+)
 create mode 100644 Platform/NXP/Readme.md

diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
new file mode 100644
index 000..902bafe
--- /dev/null
+++ b/Platform/NXP/Readme.md
@@ -0,0 +1,24 @@
+Support for all NXP boards is available in this directory.
+
+# How to build
+
+1. Set toolchain path.
+
+   export 
PATH=/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin/:$PATH
+
+2. Export following variables needed for compilation.
+
+   export CROSS_COMPILE=aarch64-linux-gnu-
+   export GCC_ARCH_PREFIX=GCC49_AARCH64_PREFIX
+   export GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
+   export PACKAGES_PATH=/edk2/edk2-platforms
+
+3. Build desired board package
+
+   source edksetup.sh
+   build -p "path to package's description (.dsc) file" -a AARCH64 -t GCC49 -b 
DEBUG/RELEASE clean
+
+   e.g.
+   build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a 
AARCH64 -t GCC49 -b DEBUG clean
+   build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a 
AARCH64 -t GCC49 -b DEBUG
+
-- 
1.9.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library

[Meenakshi Aggarwal]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 Silicon/NXP/Library/DUartPortLib/DUart.h  | 128 
 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c   | 370 ++
 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf |  41 +++
 3 files changed, 539 insertions(+)
 create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
 create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
 create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf

diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h 
b/Silicon/NXP/Library/DUartPortLib/DUart.h
new file mode 100644
index 000..3fa0a68
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -0,0 +1,128 @@
+/** DUart.h
+*  Header defining the DUART constants (Base addresses, sizes, flags)
+*
+*  Based on Serial I/O Port library headers available in PL011Uart.h
+*
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __DUART_H__
+#define __DUART_H__
+
+// FIFO Control Register
+#define DUART_FCR_FIFO_EN  0x01 /* Fifo enable */
+#define DUART_FCR_CLEAR_RCVR   0x02 /* Clear the RCVR FIFO */
+#define DUART_FCR_CLEAR_XMIT   0x04 /* Clear the XMIT FIFO */
+#define DUART_FCR_DMA_SELECT   0x08 /* For DMA applications */
+#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define DUART_FCR_TRIGGER_10x00 /* Mask for trigger set at 1 */
+#define DUART_FCR_TRIGGER_40x40 /* Mask for trigger set at 4 */
+#define DUART_FCR_TRIGGER_80x80 /* Mask for trigger set at 8 */
+#define DUART_FCR_TRIGGER_14   0xC0 /* Mask for trigger set at 14 */
+#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+// Modem Control Register
+#define DUART_MCR_DTR  0x01 /* Reserved  */
+#define DUART_MCR_RTS  0x02 /* RTS   */
+#define DUART_MCR_OUT1 0x04 /* Reserved */
+#define DUART_MCR_OUT2 0x08 /* Reserved */
+#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define DUART_MCR_AFE  0x20 /* AFE (Auto Flow Control) */
+#define DUART_MCR_DMA_EN   0x04
+#define DUART_MCR_TX_DFR   0x08
+
+// Line Control Register
+/*
+* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
+* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+*/
+#define DUART_LCR_WLS_MSK  0x03 /* character length select mask */
+#define DUART_LCR_WLS_50x00 /* 5 bit character length */
+#define DUART_LCR_WLS_60x01 /* 6 bit character length */
+#define DUART_LCR_WLS_70x02 /* 7 bit character length */
+#define DUART_LCR_WLS_80x03 /* 8 bit character length */
+#define DUART_LCR_STB  0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define DUART_LCR_PEN  0x08 /* Parity eneble */
+#define DUART_LCR_EPS  0x10 /* Even Parity Select */
+#define DUART_LCR_STKP 0x20 /* Stick Parity */
+#define DUART_LCR_SBRK 0x40 /* Set Break */
+#define DUART_LCR_BKSE 0x80 /* Bank select enable */
+#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+// Line Status Register
+#define DUART_LSR_DR   0x01 /* Data ready */
+#define DUART_LSR_OE   0x02 /* Overrun */
+#define DUART_LSR_PE   0x04 /* Parity error */
+#define DUART_LSR_FE   0x08 /* Framing error */
+#define DUART_LSR_BI   0x10 /* Break */
+#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
+#define DUART_LSR_ERR  0x80 /* Error */
+
+// Modem Status Register
+#define DUART_MSR_DCTS 0x01 /* Delta CTS */
+#define DUART_MSR_DDSR 0x02 /* Reserved */
+#define DUART_MSR_TERI 0x04 /* Reserved */
+#define DUART_MSR_DDCD 0x08 /* Reserved */
+#define DUART_MSR_CTS  0x10 /* Clear to Send */
+#define DUART_MSR_DSR  0x20 /* Reserved */
+#define DUART_MSR_RI   0x40 /* Reserved */
+#define DUART_MSR_DCD  0x80 /* Reserved */
+
+// Interrupt Identification Register
+#define DUART_IIR_NO_INT   0x01 /* No interrupts pending */
+#define DUART_IIR_ID 

[edk2] [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs

[Meenakshi Aggarwal]

|   |   |   |   |-- PciCpuIo2Dxe.c  
|   |   |   |   `-- PciCpuIo2Dxe.inf
|   |   |   |-- UsbHcdInitDxe   
|   |   |   |   |-- UsbHcd.c
|   |   |   |   |-- UsbHcd.h
|   |   |   |   `-- UsbHcd.inf  
|   |   |   `-- WatchDog
|   |   |   |-- WatchDog.c  
|   |   |   |-- WatchDogDxe.inf 
|   |   |   `-- WatchDog.h  
|   |   |-- Include 
|   |   |   |-- Chassis2
|   |   |   |   |-- SerDes.h
|   |   |   |   `-- Soc.h   
|   |   |   |-- Chassis3
|   |   |   |   |-- SerDes.h
|   |   |   |   `-- Soc.h   
|   |   |   |-- Ifc.h   
|   |   |   |-- Library 
|   |   |   |   |-- FpgaLib.h   
|   |   |   |   |-- IfcLib.h
|   |   |   |   |-- IoAccessLib.h   
|   |   |   |   `-- NorFlashLib.h   
|   |   |   |-- NorFlash.h  
|   |   |   `-- NxpPcie.h   
|   |   |-- Library 
|   |   |   |-- DUartPortLib
|   |   |   |   |-- DUart.h 
|   |   |   |   |-- DUartPortLib.c  
|   |   |   |   `-- DUartPortLib.inf
|   |   |   |-- FpgaLib 
|   |   |   |   |-- FpgaLib.c   
|   |   |   |   `-- FpgaLib.inf 
|   |   |   |-- IfcLib  
|   |   |   |   |-- IfcLib.c
|   |   |   |   |-- IfcLib.h
|   |   |   |   `-- IfcLib.inf  
|   |   |   |-- IoAccessLib 
|   |   |   |   |-- IoAccessLib.c   
|   |   |   |   `-- IoAccessLib.inf 
|   |   |   |-- NorFlashLib 
|   |   |   |   |-- CfiCommand.h
|   |   |   |   |-- CfiNorFlashLib.c
|   |   |   |   |-- CfiNorFlashLib.h
|   |   |   |   |-- NorFlashLib.c   
|   |   |   |   `-- NorFlashLib.inf 
|   |   |   |-- Pcf2129RtcLib   
|   |   |   |   |-- Pcf2129Rtc.h
|   |   |   |   |-- Pcf2129RtcLib.c 
|   |   |   |   |-- Pcf2129RtcLib.dec   
|   |   |   |   `-- Pcf2129RtcLib.inf   
|   |   |   |-- Pcf8563RealTimeClockLib 
|   |   |   |   |-- Pcf8563RealTimeClockLib.c   
|   |   |   |   |-- Pcf8563RealTimeClockLib.dec 
|   |   |   |   `-- Pcf8563RealTimeClockLib.inf 
|   |   |   |-- PciHostBridgeLib
|   |   |   |   |-- PciHostBridgeLib.c  
|   |   |   |   `-- PciHostBridgeLib.inf
|   |   |   |-- PciSegmentLib   
|   |   |   |   |-- PciSegmentLib.c 
|   |   |   |   `-- PciSegmentLib.inf   
|   |   |   `-- SocLib  
|   |   |   |-- Chassis2
|   |   |   |   `-- Soc.c   
|   |   |   |-- Chassis3
|   |   |   |   `-- Soc.c   
|   |   |   |-- Chassis.c   
|   |   |   |-- Chassis.h   
|   |   |   |-- LS1043aSocLib.inf   
|   |   |   |-- LS1046aSocLib.inf   
|   |   |   |-- LS2088aSocLib.inf   
|   |   |   `-- SerDes.c
|   |   |-- LS1043A 
|   |   |   |-- Include 
|   |   |   |   `-- SocSerDes.h 
|   |   |   |-- LS1043A.dec 
|   |   |   `-- LS1043A.dsc.inc 
|   |   |-- LS1046A 
|   |   |   |-- Include 
|   |   |   |   `-- SocSerDes.h 
|   |   |   |-- LS1046A.dec 
|   |   |   `-- LS1046A.dsc.inc 
|   |   |-- LS2088A 
|   |   |   |-- Include 
|   |   |   |   `-- SocSerDes.h 
|   |   |   |-- LS2088A.dec 
|   |   |   `-- LS2088A.dsc.inc 
|   |   `-- NxpQoriqLs.dec  


In Silicon/NXP, we are keeping our SoC specific information and all Drivers and 
Library which are used by SoCs.

Platform/NXP/ will host our board packages and build script.

Board specific libraries and header files will reside inside board package.


Looking forward for your kind support in upstreaming our boards in 
edk2-platforms.


Meenakshi Aggarwal (28):
  Silicon/NXP: Add Library to return Mmio APIs pointer
  Silicon/NXP : Add support for Watchdog driver
  SocLib : Add support for initialization of peripherals
  Silicon/NXP : Add support for DUART library
  Silicon/NXP: Add support for I2c driver
  Silicon/Maxim : Add support for DS1307 RTC library
  Platform/NXP: Add support

[edk2] [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer

[Meenakshi Aggarwal]

This library add supports to return pointer to
MMIO APIs on basis of Swap flag.
If Flag is True then MMION APIs returened in which data
swapped after reading from MMIO and before write using MMIO.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
---
 Silicon/NXP/Include/Library/IoAccessLib.h   | 332 +++
 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c   | 410 
 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf |  32 ++
 3 files changed, 774 insertions(+)
 create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
 create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
 create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf

diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h 
b/Silicon/NXP/Include/Library/IoAccessLib.h
new file mode 100644
index 000..f7372a5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -0,0 +1,332 @@
+/** @file
+ *
+ *  Copyright 2017 NXP
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD 
License
+ *  which accompanies this distribution.  The full text of the license may be 
found at
+ *  http://opensource.org/licenses/bsd-license.php
+ *
+ *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+ *
+ **/
+
+#ifndef __IO_ACCESS_LIB_H__
+#define __IO_ACCESS_LIB_H__
+
+#include 
+
+///
+///  Structure to have pointer to R/W
+///  Mmio operations for 16 bits.
+///
+typedef struct _MMIO_OPERATIONS_16 {
+  UINT16 (*Read) (UINTN Address);
+  UINT16 (*Write) (UINTN Address, UINT16 Value);
+  UINT16 (*Or) (UINTN Address, UINT16 Or);
+  UINT16 (*And) (UINTN Address, UINT16 AND);
+  UINT16 (*AndThenOr) (UINTN Address, UINT16 And, UINT16 Or);
+} MMIO_OPERATIONS_16;
+
+///
+///  Structure to have pointer to R/W
+///  Mmio operations for 32 bits.
+///
+typedef struct _MMIO_OPERATIONS_32 {
+  UINT32 (*Read) (UINTN Address);
+  UINT32 (*Write) (UINTN Address, UINT32 Value);
+  UINT32 (*Or) (UINTN Address, UINT32 Or);
+  UINT32 (*And) (UINTN Address, UINT32 AND);
+  UINT32 (*AndThenOr) (UINTN Address, UINT32 And, UINT32 Or);
+} MMIO_OPERATIONS_32;
+
+///
+///  Structure to have pointer to R/W
+///  Mmio operations for 64 bits.
+///
+typedef struct _MMIO_OPERATIONS_64 {
+  UINT64 (*Read) (UINTN Address);
+  UINT64 (*Write) (UINTN Address, UINT64 Value);
+  UINT64 (*Or) (UINTN Address, UINT64 Or);
+  UINT64 (*And) (UINTN Address, UINT64 AND);
+  UINT64 (*AndThenOr) (UINTN Address, UINT64 And, UINT64 Or);
+} MMIO_OPERATIONS_64;
+
+/**
+  Function to return pointer to 16 bit Mmio operations.
+
+  @param  Swap  Flag to tell if Swap is needed or not
+on Mmio Operations.
+
+  @return   Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_16 *
+GetMmioOperations16  (
+  IN  BOOLEAN  Swap
+  );
+
+/**
+  Function to return pointer to 32 bit Mmio operations.
+
+  @param  Swap  Flag to tell if Swap is needed or not
+on Mmio Operations.
+
+  @return   Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_32 *
+GetMmioOperations32  (
+  IN  BOOLEAN  Swap
+  );
+
+/**
+  Function to return pointer to 64 bit Mmio operations.
+
+  @param  Swap  Flag to tell if Swap is needed or not
+on Mmio Operations.
+
+  @return   Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_64 *
+GetMmioOperations64  (
+  IN  BOOLEAN  Swap
+  );
+
+/**
+  MmioRead16 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT16
+EFIAPI
+SwapMmioRead16 (
+  IN  UINTN Address
+  );
+
+/**
+  MmioRead32 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT32
+EFIAPI
+SwapMmioRead32 (
+  IN  UINTN Address
+  );
+
+/**
+  MmioRead64 for Big-Endian modules.
+
+  @param  Address The MMIO register to read.
+
+  @return The value read.
+
+**/
+UINT64
+EFIAPI
+SwapMmioRead64 (
+  IN  UINTN Address
+  );
+
+/**
+  MmioWrite16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioWrite16 (
+  IN  UINTN Address,
+  IN  UINT16Value
+  );
+
+/**
+  MmioWrite32 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioWrite32 (
+  IN  UINTN Address,
+  IN  UINT32Value
+  );
+
+/**
+  MmioWrite64 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @param  Value   The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioWrite64 (
+  IN  UINTN Address,
+  IN  UINT64Value
+  );
+
+/**
+  MmioAndThenOr16 for Big-Endian modules.
+
+  @param  Address The MMIO register to write.
+  @para

[edk2] [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library

[Meenakshi Aggarwal]

Real time clock Apis on top of I2C Apis

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Reviewed-by: Leif Lindholm 
---
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h |  54 +++
 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c  | 378 +
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec|  29 ++
 .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf|  45 +++
 4 files changed, 506 insertions(+)
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
 create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h 
b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
new file mode 100644
index 000..3fad7fa
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
@@ -0,0 +1,54 @@
+/** Ds1307Rtc.h
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef __DS1307RTC_H__
+#define __DS1307RTC_H__
+
+/*
+ * RTC time register
+ */
+#define DS1307_SEC_REG_ADDR0x00
+#define DS1307_MIN_REG_ADDR0x01
+#define DS1307_HR_REG_ADDR 0x02
+#define DS1307_DAY_REG_ADDR0x03
+#define DS1307_DATE_REG_ADDR   0x04
+#define DS1307_MON_REG_ADDR0x05
+#define DS1307_YR_REG_ADDR 0x06
+
+#define DS1307_SEC_BIT_CH  0x80  /* Clock Halt (in Register 0)   */
+
+/*
+ * RTC control register
+ */
+#define DS1307_CTL_REG_ADDR0x07
+
+#define START_YEAR 1970
+#define END_YEAR   2070
+
+/*
+ * TIME MASKS
+ */
+#define MASK_SEC   0x7F
+#define MASK_MIN   0x7F
+#define MASK_HOUR  0x3F
+#define MASK_DAY   0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+  UINTN   OperationCount;
+  EFI_I2C_OPERATION   SetAddressOp;
+  EFI_I2C_OPERATION   GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS1307RTC_H__
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c 
b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
new file mode 100644
index 000..53878ba
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -0,0 +1,378 @@
+/** Ds1307RtcLib.c
+  Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
+
+  Based on RTC implementation available in
+  EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Ds1307Rtc.h"
+
+STATIC VOID   *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL*mI2cMaster;
+
+/**
+  Read RTC register.
+
+  @param  RtcRegAddr   Register offset of RTC to be read.
+
+  @retval  Register Value read
+
+**/
+
+STATIC
+UINT8
+RtcRead (
+  IN  UINT8RtcRegAddr
+  )
+{
+  RTC_I2C_REQUEST  Req;
+  EFI_STATUS   Status;
+  UINT8Val;
+
+  Val = 0;
+
+  Req.OperationCount = 2;
+
+  Req.SetAddressOp.Flags = 0;
+  Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+  Req.SetAddressOp.Buffer = 
+
+  Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+  Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+  Req.GetSetDateTimeOp.Buffer = 
+
+  Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 
(PcdI2cSlaveAddress),
+ (VOID *),
+ NULL,  NULL);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+  }
+
+  return Val;
+}
+
+/**
+  Write RTC register.
+
+  @param  RtcRegAddr   Register offset of RTC to write.
+  @param  Val  Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+  IN  UINT8RtcRegAddr,
+  IN  UINT8   

[edk2] [PATCH v3] EmbeddedPkg/TimeBaseLib: Add function to get Week day.

[Meenakshi Aggarwal]

This patch add function EfiTimeToWday() which returns
day of the week.
It is needed by our upcoming patches in edk2-platforms.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav Sharma 
Signed-off-by: Meenakshi Aggarwal 
---
 EmbeddedPkg/Include/Library/TimeBaseLib.h |  8 ++
 EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c | 38 ---
 2 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/EmbeddedPkg/Include/Library/TimeBaseLib.h 
b/EmbeddedPkg/Include/Library/TimeBaseLib.h
index fe3618e..dd0b99f 100644
--- a/EmbeddedPkg/Include/Library/TimeBaseLib.h
+++ b/EmbeddedPkg/Include/Library/TimeBaseLib.h
@@ -65,4 +65,12 @@ EfiTimeToEpoch (
   IN  EFI_TIME  *Time
   );
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  );
+
 #endif
diff --git a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c 
b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
index 0c0d940..5f2bf65 100644
--- a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
+++ b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
@@ -77,11 +77,11 @@ EpochToEfiTime (
 }
 
 /**
-  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+  Calculate Epoch days
  **/
 UINTN
 EFIAPI
-EfiTimeToEpoch (
+EfiGetEpochDays (
   IN  EFI_TIME  *Time
   )
 {
@@ -90,7 +90,6 @@ EfiTimeToEpoch (
   UINTN m;
   UINTN JulianDate;  // Absolute Julian Date representation of the supplied 
Time
   UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
-  UINTN EpochSeconds;
 
   a = (14 - Time->Month) / 12 ;
   y = Time->Year + 4800 - a;
@@ -101,11 +100,44 @@ EfiTimeToEpoch (
   ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
   EpochDays = JulianDate - EPOCH_JULIAN_DATE;
 
+  return EpochDays;
+}
+/**
+  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+ **/
+UINTN
+EFIAPI
+EfiTimeToEpoch (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+  UINTN EpochSeconds;
+
+  EpochDays = EfiGetEpochDays (Time);
+
   EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * 
SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
 
   return EpochSeconds;
 }
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+
+  EpochDays = EfiGetEpochDays (Time);
+
+  // 4=1/1/1970 was a Thursday
+
+  return (EpochDays + 4) % 7;
+}
+
 BOOLEAN
 EFIAPI
 IsLeapYear (
-- 
1.9.1

___
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edk2-devel@lists.01.org
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Re: [edk2] [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library

[Meenakshi Aggarwal]

Hi Leif,

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, April 19, 2018 8:14 PM
> To: Meenakshi Aggarwal 
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> ; Varun Sethi ; Vabhav Sharma
> 
> Subject: Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board
> FPGA library
> 
> On Fri, Feb 16, 2018 at 02:20:18PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal 
> >
> > Library to provide functions for accessing FPGA on LS1046ARDB board.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav 
> > Signed-off-by: Meenakshi Aggarwal 
> 
> I compare this one to LS1043aRdbPkg/Library/FpgaLib, and the differences in
> the .c file are
> --- Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> 15:13:08.507949763 +0100
> +++ Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> +++ 15:13:08.531949605 +0100
> @@ -1,5 +1,5 @@
>  /** @FpgaLib.c
> -  Fpga Library for LS1043A-RDB board, containing functions to
> +  Fpga Library for LS1046A-RDB board, containing functions to
>program and read the Fpga registers.
> 
>FPGA is connected to IFC Controller and so MMIO APIs are used @@ -137,6
> +137,8 @@
>Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
>DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
>Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> +  DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
> +  SERDES_FREQ1, SERDES_FREQ1));
> 
>return;
>  }
> 
> Could these two libraries be merged into a single LS104xx variant?
> 
> The LS2088a one seems to have substantial differences, so that makes sense to
> keep separate.
> 
We were planning to keep this library common for both LS1046 and LS1043,
But as this is board specific library, and in case, same soc be used on any 
other board,
then there will be changes in common library which might not be significant for 
other.

Also, FPGA_REG_SET structure is different for both, luckily here the new struct 
members
are added in the end of structure, but we cannot be sure about same in future 
boards.

So we decided to keep board specific stuff separate.

> No other comments on this patch.
> 
> /
> Leif
> 
> > ---
> >  .../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h|  97 ++
> >  .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c| 144
> +
> >  .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf  |  32 +
> >  3 files changed, 273 insertions(+)
> >  create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> >  create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> >  create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> >
> > diff --git a/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > new file mode 100644
> > index 000..c8f7411
> > --- /dev/null
> > +++ b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > @@ -0,0 +1,97 @@
> > +/** FpgaLib.h
> > +*  Header defining the LS1046a Fpga specific constants (Base
> > +addresses, sizes, flags)
> > +*
> > +*  Copyright 2017 NXP
> > +*
> > +*  This program and the accompanying materials
> > +*  are licensed and made available under the terms and conditions of
> > +the BSD License
> > +*  which accompanies this distribution.  The full text of the license
> > +may be found at
> > +*
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.agg
> >
> +arwal%40nxp.com%7C5d08c304527946a5bf8908d5a6040dc0%7C686ea1d3bc
> 2b4c6f
> >
> +a92cd99c5c301635%7C0%7C0%7C636597458708526882=%2FFRG6Itp%
> 2B23zi
> > +FZzr8QqfiGX7IImR8L6QjjTL2R%2Fgpw%3D=0
> > +*
> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __LS1046A_FPGA_H__
> > +#define __LS1046A_FPGA_H__
> > +
> > +/**
> > +   FPGA register set of LS1046ARDB board-specific.
> > + **/
> > +typedef struct {
> > +  UINT8  FpgaVersionMajor; // 0x0 - FPGA Major Revision Register
> > +  UINT8  FpgaVersionMinor; // 0x1 - FPGA Minor Revision Register
> > +  UINT8  PcbaVersion;  // 0x2 - PCBA Revision Register
> > +  UINT8  SystemReset;  // 0x

[edk2] [PATCH v2] EmbeddedPkg/TimeBaseLib: Add function to get Week day.

[Meenakshi Aggarwal]

This patch add function EfiTimeToWday() which returns
day of the week.
It is needed by our upcoming patches in edk2-platforms.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Signed-off-by: Vabhav Sharma 
---
 EmbeddedPkg/Include/Library/TimeBaseLib.h |  8 ++
 EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c | 38 ---
 2 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/EmbeddedPkg/Include/Library/TimeBaseLib.h 
b/EmbeddedPkg/Include/Library/TimeBaseLib.h
index fe3618e..dd0b99f 100644
--- a/EmbeddedPkg/Include/Library/TimeBaseLib.h
+++ b/EmbeddedPkg/Include/Library/TimeBaseLib.h
@@ -65,4 +65,12 @@ EfiTimeToEpoch (
   IN  EFI_TIME  *Time
   );
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  );
+
 #endif
diff --git a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c 
b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
index 0c0d940..5f2bf65 100644
--- a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
+++ b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
@@ -77,11 +77,11 @@ EpochToEfiTime (
 }
 
 /**
-  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+  Calculate Epoch days
  **/
 UINTN
 EFIAPI
-EfiTimeToEpoch (
+EfiGetEpochDays (
   IN  EFI_TIME  *Time
   )
 {
@@ -90,7 +90,6 @@ EfiTimeToEpoch (
   UINTN m;
   UINTN JulianDate;  // Absolute Julian Date representation of the supplied 
Time
   UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
-  UINTN EpochSeconds;
 
   a = (14 - Time->Month) / 12 ;
   y = Time->Year + 4800 - a;
@@ -101,11 +100,44 @@ EfiTimeToEpoch (
   ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
   EpochDays = JulianDate - EPOCH_JULIAN_DATE;
 
+  return EpochDays;
+}
+/**
+  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+ **/
+UINTN
+EFIAPI
+EfiTimeToEpoch (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+  UINTN EpochSeconds;
+
+  EpochDays = EfiGetEpochDays (Time);
+
   EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * 
SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
 
   return EpochSeconds;
 }
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+
+  EpochDays = EfiGetEpochDays (Time);
+
+  // 4=1/1/1970 was a Thursday
+
+  return (EpochDays + 4) % 7;
+}
+
 BOOLEAN
 EFIAPI
 IsLeapYear (
-- 
1.9.1

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Re: [edk2] [PATCH] EmbeddedPkg/TimeBaseLib: Add function to get Week day.

[Meenakshi Aggarwal]

Yes, we need this patch for edk2-platform changes [Leif suggested to move the 
changes in edk2 as function was a generic one].

Will send V2.

Thanks,
Meenakshi

-Original Message-
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] 
Sent: Thursday, May 31, 2018 6:38 PM
To: Meenakshi Aggarwal 
Cc: Leif Lindholm ; edk2-devel@lists.01.org; Vabhav 
Sharma 
Subject: Re: [PATCH] EmbeddedPkg/TimeBaseLib: Add function to get Week day.

On 31 May 2018 at 19:02, Meenakshi Aggarwal  wrote:
> This patch add function EfiTimeToWday() which returns day of the week.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal 
> Signed-off-by: Vabhav 

Please use your full name in the S-o-b line

Also, do you need this patch for upcoming edk2-platforms changes? If so, please 
mention that, otherwise it is unclear why we need this change.


> ---
>  EmbeddedPkg/Include/Library/TimeBaseLib.h |  8 ++
>  EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c | 38 
> ---
>  2 files changed, 43 insertions(+), 3 deletions(-)
>
> diff --git a/EmbeddedPkg/Include/Library/TimeBaseLib.h 
> b/EmbeddedPkg/Include/Library/TimeBaseLib.h
> index fe3618e..dd0b99f 100644
> --- a/EmbeddedPkg/Include/Library/TimeBaseLib.h
> +++ b/EmbeddedPkg/Include/Library/TimeBaseLib.h
> @@ -65,4 +65,12 @@ EfiTimeToEpoch (
>IN  EFI_TIME  *Time
>);
>
> +/**
> +  returns Day of the week [0-6] 0=Sunday  **/ UINTN EfiTimeToWday (
> +  IN  EFI_TIME  *Time
> +  );
> +
>  #endif
> diff --git a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c 
> b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
> index 0c0d940..5f2bf65 100644
> --- a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
> +++ b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
> @@ -77,11 +77,11 @@ EpochToEfiTime (
>  }
>
>  /**
> -  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 
> 00:00:00 UTC)
> +  Calculate Epoch days
>   **/
>  UINTN
>  EFIAPI
> -EfiTimeToEpoch (
> +EfiGetEpochDays (
>IN  EFI_TIME  *Time
>)
>  {
> @@ -90,7 +90,6 @@ EfiTimeToEpoch (
>UINTN m;
>UINTN JulianDate;  // Absolute Julian Date representation of the supplied 
> Time
>UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
> -  UINTN EpochSeconds;
>
>a = (14 - Time->Month) / 12 ;
>y = Time->Year + 4800 - a;
> @@ -101,11 +100,44 @@ EfiTimeToEpoch (
>ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
>EpochDays = JulianDate - EPOCH_JULIAN_DATE;
>
> +  return EpochDays;
> +}
> +/**
> +  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 
> +00:00:00 UTC)  **/ UINTN EFIAPI EfiTimeToEpoch (
> +  IN  EFI_TIME  *Time
> +  )
> +{
> +  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
> +  UINTN EpochSeconds;
> +
> +  EpochDays = EfiGetEpochDays (Time);
> +
>EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * 
> SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
>
>return EpochSeconds;
>  }
>
> +/**
> +  returns Day of the week [0-6] 0=Sunday  **/ UINTN EfiTimeToWday (
> +  IN  EFI_TIME  *Time
> +  )
> +{
> +  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
> +
> +  EpochDays = EfiGetEpochDays (Time);
> +
> +  // 4=1/1/1970 was a Thursday
> +
> +  return (EpochDays + 4) % 7;
> +}
> +
>  BOOLEAN
>  EFIAPI
>  IsLeapYear (
> --
> 1.9.1
>
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[edk2] [PATCH] EmbeddedPkg/TimeBaseLib: Add function to get Week day.

[Meenakshi Aggarwal]

This patch add function EfiTimeToWday() which returns
day of the week.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal 
Signed-off-by: Vabhav 
---
 EmbeddedPkg/Include/Library/TimeBaseLib.h |  8 ++
 EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c | 38 ---
 2 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/EmbeddedPkg/Include/Library/TimeBaseLib.h 
b/EmbeddedPkg/Include/Library/TimeBaseLib.h
index fe3618e..dd0b99f 100644
--- a/EmbeddedPkg/Include/Library/TimeBaseLib.h
+++ b/EmbeddedPkg/Include/Library/TimeBaseLib.h
@@ -65,4 +65,12 @@ EfiTimeToEpoch (
   IN  EFI_TIME  *Time
   );
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  );
+
 #endif
diff --git a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c 
b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
index 0c0d940..5f2bf65 100644
--- a/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
+++ b/EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.c
@@ -77,11 +77,11 @@ EpochToEfiTime (
 }
 
 /**
-  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+  Calculate Epoch days
  **/
 UINTN
 EFIAPI
-EfiTimeToEpoch (
+EfiGetEpochDays (
   IN  EFI_TIME  *Time
   )
 {
@@ -90,7 +90,6 @@ EfiTimeToEpoch (
   UINTN m;
   UINTN JulianDate;  // Absolute Julian Date representation of the supplied 
Time
   UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
-  UINTN EpochSeconds;
 
   a = (14 - Time->Month) / 12 ;
   y = Time->Year + 4800 - a;
@@ -101,11 +100,44 @@ EfiTimeToEpoch (
   ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
   EpochDays = JulianDate - EPOCH_JULIAN_DATE;
 
+  return EpochDays;
+}
+/**
+  Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 
UTC)
+ **/
+UINTN
+EFIAPI
+EfiTimeToEpoch (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+  UINTN EpochSeconds;
+
+  EpochDays = EfiGetEpochDays (Time);
+
   EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * 
SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
 
   return EpochSeconds;
 }
 
+/**
+  returns Day of the week [0-6] 0=Sunday
+ **/
+UINTN
+EfiTimeToWday (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINTN EpochDays;   // Number of days elapsed since EPOCH_JULIAN_DAY
+
+  EpochDays = EfiGetEpochDays (Time);
+
+  // 4=1/1/1970 was a Thursday
+
+  return (EpochDays + 4) % 7;
+}
+
 BOOLEAN
 EFIAPI
 IsLeapYear (
-- 
1.9.1

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Re: [edk2] [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver

[Meenakshi Aggarwal]

Hi Ard

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, April 23, 2018 7:10 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: Leif Lindholm <leif.lindh...@linaro.org>; edk2-devel@lists.01.org; Udit
> Kumar <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
> 
> On 23 April 2018 at 12:34, Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com> wrote:
> > Hi Leif
> >
> >> -Original Message-
> >> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> >> Sent: Monday, April 23, 2018 2:08 PM
> >> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> >> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> >> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for
> I2c
> >> driver
> >>
> >> On Mon, Apr 23, 2018 at 08:21:22AM +, Meenakshi Aggarwal wrote:
> >> > > > +/**
> >> > > > +  Function to read data using i2c bus
> >> > > > +
> >> > > > +  @param   I2cBus  I2c Controller number
> >> > > > +  @param   ChipAddress of slave device from where data 
> >> > > > to
> be
> >> read
> >> > > > +  @param   Offset  Offset of slave memory
> >> > > > +  @param   AlenAddress length of slave
> >> > > > +  @param   Buffer  A pointer to the destination buffer for 
> >> > > > the
> data
> >> > > > +  @param   Len Length of data to be read
> >> > > > +
> >> > > > +  @retval  EFI_NOT_READY   Arbitration lost
> >> > > > +  @retval  EFI_TIMEOUT Failed to initialize data transfer in
> >> predefined
> >> > > time
> >> > > > +  @retval  EFI_NOT_FOUND   ACK was not recieved
> >> > > > +  @retval  EFI_SUCCESS Read was successful
> >> > > > +
> >> > > > +**/
> >> > > > +STATIC
> >> > > > +EFI_STATUS
> >> > > > +I2cDataRead (
> >> > > > +  IN  UINT32   I2cBus,
> >> > > > +  IN  UINT8Chip,
> >> > > > +  IN  UINT32   Offset,
> >> > > > +  IN  UINT32   Alen,
> >> > > > +  IN  UINT8*Buffer,
> >> > > > +  IN  UINT32   Len
> >> > > > +  )
> >> > > > +{
> >> > > > +  EFI_STATUS   Status;
> >> > > > +  UINT32   Temp;
> >> > > > +  INT32I;
> >> > > > +  I2C_REGS *I2cRegs;
> >> > > > +
> >> > > > +  I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> >> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize;
> >> > >
> >> > > Please get rid of this hardcoded base address and use
> NonDiscoverable
> >> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> >> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> >> > > for example.
> >> > >
> >> > I have checked SynQuacer code and i dont see its adding much
> advantage.
> >>
> >> What it gives is the ability to cover more than one controller by this
> >> driver, regardless of whether you need it for this particular platform
> >> port or not.
> >>
> > Current board needs one controller.
> 
> It is not about what the board wants. It is about reusing code.
> 
Ideally, we should reuse as much as possible,

> If you implemented a driver using the UEFI driver model, you get all
> the binding machinery for free, and you only need to declare the
> existence of a controller and the core will bind and discover drivers.

But in case of this particular driver, even if we are using UEFI driver model. 
Then from code perspective more or less, we need same code to declare i2c master
Protocol.

> This also allows you to unbind a driver from a single controller, for
> instance, and keeping the other connections alive.
> 


I don't see any case in which we need to unbind driver for i2c.

Coming back to implementation part,  there are some 
advantages using UEFI driver mo

Re: [edk2] [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver

[Meenakshi Aggarwal]

Hi Leif

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Monday, April 23, 2018 2:08 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
> 
> On Mon, Apr 23, 2018 at 08:21:22AM +, Meenakshi Aggarwal wrote:
> > > > +/**
> > > > +  Function to read data using i2c bus
> > > > +
> > > > +  @param   I2cBus  I2c Controller number
> > > > +  @param   ChipAddress of slave device from where data to 
> > > > be
> read
> > > > +  @param   Offset  Offset of slave memory
> > > > +  @param   AlenAddress length of slave
> > > > +  @param   Buffer  A pointer to the destination buffer for the 
> > > > data
> > > > +  @param   Len Length of data to be read
> > > > +
> > > > +  @retval  EFI_NOT_READY   Arbitration lost
> > > > +  @retval  EFI_TIMEOUT Failed to initialize data transfer in
> predefined
> > > time
> > > > +  @retval  EFI_NOT_FOUND   ACK was not recieved
> > > > +  @retval  EFI_SUCCESS Read was successful
> > > > +
> > > > +**/
> > > > +STATIC
> > > > +EFI_STATUS
> > > > +I2cDataRead (
> > > > +  IN  UINT32   I2cBus,
> > > > +  IN  UINT8Chip,
> > > > +  IN  UINT32   Offset,
> > > > +  IN  UINT32   Alen,
> > > > +  IN  UINT8*Buffer,
> > > > +  IN  UINT32   Len
> > > > +  )
> > > > +{
> > > > +  EFI_STATUS   Status;
> > > > +  UINT32   Temp;
> > > > +  INT32I;
> > > > +  I2C_REGS *I2cRegs;
> > > > +
> > > > +  I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize;
> > >
> > > Please get rid of this hardcoded base address and use NonDiscoverable
> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> > > for example.
> > >
> > I have checked SynQuacer code and i dont see its adding much advantage.
> 
> What it gives is the ability to cover more than one controller by this
> driver, regardless of whether you need it for this particular platform
> port or not.
> 
Current board needs one controller.
In case of multiple controller, we can use a loop to install multiple protocols 
and 
If needed then our preference would be to use I2c enumeration protocol. 
This will allow to use correct controller for connected devices. 

With sample implementation of SynQuacer code, 
Please advise, how a right controller is being connected to driver 
e.g. we are registering two controllers mI2c0Desc and mI2c1Desc and 
both are exporting same protocols.
Its user, RTC lib just checking  gEfiI2cMasterProtocolGuid. There is 
possibility 
to connect with any of the controller. I dont see in code where it is assuring 
connection with right controller.
And how we can assure we are connecting to the correct controller.

> > There also base address is hard coded SYNQUACER_I2C1_BASE in
> > PlatformDxe driver.
> 
> Yes, the PlatformDxe driver statically instantiates dynamic drivers
> for non-discoverable buses. But there is no longer any hard-coded
> addresses in the device driver itself.
> 
> /
> Leif
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Re: [edk2] [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Tuesday, April 17, 2018 10:07 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
> 
> On Fri, Feb 16, 2018 at 02:20:01PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > I2C driver produces gEfiI2cMasterProtocolGuid which can be
> > used by other modules.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  Silicon/NXP/Drivers/I2cDxe/I2cDxe.c   | 726
> ++
> >  Silicon/NXP/Drivers/I2cDxe/I2cDxe.h   |  65 +++
> >  Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf |  55 +++
> >  3 files changed, 846 insertions(+)
> >  create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> >  create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> >  create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> >
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > new file mode 100644
> > index 000..80a8826
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > @@ -0,0 +1,726 @@
> > +/** I2cDxe.c
> > +  I2c driver APIs for read, write, initialize, set speed and reset
> > +
> > +  Copyright 2017 NXP
> > +
> > +  This program and the accompanying materials
> > +  are licensed and made available under the terms and conditions of the
> BSD License
> > +  which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cf09845
> 08e3e6425a971708d5a48171ca%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636595798265709617=lqPp%2BaHIRYNO%2B9buGRqcgvffpW
> nWzpIEpeLwdxPhZAk%3D=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#include "I2cDxe.h"
> > +
> > +STATIC CONST UINT16 ClkDiv[60][2] = {
> > +  { 20,  0x00 }, { 22, 0x01 },  { 24, 0x02 },  { 26, 0x03 },
> > +  { 28,  0x04 }, { 30,  0x05 }, { 32,  0x09 }, { 34, 0x06 },
> > +  { 36,  0x0A }, { 40, 0x07 },  { 44, 0x0C },  { 48, 0x0D },
> > +  { 52,  0x43 }, { 56,  0x0E }, { 60, 0x45 },  { 64, 0x12 },
> > +  { 68,  0x0F }, { 72,  0x13 }, { 80,  0x14 }, { 88,  0x15 },
> > +  { 96,  0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> > +  { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> > +  { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> > +  { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> > +  { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> > +  { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> > +  { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
> > +  { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> > +  { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> > +  { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
> > +};
> > +
> > +/**
> > +  Calculate and return proper clock divider
> > +
> > +  @param  Rate   clock rate
> > +
> > +  @retval ClkDiv Value used to get frequency divider value
> > +
> > +**/
> > +STATIC
> > +UINT8
> > +GetClkDiv (
> > +  IN  UINT32 Rate
> > +  )
> > +{
> > +  UINTN  ClkRate;
> > +  UINT32 Div;
> > +  UINT8  ClkDivx;
> > +
> > +  ClkRate = GetBusFrequency ();
> > +
> > +  Div = (ClkRate + Rate - 1) / Rate;
> > +
> > +  if (Div < ClkDiv[0][0]) {
> > +ClkDivx = 0;
> > +  } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
> > +ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
> > +  } else {
> > +for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
> > +  }
> > +
> > +  return ClkDivx;
> > +}
> > +
> > +/**
> > +  Function us

Re: [edk2] [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, April 19, 2018 7:17 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>; Vabhav Sharma
> <vabhav.sha...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for
> PCF2129 Real Time Clock Library
> 
> On Thu, Apr 19, 2018 at 12:33:50PM +, Meenakshi Aggarwal wrote:
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +LibSetTime (
> > > > +  IN EFI_TIME*Time
> > > > +  )
> > > > +{
> > > > +  UINT8   Buffer[8];
> > > > +  UINT8   Index;
> > > > +  EFI_STATUS  Status;
> > > > +  RTC_I2C_REQUEST Req;
> > > > +  UINT8   RtcRegAddr;
> > > > +
> > > > +  Index = 0;
> > > > +  Status = EFI_SUCCESS;
> > > > +  RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> > > > +
> > > > +  if (mI2cMaster == NULL) {
> > > > +return EFI_DEVICE_ERROR;
> > > > +  }
> > > > +
> > > > +  // start register address
> > > > +  Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> > > > +
> > > > +  // hours, minutes and seconds
> > > > +  Buffer[Index++] = DecimalToBcd8 (Time->Second);
> > > > +  Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> > > > +  Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> > > > +  Buffer[Index++] = DecimalToBcd8 (Time->Day);
> > > > +  Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
> > >
> > > Why mask at the call site?
> > >
> > In GetTime function, data is been read from RTC device so we need to
> > mask the unnecessary bits
> > [as described in RTC registers] while
> > In SetTime, we are receiving the appropriate buffer so no need to
> > mask the data.
> 
> But EfiTimeToWday returns an integer in the range 0-6:
>   return (EpochDays + 4) % 7;
> 
> Anding the result of that with 0x7 has no effect.
> 
I will check this.
> /
> Leif
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Re: [edk2] [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, April 19, 2018 3:42 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>; Vabhav Sharma
> <vabhav.sha...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for
> PCF2129 Real Time Clock Library
> 
> On Fri, Feb 16, 2018 at 02:20:15PM +0530, Meenakshi wrote:
> > From: Vabhav <vabhav.sha...@nxp.com>
> >
> > Library to provide functions for NXP pcf2129 real time clock library
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav <vabhav.sha...@nxp.com>
> > ---
> >  Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h |  43 +++
> >  Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c  | 330
> +
> >  .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf|  47 +++
> >  3 files changed, 420 insertions(+)
> >  create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> >  create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> >  create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> >
> > diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> > new file mode 100644
> > index 000..735f697
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> > @@ -0,0 +1,43 @@
> > +/** Pcf2129Rtc.h
> > +*
> > +*  Copyright 2017 NXP
> > +*
> > +*  This program and the accompanying materials
> > +*  are licensed and made available under the terms and conditions of the
> BSD License
> > +*  which accompanies this distribution.  The full text of the license may 
> > be
> found at
> > +*
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cac3a81
> 31870a4f555cbc08d5a5ddfdc8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597295251146941=WheF7lR6B7iBUJBG2TGfGzJoiVhO%2F
> I1VZywt3l%2FeXug%3D=0
> > +*
> > +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __PCF2129RTC_H__
> > +#define __PCF2129RTC_H__
> > +
> > +/*
> > + * RTC register addresses
> > + */
> > +#define PCF2129_CTRL1_REG_ADDR  0x00  // Control Register 1
> > +#define PCF2129_CTRL2_REG_ADDR  0x01  // Control Register 2
> > +#define PCF2129_CTRL3_REG_ADDR  0x02  // Control Register 3
> > +#define PCF2129_SEC_REG_ADDR0x03
> > +#define PCF2129_MIN_REG_ADDR0x04
> > +#define PCF2129_HR_REG_ADDR 0x05
> > +#define PCF2129_DAY_REG_ADDR0x06
> > +#define PCF2129_WEEKDAY_REG_ADDR0x07
> > +#define PCF2129_MON_REG_ADDR0x08
> > +#define PCF2129_YR_REG_ADDR 0x09
> > +
> > +#define PCF2129_CTRL3_BIT_BLF   BIT2/* Battery Low Flag*/
> > +
> > +// Define EPOCH (1998-JANUARY-01) in the Julian Date representation
> > +#define EPOCH_JULIAN_DATE   2450815
> > +
> > +typedef struct {
> > +  UINTN   OperationCount;
> > +  EFI_I2C_OPERATION   SetAddressOp;
> > +  EFI_I2C_OPERATION   GetSetDateTimeOp;
> > +} RTC_I2C_REQUEST;
> > +
> > +#endif // __PCF2129RTC_H__
> > diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> > new file mode 100644
> > index 000..2e21014
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> > @@ -0,0 +1,330 @@
> > +/** @PCF2129RtcLib.c
> > +  Implement EFI RealTimeClock with runtime services via RTC Lib for
> PCF2129 RTC.
> > +
> > +  Based on RTC implementation available in
> > +  EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> > +
> > +  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> > +  Copyright 2017 NXP
> > +
> > +  This program and the accompanying materials
> > +  are licensed and made available under the terms and conditions of the
> BSD License
> > +  which accompanies this distribution.  The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
&

Re: [edk2] [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package.

[Meenakshi Aggarwal]

Yes, it needs changes corresponding to commit 
6281a2ed3bb3ffe57ed54cabd9a31dcf13b415f8.


> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, April 19, 2018 3:25 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for
> LS1043aRDB package.
> 
> On Fri, Feb 16, 2018 at 02:20:13PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> 
> Will this one require any changes to build (and work correctly)
> against current edk2?
> 
> If not:
> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> 
> /
> Leif
> 
> > ---
> >  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16
> +++-
> >  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf |  9 -
> >  2 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index df4d917..7708e0a 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -41,6 +41,7 @@
> >IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> >BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> >FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> > +  NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> >
> >  [PcdsFixedAtBuild.common]
> >
> > @@ -70,6 +71,13 @@
> >gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> >gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|10
> >
> > +  #
> > +  # NV Storage PCDs.
> > +  #
> > +  gArmTokenSpaceGuid.PcdVFPEnabled|1
> > +  gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x06000
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x6030
> > +
> >
> ##
> ##
> >  #
> >  # Components Section - list of all EDK II Modules needed by this Platform
> > @@ -79,9 +87,15 @@
> >#
> ># Architectural Protocols
> >#
> > -
> MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime
> Dxe.inf
> > +
> > +
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
> > + 
> > + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> > +  }
> > +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> >
> >Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> >Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > +  Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> >
> >   ##
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > index fa6510c..6b5b63f 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > @@ -55,6 +55,7 @@
> gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> >  FV = FVMAIN_COMPACT
> >
> >  !include ../FVRules.fdf.inc
> > +!include VarStore.fdf.inc
> >
> ##
> ##
> >  #
> >  # FV Section
> > @@ -103,7 +104,8 @@ READ_LOCK_STATUS   = TRUE
> >INF
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> >INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> >INF
> EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter
> .inf
> > -  INF
> MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime
> Dxe.inf
> > +  INF
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> > +  INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> >INF
> MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntime
> Dxe.inf
> >
> >INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > @@ -123,6 +125,11 @@ READ_LOCK_STATUS   = TRUE
> >INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> >
> >#
> > +  # NOR Driver
> > +  #
> > +  INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> > +
> > +  #
> ># Network modules
> >#
> >INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> > --
> > 1.9.1
> >
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Re: [edk2] [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, April 19, 2018 3:31 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>; Vabhav Sharma
> <vabhav.sha...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB
> SoCLib Support
> 
> On Fri, Feb 16, 2018 at 02:20:14PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > On LS1046A NXP SoC,Provide Functions to initialize peripherals
> > ,print board, soc information.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav <vabhav.sha...@nxp.com>
> > ---
> >  Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc |  1 +
> >  Silicon/NXP/Chassis/Chassis.c|  1 +
> >  Silicon/NXP/Chassis/Chassis.h|  1 +
> >  Silicon/NXP/Chassis/Chassis2/Soc.c   | 51 -
> >  Silicon/NXP/Chassis/LS1043aSocLib.inf|  2 +
> >  Silicon/NXP/Chassis/LS1046aSocLib.inf| 51 +
> >  Silicon/NXP/LS1046A/Include/SocSerDes.h  | 55
> ++
> >  Silicon/NXP/LS1046A/LS1046A.dec  | 22 +
> >  Silicon/NXP/LS1046A/LS1046A.dsc  | 68
> 
> >  Silicon/NXP/NxpQoriqLs.dec   |  2 +
> >  10 files changed, 253 insertions(+), 1 deletion(-)
> >  create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
> >  create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> >  create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> >  create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
> >
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index 7708e0a..b2b514e 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -59,6 +59,7 @@
> >gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> >gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> >gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> > +  gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
> >
> >#
> ># I2C controller Pcds
> > diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> > index 9f2928b..ce07fdc 100644
> > --- a/Silicon/NXP/Chassis/Chassis.c
> > +++ b/Silicon/NXP/Chassis/Chassis.c
> > @@ -44,6 +44,7 @@ GurRead (
> >   */
> >  STATIC CPU_TYPE CpuTypeList[] = {
> >CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> > +  CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> >  };
> >
> >  /*
> > diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> > index 4bdb4d0..0beb44c 100644
> > --- a/Silicon/NXP/Chassis/Chassis.h
> > +++ b/Silicon/NXP/Chassis/Chassis.h
> > @@ -56,6 +56,7 @@ CpuMaskNext (
> >
> >  #define SVR_WO_E0xFE
> >  #define SVR_LS1043A 0x879200
> > +#define SVR_LS1046A 0x870700
> >
> >  #define SVR_MAJOR(svr)  (((svr) >> 4) & 0xf)
> >  #define SVR_MINOR(svr)  (((svr) >> 0) & 0xf)
> > diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c
> b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > index 17de7e4..658df2d 100644
> > --- a/Silicon/NXP/Chassis/Chassis2/Soc.c
> > +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > @@ -17,6 +17,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -139,6 +140,44 @@ GetSysInfo (
> >  }
> >
> >  /**
> > +   Function to select pins depending upon pcd using supplemental
> > +   configuration unit(SCFG) extended RCW controlled pinmux control
> > +   register which contains the bits to provide pin multiplexing control.
> > +   This register is reset on HRESET.
> > + **/
> > +VOID
> > +ConfigScfgMux (VOID)
> > +{
> > +  CCSR_SCFG *Scfg;
> > +  UINT32 UsbPwrFault;
> > +
> > +  Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
> > +  // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> > +  // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> > +
> > +  // LS1043A
> > +  // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
> > +  // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
> > 

Re: [edk2] [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Wednesday, April 18, 2018 11:45 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 03/39] SocLib : Add support for
> initialization of peripherals
> 
> On Wed, Apr 18, 2018 at 04:38:22PM +, Meenakshi Aggarwal wrote:
> > > > +
> > > > +/*
> > > > + * Returns the bit mask for a bit index from 0 to 31
> > > > + */
> > > > +#define BIT(_BitIndex) (0x1u << (_BitIndex))
> > >
> > > I don't see these being used for anything other than setting up BIT1
> > > BIT2 BIT3 and so on. We already have those in Base.h.
> > >
> > In Base.h, we have BIT1, BIT2 defined, here the requirement is to
> > get set bit on basis of bit number, bit is not known in advance.
> 
> Ah, I missed the uses in SerDes.c and saw only the ones in UsbHcd.h
> (which could use the Base.h defines).
> 
> But does it really simplify anything in SerDes.c?
> 
>   *SerDesPrtclMap |= BIT (LanePrtcl);
> 
> is no clearer to me than
> 
>   *SerDesPrtclMap |= (1u << LanePrtcl);
> 
This can also be used.

> Best Regards,
> 
> Leif
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Re: [edk2] [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals

[Meenakshi Aggarwal]

Hi Leif,

Thanks for review, responses inlined.

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Wednesday, April 18, 2018 8:42 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 03/39] SocLib : Add support for
> initialization of peripherals
> 
> On Fri, Feb 16, 2018 at 02:19:59PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > Add SocInit function that initializes peripherals
> > and print board and soc information.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  Silicon/NXP/Chassis/Chassis.c | 388
> ++
> >  Silicon/NXP/Chassis/Chassis.h | 144 +++
> >  Silicon/NXP/Chassis/Chassis2/Chassis2.dec |  19 ++
> >  Silicon/NXP/Chassis/Chassis2/SerDes.h |  68 ++
> >  Silicon/NXP/Chassis/Chassis2/Soc.c| 172 +
> >  Silicon/NXP/Chassis/Chassis2/Soc.h| 367
> 
> >  Silicon/NXP/Chassis/LS1043aSocLib.inf |  47 
> >  Silicon/NXP/Chassis/SerDes.c  | 271 +
> >  Silicon/NXP/Include/Bitops.h  | 179 ++
> >  Silicon/NXP/LS1043A/Include/SocSerDes.h   |  55 +
> >  10 files changed, 1710 insertions(+)
> >  create mode 100644 Silicon/NXP/Chassis/Chassis.c
> >  create mode 100644 Silicon/NXP/Chassis/Chassis.h
> >  create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> >  create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
> >  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
> >  create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
> >  create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
> >  create mode 100644 Silicon/NXP/Chassis/SerDes.c
> >  create mode 100644 Silicon/NXP/Include/Bitops.h
> >  create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> >
> > diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> > new file mode 100644
> > index 000..9f2928b
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis.c
> > @@ -0,0 +1,388 @@
> > +/** @file
> > +  SoC specific Library containg functions to initialize various SoC
> components
> > +
> > +  Copyright 2017 NXP
> > +
> > +  This program and the accompanying materials
> > +  are licensed and made available under the terms and conditions of the
> BSD License
> > +  which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#include "Chassis.h"
> > +
> > +UINT32
> > +EFIAPI
> > +GurRead (
> > +  IN  UINTN Address
> > +  )
> > +{
> > +  if (FixedPcdGetBool (PcdGurBigEndian)) {
> > +return BeMmioRead32 (Address);
> > +  } else {
> > +return MmioRead32 (Address);
> > +  }
> > +}
> 
> So, since this pattern is being repeated in multiple modules, I think
> it would make sense to have (for now) an NXP-specific helper library
> to return a struct of function pointers accessing either
> 
> I.e. something like (in a header)
> 
> typedef struct _MMIO_OPERATIONS {
>   MMIO_WRITE_8 Write8;
>   ...
> } MMIO_OPERATIONS;
> 
> and then in the .c file:
> 
> STATIC MMIO_OPERATIONS SwappingFunctions = {
>   SwapMmioWrite8,
>   ...
> };
> 
> STATIC MMIO_OPERATIONS NonSwappingFunctions = {
>   MmioWrite8,
>   ...
> };
> 
> MMIO_OPERATIONS *GetMmioOperationsStructure (BOOL BigEndian)
> {
>   if (BigEndian) {
> return 
>   else {
> return 
>   }
> }
&g

[edk2] [PATCH edk2-platforms [Changes Suggested by Leif]] Silicon/NXP : Add support for Watchdog driver

[Meenakshi Aggarwal]

Installs watchdog timer arch protocol

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
---
 Silicon/NXP/Drivers/WatchDog/WatchDog.c  | 422 +++
 Silicon/NXP/Drivers/WatchDog/WatchDog.h  |  46 +++
 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf |  47 +++
 3 files changed, 515 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf

diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c 
b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
new file mode 100644
index 000..9d73823
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
@@ -0,0 +1,422 @@
+/** WatchDog.c
+*
+*  Based on Watchdog driver implemenation available in
+*  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
+*
+*  Copyright 2017 NXP
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "WatchDog.h"
+
+STATIC EFI_EVENT  EfiExitBootServicesEvent;
+STATIC EFI_EVENT  WdogFeedEvent;
+STATIC WDOG_OPERATION WdogOps;
+
+STATIC
+VOID
+SetUpWdogOps (
+  )
+{
+  if (FixedPcdGetBool (PcdWdogBigEndian)) {
+WdogOps.WdogRead = BeMmioRead16;
+WdogOps.WdogWrite = BeMmioWrite16;
+WdogOps.WdogAndThenOr= BeMmioAndThenOr16;
+WdogOps.WdogOr = BeMmioOr16;
+  } else {
+WdogOps.WdogRead = MmioRead16;
+WdogOps.WdogWrite = MmioWrite16;
+WdogOps.WdogAndThenOr= MmioAndThenOr16;
+WdogOps.WdogOr = MmioOr16;
+  }
+
+  return;
+}
+
+STATIC
+VOID
+WdogPing (
+  VOID
+  )
+{
+  //
+  // To reload a timeout value to the counter the proper service sequence 
begins by
+  // writing 0x_ followed by 0x_ to the Watchdog Service Register 
(WDOG_WSR).
+  // This service sequence will reload the counter with the timeout value 
WT[7:0] of
+  // Watchdog Control Register (WDOG_WCR).
+  //
+
+  WdogOps.WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ1);
+  WdogOps.WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ2);
+}
+
+/**
+  Stop the Wdog watchdog timer from counting down.
+**/
+STATIC
+VOID
+WdogStop (
+  VOID
+  )
+{
+  // Watchdog cannot be disabled by software once started.
+  // At best, we can keep reload counter with maximum value
+
+  WdogOps.WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+(UINT16)(~WDOG_WCR_WT),
+(WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+  WdogPing ();
+}
+
+/**
+  Starts the Wdog counting down by feeding Service register with
+  desired pattern.
+  The count down will start from the value stored in the Load register,
+  not from the value where it was previously stopped.
+**/
+STATIC
+VOID
+WdogStart (
+  VOID
+  )
+{
+  //Reload the timeout value
+  WdogPing ();
+}
+
+/**
+On exiting boot services we must make sure the Wdog Watchdog Timer
+is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+ExitBootServicesEvent (
+  IN EFI_EVENT  Event,
+  IN VOID   *Context
+  )
+{
+  WdogStop ();
+}
+
+/**
+  This function registers the handler NotifyFunction so it is called every time
+  the watchdog timer expires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.
+  If NotifyFunction is not NULL and a handler is not already registered,
+  then the new handler is registered and EFI_SUCCESS is returned.
+  If NotifyFunction is NULL, and a handler is already registered,
+  then that handler is unregistered.
+  If an attempt is made to register a handler when a handler is already 
registered,
+  then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.
+
+  @param  This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param  NotifyFunction   The function to call when a timer interrupt fires. 
This
+   function executes at TPL_HIGH_LEVEL. The DXE Core 
will
+   register a handler for the timer interrupt, so it 
can know
+   how much time has passed. This information is used 
to
+   signal timer based events. NULL will unregister the 
handler.
+
+  @retval EFI_SUCCESS   The watchdog timer handler was registered.
+  @retval EFI_ALREADY_STARTED   NotifyFunction is not N

[edk2] [PATCH edk2-platforms [Changes Suggested by Leif]] Watchdog Driver Patch

[Meenakshi Aggarwal]

Replace Mmio R/W functions with function pointer as
these can be little or big endian for Watchdog device.

Meenakshi Aggarwal (1):
  Silicon/NXP : Add support for Watchdog driver

 Silicon/NXP/Drivers/WatchDog/WatchDog.c  | 422 +++
 Silicon/NXP/Drivers/WatchDog/WatchDog.h  |  46 +++
 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf |  47 +++
 3 files changed, 515 insertions(+)
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
 create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf

-- 
1.9.1

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Re: [edk2] ShellPkg: reconnect command resulted in hang

[Meenakshi Aggarwal]

Thanks Jaben for your reply.

It is helpful information.

Regards,
Meenakshi

> -Original Message-
> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> Sent: Thursday, March 08, 2018 9:07 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; edk2-
> de...@lists.01.org
> Subject: RE: ShellPkg: reconnect command resulted in hang
> 
> The rest of the drivers needed for console input are not connecting.
> 
> The shell is dependent on the devices in the system table it was initialized
> with for console functionality.  Only when everything was disconnected does
> it know to force those to reconnect.  Otherwise you have to get it right
> yourself.
> 
> If you look at the connect command you see the "-c" option to force EFI
> variable consoles to be reconnected properly.  That doesn't exist in
> reconnect, but you can get around that with a script file.  You probably want
> to do something like:
> 
> Disconnect 20
> Connect 20 -c
> 
> 
> -Jaben
> 
> 
> 
> > -Original Message-
> > From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> > Sent: Thursday, March 08, 2018 7:27 AM
> > To: Carsey, Jaben <jaben.car...@intel.com>; edk2-devel@lists.01.org
> > Subject: RE: ShellPkg: reconnect command resulted in hang
> > Importance: High
> >
> > Yes, i am connected to the device using this serial port.
> >
> > > -Original Message-
> > > From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> > > Sent: Thursday, March 08, 2018 8:50 PM
> > > To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; edk2-
> > > de...@lists.01.org
> > > Subject: RE: ShellPkg: reconnect command resulted in hang
> > >
> > > Are you using this serial port? Are you connected to the device via this
> > serial
> > > port?
> > >
> > > > -Original Message-
> > > > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
> Of
> > > > Meenakshi Aggarwal
> > > > Sent: Thursday, March 08, 2018 1:35 AM
> > > > To: edk2-devel@lists.01.org
> > > > Subject: [edk2] ShellPkg: reconnect command resulted in hang
> > > > Importance: High
> > > >
> > > > Hi,
> > > >
> > > >
> > > > I was trying reconnect shell command with UART handle [20]
> > > >
> > > > 20 R - -  0  1   1 VenHw(D3987D4B-971A-435F-8CAF-
> > > > 4967EB627241)/Uart(115200,8,N,1)
> > > >
> > > > Shell> reconnect 20
> > > >
> > > > After this reconnect command, shell didnt come back, looks like a hang.
> > > > I analyzed further and see that code has executed completely and
> > reached
> > > > to shell but console is not coming.
> > > >
> > > >
> > > > In "reconnect -r" , we are calling ConnectAllConsoles() separately
> > between
> > > > disconnect and connect calls.
> > > >
> > > > Why is this so?
> > > >
> > > > Why only connect call is nt sufficient to bring the console up?
> > > >
> > > > Please help me in understanding this.
> > > >
> > > >
> > > > Thanks,
> > > > Meenakshi
> > > >
> > > >
> > > > ___
> > > > edk2-devel mailing list
> > > > edk2-devel@lists.01.org
> > > >
> > >
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > > s.01.org%2Fmailman%2Flistinfo%2Fedk2-
> > >
> >
> devel=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C230f90d310a
> > >
> >
> 9476a24cc08d585080ef4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%
> > >
> >
> 7C636561192036205272=6pvDPfpdDAvpKVB%2BhD7xRov7Rq6x68NhG
> > > HeL1XRZoFE%3D=0
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Re: [edk2] ShellPkg: reconnect command resulted in hang

[Meenakshi Aggarwal]

Yes, i am connected to the device using this serial port.

> -Original Message-
> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> Sent: Thursday, March 08, 2018 8:50 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; edk2-
> de...@lists.01.org
> Subject: RE: ShellPkg: reconnect command resulted in hang
> 
> Are you using this serial port? Are you connected to the device via this 
> serial
> port?
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Meenakshi Aggarwal
> > Sent: Thursday, March 08, 2018 1:35 AM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] ShellPkg: reconnect command resulted in hang
> > Importance: High
> >
> > Hi,
> >
> >
> > I was trying reconnect shell command with UART handle [20]
> >
> > 20 R - -  0  1   1 VenHw(D3987D4B-971A-435F-8CAF-
> > 4967EB627241)/Uart(115200,8,N,1)
> >
> > Shell> reconnect 20
> >
> > After this reconnect command, shell didnt come back, looks like a hang.
> > I analyzed further and see that code has executed completely and reached
> > to shell but console is not coming.
> >
> >
> > In "reconnect -r" , we are calling ConnectAllConsoles() separately between
> > disconnect and connect calls.
> >
> > Why is this so?
> >
> > Why only connect call is nt sufficient to bring the console up?
> >
> > Please help me in understanding this.
> >
> >
> > Thanks,
> > Meenakshi
> >
> >
> > ___
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> >
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.01.org%2Fmailman%2Flistinfo%2Fedk2-
> devel=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C230f90d310a
> 9476a24cc08d585080ef4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%
> 7C636561192036205272=6pvDPfpdDAvpKVB%2BhD7xRov7Rq6x68NhG
> HeL1XRZoFE%3D=0
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[edk2] ShellPkg: reconnect command resulted in hang

[Meenakshi Aggarwal]

Hi,


I was trying reconnect shell command with UART handle [20]

20 R - -  0  1   1 
VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)

Shell> reconnect 20

After this reconnect command, shell didnt come back, looks like a hang.
I analyzed further and see that code has executed completely and reached to 
shell but console is not coming.


In "reconnect -r" , we are calling ConnectAllConsoles() separately between 
disconnect and connect calls.

Why is this so?

Why only connect call is nt sufficient to bring the console up?

Please help me in understanding this.


Thanks,
Meenakshi


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Re: [edk2] [PATCH v4 0/2] quirks handling for SDHCI controllers

[Meenakshi Aggarwal]

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Tuesday, March 06, 2018 4:41 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: edk2-devel@lists.01.org
> Subject: Re: [edk2] [PATCH v4 0/2] quirks handling for SDHCI controllers
> 
> On 6 March 2018 at 05:14, Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com> wrote:
> > Hi,
> >
> > I am using Mmc Driver implemented in "
> EmbeddedPkg/Universal/MmcDxe/" for my SD/MMC controller and my
> controller is not on PCI bus.
> >
> > I am a bit confused if i should move to SD implementation available in
> 'MdeModulePkg\Bus\Pci\SdMmcPciHcDxe".
> >
> > Please suggest.
> >
> 
> It really depends on whether the IP is SDHCI compatible or not.

Thanks for reply Ard, its not SDHCI compatible, so i guess no additional 
advantage in moving to 'MdeModulePkg\Bus\Pci\SdMmcPciHcDxe' for my IP.
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Re: [edk2] [PATCH v4 0/2] quirks handling for SDHCI controllers

[Meenakshi Aggarwal]

Hi,

I am using Mmc Driver implemented in " EmbeddedPkg/Universal/MmcDxe/" for my 
SD/MMC controller and my controller is not on PCI bus.

I am a bit confused if i should move to SD implementation available in 
'MdeModulePkg\Bus\Pci\SdMmcPciHcDxe".

Please suggest.


Thanks,
Meenakshi

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Ard Biesheuvel
> Sent: Tuesday, January 30, 2018 3:22 PM
> To: Zeng, Star 
> Cc: Ni, Ruiyu ; Tian, Feng ; Wu,
> Hao A ; edk2-devel@lists.01.org;
> leif.lindh...@linaro.org; Kinney, Michael D 
> Subject: Re: [edk2] [PATCH v4 0/2] quirks handling for SDHCI controllers
> 
> On 30 January 2018 at 01:24, Zeng, Star  wrote:
> > Reviewed-by: Star Zeng 
> >
> > Thanks Hao's investigation and Ard's contribution.
> >
> 
> Thanks all
> 
> Pushed as 864701886fc3..b23fc39cd3c3
> 
> >
> > Star
> > -Original Message-
> > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> > Sent: Monday, January 29, 2018 4:26 PM
> > To: Wu, Hao A ; Zeng, Star ;
> Ni, Ruiyu 
> > Cc: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Kinney, Michael D
> ; Tian, Feng 
> > Subject: Re: [PATCH v4 0/2] quirks handling for SDHCI controllers
> >
> > On 29 January 2018 at 05:13, Wu, Hao A  wrote:
> >> One minor comment, please help to remove the line (around line 1067):
> >> @param[in] Capability The capability of the slot.
> >>
> >> within function description comment for SdMmcHcInitHost() in file:
> >> MdeModulePkg\Bus\Pci\SdMmcPciHcDxe\SdMmcPciHci.c
> >>
> >> Other than that, the series is good to me:
> >> Reviewed-by: Hao Wu 
> >>
> >
> > Thank you very much!
> >
> >> Really sorry for the delay.
> >>
> >
> > No worries. Star, Ray, any more comments from your side?
> >
> >
> >>
> >>> -Original Message-
> >>> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> >>> Sent: Friday, December 08, 2017 6:43 AM
> >>> To: edk2-devel@lists.01.org
> >>> Cc: leif.lindh...@linaro.org; Kinney, Michael D; Zeng, Star; Tian,
> >>> Feng; Ni, Ruiyu; Wu, Hao A; Ard Biesheuvel
> >>> Subject: [PATCH v4 0/2] quirks handling for SDHCI controllers
> >>>
> >>> Many SDHCI implementations exist that are almost spec complicant, and
> >>> could be driven by the generic SD/MMC host controller driver except
> >>> for some minimal necessary init time tweaks.
> >>>
> >>> Adding such tweaks to the generic driver is undesirable. On the other
> >>> hand, forking the driver for every platform that has such a SDHCI
> >>> controller is problematic when it comes to upstreaming and ongoing
> >>> maintenance (which is arguably the point of upstreaming in the first
> >>> place).
> >>>
> >>> So these patches propose a workaround that is minimally invasive on
> >>> the
> >>> EDK2 side, but gives platforms a lot of leeway when it comes to
> >>> applying SDHCI quirks.
> >>>
> >>> Changes since v3:
> >>> - remove PassThru argument from protocol members: it is unclear
> whether the
> >>>   protocol is available when the override protocol is invoked, and my
> >>>   example use case does not need it
> >>> - replace incorrect HandleProtocol with LocateProtocol, given that the
> override
> >>>   protocol is now a singleton instance
> >>> - merge notifier calls into SdMmcHcReset() and SdMmcHcInitHost (), this
> >>>   required changing the prototype to take a
> SD_MMC_HC_PRIVATE_DATA*
> >>> argument
> >>>   and so the prototypes no longer belong in SdMmcPciHci.h and have
> >>> been moved
> >>>   to SdMmcPciHcDxe.h
> >>> - use VOID* type for capability not UINT64* since we don't know its
> >>> alignment
> >>>
> >>> Changes since v2:
> >>> - use a singleton instance of the SD/MMC protocol rather than one per
> >>>   controller; this is needed to support 'reconnect -r', as pointed out
> >>>   by Ray
> >>> - use EDKII prefixes for all types defined by the protocol
> >>> - replace 'hook' with 'notify', and tweak some other identifiers
> >>> - add missing function comment headers for factored out functions
> >>>
> >>> Changes since RFC/v1:
> >>> - add EFI_SD_MMC_PASS_THRU_PROTOCOL* member to override
> methods
> >>> - use UINT64* not VOID* to pass capability structure (which is always 64
> bits
> >>>   in size)
> >>>
> >>> Ard Biesheuvel (2):
> >>>   MdeModulePkg: introduce SD/MMC override protocol
> >>>   MdeModulePkg/SdMmcPciHcDxe: allow HC capabilities to be
> overridden
> >>>
> >>>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 35
> ++-
> >>>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h   | 36
> 
> >>>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf |  2 +
> >>>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 95
> >>> +--
> >>>  

Re: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet

[Meenakshi Aggarwal]

Hi All,

Any comments on this patch or is it good to go?

Reviewed-by: Jaben Carsey <jaben.car...@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu...@intel.com>

Thanks,
Meenakshi

> -Original Message-
> From: Ni, Ruiyu [mailto:ruiyu...@intel.com]
> Sent: Thursday, February 22, 2018 2:03 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Carsey, Jaben
> <jaben.car...@intel.com>; edk2-devel@lists.01.org; ler...@redhat.com
> Subject: Re: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet
> 
> On 2/20/2018 2:18 PM, Meenakshi Aggarwal wrote:
> > Hi Ray,
> >
> > Please share your comments.
> >
> >
> > Thanks,
> > Meenakshi
> >
> >> -Original Message-
> >> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> >> Sent: Friday, February 16, 2018 8:51 PM
> >> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Ni, Ruiyu
> >> <ruiyu...@intel.com>; edk2-devel@lists.01.org; ler...@redhat.com
> >> Subject: RE: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet
> >>
> >> Seems good to me.  I will let Ray review also.
> >>
> >> Reviewed-by: Jaben Carsey <jaben.car...@intel.com>
> >>
> >>> -Original Message-
> >>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
> Of
> >>> Meenakshi
> >>> Sent: Friday, February 16, 2018 12:45 AM
> >>> To: Ni, Ruiyu <ruiyu...@intel.com>; Carsey, Jaben
> >>> <jaben.car...@intel.com>; edk2-devel@lists.01.org;
> ler...@redhat.com
> >>> Subject: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet
> >>> Importance: High
> >>>
> >>> From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >>>
> >>> Issue:
> >>> Reply for first ping packet was getting dropped.
> >>>
> >>> Cause:
> >>> Sometimes reply message comes even before trasmit
> >>> function returns, hence missing 1st reply
> >>>
> >>> Fix:
> >>> Prepare the TxList before calling Transmit function.
> >>>
> >>> Contributed-under: TianoCore Contribution Agreement 1.1
> >>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >>> ---
> >>>   ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c | 5 -
> >>>   1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >>> b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >>> index bec9535..46ba701 100644
> >>> --- a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >>> +++ b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >>> @@ -784,14 +784,17 @@ PingSendEchoRequest (
> >>> }
> >>>
> >>> ASSERT(Private->ProtocolPointers.Transmit != NULL);
> >>> +
> >>> +  InsertTailList (>TxList, >Link);
> >>> +
> >>> Status = Private->ProtocolPointers.Transmit (Private->IpProtocol,
> TxInfo-
> >>>> Token);
> >>>
> >>> if (EFI_ERROR (Status)) {
> >>> +RemoveEntryList (>Link);
> >>>   PingDestroyTxInfo (TxInfo, Private->IpChoice);
> >>>   return Status;
> >>> }
> >>>
> >>> -  InsertTailList (>TxList, >Link);
> >>> Private->TxCount++;
> >>>
> >>> return EFI_SUCCESS;
> >>> --
> >>> 1.9.1
> >>>
> >>> ___
> >>> edk2-devel mailing list
> >>> edk2-devel@lists.01.org
> >>>
> >>
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >> s.01.org%2Fmailman%2Flistinfo%2Fedk2-
> >>
> devel=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1d7bd63786b
> >>
> 044ba3c9508d57550d50a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> >>
> %7C636543912439710731=Bn%2Febt4emmCvayFNmcKCi3xJuFfV52Vq
> >> 4aQLVSNNti8%3D=0
> Reviewed-by: Ruiyu Ni <ruiyu...@intel.com>
> 
> 
> --
> Thanks,
> Ray
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Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs

[Meenakshi Aggarwal]

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Friday, February 23, 2018 2:51 PM
> To: Pankaj Bansal ; Leif Lindholm
> 
> Cc: michael.d.kin...@intel.com; edk2-devel@lists.01.org;
> ard.biesheu...@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
> 
> On 02/23/18 09:40, Pankaj Bansal wrote:
> > Hi All
> >
> >> -Original Message-
> >> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> >> Laszlo Ersek
> >> Sent: Thursday, February 22, 2018 7:26 PM
> >> To: Leif Lindholm 
> >> Cc: michael.d.kin...@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheu...@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> support
> >> for Big Endian Mmio APIs
> >>
> >> On 02/22/18 12:52, Leif Lindholm wrote:
> >>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>
> > But that brings back the complication as to how we have a driver
> > that needs an LE IO library to write output, and a BE IO library to
> > manipulate the hardware.
> 
>  Can you please explain the "write output" use case more precisely?
> 
>  My thinking would be this:
> 
>  - Use the IoLib class directly for "writing output" in little endian
>  byte order (which is still unclear to me sorry).
> >>>
> >>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
> >>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> >>> end up mapping the non-swapping, currently implemented in
> >>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>> needing to duplicated all IoLib implementation .infs to provide an
> >>> IoLib and a BeIoLib for each?
> >>>
> >>> It's at that point I burst an aneurysm.
> >>> Am I overthinking/underthinking this?
> >>
> >> We need two library classes, one for talking to LE devices and another to
> BE
> >> devices. These should be usable in a given module at the same time, as
> Ard
> >> says.
> >>
> >> Both library classes need to work on both LE and BE CPUs (working from
> your
> >> suggestion that UEFI might grow BE CPU support at some point).
> >> Whether that is implemented by dumb, separate library instances
> (yielding in
> >> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
> library
> >> instances (in total, 2), is a different question.
> >>
> >> Note that such "smarts" could be less than trivial to implement:
> >> - check CPU endianness in each library API?
> >> - or check in the lib constructor only, and flip some function pointers?
> >> - use a dynamic PCD for caching CPU endianness?
> >> - use a HOB for the same?
> >> - use a lib global variable (for caching only on the module level)?
> >>
> >> I think the solution that saves the most on the *source* code size is:
> >> - introduce the BeIoLib class
> >> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >>   BeIoLib instance that we introduce
> >> - modify the MMIO functions in *both* lib instances (original LE, and
> >>   new BE), like this:
> >>
> >>   - If the CPU architecture is known to be bound to a single endianness,
> >> then hardcode the appropriate operation. This can be done with
> >> preprocessor macros, or with the architecture support of INF files /
> >> separate source files. For example, on IA32 and X64, the IoLib
> >> instance should work transparently, unconditionally, and the BeIoLib
> >> instance should byte-swap, unconditionally.
> >>
> >>   - On other CPU arches, all the wider-than-byte MMIO functions, in
> >> *both* lib instances should do something like this:
> >>
> >> //
> >> // at file scope
> >> //
> >> STATIC CONST UINT16 mOne = 1;
> >>
> >> //
> >> // at function scope
> >> //
> >> if (*(CONST UINT8 *) == 1) {
> >>   //
> >>   // CPU in LE mode:
> >>   // - work transparently in the IoLib instance
> >>   // - byte-swap in the BeIoLib instance
> >>   //
> >> } else {
> >>   //
> >>   // CPU in BE mode:
> >>   // - byte-swap in the IoLib instance
> >>   // - work transparently in the BeIoLib instance
> >>   //
> >> }
> >
> > I suggest this approach :
> >
> > 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap
> the input before write and swap output after read and so on.
> > Mmio* functions will not perform any byte swapping
> > 2. create second instance (a copy) of this IoLib for CPUs that are Big 
> > Endian.
> We can call it BigEndianIoLib.
> >  In this library Mmio* functions will swap the input before write and 
> > swap
> output after read and so on.
> >  BeMmio* functions will not perform any byte swapping.
> > 3. Include the instance of IoLib in dsc file based on cpu endianness that 
> > the
> 

Re: [edk2] [PATCH edk2-platforms 09/39] Build : Add build script and environment script

[Meenakshi Aggarwal]

Thanks,
Meenakshi

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Wednesday, February 21, 2018 9:32 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2-
> de...@lists.01.org; Udit Kumar <udit.ku...@nxp.com>; Varun Sethi
> <v.se...@nxp.com>; Wasim Khan <wasim.k...@nxp.com>
> Subject: Re: [PATCH edk2-platforms 09/39] Build : Add build script and
> environment script
> 
> We need to have a tree where we can build all of the platforms in a
> predictable manner, so I am not inclined to take any platform-specific
> build helper scripts.
> 
> (If a platform that needs some special scripts to post-process the
> built image before writing it to a target, that is a different thing.)
> 
> What would be really useful here would be a Readme.md listing the
> platforms supported, with a brief description, and the location of
> their .dsc files (and any option that can be specified on the command
> line at build time).
> 
Yes,

Sounds Valid.

Let me give  a try to same.

> I would be more than happy to add some entries for these platforms to
> (the entirely unofficial) uefi-tools set of helper scripts available
> from
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.
> linaro.org%2Fuefi%2Fuefi-
> tools.git=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d129
> a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C636548257431632170=VHMKWjdfr2FSy8uClW4%2BLeosuVPYpD
> wOYhrIIUop5w0%3D=0.
> 
> (edk2-build.sh in there supports the same sort of 'figure out which
> toolchain profile to use' as these scripts implement)
> 
> Also, feel free to add a link to your Readme.md from
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
> hub.com%2Ftianocore%2Fedk2-platforms%23supported-
> platforms=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d1
> 29a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C0%7C636548257431788421=zrQfMandU%2BpMoSiZhc3R9%2F3vrRK
> 9tF5gMJX%2FgBrt5Lc%3D=0
> 
> /
> Leif
> 
> On Fri, Feb 16, 2018 at 02:20:05PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > Build script and Environment setup script.
> > Readme to explain how to run build script
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
> > ---
> >  Platform/NXP/Env.cshrc |  78 +
> >  Platform/NXP/Readme.md |  17 +++
> >  Platform/NXP/build.sh  | 117
> +
> >  3 files changed, 212 insertions(+)
> >  create mode 100755 Platform/NXP/Env.cshrc
> >  create mode 100644 Platform/NXP/Readme.md
> >  create mode 100755 Platform/NXP/build.sh
> >
> > diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc
> > new file mode 100755
> > index 000..eb51018
> > --- /dev/null
> > +++ b/Platform/NXP/Env.cshrc
> > @@ -0,0 +1,78 @@
> > +#  @file.
> > +#
> > +#  Copyright 2017 NXP
> > +#
> > +#  This program and the accompanying materials are licensed and made
> available under
> > +#  the terms and conditions of the BSD License which accompanies this
> distribution.
> > +#  The full text of the license may be found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d
> 129a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636548257431788421=Ut5kElH5tECkkHPBx53AJD0LeoqScX9w
> 6%2FoMz7eRclU%3D=0
> > +#
> > +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> > +
> > +if [ X"$CROSS_COMPILE_64" != X"" ]; then
> > +  ARM64_PREFIX="$CROSS_COMPILE_64"
> > +elif [ X"$CROSS_COMPILE" != X"" ]; then
> > +  ARM64_PREFIX="$CROSS_COMPILE"
> > +else
> > +  ARM64_PREFIX="aarch64-linux-gnu-"
> > +fi
> > +
> > +GCC_UTILITY="${ARM64_PREFIX}gcc"
> > +CheckGcc=`which $GCC_UTILITY >/dev/null 2>&1`
> > +if [ "$?" -eq 0 ];then
> > +  GCC_VERSION=`$GCC_UTILITY -v 2>&1 | tail -n 1 |

Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs

[Meenakshi Aggarwal]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Thursday, February 22, 2018 12:28 AM
> To: Laszlo Ersek <ler...@redhat.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> michael.d.kin...@intel.com; edk2-devel@lists.01.org;
> ard.biesheu...@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
> 
> On Wed, Feb 21, 2018 at 05:06:02PM +0100, Laszlo Ersek wrote:
> > On 02/21/18 16:46, Leif Lindholm wrote:
> > > Apologies for dropping the ball on this series during my sabbatical.
> > >
> > > For this particular patch, I would still like to see a core library
> > > provide the needed functionality. I just sent out an RFC of a possible
> > > implementation.
> > >
> > > Regardless, a key point is that this isn't about "big-endian", it is
> > > about endianness opposite to the executing processor.
> >
> > I commented on just this aspect under your RFC. I think I disagree, for
> > two reasons:
> >
> > - As long as the specs are LE-only, "endianness opposite to the
> > executing processor" is needless complication / speculative generality
> > in my eyes.
> 
> HTON/NTOH?
> 
> The specs are not LE-only.
> PI _is_ (at this point in time) LE-only.
> UEFI leaves this entirely to architectural bindings.
> 
> For PI, this is mentioned in a single paragraph, repeated 4 times in
> the PI 1.6 specification (due to it merging what was previously
> separate documents).
> 
> > - Even if we supported multiple endiannesses on the CPU front, the API
> > names should reflect the *device* byte order, not the CPU byte order.
> > Think of the case when the same platform device is integrated on board
> > B1 whose CPU is LE, and on board B2 whose CPU is BE.
> 
> The actual watchdog code in this series, and comments made on the
> list, suggests that there exists variants of this _device_ with BE
> or LE byte order.
> 
> If this is not the case, then yes, I agree that BE-naming makes sense.
> 
> So, Meenakshi - can you confirm that the Watchdog driver is expected
> to be used against devices in both BE and LE mode?
> 
Yes Leif,
Watchdog is BE in this series of patches and will be LE for coming SoCs.
In this series, IFC is the example which is in BE mode for LS1043 and LS1046
and LE for LS2088.

> If it is the case, maybe this library would make more sense as the
> non-standard protocol you suggested in
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fw
> ww.mail-archive.com%2Fedk2-
> devel%40lists.01.org%2Fmsg17869.html=02%7C01%7Cmeenakshi.aggar
> wal%40nxp.com%7C3ba61129eca0405466d508d5795d1454%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C636548363050169302=pIcASmlSK
> CD0jsCvEMkKk2ikjSuD19lTa8xErcxaH4Y%3D=0
> ?
> 
> > If we name the APIs
> > after the CPU byte order, then the same driver source code will be
> > misleading on one of the boards. Whereas, if we name the APIs after
> > device byte order, then the driver source code will be correct
> > regardless of board / CPU, and only the internal workings of the APIs
> > should change. For example, on a BE CPU / platform, the "normal" (LE)
> > IoLib class should be resolved to an instance that byte-swaps
> > internally, and the BE IoLib class should be resolved to an instance
> > that is transparent internally.
> 
> Right.
> 
> But that brings back the complication as to how we have a driver that
> needs an LE IO library to write output, and a BE IO library to
> manipulate the hardware.
> 
Yes it is complicated, but we have similar situation. 
> /
> Leif
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Re: [edk2] [PATCH] Tftp assert fix for openfile failure case

[Meenakshi Aggarwal]

Hi Ray,

Please share your thoughts on this.


Thanks,
Meenakshi

> -Original Message-
> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> Sent: Tuesday, February 13, 2018 9:07 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Leif Lindholm
> <leif.lindh...@linaro.org>; Ni, Ruiyu <ruiyu...@intel.com>
> Cc: Ye, Ting <ting...@intel.com>; edk2-devel@lists.01.org; Fu, Siyuan
> <siyuan...@intel.com>; ard.biesheu...@linaro.org
> Subject: RE: [PATCH] Tftp assert fix for openfile failure case
> 
> So I thought we are keeping the command, but I do agree with Leif that
> better error path logic would be good.  We can wait for Ray to confirm if he
> has different plans.
> 
> -Jaben
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Meenakshi Aggarwal
> > Sent: Tuesday, February 13, 2018 7:19 AM
> > To: Carsey, Jaben <jaben.car...@intel.com>; Leif Lindholm
> > <leif.lindh...@linaro.org>; Ni, Ruiyu <ruiyu...@intel.com>
> > Cc: Ye, Ting <ting...@intel.com>; edk2-devel@lists.01.org; Fu, Siyuan
> > <siyuan...@intel.com>; ard.biesheu...@linaro.org
> > Subject: Re: [edk2] [PATCH] Tftp assert fix for openfile failure case
> > Importance: High
> >
> > Jaben,
> >
> > The patch was not accepted last time because as per Leif
> > "
> > > > > > > > This shell command was introduced in the heyday of "let's
> > > > > > > > reimplement U-Boot in the EDK2 tree". Mainly, from my
> > impression,
> > > it
> > > > > > > > seems to be used in order that people don't need to learn how
> > boot
> > > > > > > > managers and device paths work.
> > > > > > >
> > > > > > > When you say about complete boot, then this may not be useful.
> > > > > > >"
> >
> >
> > So, if we are maintaining tftp command, then i will resend the patch with
> > inclusion of one comment of Leif
> > "
> > > > > > > > If the code is to be kept, I think (from a quick glance) that I
> > > > > > > > would also like to see
> > > > > > > >   *Data = NULL
> > > > > > > > in the error path of DownloadFile().
> > "
> >
> > Thanks,
> > Meenakshi
> >
> > > -Original Message-
> > > From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> > > Sent: Tuesday, February 13, 2018 8:44 PM
> > > To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Leif Lindholm
> > > <leif.lindh...@linaro.org>; Ni, Ruiyu <ruiyu...@intel.com>
> > > Cc: ard.biesheu...@linaro.org; Ye, Ting <ting...@intel.com>; edk2-
> > > de...@lists.01.org; Fu, Siyuan <siyuan...@intel.com>; Udit Kumar
> > > <udit.ku...@nxp.com>
> > > Subject: RE: [PATCH] Tftp assert fix for openfile failure case
> > >
> > > Meenakshi,
> > >
> > > The TFTP command is outside the UEFI Shell specification, therefore it is
> > > included as a DynamicCommand, not a command built into the shell itself.
> > >
> > > I a little confused by your last sentence.  Do you want to send a new
> patch?
> > > or do you have a branch to pick changes from ?
> > >
> > > -Jaben
> > >
> > >
> > > > -Original Message-
> > > > From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> > > > Sent: Tuesday, February 13, 2018 1:43 AM
> > > > To: Leif Lindholm <leif.lindh...@linaro.org>; Ni, Ruiyu
> > > <ruiyu...@intel.com>
> > > > Cc: ard.biesheu...@linaro.org; Ye, Ting <ting...@intel.com>; edk2-
> > > > de...@lists.01.org; Carsey, Jaben <jaben.car...@intel.com>; Fu,
> Siyuan
> > > > <siyuan...@intel.com>; Udit Kumar <udit.ku...@nxp.com>
> > > > Subject: RE: [PATCH] Tftp assert fix for openfile failure case
> > > > Importance: High
> > > >
> > > > Hi,
> > > >
> > > > As per commit 0961002352e9115b72f544dded239ad226efe87b
> > > >
> > > > Tftp command will be maintained to extend internal commands and
> > > >
> > > > ShellPkg/DynamicCommand/TftpDynamicCommand/Tftp.c
> > > >
> > > > Looks like a copy of ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > >
> > > > So, below fix is needed in this case 

Re: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet

[Meenakshi Aggarwal]

Hi Ray,

Please share your comments.


Thanks,
Meenakshi

> -Original Message-
> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> Sent: Friday, February 16, 2018 8:51 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Ni, Ruiyu
> <ruiyu...@intel.com>; edk2-devel@lists.01.org; ler...@redhat.com
> Subject: RE: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet
> 
> Seems good to me.  I will let Ray review also.
> 
> Reviewed-by: Jaben Carsey <jaben.car...@intel.com>
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Meenakshi
> > Sent: Friday, February 16, 2018 12:45 AM
> > To: Ni, Ruiyu <ruiyu...@intel.com>; Carsey, Jaben
> > <jaben.car...@intel.com>; edk2-devel@lists.01.org; ler...@redhat.com
> > Subject: [edk2] [RFC] ShellPkg/Ping: fix loss of first packet
> > Importance: High
> >
> > From: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >
> > Issue:
> > Reply for first ping packet was getting dropped.
> >
> > Cause:
> > Sometimes reply message comes even before trasmit
> > function returns, hence missing 1st reply
> >
> > Fix:
> > Prepare the TxList before calling Transmit function.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> > b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> > index bec9535..46ba701 100644
> > --- a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> > +++ b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> > @@ -784,14 +784,17 @@ PingSendEchoRequest (
> >}
> >
> >ASSERT(Private->ProtocolPointers.Transmit != NULL);
> > +
> > +  InsertTailList (>TxList, >Link);
> > +
> >Status = Private->ProtocolPointers.Transmit (Private->IpProtocol, TxInfo-
> > >Token);
> >
> >if (EFI_ERROR (Status)) {
> > +RemoveEntryList (>Link);
> >  PingDestroyTxInfo (TxInfo, Private->IpChoice);
> >  return Status;
> >}
> >
> > -  InsertTailList (>TxList, >Link);
> >Private->TxCount++;
> >
> >return EFI_SUCCESS;
> > --
> > 1.9.1
> >
> > ___
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> > edk2-devel@lists.01.org
> >
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[edk2] Why XIP memory for variable storage?

[Meenakshi Aggarwal]

Hi,


I want to implement Secure Uefi for my SoC and was looking for how keys and 
database were stored in edk2.

What i understood from the code is:
1.  We are using same memory space for storage of Secure and Non-Secure 
variables.
2.  We are assuming memory to be of XIP type.


Please help if above statements are correct and 
I want to use different memories for Secure and Non-Secure variables, 
e.g. i want my secure variables to be managed by my software running in EL3 or 
say a different memory which is not an XIP.


Is something similar exist in edk2 which i can refer?
Is any particular reason behind using XIP memory for variable storage?


Please help.


Thanks & Regards,
Meenakshi
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Re: [edk2] [PATCH] RFC : Ping : Fix for loss of first ping packet

[Meenakshi Aggarwal]

Hi,

I have shared patch with correction in subject.

Please see if it is visible to you now.


Thanks,
Meenakshi

> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Thursday, February 15, 2018 5:59 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> ruiyu...@intel.com; jaben.car...@intel.com; edk2-devel@lists.01.org
> Subject: Re: [edk2] [PATCH] RFC : Ping : Fix for loss of first ping packet
> 
> Hi Meenakshi,
> 
> On 02/15/18 13:08, Meenakshi Aggarwal wrote:
> > Hi,
> >
> > Any comment?
> 
> I don't see your original patch email on the list, either in my personal
> folder, or in the archive at
> <https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
> ts.01.org%2Fpipermail%2Fedk2-devel%2F2018-
> February%2Fthread.html=02%7C01%7Cmeenakshi.aggarwal%40nxp.co
> m%7Cd55e68d82714417526e008d5746faad4%7Cbd8a2a2207224ec7b35f1c4f0
> 497e341%7C0%7C0%7C636542945322839311=OyrBgmxscmLtSjkhrcglD
> A%2BYAPH77IbycKEql759m1s%3D=0>.
> Can you resend?
> 
> Also, I suggest a subject line like:
> 
>   [RFC] ShellPkg/Ping: fix loss of first packet
> 
> In other words, "RFC" should only be in the bracketed part (= the
> subject prefix). You can change the [PATCH] prefix into [RFC] by adding
> 
>   --subject-prefix=RFC
> 
> to the git-format-patch command line.
> 
> Thanks
> Laszlo
> 
> >> -Original Message-
> >> From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> >> Sent: Tuesday, February 13, 2018 8:52 PM
> >> To: ruiyu...@intel.com; jaben.car...@intel.com; edk2-devel@lists.01.org
> >> Cc: Udit Kumar <udit.ku...@nxp.com>; Varun Sethi
> <v.se...@nxp.com>;
> >> Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >> Subject: [PATCH] RFC : Ping : Fix for loss of first ping packet
> >>
> >> Issue:
> >> Reply for first ping packet was getting dropped.
> >>
> >> Cause:
> >> Sometimes reply message comes even before trasmit
> >> function returns, hence missing 1st reply
> >>
> >> Fix:
> >> Prepare the TxList before calling Transmit function.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> >> ---
> >>  ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c | 5 -
> >>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >> b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >> index bec9535..46ba701 100644
> >> --- a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >> +++ b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> >> @@ -784,14 +784,17 @@ PingSendEchoRequest (
> >>}
> >>
> >>ASSERT(Private->ProtocolPointers.Transmit != NULL);
> >> +
> >> +  InsertTailList (>TxList, >Link);
> >> +
> >>Status = Private->ProtocolPointers.Transmit (Private->IpProtocol,
> TxInfo-
> >>> Token);
> >>
> >>if (EFI_ERROR (Status)) {
> >> +RemoveEntryList (>Link);
> >>  PingDestroyTxInfo (TxInfo, Private->IpChoice);
> >>  return Status;
> >>}
> >>
> >> -  InsertTailList (>TxList, >Link);
> >>Private->TxCount++;
> >>
> >>return EFI_SUCCESS;
> >> --
> >> 1.9.1
> >
> > ___
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Re: [edk2] [PATCH] RFC : Ping : Fix for loss of first ping packet

[Meenakshi Aggarwal]

Hi,

Any comment?

Thanks & Regards,
Meenakshi

> -Original Message-
> From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> Sent: Tuesday, February 13, 2018 8:52 PM
> To: ruiyu...@intel.com; jaben.car...@intel.com; edk2-devel@lists.01.org
> Cc: Udit Kumar <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Subject: [PATCH] RFC : Ping : Fix for loss of first ping packet
> 
> Issue:
> Reply for first ping packet was getting dropped.
> 
> Cause:
> Sometimes reply message comes even before trasmit
> function returns, hence missing 1st reply
> 
> Fix:
> Prepare the TxList before calling Transmit function.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> ---
>  ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> index bec9535..46ba701 100644
> --- a/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> +++ b/ShellPkg/Library/UefiShellNetwork1CommandsLib/Ping.c
> @@ -784,14 +784,17 @@ PingSendEchoRequest (
>}
> 
>ASSERT(Private->ProtocolPointers.Transmit != NULL);
> +
> +  InsertTailList (>TxList, >Link);
> +
>Status = Private->ProtocolPointers.Transmit (Private->IpProtocol, TxInfo-
> >Token);
> 
>if (EFI_ERROR (Status)) {
> +RemoveEntryList (>Link);
>  PingDestroyTxInfo (TxInfo, Private->IpChoice);
>  return Status;
>}
> 
> -  InsertTailList (>TxList, >Link);
>Private->TxCount++;
> 
>return EFI_SUCCESS;
> --
> 1.9.1

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Re: [edk2] [PATCH] Tftp assert fix for openfile failure case

[Meenakshi Aggarwal]

Jaben,

The patch was not accepted last time because as per Leif
"
> > > > > > This shell command was introduced in the heyday of "let's
> > > > > > reimplement U-Boot in the EDK2 tree". Mainly, from my impression,
> it
> > > > > > seems to be used in order that people don't need to learn how boot
> > > > > > managers and device paths work.
> > > > >
> > > > > When you say about complete boot, then this may not be useful.
> > > > >"


So, if we are maintaining tftp command, then i will resend the patch with 
inclusion of one comment of Leif
"
> > > > > > If the code is to be kept, I think (from a quick glance) that I
> > > > > > would also like to see
> > > > > >   *Data = NULL
> > > > > > in the error path of DownloadFile().
"

Thanks,
Meenakshi 

> -Original Message-
> From: Carsey, Jaben [mailto:jaben.car...@intel.com]
> Sent: Tuesday, February 13, 2018 8:44 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>; Leif Lindholm
> <leif.lindh...@linaro.org>; Ni, Ruiyu <ruiyu...@intel.com>
> Cc: ard.biesheu...@linaro.org; Ye, Ting <ting...@intel.com>; edk2-
> de...@lists.01.org; Fu, Siyuan <siyuan...@intel.com>; Udit Kumar
> <udit.ku...@nxp.com>
> Subject: RE: [PATCH] Tftp assert fix for openfile failure case
> 
> Meenakshi,
> 
> The TFTP command is outside the UEFI Shell specification, therefore it is
> included as a DynamicCommand, not a command built into the shell itself.
> 
> I a little confused by your last sentence.  Do you want to send a new patch?
> or do you have a branch to pick changes from ?
> 
> -Jaben
> 
> 
> > -Original Message-
> > From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> > Sent: Tuesday, February 13, 2018 1:43 AM
> > To: Leif Lindholm <leif.lindh...@linaro.org>; Ni, Ruiyu
> <ruiyu...@intel.com>
> > Cc: ard.biesheu...@linaro.org; Ye, Ting <ting...@intel.com>; edk2-
> > de...@lists.01.org; Carsey, Jaben <jaben.car...@intel.com>; Fu, Siyuan
> > <siyuan...@intel.com>; Udit Kumar <udit.ku...@nxp.com>
> > Subject: RE: [PATCH] Tftp assert fix for openfile failure case
> > Importance: High
> >
> > Hi,
> >
> > As per commit 0961002352e9115b72f544dded239ad226efe87b
> >
> > Tftp command will be maintained to extend internal commands and
> >
> > ShellPkg/DynamicCommand/TftpDynamicCommand/Tftp.c
> >
> > Looks like a copy of ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> >
> > So, below fix is needed in this case as well.
> >
> > Please suggest, so we can send the updated patch [incorporating Leif's
> > comments]
> >
> >
> > Thanks,
> > Meenakshi
> >
> > > -Original Message-
> > > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > > Udit Kumar
> > > Sent: Thursday, November 09, 2017 10:13 AM
> > > To: Leif Lindholm <leif.lindh...@linaro.org>
> > > Cc: ruiyu...@intel.com; ard.biesheu...@linaro.org; ting...@intel.com;
> > edk2-
> > > de...@lists.01.org; jaben.car...@intel.com; siyuan...@intel.com
> > > Subject: Re: [edk2] [PATCH] Tftp assert fix for openfile failure case
> > >
> > >
> > >
> > > > -Original Message-
> > > > From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> > > > Sent: Wednesday, November 08, 2017 8:52 PM
> > > > To: Udit Kumar <udit.ku...@nxp.com>
> > > > Cc: Vabhav Sharma <vabhav.sha...@nxp.com>; edk2-
> > de...@lists.01.org;
> > > > ruiyu...@intel.com; jaben.car...@intel.com;
> ard.biesheu...@linaro.org;
> > > > siyuan...@intel.com; ting...@intel.com
> > > > Subject: Re: [PATCH] Tftp assert fix for openfile failure case
> > > >
> > > > On Wed, Nov 08, 2017 at 05:15:49AM +, Udit Kumar wrote:
> > > > > > > diff --git a/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > > > b/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > > > index fbde3bf..6425fc5 100755
> > > > > > > --- a/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > > > +++ b/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > > > @@ -509,6 +509,7 @@ ShellCommandRunTftp (
> > > > > > >);
> > > > > > >goto NextHandle;
> > > > > >
> >

Re: [edk2] [PATCH] Tftp assert fix for openfile failure case

[Meenakshi Aggarwal]

Hi,

As per commit 0961002352e9115b72f544dded239ad226efe87b

Tftp command will be maintained to extend internal commands and

ShellPkg/DynamicCommand/TftpDynamicCommand/Tftp.c

Looks like a copy of ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c

So, below fix is needed in this case as well.

Please suggest, so we can send the updated patch [incorporating Leif's comments]


Thanks,
Meenakshi

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Udit Kumar
> Sent: Thursday, November 09, 2017 10:13 AM
> To: Leif Lindholm 
> Cc: ruiyu...@intel.com; ard.biesheu...@linaro.org; ting...@intel.com; edk2-
> de...@lists.01.org; jaben.car...@intel.com; siyuan...@intel.com
> Subject: Re: [edk2] [PATCH] Tftp assert fix for openfile failure case
> 
> 
> 
> > -Original Message-
> > From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> > Sent: Wednesday, November 08, 2017 8:52 PM
> > To: Udit Kumar 
> > Cc: Vabhav Sharma ; edk2-devel@lists.01.org;
> > ruiyu...@intel.com; jaben.car...@intel.com; ard.biesheu...@linaro.org;
> > siyuan...@intel.com; ting...@intel.com
> > Subject: Re: [PATCH] Tftp assert fix for openfile failure case
> >
> > On Wed, Nov 08, 2017 at 05:15:49AM +, Udit Kumar wrote:
> > > > > diff --git a/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > b/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > index fbde3bf..6425fc5 100755
> > > > > --- a/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > +++ b/ShellPkg/Library/UefiShellTftpCommandLib/Tftp.c
> > > > > @@ -509,6 +509,7 @@ ShellCommandRunTftp (
> > > > >);
> > > > >goto NextHandle;
> > > >
> > > > Wow, a goto in a foor loop in a 320-line function.
> > > > What could possibly go wrong?
> > >
> > > Instead of being on some volume, if you are on Shell.
> > > Then file open will fail.
> >
> > Sure. The above was a snarky comment on the state of the existing code.
> >
> > > > >  }
> > > > > +DataSize = FileSize;
> > > > >
> > > > >  Status = DownloadFile (Mtftp4, RemoteFilePath,
> > > > > AsciiRemoteFilePath,
> > > > FileSize, BlockSize, );
> > > > >  if (EFI_ERROR (Status)) {
> > > > > @@ -539,7 +540,6 @@ ShellCommandRunTftp (
> > > > >goto NextHandle;
> > > > >  }
> > > > >
> > > > > -DataSize = FileSize;
> > > > >  Status = ShellWriteFile (FileHandle, , Data);
> > > > >  if (!EFI_ERROR (Status)) {
> > > > >ShellStatus = SHELL_SUCCESS;
> > > > > --
> > > > > 1.9.1
> > > >
> > > > So, a wider question:
> > > > This shell command was introduced in the heyday of "let's
> > > > reimplement U-Boot in the EDK2 tree". Mainly, from my impression, it
> > > > seems to be used in order that people don't need to learn how boot
> > > > managers and device paths work.
> > >
> > > When you say about complete boot, then this may not be useful.
> > >
> > > > Am I being too harsh?
> > > > Are there practical uses for this?
> > >
> > > For doing some sort of unit testing of given interface. I found this
> > > useful. During development, this is useful to transfer generic file to
> > > development board.
> >
> > OK, I can see how it could be useful.
> > My opposition is based on three things:
> > 1) people _are_ trying to use it for boot
> 
> I agree with this, please see my previous comments,
> ' When you say about complete boot, then this may not be useful.'
> 
> > 2) not a command described by UEFI Shell spec, but I keep seeing
> >platforms including it even in RELEASE builds (most likely because 1)
> > 3) code quality/maintainability
> 
> > > > If the code is to be kept, I think (from a quick glance) that I
> > > > would also like to see
> > > >   *Data = NULL
> > > > in the error path of DownloadFile().
> >
> > OK, so we don't need to drop it right now, but what's your take on this
> > comment?
> 
> I am fine, if you prefer to remove this then we will develop some test
> application
> for unit tests.
> In case, we need to maintain this piece of code then above needs to fix as
> well.
> 
> 
> > /
> > Leif
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Re: [edk2] [RFC] SATA : Implemented NXP errata A008402

[Meenakshi Aggarwal]

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ni,
> Ruiyu
> Sent: Tuesday, January 09, 2018 9:11 AM
> To: edk2-devel@lists.01.org
> Subject: Re: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> On 1/8/2018 7:16 PM, Meenakshi Aggarwal wrote:
> > Description:
> > Commands with 4 MB PRD length entries fail if PRD[DBC] is
> > set to the value according to AHCI standard spec.
> > Due to a logic error, 3F_h is misinterpreted by the
> > device as zero length.
> 
> Is the logic error mentioned here is the error in HW?
> Then I do not prefer to add such PCD for a HW workaround.
> 
Yes, the error is in hardware.
There is no other option visible to implement this errata if we want to use the 
existing AHCI framework.

I completely agree with you, but no other solution seems to exist in this case.

And this change will not impact any other hardware so no one is basically 
impacted by this change.

> >
> > Workaround:
> > Set PRD length to 0 when creating a PRD entry for
> > a maximum data transfer size of 4 MB to fix the erratum.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >   MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 2 +-
> >   MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf | 1 +
> >   MdeModulePkg/MdeModulePkg.dec  | 3 +++
> >   3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > index e6de5d6..fb6dc0b 100644
> > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > @@ -591,7 +591,7 @@ AhciBuildCommand (
> >   if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
> > AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
> >   } else {
> > -  AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
> > +  AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc = PcdGet32 (PcdPrdtMaxDataLength);
> >   }
> >
> >   Data64.Uint64 = (UINT64)MemAddr;
> > diff --git
> a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > index 82d5f7a..8921dd5 100644
> > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > @@ -70,6 +70,7 @@
> >
> >   [Pcd]
> > gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable   ##
> SOMETIMES_CONSUMES
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdPrdtMaxDataLength
> >
> >   # [Event]
> >   # EVENT_TYPE_PERIODIC_TIMER ## SOMETIMES_CONSUMES
> > diff --git a/MdeModulePkg/MdeModulePkg.dec
> b/MdeModulePkg/MdeModulePkg.dec
> > index 8efad57..b2f9f2b 100644
> > --- a/MdeModulePkg/MdeModulePkg.dec
> > +++ b/MdeModulePkg/MdeModulePkg.dec
> > @@ -1434,6 +1434,9 @@
> > # @Prompt Console Output Row of Text Setup
> >
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|25|UINT32|0x40
> 0e
> >
> > +  ## This PCD specifies the Maximum data length for a PRD Entry
> > +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPrdtMaxDataLength|0x3F|UIN
> T32|0x400f
> > +
> >   [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic,
> PcdsDynamicEx]
> > ## UART clock frequency is for the baud rate configuration.
> > # @Prompt Serial Port Clock Rate.
> >
> 
> 
> --
> Thanks,
> Ray
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Re: [edk2] [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver.

[Meenakshi Aggarwal]

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, January 08, 2018 8:35 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: Leif Lindholm <leif.lindh...@linaro.org>; Kinney, Michael D
> <michael.d.kin...@intel.com>; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller
> driver.
> 
> Hi Meenakshi,
> 
> This is looking much better - thanks for rewriting it. I do have some
> comments below
> 
> On 8 January 2018 at 15:55, Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com> wrote:
> > This patch adds support of SATA controller, which
> > Initialize SATA controller,
> > apply platform specific errata and
> > Register itself as NonDiscoverableMmioDevice
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  Platform/NXP/Drivers/SataInitDxe/SataInit.c  | 285
> +++
> >  Platform/NXP/Drivers/SataInitDxe/SataInit.h  |  36 +++
> >  Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf |  52 +
> >  Platform/NXP/NxpQoriqLs.dec  |  14 +-
> >  Platform/NXP/NxpQoriqLs.dsc  |  13 ++
> >  5 files changed, 398 insertions(+), 2 deletions(-)
> >  create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c
> >  create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h
> >  create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
> >
> > diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c
> b/Platform/NXP/Drivers/SataInitDxe/SataInit.c
> > new file mode 100644
> > index 000..bac390b
> > --- /dev/null
> > +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c
> > @@ -0,0 +1,285 @@
> > +/** @file
> > +  This driver module adds SATA controller support.
> > +
> > +  Copyright 2017 NXP
> > +
> > +  This program and the accompanying materials
> > +  are licensed and made available under the terms and conditions of the
> BSD License
> > +  which accompanies this distribution. The full text of the license may be
> found
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C1bf888
> dbc6b34f8646fe08d556a93d5a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636510207254570536=hU2o5igZuy5SDt5emEUmAqhSn1gW9
> H40OgvmH8gMn9k%3D=0
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > + **/
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "SataInit.h"
> > +
> > +STATIC VOID*mDriverEventRegistration;
> > +
> > +/**
> > +  Read AHCI Operation register.
> > +
> > +  @param  PciIoThe PCI IO protocol instance.
> > +  @param  Offset   The operation register offset.
> > +
> > +  @return  The register content read.
> > +**/
> > +
> > +UINT32
> > +EFIAPI
> > +AhciReadReg (
> > +  IN  EFI_PCI_IO_PROTOCOL  *PciIo,
> > +  IN  UINT32   Offset
> > +  )
> > +{
> > +  UINT32   Data;
> > +
> > +  ASSERT (PciIo != NULL);
> > +
> > +  Data = 0;
> > +
> > +  PciIo->Mem.Read (
> > +  PciIo,
> > +  EfiPciIoWidthUint32,
> > +  AHCI_BAR_INDEX,
> > +  (UINT64) Offset,
> > +  1,
> > +  
> > +  );
> > +
> > +  return Data;
> > +}
> > +
> > +/**
> > +  Write AHCI Operation register.
> > +
> > +  @param PciIo The PCI IO protocol instance.
> > +  @param OffsetThe operation register offset.
> > +  @param Data  The data used to write down.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +AhciWriteReg (
> > +  IN EFI_PCI_IO_PROTOCOL   *PciIo,
> > +  IN UINT32Offset,
> > +  IN UINT32Data
> > +  )
> > +{
> > +  ASSERT (PciIo != NULL);
> > +
> > +  PciIo->Mem.Write (
> > +   P

Re: [edk2] [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller

[Meenakshi Aggarwal]

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, January 08, 2018 8:42 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> Cc: Leif Lindholm <leif.lindh...@linaro.org>; Kinney, Michael D
> <michael.d.kin...@intel.com>; edk2-devel@lists.01.org; Udit Kumar
> <udit.ku...@nxp.com>; Varun Sethi <v.se...@nxp.com>
> Subject: Re: [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA
> controller
> 
> On 8 January 2018 at 15:55, Meenakshi Aggarwal
> <meenakshi.aggar...@nxp.com> wrote:
> > Enable support of SATA drives on ls1046 board.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc |  8 
> >  Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12
> 
> >  .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf |  2 ++
> >  .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c|  8
> 
> >  Silicon/NXP/LS1046A/LS1046A.dsc  |  5 +
> >  5 files changed, 35 insertions(+)
> >
> > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> > index 9d2482b..93fc848 100644
> > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> > @@ -63,6 +63,13 @@
> >#
> >gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
> >
> > +  #
> > +  # Errata Pcds
> > +  #
> > +  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE
> > +  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE
> > +  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE
> > +
> >
> ##
> ##
> >  #
> >  # Components Section - list of all EDK II Modules needed by this Platform
> > @@ -71,3 +78,4 @@
> >  [Components.common]
> >edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
> >edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
> > +  edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
> 
> This looks wrong to me. Your .dsc/.fdf files should not contain these
> edk2-platforms prefixes. Instead, you should set your PACKAGES_PATH
> correctly to include your edk2-platforms directory.
> 
OK, We will remove this from .dsc/.fdf files.
My concern is as there are already a lot of patches are under review so it will 
be 
Better if review gets completed once, then we will share the updated in next 
revision of patch
As this needs to be change in multiple patches.

There is one more comment from you on keeping shred Drivers and Library in 
Silicon/NXP directory.
In this case also, this will need a rework in all patches sent till date.

So once review comments been recieved we will made the changes in next revision 
of patch.

> > diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> > index 169cef0..23b46ad 100644
> > --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> > +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> > @@ -142,6 +142,18 @@ READ_LOCK_STATUS   = TRUE
> >
> >INF
> MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime
> Dxe.inf
> >
> > +  #
> > +  # AHCI Support
> > +  #
> > +  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > +  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> > +  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> > +  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> > +  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> > +  INF
> MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePci
> DeviceDxe.inf
> > +
> > +  INF edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
> > +
> 
> Same here
> 
> ># FAT filesystem + GPT/MBR partitioning
> >#
> >INF
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> > diff --git
> a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > index 13a0ffb..002294e 100644
> > ---
> a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > +++
> b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > @@ -68,3 +68,5 @@
> >gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> >gNxpQ

Re: [edk2] [RFC] SATA : Implemented NXP errata A008402

[Meenakshi Aggarwal]

Hi,

We will set PCD value to 0 to support our board and its default value is set to 
maximum data length.

If someone change its value to any other value in their package, then he/she 
must be aware of the consequences.

I cannot say how controller will react if value is other than 0x3f_ and 0 
(in our case).

Thanks,
Meenakshi

> -Original Message-
> From: Zeng, Star [mailto:star.z...@intel.com]
> Sent: Monday, January 08, 2018 3:54 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> de...@lists.01.org; Dong, Eric <eric.d...@intel.com>
> Cc: Ni, Ruiyu <ruiyu...@intel.com>; Zeng, Star <star.z...@intel.com>
> Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> How will the code work based on your patch if the this PCD is configured to
> other value, for example 0x20/0x30?
> 
> 
> Thanks,
> Star
> -Original Message-
> From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> Sent: Monday, January 8, 2018 5:54 PM
> To: Zeng, Star <star.z...@intel.com>; ard.biesheu...@linaro.org;
> leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> <eric.d...@intel.com>
> Cc: Ni, Ruiyu <ruiyu...@intel.com>
> Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> 
> > -Original Message-----
> > From: Zeng, Star [mailto:star.z...@intel.com]
> > Sent: Monday, January 08, 2018 3:18 PM
> > To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> > ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > de...@lists.01.org; Dong, Eric <eric.d...@intel.com>
> > Cc: Ni, Ruiyu <ruiyu...@intel.com>; Zeng, Star <star.z...@intel.com>
> > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> >
> > So this PCD needs to be defined as 0x3F or may be 0x40, then
> > it needs to be configured to 0 for your case, right?
> > Could the PCD be configured to other values?
> No, in my case i need to set it to 0 only. No other value is needed.
> >
> > According to the statement you provided, is it possible to handle the
> > case in the device firmware?
> >
> > " Due to a logic error, 3F_h is misinterpreted by the device as
> > zero length."
> >
> No, it can't be handle in device firmware for existing SATA controller.
> There are chances that in future releases of SATA controller it will get 
> fixed in
> RTL, but this change will still be needed for LS2088 board.
> 
> 
> >
> > Thanks,
> > Star
> > -Original Message-
> > From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> > Sent: Monday, January 8, 2018 2:26 PM
> > To: Zeng, Star <star.z...@intel.com>; ard.biesheu...@linaro.org;
> > leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> > <eric.d...@intel.com>
> > Cc: Ni, Ruiyu <ruiyu...@intel.com>
> > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> >
> > Hi Star,
> >
> > Apologies and some correction in my last reply.
> >
> > As per the errata, PRDT Maximum value needs to be set to 0 only  when
> > creating a PRD entry for a maximum data transfer size.
> >
> > So there is no need to replace all occurrences of
> > EFI_AHCI_MAX_DATA_PER_PRDT in file.
> > Just need to change it where we are setting the Data length.
> >
> > I define it to 0x3F, as this is the actual value we are setting
> > and this PCD need to be used only once.
> >
> > I know, its NXP specific patch only, and i try to made changes which
> > will not impact any other package.
> >
> >
> > Thanks,
> > Meenakshi
> >
> > > -Original Message-
> > > From: Meenakshi Aggarwal
> > > Sent: Monday, January 08, 2018 11:25 AM
> > > To: 'Zeng, Star' <star.z...@intel.com>; ard.biesheu...@linaro.org;
> > > leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> > > <eric.d...@intel.com>
> > > Cc: Ni, Ruiyu <ruiyu...@intel.com>
> > > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> > >
> > > Hi,
> > >
> > > I didn't prepare the full patch but will send in next few minutes,
> > >
> > > i  made the very basic changes required to test Errata implementation.
> > >
> > > I will redefine  it to 0x40.
> > > PcdPrdtMaxDataLength was defined to 0x3F just for testing purpose.
> > >
> > > Thanks,
> > > Meenakshi
> > >
> > > > -Original M

[edk2] [PATCH edk2-platforms 1/2] USB : Add DWC3 USB controller initialization driver.

[Meenakshi Aggarwal]

Add support of DWC3 controller driver which
Performs DWC3 controller initialization and
Register itself as NonDiscoverableMmioDevice

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
---
 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c   | 213 ++
 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h   | 142 +
 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf |  48 ++
 Platform/NXP/NxpQoriqLs.dsc   |   9 ++
 4 files changed, 412 insertions(+)
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf

diff --git a/Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c 
b/Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
new file mode 100644
index 000..179e9b6
--- /dev/null
+++ b/Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
@@ -0,0 +1,213 @@
+/** @file
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "UsbHcd.h"
+
+VOID
+XhciSetBeatBurstLength (
+  IN  UINTN  UsbReg
+  )
+{
+  Dwc3   *Dwc3Reg;
+
+  Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+  MmioAndThenOr32 ((UINTN)>GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
+  USB3_ENABLE_BEAT_BURST);
+  MmioOr32 ((UINTN)>GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
+
+  return;
+}
+
+VOID
+Dwc3SetFladj (
+  IN  Dwc3   *Dwc3Reg,
+  IN  UINT32 Val
+  )
+{
+  MmioOr32 ((UINTN)>GFLAdj, GFLADJ_30MHZ_REG_SEL |
+GFLADJ_30MHZ(Val));
+}
+
+VOID
+Dwc3SetMode (
+  IN  Dwc3   *Dwc3Reg,
+  IN  UINT32 Mode
+  )
+{
+  MmioAndThenOr32 ((UINTN)>GCtl,
+   ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+   DWC3_GCTL_PRTCAPDIR(Mode));
+}
+
+VOID
+Dwc3CoreSoftReset (
+  IN  Dwc3   *Dwc3Reg
+  )
+{
+  MmioOr32 ((UINTN)>GCtl, DWC3_GCTL_CORESOFTRESET);
+  MmioOr32 ((UINTN)>GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+  MmioOr32 ((UINTN)>GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
+  MmioAnd32 ((UINTN)>GCtl, ~DWC3_GCTL_CORESOFTRESET);
+
+  return;
+}
+
+EFI_STATUS
+Dwc3CoreInit (
+  IN  Dwc3   *Dwc3Reg
+  )
+{
+  UINT32 Revision;
+  UINT32 Reg;
+  UINTN  Dwc3Hwparams1;
+
+  Revision = MmioRead32 ((UINTN)>GSnpsId);
+  //
+  // This should read as U3 followed by revision number
+  //
+  if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSIS_ID) {
+DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
+return EFI_NOT_FOUND;
+  }
+
+  Dwc3CoreSoftReset (Dwc3Reg);
+
+  Reg = MmioRead32 ((UINTN)>GCtl);
+  Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+  Reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
+  Dwc3Hwparams1 = MmioRead32 ((UINTN)>GHwParams1);
+
+  if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == 
DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
+Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+  } else {
+DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
+  }
+
+  if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
+Reg |= DWC3_GCTL_U2RSTECN;
+  }
+
+  MmioWrite32 ((UINTN)>GCtl, Reg);
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+XhciCoreInit (
+  IN  UINTN  UsbReg
+  )
+{
+  EFI_STATUS Status;
+  Dwc3   *Dwc3Reg;
+
+  Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+  Status = Dwc3CoreInit (Dwc3Reg);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
+  UsbReg, Status));
+return Status;
+  }
+
+  Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
+
+  Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
+
+  return Status;
+}
+
+EFI_STATUS
+EFIAPI
+InitializeUsbController (
+  IN  UINTN  UsbReg
+  )
+{
+  EFI_STATUS Status;
+
+  Status = XhciCoreInit (UsbReg);
+
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  //
+  // Change beat burst and outstanding pipelined transfers requests
+  //
+  XhciSetBeatBurstLength (UsbReg);
+
+  return Status;
+}
+
+/**
+  The Entry Point of module. It follows the standard UEFI driver model.
+
+  @param[in] ImageHandle   The firmware allocated handle for the EFI image.
+  @param[in] SystemTable   A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS  The entry point is executed successfully.
+  @retval otherSome error occur

[edk2] [PATCH edk2-platforms 2/2] LS2088 : Enable support of USB controller

[Meenakshi Aggarwal]

Enable support of USB drives on ls2088 board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
---
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc |  1 +
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +
 2 files changed, 14 insertions(+)

diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index dbc4d33..1d840eb 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -93,3 +93,4 @@
   # I2c
   #
   edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+  edk2-platforms/Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf 
b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index f5d2f0a..ae3b2e3 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -143,6 +143,19 @@ READ_LOCK_STATUS   = TRUE
   INF  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
 !endif
 
+  INF 
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  #
+  # USB Support
+  #
+  INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  INF edk2-platforms/Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
   #
   # FAT filesystem + GPT/MBR partitioning
   #
-- 
1.9.1

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[edk2] [PATCH edk2-platforms 0/2] USB Controller Support

[Meenakshi Aggarwal]

Following set of patches add DWC3 (USB) controller driver
and enable USB support on LS2088RDB board.

DWC3 controller driver register USB as NonDiscoverableMmioDevice
of NonDiscoverableDeviceTypeXhci.

Meenakshi Aggarwal (2):
  USB : Add DWC3 USB controller initialization driver.
  LS2088 : Enable support of USB controller

 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c   | 213 ++
 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h   | 142 +
 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf |  48 ++
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc  |   1 +
 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf  |  13 ++
 Platform/NXP/NxpQoriqLs.dsc   |   9 ++
 6 files changed, 426 insertions(+)
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
 create mode 100644 Platform/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf

-- 
1.9.1

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[edk2] [PATCH edk2-platforms v2 2/2] LS1046 : Enable support of SATA controller

[Meenakshi Aggarwal]

Enable support of SATA drives on ls1046 board.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
---
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc |  8 
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 12 
 .../NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf |  2 ++
 .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c|  8 
 Silicon/NXP/LS1046A/LS1046A.dsc  |  5 +
 5 files changed, 35 insertions(+)

diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
index 9d2482b..93fc848 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -63,6 +63,13 @@
   #
   gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
 
+  #
+  # Errata Pcds
+  #
+  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|TRUE
+  gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|TRUE
+
 

 #
 # Components Section - list of all EDK II Modules needed by this Platform
@@ -71,3 +78,4 @@
 [Components.common]
   edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf
   edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf
+  edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf 
b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
index 169cef0..23b46ad 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -142,6 +142,18 @@ READ_LOCK_STATUS   = TRUE
 
   INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
 
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF 
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+  INF edk2-platforms/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
+
   # FAT filesystem + GPT/MBR partitioning
   #
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 13a0ffb..002294e 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -68,3 +68,5 @@
   gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
   gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+  gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c 
b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 7022528..4b04ff5 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -49,6 +49,8 @@
 #define DRAM3_SIZEFixedPcdGet64 (PcdDram3Size)
 #define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr)
 #define QSPI_REGION_SIZE  FixedPcdGet64 (PcdQspiRegionSize)
+#define DCSR_BASE_ADDRFixedPcdGet64 (PcdDcsrBaseAddr)
+#define DCSR_SIZE FixedPcdGet64 (PcdDcsrSize)
 
 
 /**
@@ -169,6 +171,12 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length   = QSPI_REGION_SIZE;
   VirtualMemoryTable[Index].Attributes   = 
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 
+  // DCSR Space
+  VirtualMemoryTable[++Index].PhysicalBase = DCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].VirtualBase  = DCSR_BASE_ADDR;
+  VirtualMemoryTable[Index].Length   = DCSR_SIZE;
+  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   // End of Table
   VirtualMemoryTable[++Index].PhysicalBase = 0;
   VirtualMemoryTable[Index].VirtualBase  = 0;
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
index 4e7230a..33c57ad 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc
@@ -74,5 +74,10 @@
   gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A
   gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B
   gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+  gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x2000
+  gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0400
+  gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x320
+  gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x1
+  gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x1
 
 ##
-- 

[edk2] [PATCH edk2-platforms v2 1/2] SATA : Added SATA controller driver.

[Meenakshi Aggarwal]

This patch adds support of SATA controller, which
Initialize SATA controller,
apply platform specific errata and
Register itself as NonDiscoverableMmioDevice

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
---
 Platform/NXP/Drivers/SataInitDxe/SataInit.c  | 285 +++
 Platform/NXP/Drivers/SataInitDxe/SataInit.h  |  36 +++
 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf |  52 +
 Platform/NXP/NxpQoriqLs.dec  |  14 +-
 Platform/NXP/NxpQoriqLs.dsc  |  13 ++
 5 files changed, 398 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf

diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c 
b/Platform/NXP/Drivers/SataInitDxe/SataInit.c
new file mode 100644
index 000..bac390b
--- /dev/null
+++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c
@@ -0,0 +1,285 @@
+/** @file
+  This driver module adds SATA controller support.
+
+  Copyright 2017 NXP
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "SataInit.h"
+
+STATIC VOID*mDriverEventRegistration;
+
+/**
+  Read AHCI Operation register.
+
+  @param  PciIoThe PCI IO protocol instance.
+  @param  Offset   The operation register offset.
+
+  @return  The register content read.
+**/
+
+UINT32
+EFIAPI
+AhciReadReg (
+  IN  EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN  UINT32   Offset
+  )
+{
+  UINT32   Data;
+
+  ASSERT (PciIo != NULL);
+
+  Data = 0;
+
+  PciIo->Mem.Read (
+  PciIo,
+  EfiPciIoWidthUint32,
+  AHCI_BAR_INDEX,
+  (UINT64) Offset,
+  1,
+  
+  );
+
+  return Data;
+}
+
+/**
+  Write AHCI Operation register.
+
+  @param PciIo The PCI IO protocol instance.
+  @param OffsetThe operation register offset.
+  @param Data  The data used to write down.
+
+**/
+VOID
+EFIAPI
+AhciWriteReg (
+  IN EFI_PCI_IO_PROTOCOL   *PciIo,
+  IN UINT32Offset,
+  IN UINT32Data
+  )
+{
+  ASSERT (PciIo != NULL);
+
+  PciIo->Mem.Write (
+   PciIo,
+   EfiPciIoWidthUint32,
+   AHCI_BAR_INDEX,
+   (UINT64) Offset,
+   1,
+   
+   );
+
+  return;
+}
+
+STATIC
+VOID
+PciIoRegistrationEvent (
+  IN  EFI_EVENTEvent,
+  IN  VOID *Context
+  )
+{
+  EFI_STATUS   Status;
+  UINTNHandleCount;
+  UINTNAddress;
+  UINT32   Count;
+  UINT32   Data;
+  UINT8PciClass;
+  UINT8PciSubClass;
+  EFI_PCI_IO_PROTOCOL  *PciIo;
+  EFI_HANDLE   *HandleBuf;
+
+  PciIo = NULL;
+
+  Status = gBS->LocateHandleBuffer (
+  ByProtocol,
+  ,
+  NULL,
+  ,
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Sata controller is not able to locate 
gEfiPciIoProtocolGuid 0x%x\n",
+Status));
+return;
+  }
+
+  for (Count = 0; Count < HandleCount; Count++) {
+Status = gBS->OpenProtocol (
+HandleBuf[Count],
+,
+(VOID **) ,
+NULL,
+NULL,
+EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+if (EFI_ERROR (Status)) {
+  continue;
+}
+
+//
+// Now further check the PCI header: Base class (offset 0x0B) and
+// Sub Class (offset 0x0A). This controller should be an Ide controller
+//
+Status = PciIo->Pci.Read (
+  PciIo,
+  EfiPciIoWidthUint8,
+  PCI_CLASSCODE_OFFSET + 2,
+  1,
+  
+  );
+if (EFI_ERROR (Status)) {
+  continue;
+}
+
+Status = PciIo->Pci.Read (
+  PciIo,
+  EfiPciIoWidthUint8,
+  PCI_CLASSCODE_OFFSET + 1,
+  1,
+  
+  

[edk2] [PATCH edk2-platforms v2 0/2] Cover letter:SATA controller support

[Meenakshi Aggarwal]

V2:

1. Pci Emulation layer removed.
2. Made SATA driver as NonDiscoverablePciDevice.
3. Add support of SATA on LS1046RDB board.

Meenakshi Aggarwal (2):
  SATA : Added SATA controller driver.
  LS1046 : Enable support of SATA controller

 Platform/NXP/Drivers/SataInitDxe/SataInit.c| 285 +
 Platform/NXP/Drivers/SataInitDxe/SataInit.h|  36 +++
 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf   |  52 
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc   |   8 +
 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf   |  12 +
 .../Library/PlatformLib/ArmPlatformLib.inf |   2 +
 .../Library/PlatformLib/NxpQoriqLsMem.c|   8 +
 Platform/NXP/NxpQoriqLs.dec|  14 +-
 Platform/NXP/NxpQoriqLs.dsc|  13 +
 Silicon/NXP/LS1046A/LS1046A.dsc|   5 +
 10 files changed, 433 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf


V1 :

Following patches add support for pci emulation layer
and SATA on NXP boards.

Null Library for USB is also present to give completeness
to Pci Emulation layer.

Meenakshi Aggarwal (3):
  USB: Added Support of DWC3 USB controller.
  PciEmulation : Add support for Pci Emulation layer.
  SATA : Added SATA controller initialization driver.

 Platform/NXP/Drivers/PciEmulation/PciEmulation.c   | 624 +
 Platform/NXP/Drivers/PciEmulation/PciEmulation.h   | 306 ++
 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf |  54 ++
 .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++
 Platform/NXP/Drivers/SataInitDxe/SataInit.c| 122 
 Platform/NXP/Drivers/SataInitDxe/SataInit.h|  32 ++
 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf   |  43 ++
 .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c  |  25 +
 .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf   |  28 +
 Platform/NXP/NxpQoriqLs.dec|  14 +-
 Platform/NXP/NxpQoriqLs.dsc|  15 +
 11 files changed, 1547 insertions(+), 2 deletions(-)
 create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c
 create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h
 create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf
 create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h
 create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf
 create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c
 create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary

-- 
1.9.1

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Re: [edk2] [RFC] SATA : Implemented NXP errata A008402

[Meenakshi Aggarwal]

> -Original Message-
> From: Zeng, Star [mailto:star.z...@intel.com]
> Sent: Monday, January 08, 2018 3:18 PM
> To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> de...@lists.01.org; Dong, Eric <eric.d...@intel.com>
> Cc: Ni, Ruiyu <ruiyu...@intel.com>; Zeng, Star <star.z...@intel.com>
> Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> So this PCD needs to be defined as 0x3F or may be 0x40, then it
> needs to be configured to 0 for your case, right?
> Could the PCD be configured to other values?
No, in my case i need to set it to 0 only. No other value is needed.
> 
> According to the statement you provided, is it possible to handle the case in
> the device firmware?
> 
> " Due to a logic error, 3F_h is misinterpreted by the device as zero
> length."
> 
No, it can't be handle in device firmware for existing SATA controller.
There are chances that in future releases of SATA controller it will get fixed 
in RTL,
but this change will still be needed for LS2088 board. 


> 
> Thanks,
> Star
> -Original Message-
> From: Meenakshi Aggarwal [mailto:meenakshi.aggar...@nxp.com]
> Sent: Monday, January 8, 2018 2:26 PM
> To: Zeng, Star <star.z...@intel.com>; ard.biesheu...@linaro.org;
> leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> <eric.d...@intel.com>
> Cc: Ni, Ruiyu <ruiyu...@intel.com>
> Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> Hi Star,
> 
> Apologies and some correction in my last reply.
> 
> As per the errata, PRDT Maximum value needs to be set to 0 only  when
> creating a PRD entry for a maximum data transfer size.
> 
> So there is no need to replace all occurrences of
> EFI_AHCI_MAX_DATA_PER_PRDT in file.
> Just need to change it where we are setting the Data length.
> 
> I define it to 0x3F, as this is the actual value we are setting and this 
> PCD
> need to be used only once.
> 
> I know, its NXP specific patch only, and i try to made changes which will not
> impact any other package.
> 
> 
> Thanks,
> Meenakshi
> 
> > -Original Message-
> > From: Meenakshi Aggarwal
> > Sent: Monday, January 08, 2018 11:25 AM
> > To: 'Zeng, Star' <star.z...@intel.com>; ard.biesheu...@linaro.org;
> > leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> > <eric.d...@intel.com>
> > Cc: Ni, Ruiyu <ruiyu...@intel.com>
> > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> >
> > Hi,
> >
> > I didn't prepare the full patch but will send in next few minutes,
> >
> > i  made the very basic changes required to test Errata implementation.
> >
> > I will redefine  it to 0x40.
> > PcdPrdtMaxDataLength was defined to 0x3F just for testing purpose.
> >
> > Thanks,
> > Meenakshi
> >
> > > -Original Message-
> > > From: Zeng, Star [mailto:star.z...@intel.com]
> > > Sent: Monday, January 08, 2018 11:19 AM
> > > To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> > > ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > > de...@lists.01.org; Dong, Eric <eric.d...@intel.com>
> > > Cc: Ni, Ruiyu <ruiyu...@intel.com>; Zeng, Star <star.z...@intel.com>
> > > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> > >
> > > Do you have a full patch already?
> > > Why the PcdPrdtMaxDataLength is defined to 0x3F, but not
> 0x40?
> > >
> > >
> > > Thanks,
> > > Star
> > > -Original Message-
> > > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
> > > Of Meenakshi Aggarwal
> > > Sent: Monday, January 8, 2018 7:17 PM
> > > To: ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > > de...@lists.01.org; Zeng, Star <star.z...@intel.com>; Dong, Eric
> > > <eric.d...@intel.com>
> > > Subject: [edk2] [RFC] SATA : Implemented NXP errata A008402
> > >
> > > Description:
> > > Commands with 4 MB PRD length entries fail if PRD[DBC] is set to the
> > > value according to AHCI standard spec.
> > > Due to a logic error, 3F_h is misinterpreted by the device as
> > > zero length.
> > >
> > > Workaround:
> > > Set PRD length to 0 when creating a PRD entry for a maximum data
> > > transfer size of 4 MB to fix the erratum.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> 

Re: [edk2] [RFC] SATA : Implemented NXP errata A008402

[Meenakshi Aggarwal]

Hi Star,

Apologies and some correction in my last reply.

As per the errata, PRDT Maximum value needs to be set to 0 only  when creating 
a PRD entry for
a maximum data transfer size.

So there is no need to replace all occurrences of EFI_AHCI_MAX_DATA_PER_PRDT in 
file.
Just need to change it where we are setting the Data length.

I define it to 0x3F, as this is the actual value we are setting and this 
PCD need to be used only once.

I know, its NXP specific patch only, and i try to made changes which will not 
impact any other package.


Thanks,
Meenakshi

> -Original Message-
> From: Meenakshi Aggarwal
> Sent: Monday, January 08, 2018 11:25 AM
> To: 'Zeng, Star' <star.z...@intel.com>; ard.biesheu...@linaro.org;
> leif.lindh...@linaro.org; edk2-devel@lists.01.org; Dong, Eric
> <eric.d...@intel.com>
> Cc: Ni, Ruiyu <ruiyu...@intel.com>
> Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> 
> Hi,
> 
> I didn't prepare the full patch but will send in next few minutes,
> 
> i  made the very basic changes required to test Errata implementation.
> 
> I will redefine  it to 0x40.
> PcdPrdtMaxDataLength was defined to 0x3F just for testing purpose.
> 
> Thanks,
> Meenakshi
> 
> > -Original Message-
> > From: Zeng, Star [mailto:star.z...@intel.com]
> > Sent: Monday, January 08, 2018 11:19 AM
> > To: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>;
> > ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > de...@lists.01.org; Dong, Eric <eric.d...@intel.com>
> > Cc: Ni, Ruiyu <ruiyu...@intel.com>; Zeng, Star <star.z...@intel.com>
> > Subject: RE: [edk2] [RFC] SATA : Implemented NXP errata A008402
> >
> > Do you have a full patch already?
> > Why the PcdPrdtMaxDataLength is defined to 0x3FFFFF, but not 0x40?
> >
> >
> > Thanks,
> > Star
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Meenakshi Aggarwal
> > Sent: Monday, January 8, 2018 7:17 PM
> > To: ard.biesheu...@linaro.org; leif.lindh...@linaro.org; edk2-
> > de...@lists.01.org; Zeng, Star <star.z...@intel.com>; Dong, Eric
> > <eric.d...@intel.com>
> > Subject: [edk2] [RFC] SATA : Implemented NXP errata A008402
> >
> > Description:
> > Commands with 4 MB PRD length entries fail if PRD[DBC] is
> > set to the value according to AHCI standard spec.
> > Due to a logic error, 3F_FFFFh is misinterpreted by the
> > device as zero length.
> >
> > Workaround:
> > Set PRD length to 0 when creating a PRD entry for
> > a maximum data transfer size of 4 MB to fix the erratum.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com>
> > ---
> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 2 +-
> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf | 1 +
> >  MdeModulePkg/MdeModulePkg.dec  | 3 +++
> >  3 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > index e6de5d6..fb6dc0b 100644
> > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
> > @@ -591,7 +591,7 @@ AhciBuildCommand (
> >  if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
> >AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc
> > = (UINT32)RemainedData - 1;
> >  } else {
> > -  AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc
> > = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
> > +  AhciRegisters->AhciCommandTable-
> >PrdtTable[PrdtIndex].AhciPrdtDbc
> > = PcdGet32 (PcdPrdtMaxDataLength);
> >  }
> >
> >  Data64.Uint64 = (UINT64)MemAddr;
> > diff --git
> a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > index 82d5f7a..8921dd5 100644
> > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > @@ -70,6 +70,7 @@
> >
> >  [Pcd]
> >gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable   ##
> > SOMETIMES_CONSUMES
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdPrdtMaxDataLength
> >
> >  # [Event]
> >  # EVENT_TYPE_PERIODIC_TIMER ## SOMETIMES_CONSUMES
> > diff --git a/MdeModulePkg/MdeModuleP