Re: EMC Design Question for a Backplane ...
Thanks for the responses, both on and off line. Democratically the consensus amounts to the following: Multi-hole "Sieve" Design = 2 votes for ... Reasons: 1. Reduce multi-current crowding around pins. 2. Reduce plane inductance. Single-Hole "Cookie Cutter" Design = 2 votes for ... Reasons: 1. Reduce noise coupling to power plane from pins. Now, they are all good concerns. So, what I'm going to do is try to combine the two with a suggestion from Scott and require that the holes through the power plane are to be larger than the holes through the ground plane. But, they are not to be so large that the concerns of the "sieve" design are violated, i.e. current crowding and inductance are INCREASED. Again, thanks for the reality check... Doug ... -- > From: Doug McKean > To: IEEE Product Safety Technical Committee - > Subject: EMC Design Question for a Backplane ... > Date: Wednesday, September 24, 1997 6:16 PM > > I'm having a lively discussion with one of our > design engineers about backplane PCB design. > > Here's the case: > > 1. Multilayer board, let's say 10 layers, >1 power plane (+5vdc), 3 ground planes, >6 signal planes. > > 2. Outside world connections to the >backplane with several connectors >across the back of the product. > > 3. T1/DS1 product. > > I want the +5vdc power plane cutaway, actually > well away, from pins of the connectors that do > not use the power plane. I can't draw it very > well with ASCII. But needless to say, if there's > a 6-pin connector with 1 pin using the 5 vdc, > then I want the 5 volt plane cut away from the > other 5 pins with *one* hole. > > Instead, what's being suggested is to punch *five* > separate holes through the power plane like a sieve > for each pin not using the 5 volts. > > My concern is noise, transients, or ESD coupling > from the outside world lines to the power plane > of the backplane and thus to everything connected > to the backplane. > > Am I being too picky here? > > What's the standard convention that people > use out there? >
RE: EMC Design Question for a Backplane
Why is it that I frequently get e-mails that have the first letter of
each line missing? Is there anything that can be done about this?
Thanks,
Jim Eichner
Statpower Technologies Corp.
Burnaby, B.C., Canada
jeich...@statpower.com
Any opinions expressed are those of my invisible friend, who really
exists. Honest.
-Original Message-
From: sdouglas@anetMHS (DouglasScott){MHS:sdoug...@ecrm.com}
Sent: Thursday, September 25, 1997 8:49 AM
To: dmckean@anetMHS ("Doug McKean"){MHS:dmck...@paragon-networks.com};
JEichner; bceresne
Cc: emc-pstc@anetMHS ("emc-pstc"){MHS:emc-p...@ieee.org}
Subject: RE: EMC Design Question for a Backplane ...
---[ Content-type: text/plain; name=Message Body
]--
Doug,
I have had the same "discussion" with both the designers and the board
layout
uy. Turns out that our standard proctice is to punch holes for each
connector
in. The holes are usually 0.100" on the surface layer and 0.130" on the
inner
ayers. The result is overlapping holes that end up leaving a large hole
in the
inner layer. The edge of this large hole usually looks serrated due to
the not
completely overlapping holes. Obviously this look will change depending
what p
wers, grounds, signals are connected on any given level.
We have had occaision to go back and modify this approach. This usually
happen
when the designer finds a performance issue during development or when I
have
a compliance problem. In that case we have modified the specific
connector loc
tion, sometimes having to create new pcb layout library components to
make thi
happen. But that is the exception rather than the rule.
We also use other means to address this issue. Any signal to a connector
over
0 MHz usually gets a dedicated connector or a coaxial type. Any signal
from 2
o 10 MHz gets board routing and etch shielding treatments and sometimes
filter
ng. Anything less than 2 MHz gets nothing except as required.
Regards,
Scott Douglas
Principal Compliance Engineer
ECRM Incorporated
Telephone: 1-508-851-0207
Facsimilie: 1-508-851-7016
e-mail: sdoug...@ecrm.com
__
From: Doug McKean on Thu, Sep 25, 1997 12:33 AM
Subject: EMC Design Question for a Backplane ...
To: IEEE Product Safety Technical Committee -
I'm having a lively discussion with one of our
design engineers about backplane PCB design.
Here's the case:
1. Multilayer board, let's say 10 layers,
1 power plane (+5vdc), 3 ground planes,
6 signal planes.
2. Outside world connections to the
backplane with several connectors
across the back of the product.
3. T1/DS1 product.
I want the +5vdc power plane cutaway, actually
well away, from pins of the connectors that do
not use the power plane. I can't draw it very
well with ASCII. But needless to say, if there's
a 6-pin connector with 1 pin using the 5 vdc,
then I want the 5 volt plane cut away from the
other 5 pins with *one* hole.
Instead, what's being suggested is to punch *five*
separate holes through the power plane like a sieve
for each pin not using the 5 volts.
My concern is noise, transients, or ESD coupling
from the outside world lines to the power plane
of the backplane and thus to everything connected
to the backplane.
Am I being too picky here?
What's the standard convention that people
use out there?
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From: dmck...@paragon-networks.com (Doug McKean)
To: "IEEE Product Safety Technical Committee -"
Subject: EMC Design Question for a Backplane ...
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Re: EMC Design Question for a Backplane ...
Punch like a sieve i.e. one hole for each pin insted of a large cut-out. That reduces the inductance of the power/ground plane. The increased noise coupling in insignificant compared to the lost benefits of the low plane inductance. Besides, you reduce the current flow capacity and create current crowding conditions which under certain condition can cause significant EMI radiation. Hans __ Reply Separator _ Subject: EMC Design Question for a Backplane ... Author: Non-HP-dmckean (dmck...@paragon-networks.com) at HP-ColSprings,mimegw5 List-Post: emc-pstc@listserv.ieee.org Date:9/24/97 3:16 PM I'm having a lively discussion with one of our design engineers about backplane PCB design. Here's the case: 1. Multilayer board, let's say 10 layers, 1 power plane (+5vdc), 3 ground planes, 6 signal planes. 2. Outside world connections to the backplane with several connectors across the back of the product. 3. T1/DS1 product. I want the +5vdc power plane cutaway, actually well away, from pins of the connectors that do not use the power plane. I can't draw it very well with ASCII. But needless to say, if there's a 6-pin connector with 1 pin using the 5 vdc, then I want the 5 volt plane cut away from the other 5 pins with *one* hole. Instead, what's being suggested is to punch *five* separate holes through the power plane like a sieve for each pin not using the 5 volts. My concern is noise, transients, or ESD coupling from the outside world lines to the power plane of the backplane and thus to everything connected to the backplane. Am I being too picky here? What's the standard convention that people use out there?
RE: EMC Design Question for a Backplane ...
Doug, I have had the same "discussion" with both the designers and the board layout guy. Turns out that our standard proctice is to punch holes for each connector pin. The holes are usually 0.100" on the surface layer and 0.130" on the inner layers. The result is overlapping holes that end up leaving a large hole in the inner layer. The edge of this large hole usually looks serrated due to the not completely overlapping holes. Obviously this look will change depending what powers, grounds, signals are connected on any given level. We have had occaision to go back and modify this approach. This usually happens when the designer finds a performance issue during development or when I have a compliance problem. In that case we have modified the specific connector location, sometimes having to create new pcb layout library components to make this happen. But that is the exception rather than the rule. We also use other means to address this issue. Any signal to a connector over 10 MHz usually gets a dedicated connector or a coaxial type. Any signal from 2 to 10 MHz gets board routing and etch shielding treatments and sometimes filtering. Anything less than 2 MHz gets nothing except as required. Regards, Scott Douglas Principal Compliance Engineer ECRM Incorporated Telephone: 1-508-851-0207 Facsimilie: 1-508-851-7016 e-mail: sdoug...@ecrm.com ___ From: Doug McKean on Thu, Sep 25, 1997 12:33 AM Subject: EMC Design Question for a Backplane ... To: IEEE Product Safety Technical Committee - I'm having a lively discussion with one of our design engineers about backplane PCB design. Here's the case: 1. Multilayer board, let's say 10 layers, 1 power plane (+5vdc), 3 ground planes, 6 signal planes. 2. Outside world connections to the backplane with several connectors across the back of the product. 3. T1/DS1 product. I want the +5vdc power plane cutaway, actually well away, from pins of the connectors that do not use the power plane. I can't draw it very well with ASCII. But needless to say, if there's a 6-pin connector with 1 pin using the 5 vdc, then I want the 5 volt plane cut away from the other 5 pins with *one* hole. Instead, what's being suggested is to punch *five* separate holes through the power plane like a sieve for each pin not using the 5 volts. My concern is noise, transients, or ESD coupling from the outside world lines to the power plane of the backplane and thus to everything connected to the backplane. Am I being too picky here? What's the standard convention that people use out there? -- RFC822 Header Follows -- Received: by macgtwy.ecrm.com with SMTP;25 Sep 1997 00:33:05 -0400 Received: by highlight.ecrm.com (AA08732); Thu, 25 Sep 97 00:20:16 EDT Received: from ruebert.ieee.org by maildrop.ecrm.com (AAA09548); Thu, 25 Sep 1997 00:20:45 -0400 (EDT) Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id SAA26766 for emc-pstc-list; Wed, 24 Sep 1997 18:24:42 -0400 (EDT) From: dmck...@paragon-networks.com (Doug McKean) To: "IEEE Product Safety Technical Committee -" Subject: EMC Design Question for a Backplane ... List-Post: emc-pstc@listserv.ieee.org Date: Wed, 24 Sep 1997 18:16:16 -0400 X-Msmail-Priority: Normal X-Priority: 3 X-Mailer: Microsoft Internet Mail 4.70.1161 Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Message-Id: <19970924222821068.aaa...@camalus.paragon-networks.com> Sender: owner-emc-p...@majordomo.ieee.org Precedence: bulk Reply-To: dmck...@paragon-networks.com (Doug McKean) X-Resent-To: Multiple Recipients X-Listname: emc-pstc X-Info: Help requests to emc-pstc-requ...@majordomo.ieee.org X-Info: [Un]Subscribe requests to majord...@majordomo.ieee.org X-Moderator-Address: emc-pstc-appro...@majordomo.ieee.org
EMC Design Question for a Backplane ...
I'm having a lively discussion with one of our design engineers about backplane PCB design. Here's the case: 1. Multilayer board, let's say 10 layers, 1 power plane (+5vdc), 3 ground planes, 6 signal planes. 2. Outside world connections to the backplane with several connectors across the back of the product. 3. T1/DS1 product. I want the +5vdc power plane cutaway, actually well away, from pins of the connectors that do not use the power plane. I can't draw it very well with ASCII. But needless to say, if there's a 6-pin connector with 1 pin using the 5 vdc, then I want the 5 volt plane cut away from the other 5 pins with *one* hole. Instead, what's being suggested is to punch *five* separate holes through the power plane like a sieve for each pin not using the 5 volts. My concern is noise, transients, or ESD coupling from the outside world lines to the power plane of the backplane and thus to everything connected to the backplane. Am I being too picky here? What's the standard convention that people use out there?
