from:"Idwer Vollering"

[flashrom] Re: RFC: remove the calibrated delay loop

2024-04-12 Thread Idwer Vollering

I've tested compilation of https://review.coreboot.org/c/flashrom/+/81545
and reading, erasing, writing flash on a FreeBSD -CURRENT amd64 machine
(ASUS F2A85-M). Seems to work as expected.

On Fri, Apr 12, 2024, 08:22 Peter Marheine  wrote:

> For completeness, the proposed change is at
> https://review.coreboot.org/c/flashrom/+/81545
>
> I've tested it myself (and added a unit test) and am fairly confident
> everything works well, but if anybody has a "weirder" machine than an x86
> PC to test on, additional coverage would be helpful.
>
> On Fri, Apr 5, 2024 at 11:13 PM Anastasia Klimchuk 
> wrote:
>
>> > do you want to keep around such legacy code
>> > (increasing the maintenance load) in the codebase forever?
>>
>> No I don't want to keep such code forever to maintain, mainly because
>> it won't be needed forever.
>> But dropping support for DOS will be a separate effort (with dedicated
>> threads and announcements). I don't think it should be like "while we
>> are here, let's also drop DOS", it's a bigger effort than "while we
>> are here".
>>
>> > For example, some chips use the toggle bit detection to check for a
>> > finished write.
>>
>> Do you know, are such chips marked in flashchips definition, how do we
>> know which ones are like this?
>> I understand from your words this is a subset of older non-SPI
>> (LPC/FWH/parallel) flash chips but which ones?
>>
>> Also relevant to delays: are those the same chips that need extra delay
>> 1s?
>> For context, comments here https://review.coreboot.org/c/flashrom/+/80807
>> Do you maybe remember how to find them in flashchips?
>>
>> As I understand, there are some small(?) number of older(?) chips
>> which need special treatment on delays, it would be so helpful to find
>> out which ones exactly.
>>
>> > Focusing on the 99% might yield enormous
>> > cleanup opportunities.
>>
>> Yes, that's a really good observation.
>> I have such thoughts in the background.
>>
>> --
>> Anastasia.
>>
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[flashrom] Re: Trouble flashing Winbond chip

2019-10-03 Thread Idwer Vollering

This could be caused by electrical problems. Did you find and read
this page, https://flashrom.org/Common_problems ?
Also, the particular version of flashrom was omitted in its output. It
looks like you build the binary yourself, instead of installing
through a package manager. Please mention the version as well.

Op do 3 okt. 2019 om 13:13 schreef Johan Bergsten :
>
> Hi!
>
>
>
> I have trouble flashing Winbond W25Q64 BIOS chip using Rpi. Can you please 
> advise?
>
>
>
> Output from the verbose log:
>
>
>
> pi@raspberrypi:~/Temp $ sudo flashrom -p 
> linux_spi:dev=/dev/spidev0.0,spispeed=2000 -w V3ZCAM10.BIN -V
>
> flashrom  on Linux 4.19.66-v7l+ (armv7l)
>
> flashrom is free software, get the source code at https://flashrom.org
>
>
>
> flashrom was built with libpci 3.5.2, GCC 8.2.0, little endian
>
> Command line (5 args): flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=2000 
> -w V3ZCAM10.BIN -V
>
> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
>
> Initializing linux_spi programmer
>
> Using device /dev/spidev0.0
>
> Using 2000 kHz clock
>
> The following protocols are supported: SPI.
>
>
>
> Found Winbond flash chip "W25Q64.W" (8192 kB, SPI) on linux_spi.
>
> Chip status register is 0x00.
>
>
>
> Found Winbond flash chip "W25Q64.W" (8192 kB, SPI).
>
> This chip may contain one-time programmable memory. flashrom cannot read
>
> and may never be able to write it, hence it may not be able to completely
>
> clone the contents of this chip (see man page for details).
>
> Reading old flash chip contents... done.
>
> Erasing and writing flash chip... Trying erase function 0... 
> 0x00-0x000fff:W, 0x001000-0x001fff:EFAILED at 0x1000! Expected=0xff, 
> Found=0x00, failed byte count from 0x1000-0x1fff: 0x1000
>
> ERASE FAILED!
>
> Reading current flash chip contents... done. Looking for another erase 
> function.
>
> Trying erase function 1... 0x00-0x007fff:EFAILED at 0x1000! 
> Expected=0xff, Found=0x00, failed byte count from 0x-0x7fff: 
> 0x4000
>
> ERASE FAILED!
>
> Reading current flash chip contents... done. Looking for another erase 
> function.
>
> Trying erase function 2... 0x00-0x00:EFAILED at 0x1000! 
> Expected=0xff, Found=0x00, failed byte count from 0x-0x: 
> 0x9000
>
> ERASE FAILED!
>
> Reading current flash chip contents... done. Looking for another erase 
> function.
>
> Trying erase function 3... 0x00-0x7f:EFAILED at 0x1000! 
> Expected=0xff, Found=0x00, failed byte count from 0x-0x007f: 
> 0x3fa01c
>
> ERASE FAILED!
>
> Reading current flash chip contents... done. Looking for another erase 
> function.
>
> Trying erase function 4... 0x00-0x7f:EFAILED at 0x1000! 
> Expected=0xff, Found=0x00, failed byte count from 0x-0x007f: 
> 0x41101a
>
> ERASE FAILED!
>
> Reading current flash chip contents... done. Looking for another erase 
> function.
>
> Trying erase function 5... not defined. No usable erase functions left.
>
> FAILED!
>
> Uh oh. Erase/write failed. Checking if anything has changed.
>
> Reading current flash chip contents... done.
>
> Apparently at least some data has changed.
>
> Your flash chip is in an unknown state.
>
>
>
>
>
>
>
>
>
> Kind regards
>
> Johan Bergsten
>
>
>
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Re: [flashrom] Can't Flash on AOpen i965GMt-LA motherboard

2018-03-28 Thread Idwer Vollering

I took the liberty to submit this change to gerrit;
https://review.coreboot.org/#/c/flashrom/+/25396/

2018-03-20 18:14 GMT+01:00 Luc Verhaegen :
> On Tue, Mar 20, 2018 at 02:27:54PM +0100, Luc Verhaegen wrote:
>>
>> What this board needs is a call to intel_ich_gpio20_raise();
>>
>> Will provide a patch later today.
>
> Attached.
>
>> I am a bit worried though that the lpc io BAR is empty in your lspci. I
>> am not sure whether that is handled in any way, and i do not think the
>> intel gpio code in flashrom will deal with an empty bar gracefully.
>
> Luc Verhaegen.
>
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Re: [flashrom] copying flashrom from USB

2018-03-18 Thread Idwer Vollering

Hi Shenol,

I think you mean the GPD Pocket? There is a youtube clip with the
title "GPD WIN - RESTORE BIOS DEFAULT - Optimized Defaults Aptio Setup
Utility 2016": https://www.youtube.com/watch?v=VOQuisWD-uY
There appear to be other people running into the same problem, see
https://www.reddit.com/r/GPDPocket/comments/6v0s6g/how_do_i_reset_the_cmos_batteryhardwarereset_the/

Perhaps disconnecting the CMOS battery for a short while (overnight)
will reset BIOS settings,

Best regards,

Idwer

2018-03-18 17:10 GMT+01:00 Shenol :
> Hello,
> I have mini laptop GPD ONE, I turned option USB off at boot, from BIOS and 
> because laptop uses USB keyboard! I cannot enter BIOS. My only chance is 
> flashing BIOS, however I only have a half working linux installation which 
> does not connect to Wifi, so I cannot use apt to install flashrom. I tried 
> copying it but I don't know how to copy depending libraries. Can I can copy 
> the full program from USB?
>
> Sincerely,
> Shenol Mustafov
> --
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>
>
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Re: [flashrom] Unknown error

2017-04-19 Thread Idwer Vollering

2017-04-17 12:23 GMT+02:00 Андрей Макаровский :
>  I had an error writing to flash chip sst49lf002a on chipset intel ich5:
> writing sector at 0xb7410300. What could it be?
>
> Best regards,
>
> Andrew Makarovsky

We need full (more) output. It would help to install the latest
release, then write the same file and use the -o parameter to write a
sane log file.

Also, please run 'lspci -nnvvxxx' as root and include its output.

HTH,

Idwer

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Re: [flashrom] Any chance of getting Flashrom 0.9.8 for DOS?

2016-12-04 Thread Idwer Vollering

Why is DOS a must-have in your use case?

Yes, I did cross-compile for DOS, however that was a while ago. I
don't support DOS (anymore).

- idwer

2016-12-04 21:59 GMT+01:00 Lu Xie :
> Hi,
>
> I have been quite happy with the 0.9.6.1 release for DOS and I decided to
> get a newer version. I tried several compiled executables from the buildbot
> repository but they are all unstable. I did a search in the wayback machine
> and found that 0.9.8 was the last stable release that had a DOS executable
> stored outside the buildbot repository, but the link
> (http://ra.openbios.org/~idwer/flashrom/dos/) seems to be dead. I googled
> for hours but couldn't find a copy of a 0.9.8 DOS executable. Could you
> please send me a copy of it from your archive or repository? Thanks.
>
> Lu
>
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Re: [flashrom] unknown chip

2016-04-21 Thread Idwer Vollering

Hi,

I think you meant MX25U12835F.

This fork of flashrom code seems to have done the work for us:
https://github.com/rjarzmik/flashrom2/blob/master/src/chips/mx25u12835f.c

HTH,

Idwer

2016-04-19 15:34 GMT+02:00 John Bork :
> Hi,
>
> got this probe result from a MX25U12845F chip, if you want to add it to your
> support list.
>
> BR
> John Bork
>
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Re: [flashrom] [v3,2/2] ENE KB9012 EC flashrom patch - Bug report

2016-01-30 Thread Idwer Vollering

2016-01-30 19:06 GMT+01:00 John Brown :
> Good day! I applied your most recent KB9012 flashrom patch to the latest
> flashrom copy, and tried to compile it for testing with my KB9012 chip.
> However, I have encountered the following error:
>
> flashchips.c:3209:19: error: 'FEATURE_ERASED_ZERO' undeclared here (not in a
> function)
>.feature_bits = FEATURE_ERASED_ZERO,
>^
> make: *** [flashchips.o] Error 1
>
> FEATURE_ERASED_ZERO is not declared anywhere, neither in latest flashrom
> revisions, nor in older flashrom revisions. Dont know why nobody noticed
> this problem before me...

It is defined in a pending patch:
http://www.flashrom.org/pipermail/flashrom/2015-November/013969.html

>
> Then, I thought it could be a good idea to replace this undeclared value
> with zero:
>.feature_bits = 0,

FEATURE_ERASED_ZERO definitely does not equal 0.

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Re: [flashrom] please, helpme. AMI BIOS SPI FLASH ROM 96 MB

2015-11-10 Thread Idwer Vollering

2015-11-09 23:42 GMT+01:00 Alberto Perez :
> please, helpme. i want flashear mi notebook
> (http://bangho.com.ar/wp-content/uploads/2015/04/Ultrabook-Bangho-ZERO-1430-Manual-del-usuario.pdf)
> but I do not know how to do it.
> I do not know what parameter to use in --programmer.

You'll want to look at this page, for hardware 'friendly names':
http://www.flashrom.org/Supported_hardware#USB_Devices

> my bios is AMI BIOS SPI Flash  ROM  de 96 M b
> Por favor, alguien puede ayudarme: Quiero hacer un volcado de la memoria rom
> de mi notebook pero no sé cómo hacerlo.

flashrom (as a CLI binary) doesn't handle translations.

>
>
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Re: [flashrom] flashrom

2015-11-03 Thread Idwer Vollering

2015-11-01 14:41 GMT+01:00 Денис :
> flashrom v0.9.2-r1141 on Linux 2.6.32-5-amd64 (x86_64), built with libpci
> 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian
> flashrom is free software, get the source code at http://www.flashrom.org

If you looked at that website [1] you would have found out that
version 0.9.2 was released over 5 years ago.

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Re: [flashrom] FAILED: ASUS P4P800

2015-08-28 Thread Idwer Vollering

2015-08-28 6:16 GMT+02:00 Alan Kirby alankir...@gmail.com:
 Hi Folks

 Had a result from flashrom that asked me to send this log to you guys. I'm
 certainly thankful for that.

 The mainboard flash ROM had (probably still has) malware within it that is
 persistent. Maybe it's lighteater.

You can extract the chip's content, from file, using bios_extract:
https://github.com/coreboot/bios_extract and/or radare:
http://rada.re/

 Since I haven't fully diagnosed it, I've
 attached a 64KiB file that is a dump of the boot block: F' - F'.
 One of the things it does is prevent afudos (engineer's version) from
 overwriting the boot block.

The bootblock, or in this case whole chip protection is put in place
by the vendor BIOS.

 Another thing it does : if you hit Enter at the
 afudos command, then pull out the keyboard cable, the Disk Driver (INT 13h
 handler) throws an error, saying there was a disk read error. That
 shouldn't happen, so these interrupt handlers are checking up on each
 other, in order to achieve overall persistence.

BY ALL MEANS: THEN DON'T PULL OUT THE KEYBOARD CABLE?
One could permanently break a mainboard, or at least its PS/2 port, by doing so.


 So, to get round these protections, I was attempting to shift away from
 FreeDOS and flash the ROM from Linux - Ubuntu (Trust Tahr 6.0), in fact.

 I see the warning about the mainboard-specific code but I couldn't tally
 that with any action I should take. I saw that the ASUS P4P800 is supported
 and that it is autodetected. I also tried putting different strings after
 mainboard, whilst simply probing the hardware: =ASUS, =P4P800, =ASUS
 P4P800, =ASUS:P4P800. Each generated an error. Removing the = and
 everything after it worked - the probe worked without error. That gave me
 confidence that I'd understood the autodetect part.

Which model of P4P800 is this?
Is it the P4P800-VM? If I recall correctly, a newer release of
flashrom (0.9.7 or 0.9.8) will detect the supported (sub)model.
Source: I had an ASUS P4P800-VM.


 Regards

 Alan K

HTH,

Idwer


 # ./flashrom -p internal:mainboard -E
 flashrom v0.9.6.1-r1563 on Linux 3.14.20 (i686)
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OK.
 Found chipset Intel ICH5/ICH5R. Enabling flash write... OK.
 WARNING: Your mainboard is ASUS P4P800, but the mainboard-specific
 code has not been tested, and thus will not be executed by default.
 Depending on your hardware environment, erasing, writing or even probing
 can fail without running the board specific code.

 Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection
 internal programmer) for details.
 Unhandled programmer parameters: mainboard
 Found PMC flash chip Pm49FL004 (512 kB, LPC, FWH) at physical address
 0xfff8.
 Erasing and writing flash chip... ERASE FAILED at 0x1c40 !
 Expected=0xff, Read=0x44, failed byte count from 0x1000-0x1fff:
 0x3a2
 ERASE FAILED!
 Reading current flash chip contents... done. ERASE FAILED at 0x1c40 !
 Expected=0xff, Read=0x44, failed byte count from 0x-0x:
 0xe2c5
 ERASE FAILED!
 Reading current flash chip contents... done. ERASE FAILED at 0x1c40 !
 Expected=0xff, Read=0x44, failed byte count from 0x-0x0007:
 0x7a92c
 ERASE FAILED!
 FAILED!
 Your flash chip is in an unknown state.
 Get help on IRC at chat.freenode.net (channel #flashrom) or
 mail flashrom@flashrom.org with the subject FAILED: your board name!
 --
 DO NOT REBOOT OR POWEROFF!

 A non-text attachment MR-F.BIN has been stripped.
 It is available at http://paste.flashrom.org/view.php?id=2783

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Re: [flashrom] Not detecting Am29F010 using 3Com PCI nic

2015-07-29 Thread Idwer Vollering

2015-07-29 20:38 GMT+02:00 Ignatius Grippa ignatiusgri...@gmx.com:
 Hello,

 First time posting.

 I cannot get my Am29F010 EEPROM recognized by flashrom v0.9.8-r1889

That chip *should* be detected:
http://www.flashrom.org/Supported_hardware#Supported_flash_chips


 I'm using a 3Com PCI ethernet card (3C90xB)  that recognizes the EEPROM
 using a different program bromutil

So what does [b|c|oc]romutil [1] do what the code in flashrom's
nic3com.c doesn't do?

http://git.etherboot.org/gpxe.git/tree/90bffed805ec453d2f75e61157b73eb2bb6b1fe1:/contrib/3c90xutil

 I've also tested my 3Com using a different chip AT29C010 which is recognized
  reads/writes with flashrom so I think it must be a software issue with the
 AMD.

 I can get flashrom to read the AMD to a file if I do a force -f -c
 Am29F010A/B but no write because it's not recognized.

Forcing shouldn't be necessary...

 I've attached my log. Seems flashrom is not reading the id codes correctly
 for the AMD. Instead it reads the first 2 bytes of info stored on the chip
 (4c ef in the log) However, probing for Atmel and many others retrieves the
 correct manufacturer/model id codes for the AM29F010 which is 01 20

 Any clue what might be happening? Thanks very much.

 Dave


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Re: [flashrom] 404 error on link to precompiled windows exe

2015-06-26 Thread Idwer Vollering

Hi,

2015-06-25 12:52 GMT+02:00 Michael Ayles michael.ay...@ttelectronics-ims.com:
Hi,

I’m a test development engineer and one of our clients has developed a board
with an EON EN25F20 SPI Flash. They provided a Bus Pirate and the firmware
file to be programmed and told us they use linux with flashrom to program
the parts.

Unfortunately the test solution we have developed runs windows for our test
solution. I’ve been unable to find a valid link to a precompiled executable
of flashrom for windows. The link on the (flashrom.org/windows) page
(http://ra.openbios.org/~idwer/flashrom/mingw/) returns a 404 error.

Indeed. Server configuration (which is outside my control) has
rendered this URL unreahable.

However, you can find win32 builds over here:
http://buildbot.flashrom.org/buildresults/

Could you please help me locate a .exe, I’m more of a hardware guy than
software and am struggling with the MINGW stuff.

You can find an (alpha quality) prebuilt .exe here:
http://buildbot.flashrom.org/buildresults/flashrom-000174-CcG/win32/

If you wish to reproduce the build yourself, here are in-a-nutshell
instructions:
http://flashrom.org/Windows#Building_.28cross-compiling.29_flashrom_on_Linux_for_Windows_using_MinGW.

Many thanks,

Michael Ayles

Test Development Engineer

IMS Testing Solutions (Abtest)

Abtest Ltd is a UKAS approved facility : Accreditation Number 0042

Tregwilym Industrial Estate, Rogerstone, Newport, South Wales, UK, NP10 9YA

T: +44 (0) 1443 290030 F: +44 (0) 1633 892770

E: michael.ay...@ttelectronics-ims.com

www.abtest.com

Abtest Ltd. Registration Number 620992 trading as IMS Testing Solutions

General Note: Please be aware,due to new security requirements , all visits
to Abtest must be booked in at least 24 hours in advance.

Confidentiality Notice:

This message is private and confidential. If received in error, please
destroy and notify sender. Sender does not intend to waive confidentiality
or privilege. Dissemination, use of or reliance upon this email is
prohibited when received in error. Email may be susceptible to data
corruption, interception and unauthorised amendment, and no liability is
accepted by the sender for any of the foregoing. It is the recipient’s
responsibility to scan the email and any attachment for viruses.

flashrom is open source software (GPL), and its mailing list is public
as well. Meeting such confidentiality disclaimers is impossible.
See http://www.flashrom.org/pipermail/flashrom/

HTH,

Idwer

TT electronics integrated manufacturing services Limited is a company
registered in England and Wales.

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Re: [flashrom] Support for AT25080

2015-03-18 Thread Idwer Vollering

2015-03-18 22:24 GMT+01:00 Roy Krikke roykri...@gmail.com:

 Hello,

 I have compiled the latest version of flashrom (flashrom v0.9.8-r1887) and
 hoped to flash my AT25080. But without suc6.

flashrom does not (yet) support this chip. We like patches :)


 I have connected a new AT25080 to a Raspberry Pi and hoped to flash the
 device with in system programming (ISP) mode.

 First erasing the device with sudo flashrom -E -V -p
 linux_spi:dev=/dev/spidev0.0

The command line command looks just fine, but flashrom doesn't support
this particular flash chip,


 No luke :(

 snapshot of flashrom below:
 Probing for Generic unknown SPI chip (RDID), 0 kB: RDID byte 0 parity
 violation. probe_spi_rdid_generic: id1 0x00, id2 0x00
 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI) on linux_spi.
 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x0,
 id2 0x0
 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI).
 ===
 This flash part has status NOT WORKING for operations: PROBE READ ERASE
 WRITE
 The test status of this chip may have been updated in the latest development
 version of flashrom. If you are running the latest development version,
 please email a report to flashrom@flashrom.org if any of the above
 operations
 work correctly for you with this flash chip. Please include the flashrom log
 file for all operations you tested (see the man page for details), and
 mention
 which mainboard or programmer you tested in the subject line.
 Thanks for your help!
 Read is not working on this chip. Aborting.

 Any kind of help is welcome, tips on how best to proceed!


 Thank you very much,

 Roy



 My previous post
 
 Hello,

 Is there support for the AT25080B device from ATMEL? It is not in the
 supported device list.

 http://www.atmel.com/Images/Atmel-5228-SEEPROM-AT25080B-160B-Datasheet.pdf

 Need to flash the AT25080B which is connected to a 82574L from intel. There
 are two 82574L with two AT25080B on my board. If I read from the first
 AT25080B the data is fine and I can also flash is. But the second one is not
 working at all.

 I compared/checked the SPI communication of the first one with the second
 one. This looks the same. So I thought maybe the second AT25080B is broken.
 After replacing it, still the same result.

 I hope to get is to work if I could flash is not by the SPI interface of the
 82574L, but by an in system programming (ISP). Example shown in
 http://satxhackers.org/wp/hack-content/uploads/2013/04/rPI_flashrom.pdf

 Any kind of help is welcome.

 Thanks,

 Roy




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Re: [flashrom] flashrom support for Spansion S25FL128S

2015-02-16 Thread Idwer Vollering

2015-02-16 22:19 GMT+01:00  lakesh_sha...@dell.com:
 Dell - Internal Use - Confidential

This disclaimer is useless on a public mailing list ;)


 Hello flashrom team.





 We are trying to access Spansion S25FL128S chip using flashrom (ver 0.9.7).

 It is connected to Rangeley cpu using SPI i/f.

 It seems that this chip is not supported in current version of flashrom ?

Support for that particular chip is present in development code, see
subversion revision r1858 (
http://tracker.coreboot.org/trac/flashrom/changeset/1858 ).
You can obtain the development code through the steps mentioned here:
http://flashrom.org/Downloads#Installation_from_source


 Pls see  the errors seen during read and write in attachments.



 Do we need to import patch listed in url below for suppothing this chip:



 http://flashrom.flashrom.narkive.com/zDxnVzWn/s25fl128s-0-on-usbblaster-spi





 regards

 lakesh

HTH,

Idwer



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Re: [flashrom] [PATCH] Add programmer for the MSTAR I2C ISP protocol

2015-02-08 Thread Idwer Vollering

2014-05-04 18:20 GMT+02:00 Alexandre Boeglin a...@boeglin.org:
 Hi,

 Here is a patch, that provides support for the MSTAR ISP protocol.

 Basically, among other chips, MSTAR manufactures SoCs that equip TV sets
 and computer screens, and it seems that all of their products use the
 same in-system programming protocol. Basically, they use the DDC channel
 of VGA or DVI connectors, which is actually an I2C bus, to encapsulate
 SPI frames (the flash chip is connected to the SoC through an SPI bus).

 I wrote this patch since the screen I bought had a software bug, and the
 manufacturer only released a new firmware binary, but no tool or
 instructions on flashing it.

 More details can be found here:
 http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(dom)

There seems to be a silicon (=SoC) bug as well.

One can recover by rotating the original image (YOU DO HAVE BACKUPS,
RIGHT :) ) _back_wards - the example assumes the read file is 128
kilobyte large:
tail -c 1 orig_read.bin  realimage.bin; head -c 131071 orig_read.bin
 realimage.bin; flashrom -p mstar -w realimage.bin --noverify

HTH,

Idwer

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Re: [flashrom] flashrom error ioctl

2014-11-11 Thread Idwer Vollering

2014-11-11 21:26 GMT+01:00 Jorge Mesquita jo...@jmtech.com.py:

 Hi, im trying to program a flash on hardkernel's odroid u3,

 my paste is here any help would be appreciated, thanks.

Quote from paste:

root@odroid:/home/odroid/flashrom-0.9.7# ./flashrom -p
linux_spi:dev=/dev/spidev1.0 -E
flashrom v0.9.7-r1711 on Linux 3.8.13.28 (armv7l)
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found Winbond flash chip W25Q64.V (8192 kB, SPI) on linux_spi.
Erasing and writing flash chip... linux_spi_send_command: ioctl:
Input/output error
Verification impossible because read failed at 0x0 (len 0x1000)
ERASE FAILED!
Reading current flash chip contents... linux_spi_send_command: ioctl:
Input/output error
Can't read anymore! Aborting.
FAILED!
Your flash chip is in an unknown state.
Please report this on IRC at chat.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org, thanks!


Can you re-run the same command, but this time add one -V parameter?
Are you familiar with strace and/or gdb?

Idwer

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[flashrom] [patch] exit when the same filename is used for reading/writing flash chip content and to store log output

2014-08-21 Thread Idwer Vollering

Tested on physical hardware, built on FreeBSD (less portability 'headaches').

Signed-off-By: Idwer Vollering vid...@gmail.com

Index: cli_output.c
===
--- cli_output.c(revision 1846)
+++ cli_output.c(working copy)
@@ -52,8 +52,12 @@
msg_gerr(No logfile name specified.\n);
return 1;
}
-   if ((logfile = fopen(filename, w)) == NULL) {
+   if ((logfile = fopen(filename, xw)) == NULL) {
msg_gerr(Error: opening log file \%s\ failed:
%s\n, filename, strerror(errno));
+   msg_gdbg(This means that flashrom can't write log output\n \
+   to the file you specified (\%s\),\n \
+   or you are using the same filename to read
from/write to (-r / -w)\n \
+   and write the log output to (-o).\n, filename);
return 1;
}
return 0;

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Re: [flashrom] strange behaviour of flashrom

2014-06-20 Thread Idwer Vollering

2014-06-20 22:42 GMT+02:00 KOLANICH kola...@mail.ru:
 It is very strange.

Actually it is not: flashrom ('s source code) just became louder about
every flash chip status 'core'.

Quoting the file flashrom_log.txt you have attached:
Found Spansion flash chip S25FL008A (1024 kB, SPI).
===
This flash part has status UNTESTED for operations: WRITE

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Re: [flashrom] nice Programm, but failed this time :(

2014-05-08 Thread Idwer Vollering

2014-05-08 12:07 GMT+02:00 Benedikt Tissot benedikt.tis...@googlemail.com:

Subject Re: [flashrom] nice Programm, but failed this time :(

flashrom does indeed show some warnings, however there are good bits too:

Good bits:
 flashrom v0.9.7-r1711 on Linux 3.14.2-1-ARCH (x86_64)
 Found chipset Intel H77. Enabling flash write...

Warnings:
 Warning: BIOS region SMM protection is enabled!
 Warning: Setting Bios Control at 0xdc from 0x2a to 0x0b on H77 failed.
 Warning: SPI Configuration Lockdown activated.
 PROBLEMS, continuing anyway

Good bits:
 Found Winbond flash chip W25Q64.V (8192 kB, SPI) at physical address 
 0xff80.
 Reading old flash chip contents... done.

Warnings:
 Verifying flash... FAILED at 0x2000! Expected=0x46, Found=0xff, failed
 byte count from 0x-0x007f: 0x1dd50



Then on to the console output from writing:

 [benneti@TiProdigy ~]$ sudo flashrom --programmer internal -f -w 
 '/home/benneti/flashed.rom'
 flashrom v0.9.7-r1711 on Linux 3.14.2-1-ARCH (x86_64)

Good bits:
 Found Winbond flash chip W25Q64.V (8192 kB, SPI) at physical address 
 0xff80.
 Reading old flash chip contents... done.

Warnings:
 Erasing and writing flash chip... Transaction error!
 spi_block_erase_20 failed during command execution at address 0x18
 Reading current flash chip contents... done. spi_block_erase_52 failed
 during command execution at address 0x18
 Reading current flash chip contents... done. spi_block_erase_d8 failed
 during command execution at address 0x18
 Reading current flash chip contents... done. spi_chip_erase_60 failed during
 command execution
 Reading current flash chip contents... done. spi_chip_erase_c7 failed during
 command execution
 FAILED!
 Uh oh. Erase/write failed. Checking if anything changed.

Good bits:
 Good. It seems nothing was changed.
 Writing to the flash chip apparently didn't do anything.
 This means we have to add special support for your board, programmer or
 flash
 chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or
 mail flashrom@flashrom.org, thanks!
 ---
 You may now reboot or simply leave the machine running.


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[flashrom] [patch] add SST25LF020A SPI flash chip support

2014-05-06 Thread Idwer Vollering

See patch.

Signed-off-by: Idwer Vollering vid...@gmail.com
Index: flashchips.c
===
--- flashchips.c	(revision 1786)
+++ flashchips.c	(working copy)
@@ -9614,6 +9614,38 @@
 
 	{
 		.vendor		= SST,
+		.name		= SST25LF020A,
+		.bustype	= BUS_SPI,
+		.manufacture_id	= SST_ID,
+		.model_id	= SST_SST25VF020_REMS,
+		.total_size	= 256,
+		.page_size	= 256,
+		.feature_bits	= FEATURE_WRSR_EWSR,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_spi_rems,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+.eraseblocks = { {4 * 1024, 64} },
+.block_erase = spi_block_erase_20,
+			}, {
+.eraseblocks = { {32 * 1024, 8} },
+.block_erase = spi_block_erase_52,
+			}, {
+.eraseblocks = { {256 * 1024, 1} },
+.block_erase = spi_block_erase_60,
+			},
+		},
+		.printlock	= spi_prettyprint_status_register_sst25, /* FIXME: No BP2  3 */
+		.unlock		= spi_disable_blockprotect,
+		.write		= spi_chip_write_1, /* AAI supported, but opcode is 0xAF */
+		.read		= spi_chip_read, /* only */
+		.voltage	= {2700, 3600},
+	},
+
+	{
+		.vendor		= SST,
 		.name		= SST25LF040A,
 		.bustype	= BUS_SPI,
 		.manufacture_id	= SST_ID,
Index: flashchips.h
===
--- flashchips.h	(revision 1786)
+++ flashchips.h	(working copy)
@@ -574,6 +574,7 @@
  * byte of device ID is related to log(bitsize) at least for some chips.
  */
 #define SST_ID			0xBF	/* SST */
+#define SST_SST25LF020_REMS	0x43	/* REMS or RES opcode */
 #define SST_SST25WF512		0x2501
 #define SST_SST25WF010		0x2502
 #define SST_SST25WF020		0x2503
@@ -581,7 +582,7 @@
 #define SST_SST25WF080		0x2505
 #define SST_SST25VF512A_REMS	0x48	/* REMS or RES opcode */
 #define SST_SST25VF010_REMS	0x49	/* REMS or RES opcode */
-#define SST_SST25VF020_REMS	0x43	/* REMS or RES opcode */
+#define SST_SST25VF020_REMS	0x43	/* REMS or RES opcode, same as SST25LF020A */
 #define SST_SST25VF020B		0x258C
 #define SST_SST25VF040_REMS	0x44	/* REMS or RES opcode, same as SST25LF040A */
 #define SST_SST25VF040B		0x258D
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Re: [flashrom] Bus Pirate v4

2014-05-01 Thread Idwer Vollering

2014-05-01 13:36 GMT+02:00 Stefan Tauner stefan.tau...@alumni.tuwien.ac.at:
 On Thu, 1 May 2014 12:12:50 +0200
 Jan Hagedorn jan.hagedorn.1...@t-online.de wrote:

 Ok I will do that. Will send the log by mail to you? The BP FW is up to date 
 (6.3 I think). But the Windows snapshot of flashrom seems to be a bit old. 
 Is there maybe a newer one available? I tried to build one but I'm totally 
 lost as I am an absolute newbie to Linux...

Try http://ra.openbios.org/~idwer/flashrom/mingw/mingw32-w64-flashrom-r1781.exe
and
if you need libusb DLLs: they are found in
http://ra.openbios.org/~idwer/flashrom/mingw/flashrom-0.9.6.1-r1705-mingw.7z


 Our buildbot was killed by a RAID failure last year and we were too
 lazy (I mean busy) too resurrect it yet, that's why there are no
 current builds floating around. You did not mention which version you
 are using yet... a log would also have helped with that ;)
 I think I can cross-compile windows binaries for you if need be, but I
 presume the latest available are good enough.

 --
 Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Can I get some help?

2014-04-26 Thread Idwer Vollering

2014-04-26 19:39 GMT+02:00 Jonathan B. Horen jbho...@gmail.com:

 Uh oh. Erase/write failed. Checking if anything changed.
 Good. It seems nothing was changed.
 Writing to the flash chip apparently didn't do anything.
 This means we have to add special support for your board, programmer or
 flash chip. Please report this on IRC at chat.freenode.net (channel 
 #flashrom) or
 mail flashrom@flashrom.org, thanks!
 ---
 You may now reboot or simply leave the machine running.

 I guess the problem is solved.

No - instead a write/erase protection is active.

We need special code to support writing on your mainboard.
Please upload the output of 'flashrom -p internal -V', 'lspci
-nnvvvxxx', 'superiotool -deV' (run all commands as root) and the file
read with 'flashrom -p internal -r readout.rom' to
http://paste.flashrom.org. Send all resulting URLs to
flashrom@flashrom.org and mention the exact name of your board
(including revision, if there are multiple revisions) in the subject.

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Re: [flashrom] flashrom help

2014-04-12 Thread Idwer Vollering

2014-04-12 12:42 GMT+02:00 Mladen Milinkovic max...@smoothware.net:
 Hello Idwer,

 Sorry for bothering you, have seen you mail on mailing list
 Just wanted to thank you for your help on irc with flashing.
 Everything went fine and is working fine.

Great!

For completeness, this is about dualbios on the GIGABYTE GA-B85M-D3H
mainboard, which uses the ITE IT8728F superio chip.


 thanks
  maxrd2


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Re: [flashrom] GSoCs Winflashrom versus r126.

2014-04-10 Thread Idwer Vollering

2014-04-09 11:07 GMT+02:00 Aparecido David Esperanca
aparecidoda...@icloud.com:
 Por favor nos ajudar estamos com wise s-10 com firmware de 2008 gostaria DD 
 uma atualização mais recente para rodar.  Em server 2012 caso possa nos 
 ajudar ficarei extremamente grato

We tend to communicate in English, not Portuguese. This unfortunately,
again, leads to language barriers.

About Windows Server 2012 support: if a driver exist for this
particular operating system, flashrom *could* read from, and write to,
the flash chip that the mainboard in question boots from.
Look at the shape that has 'boot flash' written on it:
http://stuge.se/pc2010.png

I doubt that a public driver that does that exactly exists, so you
will want to consider using linux or FreeBSD (or any other OS that
supports direct flash chip access) to update system flash.

HTH,

Idwer

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Re: [flashrom] How To Determine Chip Name In The Case Of Multiple Flash Chip Definitions Matched

2014-04-02 Thread Idwer Vollering

2014-04-01 4:41 GMT+02:00 Andrew Ngo andyh...@hotmail.com:
Hello, the flashrom Community,

I am trying to flash my server with flashrom. Motherboard is X8DA3 made
by Supermicro. The command I used is: flashrom -w myFileName -p internal.
Following are the errors:

Found Macronix flash chip MX25L3205(A) (4096KB, SPI) at physical address
0xffc0
Found Macronix flash chip MX25L3205D/MX25L3208D (4096KB, SPI) at physical
address 0xffc0
Found Macronix flash chip MX25L3206E (4096KB, SPI) at physical address
0xffc0
Multiple flash chip definitions match the detected chip(s): MX25L3205(A),
MX25L3205D/MX25L3208D, MX25L3206E
Please specify which chip definition to use with the -c chipname option

I also noticed that there is another flash chip related to the 32MB Macronix
flash chip on the support list, namely the MX25L3235D.

That's megabit, not megabyte ;) so 32mbit would make 4 megabyte.
That chip is connected to the mainboard's remote management features.

However, the array in the flashrom program only allocates array size of 3 and
thus this chip
name is not printed out.

Question:
1. Are all these chip name the same?

No, there most likely are subtle differences like page/sector size,
environment friendlyness, etcetera.

2. If they are not the same, which chipname should I use with the -c
option?

This is where you subject the flash chip to a visual exam.
Photo of the mainboard:
http://upload.wikimedia.org/wikipedia/commons/b/bf/Mainboard_supermicro_x8da3_IMGP0593_wp.jpg
Here, the flash chip is located to the right of the middle PCI slot.

3. Is there a way to automatically determine this chipname by c or python?
(My flashing application is written in python).

Thanks...
Andy Ngo
andrew.h@leidos.com
andyh...@hotmail.com

HTH,

Idwer

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Re: [flashrom] iscsi issue

2014-04-02 Thread Idwer Vollering

2014-04-02 5:07 GMT+02:00 Tsukasa Mcp_Reznor mcp_rez...@hotmail.com:
 okay, no rush, ipxe builds fine (used it a ton, have a good iscsi net). I'm
 converting to 2 separate networks, so I'm skipping the pxe with chaining
 configs, I have a few intel 1000 gt cards, with the intel util it won't use
 .rom files, so I used flashrom, no issues there, the issue is on boot, my
 normal script sets the ip/netmask/gateway and does sanboot
 iscsi:blahtarget:diskname. but with the flashed rom (with embedded
 script) the first time flashing, I got a blue rectangle on the bottom left,
 with a smaller white rectangle to the right of it, and it didn't load the
 disk, my 2nd try, I get nothing after it shows ipxe and the version and
 clears the screen, so I used the control B method, using the same script
 typed out, it won't connect, until I filled out the initiator-iqn and I also
 had to issues ifopen

 then I get that it attached to 0x80, and booting 0x80, but it doesn't go any
 farther and actually boot
 any pointers on what might be wrong?  I did pad the .rom using dd, verified
 the size, if the pci ID helps its 8086107c
 I believe the romchip was a w25x10, 128Kb, I used the nicintel_sbi
 programmer
 not sure how much more clear I can be on my own, so if you have any
 questions I'll idle away :)

 Thanks for your time and for making flashrom, it's a great utility that I'm
 going to be using alot over the next few weeks

From all that information I would expect this to be an ipxe issue.

ipxe seems to have some ways of showing what is going on (or not) while booting:
http://ipxe.org/buildcfg/log_level
http://ipxe.org/buildcfg/console_serial
http://ipxe.org/buildcfg/console_syslog

And you can reach the developers through ways listed here:
http://ipxe.org/contact

HTH,

Idwer

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Re: [flashrom] error reporting

2014-03-30 Thread Idwer Vollering

2014-03-30 14:28 GMT+02:00 Adam Vegh devi...@zioncity.hu:
 Erase/write done.
 Verifying flash... FAILED at 0x0055bc8b! Expected=0x71, Found=0x48, failed
 byte count from 0x-0x007f: 0x217dbe
 Your flash chip is in an unknown state.

Hello Adam,

Can you supply all output (like which version of flashrom errors out
on which chipset and mainboard)?
Run flashrom with at least one level of verbosity, add a -V parameter.
Newer versions of flashrom can save output to a file with '-o name of
logfile'.

HTH,

Idwer

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Re: [flashrom] CHIPSET: ALIX 2d13

2014-03-18 Thread Idwer Vollering

2014-03-18 18:49 GMT+01:00 Timo Buhrmester t...@math.uni-bonn.de:

 flashrom on debian wheezy told me to mail you.
 The board in question is this one: http://pcengines.ch/alix2d13.htm

  Found chipset AMD CS5536. Enabling flash write... OK.
  WARNING: unexpected second chipset match: AMD CS5536
  ignoring, please report lspci and board URL to flashrom@flashrom.org
  with 'CHIPSET: your board name' in the subject line.
  Found SST flash chip SST49LF080A (1024 kB, LPC) at physical address
 0xfff0.
  Reading flash... done.

 # lspci -vvvxxx
 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion]
 Host Bridge (rev 33)
 Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion]
 Host Bridge
 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
 ParErr- Stepping- SERR- FastB2B- DisINTx-
 Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium TAbort-
 TAbort- MAbort- SERR- PERR- INTx-
 Latency: 248, Cache Line Size: 32 bytes
 Region 0: I/O ports at ac1c [size=4]
 00: 22 10 80 20 05 00 20 02 33 00 00 06 08 f8 80 00

 ^^ ^^
The above numbers read as 0x1022, 0x2080

Only one line should match, see
https://github.com/stefanct/flashrom/blob/master/chipset_enable.c#L1375
Which version of flashrom are you using?
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Re: [flashrom] [PATCH] Add support for 82574L to nicintel_spi.c

2014-03-14 Thread Idwer Vollering

2014-03-13 22:59 GMT+01:00 Bill Paul wp...@windriver.com:

 I recently found a need to re-flash the option ROM on an Intel 82574L
 gigabit
 ethernet card. These are a bit more common these days than the 82571 and
 82572
 and relatively cheap. It turns out this works with flashrom, but it doesn't
 detect the PCI ID for the device out of the box. Below is a patch add it to
 nicintel_spi.c. Note that there are probably other devices in the PRO/1000
 family that would work too.

 Here's an example run with the latest code from svn:

 [...]
 flashrom v0.9.7-unknown on FreeBSD 10.0-RELEASE (amd64)
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OK.
 Found Winbond flash chip W25X40 (512 kB, SPI) on nicintel_spi.
 Reading old flash chip contents... done.
 Erasing and writing flash chip... Erase/write done.
 Verifying flash... VERIFIED.
 [...]

 FreeBSD detects the device as follows:

 em1@pci0:2:0:0: class=0x02 card=0xa01f8086 chip=0x10d38086 rev=0x00
 hdr=0x00
 vendor = 'Intel Corporation'
 device = '82574L Gigabit Network Connection'
 class  = network
 subclass   = ethernet

 I also added links to the Intel PCIe ethernet controllers programming
 manual
 and the 82574 datasheet.

 Incidentally, thanks to everyone involved for their work in this project.
 It
 helped me out of a bit of a jam.

 -Bill

 Signed-off-by: Bill Paul wp...@windriver.com


This patch is Acked-by: Idwer Vollering vid...@gmail.com
when you adjust the PDF URL in a follow-up patch, see below.


 Index: nicintel_spi.c
 ===
 --- nicintel_spi.c  (revision 1765)
 +++ nicintel_spi.c  (working copy)
 @@ -17,14 +17,20 @@
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301
 USA
   */

  /*
 - * Datasheet:
 + * Datasheets:
   * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's
 Manual
   * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
   * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf


Would you change the hyperlink above to point to
http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.htmlinstead?
That way it is inline with the other comments.


 + *
 + * PCIe GbE Controllers Open Source Software Developer's Manual
 + * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-
 controllers-open-source-manual.html
 + *
 + * Intel 82574 Gigabit Ethernet Controller Family Datasheet
 + *
 http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-
 controller-datasheet.html
   */

  #include stdlib.h
  #include unistd.h
  #include flash.h
 @@ -70,10 +76,11 @@
  const struct dev_entry nics_intel_spi[] = {
 {PCI_VENDOR_ID_INTEL, 0x105e, OK, Intel, 82571EB Gigabit
 Ethernet
 Controller},
 {PCI_VENDOR_ID_INTEL, 0x1076, OK, Intel, 82541GI Gigabit
 Ethernet
 Controller},
 {PCI_VENDOR_ID_INTEL, 0x107c, OK, Intel, 82541PI Gigabit
 Ethernet
 Controller},
 {PCI_VENDOR_ID_INTEL, 0x10b9, OK, Intel, 82572EI Gigabit
 Ethernet
 Controller},
 +   {PCI_VENDOR_ID_INTEL, 0x10d3, OK, Intel, 82574L Gigabit Ethernet
 Controller},

 {0},
  };

  static void nicintel_request_spibus(void)

 --

 =
 -Bill Paul(510) 749-2329 | Senior Member of Technical Staff,
  wp...@windriver.com | Master of Unix-Fu - Wind River
 Systems

 =
I put a dollar in a change machine. Nothing changed. - George Carlin

 =

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Re: [flashrom] FAILED: SST49LF004A/B

2014-02-28 Thread Idwer Vollering

2014-02-25 23:39 GMT+01:00 Stefan Tauner
stefan.tstefan.tau...@student.tuwien.ac.at

 In that case your boards need a so-called board enable.


See http://flashrom.org/Board_Enable#Reverse_Engineering_your_BIOS

Additional information and details can be found here:
http://www.flashrom.org/Laptop_enable
http://flashrom.org/Board_Testing_HOWTO

HTH,

Idwer
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Re: [flashrom] Compatibility with ECS Socket AM2+

2014-02-28 Thread Idwer Vollering

2014-02-27 20:32 GMT+01:00 Leif Middelschulte leif.middelschu...@gmail.com
:

 Hi,

 firstofall thanks for your effort with flashrom. It’s really great to be
 able to flash a bios image independently of Windows.

 Sorry I didn’t catch the entire/verbose output. Nevertheless I could
 successfully flash a vendor bios for the following Motherboard:

 http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=865MenuID=20LanID=0


Mainboard name is ECS GeForce7050M-M V2.0t
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Re: [flashrom] Problems with Jetway Board and Winbond chip

2014-02-17 Thread Idwer Vollering

2014-01-16 9:22 GMT+01:00 Hans-Martin Roßmann ha-ma.rossm...@gmx.net:

 Hey there…

 first of all: Thank you for that incredible flashrom tool.
 But sadly: I can not write my BIOS chip on my Jetway Board.

 I got a Jetway NC96FL Mainboard with a Winbond W25Q80BV BIOS Chip, Intel
 NM10 Chipset and running Ubuntu 10.10.
 Flashrom detects the chip and the chipset well, but can not disable block
 protection. So it is not possible to write.

 I also tried to flash the chip with the Serprog/Arduino-Flasher on an
 Arduino Uno and it works. (But I want to burn it with my Jetway Board.)
 Then I tried to write it in my Jetway Board with manual raising the
 /WP-Pin of the Winbond Chip to VCC and it works too.
 So is it something (GPIO) to raise the /WP-Pin in the chipset?

Can somebody help me?


The write protection is applied/released by code in the bootblock (or
however EFI does that, nowadays)

You can retrieve the bootblock with bios_extract:
http://review.coreboot.org/gitweb?p=bios_extract.git;a=summary

Here are some writeups that can get you on the right track.
http://flashrom.org/Laptop_enable
http://flashrom.org/Finding_Board_Enable_by_Reverse_Engineering
http://flashrom.org/Board_Enable



 I attached the logs from:
 $ flashrom -p internal -w flash.rom (write.log)
 $ flashrom -p internal -V (flash.log)
 $ lspci -nnvvxxx (lspci.log)
 $ superiotool -deV (superio.log)

 Thanks a lot,

 Hans-Martin


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Re: [flashrom] Flashing fails with SF100

2014-02-13 Thread Idwer Vollering

2014-02-12 13:34 GMT+01:00 Arun Chandran achand...@mvista.com:
 Hi,

 I am using the latest flashrom. I am unable to flashBIOS using dediprog sf
 100 programmer.

 The log is pasted below. Please help.
 ###

 arun@arun-OptiPlex-9010:~/work/vview/flashrom$ sudo flashrom -p internal -w
 BYTI_072_011_ReleasePackage/BYTICRB__X64_R_0072_11_SeC_Enable.bin -V

When you run flashrom like that, you will tell it to write
'BYTI_072_011_ReleasePackage/BYTICRB__X64_R_0072_11_SeC_Enable.bin' to
your optiplex' mainboard flash chip, not to the flash chip connected
to your dediprog. (hint: change the target programmer after reading
the comment below)

Most, if not all, distributions package without compiling in dediprog
support. If this is the case, this means that you must compile
flashrom with dediprog support yourself.
Instructions are found here:
http://flashrom.org/Downloads#Installation_from_source

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Re: [flashrom] Motherboard Support Inquiry

2014-02-11 Thread Idwer Vollering

2014-02-11 9:00 GMT+01:00 Anthony Ross anthonyross...@gmail.com:
 Hello One and all
 Well Im new to this mailing list  would like to confirm if flashrom
 supports my motherboard. Here is the output of Flashrom  lspci

 user#flashrom -V -p internal
 flashrom v0.9.7-r1711 on Linux 3.5.0-23-generic (i686)
 flashrom is free software, get the source code at http://www.flashrom.org

 flashrom was built with libpci 3.1.8, GCC 4.4.7, little endian
 Command line (3 args): flashrom -V -p internal
 Calibrating delay loop... OS timer resolution is 1 usecs, 1725M loops
 per second, delay more than 10% too short (got 89% of expected delay),
 recalculating... 1702M loops per second, delay more than 10% too short
 (got 87% of expected delay), recalculating... 1827M loops per second, 10
 myus = 9 us, 100 myus = 93 us, 1000 myus = 930 us, 1 myus = 9310 us,
 4 myus = 4 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: 
 DMI string system-product-name: 
 DMI string system-version: 
 DMI string baseboard-manufacturer: Intel Corporation
 DMI string baseboard-product-name: D945GCCR
 DMI string baseboard-version: AAD78647-304
 DMI string chassis-type: Desktop
 Found ITE Super I/O, ID 0x8603 on port 0x2e
 Found chipset Intel ICH7/ICH7R with PCI ID 8086:27b8. Enabling flash
 write...
 0xfff8/0xffb8 FWH IDSEL: 0x0
 0xfff0/0xffb0 FWH IDSEL: 0x0
 0xffe8/0xffa8 FWH IDSEL: 0x1
 0xffe0/0xffa0 FWH IDSEL: 0x1
 0xffd8/0xff98 FWH IDSEL: 0x2
 0xffd0/0xff90 FWH IDSEL: 0x2
 0xffc8/0xff88 FWH IDSEL: 0x3
 0xffc0/0xff80 FWH IDSEL: 0x3
 0xff70/0xff30 FWH IDSEL: 0x4
 0xff60/0xff20 FWH IDSEL: 0x5
 0xff50/0xff10 FWH IDSEL: 0x6
 0xff40/0xff00 FWH IDSEL: 0x7
 0xfff8/0xffb8 FWH decode enabled
 0xfff0/0xffb0 FWH decode enabled
 0xffe8/0xffa8 FWH decode disabled
 0xffe0/0xffa0 FWH decode disabled
 0xffd8/0xff98 FWH decode disabled
 0xffd0/0xff90 FWH decode disabled
 0xffc8/0xff88 FWH decode disabled
 0xffc0/0xff80 FWH decode disabled
 0xff70/0xff30 FWH decode disabled
 0xff60/0xff20 FWH decode disabled
 0xff50/0xff10 FWH decode disabled
 0xff40/0xff00 FWH decode disabled
 Maximum FWH chip size: 0x10 bytes
 BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled
 Warning: Setting Bios Control at 0xdc from 0x02 to 0x03 on ICH7/ICH7R
 failed.

This is/could be blocking.

 New value is 0x02.
 Root Complex Register Block address = 0xfed1c000
 GCS = 0x50444: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1
 (SPI)
 Top Swap : not enabled
 SPIBAR = 0xfed1c000 + 0x3020
 0x00: 0x0004 (SPIS)
 0x02: 0x4004 (SPIC)
 0x04: 0x (SPIA)
 0x08: 0x (SPID0)
 0x0c: 0x (SPID0+4)
 0x10: 0x (SPID1)
 0x14: 0x (SPID1+4)
 0x18: 0x (SPID2)
 0x1c: 0x (SPID2+4)
 0x20: 0x (SPID3)
 0x24: 0x (SPID3+4)
 0x28: 0x (SPID4)
 0x2c: 0x (SPID4+4)
 0x30: 0x (SPID5)
 0x34: 0x (SPID5+4)
 0x38: 0x (SPID6)
 0x3c: 0x (SPID6+4)
 0x40: 0x (SPID7)
 0x44: 0x (SPID7+4)
 0x50: 0x00f8 (BBAR)
 0x54: 0x0004 (PREOP)
 0x56: 0x (OPTYPE)
 0x58: 0x0005 (OPMENU)
 0x5c: 0x (OPMENU+4)
 0x60: 0x (PBR0)
 0x64: 0x (PBR1)
 0x68: 0x (PBR2)
 Programming OPCODES... done
 SPI Read Configuration: prefetching disabled, caching enabled, PROBLEMS,
 continuing anyway

This too.

 Super I/O ID 0x8603 is not on the list of flash capable controllers.
 The following protocols are supported: SPI.
 Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef,
 id2 0x3013
 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef,
 id2 0x3013
 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2
 0x3013
 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef,

Re: [flashrom] [PATCH] Bus Pirate UART speedup.

2014-02-08 Thread Idwer Vollering

2013-04-01 18:49 GMT+02:00 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 Increase PIC/FT232 UART speed to 2 Mbaud (instead of 115200 baud) in
 firmware 5.5 and newer. Given that UART speed is the biggest bottleneck
 for Bus Pirate communication (right now 90% of the read time is caused
 by slow BP-host communication), this patch is absolutely needed to get
 any decent speed out of the Bus Pirate.

 WARNING: This patch may hang flashrom or corrupt data for any non-v3 Bus
 Pirate model. I haven't tested such models, and it might work without
 problems. Who knows. We would have to find someone with a v2 (or
 earlier) Bus Pirate and a firmware version =v5.5 to test this. For Bus
 Pirate model v4 this patch may be completely superfluous. Anyway,
 activating fast UART only for some models is probably the way to go. We
 already have code to determine the hardware model in the init function,
 this just needs to be stored in some variable.

I've applied this patch but it doesn't use 2Mbaud on my buspirate v3.a
with firmware v6.3-beta1 r2088 or v6.3-beta1 r2151, nor will it
proceed to probing. Platforms used are linux and windows.

flashrom v0.9.7-r1764 on Linux 3.10-3-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian
Command line (5 args): ./flashrom -VVV -p
buspirate_spi:dev=/dev/ttyUSB0 -r buspirate_read.bin
Calibrating delay loop... OS timer resolution is 1 usecs, 945M loops
per second, 10 myus = 12 us, 100 myus = 119 us, 1000 myus = 1187 us,
1 myus = 11863 us, 4 myus = 5 us, OK.
Initializing buspirate_spi programmer
Baud rate is 115200 now.
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 1, read 0 Sending 0x00
buspirate_sendrecv: write 0, read 4 , receiving 0x42 0x42 0x49 0x4f
buspirate_sendrecv: write 1, read 0 Sending 0x0f
buspirate_sendrecv: write 0, read 6 , receiving 0x31 0x01 0x0d 0x0a 0x42 0x75
buspirate_sendrecv: write 0, read 1 , receiving 0x73
buspirate_sendrecv: write 0, read 1 , receiving 0x20
buspirate_sendrecv: write 0, read 1 , receiving 0x50
buspirate_sendrecv: write 0, read 1 , receiving 0x69
buspirate_sendrecv: write 0, read 1 , receiving 0x72
buspirate_sendrecv: write 0, read 1 , receiving 0x61
buspirate_sendrecv: write 0, read 1 , receiving 0x74
buspirate_sendrecv: write 0, read 1 , receiving 0x65
buspirate_sendrecv: write 0, read 1 , receiving 0x20
buspirate_sendrecv: write 0, read 1 , receiving 0x76
buspirate_sendrecv: write 0, read 1 , receiving 0x33
buspirate_sendrecv: write 0, read 1 , receiving 0x2e
buspirate_sendrecv: write 0, read 1 , receiving 0x61
buspirate_sendrecv: write 0, read 1 , receiving 0x0d
Detected Bus Pirate hardware v3.a
buspirate_sendrecv: write 0, read 8 , receiving 0x0a 0x46 0x69 0x72
0x6d 0x77 0x61 0x72
buspirate_sendrecv: write 0, read 1 , receiving 0x65
buspirate_sendrecv: write 0, read 1 , receiving 0x20
buspirate_sendrecv: write 0, read 1 , receiving 0x76
buspirate_sendrecv: write 0, read 1 , receiving 0x36
buspirate_sendrecv: write 0, read 1 , receiving 0x2e
buspirate_sendrecv: write 0, read 1 , receiving 0x33
buspirate_sendrecv: write 0, read 1 , receiving 0x2d
buspirate_sendrecv: write 0, read 1 , receiving 0x62
buspirate_sendrecv: write 0, read 1 , receiving 0x65
buspirate_sendrecv: write 0, read 1 , receiving 0x74
buspirate_sendrecv: write 0, read 1 , receiving 0x61
buspirate_sendrecv: write 0, read 1 , receiving 0x31
buspirate_sendrecv: write 0, read 1 , receiving 0x20
Detected Bus Pirate firmware 6.3 (v6.3-beta1)
buspirate_sendrecv: write 0, read 4 , receiving 0x72 0x32 0x30 0x38
buspirate_sendrecv: write 0, read 1 , receiving 0x38
buspirate_sendrecv: write 0, read 1 , receiving 0x20
buspirate_sendrecv: write 0, read 1 , receiving 0x20
buspirate_sendrecv: write 0, read 1 , receiving 0x42
buspirate_sendrecv: write 0, read 1 , receiving 0x6f
buspirate_sendrecv: write 0, read 1 , receiving 0x6f
buspirate_sendrecv: write 0, read 1 , receiving 0x74
buspirate_sendrecv: write 0, read 1 , receiving 0x6c
buspirate_sendrecv: write 0, read 1 , receiving 0x6f

Re: [flashrom] Issues recognizing Macronics 25L3205D using UM232H-B-WE

2014-02-03 Thread Idwer Vollering

2014-02-03 Jay Khan greekh...@hotmail.com:
 Hello,

 I am trying to get the Macronics Flash MX25L3205D using FTDI UM232H-B-WE
 with Flashrom 0.9.7-r1764 on lunux.

 The programmer UM232H seems to be supported based on
 http://flashrom.org/Supported_programmers
 The flash MX25L3205D seems to be supported based on:
 http://flashrom.org/Supported_hardware  (MX datasheet:
 http://www.macronix.com/Lists/DataSheet/Attachments/1534/MX25L6405D,%203V,%2064Mb,%20v1.5.pdf)

 I have the following pins connected using the following mapping and
 connected the MX flash using test clip:

 UM232H MappingMacronics (25L3205D)
 D0-SPI_SK6
 D1-SPI_DO   2
 D2-SPI_DI 5
 D3-SPI_CS1
 D4-SPI_WP  3
 D5-SPI_HOLD  7
 GND4
 VCC8(3.13v)

That mapping looks good, and when you apply VCC power to HOLD and WP
this flash chip should be detected.
Although this wiki page is about the buspirate, the connection section
applies to a great amount of flash chips:
http://flashrom.org/Bus_Pirate#Connections


 When I use flashrom with command line: flashrom -p ft2232_spi:type232H,
 flashrom replies with Found Generic flash chip unknown SPI chip (RDID) (0
 kB, SPI) on ft2232_spi. Unsupported etc..

 It is my understanding that the 25L3205D is supported and I am not sure why
 I would get this message. Any pointers would be very helpful.

 Thanks!



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Re: [flashrom] Issues recognizing Macronics 25L3205D using UM232H-B-WE

2014-02-03 Thread Idwer Vollering

2014-02-03 Jay Khan greekh...@hotmail.com:
 Thanks Idwer for your quick response.

 I changed the HOLD and WP to VCC still no luck; I am attaching the output
 with -V option; but it now does seem to detect the ID1 and ID2:

 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic:
 id1 0x7f7f, id2 0x7f

This is where you have to tell us where the chip is connected to, or
if it is desoldered :)
The wiki page http://flashrom.org/ISP describes the procedure of
writing a flash chip while it is (already/still) attached to the
circuit it is to be used with.


 Still gives the error as before:


 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI) on
 ft2232_spi.
 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x7f,
 id2 0x7f
 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI).
 ===

From the attached log file:

flashrom v0.9.7-r1764 on Linux 3.2.0-4-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.9, GCC 4.7.2, little endian
Command line (3 args): ./flashrom -p ft2232_spi:type=232H,port=A -V
Calibrating delay loop... OS timer resolution is 1 usecs, 2886M loops
per second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 1043 us,
1 myus = 9400 us, 4 myus = 4 us, OK.
Initializing ft2232_spi programmer
Using device type FTDI FT232H channel A.
Disable divide-by-5 front stage
Set clock divisor
MPSSE clock: 60.00 MHz, divisor: 2, SPI clock: 30.00 MHz
No loopback of TDI/DO TDO/DI
Set data bits
The following protocols are supported: SPI.
Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f7f
Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f7f
Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x7f7f,
id2 0x7f7f
Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f7f
Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f7f
Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic:
id1 0x7f7f, id2 0x7f
Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0x7f, id2 0x7f
Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0x7f, id2 0x7f
Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x7f7f, id2 0x7f
Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0x7f, id2 0x7f
Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0x7f, id2 0x7f
Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0x7f, id2 0x7f
Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f
Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1
0x7f7f, id2 0x7f

Re: [flashrom] MX25L25635F support?

2014-01-24 Thread Idwer Vollering

2014/1/24 Brian Rak b...@gameservers.com:
 How would I go about getting an additional chip supported?  I've got one of
 these:
 http://datasheet.octopart.com/MX25L25635FZNI-12G-Macronix-datasheet-12537112.pdf
 connected to a buspirate.  I'm able to detect it:

 Found Macronix flash chip unknown Macronix SPI chip (0 kB, SPI).

 but that's about it.  This isn't part of a BIOS (it's actually used by an
 IPMI controller), so I don't have any ability to attempt to use an internal
 programmer.

Which version or build of flashrom were you using? Chip support for
this MX25L25635F was committed a while ago:
http://flashrom.org/trac/flashrom/changeset/1702

See http://flashrom.org/Downloads#Installation_from_source for
instructions to download and compile flashrom's source code manually.

HTH,

Idwer

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Re: [flashrom] F2A85-M with flashrom

2014-01-18 Thread Idwer Vollering

Please include the mailinglist on the To: field hereafter, thanks :)

2014/1/18 HacKurx hack...@gmail.com:
 Hello,

 I have a error with flashrom on f2a85_m :
 ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.

 flashrom --programmer internal -r sauvegarde-bios.rom
 flashrom v0.9.7-r1720 on Linux 3.12.7 (x86_64)
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OK.
 Found chipset AMD FCH. Enabling flash write... ERROR: State of
 SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.
 PROBLEMS, continuing anyway
 No EEPROM/flash device found.
 Note: flashrom can never write if the flash chip isn't found automatically.

 How to solve this problem?

I ran into this too, and found out that F2A85M's BIOS v6404 prohibits
access where v5018 (the version that was preloaded on my board) does
not.

I haven't tried whether any other build (5103 or 5104 or 51047 or 5202
or 6002 or 6004 or 6102 or 6402) blocks full access.

To solve this problem: either downgrade or read the chip using (a
breadboard and) an external programmer.


 Thanks, Best regards,

 Loic
 http://hackurx.wordpress.com

HTH,

Idwer

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Re: [flashrom] Unsupported 3com device (3c905 100BaseTX [Boomerang])

2013-10-23 Thread Idwer Vollering

2013/10/23 san s...@plusnet.pl:
 W29EE011 does work with no problems.


 2013/10/23 san s...@plusnet.pl

 I have unsupported one, so i won't use it.

 PM29F002T is too big (256kB over 128kB).
 It does work at last for read.

 When erase it does work about 1/3 times.
 Once i suceed to write (after erase), and whole chip was programmed well!

 There is something wrong with erase function in nic3com, as i belive...

 Later i'll try to use W29EE011 (128kB).

 Regards!

What's the FCC ID of your 3Com (10b7:9050) NIC? Mine says DF63C905-TX
and 'ASSY 03-0104-005', 'REV A'.
Neither AT29C010, W29C011 or P28F001 was detected, over here.

Idwer

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Re: [flashrom] Unsupported 3com device (3c905 100BaseTX [Boomerang])

2013-10-22 Thread Idwer Vollering

2013/10/22 san s...@plusnet.pl:
 Hi!

 I own:
 02:00.0 Ethernet controller [0200]: 3Com Corporation 3c905 100BaseTX
 [Boomerang] [10b7:9050]

 It's unsupported:
 ---[code]---
 Error: No supported PCI device found.
 Error: Programmer initialization failed.
 ---[/code]---

 I would love to help You to get it to work with flashrom.
 Do You need it?

 Regards!

Yes, we would appreciate some testing.

Do you have a parallel DIP32 chip that you can insert into its socket?
Either SST39SF512, CAT28F125 or AT29C512 should work:
http://www.ebay.com/sch/i.html?_nkw=SST39SF512
http://www.ebay.com/sch/i.html?_nkw=CAT28F512
http://www.ebay.com/sch/i.html?_nkw=AT29C512

When you have that set up, apply this patch:

Index: nic3com.c
===
--- nic3com.c   (revision 1760)
+++ nic3com.c   (working copy)
@@ -37,6 +37,9 @@
 static uint16_t id;

 const struct dev_entry nics_3com[] = {
+   /* 3C905 */
+   {0x10b7, 0x9050, NT, 3COM, 3c905: Fast EtherLink XL PCI (3c905-TX)},
+
/* 3C90xB */
{0x10b7, 0x9055, OK, 3COM, 3C90xB: PCI 10/100 Mbps; shared
10BASE-T/100BASE-TX},
{0x10b7, 0x9001, NT, 3COM, 3C90xB: PCI 10/100 Mbps; shared
10BASE-T/100BASE-T4 },

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Re: [flashrom] flashrom behavior report: Sun Fire X4500 w/FlashROM 0.9.7

2013-08-26 Thread Idwer Vollering

2013/8/26 Rich rerc...@pha.jhu.edu

 A brief summary:
 Nothing works.

 # ./flashrom -p internal
 flashrom v0.9.7-r1711 on Linux 3.8.0-29-generic (x86_64)
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OK.
 Found chipset AMD AMD8111. Enabling flash write... OK.
 No EEPROM/flash device found.
 Note: flashrom can never write if the flash chip isn't found automatically.


It's likely that remote management (DRAC, iLO/IPMI) peripheral hardware are
hiding the flash chip.


 Log from lspci, superiotool, and flashrom 0.9.7 attached.


The X4500 is from 2006, my guess is that the flash chip comes in the TSOP
form factor: http://flashrom.org/Technology

Can you remove the CPU/processor board (and take a high resolution photo)?


 - Rich

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Re: [flashrom] Preserve BIOS settings for copying flash between identical machines

2013-08-19 Thread Idwer Vollering

2013/8/16 Clayton Falzone clayton.falz...@gmail.com

 After a successful flash on the next boot the firmware resorts to default
 config. Is there some way around this? It would be a useful feature to
 preserve settings between boots.


First: flashrom does not touch CMOS settings (nvram).
However, there is an utility called nvramtool:
http://www.coreboot.org/Nvramtool



 For example, reading the FLASHROM to a file...
 $ sudo flashrom -r bios_backup.bin -p internal
 And then writing the bios to an identical but physically different machine
 $ sudo flashrom -w bios_backup.bin -p internal

 It would be quite a feature to preserve settings to this new machine. Is
 this possible?


What's the name/type of the machine(s) you're using?



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Re: [flashrom] Flashrom advised to email!

2013-05-27 Thread Idwer Vollering

2013/5/24 Eamon M ea...@hotmail.co.uk:
 Hi,

 Flashrom advised to email.

 Flashing 2048k bios rom file to a Lanner FW-8750 motherboard gave the
 following error as attached.

 Any help would be gratefully received.

 Regards,
 Eamon

Alright, this took me a (damn long) while but I now have a
pfsense-2.0.3 binary that will work.

After you have installed libpci (will install as a symlink:
/usr/local/lib/libpci.so - /usr/local/lib/libpci.so.3) and dmidecode
(IIRC you have already done this), download and run
http://ra.openbios.org/~idwer/pfsense_package/flashrom_fbsd_8.1

You can ignore the need of gmake/subversion for now.

HTH,
Idwer

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Re: [flashrom] About flashing mx25l4005 on Itona TC2331

2013-05-15 Thread Idwer Vollering

2013/5/15 Bin X z2...@outlook.com:
 Thanks for the reply. I will do some homework on the coreboot.

 However I think my chanllenge here is to find a program (I don't have
 hardware programmer) to flash the chip. I run
 flashrom.exe -p internal -c MX25L4005(A/C) -VVV

 and here is what I got
 flashrom v0.9.6.1-r1671 on MS-DOS 7 (i686)
 flashrom is free software, get the source code at http://www.flashrom.org

 flashrom was built with libpci 3.1.5, GCC 4.4.4, little endian
 Command line (5 args): c:/bios/flashrom.exe -p internal -c MX25L4005(A/C)
 -VVV
 Calibrating delay loop... OS timer resolution is 11 usecs, 298M loops
 per second, delay more than 10% too short (got 84% of expected delay),
 recalculating... 347M loops per second, 10 myus = 0 us, 100 myus = 0 us,
 1000 myus = 0 us, 1 myus = 0 us, 44 myus = 44 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: 
 DMI string system-product-name: 
 DMI string system-version: 
 DMI string baseboard-manufacturer: 
 DMI string baseboard-product-name: 
 DMI string baseboard-version: 
 DMI string chassis-type: 
 DMI chassis-type is not specific enough.
 Found ITE Super I/O, ID 0x8712 on port 0x2e
 Bad Command or file name
 Bad Command or file name
 Bad Command or file name
 Bad Command or file name
 Bad Command or file name
 Bad Command or file name

 I am not sure which part is wrong. Is it because I don't have a full dos
 enviroment?

You seem to be missing dmidecode.exe, get it from
http://assembler.cz/flashrom/dmidecode.exe

The alternative is to run flashrom from any live-CD/USB Linux
distribution. Ubuntu Quantal/Raring and Debian testing/unstable can
install flashrom-0.9.6.1


 Thanks,

 Date: Tue, 14 May 2013 22:05:06 +0200
 From: vid...@gmail.com
 To: z2...@outlook.com
 CC: flashrom@flashrom.org; coreb...@coreboot.org
 Subject: Re: [flashrom] About flashing mx25l4005 on Itona TC2331


 2013/5/14 Bin X z2...@outlook.com:
  I apologize if it does not make sense at all since this is my first
  attempt
  to flash a bios with unmatched bios ID.
 
  I was trying to flash bios on a Itona TC2331 to get rid of the
  limitation
  they put on of any IDE HDD and USB HDD can’t be larger than 64mb.

 coreboot can do that, but you have to spend 'some' time on adding
 support for your particular mainboard.

 See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp
 (Chipset VIA CN700 chipset with VIA VT8237R Plus) and
 http://www.coreboot.org/Supported_Chipsets_and_Devices

 
  The current bios rom, flash program and documentation can be found here:
 
  ftp://ftpguest:letm...@ftp.vxl.net/../Utilities/BIOS/TC23YY/
 
  Since I don’t have any working rom so I am hoping to use the file from
  this
  board
 
  http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl
 
  Because they are from the same vendor and used the same chipset. I
  understand it may not work at all but decide to take the risk.
 
  However, I can’t find any program to flash the bios that can ignore the
  bios
  ID. The vendor provided one can flash the bios but does not have the
  option
  to ignore the unmatched bios ID. Flashrom failed at probing the chipset.
 
  The building Q-Flash tells that it is MX25L4005 which should be
  supported by
  Flashrom. I also tried “internal:laptop=this_is_not_a_laptop” and still
  no
  success.

 It's very good that you found that programmer parameter. However, the
 Gigabyte product picture shows that this (non-VXL) board uses LPC
 flash instead of SPI.

 What we're interested in is what flashrom's output looks like when
 there is - your words - no success. Does its output end with many
 times hexadecimal value:S?

 
  So I am not sure what else I should try to make Flashrom work.
 
  Any suggestions?
 
  Thanks,
 
 
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Re: [flashrom] About flashing mx25l4005 on Itona TC2331

2013-05-14 Thread Idwer Vollering

2013/5/14 Bin X z2...@outlook.com:
 I apologize if it does not make sense at all since this is my first attempt
 to flash a bios with unmatched bios ID.

 I was trying to flash bios on a Itona TC2331 to get rid of the limitation
 they put on of any IDE HDD and USB HDD can’t be larger than 64mb.

coreboot can do that, but you have to spend 'some' time on adding
support for your particular mainboard.

See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp
(Chipset VIA CN700 chipset with VIA VT8237R Plus) and
http://www.coreboot.org/Supported_Chipsets_and_Devices


 The current bios rom, flash program and documentation can be found here:

 ftp://ftpguest:letm...@ftp.vxl.net/../Utilities/BIOS/TC23YY/

 Since I don’t have any working rom so I am hoping to use the file from this
 board

 http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl

 Because they are from the same vendor and used the same chipset. I
 understand it may not work at all but decide to take the risk.

 However, I can’t find any program to flash the bios that can ignore the bios
 ID. The vendor provided one can flash the bios but does not have the option
 to ignore the unmatched bios ID. Flashrom failed at probing the chipset.

 The building Q-Flash tells that it is MX25L4005 which should be supported by
 Flashrom.   I also tried “internal:laptop=this_is_not_a_laptop” and still no
 success.

It's very good that you found that programmer parameter. However, the
Gigabyte product picture shows that this (non-VXL) board uses LPC
flash instead of SPI.

What we're interested in is what flashrom's output looks like when
there is - your words - no success. Does its output end with many
times hexadecimal value:S?


 So I am not sure what else I should try to make Flashrom work.

 Any suggestions?

 Thanks,


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Re: [flashrom] [PATCH 3/3] udelay.c: usleep() not found in MinGW, used Sleep()

2013-04-02 Thread Idwer Vollering

2013/4/2 Stefan Tauner stefan.tau...@student.tuwien.ac.at

 On Mon, 1 Apr 2013 19:08:30 +0400
 Maksim Kuleshov m...@ucs.ru wrote:

  From 62ffe98744aba140e5959635abb46c32a47887d2 Mon Sep 17 00:00:00 2001
  From: Maksim Kuleshov m...@mail.ru
  Date: Mon, 1 Apr 2013 19:03:43 +0400
  Subject: [PATCH 3/3] udelay.c: usleep() not found in MinGW, used Sleep()
 
  Signed-off-by: Maksim Kuleshov m...@mail.ru

 I don't think that we ever had a problem with that. (Please correct
 me... Idwer?). What version of MinGW are you using? What's your make
 command and what does it print as error?

The gcc I have installed is i486-mingw32-gcc:
https://www.archlinux.org/packages/community/i686/mingw32-gcc/
My local Makefile changes include libusb-win32-bin-1.2.4.0 and
libftdi_0.20git_win32

However, no usleep() problems here:
flashrom.c: In function 'read_buf_from_file':
flashrom.c:1170:3: error: unknown conversion type character 'j' in
format [-Werror=format]
flashrom.c:1170:3: error: format '%ld' expects argument of type 'long
int', but argument 3 has type 'long long int' [-Werror=format]
flashrom.c:1170:3: error: too many arguments for format
[-Werror=format-extra-args]


 --
 Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)

2013-03-28 Thread Idwer Vollering

2013/3/28 Racine, Michel michel.rac...@hp.com:
 Hello,

 I attached imc.c. The compiler complained with:

 imc.c: In function ‘mbox_wait_ack’:
 imc.c:107:2: error: implicit declaration of function ‘msg_pwarn’ 
 [-Werror=implicit-function-declaration]
 cc1: all warnings being treated as errors
 make: *** [imc.o] Error 1

 Thanks,
 Michel.

Did you delete imc.bin before applying Rudolf's follow-up patch?

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Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)

2013-03-28 Thread Idwer Vollering

2013/3/28 Idwer Vollering vid...@gmail.com:
 2013/3/28 Racine, Michel michel.rac...@hp.com:
 Hello,

 I attached imc.c. The compiler complained with:

 imc.c: In function ‘mbox_wait_ack’:
 imc.c:107:2: error: implicit declaration of function ‘msg_pwarn’ 
 [-Werror=implicit-function-declaration]
 cc1: all warnings being treated as errors
 make: *** [imc.o] Error 1

 Thanks,
 Michel.

 Did you delete imc.bin before applying Rudolf's follow-up patch?

That should have been imc.c

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Re: [flashrom] FAILED: GENE 5315 Rev.B

2013-03-25 Thread Idwer Vollering

2013/3/25 sergey serg99...@mail.ru:


 I send you URL of upload.

Next time, hit reply to all as well, so your reply ends up at all
recipients instead of just me. Thanks.

  AwardBios: http://paste.flashrom.org/view.php?id=1562 .

 Coreboot: http://paste.flashrom.org/view.php?id=1563.

  Programming flash chip ended of success after start modprobe msr.  Thank
 you for the support.



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Re: [flashrom] Successful firmware update: MX25L1605

2013-03-23 Thread Idwer Vollering

2013/3/23 Jerome Leclanche adys...@gmail.com:
 I noticed during the upgrade flashrom was asking me to forward you a verbose
 log; I comply :)

Look closer: it hasn't written or erased ;)

Found Macronix flash chip MX25L1605 (2048 kB, SPI).
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0...
0x00-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S,
0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S,
0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S,
0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S,
0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S,
0x00f000-0x00:S, 0x01-0x010fff:S, 0x011000-0x011fff:S,
0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S,
0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S,
0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S,
0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S,
0x01e000-0x01efff:S, 0x01f000-0x01:S, 0x02-0x020fff:S,
0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S,
0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S,
0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S,
0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S,
0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02:S,
0x03-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S,
0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S,
0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S,
0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S,
0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S,
0x03f000-0x03:S, 0x04-0x040fff:S, 0x041000-0x041fff:S,
0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S,
0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S,
0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S,
0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S,
0x04e000-0x04efff:S, 0x04f000-0x04:S, 0x05-0x050fff:S,
0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S,
0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S,
0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S,
0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S,
0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05:S,
0x06-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S,
0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S,
0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S,
0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S,
0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S,
0x06f000-0x06:S, 0x07-0x070fff:S, 0x071000-0x071fff:S,
0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S,
0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S,
0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S,
0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S,
0x07e000-0x07efff:S, 0x07f000-0x07:S, 0x08-0x080fff:S,
0x081000-0x081fff:S, 0x082000-0x082fff:S, 0x083000-0x083fff:S,
0x084000-0x084fff:S, 0x085000-0x085fff:S, 0x086000-0x086fff:S,
0x087000-0x087fff:S, 0x088000-0x088fff:S, 0x089000-0x089fff:S,
0x08a000-0x08afff:S, 0x08b000-0x08bfff:S, 0x08c000-0x08cfff:S,
0x08d000-0x08dfff:S, 0x08e000-0x08efff:S, 0x08f000-0x08:S,
0x09-0x090fff:S, 0x091000-0x091fff:S, 0x092000-0x092fff:S,
0x093000-0x093fff:S, 0x094000-0x094fff:S, 0x095000-0x095fff:S,
0x096000-0x096fff:S, 0x097000-0x097fff:S, 0x098000-0x098fff:S,
0x099000-0x099fff:S, 0x09a000-0x09afff:S, 0x09b000-0x09bfff:S,
0x09c000-0x09cfff:S, 0x09d000-0x09dfff:S, 0x09e000-0x09efff:S,
0x09f000-0x09:S, 0x0a-0x0a0fff:S, 0x0a1000-0x0a1fff:S,
0x0a2000-0x0a2fff:S, 0x0a3000-0x0a3fff:S, 0x0a4000-0x0a4fff:S,
0x0a5000-0x0a5fff:S, 0x0a6000-0x0a6fff:S, 0x0a7000-0x0a7fff:S,
0x0a8000-0x0a8fff:S, 0x0a9000-0x0a9fff:S, 0x0aa000-0x0aafff:S,
0x0ab000-0x0abfff:S, 0x0ac000-0x0acfff:S, 0x0ad000-0x0adfff:S,
0x0ae000-0x0aefff:S, 0x0af000-0x0a:S, 0x0b-0x0b0fff:S,
0x0b1000-0x0b1fff:S, 0x0b2000-0x0b2fff:S, 0x0b3000-0x0b3fff:S,
0x0b4000-0x0b4fff:S, 0x0b5000-0x0b5fff:S, 0x0b6000-0x0b6fff:S,
0x0b7000-0x0b7fff:S, 0x0b8000-0x0b8fff:S, 0x0b9000-0x0b9fff:S,
0x0ba000-0x0bafff:S, 0x0bb000-0x0bbfff:S, 0x0bc000-0x0bcfff:S,
0x0bd000-0x0bdfff:S, 0x0be000-0x0befff:S, 0x0bf000-0x0b:S,
0x0c-0x0c0fff:S, 0x0c1000-0x0c1fff:S, 0x0c2000-0x0c2fff:S,
0x0c3000-0x0c3fff:S, 0x0c4000-0x0c4fff:S, 0x0c5000-0x0c5fff:S,
0x0c6000-0x0c6fff:S, 0x0c7000-0x0c7fff:S, 0x0c8000-0x0c8fff:S,
0x0c9000-0x0c9fff:S, 0x0ca000-0x0cafff:S, 0x0cb000-0x0cbfff:S,
0x0cc000-0x0ccfff:S, 0x0cd000-0x0cdfff:S, 0x0ce000-0x0cefff:S,
0x0cf000-0x0c:S, 0x0d-0x0d0fff:S, 0x0d1000-0x0d1fff:S,
0x0d2000-0x0d2fff:S, 0x0d3000-0x0d3fff:S, 0x0d4000-0x0d4fff:S,
0x0d5000-0x0d5fff:S, 0x0d6000-0x0d6fff:S, 0x0d7000-0x0d7fff:S,
0x0d8000-0x0d8fff:S, 0x0d9000-0x0d9fff:S,

Re: [flashrom] FAILED: GENE 5315 Rev.B

2013-03-22 Thread Idwer Vollering

2013/3/22 sergey serg99...@mail.ru:
Hello.
I am using your program Flasrom. I have problem with changing of AwardBios
on Coreboot.
I think problem arises because Flashrom don't support this motherboard.

It's obvious that you need a board enable [1] to lift the write/erase
protection, or a spare chip - it's recommended to have a spare chip
when replacing $vendorbios with coreboot.
Can you read the AwardBios to a file, upload the file to
http://paste.flashrom.org/ and reply with the resulting URL?

From the product picture [2] can be deduced that the flash chip is socketed.
ebay link to an empty, spare, SST49LF008A:
http://www.ebay.nl/itm/SST-49LF008A-33-4C-NHE-Blank-/271165788511?pt=UK_WSJL_Wholesale_GLhash=item3f22bd915f

[1] http://flashrom.org/Board_Enable
[2] http://www.tri-m.com/products/aaeon/gene5315.html

But when I load in flash chip data, which were previously saved (AwardBios),
Flashrom has success.
This problem have decision?
Below result of works Flashrom.

For coreboot.
==

k2000@k2000-desktop:~$ sudo flashrom -p internal:boardmismatch=force -w
/home/k2000/coreboot/build/coreboot.rom
[sudo] password for k2000:
flashrom v0.9.6.1-r1564 on Linux 2.6.32-38-generic (i586)
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found chipset AMD CS5536. Enabling flash write... Error while opening
/dev/cpu/0/msr: No such file or directory
Did you run 'modprobe msr'?

Did you run 'modprobe msr'?

FAILED!
WARNING: unexpected second chipset match: AMD CS5536
ignoring, please report lspci and board URL to flashrom@flashrom.org
with 'CHIPSET: your board name' in the subject line.

Run 'lspci -nnvvvxxx' (as root) and attach the output.

Found SST flash chip SST49LF008A (1024 kB, FWH) at physical address
0xfff0.
Note: If the following flash access fails, try -p
internal:mainboard=vendor:mainboard.
Reading old flash chip contents... done.
Erasing and writing flash chip... ERASE FAILED at 0x000ed000! Expected=0xff,
Read=0x00, failed byte count from 0x000ed000-0x000edfff: 0xeb1
ERASE FAILED!
Reading current flash chip contents... done. ERASE FAILED at 0x000ed000!
Expected=0xff, Read=0x00, failed byte count from 0x000e-0x000e:
0x2686
ERASE FAILED!
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Your flash chip is in an unknown state.
Get help on IRC at chat.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org with the subject FAILED: your board name!
---
DO NOT REBOOT OR POWEROFF!
k2000@k2000-desktop:~$
k2000@k2000-desktop:~$ sudo flashrom -p internal:boardmismatch=force -w
/home/k2000/coreboot/build/coreboot.rom
[sudo] password for k2000:
flashrom v0.9.6.1-r1564 on Linux 2.6.32-38-generic (i586)
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found chipset AMD CS5536. Enabling flash write... Error while opening
/dev/cpu/0/msr: No such file or directory
Did you run 'modprobe msr'?
FAILED!
WARNING: unexpected second chipset match: AMD CS5536
ignoring, please report lspci and board URL to flashrom@flashrom.org
with 'CHIPSET: your board name' in the subject line.
Found SST flash chip SST49LF008A (1024 kB, FWH) at physical address
0xfff0.
Note: If the following flash access fails, try -p
internal:mainboard=vendor:mainboard.
Reading old flash chip contents... done.
Erasing and writing flash chip... ERASE FAILED at 0x000ed000! Expected=0xff,
Read=0x00, failed byte count from 0x000ed000-0x000edfff: 0xeb1
ERASE FAILED!
Reading current flash chip contents... done. ERASE FAILED at 0x000ed000!
Expected=0xff, Read=0x00, failed byte count from 0x000e-0x000e:
0x2686
ERASE FAILED!
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or
flash chip.
Please report this on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom@flashrom.org!
---
You may now reboot or simply leave the machine running.
k2000@k2000-desktop:~$

For AwardBios.
==

k2000@k2000-desktop:~$ sudo flashrom -p internal:boardmismath=force -w
/home/k2000/m1
flashrom v0.9.6.1-r1564 on Linux 2.6.32-38-generic (i586)
flashrom is free software, get the source code at http://www.flashrom.org

Re: [flashrom] Hello ! ERASE FAILED ASUS P5VD2-MX SE

2013-03-13 Thread Idwer Vollering

2013/3/13 Rémi charest remichar...@gmail.com:
   Hello it seems my motherboard isn't really supported... Can you add
 support for my board please ?

Certainly.. run and attach the output of 'lspci -nnvvvxxx' (as root).
Beware that writing, when a board enable is applied, trashes the LOM
MAC address: http://www.flashrom.org/pipermail/flashrom/2012-March/009017.html

 I'm wiLling to help if i can (linux noob here).

 Thanks !

 I DID: flashrom -p internal -w P5V0701.ROM
 ON :   flashrom v0.9.6.1-r1564 on Linux 3.7.10-1-ARCH (i686)

 TERMINAL SAID:
 Calibrating delay loop... OK.
 Found chipset VIA VT8237A. Enabling flash write... OK.
 Found SST flash chip SST49LF040B (512 kB, LPC) at physical address
 0xfff8.
 Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
 Reading old flash chip contents... done.
 Erasing and writing flash chip... ERASE FAILED at 0x00014000! Expected=0xff,
 Read=0x17, failed byte count from 0x00014000-0x00014fff: 0xfe7
 ERASE FAILED!
 Reading current flash chip contents... done. ERASE FAILED at 0x0001!
 Expected=0xff, Read=0x17, failed byte count from 0x0001-0x0001:
 0xfee5
 ERASE FAILED!
 FAILED!
 Uh oh. Erase/write failed. Checking if anything changed.
 Good. It seems nothing was changed.
 Writing to the flash chip apparently didn't do anything.
 This means we have to add special support for your board, programmer or
 flash chip.
 Please report this on IRC at irc.freenode.net (channel #flashrom) or
 mail flashrom@flashrom.org!


 MY MOTHERBOARD:
  ASUS P5VD2-MX SE
 version: Rev 1.xx
 BIOS American Megatrends Inc.
 version: 0602

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Re: [flashrom] flashrom first use....

2013-02-26 Thread Idwer Vollering

2013/2/26 Francisco Otero Martínez de Al girot...@yahoo.es:
 I didn't flash nothing yet.
 Please advise me if it is safe to load coreboot on this motherboard.

Quoting the logfile: Found chipset NVIDIA MCP61
MCP61 is not in this list:
http://www.coreboot.org/Supported_Chipsets_and_Devices so the answer
is no.

 Thank you.
 Francisco Otero

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Re: [flashrom] a serious problem to solve

2013-02-10 Thread Idwer Vollering

2013/2/10 Henry Blanco Lores hblanco2...@gmail.com:
 Hi Idwer, do you finally have any idea if the problem could be solved?
 Henry

Pleasse read, and reply to, the mailinglist for questions, don't reply
to me or others without adding flashrom@flashrom.org to To: or Cc:.
Thanks :)

http://www.coreboot.org/pipermail/flashrom/2013-February/thread.html#10519

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Re: [flashrom] a serious problem to solve

2013-02-08 Thread Idwer Vollering

2013/2/8 Henry Blanco Lores hblanco2...@gmail.com:
 Hello guys, I have subscribed to this mailing list looking for some help
 about the use of the flashrom tool.
 The problem is this:

 A friend of mine who has just started using Linux, was testing some tools
 and not reading carefully their corresponding manuals, he executed this
 command: flashrom -r

 and this seems to have erased the BIOS of his PC. This is my guess because
 he just told me by phone that not even the video signal was working. His
 motherboard is an ASUS P5GC. Is it possible to recover the BIOS back to the
 previous state??

The above command, 'flashrom -r', will not erase a flash chip. Have
your friend either power cycle his machine or remove the mainboard
battery (CMOS reset) with mains disconnected.

Given the fact that the parameter '-p internal' was not used, he was
using an old version of flashrom, version 0.9.3 or older.


 Please, I will be looking forward for your comments.
 Thanks in advance.

 H.

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Re: [flashrom] 2009 era -L output

2013-01-18 Thread Idwer Vollering

2013/1/15 Robert S. Done, Ph.D. rd...@cox.net:
 Hi,



 Short version: I am trying to reset/remove Computrace in a Lenovo T500
 laptop. If you have a solution, please share.

It's easy to find out that the CompuTrace module (optionrom) can be
permanently disabled:

https://www.google.nl/search?q=t500+remove+computrace

http://forums.lenovo.com/t5/T400-T500-and-newer-T-series/BIOS-option-to-quot-permanently-disable-quot-Computrace/td-p/104500

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Re: [flashrom] Intel 82802AB report

2013-01-11 Thread Idwer Vollering

2013/1/11 Pavel Shvagirev pavel.shvagi...@gmail.com:
 Hello

 Here's a listing showing that this chip is OK:

Thanks for the info, though we are more interested in the name of the
mainboard that this flash chip is on.
The chip itself is known to fully work:
http://flashrom.org/Supported_hardware#Supported_chips

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Re: [flashrom] [PATCH] Introduce msg_*warn.

2013-01-04 Thread Idwer Vollering

: Failed to enable flash write on 
 \%s\\n, name);
 +   msg_pwarn(\nWarning: Failed to enable flash write on 
 \%s\\n, name);
 return -1;
 }

 @@ -1516,7 +1516,7 @@ int chipset_flash_enable(void)
 if (!dev)
 continue;
 if (ret != -2) {
 -   msg_pinfo(WARNING: unexpected second chipset match: 
 +   msg_pwarn(Warning: unexpected second chipset match: 
 \%s %s\\n
   ignoring, please report lspci and board 
 URL 
 to flashrom@flashrom.org\n
 diff --git a/cli_output.c b/cli_output.c
 index 57a0a05..54b09a6 100644
 --- a/cli_output.c
 +++ b/cli_output.c
 @@ -74,16 +74,15 @@ int print(enum msglevel level, const char *fmt, ...)
 int ret = 0;
 FILE *output_type = stdout;

 -   if (level == MSG_ERROR)
 +   if (level  MSG_INFO)
 output_type = stderr;

 if (level = verbose_screen) {
 va_start(ap, fmt);
 ret = vfprintf(output_type, fmt, ap);
 va_end(ap);
 -   /* msg_*spew usually happens inside chip accessors in possibly
 -* time-critical operations. Don't slow them down by flushing.
 -*/
 +   /* msg_*spew often happens inside chip accessors in possibly
 +* time-critical operations. Don't slow them down by 
 flushing. */
 if (level != MSG_SPEW)
 fflush(output_type);
 }
 diff --git a/dmi.c b/dmi.c
 index a6e2146..5e293c7 100644
 --- a/dmi.c
 +++ b/dmi.c
 @@ -105,7 +105,7 @@ static char *get_dmi_string(const char *string_name)
  %s -s %s, dmidecode_command, string_name);
 dmidecode_pipe = popen(commandline, r);
 if (!dmidecode_pipe) {
 -   msg_perr(DMI pipe open error\n);
 +   msg_perr(Opening DMI pipe failed!\n);
 return NULL;
 }

 @@ -127,13 +127,11 @@ static char *get_dmi_string(const char *string_name)
 }
 } while (answerbuf[0] == '#');

 -   /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent
 -  deadlock on pclose. */
 +   /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent deadlock 
 on pclose. */

Replace 'toss' with 'discard' (as you are going to do), then this is
Acked-by: Idwer Vollering vid...@gmail.com

 while (!feof(dmidecode_pipe))
 getc(dmidecode_pipe);
 if (pclose(dmidecode_pipe) != 0) {
 -   msg_pinfo(dmidecode execution unsuccessful - continuing 
 - without DMI info\n);
 +   msg_pwarn(dmidecode execution unsuccessful - continuing 
 without DMI info\n);
 return NULL;
 }

 @@ -144,7 +142,7 @@ static char *get_dmi_string(const char *string_name)

 result = strdup(answerbuf);
 if (!result)
 -   msg_perr(WARNING: Out of memory - DMI support fails);
 +   msg_pwarn(Warning: Out of memory - DMI support fails);

 return result;
  }
 diff --git a/flash.h b/flash.h
 index 3149b4f..a479286 100644
 --- a/flash.h
 +++ b/flash.h
 @@ -271,16 +271,20 @@ void start_logging(void);
  #endif
  enum msglevel {
 MSG_ERROR   = 0,
 -   MSG_INFO= 1,
 -   MSG_DEBUG   = 2,
 -   MSG_DEBUG2  = 3,
 -   MSG_SPEW= 4,
 +   MSG_WARN= 1,
 +   MSG_INFO= 2,
 +   MSG_DEBUG   = 3,
 +   MSG_DEBUG2  = 4,
 +   MSG_SPEW= 5,
  };
  /* Let gcc and clang check for correct printf-style format strings. */
  int print(enum msglevel level, const char *fmt, ...) 
 __attribute__((format(printf, 2, 3)));
  #define msg_gerr(...)  print(MSG_ERROR, __VA_ARGS__)   /* general errors */
  #define msg_perr(...)  print(MSG_ERROR, __VA_ARGS__)   /* programmer errors 
 */
  #define msg_cerr(...)  print(MSG_ERROR, __VA_ARGS__)   /* chip errors */
 +#define msg_gwarn(...) print(MSG_WARN, __VA_ARGS__)/* general warnings */
 +#define msg_pwarn(...) print(MSG_WARN, __VA_ARGS__)/* programmer 
 warnings */
 +#define msg_cwarn(...) print(MSG_WARN, __VA_ARGS__)/* chip warnings */
  #define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__)/* general info */
  #define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__)/* programmer info */
  #define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__)/* chip info */
 diff --git a/ichspi.c b/ichspi.c
 index fadfe62..2a3d58a 100644
 --- a/ichspi.c
 +++ b/ichspi.c
 @@ -1455,7 +1455,7 @@ static int ich9_handle_frap(uint32_t frap, int i)
 return 0;
 }

 -   msg_pinfo(FREG%i: WARNING: %s region (0x%08x-0x%08x) is %s.\n, i,
 +   msg_pwarn(FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n, i,
   region_names[i], base, (limit | 0x0fff

Re: [flashrom] 2theMax RAID 100 (HPT370)

2012-12-27 Thread Idwer Vollering

2012/12/27 Roy roy...@gmail.com:
 Hi all,

 I got a 2theMax RAID 100 card with SST MPF 39SF512 70-4C-NH 64KB ROm on PCB,
 flashrom segfaults at the end.

Interesting. Can you run flashrom from GDB?

'gdb --args ./flashrom -p atahpt -V'
(gdb) start
(wait a little)
(gdb) bt


 lspci:
 00:0f.0 Mass storage controller [0180]: HighPoint Technologies, Inc.
 HPT366/368/370/370A/372/372N [1103:0004] (rev 03)
 Subsystem: HighPoint Technologies, Inc. HPT370 UDMA100 [1103:0005]
 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
 Stepping- SERR- FastB2B- DisINTx-
 Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium TAbort-
 TAbort- MAbort- SERR- PERR- INTx-
 Latency: 120 (2000ns min, 2000ns max), Cache Line Size: 32 bytes
 Interrupt: pin A routed to IRQ 18
 Region 0: I/O ports at a800 [size=8]
 Region 1: I/O ports at a400 [size=4]
 Region 2: I/O ports at a000 [size=8]
 Region 3: I/O ports at 9800 [size=4]
 Region 4: I/O ports at 9400 [size=256]
 [virtual] Expansion ROM at 2002 [disabled] [size=128K]
 Kernel driver in use: HPT366_IDE

Does unloading/not loading hpt366_ide at boot time improve things?

 00: 03 11 04 00 05 00 00 02 03 00 80 01 08 78 00 00
 10: 01 a8 00 00 01 a4 00 00 01 a0 00 00 01 98 00 00
 20: 01 94 00 00 00 00 00 00 00 00 00 00 03 11 05 00
 30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 08 08
 40: a7 4e 81 06 a7 4e 81 06 a7 4e 81 06 a7 4e 81 06
 50: 05 01 00 00 05 01 00 00 1b 00 00 23 24 00 26 00
 60: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00
 70: 00 00 00 00 00 00 00 00 94 00 00 00 00 00 00 00
 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 flashrom v0.9.6.1-r1564 on Linux 2.6.32-5-686 (i686)
 flashrom is free software, get the source code at http://www.flashrom.org

 flashrom was built with libpci 3.1.7, GCC 4.4.5, little endian

On which operating system is it built, segfaulting?

 Command line (3 args): ./flashrom -p atahpt -V
 Calibrating delay loop... OS timer resolution is 1 usecs, 230M loops per
 second, delay more than 10% too short (got 76% of expected delay),
 recalculating... 291M loops per second, 10 myus = 10 us, 100 myus = 97 us,
 1000 myus = 962 us, 1 myus = 9635 us, 4 myus = 5 us, OK.
 Initializing atahpt programmer
 Found Highpoint HPT366/368/370/370A/372/372N (1103:0004, BDF 00:0f.0).
 ===
 This PCI device is UNTESTED. Please report the 'flashrom -p ' output
 to flashrom@flashrom.org if it works for you. Please add the name of your
 PCI device to the subject. Thank you for your help!
 ===
 Requested BAR is I/O
 The following protocols are supported: Parallel.
 Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0x00, id2
 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0x00, id2
 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x00, id2 0x00,
 id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for AMD Am29LV008BB, 1024 kB:

Re: [flashrom] mail archives down?

2012-12-10 Thread Idwer Vollering

2012/12/10 Bernd Blaauw bbla...@home.nl

 Are the Pipermail mail archives down for some reason?
 Seeing this at flashrom, seabios and coreboot, of which I'm only
 subscribed to the first one (thus reading the other 2 from web archive).

 Getting a 403/Forbidden when clicking the Archives link at:
 http://www.flashrom.org/**mailman/listinfo/flashromhttp://www.flashrom.org/mailman/listinfo/flashrom


Works for me. This however looks wrong:
http://www.flashrom.org/pipermail/flashrom/2012-December/73.html




 Bernd

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Re: [flashrom] BPv3.6 w flashrom

2012-12-05 Thread Idwer Vollering

Please reply to all.

2012/12/5 Nabil nabil.ger...@yahoo.com.au:
 Sorry there's one thing I'm not sure I understand...
 Is it possible to adjust the locations of the wires of the soic clip so they 
 match up with the correct pinouts?
 I just dont get how gnd (pin 10 of bus pirate) can be connected to the soic 
 clip (only 8 cables which connect to pins 1-8)
 there's something I'm missing here i think, could you explain to me how to 
 use an soic clip in detail, sorry for the trouble, much obliged. Nabs

Which soic8 clip do you have? I have a Pomona 5250; it is possible to
adjust the wire locations (pinouts) if you have the probe cable (that
fits on the open end of the wires - the other end is a box header that
connects to the buspirate):
http://dangerousprototypes.com/2011/08/03/new-bus-pirate-probe-cable/


 Idwer Vollering vid...@gmail.com wrote:

2012/12/5 Nabs ch1201...@yahoo.com.au:
 Hi, sorry for the trouble. I'm running bus piratev3.6, bootloaderv4.4,
 firmwarev6.1 on flashrom-0.9.6.1, i plan to run the BP at 1M.

 When i run the command flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -Vr
 oldbios.bin
 I get:
 
 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI) on
 buspirate_spi.
 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0x0,
 id2 0x0
 Found Generic flash chip unknown SPI chip (RDID) (0 kB, SPI).
 ===
 This flash part has status NOT WORKING for operations: PROBE READ ERASE
 WRITE
  etc...


 I think i have the wiring wrong which is why i get that error, i wonder if
 you could help me as its my first time?
 I'm trying to use In-circuit programming with a soldered bios chip using an
 'SOIC 8 clip' and it has 8 wires. But the bus pirate has 10 pins.

 From another thread, these are the connections i need:
 Bus Pirate MISO (Pin 1) - SPI Device DO (Wire/Pin 2)
 Bus Pirate CS (Pin 2) - SPI Device CS (Wire/Pin 1)
 Bus Pirate MOSI (Pin 3) - SPI Device DI (Wire/Pin 5)
 Bus Pirate CLK (Pin 4) - SPI Device CLK (Wire/Pin 6)
 Bus Pirate GND (Pin 10)  SPI Device GND (Wire/Pin 4)

 It appears to me that GND is pin 10 and that the wires of the SOIC8 clip
 only contact pins 1-8, so how can this work?

 Also, could i just check the layout of the pins on the bus pirate if i'm
 reading it correctly on BPv3.6:
 10  9
 87
 65
 43
 21

 Corresponding to:
 GND  3V3
 +5VADC
 VPU   AUX
 CLKMOSI
 CS MISO

Forget the existence of +5V, VPU, ADC and AUX for now (
http://dangerousprototypes.com/docs/Bus_Pirate_I/O_Pin_Descriptions ),
connect the clip to the buspirate so that the clip passes the
buspirate pins like mentioned in this post:
http://www.coreboot.org/pipermail/flashrom/2012-November/010178.html

This works for me, with a MX25L1605A soic8 chip:

CS# (CS)  [1  chip  8]VCC
(bridge with buspirate pin 3+7)
SO (MISO)[2  chip  7]HOLD# (+3V3)
WP# (bridge with buspirate pin 7+8)[3  chip  6]SCLK (CLK)
GND (GND)   [4  chip  5]SI (MOSI)


 Or are the pin numbers read in the opposite direction?
 ie
 9  10
 7  8
 5  6
 3  4
 1  2

 Here's an image of my bus pirate if it helps:
 http://dangerousprototypes.com/wp-content/media/2012/11/Bus-Pirate-v3.6interface_01-W600.jpg

 Your help is much appreciated and i appreciate your patience, Nabs.

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Re: [flashrom] EC A928 failed flash. part 2.1

2012-12-01 Thread Idwer Vollering

2012/12/1 simon simon.ri...@gmail.com:
 Den 01-12-2012 02:13, Stefan Tauner skrev:

 Hi Stefan

 Patch added and seems to work fine.

Can you re-send the patch, which we'll happily integrate, this time
not as a .vcf?

Idwer

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Re: [flashrom] MX25L1605DM2I-12G with Buspirate

2012-11-29 Thread Idwer Vollering

2012/11/29 Daniel . phl3...@googlemail.com:
 Hi everyone,

 I am absolute beginner but I need to read and write the above mentioned
 serial Flash memory.

 This is a BIOS chip and had a bad flash. Now it is unsoldered from
 mainboard.

How do you connect the buspirate to the chip and what is the chip's
form factor (e.g. soic8)? The datasheet mentions SOP/WSON/PDIP.

 I want read it out and reflash a new BIOS file.

 Therefore I really need help how to connect the chip pins with the buspirate
 pins in a correct way.

 This is how pins are shown in the data sheet of Macronix MX25L1605DM2I-12G

 CS#1   8   VCC
 SO/SIO127   HOLD#
 WP#ACC   36SCLK
 GND   45SI/SIO0

http://dangerousprototypes.com/docs/Bus_Pirate_I/O_Pin_Descriptions

This is how I connect my buspirate to a MX25L1605A soic8 chip:

CS# (CS)[1  8]  VCC 
(bridge with buspirate pin 3+7)
SO (MISO)   [2  7]  HOLD # (+3V3)
WP# (bridge with buspirate pin 7+8) [3  6]  SCLK (CLK)
GND (GND)   [4  5]  SI (MOSI)


 I am using Bus Pirate v3.5 with FW v6.2-beta1 r1981 BL v4.4 and flashrom
 v0.9.6.1-r1624 on Windows.

HiZi
Bus Pirate v3.a
Firmware v6.2-beta1 r1981  Bootloader v4.4


 Would I have to setup the buspirate in a terminal before using flashrom? I
 mean SPI mode and so on? If yes could someone help me with this settings
 too?

It's not necessary to change modes (no need to change from HiZ to SPI).


 Thanks!

 Best regards,
 Daniel


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Re: [flashrom] [PATCH] Break endless loop in serialport_write().

2012-11-29 Thread Idwer Vollering

2012/11/29 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 serialport_write could loop endlessly when used with a seemingly valid port
 that does always return 0 on writes instead of an error.
 Give up after about 125 ms i.e. 250 tries with a period of 500 us.

 Signed-off-by: Stefan Tauner stefan.tau...@student.tuwien.ac.at

Note that this introduces a minor execution slowdown when used with -o/--output.

Acked-by: Idwer Vollering vid...@gmail.com

 ---
  serial.c |   14 +++---
  1 file changed, 11 insertions(+), 3 deletions(-)

 diff --git a/serial.c b/serial.c
 index 7e47dcc..794763e 100644
 --- a/serial.c
 +++ b/serial.c
 @@ -262,6 +262,7 @@ int serialport_write(unsigned char *buf, unsigned int 
 writecnt)
  #else
 ssize_t tmp = 0;
  #endif
 +   unsigned int empty_writes = 250; /* results in a ca. 125ms timeout */

 while (writecnt  0) {
  #ifdef _WIN32
 @@ -273,9 +274,16 @@ int serialport_write(unsigned char *buf, unsigned int 
 writecnt)
 msg_perr(Serial port write error!\n);
 return 1;
 }
 -   if (!tmp)
 -   msg_pdbg(Empty write\n);
 -   writecnt -= tmp;
 +   if (!tmp) {
 +   msg_pdbg2(Empty write\n);
 +   empty_writes--;
 +   programmer_delay(500);
 +   if (empty_writes == 0) {
 +   msg_perr(Serial port seems dead!\n);
 +   return 1;
 +   }
 +   }
 +   writecnt -= tmp;
 buf += tmp;
 }

 --
 Kind regards, Stefan Tauner


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Re: [flashrom] MX25L1605DM2I-12G with Buspirate

2012-11-29 Thread Idwer Vollering

2012/11/29 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 On Thu, 29 Nov 2012 23:29:28 +0100
 Daniel . phl3...@googlemail.com wrote:

 Maybe just a last question. Is it possible to flash a .wph BIOS-file with
 flashrom? Furthermore I have read something about that the BIOS-file has to
 be the same size like the chip. This is not the case for me. Can someone
 help?

 flashrom does not care about the contents of the files you fed it at
 all, hence they must be prepared first. usually this is done by cutting
 out headers or footers. in the case of wph it is likely that you can
 cut everything away that is larger than your flash chip AFAIK.

If you took the chip from a laptop, with a soldering iron, removing
the trailer with 'dd' will likely work.
To split off the first megabyte, run: dd if=romfile
of=trimmed_file.bin bs=1024k count=1
See http://flashrom.org/Laptop_enable

 --
 Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Modded Bios

2012-11-04 Thread Idwer Vollering

2012/11/4 Michael Card michaelc...@shaw.ca:
 Hi there

 I am trying to follow the instructions to save my Bios to disk using 
 DPCIManager…

You are posting to the flashrom mailing list :)

It never saves a file?

Why not? What does flashrom tell you when you run it like 'flashrom -r
bios_saved_with_flashrom.biosfile -p internal -VVV' ?

I have an Asrock H77 Pro4-M Motherboard.  Could you help me save/edit/flash a 
modded bios to this board?

Saving and/or flashing, yes - editing: no.

Reading/writing can be a bit troublesome or even impossible when
running flashrom from userland.
See http://flashrom.org/ISP and
http://tracker.coreboot.org/trac/flashrom/browser/trunk/Documentation/mysteries_intel.txt


 Thx

 Michael Card
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Re: [flashrom] laptop with no BIOS? or BIOS reflash pain

2012-10-30 Thread Idwer Vollering

I've HP compaq 6715s laptop.
It's all right with 10-current.
I've got wireless and at one point
I even managed to get flash working.

My problem is with BIOS.
Apparently it's wrong and John Baldwin
provided me with a pci.c patch to get
it to boot.

There is an updated BIOS version, but
so far I failed to get it installed.
HP only provide MS and freedos executables.
I tried BartPE - doesn't work.
I tried plugging in a MS disk - doesn't work.
The only think I haven't tried is getting
a spare disk, installing freedos on it
and then running the freedos executable
from USB - what a fucking pain...

For proper hardware (servers) HP provide
images which are executed from management
console, but not for laptops.
I guess the idea that one might
use their laptops for anything other than MS
is so wild, that it never crossed their maid.

Anyway, I think I've heard there are some laptops
with no BIOS, is this true?
Or perhaps there are brands where BIOS
reflash is not such a great pain?
I remember on Compaq Armada the BIOS was
stored on disk and Compaq provided a floppy
image to boot from and reflash BIOS.
That was easy.
Anything like this exist these days?
Are there any EFI laptops?
Any model people would recommend?

Thanks

Anton

Another approach is to use an external SPI programmer:
http://flashrom.org/Supported_programmers
The 'downside' of this is that you need to take your laptop apart.

ODM schematics of your laptop are found here:
http://notebookschematic.com/wp-content/uploads/2010/06/6515b_6715s.png
Downloads for BIOS updates:
http://h2.www2.hp.com/bizsupport/TechSupport/SoftwareIndex.jsp?lang=encc=usprodNameId=3356623prodTypeId=321957prodSeriesId=3368539swLang=13taskId=135swEnvOID=1093#120
and ftp://ftp.hp.com/pub/softpaq/sp55501-56000/sp6.exe

My guess (I am not a HP service technician) is that you need
ROM.CAB/Rom.bin from sp6.exe - you can use 7zip to extract Rom.bin

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Re: [flashrom] NEED help for programing the EEPROM on intel NIC 9400PT

2012-10-16 Thread Idwer Vollering

2012/10/16 zz z enn...@gmail.com:
 Hello flashrom's developers:

 I want to save my ethernet adapter.

 I have an Intel 9400PT nic, the controller is 82572EI which was on your
 supported list, but the PCI ID is not match, mine is 8086-107D, and your
 list show 8086-10B9.And these two NIC is totally identical in hardware, just
 different eeprom contents.

 My problem is I used eeupdate clear the PCI Vendor ID to  by my
 mistake. Now the PCI device id is -107D.

 As the result BIOS  OS can't recognise it at all, even eeupdate itself !
 But some software (like AIDA64 ) can recognise it as a unknown device which
 pci vendor id is .
 So I google that flashrom can help me ,(I have the original eep file.) I
 download it and run it in DOS. I used command flashrom -w 9400pt.eep -p
 -nicintel_spi, then flashrom told me:

 Calibrating delay loop... OK.
 No EEPROM/flash device found.
 Note: flashrom can never write if the flash chip isn't found
 automatically.


 So I need help how to using flashrom to program the eeprom on NIC. And can
 flashrom use SMBUS address to flash?(I know the SMBUS address of this NIC.)

http://blog.vodkamelone.de/archives/146-Unbricking-an-Intel-Pro1000-e1000-network-interface.html



 Thanks a lot.
 yours sincerely


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Re: [flashrom] Foxconn P55mx\H55mx

2012-10-02 Thread Idwer Vollering

2012/10/2 Владислав Быков vladislavb...@gmail.com:
 No problem :3
 Default jumper position (enabled):

  sudo flashrom -p internal -VV
 [sudo] password for vladislavbyk:
 flashrom v0.9.6.1-r1564 on Linux 3.5.4-1-ARCH (i686)
 flashrom is free software, get the source code at http://www.flashrom.org

 flashrom was built with libpci 3.1.10, GCC 4.7.1 20120721 (prerelease),
 little endian
 Command line (3 args): flashrom -p internal -VV
 Calibrating delay loop... OS timer resolution is 1 usecs, 1355M loops per
 second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 1126 us, 1 myus =
 9925 us, 4 myus = 4 us, OK.

 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: To Be Filled By O.E.M.
 DMI string system-product-name: To Be Filled By O.E.M.
 DMI string system-version: To Be Filled By O.E.M.
 DMI string baseboard-manufacturer: Foxconn
 DMI string baseboard-product-name: H55MX-S Series
 DMI string baseboard-version: 1.1
 DMI string chassis-type: Desktop
 Found ITE Super I/O, ID 0x8720 on port 0x2e
 Found chipset Intel H55 with PCI ID 8086:3b06. Enabling flash write...
 0xfff8/0xffb8 FWH IDSEL: 0x0
 0xfff0/0xffb0 FWH IDSEL: 0x0
 0xffe8/0xffa8 FWH IDSEL: 0x1
 0xffe0/0xffa0 FWH IDSEL: 0x1
 0xffd8/0xff98 FWH IDSEL: 0x2
 0xffd0/0xff90 FWH IDSEL: 0x2
 0xffc8/0xff88 FWH IDSEL: 0x3
 0xffc0/0xff80 FWH IDSEL: 0x3
 0xff70/0xff30 FWH IDSEL: 0x4
 0xff60/0xff20 FWH IDSEL: 0x5
 0xff50/0xff10 FWH IDSEL: 0x6
 0xff40/0xff00 FWH IDSEL: 0x7
 0xfff8/0xffb8 FWH decode enabled
 0xfff0/0xffb0 FWH decode enabled
 0xffe8/0xffa8 FWH decode disabled
 0xffe0/0xffa0 FWH decode disabled
 0xffd8/0xff98 FWH decode disabled
 0xffd0/0xff90 FWH decode disabled
 0xffc8/0xff88 FWH decode disabled
 0xffc0/0xff80 FWH decode disabled
 0xff70/0xff30 FWH decode disabled
 0xff60/0xff20 FWH decode disabled
 0xff50/0xff10 FWH decode disabled
 0xff40/0xff00 FWH decode disabled
 Maximum FWH chip size: 0x10 bytes
 BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8
 Root Complex Register Block address = 0xfed1c000
 GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3
 (SPI)
 Top Swap : not enabled
 SPIBAR = 0xfed1c000 + 0x3800
 0x04: 0x6008 (HSFS)
 HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1,
 FLOCKDN=0
 Programming OPCODES...
 program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190
 done
 OPType  Pre-OP
 op[0]: 0x02, write w/  addr, none
 op[1]: 0x03, read  w/  addr, none
 op[2]: 0xd8, write w/  addr, none
 op[3]: 0x05, read  w/o addr, none
 op[4]: 0x90, read  w/  addr, none
 op[5]: 0x01, write w/o addr, none
 op[6]: 0x9f, read  w/o addr, none
 op[7]: 0xc7, write w/o addr, none
 Pre-OP 0: 0x06, Pre-OP 1: 0x50

 0x06: 0x (HSFC)
 HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
 0x08: 0x (FADDR)
 0x50: 0x0a0b (FRAP)
 BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b
 0x54: 0x FREG0: WARNING: Flash Descriptor region
 (0x-0x0fff) is read-only.

 0x58: 0x07ff0700 FREG1: BIOS region (0x0070-0x007f) is read-write.
 0x5C: 0x06ff0001 FREG2: WARNING: Management Engine region
 (0x1000-0x006f) is locked.
 0x60: 0x1fff FREG3: Gigabit Ethernet region is unused.
 0x64: 0x1fff FREG4: Platform Data region is unused.
 0x74: 0x (PR0 is unused)
 0x78: 0x (PR1 is unused)
 0x7C: 0x (PR2 is unused)
 0x80: 0x (PR3 is unused)
 0x84: 0x (PR4 is unused)
 Please send a verbose log to flashrom@flashrom.org if this board is not
 listed on
 http://flashrom.org/Supported_hardware#Supported_mainboards yet.
 Writes have been disabled. You can enforce write support with the
 ich_spi_force programmer option, but it will most likely harm your
 hardware!
 If you force flashrom you will get no support if something breaks.

 0x90: 0x00 (SSFS)
 SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
 0x91: 0xf84200 (SSFC)
 SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0
 0x94: 0x5006 (PREOP)
 0x96: 0x463b (OPTYPE)
 0x98: 0x05d80302 (OPMENU)
 0x9C: 0xc79f0190 (OPMENU+4)
 0xA0: 0x (BBAR)
 0xC4: 0x (LVSCC)
 LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0
 0xC8: 0x2001 (UVSCC)
 UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20, VCL=0
 0xD0: 0x (FPB)

 Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
 === Content Section ===
 FLVALSIG 0x0ff0a55a
 FLMAP0   0x02040102
 FLMAP1   0x10100206
 FLMAP2   0x0020

 --- Details ---
 NR  (Number of Regions): 3
 FRBA(Flash Region Base Address): 0x040
 NC  (Number of Components):  2
 FCBA(Flash Component Base Address):  0x020
 ISL (ICH/PCH Strap Length): 16
 FISBA/FPSBA (Flash ICH/PCH Strap Base Address):

Re: [flashrom] Flashrom problem

2012-09-22 Thread Idwer Vollering

2012/9/22 Jonas Peres jones.st...@gmail.com:
 Sorry, forgot to send report from flashrom
 There he goes.
 Sorry about my inglish.

 Regards
 Jonas Peres

The version of flashrom you have installed (v0.9.1) is really old, we
recommend to use the latest stable release or compile from subversion
code: http://www.flashrom.org/Downloads#Installation_from_source

Furthermore, the output you sent is incomplete (or flashrom aborted/segfaulted).

Idwer

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Re: [flashrom] [coreboot] New laptop: Lenovo ThinkPad X230 tablet, with dumps to go with it

2012-09-15 Thread Idwer Vollering

CC: flashrom@flashrom.org

2012/9/15 Keith Hui buu...@gmail.com:
Hi all,

I'm back. With a new laptop.

I'm now rocking a Lenovo x230 tablet, dual-booting Windows 7 and
Fuduntu, both 64-bit. Knowing the last time I contributed to coreboot
it was the good old 440BX when life was much simpler, it could be a
while before I can get up to speed again, so I'll for now just put
forth the obligatory lspci/superiotool dump to give any interested
parties a heads-up of what support needs to be programmed for.

Another interesting thing is it does UEFI.

Below is output of flashrom 0.9.6.1. I cannot get it to identify the
flash chip. lspci and superiotool dumps are attached.

This thread mentions that it runs QM77:
http://forums.lenovo.com/t5/X-Series-Tablet-ThinkPad-Laptops/X230-Tablet-Chipset/td-p/856103

# /usr/src/flashrom-0.9.6.1/flashrom -V -p internal
flashrom v0.9.6.1-r1564 on Linux 3.4.9-1.fu2012.x86_64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.7, GCC 4.6.3 20120306 (Red Hat
4.6.3-2), little endian
Command line (3 args): /usr/src/flashrom-0.9.6.1/flashrom -V -p internal
Calibrating delay loop... OS timer resolution is 1 usecs, 3243M loops
per second, 10 myus = 10 us, 100 myus = 119 us, 1000 myus = 1026 us,
1 myus = 10097 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: LENOVO
DMI string system-product-name: 3434CTO
DMI string system-version: ThinkPad X230 Tablet
DMI string baseboard-manufacturer: LENOVO
DMI string baseboard-product-name: 3434CTO
DMI string baseboard-version: Not Available
DMI string chassis-type: Notebook
Laptop detected via DMI.
W836xx enter config mode worked or we were already in config mode.
W836xx leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: 00.
Please send the output of flashrom -V to
flashrom@flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.

WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

Also, see the Laptops section in flashrom's man page.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.

Aborting.
Error: Programmer initialization failed.

You'll want to do a little investigation on which external programmer
[1] suits your needs.

[1] http://flashrom.org/Supported_programmers

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Re: [flashrom] [PATCH] Fix flashrom running on boards with coreboot.

2012-09-15 Thread Idwer Vollering

2012/9/15 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 In r1577 we removed the discrimination of coreboot IDs and user-specified
 mainboards. The problem is that the board enable code required to find
 a board enable if either of these model strings were set. Therefore boards
 running coreboot that do not need a board enable failed to execute flashrom
 since then. This patch fixes this by handling coreboot IDs and user-supplied
 IDs differently again.

 Signed-off-by: Stefan Tauner stefan.tau...@student.tuwien.ac.at

Acked-by: Idwer Vollering vid...@gmail.com

 ---
  board_enable.c |   20 +++-
  internal.c |   10 +++---
  programmer.h   |2 +-
  3 files changed, 19 insertions(+), 13 deletions(-)

 diff --git a/board_enable.c b/board_enable.c
 index 2668f10..bdd5ebb 100644
 --- a/board_enable.c
 +++ b/board_enable.c
 @@ -2493,7 +2493,6 @@ static const struct board_match *board_match_name(const 
 char *vendor, const char
 if (partmatch)
 return partmatch;

 -   msg_perr(No suitable board enable found for vendor=\%s\, 
 model=\%s\.\n, vendor, model);
 return NULL;
  }

 @@ -2603,16 +2602,27 @@ void board_handle_before_laptop(void)
 board_handle_phase(P2);
  }

 -int board_flash_enable(const char *vendor, const char *model)
 +int board_flash_enable(const char *vendor, const char *model, const char 
 *cb_vendor, const char *cb_model)

Future plan: pass board_match{} to board_flash_enable() instead?

  {
 const struct board_match *board = NULL;
 int ret = 0;

 -   if (vendor  model) {
 +   if (cb_vendor != NULL  cb_model != NULL) {
 +   board = board_match_name(cb_vendor, cb_model);
 +   if (!board) { /* Failure is an option here, because many cb 
 boards don't require an enable. */
 +   msg_pdbg2(No board enable found matching coreboot 
 IDs vendor=\%s\, model=\%s\.\n,
 + vendor, model);
 +   }
 +   }
 +   if (board == NULL  vendor  model) {
 board = board_match_name(vendor, model);
 -   if (!board) /* if a board was given it has to match, else we 
 abort here. */
 +   if (!board) { /* If a board was given by the user it has to 
 match, else we abort here. */
 +   msg_perr(No suitable board enable found for 
 vendor=\%s\, model=\%s\.\n,
 +vendor, model);
 return 1;
 -   } else {
 +   }
 +   }
 +   if (board == NULL) {
 board = board_match_pci_ids(P3);
 if (!board) /* i.e. there is just no board enable available 
 for this board */
 return 0;
 diff --git a/internal.c b/internal.c
 index 7b6cff2..b4414a5 100644
 --- a/internal.c
 +++ b/internal.c
 @@ -257,12 +257,8 @@ int internal_init(void)
 }

  #if defined(__i386__) || defined(__x86_64__)
 -   if (cb_parse_table(cb_vendor, cb_model) == 0) { /* coreboot IDs 
 valid */
 -   /* If no -p internal:mainboard was given but there are valid 
 coreboot IDs then use those. */
 -   if (board_vendor == NULL || board_model == NULL) {
 -   board_vendor = cb_vendor;
 -   board_model = cb_model;
 -   } else if (strcasecmp(board_vendor, cb_vendor) || 
 strcasecmp(board_model, cb_model)) {
 +   if ((cb_parse_table(cb_vendor, cb_model) == 0)  (board_vendor != 
 NULL)  (board_model != NULL)) {
 +   if (strcasecmp(board_vendor, cb_vendor) || 
 strcasecmp(board_model, cb_model)) {
 msg_pinfo(WARNING: The mainboard IDs set by -p 
 internal:mainboard (%s:%s) do not\n
match the current coreboot IDs of 
 the mainboard (%s:%s).\n,
   board_vendor, board_model, cb_vendor, 
 cb_model);
 @@ -339,7 +335,7 @@ int internal_init(void)
 init_superio_ite();
  #endif

 -   if (board_flash_enable(board_vendor, board_model)) {
 +   if (board_flash_enable(board_vendor, board_model, cb_vendor, 
 cb_model)) {
 msg_perr(Aborting to be safe.\n);
 return 1;
 }
 diff --git a/programmer.h b/programmer.h
 index 51b9c40..dedec67 100644
 --- a/programmer.h
 +++ b/programmer.h
 @@ -256,7 +256,7 @@ void sio_write(uint16_t port, uint8_t reg, uint8_t data);
  void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
  void board_handle_before_superio(void);
  void board_handle_before_laptop(void);
 -int board_flash_enable(const char *vendor, const char *model);
 +int board_flash_enable(const char *vendor, const char *model, const char 
 *cb_vendor, const char *cb_model);

See above.


  /* chipset_enable.c */
  int chipset_flash_enable(void);
 --
 Kind regards, Stefan Tauner


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[flashrom] [patch] atavia

2012-09-02 Thread Idwer Vollering

Add VIA VT6421A LPC programmer driver.

Updated to be applied against HEAD (r1357 -- r1586).

Signed-off-by: Jonathan Kollasch jakll...@kollasch.net


atavia_r1586.patch
Description: Binary data
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Re: [flashrom] [PATCH] Fix compilation with MinGW.

2012-09-01 Thread Idwer Vollering

2012/9/1 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 This was broken since r1557 when we got rid of some exit calls, but returned
 -1 instead which is not a valid HANDLE value.

 Signed-off-by: Stefan Tauner stefan.tau...@student.tuwien.ac.at

Acked-by: Idwer Vollering vid...@gmail.com

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Re: [flashrom] How to reflash ROM file for Persimmon board

2012-08-08 Thread Idwer Vollering

2012/8/7 Tung Hoang tu...@techburgcorp.com:
 Hi all
 I has a Persimmon board and I installed Ubuntu OS on it.
 I build Coreboot with GRUB2  for my board ( output is new ROM file )

Starting grub2 as a payload might or might not work, can you
troubleshoot your machine (= look at coreboot/the payload's console
output) when it doesn't work as expected? Why did you choose grub2
over seabios?

 Now, I intent use flashrom tool to flash new ROM file for my board.
 But I'm not sure my new ROM file is work well or not.
 As i understand, I can backup original ROM file of Persimmon board and using
 flashrom tool to load new ROM file to my board ( flashrom is installed on
 Ubuntu OS run on Persimmon board )
 My question is :
 If my new ROM file is not working, How to reflash original ROM file ( which
 i backup from Persimmon board ) ?
 Can we use flashrom or other tool ?

You certainly want to save the original rom content, maybe store it on
another machine, or get a spare chip to program coreboot.rom to.
If you prefer to use an external programmer for SPI chips I can
recommend the buspirate: http://flashrom.org/Bus_Pirate and compatible
soic8 clips, if the flash is soldered to the board,
http://www.hmcelectronics.com/product/Pomona/5250


 Thanks
 --
 Hoang Tung (Mr)




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Re: [flashrom] IBM SurePOS 700 4800-783 support

2012-07-20 Thread Idwer Vollering

2012/7/20 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 On Mon, 16 Jul 2012 13:57:36 +0200
 Stefan Tauner stefan.tau...@student.tuwien.ac.at wrote:

 Above all we need to work on the support for the VIA chipset (VT8251),
 but IBM won't be able to help us with that. I have no news regarding
 that.

 Hello again,

 i have a patch for you to test. It tries to add support for the VT8251
 by using the code for similar VIA chipsets. We are pretty confident
 that it will work although we could not verify it against a datasheet
 (yet). The Renesas chip might still be a problem, but we hopefully be
 able to take one step forward. Please apply the attached patch to the
 current subversion head

You can find the subversion URI here:
http://www.flashrom.org/Downloads#Installation_from_source
Run 'make' after patching.

 and send us the output of

 flashrom -V -p internal:laptop=this_is_not_a_laptop

 and if that finds a chip also the output of

 flashrom -V -p internal:laptop=this_is_not_a_laptop -r testfile.bin

 Please don't try to write or erase yet!
 --
 Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] (no subject)

2012-07-19 Thread Idwer Vollering

2012/7/19 Riccardo Berto riccardo...@gmail.com:


 ok lol

 thanks for the explanation
 btw I think that with battery on it and connected to AC you can use a
 laptop
 safely (with battery you avoid instant shutdowns)

No, the battery isn't there to prevent unexpected poweroffs.
Read the following two wiki pages, there you'll find out more about
why we strongly discourage running flashrom on laptops/mobile
hardware.

http://flashrom.org/Laptops
http://flashrom.org/Laptop_enable

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Re: [flashrom] [PATCH] Bus Pirate: Speedup and firmware workarounds

2012-07-15 Thread Idwer Vollering

2012/6/13 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net:
 Bus Pirate Firmware v5.5 and newer support a new SPI binary mode. Use it
 if available.
 Bus Pirate Firmware v6.1 and older have broken (too slow) SPI clock
 divisor for any requested speed above 2 MHz. Force a downgrade to 2 MHz
 for affected firmware versions.
 flashrom will recommend to upgrade the Bus Pirate Firmware if it is
 older than v6.2.

 Somewhat tested, code still needs to be cleaned up in a few spots.

Tested with reading/erasing/writing a MX25L1605 on a Thinkpad X60
mainboard, using buspirate hardware v3.a running firmware v6.2-test
that can be found here (bp-spifix.zip):
http://dangerousprototypes.com/forum/viewtopic.php?f=40t=3864sid=426d32139bbbd6fa5abf86ef084cfe8cstart=15#p41505
.


 Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net

 Index: flashrom-buspirate_newcommands/buspirate_spi.c
 ===
 --- flashrom-buspirate_newcommands/buspirate_spi.c  (Revision 1541)
 +++ flashrom-buspirate_newcommands/buspirate_spi.c  (Arbeitskopie)
 @@ -50,6 +50,7 @@
  #define sp_flush_incoming(...) 0
  #endif

 +static int buspirate_interface_version;
  static unsigned char *bp_commbuf = NULL;
  static int bp_commbufsize = 0;

 @@ -83,7 +84,8 @@
 msg_perr(Zero length command!\n);
 return 1;
 }
 -   msg_pspew(Sending);
 +   if (writecnt)
 +   msg_pspew(Sending);

or:
while (writecnt)
instead?

 for (i = 0; i  writecnt; i++)
 msg_pspew( 0x%02x, buf[i]);
  #ifdef FAKE_COMMUNICATION
 @@ -103,23 +105,36 @@
 if (ret)
 return ret;
  #endif
 -   msg_pspew(, receiving);
 +   if (readcnt)
 +   msg_pspew(, receiving);

or:
while (readcnt)
?


 for (i = 0; i  readcnt; i++)
 msg_pspew( 0x%02x, buf[i]);
 msg_pspew(\n);
 return 0;
  }

 -static int buspirate_spi_send_command(struct flashctx *flash,
 - unsigned int writecnt,
 - unsigned int readcnt,
 - const unsigned char *writearr,
 - unsigned char *readarr);
 +static int buspirate_wait_for_string(unsigned char *buf, char *key)
 +{
 +   unsigned int keylen = strlen(key);
 +   int ret;

 -static const struct spi_programmer spi_programmer_buspirate = {
 +   ret = buspirate_sendrecv(buf, 0, keylen);
 +   while (!ret) {
 +   if (!memcmp(buf, key, keylen))
 +   return 0;
 +   memmove(buf, buf + 1, keylen - 1);
 +   ret = buspirate_sendrecv(buf + keylen - 1, 0, 1);
 +   }
 +   return ret;
 +}
 +
 +static int buspirate_spi_send_command(struct flashctx *flash, unsigned int 
 writecnt, unsigned int readcnt,
 + const unsigned char *writearr, unsigned 
 char *readarr);
 +
 +static struct spi_programmer spi_programmer_buspirate = {
 .type   = SPI_CONTROLLER_BUSPIRATE,
 -   .max_data_read  = 12,
 -   .max_data_write = 12,
 +   .max_data_read  = MAX_DATA_UNSPECIFIED,
 +   .max_data_write = MAX_DATA_UNSPECIFIED,
 .command= buspirate_spi_send_command,
 .multicommand   = default_spi_send_multicommand,
 .read   = default_spi_read,
 @@ -138,6 +153,53 @@
 {NULL,  0x0},
  };

 +int buspirate_spi_set_config(unsigned char *buf, int spispeed)
 +{
 +   int ret;
 +
 +   /* Initial setup (SPI peripherals config): Enable power, CS high, AUX 
 */
 +   buf[0] = 0x40 | 0xb;

This could use some explanation of the bits that are set in bit[0]: 0x40 and 0xb

 +   ret = buspirate_sendrecv(buf, 1, 1);
 +   if (ret)
 +   return 1;
 +   if (buf[0] != 0x01) {
 +   msg_perr(Protocol error while setting power/CS/AUX!\n);
 +   return 1;
 +   }
 +
 +   /* Set SPI speed */
 +   buf[0] = 0x60 | spispeed;

explanation of 0x60

 +   ret = buspirate_sendrecv(buf, 1, 1);
 +   if (ret)
 +   return 1;
 +   if (buf[0] != 0x01) {

#define BP_PROTO_ERR_SPEED 0x1?

 +   msg_perr(Protocol error while setting SPI speed!\n);
 +   return 1;
 +   }
 +
 +   /* Set SPI config: output type, idle, clock edge, sample */
 +   buf[0] = 0x80 | 0xa;

explanation of 0x80 and 0xa

 +   ret = buspirate_sendrecv(buf, 1, 1);
 +   if (ret)
 +   return 1;
 +   if (buf[0] != 0x01) {

#define BP_PROTO_ERR_CONFIG 0x1?

 +   msg_perr(Protocol error while setting SPI config!\n);
 +   return 1;
 +   }
 +
 +   /* De-assert CS# */
 +   buf[0] = 0x03;

#define ... 0x3 ?

 +   ret = buspirate_sendrecv(buf, 1, 1);
 +   if (ret)
 +   return 1;
 +   if (buf[0] != 0x01) {

#define

Re: [flashrom] IBM SurePOS 700 4800-783 support

2012-07-10 Thread Idwer Vollering

2012/7/10 jason_vann...@abercrombie.com

 Output from ./flashrom -V -p internal:laptop=this_is_not_a_laptop 

 flashrom v0.9.5.2-r1515 on Linux 2.6.32.12-0.7-default (i686), built with
 libpci 3.1.7, GCC 4.5.1 20101208 [gcc-4_5-branch revision 167585], little
 endian
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OS timer resolution is 1 usecs, 1774M loops per
 second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1009 us, 1 myus
 = 9982 us, 4 myus = 5 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: IBM CORPORATION
 DMI string system-product-name: 4800783
 DMI string system-version: 4800783
 DMI string baseboard-manufacturer: IBM CORPORATION
 DMI string baseboard-product-name: P4M900/VT8251/DME1737
 DMI string baseboard-version: BAD INDEX
 DMI string chassis-type: 
 DMI chassis-type is not specific enough.
 The following protocols are supported: Non-SPI.


So the chipset in your POS machine is, at the moment, not recognized by
flashrom.



 No EEPROM/flash device found.
 Note: flashrom can never write if the flash chip isn't found automatically.


According to this IBM web page [1] there is a Service Processor Renesas
H8S2116 [2] present.

[1] http://www-01.ibm.com/support/docview.wss?uid=pos1R1003969
[2]
http://documentation.renesas.com/doc/products/mpumcu/rej09b0255_h8s2116hm.pdf
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Re: [flashrom] Verbose output of flashrom @ ASUS M3NHT DELUXE Motherboard; everything ok

2012-06-14 Thread Idwer Vollering

2012/6/14 Björn Schmidt bjoern.schm...@gmxpro.de:
 Hello here is the output of  flashrom @ ASUS M3NHT DELUXE  Motherboard


 bjoern@Bjoern-Desktop:~/Downloads/Bios$ sudo flashrom -c AT26DF081A -w

Why did you have to add -c AT26DF081A?

 M3N-HT-DELUXE-3401.BIN -V
 flashrom v0.9.5.2-r1517 on Linux 3.2.0-25-generic (x86_64), built with
 libpci 3.1.8, GCC 4.6.3, little endian
 flashrom is free software, get the source code at
 http://www.flashrom.org

 Calibrating delay loop... OS timer resolution is 1 usecs, 868M loops per
 second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 998 us, 1
 myus = 10004 us, 4 myus = 4 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: System manufacturer
 DMI string system-product-name: System Product Name
 DMI string system-version: System Version
 DMI string baseboard-manufacturer: ASUSTeK Computer INC.
 DMI string baseboard-product-name: M3N-HT DELUXE
 DMI string baseboard-version: 1.XX
 DMI string chassis-type: Desktop
 Found ITE Super I/O, ID 0x8716 on port 0x2e
 Found chipset NVIDIA MCP78S with PCI ID 10de:075d. Enabling flash
 write... This chipset is not really supported yet. Guesswork...
 ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0
 Flash bus type is SPI
 SPI on this chipset is WIP. Please report any success or failure by
 mailing us the verbose output to flashrom@flashrom.org, thanks!
 Found SMBus device 10de:0752 at 00:01:1
 MCP SPI BAR is at 0xfdf8
 Mapping NVIDIA MCP6x SPI at 0xfdf8, unaligned size 0x544.
 SPI control is 0xc012, req=0, gnt=0
 Please send the output of flashrom -V to flashrom@flashrom.org with
 your board name: flashrom -V as the subject to help us finish support
 for your
 chipset. Thanks.
 OK.
 No IT87* serial flash segment enabled.
 The following protocols are supported: SPI.
 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f,
 id2 0x4501
 Chip status register is 10
 Found Atmel flash chip AT26DF081A (1024 kB, SPI) at physical address
 0xfff0.
 Chip status register is 10
 Chip status register: Sector Protection Register Lock (SRPL) is not set
 Chip status register: Sequential Program Mode Status (SPM) is not set
 Chip status register: Erase/Program Error (EPE) is not set
 Chip status register: WP# pin (WPP) is not asserted
 Chip status register: Software Protection Status (SWP): no sectors are
 protected
 Chip status register: Write Enable Latch (WEL) is not set
 Chip status register: Write In Progress (WIP/BUSY) is not set
 Flash image seems to be a legacy BIOS. Disabling coreboot-related
 checks.
 Reading old flash chip contents... done.
 Erasing and writing flash chip... Trying erase function 0...
 0x00-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S,
 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S,
 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S,
 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S,
 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S,
 0x00f000-0x00:S, 0x01-0x010fff:S, 0x011000-0x011fff:S,
 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S,
 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S,
 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S,
 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S,
 0x01e000-0x01efff:S, 0x01f000-0x01:S, 0x02-0x020fff:S,
 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S,
 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S,
 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S,
 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S,
 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02:S,
 0x03-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S,
 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S,
 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S,
 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S,
 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S,
 0x03f000-0x03:S, 0x04-0x040fff:S, 0x041000-0x041fff:S,
 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S,
 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S,
 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S,
 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S,
 0x04e000-0x04efff:S, 0x04f000-0x04:S, 0x05-0x050fff:S,
 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S,
 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S,
 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S,
 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S,
 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05:S,
 0x06-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S,
 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S,
 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S,
 0x069000-0x069fff:S, 0x06a000-0x06afff:S,

Re: [flashrom] [PATCH] Add logfile support to flashrom

2012-06-05 Thread Idwer Vollering

2012/6/3 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net:
 New version, all review comments addressed.
 Note: The log file is opened with mode w, not wb, and that means
 DOS/Windows/Mac users can open the log file with a text editor and the
 line breaks just work. It will require a bit more work on our side if
 the file is uploaded unmodified, though.

 Usage: flashrom --output logfile.txt

 Logfile output has at least dbg2 verbosity or screen verbosity,
 whichever is greater.

 Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net

Tested on Windows and FreeBSD, not tested on DOS.
Acked-by: Idwer Vollering vid...@gmail.com

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Re: [flashrom] [PATCH] Add logfile support to flashrom

2012-05-08 Thread Idwer Vollering

2012/5/3 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net:
 I have decided to discard most of the logging code and rewrite it to be
 more readable. It even worked in preliminary tests.
 TODO:
 - Should -o - be a no-op which just redirects stderr to stdout? Right
 now - is treated as regular file name, but most Unix utilities are
 unable to handle a file with that name (try less - for amusement).

Is this a part of your long-term plan?

 - Add man page entry
 - Is the log level difference for screen/logfile a good thing, and
 should we default the logfile level to dbg2 instead of dbg?

 Add log file support to flashrom.

 If you use cli_classic, the log file will always contain messages at
 a level which is one higher than the one specified. That way we get
 all verbose messages in the log even if the user doesn't specify -V.

This handles -VV and -VVV too, correct?


 Convert all printf() after start of logging to msg_*().

 Allow separate control of log level for screen and logfile in case
 other frontends (e.g. GUI, cli_mfg) want that.

 Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net

 Index: flashrom-logfile/flash.h
 ===
 --- flashrom-logfile/flash.h    (Revision 1528)
 +++ flashrom-logfile/flash.h    (Arbeitskopie)
 @@ -228,7 +228,8 @@
        write_gran_1byte,
        write_gran_256bytes,
  };
 -extern int verbose;
 +extern int verbose_screen;
 +extern int verbose_logfile;
  extern const char flashrom_version[];
  extern char *chip_to_probe;
  void map_flash_registers(struct flashctx *flash);
 @@ -268,13 +269,20 @@
  #define ERROR_FLASHROM_LIMIT -201

  /* cli_output.c */
 +#ifndef STANDALONE
 +int open_logfile(const char * const filename);
 +int close_logfile(void);
 +void start_logging(void);
 +#endif
  /* Let gcc and clang check for correct printf-style format strings. */
 -int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 
 3)));
 -#define MSG_ERROR      0
 -#define MSG_INFO       1
 -#define MSG_DEBUG      2
 -#define MSG_DEBUG2     3

http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/loglevel.h;h=290cd891eb994b34a5060a469bde9589e1419f90;hb=HEAD

#define MSG_NOTICE 2
#define MSG_DEBUG 3

 -#define MSG_BARF       4

#define MSG_SPEW 4

 +enum msglevel {
 +       MSG_ERROR       = 0,
 +       MSG_INFO        = 1,
 +       MSG_DEBUG       = 2,
 +       MSG_DEBUG2      = 3,
 +       MSG_BARF        = 4,
 +};
 +int print(enum msglevel level, const char *fmt, ...) 
 __attribute__((format(printf, 2, 3)));
  #define msg_gerr(...)  print(MSG_ERROR, __VA_ARGS__)   /* general errors */
  #define msg_perr(...)  print(MSG_ERROR, __VA_ARGS__)   /* programmer errors 
 */
  #define msg_cerr(...)  print(MSG_ERROR, __VA_ARGS__)   /* chip errors */
 Index: flashrom-logfile/cli_output.c
 ===
 --- flashrom-logfile/cli_output.c       (Revision 1528)
 +++ flashrom-logfile/cli_output.c       (Arbeitskopie)
 @@ -2,6 +2,7 @@
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2009 Sean Nelson audiohac...@gmail.com
 + * Copyright (C) 2011 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 @@ -20,36 +21,80 @@

  #include stdio.h
  #include stdarg.h
 +#include string.h
 +#include errno.h
  #include flash.h

 -int print(int type, const char *fmt, ...)
 +static FILE *logfile = NULL;
 +
 +#ifndef STANDALONE
 +int close_logfile(void)
  {
 +       if (logfile  fclose(logfile)) {

No sync() / fsync() ?
From http://linux.die.net/man/3/fclose Note that fclose() only
flushes the user space buffers provided by the C library. To ensure
that the data is physically stored on disk the kernel buffers must be
flushed too, for example, with sync(2) or fsync(2).

 +               /* fclose returned an error. Stop writing to be safe. */
 +               logfile = NULL;
 +               msg_perr(Closing the log file returned error %s\n,
 +                        strerror(errno));
 +               return 1;
 +       }
 +       logfile = NULL;
 +       return 0;
 +}
 +
 +int open_logfile(const char * const filename)
 +{
 +       if (!filename) {
 +               msg_gerr(No filename specified.\n);
 +               return 1;
 +       }
 +       if ((logfile = fopen(filename, w)) == NULL) {
 +               perror(filename);
 +               return 1;
 +       }
 +       return 0;
 +}
 +
 +void start_logging(void)
 +{
 +       enum msglevel oldverbose_screen = verbose_screen;
 +       enum msglevel oldverbose_logfile = verbose_logfile;
 +
 +       /* Shut up the console. */
 +       verbose_screen = MSG_ERROR;
 +       verbose_logfile = MSG_DEBUG;
 +       print_version();
 +       verbose_screen = oldverbose_screen;
 +       verbose_logfile = oldverbose_logfile;
 +}
 +#endif /* STANDALONE */
 +
 +/*

Re: [flashrom] Fedora 8 cross compile flashrom failed

2012-04-26 Thread Idwer Vollering

Op 26 april 2012 15:14 heeft 陳力綸 chychen.c...@msa.hinet.net het
volgende geschreven:
 Dear Sir:

  Attached file si for it.

  Thank you.

 Best Regards,
 Loren Chen

We require every submitter to add a sign-off line, see below. Also, a
summary of what a patch adds is required.
A good example can be found here: http://patchwork.coreboot.org/patch/3598/
Don't forget to attach your patch!


Sign-off Procedure

We employ a similar sign-off procedure for coreboot as the Linux
developers do. Please add a note such as

Signed-off-by: Random J Developer ran...@developer.example.org

to your email/patch if you agree with the following Developer's
Certificate of Origin 1.1.

Patches without a Signed-off-by cannot be pushed to gerrit!

You have to use your real name in the Signed-off-by line and in any
copyright notices you add. Patches without an associated real name
cannot be committed!

Developer's Certificate of Origin 1.1:

By making a contribution to this project, I certify that:

(a) The contribution was created in whole or in part by me and I have
the right to submit it under the open source license indicated in the file; or

(b) The contribution is based upon previous work that, to the best of my
knowledge, is covered under an appropriate open source license and I have the
right under that license to submit that work with modifications, whether created
in whole or in part by me, under the same open source license (unless I am
permitted to submit under a different license), as indicated in the file; or

(c) The contribution was provided directly to me by some other person who
certified (a), (b) or (c) and I have not modified it; and

(d) In the case of each of (a), (b), or (c), I understand and agree that
this project and the contribution are public and that a record of the
contribution
(including all personal information I submit with it, including my sign-off) is
maintained indefinitely and may be redistributed consistent with this
project or the
open source license indicated in the file.



HTH,
Idwer

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Re: [flashrom] Fedora 8 cross compile flashrom failed

2012-04-25 Thread Idwer Vollering

CC'ing flashrom@flashrom.org, please use reply-to-all.

Op 25 april 2012 06:53 schreef 陳力綸 chychen.c...@msa.hinet.net het
volgende:

 Dear Sir:


Hello,


 

 ** **

   I am s senior BIOS engineer,

 ** **

   I try cross compile the flashrom for DOS but it say can’t not fount
 pciutil header and can’t build.


May I ask why you are using DOS, as a target operating system, instead of
Linux?

See this page: http://www.flashrom.org/Downloads
You have to install, quote: pciutils development package
(pciutils-dev/libpci-dev/pciutils-devel, depending on OS/distribution)


 

 ** **

   Can you give me some hinet about how to correct dot it?


Yes: you have to adjust/include the path(s) to i586-pc-msdosdjgpp-gcc and
the cross-compiled versions of libgetopt ( http://assembler.cz/flashrom/ )
and libpci.
I suggest that you study flashrom's Makefile, all the hints should be there.


 

 ** **

   Thank you.

 ** **

 Best Regards,

 Loren Chen


Idwer
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Re: [flashrom] Fedora 8 cross compile flashrom failed

2012-04-25 Thread Idwer Vollering

Op 25 april 2012 13:11 heeft 陳力綸 chychen.c...@msa.hinet.net het
volgende geschreven:
 Dear Sir:



   Because I am also a DOS fans not much like using OS(like Windows, Linux)
 to flash BIOS.



   And cross compiler is much interesting to me, because I not touch it
 before.

Perhaps you can ask a colleague for assistance?




   So, I am eager want to know how can I learn to set up a cross compiler
 environment for me to play with funny.

Start with installing DJGPP [1] and follow the steps documented at the
DOS wiki page [2].

[1] http://www.delorie.com/djgpp/
[2] http://www.flashrom.org/DOS




   So, I do need your help to do so, I am stupid a little but I am a work
 hard man.

If you want I can build a DOS .exe for you; send a proper patch with
your Foxconn/WynMax as the sign-off:
http://flashrom.org/Development_Guidelines




 Best Regards,

 Loren Chen

 From: Idwer Vollering [mailto:vid...@gmail.com]
 Sent: Wednesday, April 25, 2012 6:42 PM
 To: 陳力綸
 Cc: flashrom
 Subject: Re: Fedora 8 cross compile flashrom failed




 CC'ing flashrom@flashrom.org, please use reply-to-all.

 Op 25 april 2012 06:53 schreef 陳力綸 chychen.c...@msa.hinet.net het
 volgende:

 Dear Sir:


 Hello,




   I am s senior BIOS engineer,



   I try cross compile the flashrom for DOS but it say can’t not fount
 pciutil header and can’t build.


 May I ask why you are using DOS, as a target operating system, instead of
 Linux?


 See this page: http://www.flashrom.org/Downloads
 You have to install, quote: pciutils development package
 (pciutils-dev/libpci-dev/pciutils-devel, depending on OS/distribution)




   Can you give me some hinet about how to correct dot it?


 Yes: you have to adjust/include the path(s) to i586-pc-msdosdjgpp-gcc and
 the cross-compiled versions of libgetopt ( http://assembler.cz/flashrom/ )
 and libpci.
 I suggest that you study flashrom's Makefile, all the hints should be there.




   Thank you.



 Best Regards,

 Loren Chen


 Idwer

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Re: [flashrom] info recovery bios foxconn bloodrage socket 1366.

2012-04-22 Thread Idwer Vollering

Op 22 april 2012 22:30 schreef pretoria...@libero.it
pretoria...@libero.ithet volgende:


 Hello,
 Thank you for your response.


Please use reply-to-all, thanks.



 ok with an external programmer can reprogram the chip, I wonder if this
 programmer is fine:
 USB SPI BIOS 25X Series EN25T80 Programmer / AMIC / ATMEL / WINBOND / EON
 / ST / MXIC / Nex. I found it on ebay.


Do you have a link to this programmer?


 The motherboard is propio that indicated to you, and has 2 bios chip, but
 I unfortunately have corrupted both chips, I was a bit careless.


What does 'propio' mean?




 For if you know any store that sells chips reprogrammed?


You might be able to buy a replacement chip on this website:
http://bios-repair.co.uk

Information about flash chips can be found at this URL:
http://flashrom.org/Technology
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Re: [flashrom] info recovery bios foxconn bloodrage socket 1366.

2012-04-21 Thread Idwer Vollering

Op 20 april 2012 15:46 schreef pretoria...@libero.it
pretoria...@libero.ithet volgende:


 Good morning,

 I contact you for a problem of corrupted bios on my motherboard,
 unfortunately
 I made the flash via windows xp, and after I received an error, I restart
 the
 PC with the screen remains black. I would like to know if there is some
 procedure to restore the bios, or some alternative system of flash chips.


You can use an external programmer to restore the BIOS/(U)EFI image:
http://flashrom.org/Supported_programmers

This is a photo of your mainboard:
http://i203.photobucket.com/albums/aa319/fjord_of_war/IMG_3394.jpg - what
is the second chip for, does the manual say something about this?

Idwer


 Best regards.

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Re: [flashrom] [PATCH] Add support for Numonyx N25Q064

2012-04-05 Thread Idwer Vollering

Op 5 april 2012 13:29 heeft Niklas Söderlund
niklas.soderl...@ericsson.com het volgende geschreven:
 From: Niklas Söderlund niklas.soderl...@combitech.se

 Niklas Söderlund niklas.soderl...@combitech.se

I'll treat this as a Signed-off-by:.

 ---
  flashchips.c |   29 +
  flashchips.h |    1 +
  2 files changed, 30 insertions(+), 0 deletions(-)

 diff --git a/flashchips.c b/flashchips.c
 index b6296c5..c23bd34 100644
 --- a/flashchips.c
 +++ b/flashchips.c
 @@ -5010,6 +5010,35 @@ const struct flashchip flashchips[] = {
        },

        {
 +               .vendor         = Numonyx,
 +               .name           = N25Q064,
 +               .bustype        = BUS_SPI,
 +               .manufacture_id = ST_ID,
 +               .model_id       = ST_N25Q064,
 +               .total_size     = 8192,
 +               .page_size      = 256,
 +               .tested         = TEST_UNTESTED,

If you change the above line to TEST_PREW (can you provide some output
that shows probing/reading/erasing/writing?), this is
Acked-by: Idwer Vollering vid...@gmail.com

 +               .probe          = probe_spi_rdid,
 +               .probe_timing   = TIMING_ZERO,
 +               .block_erasers  =
 +               {
 +                       {
 +                               .eraseblocks = { {4 * 1024, 2048 } },
 +                               .block_erase = spi_block_erase_20,
 +                       }, {
 +                               .eraseblocks = { {64 * 1024, 128} },
 +                               .block_erase = spi_block_erase_d8,
 +                       }, {
 +                               .eraseblocks = { {8 * 1024 * 1024, 1} },
 +                               .block_erase = spi_block_erase_c7,
 +                       }
 +               },
 +               .unlock         = spi_disable_blockprotect,
 +               .write          = spi_chip_write_256,
 +               .read           = spi_chip_read,
 +       },
 +
 +       {
                .vendor         = PMC,
                .name           = Pm25LV010,
                .bustype        = BUS_SPI,
 diff --git a/flashchips.h b/flashchips.h
 index de3c79d..89d20bb 100644
 --- a/flashchips.h
 +++ b/flashchips.h
 @@ -574,6 +574,7 @@
  #define ST_M29W010B            0x23
  #define ST_M29W040B            0xE3
  #define ST_M29W512B            0x27
 +#define ST_N25Q064             0xBA17

  #define SYNCMOS_MVC_ID         0x40    /* SyncMOS (SM) and Mosel Vitelic 
 Corporation (MVC) */
  #define MVC_V29C51000T         0x00
 --
 1.7.7


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Re: [flashrom] Support for Intel DH89xxCC PCH

2012-03-27 Thread Idwer Vollering

Op 27 maart 2012 21:01 heeft Sean Mahood smah...@uwaterloo.ca het
volgende geschreven:
 Hello,

 I have confirmed that the the following addition to chipset_enable.c will
 allow the programming of DH89xxCC PCH chips.

    {0x8086, 0x1d40, OK, Intel, X79,        enable_flash_pch6},
    {0x8086, 0x1d41, NT, Intel, X79,        enable_flash_pch6},
 +   {0x8086, 0x2310, NT, Intel, DH89xxCC,   enable_flash_pch6},

If programming (write/erase) on that DH89xxCC chipset is confirmed to
work, you should change NT to OK.

    {0x8086, 0x2410, OK, Intel, ICH,        enable_flash_ich_4e},
    {0x8086, 0x2420, OK, Intel, ICH0,       enable_flash_ich_4e},


 Similar patches have been made to operating systems:

 Linux
 http://groups.google.com/group/linux.kernel/browse_thread/thread/ddfde330d4ce70f8

 FreeBSD
 http://lists.freebsd.org/pipermail/svn-src-head/2011-January/024584.html

 I am not sure of the process in which to get this added to the next release,
 so I thought it wise to post it here.

Can you download the latest code [1], edit chipset_enable.c and submit
and sign-off a patch - see [2]?

[1] http://www.flashrom.org/Downloads#Installation_from_source
[2] http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure


 Hope this helps!

 Sincerely,
 Sean Mahood

Idwer

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Re: [flashrom] [PATCH 7/8] check if write enable is really set in nicintel_spi_init (and minor comment changes).

2012-02-20 Thread Idwer Vollering

2011/3/15 Stefan Tauner stefan.tau...@student.tuwien.ac.at:
 Signed-off-by: Stefan Tauner stefan.tau...@student.tuwien.ac.at

Adding pci_mmio_writel(FLASH_WRITES_DISABLED, nicintel_spibar +
EECD); right after the usage of register_shutdown() works as it
should:

Initializing nicintel_spi programmer
Found Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 01:01.0).
Requested BAR is MEM, 32bit, not prefetchable
Enabling flash write access failed.
Error: Programmer initialization failed.

Acked-by: Idwer Vollering vid...@gmail.com

 ---
  nicintel_spi.c |   15 +--
  1 files changed, 13 insertions(+), 2 deletions(-)

 diff --git a/nicintel_spi.c b/nicintel_spi.c
 index 811ed6e..88d86af 100644
 --- a/nicintel_spi.c
 +++ b/nicintel_spi.c
 @@ -34,11 +34,14 @@

  #define MEMMAP_SIZE getpagesize()

 +/* EEPROM/Flash Control  Data Register */
  #define EECD   0x10
 +/* Flash Access Register */
  #define FLA    0x1c

  /*
  * Register bits of EECD.
 + * Table 13-6
  *
  * Bit 04, 05: FWE (Flash Write Enable Control)
  * 00b = not allowed
 @@ -49,8 +52,9 @@
  #define FLASH_WRITES_DISABLED  0x10 /* FWE: 1b */
  #define FLASH_WRITES_ENABLED   0x20 /* FWE: 10b */

 -/* Flash Access register bits */
 -/* Table 13-9 */
 +/* Flash Access register bits
 + * Table 13-9
 + */
  #define FL_SCK 0
  #define FL_CS  1
  #define FL_SI  2
 @@ -157,6 +161,13 @@ int nicintel_spi_init(void)
        tmp |= FLASH_WRITES_ENABLED;
        pci_mmio_writel(tmp, nicintel_spibar + EECD);

 +       /* test if FWE is really set to allow writes */
 +       tmp = pci_mmio_readl(nicintel_spibar + EECD);
 +       if ( (tmp  FLASH_WRITES_DISABLED) || !(tmp  FLASH_WRITES_ENABLED) ) 
 {
 +               msg_perr(Enabling flash write access failed.\n);
 +               return 1;
 +       }
 +
        /* 1 usec halfperiod delay for now. */
        if (bitbang_spi_init(bitbang_spi_master_nicintel, 1))
                return 1;
 --
 1.7.1


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Re: [flashrom] [PATCH] Workaround missing %hhx support in MinGW sscanf

2012-02-15 Thread Idwer Vollering

2012/2/16 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net:
 MinGW uses standard Windows C libraries and those apparently don't
 support %hhx for sscanf into a uint8_t. SCNx8 isn't available either.

 Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net

Acked-by: Idwer Vollering vid...@gmail.com


 Index: flashrom-mingw_workaround_broken_sscanf_uint8t/dummyflasher.c
 ===
 --- flashrom-mingw_workaround_broken_sscanf_uint8t/dummyflasher.c       
 (Revision 1492)
 +++ flashrom-mingw_workaround_broken_sscanf_uint8t/dummyflasher.c       
 (Arbeitskopie)
 @@ -199,7 +199,12 @@
                        }
                }
                for (i = 0; i  spi_blacklist_size; i++) {
 -                       sscanf(tmp + i * 2, %2hhx, spi_blacklist[i]);
 +                       unsigned int tmp2;
 +                       /* SCNx8 is apparently not supported by MSVC (and thus
 +                        * MinGW), so work around it with an extra variable
 +                        */
 +                       sscanf(tmp + i * 2, %2x, tmp2);
 +                       spi_blacklist[i] = (uint8_t)tmp2;
                }
                msg_pdbg(SPI blacklist is );
                for (i = 0; i  spi_blacklist_size; i++)
 @@ -230,7 +235,12 @@
                        }
                }
                for (i = 0; i  spi_ignorelist_size; i++) {
 -                       sscanf(tmp + i * 2, %2hhx, spi_ignorelist[i]);
 +                       unsigned int tmp2;
 +                       /* SCNx8 is apparently not supported by MSVC (and thus
 +                        * MinGW), so work around it with an extra variable
 +                        */
 +                       sscanf(tmp + i * 2, %2x, tmp2);
 +                       spi_ignorelist[i] = (uint8_t)tmp2;
                }
                msg_pdbg(SPI ignorelist is );
                for (i = 0; i  spi_ignorelist_size; i++)


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Re: [flashrom] FAILED : mcp61sm -am

2012-02-09 Thread Idwer Vollering

2012/2/9 Vince S vince0...@gmail.com:
 good evening
 Good news I realized what was happening and managed to flash my bios.

 The bios I was cleanliness was set to boot block protection

 there is no pin on the mainboard but the parameter is adjustable from the
 interface of the bios, so I changed this parameter in the bios, boot from my
 linux session, then I share them with the bios mine I flashed with flashrom
 and that's ok

I would like to see the output of lspci -nnvvvxxx and superiotool
-deV (run both commands as root) before and after changing this
parameter, so we can look into adding board enabling code.


 Thanks for your work

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Re: [flashrom] [PATCH] flashrom.c: Reorder list of options to test

2012-01-13 Thread Idwer Vollering

2012/1/12 Paul Menzel paulepan...@users.sourceforge.net:
 Date: Thu, 12 Jan 2012 01:59:42 +0100
 Subject: [PATCH] flashrom.c: Reorder list of options to test

 If a chip is unknown the user is asked to test and report the result to the 
 mailing list. Having `-VE` listed as the last option can result in an 
 unbootable system for users not knowing what the command does, since 
 rebooting the system after that command is fatal since the flash chip is 
 empty. [1]

 Reorder the options as a quick fix to prevent that in the future as suggested 
 by idwer on #flashrom.

 [1] http://www.flashrom.org/pipermail/flashrom/2012-January/008551.html

 Signed-off-by: Paul Menzel paulepan...@users.sourceforge.net
 ---
  flashrom.c |    2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)

 diff --git a/flashrom.c b/flashrom.c
 index f1a6165..ee68344 100644
 --- a/flashrom.c
 +++ b/flashrom.c
 @@ -1600,7 +1600,7 @@ void check_chip_supported(const struct flashctx *flash)
                            include the flashrom\n
                          output with the additional -V option for all 
                            operations you tested (-V, -Vr,\n
 -                         -Vw, -VE), and mention which mainboard or 
 +                         -VE, -Vw), and mention which mainboard or 
                            programmer you tested.\n
                          Please mention your board in the subject line. 
                            Thanks for your help!\n);

I was thinking of this (see patch), this way flashrom shows verbs
(actions) instead of parameters.

Signed-off-by: Idwer Vollering vid...@gmail.com

Index: flashrom.c
===
--- flashrom.c  (revision 1485)
+++ flashrom.c  (working copy)
@@ -1598,10 +1598,11 @@
any of the above operations\n
  work correctly for you with this flash part. Please 
include the flashrom\n
- output with the additional -V option for all 
-   operations you tested (-V, -Vr,\n
- -VE, -Vw), and mention which mainboard or 
+ output with the -V option for all 
+   operations you tested (verbose, verbose read,\n
+ verbose erase, verbose write), and mention
which mainboard or 
programmer you tested.\n
+ The parameters are listed after running
'flashrom --help'\n
  Please mention your board in the subject line. 
Thanks for your help!\n);
}

 --
 1.7.8.3

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Re: [flashrom] flashrom -V

2012-01-11 Thread Idwer Vollering

2012/1/11 Vince S vince0...@gmail.com:
 Hello
 The output of flashrom -V :


 flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci
 3.1.7, GCC 4.6.1, little endian
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per
 second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 1 myus
 = 10004 us, 4 myus = 5 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: Acer
 DMI string system-product-name: Aspire T180
 DMI string system-version: R01-A2
 DMI string baseboard-manufacturer: Acer
 DMI string baseboard-product-name: EM61SM/EM61PM 
 DMI string baseboard-version:  
 DMI string chassis-type: Desktop
 Found ITE Super I/O, ID 0x8726 on port 0x2e
 Found chipset NVIDIA MCP61 with PCI ID 10de:03e0.
 This chipset is marked as untested. If you are using an up-to-date version
 of flashrom please email a report to flashrom@flashrom.org including a
 verbose (-V) log. Thank you!
 Enabling flash write... This chipset is not really supported yet.
 Guesswork...
 ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0
 Flash bus type is LPC
 Found SMBus device 10de:03eb at 00:01:1
 MCP SPI BAR is at 0x
 MCP SPI is not used.
 Please send the output of flashrom -V to flashrom@flashrom.org with
 your board name: flashrom -V as the subject to help us finish support for
 your
 chipset. Thanks.
 OK.
 This chipset supports the following protocols: LPC.
 Super I/O ID 0x8726 is not on the list of flash capable controllers.
 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Found SST flash chip SST49LF040B (512 kB, LPC) at physical address
 0xfff8.
 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing
 information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content

 Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is
 normal flash content, id2 is normal flash content
 Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is
 normal flash content, id2 is normal flash content
 Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2
 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2
 0x50, id1 is normal flash content
 ===
 This flash part has status UNTESTED for operations: WRITE
 The test status of this chip may have been updated in the latest development
 version of flashrom. If you are running the latest development version,
 please email a report to flashrom@flashrom.org if any of the above
 operations
 work correctly for you with this flash part. Please include the flashrom
 output with the additional -V option for all operations you tested (-V, -Vr,
 -Vw, -VE), and mention which mainboard or programmer you tested.
 Please mention your board in the subject line. Thanks for your help!

 No operations were specified.
 Restoring PCI config space for 00:01:0 reg 0x6d
 Restoring PCI config space for 00:01:0 reg 0x90
 Restoring PCI config space for 00:01:0 reg 0x8c
 Restoring PCI config space for 00:01:0 reg 0x88


 

 Here the output of flashrom -VE :

 flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci
 3.1.7, GCC 4.6.1, little endian
 flashrom is free software, get the source code at

Re: [flashrom] flashrom -V

2012-01-11 Thread Idwer Vollering

2012/1/11 Idwer Vollering vid...@gmail.com:
 2012/1/11 Vince S vince0...@gmail.com:
 Hello
 The output of flashrom -V :


 flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci
 3.1.7, GCC 4.6.1, little endian
 flashrom is free software, get the source code at http://www.flashrom.org

 Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per
 second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 1 myus
 = 10004 us, 4 myus = 5 us, OK.
 Initializing internal programmer
 No coreboot table found.
 DMI string system-manufacturer: Acer
 DMI string system-product-name: Aspire T180
 DMI string system-version: R01-A2
 DMI string baseboard-manufacturer: Acer
 DMI string baseboard-product-name: EM61SM/EM61PM 
 DMI string baseboard-version:  
 DMI string chassis-type: Desktop
 Found ITE Super I/O, ID 0x8726 on port 0x2e
 Found chipset NVIDIA MCP61 with PCI ID 10de:03e0.
 This chipset is marked as untested. If you are using an up-to-date version
 of flashrom please email a report to flashrom@flashrom.org including a
 verbose (-V) log. Thank you!
 Enabling flash write... This chipset is not really supported yet.
 Guesswork...
 ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0
 Flash bus type is LPC
 Found SMBus device 10de:03eb at 00:01:1
 MCP SPI BAR is at 0x
 MCP SPI is not used.
 Please send the output of flashrom -V to flashrom@flashrom.org with
 your board name: flashrom -V as the subject to help us finish support for
 your
 chipset. Thanks.
 OK.
 This chipset supports the following protocols: LPC.
 Super I/O ID 0x8726 is not on the list of flash capable controllers.
 Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
 id1 is normal flash content
 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Found SST flash chip SST49LF040B (512 kB, LPC) at physical address
 0xfff8.
 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing
 information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content

 Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is
 normal flash content, id2 is normal flash content
 Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is
 normal flash content, id2 is normal flash content
 Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
 parity violation, id1 is normal flash content, id2 is normal flash content
 Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2
 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash
 content
 Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2
 0x50, id1 is normal flash content
 ===
 This flash part has status UNTESTED for operations: WRITE
 The test status of this chip may have been updated in the latest development
 version of flashrom. If you are running the latest development version,
 please email a report to flashrom@flashrom.org if any of the above
 operations
 work correctly for you with this flash part. Please include the flashrom
 output with the additional -V option for all operations you tested (-V, -Vr,
 -Vw, -VE), and mention which mainboard or programmer you tested.
 Please mention your board in the subject line. Thanks for your help!

 No operations were specified.
 Restoring PCI config space for 00:01:0 reg 0x6d
 Restoring PCI config space for 00:01:0 reg 0x90
 Restoring PCI config space for 00:01:0 reg 0x8c
 Restoring PCI config space for 00:01:0 reg 0x88


 

 Here the output of flashrom -VE :

 flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci
 3.1.7, GCC 4.6.1, little endian
 flashrom is free

[flashrom] Fwd: flashrom -V

2012-01-11 Thread Idwer Vollering

-- Forwarded message --
From: Vince S vince0...@gmail.com
Date: 2012/1/11
Subject: Re: [flashrom] flashrom -V
To: Idwer Vollering vid...@gmail.com

It s to late i already shutdown the oc so i can t restart...

Le 11 janv. 2012 16:58, Idwer Vollering vid...@gmail.com a écrit :

 2012/1/11 Idwer Vollering vid...@gmail.com:
  2012/1/11 Vince S vince0...@gmail.com:
  Hello
  The output of flashrom -V :

  flashrom v0.9.4-r1394 on Linux 3.0.0-15-generic (x86_64), built with libpci
  3.1.7, GCC 4.6.1, little endian
  flashrom is free software, get the source code at http://www.flashrom.org

  Calibrating delay loop... OS timer resolution is 1 usecs, 736M loops per
  second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 1 myus
  = 10004 us, 4 myus = 5 us, OK.
  Initializing internal programmer
  No coreboot table found.
  DMI string system-manufacturer: Acer
  DMI string system-product-name: Aspire T180
  DMI string system-version: R01-A2
  DMI string baseboard-manufacturer: Acer
  DMI string baseboard-product-name: EM61SM/EM61PM 
  DMI string baseboard-version:  
  DMI string chassis-type: Desktop
  Found ITE Super I/O, ID 0x8726 on port 0x2e
  Found chipset NVIDIA MCP61 with PCI ID 10de:03e0.
  This chipset is marked as untested. If you are using an up-to-date version
  of flashrom please email a report to flashrom@flashrom.org including a
  verbose (-V) log. Thank you!
  Enabling flash write... This chipset is not really supported yet.
  Guesswork...
  ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0
  Flash bus type is LPC
  Found SMBus device 10de:03eb at 00:01:1
  MCP SPI BAR is at 0x
  MCP SPI is not used.
  Please send the output of flashrom -V to flashrom@flashrom.org with
  your board name: flashrom -V as the subject to help us finish support for
  your
  chipset. Thanks.
  OK.
  This chipset supports the following protocols: LPC.
  Super I/O ID 0x8726 is not on the list of flash capable controllers.
  Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
  Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
  id1 is normal flash content
  Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
  Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50,
  id1 is normal flash content
  Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 
  0x50,
  id1 is normal flash content
  Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
  Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50
  Found SST flash chip SST49LF040B (512 kB, LPC) at physical address
  0xfff8.
  Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing
  information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
  0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
  flash
  content

  Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, 
  id1
  parity violation, id1 is normal flash content, id2 is normal flash content
  Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 
  is
  normal flash content, id2 is normal flash content
  Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 
  is
  normal flash content, id2 is normal flash content
  Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
  parity violation, id1 is normal flash content, id2 is normal flash content
  Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1
  parity violation, id1 is normal flash content, id2 is normal flash content
  Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1
  parity violation, id1 is normal flash content, id2 is normal flash content
  Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 
  0x50
  Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 
  0x50
  Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 
  0x50
  Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2
  0xff, id1 parity violation, id1 is normal flash content, id2 is normal 
  flash
  content
  Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2
  0x50, id1 is normal flash content
  ===
  This flash part has status UNTESTED for operations: WRITE
  The test status of this chip may have been updated in the latest 
  development
  version of flashrom. If you are running the latest development version,
  please email a report to flashrom@flashrom.org if any of the above
  operations
  work correctly for you with this flash part. Please include the flashrom
  output with the additional -V option for all operations you tested (-V, 
  -Vr,
  -Vw, -VE), and mention which mainboard or programmer you tested.
  Please mention your board in the subject line. Thanks for your help!

  No operations were

Re: [flashrom] Difference of factory bios and dumped image

2011-12-31 Thread Idwer Vollering

2011/12/31 Prakash Punnoor praka...@arcor.de:
On 31.12.2011 11:39, Paul Menzel wrote:

Am Samstag, den 31.12.2011, 10:55 +0100 schrieb Prakash Punnoor:

flashrom kind of works on my system, but not with the factory images. If I
read it out with flashrom and write it back with flashrom (also to a
different
chip) it works. The sizes of factory and dumped image are same but they are
somewhat binary different. Any idea? The motherboard is Abit A-S78H. As I am
playing around with coreboot - so far unsuccessfully - I want to know
whether
flashrom is writing the generated image correctly... I can upload both
images
somewhere if interested. This is flashrom output on my system:

flashrom v0.9.4-r1395 on Linux 3.2.0-rc7+ (x86_64), built with libpci 3.1.7,
GCC 4.5.2, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found chipset AMD SB700/SB710/SB750/SB850. Enabling flash write... OK.
This chipset supports the following protocols: LPC, FWH, SPI.
Found Macronix flash chip MX25L8005 (1024 kB, SPI) at physical address
0xfff0.
No operations were specified.
Unfortunately this question seems not be listed in the FAQ. Most of the
time some areas differ because the MAC address and other configuration
data of the downloaded images differs [2]. I hope you mean the
downloaded image by factory/vendor image.
To clarify:
- Image I got from vendor web page: Flashed with flashrom won't work
(machine doesn't POST). Flashed with awdflash works.

Is the bootblock in the downloaded image intact/present? You can use
bios_extract: http://cgit.freedesktop.org/~libv/bios_extract

What happens when you reset the CMOS/ESCD data after flashing with
flashrom? awdflash does that with the /cp parameter, see
http://www.plasma-online.de/textual/howto/flash_award.html

- Image flashed with awdflash, dumped from bios chip using flashrom and
writing back using flashrom (to an empty chip also) works (machine does
POST and I can boot my OS)
- I haven't tried writing flashrom dumped image using awdflash.
- If I write a dumped image using flashrom and later do a flashrom -v it
will complain about some difference. But flashrom -w verify pass was OK.

This makes my head scratch and I wonder whether flashrom is working 100%
correctly - especially using the generated coreboot rom.

Do you have a POST card? You can get one off dealextreme..
http://www.dealextreme.com/p/pc-motherboard-repair-troubleshoot-boot-failure-diagnostic-pci-card-21997

Regards,

Prakash

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Re: [flashrom] X8DTT-H

2011-12-21 Thread Idwer Vollering

Hi,

2011/12/21 Jimmie Tauriainen jim...@southpole.se:
 Hi,

 This is a Supermicro X8DTT-HIBQF but it uses the same BIOS as X8DTT-H as
 refered in DMI. Probably all H8DTT* boards uses same.

 Anyway attaching flashrom -V outputs.

Can you attach the output of 'lspci -nnvvvxxx' and 'superiotool -deV'
(run as root) as well? Some code needs to be written to clear the
erase/write protection, see http://flashrom.org/Board_Enable


 root@spts-10-143:~/flashrom# dmidecode -t baseboard
 # dmidecode 2.9
 SMBIOS 2.6 present.

 Handle 0x0002, DMI type 2, 15 bytes
 Base Board Information
        Manufacturer: Supermicro
        Product Name: X8DTT-H
        Version: 2.0
        Serial Number: 1234567890
        Asset Tag: 1234567890
        Features:
                Board is a hosting board
                Board is replaceable
        Location In Chassis: 1234567890
        Chassis Handle: 0x0003
        Type: Motherboard
        Contained Object Handles: 0


 Best regards,
 Jimmie

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