Re: [PATCH] RISC-V: Add builtin .def file dependencies

[Kito Cheng via Gcc-patches]

LGTM, thanks for fixing that :)

On Tue, Sep 19, 2023 at 8:54 AM Tsukasa OI via Gcc-patches
 wrote:
>
> From: Tsukasa OI 
>
> riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def
> (making dependencies) but their dependencies must be explicitly defined at
> the configuration file, t-riscv.
>
> They were the last two .def files without correct dependency information.
>
> gcc/ChangeLog:
>
> * config/riscv/t-riscv: Add dependencies for riscv-builtins.cc,
> riscv-cmo.def and riscv-scalar-crypto.def.
> ---
>  gcc/config/riscv/t-riscv | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
> index 104f85c6c8b1..f137e1f17ef3 100644
> --- a/gcc/config/riscv/t-riscv
> +++ b/gcc/config/riscv/t-riscv
> @@ -8,7 +8,9 @@ riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc 
> $(CONFIG_H) \
>$(DIAGNOSTIC_CORE_H) $(OPTABS_H) $(RISCV_BUILTINS_H) \
>$(srcdir)/config/riscv/riscv-ftypes.def \
>$(srcdir)/config/riscv/riscv-vector-builtins-types.def \
> -  $(srcdir)/config/riscv/riscv-modes.def
> +  $(srcdir)/config/riscv/riscv-modes.def \
> +  $(srcdir)/config/riscv/riscv-cmo.def \
> +  $(srcdir)/config/riscv/riscv-scalar-crypto.def
> $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
> $(srcdir)/config/riscv/riscv-builtins.cc
>
>
> base-commit: 68845f7c4d58186cc0a5b09f7511f3c0a8f07e88
> --
> 2.42.0
>

Re: On a Plane During Tomorrow's RISC-V GCC Patchwork Meeting

[Kito Cheng via Gcc-patches]

I may missed that one time too, not on plane yet, but need to go bed
earlier due to my flight is in next day early morning...

On Mon, Sep 18, 2023 at 11:07 PM Palmer Dabbelt  wrote:
>
> My flight to the Cauldron lands in the middle of the meeting, so I'm
> going to miss it.  In theory it's all set up such that anyone can
> join/run the meeting.

Re: [PATCH] RISC-V: Support VLS modes reduction[PR111153]

[Kito Cheng via Gcc-patches]

LGTM

On Sun, Sep 17, 2023 at 10:07 AM Juzhe-Zhong  wrote:
>
> This patch supports VLS reduction vectorization.
>
> It can optimize the current reduction vectorization codegen with current COST 
> model.
>
> #define DEF_REDUC_PLUS(TYPE)\
> TYPE __attribute__ ((noinline, noclone))\
> reduc_plus_##TYPE (TYPE * __restrict a, int n)  \
> {   \
>   TYPE r = 0;   \
>   for (int i = 0; i < n; ++i)   \
> r += a[i];  \
>   return r; \
> }
>
> #define TEST_PLUS(T)\
>   T (int32_t)   \
>
> TEST_PLUS (DEF_REDUC_PLUS)
>
>
> Before this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> lui a4,%hi(.LC0)
> lui a5,%hi(.LC1)
> addia4,a4,%lo(.LC0)
> vlm.v   v0,0(a4)
> addia5,a5,%lo(.LC1)
> andia1,a1,-4
> vmv1r.v v2,v3
> vlm.v   v4,0(a5)
> vcompress.vmv2,v1,v0
> vmv1r.v v0,v4
> vadd.vv v1,v2,v1
> vcompress.vmv3,v1,v0
> vadd.vv v3,v3,v1
> vmv.x.s a0,v3
> sext.w  a0,a0
> beq a3,a1,.L12
>
> After this patch:
>
> vle32.v v2,0(a5)
> addia5,a5,16
> vadd.vv v1,v1,v2
> bne a5,a4,.L4
> li  a5,0
> andia1,a1,-4
> vmv.s.x v2,a5
> vredsum.vs  v1,v1,v2
> vmv.x.s a0,v1
> beq a3,a1,.L12
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Add VLS modes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction case.
> * gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 30 +++
>  .../riscv/rvv/autovec/vls/reduc-1.c   | 31 +++
>  .../riscv/rvv/autovec/vls/reduc-10.c  | 50 
>  .../riscv/rvv/autovec/vls/reduc-11.c  | 46 +++
>  .../riscv/rvv/autovec/vls/reduc-12.c  | 30 +++
>  .../riscv/rvv/autovec/vls/reduc-13.c  | 28 +++
>  .../riscv/rvv/autovec/vls/reduc-14.c  | 26 ++
>  .../riscv/rvv/autovec/vls/reduc-15.c  | 81 +++
>  .../riscv/rvv/autovec/vls/reduc-16.c  | 75 +
>  .../riscv/rvv/autovec/vls/reduc-17.c  | 69 
>  .../riscv/rvv/autovec/vls/reduc-18.c  | 63 +++
>  .../riscv/rvv/autovec/vls/reduc-19.c  | 18 +
>  .../riscv/rvv/autovec/vls/reduc-2.c   | 29 +++
>  .../riscv/rvv/autovec/vls/reduc-20.c  | 17 
>  .../riscv/rvv/autovec/vls/reduc-21.c  | 16 
>  .../riscv/rvv/autovec/vls/reduc-3.c   | 27 +++
>  .../riscv/rvv/autovec/vls/reduc-4.c   | 25 ++
>  .../riscv/rvv/autovec/vls/reduc-5.c   | 18 +
>  .../riscv/rvv/autovec/vls/reduc-6.c   | 17 
>  .../riscv/rvv/autovec/vls/reduc-7.c   | 16 
>  .../riscv/rvv/autovec/vls/reduc-8.c   | 58 +
>  .../riscv/rvv/autovec/vls/reduc-9.c   | 54 +
>  23 files changed, 825 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
>  create mode 100644 

Re: [PATCH] RISC-V: Fix vsetvl pass ICE

[Kito Cheng via Gcc-patches]

OK for backport now, steps for backport:
- checkout to releases/gcc-13 branch
- ./contrib/git-backport.py 
- Make sure everything is alright, build-able, no extra regression.
- push releases/gcc-13 branch!

On Mon, Sep 18, 2023 at 3:54 PM Lehua Ding  wrote:
>
> Hi Kito,
>
> Can this bugfix be backported to GCC 13 now? If so, how can I do it?
>
> On 2023/8/31 10:12, Lehua Ding wrote:
> > Committed to the trunk and backported to GCC 13 one week later.
> > Thanks Juzhe and Kito.
> >
> > On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
> >> OK for gcc 13 branch too, the general rule for backport is to wait one
> >> week on trunk to make sure the fix is stable.
> >>
> >>
> >> On Thu, Aug 31, 2023 at 8:08 AM juzhe.zh...@rivai.ai
> >>  wrote:
> >>>
> >>> Ok for trunk. But not sure whether it's ok for GCC-13.
> >>>
> >>>
> >>>
> >>> juzhe.zh...@rivai.ai
> >>>
> >>> From: Lehua Ding
> >>> Date: 2023-08-30 17:51
> >>> To: gcc-patches
> >>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
> >>> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
> >>> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
> >>> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
> >>>
> >>> PR target/111234
> >>>
> >>> gcc/ChangeLog:
> >>>
> >>> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
> >>>
> >>> gcc/testsuite/ChangeLog:
> >>>
> >>> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
> >>>
> >>> ---
> >>> gcc/config/riscv/riscv-vsetvl.cc  |  2 +-
> >>> .../gcc.target/riscv/rvv/vsetvl/pr111234.c| 19 +++
> >>> 2 files changed, 20 insertions(+), 1 deletion(-)
> >>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>>
> >>> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> >>> b/gcc/config/riscv/riscv-vsetvl.cc
> >>> index 1386d9250ca..a81bb53a521 100644
> >>> --- a/gcc/config/riscv/riscv-vsetvl.cc
> >>> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> >>> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const
> >>> vector_insn_info ,
> >>>   new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
> >>> else
> >>>   {
> >>> -  if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
> >>> +  if (vsetvl_insn_p (rinsn))
> >>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
> >>> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
> >>> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
> >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> new file mode 100644
> >>> index 000..ee5eec4a257
> >>> --- /dev/null
> >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> @@ -0,0 +1,19 @@
> >>> +/* { dg-do compile } */
> >>> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> >>> +
> >>> +#include 
> >>> +
> >>> +void
> >>> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
> >>> +{
> >>> +  vint32m1_t va = *in;
> >>> +  vbool32_t mask = *m;
> >>> +  vint64m2_t vb
> >>> += __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2
> >>> ());
> >>> +  vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> +  if (b != 0)
> >>> +vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> +  *out = vc;
> >>> +}
> >>> --
> >>> 2.36.3
> >>>
> >
>
> --
> Best,
> Lehua
>

Re: [PATCH] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC]

[Kito Cheng via Gcc-patches]

LGTM :)

On Mon, Sep 18, 2023 at 3:07 PM Juzhe-Zhong  wrote:
>
> We have largely supportted VLS modes. Only move patterns of VLS modes are
> different from VLS patterns. The rest of them are the same.
>
> We always extend the current VLA patterns with VLSmodes:
>
> VI --> V_VLSI
> VF --> V_VLSF
>
> It makes no sense to have a separate file holding a very few VLS patterns
> that can not be extended from the current VLA patterns.
>
> So remove autovec-vls.md
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md (mov): New pattern.
> (*mov_mem_to_mem): Ditto.
> (*mov): Ditto.
> (@mov_lra): Ditto.
> (*mov_lra): Ditto.
> (*mov_vls): Ditto.
> (movmisalign): Ditto.
> (@vec_duplicate): Ditto.
> * config/riscv/autovec-vls.md: Removed.
>
> ---
>  gcc/config/riscv/autovec-vls.md | 196 
>  gcc/config/riscv/vector.md  | 172 +++-
>  2 files changed, 170 insertions(+), 198 deletions(-)
>  delete mode 100644 gcc/config/riscv/autovec-vls.md
>
> diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> deleted file mode 100644
> index 3488f452e5d..000
> --- a/gcc/config/riscv/autovec-vls.md
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -;; Machine description for VLS of RVV auto-vectorization.
> -;; Copyright (C) 2023 Free Software Foundation, Inc.
> -;; Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
> -
> -;; This file is part of GCC.
> -
> -;; GCC is free software; you can redistribute it and/or modify
> -;; it under the terms of the GNU General Public License as published by
> -;; the Free Software Foundation; either version 3, or (at your option)
> -;; any later version.
> -
> -;; GCC is distributed in the hope that it will be useful,
> -;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -;; GNU General Public License for more details.
> -
> -;; You should have received a copy of the GNU General Public License
> -;; along with GCC; see the file COPYING3.  If not see
> -;; .
> -
> -;; We define VLS modes as 'define_insn_and_split' with normal
> -;; RTX_CODE operation, so we can gain benefits from Combine optimizations.
> -
> -;; -
> -;;  Moves Operations
> -;; -
> -
> -(define_expand "mov"
> -  [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
> -   (match_operand:VLS_AVL_IMM 1 "general_operand"))]
> -  "TARGET_VECTOR"
> -{
> -  if (riscv_vector::legitimize_move (operands[0], operands[1]))
> -DONE;
> -})
> -
> -(define_insn_and_split "*mov_mem_to_mem"
> -  [(set (match_operand:VLS_AVL_IMM 0 "memory_operand")
> -   (match_operand:VLS_AVL_IMM 1 "memory_operand"))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -  {
> -if (GET_MODE_BITSIZE (mode).to_constant () <= MAX_BITS_PER_WORD)
> -  {
> -/* Opitmize the following case:
> -
> -   typedef int8_t v2qi __attribute__ ((vector_size (2)));
> -   v2qi v = *(v2qi*)in;
> -   *(v2qi*)out = v;
> -
> -   We prefer scalar load/store instead of vle.v/vse.v when
> -   the VLS modes size is smaller scalar mode.  */
> -machine_mode mode;
> -unsigned size = GET_MODE_BITSIZE (mode).to_constant ();
> -if (FLOAT_MODE_P (mode))
> - mode = mode_for_size (size, MODE_FLOAT, 0).require ();
> -else
> - mode = mode_for_size (size, MODE_INT, 0).require ();
> -emit_move_insn (gen_lowpart (mode, operands[0]),
> -   gen_lowpart (mode, operands[1]));
> -  }
> -else
> -  {
> -   operands[1] = force_reg (mode, operands[1]);
> -   emit_move_insn (operands[0], operands[1]);
> -  }
> -DONE;
> -  }
> -  [(set_attr "type" "vmov")]
> -)
> -
> -(define_insn_and_split "*mov"
> -  [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> -   (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" "  m,vr, vr"))]
> -  "TARGET_VECTOR
> -   && (register_operand (operands[0], mode)
> -   || register_operand (operands[1], mode))"
> -  "@
> -   #
> -   #
> -   vmv%m1r.v\t%0,%1"
> -  "&& reload_completed
> -   && (!register_operand (operands[0], mode)
> -   || !register_operand (operands[1], mode))"
> -  [(const_int 0)]
> -  {
> -bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
> -gcc_assert (ok_p);
> -DONE;
> -  }
> -  [(set_attr "type" "vmov")]
> -)
> -
> -(define_expand "mov"
> -  [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
> -   (match_operand:VLS_AVL_REG 1 "general_operand"))]
> -  "TARGET_VECTOR"
> -{
> -  bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
> -  gcc_assert (ok_p);
> -  DONE;

Re: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]

[Kito Cheng via Gcc-patches]

I think it's not make too much sense to back port GCC14's change to
GCC 13, removing phase 6 optimization is reasonable to me, so  LGTM :)

On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai
 wrote:
>
> Thanks for fixing it.
> I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 
> kito has refactored it) there.
> But I think we need kito's more comments about that.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Li Xu
> Date: 2023-09-18 12:19
> To: gcc-patches
> CC: kito.cheng; palmer; juzhe.zhong; xuli
> Subject: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]
> From: xuli 
>
> vsetvl pass has been refactored in gcc14, and the optimization
> is more reasonable than releases/gcc-13. This problem does not
> exist in gcc14.
>
> Phase 6 of gcc13 is an optimization patch. Due to lack of consideration,
> there will be some hidden bugs, so we decided to remove phase 6.
> Although the generated code will be redundant, the program is correct.
>
> PR target/111412
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (vector_infos_manager::release): 
> Remove.
> (pass_vsetvl::refine_vsetvls): Ditto.
> (pass_vsetvl::cleanup_vsetvls): Ditto.
> (pass_vsetvl::propagate_avl): Ditto.
> (pass_vsetvl::lazy_vsetvl): Ditto.
> * config/riscv/riscv-vsetvl.h: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Adjust case.
> * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto.
> * gcc.target/riscv/rvv/base/pr111412.c: New test.
> ---
> gcc/config/riscv/riscv-vsetvl.cc  | 153 +-
> gcc/config/riscv/riscv-vsetvl.h   |   2 -
> .../gcc.target/riscv/rvv/base/pr111412.c  |  41 +
> .../riscv/rvv/vsetvl/avl_single-79.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-80.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-86.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-87.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-88.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-89.c  |   4 +-
> .../riscv/rvv/vsetvl/avl_single-90.c  |   4 +-
> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c |  10 +-
> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c |  10 +-
> .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c  |   6 +-
> .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c  |   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c|   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c|   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c|   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c|   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c|   2 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c |   4 +-
> .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c |   4 +-
> 21 files changed, 80 insertions(+), 190 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111412.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 0cf4bc818e2..9dca2ce709d 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2494,8 +2494,6 @@ vector_infos_manager::release (void)
>if (!vector_exprs.is_empty ())
>  vector_exprs.release ();
> -  gcc_assert (to_refine_vsetvls.is_empty ());
> -  gcc_assert (to_delete_vsetvls.is_empty ());
>if (optimize > 0)
>  free_bitmap_vectors ();
> }
> @@ -2702,9 +2700,6 @@ private:
>/* Phase 5.  */
>void cleanup_insns (void) const;
> -  /* Phase 6.  */
> -  void propagate_avl (void) const;
> -
>void init (void);
>void done (void);
>void compute_probabilities (void);
> @@ -3823,10 +3818,8 @@ pass_vsetvl::refine_vsetvls (void) const
>/* We can't refine user vsetvl into vsetvl zero,zero since the dest
> will be used by the following instructions.  */
>if (vector_config_insn_p (rinsn))
> - {
> -   m_vector_manager->to_refine_vsetvls.add (rinsn);
>   continue;
> - 

Re: [PATCH v1] RISC-V: Support VLS mode for vec_set

[Kito Cheng via Gcc-patches]

LGTM

On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to add the VLS support vec_set, both INT
> and FP are included.
>
> Give sample code as below:
>
> typedef long long vl_t \
>   __attribute__((vector_size(2 * sizeof (long long;
>
> vl_t init_vl (vl_t v, unsigned index, unsigned value)
> {
>   v[index] = value;
>
>   return v;
> }
>
> Before this patch:
> init_vl:
>   addi sp,sp,-16
>   vsetivli zero,2,e64,m1,ta,ma
>   vle64.v  v1,0(a1)
>   vse64.v  v1,0(sp)
>   slli a4,a2,32
>   srli a2,a4,29
>   add  a2,sp,a2
>   slli a3,a3,32
>   srli a3,a3,32
>   sd   a3,0(a2)
>   vle64.v  v1,0(sp)
>   vse64.v  v1,0(a0)
>   addi sp,sp,16
>   jr   ra
>
> After this patch:
> init_vl:
>   vsetivlizero,2,e64,m1,ta,ma
>   vle64.v v1,0(a1)
>   sllia3,a3,32
>   srlia3,a3,32
>   addia5,a2,1
>   vsetvli zero,a5,e64,m1,tu,ma
>   vmv.v.x v2,a3
>   vslideup.vx v1,v2,a2
>   vsetivlizero,2,e64,m1,ta,ma
>   vse64.v v1,0(a0)
>   ret
>
> Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend to vls mode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/autovec.md   |  4 +--
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-10.c| 31 
>  .../riscv/rvv/autovec/vls/vec-set-11.c| 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-12.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-13.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-14.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-15.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-16.c| 21 +++
>  .../riscv/rvv/autovec/vls/vec-set-17.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-18.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-19.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-2.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-20.c| 20 +++
>  .../riscv/rvv/autovec/vls/vec-set-21.c| 19 ++
>  .../riscv/rvv/autovec/vls/vec-set-22.c| 18 ++
>  .../riscv/rvv/autovec/vls/vec-set-3.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++
>  .../riscv/rvv/autovec/vls/vec-set-6.c | 33 +
>  .../riscv/rvv/autovec/vls/vec-set-7.c | 31 
>  .../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++
>  .../riscv/rvv/autovec/vls/vec-set-9.c | 33 +
>  24 files changed, 582 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
>  create mode 100644 
> 

Re: [PATCH] [RISC-V] fix PR 111259 invalid zcmp mov predicate.

[Kito Cheng via Gcc-patches]

I guess another solution is using reg_or_subregno instead of REGNO, but
that should not catch more cases, and just more run-time check, so this
version is LGTM.

Re: [PATCH] RISC-V: Refactor expand_reduction and cleanup enum reduction_type

[Kito Cheng via Gcc-patches]

LGTM

On Fri, Sep 15, 2023 at 1:06 PM Lehua Ding  wrote:

> This patch refactors expand_reduction, remove the reduction_type argument
> and add insn_flags argument to determine the passing of the operands.
> ops has also been modified to restrict it to only two cases and to remove
> operand that are not in use.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Adjust.
> * config/riscv/autovec.md: Ditto.
> * config/riscv/riscv-protos.h (enum class): Delete enum
> reduction_type.
> (expand_reduction): Adjust expand_reduction prototype.
> * config/riscv/riscv-v.cc (need_mask_operand_p): New helper
> function.
> (expand_reduction): Refactor expand_reduction.
>
> ---
>  gcc/config/riscv/autovec-opt.md | 22 +++-
>  gcc/config/riscv/autovec.md | 51 ++--
>  gcc/config/riscv/riscv-protos.h |  9 +
>  gcc/config/riscv/riscv-v.cc | 60 +
>  4 files changed, 79 insertions(+), 63 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index df516849527..b47bae16193 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -1208,7 +1208,8 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (, operands,
> +  riscv_vector::expand_reduction (,
> riscv_vector::REDUCE_OP,
> +  operands,
>CONST0_RTX (mode));
>DONE;
>  }
> @@ -1226,7 +1227,9 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED,
> +  riscv_vector::REDUCE_OP_FRM_DYN,
> +  operands,
>CONST0_RTX (mode));
>DONE;
>  }
> @@ -1245,9 +1248,9 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> - operands[1],
> - riscv_vector::reduction_type::FOLD_LEFT);
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> +  riscv_vector::REDUCE_OP_FRM_DYN,
> +  operands, operands[1]);
>DONE;
>  }
>  [(set_attr "type" "vector")])
> @@ -1271,9 +1274,12 @@
>if (rtx_equal_p (operands[4], const0_rtx))
>  emit_move_insn (operands[0], operands[1]);
>else
> -riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> -   operands[1],
> -
>  riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
> +{
> +  rtx ops[] = {operands[0], operands[2], operands[3], operands[4]};
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED,
> +  riscv_vector::REDUCE_OP_M_FRM_DYN,
> +  ops, operands[1]);
> +}
>DONE;
>  }
>  [(set_attr "type" "vector")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 8537b9d41f6..c6175a3b1f6 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2096,7 +2096,8 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX
> (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM,
> riscv_vector::REDUCE_OP,
> +  operands, CONST0_RTX (mode));
>DONE;
>  }
>  [(set_attr "type" "vector")])
> @@ -2108,7 +2109,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX,
> riscv_vector::REDUCE_OP,
> +  operands, min);
>DONE;
>  })
>
> @@ -2117,7 +2119,8 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
>  {
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX
> (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU,
> riscv_vector::REDUCE_OP,
> +  operands, CONST0_RTX (mode));
>DONE;
>  })
>
> @@ -2128,7 +2131,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN,
> riscv_vector::REDUCE_OP,
> +  operands, max);
>DONE;
>  })
>
> @@ -2139,7 +2143,8 @@
>  {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED),
> mode);
> -  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU,
> 

Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

I am thinking what we are doing is something like we are allowing
scalar mode within the vector register, so...not sure should we try to
implement that within the mov pattern?

I guess we need some inputs from Jeff.


e.g.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0ecda795b38..ffced41588d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7621,6 +7621,9 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
}
  else if (V_REG_P (regno))
{
+  if (mode is scalar)
+   return true;
+
  if (!riscv_v_ext_mode_p (mode))
   return false;

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6d6a2b3748c..50bac39f125 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2035,8 +2035,8 @@ (define_insn "*movdi_32bit"
   (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])

(define_insn "*movdi_64bit"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,
*f,*f,*r,*f,*m,r")
-   (match_operand:DI 1 "move_operand" "
r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,
*f,*f,*r,*f,*m,r,*vr,*r,*vr,*vr,*m")
+   (match_operand:DI 1 "move_operand" "
r,T,m,rJ,*r*J,*m,*f,*f,*f,vp,vr,vr,r,m,vr"))]
  "TARGET_64BIT
   && (register_operand (operands[0], DImode)
   || reg_or_0_operand (operands[1], DImode))"

Re: [PATCH] RISC-V: Support combine extend and reduce sum to widen reduce sum

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Sep 14, 2023 at 11:51 PM Lehua Ding  wrote:
>
> This patch add combine pattern to combine extend and reduce sum
> to widen reduce sum. The pattern in autovec.md was adjusted as
> needed. Note that the current vectorization cannot generate reduce
> openrand which is LMUL=M8, because this means that we need an LMUL=M16
> for the extended openrand, which is currently not possible. So I've
> added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude
> mode which is LMUL=M8.
>
> PR target/111381
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*reduc_plus_scal_):
> New combine pattern.
> (*fold_left_widen_plus_): Ditto.
> (*mask_len_fold_left_widen_plus_): Ditto.
> * config/riscv/autovec.md (reduc_plus_scal_):
> Change from define_expand to define_insn_and_split.
> (fold_left_plus_): Ditto.
> (mask_len_fold_left_plus_): Ditto.
> * config/riscv/riscv-v.cc (expand_reduction):
> Support widen reduction.
> * config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM):
> Add new iterators and attrs.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 82 +++
>  gcc/config/riscv/autovec.md   | 74 +++--
>  gcc/config/riscv/riscv-v.cc   |  7 +-
>  gcc/config/riscv/vector-iterators.md  | 51 
>  .../riscv/rvv/autovec/widen/widen_reduc-1.c   | 27 ++
>  .../rvv/autovec/widen/widen_reduc_order-1.c   | 20 +
>  .../rvv/autovec/widen/widen_reduc_order-2.c   | 19 +
>  .../autovec/widen/widen_reduc_order_run-1.c   | 24 ++
>  .../autovec/widen/widen_reduc_order_run-2.c   | 22 +
>  .../rvv/autovec/widen/widen_reduc_run-1.c | 22 +
>  10 files changed, 321 insertions(+), 27 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 22ab8afc994..df516849527 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -1196,6 +1196,88 @@
>  }
>  [(set_attr "type" "vfwmul")])
>
> +;; Combine extend + vredsum to vwredsum[u]
> +(define_insn_and_split "*reduc_plus_scal_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (any_extend:
> +(match_operand:VI_QHS_NO_M8 1 "register_operand"))
> +] UNSPEC_REDUC_SUM))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (, operands,
> +  CONST0_RTX (mode));
> +  DONE;
> +}
> +[(set_attr "type" "vector")])
> +
> +;; Combine extend + vfredusum to vfwredusum
> +(define_insn_and_split "*reduc_plus_scal_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (float_extend:
> +(match_operand:VF_HS_NO_M8 1 "register_operand"))
> +] UNSPEC_REDUC_SUM_UNORDERED))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
> +  CONST0_RTX (mode));
> +  DONE;
> +}
> +[(set_attr "type" "vector")])
> +
> +;; Combine extend + vfredosum to vfwredosum
> +(define_insn_and_split "*fold_left_widen_plus_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (float_extend:
> +(match_operand:VF_HS_NO_M8 2 "register_operand"))
> +  (match_operand: 1 "register_operand")
> +] UNSPEC_REDUC_SUM_ORDERED))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> + operands[1],
> + riscv_vector::reduction_type::FOLD_LEFT);
> +  DONE;
> +}
> +[(set_attr "type" 

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

[Kito Cheng via Gcc-patches]

LGTM too :)

On Thu, Sep 14, 2023 at 10:11 PM 钟居哲  wrote:
>
> LGTM.
> It's obvious you fixed my previous redundant codes.
> Thanks.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date: 2023-09-13 20:31
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
> Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
> This patch adjust reduction patterns struct, change it from:
>(any_reduc:VI
>  (vec_duplicate:VI
>(vec_select:
>  (match_operand: 4 "register_operand"  "   vr,   
> vr")
>  (parallel [(const_int 0)])))
>  (match_operand:VI   3 "register_operand"  "   vr,   
> vr"))
> to:
>(unspec: [
>  (match_operand:VI3 "register_operand"  "   vr,   
> vr")
>  (match_operand: 4 "register_operand"  "   vr,   
> vr")
>] ANY_REDUC)
>
> The reason for the change is that the semantics of the previous pattern is 
> incorrect.
> GCC does not have a standard rtx code to express the reduction calculation 
> process.
> It makes more sense to use UNSPEC.
>
> Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred 
> (unspec, mode)),
> so that all reduction patterns can have a uniform icode name. After this 
> adjust, widen_reducop
> and widen_freducop are redundant.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Change rtx code to unspec.
> * config/riscv/riscv-protos.h (expand_reduction): Change prototype.
> * config/riscv/riscv-v.cc (expand_reduction): Change prototype.
> * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
> Removed.
> (class widen_freducop): Removed.
> * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
> * config/riscv/vector.md (@pred_reduc_): Change name.
> (@pred_): New name.
> (@pred_widen_reduc_plus): Change name.
> (@pred_reduc_plus): Change name.
> (@pred_widen_reduc_plus): Change name.
>
> ---
> gcc/config/riscv/autovec.md   |  27 ++--
> gcc/config/riscv/riscv-protos.h   |   2 +-
> gcc/config/riscv/riscv-v.cc   |  13 +-
> .../riscv/riscv-vector-builtins-bases.cc  |  82 
> gcc/config/riscv/vector-iterators.md  |  62 +++--
> gcc/config/riscv/vector.md| 118 +-
> 6 files changed, 152 insertions(+), 152 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4a6b8f8c939..16ac125f53f 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2091,7 +2091,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2102,7 +2102,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode);
> -  riscv_vector::expand_reduction (SMAX, operands, min);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
>DONE;
> })
> @@ -2111,7 +2111,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2122,7 +2122,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode);
> -  riscv_vector::expand_reduction (SMIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
>DONE;
> })
> @@ -2133,7 +2133,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode);
> -  riscv_vector::expand_reduction (UMIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
>DONE;
> })
> @@ -2142,7 +2142,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX 
> (mode));
>DONE;
> })
> @@ -2151,7 +2151,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2160,7 +2160,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2178,7 +2178,8 @@
> (match_operand:VF 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  

Re: [PATCH] RISC-V: Support VLS modes mask operations

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月14日 週四 20:44 寫道：

> This patch support mask operations (comparison and logical).
>
> This patch reduce these FAILs of "vect" testsuite:
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{
> 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 1, 65535 }"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\s*.+{
> 255, 15, 1, 65535 }"
>
> Full regression passed (with reducing 4 FAILs).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add VLS mask modes.
> * config/riscv/autovec.md (@vcond_mask_): Remove @.
> (vcond_mask_): Add VLS mask modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS tests.
> * gcc.target/riscv/rvv/autovec/vls/cmp-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-3.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   |  18 +--
>  gcc/config/riscv/autovec.md   |  32 +++---
>  gcc/config/riscv/vector.md|  60 +-
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/def.h|   9 ++
>  .../gcc.target/riscv/rvv/autovec/vls/mask-1.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-2.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-3.c |  69 
>  13 files changed, 907 insertions(+), 55 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index e26c01856ff..22ab8afc994 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -67,10 +67,10 @@
>  ;;
> -
>
>  (define_insn_and_split "*not"
> -  [(set (match_operand:VB 0 "register_operand"   "=vr")
> -   (bitmanip_bitwise:VB
> - (not:VB (match_operand:VB 2 "register_operand" " vr"))
> - (match_operand:VB 1 "register_operand" " vr")))]
> +  [(set (match_operand:VB_VLS 0 "register_operand"   "=vr")
> +   (bitmanip_bitwise:VB_VLS
> + (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr"))
> + (match_operand:VB_VLS 1 "register_operand" " vr")))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -93,11 +93,11 @@
>  ;;
> -
>
>  (define_insn_and_split "*n"
> -  [(set (match_operand:VB 0 "register_operand" "=vr")
> -   (not:VB
> - (any_bitwise:VB
> -   (match_operand:VB 1 "register_operand" " vr")
> -   (match_operand:VB 2 "register_operand" " vr"]
> +  [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
> +   (not:VB_VLS
> + (any_bitwise:VB_VLS
> +   (match_operand:VB_VLS 1 "register_operand" " vr")
> +   (match_operand:VB_VLS 2 "register_operand" " vr"]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 7121bab1716..d2002a8ee26 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -495,9 +495,9 @@
>  ;;
> 

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x


On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
 wrote:
>
> You mean try pr111391.c
> that I added with rv64gcv_zve32x ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 17:20
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
> Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> move[PR111391]
> Could you check if it work correctly for rv64gcv_zve32x? add testcase
> no matter if it works or not :)
>
> On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
>  wrote:
> >
> > Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> > vec_extract optab ?
> >
> >
> >
> > juzhe.zh...@rivai.ai
> >
> > From: Kito Cheng
> > Date: 2023-09-14 16:11
> > To: Juzhe-Zhong
> > CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> > Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> > move[PR111391]
> > On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> > >
> > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> > >
> > > I notice that previous patch (V2 patch) cause additional execution fail 
> > > of pr69719.c
> > > This FAIL is because of the latent BUG of VSETVL PASS.
> > >
> > > So this patch includes VSETVL PASS fix even though it's not related to 
> > > the PR111391.
> > >
> > > I have confirm the whole regression no additional FAILs are introduced.
> > >
> > > PR target/111391
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/autovec.md (@vec_extract): Remove @.
> > > (vec_extract): Ditto.
> > > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> > >
> > > ---
> > >  gcc/config/riscv/autovec.md   |  2 +-
> > >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> > >  gcc/config/riscv/riscv.cc | 32 +++
> > >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> > >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> > >  5 files changed, 64 insertions(+), 3 deletions(-)
> > >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> > >
> > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > > index e74a1695709..7121bab1716 100644
> > > --- a/gcc/config/riscv/autovec.md
> > > +++ b/gcc/config/riscv/autovec.md
> > > @@ -1442,7 +1442,7 @@
> > >  ;; 
> > > -
> > >  ;;  [INT,FP] Extract a vector element.
> > >  ;; 
> > > -
> > > -(define_expand "@vec_extract"
> > > +(define_expand "vec_extract"
> >
> > Why remove this? I saw this change was introduced in v3?
> >
> >
> > >[(set (match_operand: 0 "register_operand")
> > >   (vec_select:
> > > (match_operand:V_VLS  1 "register_operand")
> >
>

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)

On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
 wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 16:11
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> >
> > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> >
> > I notice that previous patch (V2 patch) cause additional execution fail of 
> > pr69719.c
> > This FAIL is because of the latent BUG of VSETVL PASS.
> >
> > So this patch includes VSETVL PASS fix even though it's not related to the 
> > PR111391.
> >
> > I have confirm the whole regression no additional FAILs are introduced.
> >
> > PR target/111391
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md (@vec_extract): Remove @.
> > (vec_extract): Ditto.
> > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> >
> > ---
> >  gcc/config/riscv/autovec.md   |  2 +-
> >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> >  gcc/config/riscv/riscv.cc | 32 +++
> >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> >  5 files changed, 64 insertions(+), 3 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> >
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index e74a1695709..7121bab1716 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1442,7 +1442,7 @@
> >  ;; 
> > -
> >  ;;  [INT,FP] Extract a vector element.
> >  ;; 
> > -
> > -(define_expand "@vec_extract"
> > +(define_expand "vec_extract"
>
> Why remove this? I saw this change was introduced in v3?
>
>
> >[(set (match_operand: 0 "register_operand")
> >   (vec_select:
> > (match_operand:V_VLS  1 "register_operand")
>

Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of 
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch includes VSETVL PASS fix even though it's not related to the 
> PR111391.
>
> I have confirm the whole regression no additional FAILs are introduced.
>
> PR target/111391
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (@vec_extract): Remove @.
> (vec_extract): Ditto.
> * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
>  gcc/config/riscv/riscv.cc | 32 +++
>  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
>  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
>  5 files changed, 64 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e74a1695709..7121bab1716 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1442,7 +1442,7 @@
>  ;; -
>  ;;  [INT,FP] Extract a vector element.
>  ;; -
> -(define_expand "@vec_extract"
> +(define_expand "vec_extract"

Why remove this? I saw this change was introduced in v3?


>[(set (match_operand: 0 "register_operand")
>   (vec_select:
> (match_operand:V_VLS  1 "register_operand")

Re: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

[Kito Cheng via Gcc-patches]

lgtm

On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong  wrote:
>
> update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
>
> This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE
>
> update v2 -> v3: Remove redundant format.
>
> PR target/111395
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
> (vector_insn_info::global_merge): Ditto.
> (vector_insn_info::get_avl_or_vl_reg): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
> * gcc.target/riscv/rvv/rvv-fortran.exp: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 28 +++-
>  .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +
>  .../gcc.target/riscv/rvv/rvv-fortran.exp  | 45 +++
>  3 files changed, 103 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index f81361c4ccd..8ec54092a48 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info ) const
>/* Handle VLMAX AVL.  */
>if (vlmax_avl_p (m_value))
>  return vlmax_avl_p (other.get_value ());
> +  if (vlmax_avl_p (other.get_value ()))
> +return false;
>
>/* If any source is undef value, we think they are not equal.  */
>if (!m_source || !other.get_source ())
> @@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info 
> _info,
> new_info.set_avl_source (first_set);
>  }
>
> +  /* Make sure VLMAX AVL always has a set_info the get VL.  */
> +  if (vlmax_avl_p (new_info.get_avl ()))
> +{
> +  if (this->get_avl_source ())
> +   new_info.set_avl_source (this->get_avl_source ());
> +  else
> +   {
> + gcc_assert (merge_info.get_avl_source ());
> + new_info.set_avl_source (merge_info.get_avl_source ());
> +   }
> +}
> +
>new_info.fuse_sew_lmul (*this, merge_info);
>new_info.fuse_tail_policy (*this, merge_info);
>new_info.fuse_mask_policy (*this, merge_info);
> @@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (get_avl_source ())
> -return get_avl_reg_rtx ();
> -
>rtx_insn *rinsn = get_insn ()->rtl ();
>if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
>  {
> @@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const
> return vl;
>  }
>
> -  /* A DIRTY (polluted EMPTY) block if:
> -   - get_insn is scalar move (no AVL or VL operand).
> -   - get_avl_source is null (no def in the current DIRTY block).
> - Then we trace the previous insn which must be the insn
> - already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
> -  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
> -  return ::get_vl (prev_rinsn);
> +  /* We always has avl_source if it is VLMAX AVL.  */
> +  gcc_assert (get_avl_source ());
> +  return get_avl_reg_rtx ();
>  }
>
>  bool
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 
> b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> new file mode 100644
> index 000..71253fe6bc5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> @@ -0,0 +1,41 @@
> +! { dg-do compile }
> +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
> +
> +MODULE a
> +  REAL b
> +CONTAINS
> +  SUBROUTINE c(d,KTE)
> +REAL,DIMENSION(KTE) :: d,e,f,g
> +REAL,DIMENSION(KTE) :: h
> +i : DO j=1,b
> +   z=k
> +   DO l=m,n
> +  IF(o>=p)THEN
> + IF(l +q=z/0
> + ENDIF
> + e=q
> + f=EXP(r)
> +  ENDIF
> +   ENDDO
> +   s : DO t=1,2
> +  DO l=m,u
> + v=v+l
> +  ENDDO
> +  IF(w<=x)THEN
> + DO l=w,x
> +g=y
> + ENDDO
> +  ENDIF
> +   ENDDO  s
> +   aa=v
> +   ab=ac/aa
> +   k=ad/ab
> +ENDDO  i
> +IF(ae>af)THEN
> +   DO l=m,n
> +  d=h
> +   ENDDO
> +ENDIF
> +  END SUBROUTINE c
> +END MODULE a
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp 
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
> new file mode 100644
> index 000..88d82281d43
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
> @@ -0,0 +1,45 @@
> +#   Copyright (C) 2023-2023 Free Software Foundation, Inc.
> +
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# 

Re: [PATCH V2] RISC-V: Fix ICE in get_avl_or_vl_reg

[Kito Cheng via Gcc-patches]

LGTM with a minor comment.

> @@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const 
> bb_info *bb) const
>  }
>
>/* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  
> */
> -  auto_vec pred_cfg_bbs = get_dominated_by 
> (CDI_POST_DOMINATORS, cfg_bb);
> +  auto_vec pred_cfg_bbs
> += get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);

This change seems like a format fixing? If so plz split it into a
separate patch and apply clang-format to riscv-vsetvl.cc?
pre-approved for that reformat patch

>FOR_EACH_EDGE (e, ei, cfg_bb->preds)
>  {
>sbitmap avout = m_vector_manager->vector_avout[e->src->index];

Re: [PATCH] RISC-V: Support cond vmulh.vv and vmulu.vv

[Kito Cheng via Gcc-patches]

LGTM, thanks :)

On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding  wrote:
>
> This patch adds combine patterns to combine vmulh[u].vv + vcond_mask
> to mask vmulh[u].vv. For vmulsu.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*cond_3_highpart):
> New combine pattern.
> * config/riscv/autovec.md (smul3_highpart): Mrege smul and umul.
> (3_highpart): Merged pattern.
> (umul3_highpart): Mrege smul and umul.
> * config/riscv/vector-iterators.md (umul): New iterators.
> (UNSPEC_VMULHU): New iterators.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 23 -
>  gcc/config/riscv/autovec.md   | 22 ++--
>  gcc/config/riscv/vector-iterators.md  |  4 +++
>  .../riscv/rvv/autovec/cond/cond_mulh-1.c  | 29 
>  .../riscv/rvv/autovec/cond/cond_mulh-2.c  | 30 
>  .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  | 32 +
>  .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  | 34 +++
>  7 files changed, 154 insertions(+), 20 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 0d2721f0b29..552be48bf73 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -970,6 +970,28 @@
>  }
>   [(set_attr "type" "vnshift")])
>
> +;; Combine vmulh.vv/vmulhu.vv + vcond_mask
> +(define_insn_and_split "*cond_3_highpart"
> +   [(set (match_operand:VFULLI 0 "register_operand")
> +(if_then_else:VFULLI
> +  (match_operand: 1 "register_operand")
> +  (mulh:VFULLI
> +(match_operand:VFULLI 2 "register_operand")
> +(match_operand:VFULLI 3 "register_operand"))
> +  (match_operand:VFULLI 4 "register_operand")))]
> +   "TARGET_VECTOR && can_create_pseudo_p ()"
> +   "#"
> +   "&& 1"
> +   [(const_int 0)]
> +{
> +  insn_code icode = code_for_pred_mulh (, mode);
> +  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[4],
> +   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
> +  riscv_vector::expand_cond_len_binop (icode, ops);
> +   DONE;
> +}
> +[(set_attr "type" "vector")])
> +
>  ;; 
> =
>  ;; Combine extend + binop to widen_binop
>  ;; 
> =
> @@ -1172,7 +1194,6 @@
>  }
>  [(set_attr "type" "vfwmul")])
>
> -
>  ;; 
> =
>  ;; Misc combine patterns
>  ;; 
> =
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e9dd40af935..b4ac22bb97b 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1569,9 +1569,9 @@
>  ;; - vmulhu.vv
>  ;; -
>
> -(define_insn_and_split "smul3_highpart"
> +(define_insn_and_split "3_highpart"
>[(set (match_operand:VFULLI 0 "register_operand")
> -(smul_highpart:VFULLI
> +(mulh:VFULLI
>(match_operand:VFULLI 1 "register_operand")
>(match_operand:VFULLI 2 "register_operand")))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
> @@ -1579,23 +1579,7 @@
>"&& 1"
>[(const_int 0)]
>  {
> -  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, mode);
> -  riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
> -  DONE;
> -}
> -[(set_attr "type" "vimul")])
> -
> -(define_insn_and_split "umul3_highpart"
> -  [(set (match_operand:VFULLI 0 "register_operand")
> -(umul_highpart:VFULLI
> -  (match_operand:VFULLI 1 "register_operand")
> -  (match_operand:VFULLI 2 "register_operand")))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -{
> -  insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, mode);
> +  insn_code icode = code_for_pred_mulh (, mode);
>riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
>DONE;
>  }
> diff --git a/gcc/config/riscv/vector-iterators.md 
> 

Re: [PATCH] RISC-V: Support cond vfsgnj.vv autovec pattern

[Kito Cheng via Gcc-patches]

LGTM

On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding  wrote:
>
> This patch add combine patterns to combine vfsgnj.vv + vcond_mask
> to mask vfsgnj.vv. For vfsgnjx.vv, it can not be produced in midend
> currently. We will send another patch to take this issue.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*copysign_neg): Move.
> (*cond_copysign): New combine pattern.
> * config/riscv/riscv-v.cc (needs_fp_rounding): Extend.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_copysign-template.h: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: New 
> test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 68 +
>  gcc/config/riscv/riscv-v.cc   |  4 +-
>  .../rvv/autovec/cond/cond_copysign-run.c  | 99 +++
>  .../rvv/autovec/cond/cond_copysign-rv32gcv.c  | 12 +++
>  .../rvv/autovec/cond/cond_copysign-rv64gcv.c  | 12 +++
>  .../rvv/autovec/cond/cond_copysign-template.h | 81 +++
>  .../rvv/autovec/cond/cond_copysign-zvfh-run.c | 93 +
>  7 files changed, 349 insertions(+), 20 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-template.h
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 58e80044f1e..f759525f96b 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -609,6 +609,10 @@
> (set_attr "mode" "")
> (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> +;; 
> =
> +;; Combine op + vmerge to cond_op
> +;; 
> =
> +
>  ;; Combine  and vcond_mask generated by midend into cond_len_
>  ;; Currently supported operations:
>  ;;   abs(FP)
> @@ -651,25 +655,6 @@
>DONE;
>  })
>
> -;; Combine vlmax neg and UNSPEC_VCOPYSIGN
> -(define_insn_and_split "*copysign_neg"
> -  [(set (match_operand:VF 0 "register_operand")
> -(neg:VF
> -  (unspec:VF [
> -(match_operand:VF 1 "register_operand")
> -(match_operand:VF 2 "register_operand")
> -  ] UNSPEC_VCOPYSIGN)))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -{
> -  riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode),
> -  riscv_vector::BINARY_OP, operands);
> -  DONE;
> -}
> -[(set_attr "type" "vector")])
> -
>  ;; Combine sign_extend/zero_extend(vf2) and vcond_mask
>  (define_insn_and_split "*cond_"
>[(set (match_operand:VWEXTI 0 "register_operand")
> @@ -918,6 +903,27 @@
>  }
>  [(set_attr "type" "vector")])
>
> +;; Combine vfsgnj.vv + vcond_mask
> +(define_insn_and_split "*cond_copysign"
> +   [(set (match_operand:VF 0 "register_operand")
> +(if_then_else:VF
> +  (match_operand: 1 "register_operand")
> +  (unspec:VF
> +   [(match_operand:VF 2 "register_operand")
> +(match_operand:VF 3 "register_operand")] UNSPEC_VCOPYSIGN)
> +  (match_operand:VF 4 "register_operand")))]
> +   "TARGET_VECTOR && can_create_pseudo_p ()"
> +   "#"
> +   "&& 1"
> +   [(const_int 0)]
> +{
> +  insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, mode);
> +  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[4],
> +   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
> +  riscv_vector::expand_cond_len_binop (icode, ops);
> +   DONE;
> +})
> +
>  ;; 
> =
>  ;; Combine extend + binop to widen_binop
>  ;; 
> =
> @@ -1119,3 +1125,27 @@
>DONE;
>  }
>  [(set_attr "type" "vfwmul")])
> +
> +
> +;; 
> =
> +;; Misc combine patterns
> +;; 
> =
> +
> +;; Combine vlmax neg and UNSPEC_VCOPYSIGN
> +(define_insn_and_split "*copysign_neg"
> +  [(set (match_operand:VF 0 "register_operand")
> +(neg:VF
> +  (unspec:VF [
> +(match_operand:VF 1 "register_operand")
> +(match_operand:VF 2 

Re: [PATCH] RISC-V: Support cond vnsrl/vnsra

[Kito Cheng via Gcc-patches]

LGTM

On Wed, Sep 13, 2023 at 12:25 AM Lehua Ding  wrote:
>
> This patch add combine patterns to combine vnsra.w[vxi] + vcond_mask
> to a mask vnsra.w[vxi].
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md 
> (*cond_vtrunc):
> New combine pattern.
> (*cond_trunc): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: New test.
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: New 
> test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 46 +++
>  .../rvv/autovec/cond/cond_narrow_shift-1.c| 27 +++
>  .../rvv/autovec/cond/cond_narrow_shift-2.c| 30 
>  .../rvv/autovec/cond/cond_narrow_shift-3.c| 30 
>  .../autovec/cond/cond_narrow_shift_run-1.c| 29 
>  .../autovec/cond/cond_narrow_shift_run-2.c| 30 
>  .../autovec/cond/cond_narrow_shift_run-3.c| 31 +
>  7 files changed, 223 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index f759525f96b..0d2721f0b29 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -924,6 +924,52 @@
> DONE;
>  })
>
> +;; Combine vnsra + vcond_mask
> +(define_insn_and_split 
> "*cond_vtrunc"
> +  [(set (match_operand: 0 "register_operand")
> + (if_then_else:
> +   (match_operand: 1 "register_operand")
> +   (truncate:
> + (any_shiftrt:VWEXTI
> +   (match_operand:VWEXTI 2 "register_operand")
> +  (any_extend:VWEXTI
> + (match_operand: 3 "vector_shift_operand"
> +   (match_operand: 4 "register_operand")))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  insn_code icode = code_for_pred_narrow (, mode);
> +  rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[4],
> +   gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
> +  riscv_vector::expand_cond_len_binop (icode, ops);
> +  DONE;
> +}
> + [(set_attr "type" "vnshift")])
> +
> +(define_insn_and_split "*cond_trunc"
> +  [(set (match_operand: 0 "register_operand")
> + (if_then_else:
> +   (match_operand: 1 "register_operand")
> +   (truncate:
> + (any_shiftrt:VWEXTI
> +   (match_operand:VWEXTI 2 "register_operand")
> +  (match_operand: 3 "csr_operand")))
> +   (match_operand: 4 "register_operand")))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  insn_code icode = code_for_pred_narrow_scalar (, 
> mode);
> +  rtx ops[] = {operands[0], operands[1], operands[2], gen_lowpart (Pmode, 
> operands[3]),
> +   operands[4], gen_int_mode (GET_MODE_NUNITS (mode), 
> Pmode)};
> +  riscv_vector::expand_cond_len_binop (icode, ops);
> +  DONE;
> +}
> + [(set_attr "type" "vnshift")])
> +
>  ;; 
> =
>  ;; Combine extend + binop to widen_binop
>  ;; 
> =
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
> new file mode 100644
> index 000..d068110a8a8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d 
> --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
> +
> +#include 
> +
> +#define DEF_LOOP(TYPE1, TYPE2)   
>   \
> +  void __attribute__ ((noipa))   
>   \
> +  test_##TYPE1##_##TYPE2 (TYPE2 *__restrict r, TYPE2 *__restrict a,  
> \
> +   TYPE1 *__restrict b, int n)   
>  \
> +  {

Re: [PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit

[Kito Cheng via Gcc-patches]

LGTM :)

On Wed, Sep 13, 2023 at 2:07 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> When the mode switching from NONE to CALL, we will restore the
> frm but lack some check if we have static frm insn in cfun.
>
> This patch would like to fix this by adding static frm insn check.
>
> gcc/ChangeLog:
>
> * PR target/111362
> * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
>
> gcc/testsuite/ChangeLog:
>
> * PR target/111362
> * gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv.cc|  2 +-
>  .../gcc.target/riscv/rvv/base/no-honor-frm-1.c   | 12 
>  2 files changed, 13 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 9d04ddd69e0..762937b0e37 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
>rtx frm = gen_int_mode (mode, SImode);
>
>if (mode == riscv_vector::FRM_DYN_CALL
> -   && prev_mode != riscv_vector::FRM_DYN)
> +   && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
> /* No need to emit when prev mode is DYN already.  */
> emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
>else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> new file mode 100644
> index 000..b2e0f217bfa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +void foo (void) {
> +  for (unsigned i = 0; i < sizeof(foo); i++)
> +__builtin_printf("%d", i);
> +}
> +
> +/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
> +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
> +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */
> --
> 2.34.1
>

Re: [committed] RISC-V: Remove redundant ABI test

[Kito Cheng via Gcc-patches]

lgtm

On Wed, Sep 13, 2023 at 11:23 AM Juzhe-Zhong  wrote:
>
> We only support and report warning for RVV types.
>
> We don't report warning for GNU vectors.
> So this testcase checking is incorrect and the FAIL is bogus.
>
> Remove it and commit it.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vector-abi-9.c: Removed.
>
> ---
>  .../gcc.target/riscv/rvv/base/vector-abi-9.c | 16 
>  1 file changed, 16 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c
> deleted file mode 100644
> index b5f130f0caf..000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-9.c
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d 
> --param=riscv-autovec-preference=fixed-vlmax" } */
> -
> -#include "riscv_vector.h"
> -
> -typedef int v4si __attribute__ ((vector_size (16)));
> -
> -v4si
> -fun (v4si a) {  return a; }  /* { dg-warning "the vector type" } */
> -
> -void
> -bar ()
> -{
> -  v4si a;
> -  fun (a);
> -}
> --
> 2.36.3
>

Re: [PATCH] RISC-V: Add missed cond autovec testcases

[Kito Cheng via Gcc-patches]

LGTM

On Tue, Sep 12, 2023 at 4:58 PM Lehua Ding  wrote:
>
> This patch adds all missed cond autovec testcases. For not support
> cond patterns, the following patches will be sent to fix it.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Add vrem op.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c: Moved to...
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: 
> ...here.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c: Moved to...
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: 
> ...here.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c: Moved to...
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: 
> ...here.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c: Moved to...
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: 
> ...here.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c: Moved to...
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: 
> ...here.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c: Removed.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c: Removed.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c: Removed.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c: Removed.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c: Removed.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: New 
> test.
>
> ---
>  .../riscv/rvv/autovec/cond/cond_arith-1.c | 13 +
>  .../riscv/rvv/autovec/cond/cond_arith-2.c |  3 ++
>  .../riscv/rvv/autovec/cond/cond_arith-3.c | 15 ++
>  .../riscv/rvv/autovec/cond/cond_arith-4.c |  3 ++
>  .../riscv/rvv/autovec/cond/cond_arith-5.c | 13 +
>  .../riscv/rvv/autovec/cond/cond_arith-6.c |  3 ++
>  .../riscv/rvv/autovec/cond/cond_arith-7.c |  9 
>  .../riscv/rvv/autovec/cond/cond_arith-8.c | 17 ++-
>  .../riscv/rvv/autovec/cond/cond_arith-9.c | 11 -
>  .../riscv/rvv/autovec/cond/cond_logical-1.c   | 43 
>  .../riscv/rvv/autovec/cond/cond_logical-2.c   | 43 
>  .../riscv/rvv/autovec/cond/cond_logical-3.c   | 43 
>  .../riscv/rvv/autovec/cond/cond_logical-4.c   | 43 
>  .../riscv/rvv/autovec/cond/cond_logical-5.c   | 43 
>  .../rvv/autovec/cond/cond_logical_min_max-1.c | 49 +++
>  .../rvv/autovec/cond/cond_logical_min_max-2.c | 49 +++
>  .../rvv/autovec/cond/cond_logical_min_max-3.c | 49 +++
>  .../rvv/autovec/cond/cond_logical_min_max-4.c | 49 +++
>  .../rvv/autovec/cond/cond_logical_min_max-5.c | 49 +++
>  ...l_run-1.c => cond_logical_min_max_run-1.c} |  2 +-
>  ...l_run-2.c => cond_logical_min_max_run-2.c} |  2 +-
>  ...l_run-3.c => cond_logical_min_max_run-3.c} |  2 +-
>  ...l_run-4.c => cond_logical_min_max_run-4.c} |  2 +-
>  ...l_run-5.c => cond_logical_min_max_run-5.c} |  2 +-
>  .../autovec/cond/cond_widen_complicate-1.c| 35 +
>  .../autovec/cond/cond_widen_complicate-2.c| 35 +
>  .../autovec/cond/cond_widen_complicate-3.c| 36 

Re: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types

[Kito Cheng via Gcc-patches]

LGTM, thanks for implement this :)

On Tue, Sep 12, 2023 at 10:16 AM juzhe.zh...@rivai.ai
 wrote:
>
> Thanks for support it.
> LGTM from my side.
> Wait for kito's more comments.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Li Xu
> Date: 2023-09-12 10:08
> To: gcc-patches
> CC: kito.cheng; palmer; juzhe.zhong; pan2.li; gaofei; wangfeng; xuli
> Subject: [PATCH] RISC-V: Add vcreate intrinsics for RVV tuple types
> From: xuli 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc (class vcreate):
> (BASE): New class.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def (vcreate): Add 
> vcreate support.
> * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): 
> Ditto.
> (SHAPE): Ditto.
> * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
> * config/riscv/riscv-vector-builtins.cc: Add args type.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/tuple_create.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc  |  40 ++
> .../riscv/riscv-vector-builtins-bases.h   |   1 +
> .../riscv/riscv-vector-builtins-functions.def |   1 +
> .../riscv/riscv-vector-builtins-shapes.cc |  50 +++
> .../riscv/riscv-vector-builtins-shapes.h  |   1 +
> gcc/config/riscv/riscv-vector-builtins.cc |  12 ++
> .../gcc.target/riscv/rvv/base/tuple_create.c  | 123 ++
> 7 files changed, 228 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_create.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 8e679f72392..be3df2c1ea2 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1824,6 +1824,44 @@ public:
>}
> };
> +class vcreate : public function_base
> +{
> +public:
> +  gimple *fold (gimple_folder ) const override
> +  {
> +unsigned int nargs = gimple_call_num_args (f.call);
> +tree lhs_type = TREE_TYPE (f.lhs);
> +
> +/* Replace the call with a clobber of the result (to prevent it from
> +   becoming upwards exposed) followed by stores into each individual
> +   vector of tuple.
> +
> +   The fold routines expect the replacement statement to have the
> +   same lhs as the original call, so return the clobber statement
> +   rather than the final vector store.  */
> +gassign *clobber = gimple_build_assign (f.lhs, build_clobber (lhs_type));
> +
> +for (unsigned int i = nargs; i-- > 0; )
> +  {
> + tree rhs_vector = gimple_call_arg (f.call, i);
> + tree field = tuple_type_field (TREE_TYPE (f.lhs));
> + tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
> + unshare_expr (f.lhs), field, NULL_TREE);
> + tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
> +   lhs_array, size_int (i),
> +   NULL_TREE, NULL_TREE);
> + gassign *assign = gimple_build_assign (lhs_vector, rhs_vector);
> + gsi_insert_after (f.gsi, assign, GSI_SAME_STMT);
> +  }
> +return clobber;
> +  }
> +
> +  rtx expand (function_expander ) const override
> +  {
> +return NULL_RTX;
> +  }
> +};
> +
> class read_vl : public function_base
> {
> public:
> @@ -2285,6 +2323,7 @@ static CONSTEXPR const vlmul_ext vlmul_ext_obj;
> static CONSTEXPR const vlmul_trunc vlmul_trunc_obj;
> static CONSTEXPR const vset vset_obj;
> static CONSTEXPR const vget vget_obj;
> +static CONSTEXPR const vcreate vcreate_obj;
> static CONSTEXPR const read_vl read_vl_obj;
> static CONSTEXPR const vleff vleff_obj;
> static CONSTEXPR const vlenb vlenb_obj;
> @@ -2546,6 +2585,7 @@ BASE (vlmul_ext)
> BASE (vlmul_trunc)
> BASE (vset)
> BASE (vget)
> +BASE (vcreate)
> BASE (read_vl)
> BASE (vleff)
> BASE (vlenb)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 69d4562091f..131041ea66f 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -267,6 +267,7 @@ extern const function_base *const vlmul_ext;
> extern const function_base *const vlmul_trunc;
> extern const function_base *const vset;
> extern const function_base *const vget;
> +extern const function_base *const vcreate;
> extern const function_base *const read_vl;
> extern const function_base *const vleff;
> extern const function_base *const vlenb;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 3ce06dc60b7..18ed2c2b8f6 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -621,6 +621,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds, 
> all_v_vget_lmul4_x2_ops)
> // Tuple types
> DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops)
> DEF_RVV_FUNCTION (vget, vget, none_preds, 

Re: [PATCH 2/2] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

[Kito Cheng via Gcc-patches]

LGTM, I think llvm and GCC are inconsistent for those intrinsics API
is really unfortunate...so really appreciate making those API align :)
And did you have plan to add riscv_crypto.h after updating/fixing all builtin?

On Tue, Sep 12, 2023 at 9:29 AM Tsukasa OI via Gcc-patches
 wrote:
>
> From: Tsukasa OI 
>
> This is in parity with the LLVM commit a64b3e92c7cb ("[RISCV] Re-define
> sha256, Zksed, and Zksh intrinsics to use i32 types.").
>
> SHA-256, SM3 and SM4 instructions operate on 32-bit integers and upper
> 32-bits have no effects on RV64 (the output is sign-extended from the
> original 32-bit value).  In that sense, making those intrinsics only
> operate on uint32_t is much more natural than XLEN-bits wide integers.
>
> This commit reforms instructions and expansions based on 32-bit
> instruction handling on RV64 (such as ADDW).
>
> Before:
>riscv__si: For RV32, fully operate on uint32_t
>riscv__di: For RV64, fully operate on uint64_t
> After:
>   *riscv__si: For RV32, fully operate on uint32_t
>riscv__di_extended:
>   For RV64.  Input is uint32_t and output is int64_t,
>   sign-extended from the int32_t result
>   (represents a part of  behavior).
>riscv__si: Common (fully operate on uint32_t).
>   On RV32, "expands" to *riscv__si.
>   On RV64, initially expands to riscv__di_extended *and*
>   extracts lower 32-bits from the int64_t result.
>
> It also refines definitions of SHA-256, SM3 and SM4 intrinsics.
>
> gcc/ChangeLog:
>
> * config/riscv/crypto.md (riscv_sha256sig0_,
> riscv_sha256sig1_, riscv_sha256sum0_,
> riscv_sha256sum1_, riscv_sm3p0_, riscv_sm3p1_,
> riscv_sm4ed_, riscv_sm4ks_): Remove and replace with
> new insn/expansions.
> (SHA256_OP, SM3_OP, SM4_OP): New iterators.
> (sha256_op, sm3_op, sm4_op): New attributes for iteration.
> (*riscv__si): New raw instruction for RV32.
> (*riscv__si): Ditto.
> (*riscv__si): Ditto.
> (riscv__di_extended): New base instruction for RV64.
> (riscv__di_extended): Ditto.
> (riscv__di_extended): Ditto.
> (riscv__si): New common instruction expansion.
> (riscv__si): Ditto.
> (riscv__si): Ditto.
> * config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
> "crypto_zksh" and "crypto_zksed".  Remove availability
> "crypto_zksh{32,64}" and "crypto_zksed{32,64}".
> * config/riscv/riscv-ftypes.def: Remove unused function type.
> * config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
> intrinsics to operate on uint32_t.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zknh-sha256.c: Moved to...
> * gcc.target/riscv/zknh-sha256-64.c: ...here.  Test RV64.
> * gcc.target/riscv/zknh-sha256-32.c: New test for RV32.
> * gcc.target/riscv/zksh64.c: Change the type.
> * gcc.target/riscv/zksed64.c: Ditto.
> ---
>  gcc/config/riscv/crypto.md| 161 --
>  gcc/config/riscv/riscv-builtins.cc|   7 +-
>  gcc/config/riscv/riscv-ftypes.def |   1 -
>  gcc/config/riscv/riscv-scalar-crypto.def  |  24 +--
>  .../gcc.target/riscv/zknh-sha256-32.c |  10 ++
>  .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
>  gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
>  gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
>  8 files changed, 139 insertions(+), 80 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
>  rename gcc/testsuite/gcc.target/riscv/{zknh-sha256.c => zknh-sha256-64.c} 
> (78%)
>
> diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
> index e4b7f0190dfe..03a1d03397d9 100644
> --- a/gcc/config/riscv/crypto.md
> +++ b/gcc/config/riscv/crypto.md
> @@ -250,36 +250,47 @@
>
>  ;; ZKNH - SHA256
>
> -(define_insn "riscv_sha256sig0_"
> -  [(set (match_operand:X 0 "register_operand" "=r")
> -(unspec:X [(match_operand:X 1 "register_operand" "r")]
> -  UNSPEC_SHA_256_SIG0))]
> -  "TARGET_ZKNH"
> -  "sha256sig0\t%0,%1"
> -  [(set_attr "type" "crypto")])
> -
> -(define_insn "riscv_sha256sig1_"
> -  [(set (match_operand:X 0 "register_operand" "=r")
> -(unspec:X [(match_operand:X 1 "register_operand" "r")]
> -  UNSPEC_SHA_256_SIG1))]
> -  "TARGET_ZKNH"
> -  "sha256sig1\t%0,%1"
> +(define_int_iterator SHA256_OP [
> +  UNSPEC_SHA_256_SIG0 UNSPEC_SHA_256_SIG1
> +  UNSPEC_SHA_256_SUM0 UNSPEC_SHA_256_SUM1])
> +(define_int_attr sha256_op [
> +  (UNSPEC_SHA_256_SIG0 "sha256sig0") (UNSPEC_SHA_256_SIG1 "sha256sig1")
> +  (UNSPEC_SHA_256_SUM0 "sha256sum0") (UNSPEC_SHA_256_SUM1 "sha256sum1")])
> +
> +(define_insn "*riscv__si"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
> +   

Re: [PATCH v5] RISC-V:Optimize the MASK opt generation

[Kito Cheng via Gcc-patches]

Hi Feng:

This version is LGTM, but I guess I would like to ask Jeff or another
global maintainer to approve that, anyway I'll follow up this in the
next gcc sync up meeting :)

On Fri, Sep 8, 2023 at 9:28 AM Feng Wang  wrote:
>
> Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
> to generate MASK and TARGET MACRO automatically.
> This patch improve the MACRO generation of MASK_* and TARGET_*.
> Due to the more and more riscv extensions are added, the default target_flag
> is full.
> Before this patch,if you want to add new MACRO,you should define the
> MACRO in the riscv-opts.h manually.
> After this patch, you just need two steps:
> 1.Define the new TargetVariable.
> 2.Define "MASK(name) Var(new_target_flag).
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL):Ditto;
> (MASK_ZIHINTPAUSE):  Ditto;
> (TARGET_ZICSR):  Ditto;
> (TARGET_ZIFENCEI):   Ditto;
> (TARGET_ZIHINTNTL):  Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS):Ditto;
> (TARGET_ZAWRS):  Ditto;
> (MASK_ZBA):  Ditto;
> (MASK_ZBB):  Ditto;
> (MASK_ZBC):  Ditto;
> (MASK_ZBS):  Ditto;
> (TARGET_ZBA):Ditto;
> (TARGET_ZBB):Ditto;
> (TARGET_ZBC):Ditto;
> (TARGET_ZBS):Ditto;
> (MASK_ZFINX):Ditto;
> (MASK_ZDINX):Ditto;
> (MASK_ZHINX):Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX):  Ditto;
> (TARGET_ZDINX):  Ditto;
> (TARGET_ZHINX):  Ditto;
> (TARGET_ZHINXMIN):   Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR):  Ditto;
> (MASK_ZKSED):Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT):  Ditto;
> (TARGET_ZBKB):   Ditto;
> (TARGET_ZBKC):   Ditto;
> (TARGET_ZBKX):   Ditto;
> (TARGET_ZKNE):   Ditto;
> (TARGET_ZKND):   Ditto;
> (TARGET_ZKNH):   Ditto;
> (TARGET_ZKR):Ditto;
> (TARGET_ZKSED):  Ditto;
> (TARGET_ZKSH):   Ditto;
> (TARGET_ZKT):Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO):   Ditto;
> (MASK_VECTOR_ELEN_32):   Ditto;
> (MASK_VECTOR_ELEN_64):   Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>  (MASK_ZVBB):   Ditto;
> (MASK_ZVBC):   Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG):   Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH):  Ditto;
> (MASK_ZVKN):   Ditto;
> (MASK_ZVKNC):  Ditto;
> (MASK_ZVKNG):  Ditto;
> (MASK_ZVKS):   Ditto;
> (MASK_ZVKSC):  Ditto;
> (MASK_ZVKSG):  Ditto;
> (MASK_ZVKT):   Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED):   Ditto;
> (TARGET_ZVKNHA):   Ditto;
> (TARGET_ZVKNHB):   Ditto;
> (TARGET_ZVKSED):   Ditto;
> (TARGET_ZVKSH):Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC):Ditto;
> (TARGET_ZVKNG):Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC):Ditto;
> (TARGET_ZVKSG):Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B):Ditto;
> (MASK_ZVL256B):Ditto;
> (MASK_ZVL512B):Ditto;
> (MASK_ZVL1024B):   Ditto;
> (MASK_ZVL2048B):   Ditto;
> (MASK_ZVL4096B):   Ditto;
> (MASK_ZVL8192B):   Ditto;
> (MASK_ZVL16384B):  Ditto;
> (MASK_ZVL32768B):  Ditto;
> (MASK_ZVL65536B):  Ditto;
> (TARGET_ZVL32B):   Ditto;
> (TARGET_ZVL64B):   Ditto;
> (TARGET_ZVL128B):  Ditto;
> (TARGET_ZVL256B):  Ditto;
> (TARGET_ZVL512B):  Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> 

Re: [PATCH 0/2] resolve confilct between zcmp multi push/pop and shrink-wrap-separate

[Kito Cheng via Gcc-patches]

Pushed to trunk, thanks :)

On Wed, Sep 6, 2023 at 5:41 PM Fei Gao  wrote:
>
> Enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective.
>
> Fei Gao (2):
>   allow targets to check shrink-wrap-separate enabled or not
>   [V2][RISC-V] enable muti push and pop for Zcmp when shrink-wrap-separate is 
> ineffective
>
>  gcc/config/riscv/riscv.cc | 21 -
>  gcc/shrink-wrap.cc| 22 +++--
>  gcc/shrink-wrap.h |  1 +
>  gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c   |  2 +-
>  gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c   |  2 +-
>  .../gcc.target/riscv/zcmp_push_fpr.c  |  2 +-
>  .../riscv/zcmp_shrink_wrap_separate.c | 93 +++
>  .../riscv/zcmp_shrink_wrap_separate2.c| 93 +++
>  .../gcc.target/riscv/zcmp_stack_alignment.c   |  2 +-
>  9 files changed, 223 insertions(+), 15 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c
>
> --
> 2.17.1
>

Re: [PATCH] RISC-V: Remove redundant functions

[Kito Cheng via Gcc-patches]

LGTM

On Mon, Sep 11, 2023 at 5:20 PM Juzhe-Zhong  wrote:
>
> I just finished V2 version of LMUL cost model.
> Turns out we don't these redundant functions.
>
> Remove them.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (get_all_predecessors): Remove.
> (get_all_successors): Ditto.
> * config/riscv/riscv-v.cc (get_all_predecessors): Ditto.
> (get_all_successors): Ditto.
>
> ---
>  gcc/config/riscv/riscv-protos.h |  2 --
>  gcc/config/riscv/riscv-v.cc | 48 -
>  2 files changed, 50 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 46d77ef927c..e91a55ec057 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -498,8 +498,6 @@ enum floating_point_rounding_mode get_frm_mode (rtx);
>  opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
>  poly_uint64);
>  unsigned int autovectorize_vector_modes (vec *, bool);
> -hash_set get_all_predecessors (basic_block);
> -hash_set get_all_successors (basic_block);
>  bool cmp_lmul_le_one (machine_mode);
>  bool cmp_lmul_gt_one (machine_mode);
>  }
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 3cd1f61de0e..4d95bd773a2 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -3388,54 +3388,6 @@ expand_fold_extract_last (rtx *ops)
>emit_label (end_label);
>  }
>
> -hash_set
> -get_all_predecessors (basic_block bb)
> -{
> -  hash_set blocks;
> -  auto_vec work_list;
> -  hash_set visited_list;
> -  work_list.safe_push (bb);
> -
> -  while (!work_list.is_empty ())
> -{
> -  basic_block new_bb = work_list.pop ();
> -  visited_list.add (new_bb);
> -  edge e;
> -  edge_iterator ei;
> -  FOR_EACH_EDGE (e, ei, new_bb->preds)
> -   {
> - if (!visited_list.contains (e->src))
> -   work_list.safe_push (e->src);
> - blocks.add (e->src);
> -   }
> -}
> -  return blocks;
> -}
> -
> -hash_set
> -get_all_successors (basic_block bb)
> -{
> -  hash_set blocks;
> -  auto_vec work_list;
> -  hash_set visited_list;
> -  work_list.safe_push (bb);
> -
> -  while (!work_list.is_empty ())
> -{
> -  basic_block new_bb = work_list.pop ();
> -  visited_list.add (new_bb);
> -  edge e;
> -  edge_iterator ei;
> -  FOR_EACH_EDGE (e, ei, new_bb->succs)
> -   {
> - if (!visited_list.contains (e->dest))
> -   work_list.safe_push (e->dest);
> - blocks.add (e->dest);
> -   }
> -}
> -  return blocks;
> -}
> -
>  /* Return true if the LMUL of comparison less than or equal to one.  */
>  bool
>  cmp_lmul_le_one (machine_mode mode)
> --
> 2.36.3
>

Re: [PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic

[Kito Cheng via Gcc-patches]

> @@ -545,7 +563,7 @@ struct move_def : public build_base
>  /* According to rvv-intrinsic-doc, it does not add "_m" suffix
> for vop_m C++ overloaded API.  */
> -if (overloaded_p && instance.pred == PRED_TYPE_m)
> +if (overloaded_p)

Just make sure it's the right change?

>return b.finish_name ();
>  b.append_name (predication_suffixes[instance.pred]);
>  return b.finish_name ();

Re: [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination

[Kito Cheng via Gcc-patches]

LGTM, and I guess you will remove get_all_predecessors once LMUL cost
model can use dominator info as well?


On Mon, Sep 11, 2023 at 11:34 AM Juzhe-Zhong  wrote:
>
> I found that it's more reasonable to use existing dominance analysis.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc 
> (pass_vsetvl::global_eliminate_vsetvl_insn): Use dominance analysis.
> (pass_vsetvl::init): Ditto.
> (pass_vsetvl::done): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 134b97737ae..f81361c4ccd 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const 
> bb_info *bb) const
>  }
>
>/* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  
> */
> -  hash_set pred_cfg_bbs = get_all_predecessors (cfg_bb);
> +  auto_vec pred_cfg_bbs = get_dominated_by 
> (CDI_POST_DOMINATORS, cfg_bb);
>FOR_EACH_EDGE (e, ei, cfg_bb->preds)
>  {
>sbitmap avout = m_vector_manager->vector_avout[e->src->index];
> @@ -4243,6 +4243,7 @@ pass_vsetvl::init (void)
>  {
>/* Initialization of RTL_SSA.  */
>calculate_dominance_info (CDI_DOMINATORS);
> +  calculate_dominance_info (CDI_POST_DOMINATORS);
>df_analyze ();
>crtl->ssa = new function_info (cfun);
>  }
> @@ -4264,6 +4265,7 @@ pass_vsetvl::done (void)
>  {
>/* Finalization of RTL_SSA.  */
>free_dominance_info (CDI_DOMINATORS);
> +  free_dominance_info (CDI_POST_DOMINATORS);
>if (crtl->ssa->perform_pending_updates ())
> cleanup_cfg (0);
>delete crtl->ssa;
> --
> 2.36.3
>

Re: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]

[Kito Cheng via Gcc-patches]

OK, but could you split this patch into two patches? pre-approved for both.

On Mon, Sep 11, 2023 at 10:36 AM juzhe.zh...@rivai.ai
 wrote:
>
> >> Should we also add loads and stores as well?
> >> and just make sure this is also necessary for the fix and not sneaky, 
> >> right?
>
> No, we don't need loads/stores. Since this following handling codes:
> (define_insn_and_split "*mov_lra"
>   [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
>   (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" "  m,vr,vr"))
>(clobber (match_scratch:P 2 "=,,X"))]
>   "TARGET_VECTOR && (lra_in_progress || reload_completed)
>&& (register_operand (operands[0], mode)
>|| register_operand (operands[1], mode))"
>   "#"
>   "&& reload_completed"
>   [(const_int 0)]
> {
>   if (REG_P (operands[0]) && REG_P (operands[1]))
>   emit_insn (gen_rtx_SET (operands[0], operands[1]));
>   else
> {
>   emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS 
> (mode),
>  Pmode));
>   unsigned insn_flags
> = GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL
>  ? riscv_vector::UNARY_MASK_OP
>  : riscv_vector::UNARY_OP;
>   riscv_vector::emit_nonvlmax_insn (code_for_pred_mov 
> (mode),
>   insn_flags, operands, operands[2]);
> }
>   DONE;
> }
>   [(set_attr "type" "vmov")]
> )
>
> We split special case use emit_insn (gen_rtx_SET (operands[0], operands[1]));
>
> Missing this pattern will cause ICE but current testcases didn't produce such 
> issues.
> This issue is recognized after I support this pattern.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-11 10:18
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng
> Subject: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
> > diff --git a/gcc/config/riscv/autovec-vls.md 
> > b/gcc/config/riscv/autovec-vls.md
> > index d208b418e5f..6f48f7d6232 100644
> > --- a/gcc/config/riscv/autovec-vls.md
> > +++ b/gcc/config/riscv/autovec-vls.md
> > @@ -148,6 +148,14 @@
> >[(set_attr "type" "vmov")
> > (set_attr "mode" "")])
> >
> > +(define_insn "*mov_vls"
> > +  [(set (match_operand:VLSB 0 "register_operand" "=vr")
> > +   (match_operand:VLSB 1 "register_operand" " vr"))]
> > +  "TARGET_VECTOR"
> > +  "vmv1r.v\t%0,%1"
> > +  [(set_attr "type" "vmov")
> > +   (set_attr "mode" "")])
>
> Should we also add loads and stores as well?
> and just make sure this is also necessary for the fix and not sneaky, right?
>
> > +
> >  (define_expand "movmisalign"
> >[(set (match_operand:VLS 0 "nonimmediate_operand")
> > (match_operand:VLS 1 "general_operand"))]
>

Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]

[Kito Cheng via Gcc-patches]

> diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> index d208b418e5f..6f48f7d6232 100644
> --- a/gcc/config/riscv/autovec-vls.md
> +++ b/gcc/config/riscv/autovec-vls.md
> @@ -148,6 +148,14 @@
>[(set_attr "type" "vmov")
> (set_attr "mode" "")])
>
> +(define_insn "*mov_vls"
> +  [(set (match_operand:VLSB 0 "register_operand" "=vr")
> +   (match_operand:VLSB 1 "register_operand" " vr"))]
> +  "TARGET_VECTOR"
> +  "vmv1r.v\t%0,%1"
> +  [(set_attr "type" "vmov")
> +   (set_attr "mode" "")])

Should we also add loads and stores as well?
and just make sure this is also necessary for the fix and not sneaky, right?

> +
>  (define_expand "movmisalign"
>[(set (match_operand:VLS 0 "nonimmediate_operand")
> (match_operand:VLS 1 "general_operand"))]

Re: [PATCH] RISC-V: Fix dump FILE of VSETVL PASS[PR111311]

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月10日 週日 07:58 寫道：

> To make the dump FILE not too big, add TDF_DETAILS.
>
> This patch fix these following FAILs in
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311
>
> FAIL: gcc.c-torture/unsorted/dump-noaddr.c.*r.vsetvl,  -O3
> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
> -finline-functions  comparison
> FAIL: gcc.c-torture/unsorted/dump-noaddr.c.*r.vsetvl,  -O3 -g  comparison
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl::vsetvl_fusion): Add
> TDF_DETAILS.
> (pass_vsetvl::pre_vsetvl): Ditto.
> (pass_vsetvl::init): Ditto.
> (pass_vsetvl::lazy_vsetvl): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index ae362a3f6a8..134b97737ae 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3438,7 +3438,7 @@ pass_vsetvl::vsetvl_fusion (void)
> m_vector_manager->vector_kill,
> m_vector_manager->vector_earliest);
>changed_p |= earliest_fusion ();
> -  if (dump_file)
> +  if (dump_file && (dump_flags & TDF_DETAILS))
> {
>   fprintf (dump_file, "\nEARLIEST fusion %d\n", fusion_no);
>   m_vector_manager->dump (dump_file);
> @@ -3720,7 +3720,7 @@ pass_vsetvl::pre_vsetvl (void)
>
>/* We should dump the information before CFG is changed. Otherwise it
> will
>   produce ICE (internal compiler error).  */
> -  if (dump_file)
> +  if (dump_file && (dump_flags & TDF_DETAILS))
>  m_vector_manager->dump (dump_file);
>
>refine_vsetvls ();
> @@ -4250,7 +4250,7 @@ pass_vsetvl::init (void)
>m_vector_manager = new vector_infos_manager ();
>compute_probabilities ();
>
> -  if (dump_file)
> +  if (dump_file && (dump_flags & TDF_DETAILS))
>  {
>fprintf (dump_file, "\nPrologue: Initialize vector infos\n");
>m_vector_manager->dump (dump_file);
> @@ -4334,7 +4334,7 @@ pass_vsetvl::lazy_vsetvl (void)
>  fprintf (dump_file, "\nPhase 1: Compute local backward vector
> infos\n");
>for (const bb_info *bb : crtl->ssa->bbs ())
>  compute_local_backward_infos (bb);
> -  if (dump_file)
> +  if (dump_file && (dump_flags & TDF_DETAILS))
>  m_vector_manager->dump (dump_file);
>
>/* Phase 2 - Emit vsetvl instructions within each basic block according
> to
> @@ -4344,7 +4344,7 @@ pass_vsetvl::lazy_vsetvl (void)
>  "\nPhase 2: Emit vsetvl instruction within each block\n");
>for (const bb_info *bb : crtl->ssa->bbs ())
>  emit_local_forward_vsetvls (bb);
> -  if (dump_file)
> +  if (dump_file && (dump_flags & TDF_DETAILS))
>  m_vector_manager->dump (dump_file);
>
>/* Phase 3 - Propagate demanded info across blocks.  */
> --
> 2.36.3
>
>

Re: [PATCH] riscv: xtheadbb: Fix extendqi insn

[Kito Cheng via Gcc-patches]

LGTM

Christoph Muellner 於 2023年9月8日 週五，14:00寫道：

> From: Christoph Müllner 
>
> Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
> * 500.perlbench_r
> * 525.x264_r
> * 557.xz_r
>
> Tracing the issue down revealed, that we emit a 'th.ext xN,xN,15,0'
> for a extendqi insn, which is obviously wrong.
> This patch splits the common 'extend2_th_ext'
> insn into two 'extendqi' and 'extendhi' insns,
> which emit the right extension instruction.
> Additionally, this patch adds test cases for these insns.
>
> Signed-off-by: Christoph Müllner 
>
> gcc/ChangeLog:
>
> * config/riscv/thead.md
> (*extend2_th_ext):
> Remove broken INSN.
> (*extendhi2_th_ext): New INSN.
> (*extendqi2_th_ext): New INSN.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xtheadbb-ext-2.c: New test.
> * gcc.target/riscv/xtheadbb-ext-3.c: New test.
> ---
>  gcc/config/riscv/thead.md   | 17 ++---
>  gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c | 12 
>  gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c | 12 
>  3 files changed, 38 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 29f98dec3a8..05d1b32bd94 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -58,14 +58,25 @@ (define_insn "*th_ext4"
>[(set_attr "type" "bitmanip")
> (set_attr "mode" "")])
>
> -(define_insn "*extend2_th_ext"
> +(define_insn "*extendhi2_th_ext"
>[(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
> (sign_extend:SUPERQI
> -   (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
> +   (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
>"TARGET_XTHEADBB"
>"@
> th.ext\t%0,%1,15,0
> -   l\t%0,%1"
> +   lh\t%0,%1"
> +  [(set_attr "type" "bitmanip,load")
> +   (set_attr "mode" "")])
> +
> +(define_insn "*extendqi2_th_ext"
> +  [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
> +   (sign_extend:SUPERQI
> +   (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
> +  "TARGET_XTHEADBB"
> +  "@
> +   th.ext\t%0,%1,7,0
> +   lb\t%0,%1"
>[(set_attr "type" "bitmanip,load")
> (set_attr "mode" "")])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> new file mode 100644
> index 000..4645b9c56df
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
> +
> +signed long extqi(signed char i)
> +{
> +return --i;
> +}
> +
> +/* { dg-final { scan-assembler "th.ext\ta\[0-9\]+,a\[0-9\]+,7,0" } } */
> +/* { dg-final { scan-assembler-not "th.ext\ta\[0-9\]+,a\[0-9\]+,15,0" } }
> */
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> new file mode 100644
> index 000..2c9ebbc563a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
> +
> +signed long exthi(signed short i)
> +{
> +return --i;
> +}
> +
> +/* { dg-final { scan-assembler "th.ext\ta\[0-9\]+,a\[0-9\]+,15,0" } } */
> +/* { dg-final { scan-assembler-not "th.ext\ta\[0-9\]+,a\[0-9\]+,7,0" } }
> */
> --
> 2.41.0
>
>

Re: [PATCH] RISC-V: Suppress bogus warning for VLS types

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月8日 週五 16:20 寫道：

> This patch fixes over 100+ bogus FAILs due to experimental vector ABI
> warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_pass_in_vector_p): Only allow RVV
> type.
>
> ---
>  gcc/config/riscv/riscv.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 9f0c8bbe9ed..81682d95ba4 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4414,7 +4414,7 @@ riscv_pass_in_vector_p (const_tree type)
>  {
>static int warned = 0;
>
> -  if (type && riscv_v_ext_mode_p (TYPE_MODE (type)) && !warned)
> +  if (type && riscv_vector::lookup_vector_type_attribute (type) &&
> !warned)
>  {
>warning (OPT_Wpsabi,
>"ABI for the vector type is currently in experimental stage
> and "
> --
> 2.36.3
>
>

Re: [PATCH] riscv: thead: Fix mode attribute for extension patterns

[Kito Cheng via Gcc-patches]

LGTM

Christoph Muellner  於 2023年9月8日 週五 14:16 寫道：

> From: Christoph Müllner 
>
> The mode attribute of an extension pattern is usually set to the target
> type.
> Let's follow this convention consistently for xtheadbb.
>
> Signed-off-by: Christoph Müllner 
>
> gcc/ChangeLog:
>
> * config/riscv/thead.md: Use more appropriate mode attributes
> for extensions.
> ---
>  gcc/config/riscv/thead.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 05d1b32bd94..2287b752ea1 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -101,7 +101,7 @@ (define_insn "*zero_extendsidi2_th_extu"
> th.extu\t%0,%1,31,0
> lwu\t%0,%1"
>[(set_attr "type" "bitmanip,load")
> -   (set_attr "mode" "SI")])
> +   (set_attr "mode" "DI")])
>
>  (define_insn "*zero_extendhi2_th_extu"
>[(set (match_operand:GPR 0 "register_operand" "=r,r")
> @@ -111,7 +111,7 @@ (define_insn "*zero_extendhi2_th_extu"
> th.extu\t%0,%1,15,0
> lhu\t%0,%1"
>[(set_attr "type" "bitmanip,load")
> -   (set_attr "mode" "HI")])
> +   (set_attr "mode" "")])
>
>  (define_insn "*th_clz2"
>[(set (match_operand:X 0 "register_operand" "=r")
> --
> 2.41.0
>
>

Re: [PATCH] RISC-V: Fix incorrect nregs calculation for VLS modes

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月8日 週五 15:52 寫道：

> This patch fixes obvious bug: TARGET_MIN_VLEN is bitsize.
>
> All these following bugs are fixed with this patch:
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (test for excess
> errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (test for excess
> errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (test for excess
> errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto
> -fno-use-linker-plugin -flto-partition=none  (internal compiler error: in
> gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto
> -fno-use-linker-plugin -flto-partition=none  (test for excess errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto
> -fuse-linker-plugin -fno-fat-lto-objects  (internal compiler error: in
> gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto
> -fuse-linker-plugin -fno-fat-lto-objects  (test for excess errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (test for excess
> errors)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (internal compiler
> error: in gen_reg_rtx, at emit-rtl.cc:1176)
> FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (test for excess
> errors)
> FAIL: gcc.target/riscv/rvv/base/mov-13.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/mov-13.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-1.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-1.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-2.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-2.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-3.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-3.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-4.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-4.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-5.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-5.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-6.c (internal compiler error: in
> partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-6.c (test for excess errors)
> FAIL: gcc.target/riscv/rvv/base/spill-sp-adjust.c (internal compiler
> error: in partial_subreg_p, at rtl.h:3186)
> FAIL: gcc.target/riscv/rvv/base/spill-sp-adjust.c (test for excess errors)
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_hard_regno_nregs): Fix bug.
>
> ---
>  gcc/config/riscv/riscv.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index c0c9c990a23..9f0c8bbe9ed 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7548,7 +7548,7 @@ riscv_hard_regno_nregs (unsigned int regno,
> machine_mode mode)
>/* For VLS modes, we allocate registers according to TARGET_MIN_VLEN.
> */
>if (riscv_v_ext_vls_mode_p (mode))
>  {
> -  int size = GET_MODE_SIZE (mode).to_constant ();
> +  int size = GET_MODE_BITSIZE (mode).to_constant ();
>if (size < TARGET_MIN_VLEN)
> return 1;
>else
> --
> 2.36.3
>
>

Re: [PATCH] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313]

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月7日 週四 11:36 寫道：

> This patch removes the incorrect earliest poset vsetvl optimization,
> such bug was found in vect-double-reduc-5.c which is runtime(execution
> fail) and also in PR111313.
>
> For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl
> (see vector.md) to
> occupy a scalar register which is used by the following RVV instruction
> which is VLMAX AVL.
>
> Then for O2, O3, Ofast, earliest LCM works so well.
> However, for O1, the vlmax_avl is not well optimized in the before pass
> which confused LCM earliest
> so that we will end up with some redundant vsetvli zero,zero instructions
> in O1. (Note that O2 O3 Ofast are all good).
>
> To elide those redundant vsetvli zero,zero, I added
> cleanup_earliest_vsetvls to elide those redundant vsetvls.
>
> Now, after I review the implementation of this post optimizaiton again, I
> found it is incorrect and it is hard to
> do the post optimizations for vsetvls that earliest LCM failed to
> eliminate.
>
> Besides, such performance issues only happen in O1 or O0, such issues may
> not be serious.
> So remove it and we may will find another way (E.g. adjust vlmax_avl
> pattern COST)
> to optimize it if we really need to care about performance for O1.
>
> PR target/111313
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc
> (pass_vsetvl::cleanup_earliest_vsetvls): Remove.
> (pass_vsetvl::df_post_optimization): Remove incorrect function.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Adapt test.
> * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Skip check for
> O1.
> * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr111313.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 58 ---
>  .../gcc.target/riscv/rvv/autovec/pr111313.c   | 20 +++
>  .../riscv/rvv/vsetvl/avl_single-13.c  |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_bb_prop-17.c   |  8 +--
>  .../riscv/rvv/vsetvl/vlmax_bb_prop-18.c   |  8 +--
>  .../riscv/rvv/vsetvl/vlmax_bb_prop-19.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_bb_prop-20.c   |  4 +-
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-10.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-11.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-12.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-13.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-14.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-15.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-16.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-17.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-18.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-19.c   |  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-20.c   |  2 +-
>  .../riscv/rvv/vsetvl/vlmax_phi-21.c   |  2 +-
>  

Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

[Kito Cheng via Gcc-patches]

csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.

Edwin Lu  於 2023年9月7日 週四 01:51 寫道：

> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr" type
> * config/riscv/zc.md: Update types
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/riscv.md |   3 +-
>  gcc/config/riscv/zc.md| 102 +++---
>  2 files changed, 54 insertions(+), 51 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index d80b6938f84..6684ad89cff 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
>  ;; condmoveconditional moves
>  ;; cbocache block instructions
>  ;; crypto cryptography instructions
> +;; csrcode size reduction instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
>  ;; rdvlenb vector byte length vlenb csrr read
>  ;; rdvlvector length vl csrr read
> @@ -421,7 +422,7 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> -   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> +   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> index 77b28adde95..86f1afd66cb 100644
> --- a/gcc/config/riscv/zc.md
> +++ b/gcc/config/riscv/zc.md
> @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s0_"
>[(set (reg:X SP_REGNUM)
> @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s1_"
>[(set (reg:X SP_REGNUM)
> @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s2_"
>[(set (reg:X SP_REGNUM)
> @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s3_"
>[(set (reg:X SP_REGNUM)
> @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s4_"
>[(set (reg:X SP_REGNUM)
> @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s5_"
>[(set (reg:X SP_REGNUM)
> @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s6_"
>[(set (reg:X SP_REGNUM)
> @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s7_"
>[(set (reg:X SP_REGNUM)
> @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
>(const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s8_"
>[(set (reg:X SP_REGNUM)
> @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s9_"
>[(set (reg:X SP_REGNUM)
> @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s11_"
>[(set (reg:X SP_REGNUM)
> @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s11}, %0"
> -)
> +[(set_attr "type" 

Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions

[Kito Cheng via Gcc-patches]

LGTM

Edwin Lu  於 2023年9月7日 週四 01:51 寫道：

> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
> * config/riscv/autovec.md: likewise
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/autovec-opt.md | 42 ++---
>  gcc/config/riscv/autovec.md | 28 +++---
>  2 files changed, 47 insertions(+), 23 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index 1ca5ce97193..6cc1a01629c 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs"
>  gen_int_mode (GET_MODE_NUNITS
> (mode), Pmode),
>  const0_rtx));
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
>  (define_insn_and_split "*copysign_neg"
> @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign_neg"
>riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (mode),
>riscv_vector::BINARY_OP, operands);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine sign_extend/zero_extend(vf2) and vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -765,7 +767,8 @@ (define_insn_and_split
> "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine sign_extend/zero_extend(vf4) and vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -784,7 +787,8 @@ (define_insn_and_split
> "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine sign_extend/zero_extend(vf8) and vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -803,7 +807,8 @@ (define_insn_and_split
> "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine trunc(vf2) + vcond_mask
>  (define_insn_and_split "*cond_trunc"
> @@ -823,7 +828,8 @@ (define_insn_and_split
> "*cond_trunc"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
>  (define_insn_and_split "*cond_extend"
> @@ -842,7 +848,8 @@ (define_insn_and_split
> "*cond_extend"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine FP trunc(vf2) + vcond_mask
>  (define_insn_and_split "*cond_trunc"
> @@ -862,7 +869,8 @@ (define_insn_and_split
> "*cond_trunc"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(FP->INT) + vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(INT->FP) + vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -902,7 +911,8 @@ (define_insn_and_split
> "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(FP->2xINT) + vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(INT->2xFP) + vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -942,7 +953,8 @@ (define_insn_and_split
> "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(2xFP->INT) + vcond_mask
>  (define_insn_and_split "*cond_"
> @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_"
> gen_int_mode (GET_MODE_NUNITS (mode), Pmode)};
>riscv_vector::expand_cond_len_unop (icode, ops);
>DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
>  ;; Combine convert(2xINT->FP) + vcond_mask
>  (define_insn_and_split "*cond_2"
> @@ -982,4 +995,5 @@ 

Re: [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions

[Kito Cheng via Gcc-patches]

LGTM

Edwin Lu  於 2023年9月7日 週四 01:52 寫道：

> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Update types
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/riscv.md | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index c329f55db43..c1cecd27815 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
>"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>"fmv.x.w\t%0,%1"
>[(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
>
> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
>"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>"fmvh.x.d\t%0,%1"
>[(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
>  (define_insn "movdfsisi3_rv32"
> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
>"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>"fmvp.d.x\t%0,%2,%1"
>[(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
>  (define_split
> --
> 2.34.1
>
>

Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions

[Kito Cheng via Gcc-patches]

LGTM

Edwin Lu  於 2023年9月7日 週四 01:53 寫道：

> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/riscv.md  | 5 +++--
>  gcc/config/riscv/zicond.md | 8 
>  2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6684ad89cff..c329f55db43 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
>  ;; cbocache block instructions
>  ;; crypto cryptography instructions
>  ;; csrcode size reduction instructions
> +;; zicondzicond instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
>  ;; rdvlenb vector byte length vlenb csrr read
>  ;; rdvlvector length vl csrr read
> @@ -422,8 +423,8 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> -   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> -   vlde,vste,vldm,vstm,vlds,vsts,
> +   atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
> +   vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 1721e1011ea..0269bd14399 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -30,7 +30,7 @@ (define_insn "*czero.."
>(const_int 0)))]
>"TARGET_ZICOND"
>"czero.\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  (define_insn "*czero.."
>[(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -40,7 +40,7 @@ (define_insn "*czero.."
>(match_operand:GPR 2 "register_operand"
>  "r")))]
>"TARGET_ZICOND"
>"czero.\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  ;; Special optimization under eq/ne in primitive semantics
>  (define_insn "*czero.eqz..opt1"
> @@ -51,7 +51,7 @@ (define_insn "*czero.eqz..opt1"
>(match_operand:GPR 3 "register_operand" "r")))]
>"TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
>"czero.eqz\t%0,%3,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  (define_insn "*czero.nez..opt2"
>[(set (match_operand:GPR 0 "register_operand"   "=r")
> @@ -61,7 +61,7 @@ (define_insn "*czero.nez..opt2"
>(match_operand:GPR 3 "register_operand" "1")))]
>"TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
>"czero.eqz\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
>  ;; Combine creates this form in some cases (particularly the coremark
>  ;; CRC loop.
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Kito Cheng via Gcc-patches]

Thanks for explaining, LGTM :)


On Mon, Sep 4, 2023 at 11:39 PM Lehua Ding  wrote:
>
> Hi Kito,
>
> > Can those intermediate patterns be used for intrinsic? I would prefer
> > to keep those stuff *IF* possible used for intrinsics.
>
> I think we don't need those patterns for intrinisc. First, the deleted
> pattern does not directly correspond to intrinisc. Second, if you want
> to use these patterns to optimize the following intrinisc program (e.g.
> combine to a single vwadd.vv instruction), we'd better fold them
> directly into the internal function of autovec in Gimple IR.
>
>vint32m1_t foo(vint16mf2_t va1, vint16mf2_t vb1) {
>  vint32m1_t va2 = __riscv_vsext_vf2_i32m1(va1,
> __riscv_vsetvlmax_e32m1());
>  vint32m1_t vb2 = __riscv_vsext_vf2_i32m1(vb1,
> __riscv_vsetvlmax_e32m1());
>  vint32m1_t vc = __riscv_vadd_vv_i32m1(va2, vb2,
> __riscv_vsetvlmax_e32m1());
>  return vc;
>}
> --
> Best,
> Lehua
>
>

Re: [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention

[Kito Cheng via Gcc-patches]

Pushed to trunk with few testcase modifications, e.g. adding { target
{ riscv_vector } } to dg-run and adding -march / -mabi for compile
tests.

On Tue, Sep 5, 2023 at 4:18 PM Kito Cheng  wrote:
>
> Thanks for fixing the issue! I guess I could find time tonight to do
> the final round review and test :P then we could land this patch this
> week.
>
> On Tue, Sep 5, 2023 at 3:45 PM Lehua Ding  wrote:
> >
> > V5 change: Rebase and fix vsetvl testcase fail by change
> > `(unspec [...] UNSPEC_CALLEE_CC)` to `(use (unspec [...] 
> > UNSPEC_CALLEE_CC))`.
> > This change makes single_set function re-think call_insn as a
> > single set pattern.
> >
> > Hi RISC-V folks,
> >
> > This patch implement the proposal of RISC-V vector calling convention[1] and
> > this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
> > all vector type arguments and return values are pass by reference. With this
> > patch, these arguments and return values can pass through vector registers.
> > Currently only vector types defined in the RISC-V Vector Extension 
> > Intrinsic Document[2]
> > are supported. GNU-ext vector types are unsupported for now since the
> > corresponding proposal was not presented.
> >
> > The proposal introduce a new calling convention variant, functions which 
> > follow
> > this variant need follow the bellow vector register convention.
> >
> > | Name| ABI Mnemonic | Meaning  | Preserved across 
> > calls?
> > =
> > | v0  |  | Argument register| No
> > | v1-v7   |  | Callee-saved registers   | Yes
> > | v8-v23  |  | Argument registers   | No
> > | v24-v31 |  | Callee-saved registers   | Yes
> >
> > If a functions follow this vector calling convention, then the function 
> > symbole
> > must be annotated with .variant_cc directive[3] (used to indicate that it 
> > is a
> > calling convention variant).
> >
> > This implementation split into three parts, each part corresponds to a 
> > sub-patch.
> >
> > - Part-1: Select suitable vector regsiters for vector type arguments and 
> > return
> >   values according to the proposal.
> > - Part-2: Allocate frame area for callee-saved vector registers and 
> > save/restore
> >   them in prologue and epilogue.
> > - Part-3: Generate .variant_cc directive for vector function in assembly 
> > code.
> >
> > [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
> > [2] 
> > https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
> > [3] 
> > https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
> >
> > Best,
> > Lehua
> >
> > Lehua Ding (3):
> >   RISC-V: Part-1: Select suitable vector registers for vector type args
> > and returns
> >   RISC-V: Part-2: Save/Restore vector registers which need to be
> > preversed
> >   RISC-V: Part-3: Output .variant_cc directive for vector function
> >
> >  gcc/config/riscv/riscv-protos.h   |   4 +
> >  gcc/config/riscv/riscv-sr.cc  |   8 +-
> >  gcc/config/riscv/riscv-vector-builtins.cc |  10 +
> >  gcc/config/riscv/riscv.cc | 484 --
> >  gcc/config/riscv/riscv.h  |  43 ++
> >  gcc/config/riscv/riscv.md |  51 +-
> >  gcc/config/riscv/riscv.opt|   5 +
> >  .../riscv/rvv/base/abi-call-args-1-run.c  | 127 +
> >  .../riscv/rvv/base/abi-call-args-1.c  | 197 +++
> >  .../riscv/rvv/base/abi-call-args-2-run.c  |  34 ++
> >  .../riscv/rvv/base/abi-call-args-2.c  |  27 +
> >  .../riscv/rvv/base/abi-call-args-3-run.c  | 260 ++
> >  .../riscv/rvv/base/abi-call-args-3.c  | 116 +
> >  .../riscv/rvv/base/abi-call-args-4-run.c  | 145 ++
> >  .../riscv/rvv/base/abi-call-args-4.c  | 111 
> >  .../riscv/rvv/base/abi-call-error-1.c |  11 +
> >  .../riscv/rvv/base/abi-call-return-run.c  | 127 +
> >  .../riscv/rvv/base/abi-call-return.c  | 197 +++
> >  .../riscv/rvv/base/abi-call-variant_cc.c  |  39 ++
> >  .../rvv/base/abi-callee-saved-1-fixed-1.c |  86 
> >  .../rvv/base/abi-callee-saved-1-fixed-2.c |  86 
> >  .../base/abi-callee-saved-1-save-restore.c|  85 +++
> >  .../riscv/rvv/base/abi-callee-saved-1-zcmp.c  |  85 +++
> >  .../riscv/rvv/base/abi-callee-saved-1.c   |  88 
> >  .../base/abi-callee-saved-2-save-restore.c| 108 
> >  .../riscv/rvv/base/abi-callee-saved-2-zcmp.c  | 107 
> >  .../riscv/rvv/base/abi-callee-saved-2.c   | 117 +
> >  27 files changed, 2709 insertions(+), 49 deletions(-)
> >  create mode 100644 
> > gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
> >  create mode 100644 
> > gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
> >  create mode 

Re: [PATCH] RISC-V: Add conditional sqrt autovec pattern

[Kito Cheng via Gcc-patches]

Got failed on the trunk, could you take a look?

=== gcc: Unexpected fails for rv32imafdc ilp32d medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
scan-assembler-times \\tvfsqrt\\.v\\tv[0-9]+,v[0-9]+,v0\\.t 3
   === gcc: Unexpected fails for rv64imac lp64 medlow ===
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c scan-assembler
\\tvsetvli\\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu

Re: Re: [PATCH 2/2] [RISC-V] Enalble zcmp for -Os

[Kito Cheng via Gcc-patches]

On Wed, Sep 6, 2023 at 9:47 AM Fei Gao  wrote:
>
> On 2023-09-05 20:02  Kito Cheng  wrote:
> >
> >> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct 
> >> riscv_frame_info *frame)
> >>  {
> >>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
> >>|| cfun->machine->interrupt_handler_p || 
> >> cfun->machine->varargs_size != 0
> >> -  || crtl->args.pretend_args_size != 0 || flag_shrink_wrap_separate
> >> +  || crtl->args.pretend_args_size != 0
> >> +  || (use_shrink_wrapping_separate ()
> >> + && !riscv_avoid_shrink_wrapping_separate ())
> >
> >I think we should also check "!optimize_function_for_size_p (cfun)"
> >here, otherwise that does not really match what we claim in the commit
> >message.
> >
> A similar check optimize_function_for_speed_p is included in
> use_shrink_wrapping_separate of [1/2] allow targets to check
> shrink-wrap-separate enabled or not.
>
> >e.g. it still will enable with -O2 -fno-shrink-wrap-separate
> It's intentional to enable zcmp with -O2 -fno-shrink-wrap-separate.
> Maybe I should have given a better commit message saying
> "enable muti push and pop for Zcmp extension when
> shrink-wrap-separate is inactive".
>
> Would you like a new patch from me or agree with my
> explanation and modify commit message in your side?

Could you send a new patch with updated commit message.


>
> BR
> Fei
> >
> >>|| (frame->mask & ~MULTI_PUSH_GPR_MASK))
> >>  return true;
> >>
>

Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

[Kito Cheng via Gcc-patches]

I saw RVC has MASK_RVC and TARGET_RVC in options.h?

On Wed, Sep 6, 2023 at 2:39 PM Feng Wang  wrote:
>
> According to the doc, take“Mask(VECTOR_ELEN_32)
> Var(riscv_vector_elen_flags)”as example,
> it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate 
> MASK_VECTOR_ELEN_32
> and TARGET_VECTOR_ELEN_32.
> Do you want to use "MASK(name) Var(other_flags)" to generate the MASK and 
> TARGET Macro?
> I think it will change a lot of code and the original meaning is changed.
> --
> Feng Wang
> >Reading the manual again, it seems I missed something in the manual
> >before, the MASK syntax already says we can specify Var to select the
> >variable other than target_flags, but I tried that not work when we
> >only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
> >Var(riscv_vector_elen_flags)" still using target_flags)
> >
> >So maybe we should just fix that instead of extending the syntax?
> >e.g.
> >Mask(VECTOR_ELEN_32)Var(riscv_vector_elen_flags)
> >rather than
> >Mask(VECTOR_ELEN_32)in TargetVariable(riscv_vector_elen_flags)
> >
> >
> >On Wed, Sep 6, 2023 at 10:03 AM Feng Wang  
> >wrote:
> >>
> >> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> >> generation" and add the new explanation in the options.texi.
> >> Please check the detail info on the
> >> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html;
> >> gcc/ChangeLog:
> >>
> >> * config/riscv/riscv-opts.h (MASK_ZICSR):
> >> (MASK_ZIFENCEI): Delete;
> >> (MASK_ZIHINTNTL):Ditto;
> >> (MASK_ZIHINTPAUSE):  Ditto;
> >> (TARGET_ZICSR):  Ditto;
> >> (TARGET_ZIFENCEI):   Ditto;
> >> (TARGET_ZIHINTNTL):  Ditto;
> >> (TARGET_ZIHINTPAUSE):Ditto;
> >> (MASK_ZAWRS):Ditto;
> >> (TARGET_ZAWRS):  Ditto;
> >> (MASK_ZBA):  Ditto;
> >> (MASK_ZBB):  Ditto;
> >> (MASK_ZBC):  Ditto;
> >> (MASK_ZBS):  Ditto;
> >> (TARGET_ZBA):Ditto;
> >> (TARGET_ZBB):Ditto;
> >> (TARGET_ZBC):Ditto;
> >> (TARGET_ZBS):Ditto;
> >> (MASK_ZFINX):Ditto;
> >> (MASK_ZDINX):Ditto;
> >> (MASK_ZHINX):Ditto;
> >> (MASK_ZHINXMIN): Ditto;
> >> (TARGET_ZFINX):  Ditto;
> >> (TARGET_ZDINX):  Ditto;
> >> (TARGET_ZHINX):  Ditto;
> >> (TARGET_ZHINXMIN):   Ditto;
> >> (MASK_ZBKB): Ditto;
> >> (MASK_ZBKC): Ditto;
> >> (MASK_ZBKX): Ditto;
> >> (MASK_ZKNE): Ditto;
> >> (MASK_ZKND): Ditto;
> >> (MASK_ZKNH): Ditto;
> >> (MASK_ZKR):  Ditto;
> >> (MASK_ZKSED):Ditto;
> >> (MASK_ZKSH): Ditto;
> >> (MASK_ZKT):  Ditto;
> >> (TARGET_ZBKB):   Ditto;
> >> (TARGET_ZBKC):   Ditto;
> >> (TARGET_ZBKX):   Ditto;
> >> (TARGET_ZKNE):   Ditto;
> >> (TARGET_ZKND):   Ditto;
> >> (TARGET_ZKNH):   Ditto;
> >> (TARGET_ZKR):Ditto;
> >> (TARGET_ZKSED):  Ditto;
> >> (TARGET_ZKSH):   Ditto;
> >> (TARGET_ZKT):Ditto;
> >> (MASK_ZTSO): Ditto;
> >> (TARGET_ZTSO):   Ditto;
> >> (MASK_VECTOR_ELEN_32):   Ditto;
> >> (MASK_VECTOR_ELEN_64):   Ditto;
> >> (MASK_VECTOR_ELEN_FP_32):Ditto;
> >> (MASK_VECTOR_ELEN_FP_64):Ditto;
> >> (MASK_VECTOR_ELEN_FP_16):Ditto;
> >> (TARGET_VECTOR_ELEN_32): Ditto;
> >> (TARGET_VECTOR_ELEN_64): Ditto;
> >> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> >> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> >> (TARGET_VECTOR_ELEN_FP_16):Ditto;
> >>  (MASK_ZVBB):   Ditto;
> >> (MASK_ZVBC):   Ditto;
> >> (TARGET_ZVBB): Ditto;
> >> (TARGET_ZVBC): Ditto;
> >> (MASK_ZVKG):   Ditto;
> >> (MASK_ZVKNED): Ditto;
> >> (MASK_ZVKNHA): Ditto;
> >> (MASK_ZVKNHB): Ditto;
> >> (MASK_ZVKSED): Ditto;
> >> (MASK_ZVKSH):  Ditto;
> >> (MASK_ZVKN):   Ditto;
> >> (MASK_ZVKNC):  Ditto;
> >> (MASK_ZVKNG):  Ditto;
> >> (MASK_ZVKS):   Ditto;
> >> (MASK_ZVKSC):  Ditto;
> >> (MASK_ZVKSG):  Ditto;
> >> (MASK_ZVKT):   Ditto;
> >> (TARGET_ZVKG): Ditto;
> >> (TARGET_ZVKNED):   Ditto;
> >> (TARGET_ZVKNHA):   Ditto;
> >> (TARGET_ZVKNHB):   Ditto;
> >> (TARGET_ZVKSED):   Ditto;
> >> (TARGET_ZVKSH):Ditto;
> >> (TARGET_ZVKN): Ditto;
> >> (TARGET_ZVKNC):Ditto;
> >> (TARGET_ZVKNG):Ditto;
> >>

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

[Kito Cheng via Gcc-patches]

Reading the manual again, it seems I missed something in the manual
before, the MASK syntax already says we can specify Var to select the
variable other than target_flags, but I tried that not work when we
only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
Var(riscv_vector_elen_flags)" still using target_flags)

So maybe we should just fix that instead of extending the syntax?
e.g.
Mask(VECTOR_ELEN_32)Var(riscv_vector_elen_flags)
rather than
Mask(VECTOR_ELEN_32)in TargetVariable(riscv_vector_elen_flags)


On Wed, Sep 6, 2023 at 10:03 AM Feng Wang  wrote:
>
> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> generation" and add the new explanation in the options.texi.
> Please check the detail info on the
> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html;
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL):Ditto;
> (MASK_ZIHINTPAUSE):  Ditto;
> (TARGET_ZICSR):  Ditto;
> (TARGET_ZIFENCEI):   Ditto;
> (TARGET_ZIHINTNTL):  Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS):Ditto;
> (TARGET_ZAWRS):  Ditto;
> (MASK_ZBA):  Ditto;
> (MASK_ZBB):  Ditto;
> (MASK_ZBC):  Ditto;
> (MASK_ZBS):  Ditto;
> (TARGET_ZBA):Ditto;
> (TARGET_ZBB):Ditto;
> (TARGET_ZBC):Ditto;
> (TARGET_ZBS):Ditto;
> (MASK_ZFINX):Ditto;
> (MASK_ZDINX):Ditto;
> (MASK_ZHINX):Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX):  Ditto;
> (TARGET_ZDINX):  Ditto;
> (TARGET_ZHINX):  Ditto;
> (TARGET_ZHINXMIN):   Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR):  Ditto;
> (MASK_ZKSED):Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT):  Ditto;
> (TARGET_ZBKB):   Ditto;
> (TARGET_ZBKC):   Ditto;
> (TARGET_ZBKX):   Ditto;
> (TARGET_ZKNE):   Ditto;
> (TARGET_ZKND):   Ditto;
> (TARGET_ZKNH):   Ditto;
> (TARGET_ZKR):Ditto;
> (TARGET_ZKSED):  Ditto;
> (TARGET_ZKSH):   Ditto;
> (TARGET_ZKT):Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO):   Ditto;
> (MASK_VECTOR_ELEN_32):   Ditto;
> (MASK_VECTOR_ELEN_64):   Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>  (MASK_ZVBB):   Ditto;
> (MASK_ZVBC):   Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG):   Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH):  Ditto;
> (MASK_ZVKN):   Ditto;
> (MASK_ZVKNC):  Ditto;
> (MASK_ZVKNG):  Ditto;
> (MASK_ZVKS):   Ditto;
> (MASK_ZVKSC):  Ditto;
> (MASK_ZVKSG):  Ditto;
> (MASK_ZVKT):   Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED):   Ditto;
> (TARGET_ZVKNHA):   Ditto;
> (TARGET_ZVKNHB):   Ditto;
> (TARGET_ZVKSED):   Ditto;
> (TARGET_ZVKSH):Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC):Ditto;
> (TARGET_ZVKNG):Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC):Ditto;
> (TARGET_ZVKSG):Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B):Ditto;
> (MASK_ZVL256B):Ditto;
> (MASK_ZVL512B):Ditto;
> (MASK_ZVL1024B):   Ditto;
> (MASK_ZVL2048B):   Ditto;
> (MASK_ZVL4096B):   Ditto;
> (MASK_ZVL8192B):   Ditto;
> (MASK_ZVL16384B):  Ditto;
> (MASK_ZVL32768B):  Ditto;
> (MASK_ZVL65536B):  Ditto;
> (TARGET_ZVL32B):   Ditto;
> (TARGET_ZVL64B):   Ditto;
> (TARGET_ZVL128B):  Ditto;
> (TARGET_ZVL256B):  Ditto;
> (TARGET_ZVL512B):  Ditto;
> 

Re: [PATCH] RISC-V: Emit .note.GNU-stack for non-linux target as well

[Kito Cheng via Gcc-patches]

RISC-V qemu default that to false, which mean stack can't execute anything
by default, that's match RISC-V linux kernel behaviour, but the problem is
risc-v bare metal toolchain may execute code on stack *without* that tag,
that does not cause problems before for running tests on qemu user mode,
but...it causes problems once using newer qemu (with that patch).

Fangrui Song  於 2023年9月6日 週三 04:53 寫道：

> On Tue, Sep 5, 2023 at 5:14 AM Kito Cheng via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
>
>> committed, thanks :)
>>
>> On Tue, Sep 5, 2023 at 3:18 PM Jeff Law via Gcc-patches
>>  wrote:
>> >
>> >
>> >
>> > On 8/31/23 03:05, Kito Cheng wrote:
>> > > We only emit that on linux target before, that not problem before,
>> > > however Qemu has fix a bug to make qemu user mode honor
>> PT_GNU_STACK[1],
>> > > that will cause problem when we test baremetal with qemu.
>> > >
>> > > So the straightforward is enable that as well for non-linux toolchian,
>> > > the price is that will increase few bytes for each binary.
>> > >
>> > > [1]
>> https://github.com/qemu/qemu/commit/872f3d046f2381e3f416519e82df96bd60818311
>> > >
>> > > gcc/ChangeLog:
>> > >
>> > >   * config/riscv/linux.h (TARGET_ASM_FILE_END): Move ...
>> > >   * config/riscv/riscv.cc (TARGET_ASM_FILE_END): to here.
>> > OK.
>> > jeff
>>
>
> Does
> https://github.com/qemu/qemu/commit/872f3d046f2381e3f416519e82df96bd60818311
> use #define EXSTACK_DEFAULT true
> for riscv?
>
>
>
>
> --
> 宋方睿
>

Re: [PATCH] RISC-V: Emit .note.GNU-stack for non-linux target as well

[Kito Cheng via Gcc-patches]

committed, thanks :)

On Tue, Sep 5, 2023 at 3:18 PM Jeff Law via Gcc-patches
 wrote:
>
>
>
> On 8/31/23 03:05, Kito Cheng wrote:
> > We only emit that on linux target before, that not problem before,
> > however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
> > that will cause problem when we test baremetal with qemu.
> >
> > So the straightforward is enable that as well for non-linux toolchian,
> > the price is that will increase few bytes for each binary.
> >
> > [1] 
> > https://github.com/qemu/qemu/commit/872f3d046f2381e3f416519e82df96bd60818311
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/linux.h (TARGET_ASM_FILE_END): Move ...
> >   * config/riscv/riscv.cc (TARGET_ASM_FILE_END): to here.
> OK.
> jeff

Re: [PATCH 2/2] [RISC-V] Enalble zcmp for -Os

[Kito Cheng via Gcc-patches]

> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct riscv_frame_info 
> *frame)
>  {
>if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
>|| cfun->machine->interrupt_handler_p || cfun->machine->varargs_size 
> != 0
> -  || crtl->args.pretend_args_size != 0 || flag_shrink_wrap_separate
> +  || crtl->args.pretend_args_size != 0
> +  || (use_shrink_wrapping_separate ()
> + && !riscv_avoid_shrink_wrapping_separate ())

I think we should also check "!optimize_function_for_size_p (cfun)"
here, otherwise that does not really match what we claim in the commit
message.

e.g. it still will enable with -O2 -fno-shrink-wrap-separate

>|| (frame->mask & ~MULTI_PUSH_GPR_MASK))
>  return true;
>

Re: [PATCH v2] RISC-V: Optimize the MASK opt generation

[Kito Cheng via Gcc-patches]

Hi Feng:

Thanks for the simplification, that reduces the effort of adding a new
extension!
Functional part looks good, but I think we may document that new
syntax at gcc/gcc/doc/options.texi

On Thu, Aug 31, 2023 at 11:32 AM Feng Wang  wrote:
>
> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> generation". Please check the detail info on the
> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html;
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL):Ditto;
> (MASK_ZIHINTPAUSE):  Ditto;
> (TARGET_ZICSR):  Ditto;
> (TARGET_ZIFENCEI):   Ditto;
> (TARGET_ZIHINTNTL):  Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS):Ditto;
> (TARGET_ZAWRS):  Ditto;
> (MASK_ZBA):  Ditto;
> (MASK_ZBB):  Ditto;
> (MASK_ZBC):  Ditto;
> (MASK_ZBS):  Ditto;
> (TARGET_ZBA):Ditto;
> (TARGET_ZBB):Ditto;
> (TARGET_ZBC):Ditto;
> (TARGET_ZBS):Ditto;
> (MASK_ZFINX):Ditto;
> (MASK_ZDINX):Ditto;
> (MASK_ZHINX):Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX):  Ditto;
> (TARGET_ZDINX):  Ditto;
> (TARGET_ZHINX):  Ditto;
> (TARGET_ZHINXMIN):   Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR):  Ditto;
> (MASK_ZKSED):Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT):  Ditto;
> (TARGET_ZBKB):   Ditto;
> (TARGET_ZBKC):   Ditto;
> (TARGET_ZBKX):   Ditto;
> (TARGET_ZKNE):   Ditto;
> (TARGET_ZKND):   Ditto;
> (TARGET_ZKNH):   Ditto;
> (TARGET_ZKR):Ditto;
> (TARGET_ZKSED):  Ditto;
> (TARGET_ZKSH):   Ditto;
> (TARGET_ZKT):Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO):   Ditto;
> (MASK_VECTOR_ELEN_32):   Ditto;
> (MASK_VECTOR_ELEN_64):   Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>  (MASK_ZVBB):   Ditto;
> (MASK_ZVBC):   Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG):   Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH):  Ditto;
> (MASK_ZVKN):   Ditto;
> (MASK_ZVKNC):  Ditto;
> (MASK_ZVKNG):  Ditto;
> (MASK_ZVKS):   Ditto;
> (MASK_ZVKSC):  Ditto;
> (MASK_ZVKSG):  Ditto;
> (MASK_ZVKT):   Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED):   Ditto;
> (TARGET_ZVKNHA):   Ditto;
> (TARGET_ZVKNHB):   Ditto;
> (TARGET_ZVKSED):   Ditto;
> (TARGET_ZVKSH):Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC):Ditto;
> (TARGET_ZVKNG):Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC):Ditto;
> (TARGET_ZVKSG):Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B):Ditto;
> (MASK_ZVL256B):Ditto;
> (MASK_ZVL512B):Ditto;
> (MASK_ZVL1024B):   Ditto;
> (MASK_ZVL2048B):   Ditto;
> (MASK_ZVL4096B):   Ditto;
> (MASK_ZVL8192B):   Ditto;
> (MASK_ZVL16384B):  Ditto;
> (MASK_ZVL32768B):  Ditto;
> (MASK_ZVL65536B):  Ditto;
> (TARGET_ZVL32B):   Ditto;
> (TARGET_ZVL64B):   Ditto;
> (TARGET_ZVL128B):  Ditto;
> (TARGET_ZVL256B):  Ditto;
> (TARGET_ZVL512B):  Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> (TARGET_ZVL4096B): Ditto;
> (TARGET_ZVL8192B): Ditto;
> (TARGET_ZVL16384B):Ditto;
> (TARGET_ZVL32768B):Ditto;
> (TARGET_ZVL65536B):Ditto;
> (MASK_ZICBOZ): Ditto;
> (MASK_ZICBOM): Ditto;
> (MASK_ZICBOP): 

Re: [PATCH V5 0/3] RISC-V: Add an experimental vector calling convention

[Kito Cheng via Gcc-patches]

Thanks for fixing the issue! I guess I could find time tonight to do
the final round review and test :P then we could land this patch this
week.

On Tue, Sep 5, 2023 at 3:45 PM Lehua Ding  wrote:
>
> V5 change: Rebase and fix vsetvl testcase fail by change
> `(unspec [...] UNSPEC_CALLEE_CC)` to `(use (unspec [...] UNSPEC_CALLEE_CC))`.
> This change makes single_set function re-think call_insn as a
> single set pattern.
>
> Hi RISC-V folks,
>
> This patch implement the proposal of RISC-V vector calling convention[1] and
> this feature can be enabled by `--param=riscv-vector-abi` option. Currently,
> all vector type arguments and return values are pass by reference. With this
> patch, these arguments and return values can pass through vector registers.
> Currently only vector types defined in the RISC-V Vector Extension Intrinsic 
> Document[2]
> are supported. GNU-ext vector types are unsupported for now since the
> corresponding proposal was not presented.
>
> The proposal introduce a new calling convention variant, functions which 
> follow
> this variant need follow the bellow vector register convention.
>
> | Name| ABI Mnemonic | Meaning  | Preserved across 
> calls?
> =
> | v0  |  | Argument register| No
> | v1-v7   |  | Callee-saved registers   | Yes
> | v8-v23  |  | Argument registers   | No
> | v24-v31 |  | Callee-saved registers   | Yes
>
> If a functions follow this vector calling convention, then the function 
> symbole
> must be annotated with .variant_cc directive[3] (used to indicate that it is a
> calling convention variant).
>
> This implementation split into three parts, each part corresponds to a 
> sub-patch.
>
> - Part-1: Select suitable vector regsiters for vector type arguments and 
> return
>   values according to the proposal.
> - Part-2: Allocate frame area for callee-saved vector registers and 
> save/restore
>   them in prologue and epilogue.
> - Part-3: Generate .variant_cc directive for vector function in assembly code.
>
> [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389
> [2] 
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#type-system
> [3] 
> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops
>
> Best,
> Lehua
>
> Lehua Ding (3):
>   RISC-V: Part-1: Select suitable vector registers for vector type args
> and returns
>   RISC-V: Part-2: Save/Restore vector registers which need to be
> preversed
>   RISC-V: Part-3: Output .variant_cc directive for vector function
>
>  gcc/config/riscv/riscv-protos.h   |   4 +
>  gcc/config/riscv/riscv-sr.cc  |   8 +-
>  gcc/config/riscv/riscv-vector-builtins.cc |  10 +
>  gcc/config/riscv/riscv.cc | 484 --
>  gcc/config/riscv/riscv.h  |  43 ++
>  gcc/config/riscv/riscv.md |  51 +-
>  gcc/config/riscv/riscv.opt|   5 +
>  .../riscv/rvv/base/abi-call-args-1-run.c  | 127 +
>  .../riscv/rvv/base/abi-call-args-1.c  | 197 +++
>  .../riscv/rvv/base/abi-call-args-2-run.c  |  34 ++
>  .../riscv/rvv/base/abi-call-args-2.c  |  27 +
>  .../riscv/rvv/base/abi-call-args-3-run.c  | 260 ++
>  .../riscv/rvv/base/abi-call-args-3.c  | 116 +
>  .../riscv/rvv/base/abi-call-args-4-run.c  | 145 ++
>  .../riscv/rvv/base/abi-call-args-4.c  | 111 
>  .../riscv/rvv/base/abi-call-error-1.c |  11 +
>  .../riscv/rvv/base/abi-call-return-run.c  | 127 +
>  .../riscv/rvv/base/abi-call-return.c  | 197 +++
>  .../riscv/rvv/base/abi-call-variant_cc.c  |  39 ++
>  .../rvv/base/abi-callee-saved-1-fixed-1.c |  86 
>  .../rvv/base/abi-callee-saved-1-fixed-2.c |  86 
>  .../base/abi-callee-saved-1-save-restore.c|  85 +++
>  .../riscv/rvv/base/abi-callee-saved-1-zcmp.c  |  85 +++
>  .../riscv/rvv/base/abi-callee-saved-1.c   |  88 
>  .../base/abi-callee-saved-2-save-restore.c| 108 
>  .../riscv/rvv/base/abi-callee-saved-2-zcmp.c  | 107 
>  .../riscv/rvv/base/abi-callee-saved-2.c   | 117 +
>  27 files changed, 2709 insertions(+), 49 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c
>  

Re: [PATCH] RISC-V: Keep vlmax vector operators in simple form until split1 pass

[Kito Cheng via Gcc-patches]

Can those intermediate patterns be used for intrinsic? I would prefer
to keep those stuff *IF* possible used for intrinsics.

On Mon, Sep 4, 2023 at 7:14 PM Lehua Ding  wrote:
>
> This patch keep vlmax vector pattern in simple before split1 pass which
> will allow more optimization (e.g. combine) before split1 pass.
> This patch changes the vlmax pattern in autovec.md to define_insn_and_split
> as much as possible and clean up some combine patterns that are no longer 
> needed.
> This patch also fixed PR111232 bug which was caused by a combined failed.
>
> PR target/111232
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md 
> (@pred_single_widen_mul):
> Delete.
> (*pred_widen_mulsu): Delete.
> (*pred_single_widen_mul): Delete.
> (*dual_widen_):
> Add new combine patterns.
> (*single_widen_sub): Ditto.
> (*single_widen_add): Ditto.
> (*single_widen_mult): Ditto.
> (*dual_widen_mulsu): Ditto.
> (*dual_widen_mulus): Ditto.
> (*dual_widen_): Ditto.
> (*single_widen_add): Ditto.
> (*single_widen_sub): Ditto.
> (*single_widen_mult): Ditto.
> * config/riscv/autovec.md (3):
> Change define_expand to define_insn_and_split.
> (2): Ditto.
> (abs2): Ditto.
> (smul3_highpart): Ditto.
> (umul3_highpart): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testcases.
> * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr111232.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 294 --
>  gcc/config/riscv/autovec.md   |  82 +++--
>  .../gcc.target/riscv/rvv/autovec/pr111232.c   |  18 ++
>  .../riscv/rvv/autovec/widen/widen-4.c |   7 +-
>  .../rvv/autovec/widen/widen-complicate-4.c|  11 +-
>  5 files changed, 276 insertions(+), 136 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index d9863c76654..3aaee54f02a 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -18,67 +18,6 @@
>  ;; along with GCC; see the file COPYING3.  If not see
>  ;; .
>
> -;; We don't have vwmul.wv instruction like vwadd.wv in RVV.
> -;; This pattern is an intermediate RTL IR as a pseudo vwmul.wv to enhance
> -;; optimization of instructions combine.
> -(define_insn_and_split "@pred_single_widen_mul"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  
> "=,")
> -   (if_then_else:VWEXTI
> - (unspec:
> -   [(match_operand: 1 "vector_mask_operand"   
> "vmWc1,vmWc1")
> -(match_operand 5 "vector_length_operand"  "   rK,   
> rK")
> -(match_operand 6 "const_int_operand"  "i,
> i")
> -(match_operand 7 "const_int_operand"  "i,
> i")
> -(match_operand 8 "const_int_operand"  "i,
> i")
> -(reg:SI VL_REGNUM)
> -(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (mult:VWEXTI
> -   (any_extend:VWEXTI
> - (match_operand: 4 "register_operand" "   vr,   
> vr"))
> -   (match_operand:VWEXTI 3 "register_operand" "   vr,   
> vr"))
> - (match_operand:VWEXTI 2 "vector_merge_operand"   "   vu,
> 0")))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> -  {
> -insn_code icode = code_for_pred_vf2 (, mode);
> -rtx tmp = gen_reg_rtx (mode);
> -rtx ops[] = {tmp, operands[4]};
> -riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
> -
> -emit_insn (gen_pred (MULT, mode, operands[0], operands[1], 
> operands[2],
> -operands[3], tmp, operands[5], operands[6],
> -operands[7], operands[8]));
> -DONE;
> -  }
> -  [(set_attr "type" "viwmul")
> -   (set_attr "mode" "")])
> -
> -;; This pattern it to enchance the instruction combine optimizations for 
> complicate
> -;; sign and unsigned widening multiplication operations.
> -(define_insn "*pred_widen_mulsu"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  
> "=,")
> -   (if_then_else:VWEXTI
> - (unspec:
> -   [(match_operand: 1 "vector_mask_operand"   
> "vmWc1,vmWc1")
> -(match_operand 5 "vector_length_operand"  "   rK,   
> rK")
> -(match_operand 6 "const_int_operand"  "i,
> i")
> -(match_operand 7 "const_int_operand"  "i,
> i")
> -(match_operand 8 "const_int_operand"  "i,
> i")
> -(reg:SI VL_REGNUM)
> - 

Re: [PATCH v1] RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic

[Kito Cheng via Gcc-patches]

LGTM

On Mon, Sep 4, 2023 at 3:18 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to add FP16 support for the VRGATHEREI16
> intrinsic. Aka:
>
> * __riscv_vrgatherei16_vv_f16mf4
> * __riscv_vrgatherei16_vv_f16mf4_m
>
> As well as f16mf2 to f16m8 types.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat16mf4_t): Add FP16 intrinsic def.
> (vfloat16mf2_t): Ditto.
> (vfloat16m1_t): Ditto.
> (vfloat16m2_t): Ditto.
> (vfloat16m4_t): Ditto.
> (vfloat16m8_t): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-types.def |  9 ++
>  .../riscv/rvv/intrisinc-vrgatherei16.c| 28 +++
>  2 files changed, 37 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 1c3cc0eb222..6aa45ae9a7e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -689,11 +689,20 @@ DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
>  DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
>  DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
>  DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_EI16_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_EI16_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
> +
>  DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
> RVV_REQUIRE_MIN_VLEN_64)
>  DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
>  DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
>  DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
>  DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
> +
>  DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
>  DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
>  DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
> new file mode 100644
> index 000..59c6d7c887d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef _Float16 float16_t;
> +
> +vfloat16mf4_t test_vrgatherei16_vv_f16mf4(vfloat16mf4_t op1, vuint16mf4_t 
> op2,
> +  size_t vl) {
> +  return __riscv_vrgatherei16_vv_f16mf4(op1, op2, vl);
> +}
> +
> +vfloat16m8_t test_vrgatherei16_vv_f16m8(vfloat16m8_t op1, vuint16m8_t op2,
> +  size_t vl) {
> +  return __riscv_vrgatherei16_vv_f16m8(op1, op2, vl);
> +}
> +
> +vfloat16mf4_t test_vrgatherei16_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t 
> op1,
> +  vuint16mf4_t op2, size_t vl) {
> +  return __riscv_vrgatherei16_vv_f16mf4_m(mask, op1, op2, vl);
> +}
> +
> +vfloat16m8_t test_vrgatherei16_vv_f16m8_m(vbool2_t mask, vfloat16m8_t op1,
> +  vuint16m8_t op2, size_t vl) {
> +  return __riscv_vrgatherei16_vv_f16m8_m(mask, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times 
> {vrgatherei16.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Fix Zicond ICE on large constants

[Kito Cheng via Gcc-patches]

Maybe move the check logic a bit forward? My thought is the logic is
already specialized into a few catalogs, (imm, imm), (imm, reg), (reg,
reg)... and the logic you put is already in (imm, reg), but it should
really move into (reg, reg) case IMO? and move that forward we could
prevent add too much logic to redirect the case.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2db9c81ac8b..c84509c393b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3892,6 +3892,12 @@ riscv_expand_conditional_move (rtx dest, rtx
op, rtx cons, rtx alt)
 op1 = XEXP (op, 1);
   }

+  /* CONS might not fit into a signed 12 bit immediate suitable
+for an addi instruction.  If that's the case, force it into
+a register.  */
+  if (CONST_INT_P (cons) && !SMALL_OPERAND (INTVAL (cons)))
+   cons = force_reg (mode, cons);
+
  /* 0, reg or 0, imm */
  if (cons == CONST0_RTX (mode)
 && (REG_P (alt)

On Mon, Sep 4, 2023 at 8:21 AM Tsukasa OI via Gcc-patches
 wrote:
>
> From: Tsukasa OI 
>
> Large constant cons and/or alt will trigger ICEs building GCC target
> libraries (libgomp and libatomic) when the 'Zicond' extension is enabled.
>
> For instance, zicond-ice-2.c (new test case in this commit) will cause
> an ICE when SOME_NUMBER is 0x1000 or larger.  While opposite numbers
> corresponding cons/alt (two temp2 variables) are checked, cons/alt
> themselves are not checked and causing 2 ICEs building
> GCC target libraries as of this writing:
>
> 1.  gcc/libatomic/config/posix/lock.c
> 2.  gcc/libgomp/fortran.c
>
> Coercing a large value into a register will fix the issue.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_expand_conditional_move): Force
> large constant cons/alt into a register.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zicond-ice-2.c: New test.  This is based on
> an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c
> but heavily minimized.
> ---
>  gcc/config/riscv/riscv.cc | 16 ++--
>  gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 +++
>  2 files changed, 21 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8d8f7b4f16ed..cfaa4b6a7720 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3940,11 +3940,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
> cons, rtx alt)
>   rtx temp1 = gen_reg_rtx (mode);
>   rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode);
>
> - /* TEMP2 might not fit into a signed 12 bit immediate suitable
> -for an addi instruction.  If that's the case, force it into
> -a register.  */
> + /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
> +suitable for an addi instruction.  If that's the case, force it
> +into a register.  */
>   if (!SMALL_OPERAND (INTVAL (temp2)))
> temp2 = force_reg (mode, temp2);
> + if (!SMALL_OPERAND (INTVAL (cons)))
> +   cons = force_reg (mode, cons);
>
>   riscv_emit_binary (PLUS, temp1, alt, temp2);
>   emit_insn (gen_rtx_SET (dest,
> @@ -3986,11 +3988,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
> cons, rtx alt)
>   rtx temp1 = gen_reg_rtx (mode);
>   rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode);
>
> - /* TEMP2 might not fit into a signed 12 bit immediate suitable
> -for an addi instruction.  If that's the case, force it into
> -a register.  */
> + /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
> +suitable for an addi instruction.  If that's the case, force it
> +into a register.  */
>   if (!SMALL_OPERAND (INTVAL (temp2)))
> temp2 = force_reg (mode, temp2);
> + if (!SMALL_OPERAND (INTVAL (alt)))
> +   alt = force_reg (mode, alt);
>
>   riscv_emit_binary (PLUS, temp1, cons, temp2);
>   emit_insn (gen_rtx_SET (dest,
> diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c 
> b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
> new file mode 100644
> index ..ffd8dcb5814e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
> +
> +#define SOME_NUMBER 0x1000
> +
> +unsigned long
> +d (unsigned long n)
> +{
> +  return n > SOME_NUMBER ? SOME_NUMBER : n;
> +}
>
> base-commit: 78f636d979530c8a649262dbd44914bdfb6f7290
> --
> 2.42.0
>

Re: [PATCH v1] RISC-V: Support FP MAX/MIN autovec for VLS mode

[Kito Cheng via Gcc-patches]

Ok

Pan Li via Gcc-patches 於 2023年9月2日 週六，16:54寫道：

> From: Pan Li 
>
> This patch would like to allow the VLS mode autovec for the
> floating-point binary operation MAX/MIN.
>
> Given below code example:
>
> test (float *out, float *in1, float *in2)
> {
>   for (int i = 0; i < 128; i++)
> out[i] = in1[i] > in2[i] ? in1[i] : in2[i];
> // Or out[i] = fmax (in1[i], in2[i]);
> }
>
> Before this patch:
> test:
>   csrra4,vlenb
>   sllia4,a4,1
>   li  a5,128
>   bleua5,a4,.L2
>   mv  a5,a4
> .L2:
>   vsetvli zero,a5,e32,m8,ta,ma
>   vle32.v v16,0(a1)
>   vle32.v v8,0(a2)
>   vsetvli a3,zero,e32,m8,ta,ma
>   vmfgt.vvv0,v16,v8
>   vmerge.vvm  v8,v8,v16,v0
>   vsetvli zero,a5,e32,m8,ta,ma
>   vse32.v v8,0(a0)
>   ret
>
> After this patch:
> test:
>   li  a5,128
>   vsetvli zero,a5,e32,m1,ta,ma
>   vle32.v v1,0(a1)
>   vle32.v v2,0(a2)
>   vfmax.vvv1,v1,v2
>   vse32.v v1,0(a0)
>   ret
>
> This MAX/MIN autovec acts on function call like fmaxf/fmax in math.h
> too. And it depends on the option -ffast-math.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-vls.md (3): New pattern for
> fmax/fmin
> * config/riscv/vector.md: Add VLS modes to vfmax/vfmin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: New
> test.
> ---
>  gcc/config/riscv/autovec-vls.md   | 23 ++
>  gcc/config/riscv/vector.md| 12 +++---
>  .../gcc.target/riscv/rvv/autovec/vls/def.h| 16 +++
>  .../rvv/autovec/vls/floating-point-max-1.c| 43 +++
>  .../rvv/autovec/vls/floating-point-max-2.c| 43 +++
>  .../rvv/autovec/vls/floating-point-max-3.c| 43 +++
>  .../rvv/autovec/vls/floating-point-max-4.c| 43 +++
>  .../rvv/autovec/vls/floating-point-max-5.c| 31 +
>  .../rvv/autovec/vls/floating-point-min-1.c| 43 +++
>  .../rvv/autovec/vls/floating-point-min-2.c| 43 +++
>  .../rvv/autovec/vls/floating-point-min-3.c| 43 +++
>  .../rvv/autovec/vls/floating-point-min-4.c| 43 +++
>  .../rvv/autovec/vls/floating-point-min-5.c| 31 +
>  13 files changed, 451 insertions(+), 6 deletions(-)
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
>
> diff --git a/gcc/config/riscv/autovec-vls.md
> b/gcc/config/riscv/autovec-vls.md
> index 4ca640c11e2..7ef29637e33 100644
> --- a/gcc/config/riscv/autovec-vls.md
> +++ b/gcc/config/riscv/autovec-vls.md
> @@ -232,6 +232,29 @@ (define_insn_and_split "3"
>  [(set_attr "type" "vector")]
>  )
>
> +;;
> -
> +;; Includes:
> +;; - vfmin.vv/vfmax.vv
> +;; - vfmin.vf/vfmax.vf
> +;; - fmax/fmaxf in math.h
> +;;
> -
> +(define_insn_and_split "3"
> +  [(set (match_operand:VLSF 0 "register_operand")
> +(any_float_binop_nofrm:VLSF
> + (match_operand:VLSF 1 "")
> + (match_operand:VLSF 2 "")))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::emit_vlmax_insn (code_for_pred (, mode),
> +  

Re: [PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Aug 24, 2023 at 12:49 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be a case like below for intrinsic and autovec combination
>
> vfadd RTZ   <- intrinisc static rounding
> vfmadd  <- autovec/autovec-opt
>
> The autovec generated vfmadd should take DYN mode, and the
> frm must be restored before the vfmadd insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the vfmadd/vfmacc autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +
> | frrm  a5
> | ...
> | fsrmi 4
> | vfadd   <- intrinsic static rounding.
> | ...
> | fsrm  a5
> | vfmadd  <- autovec/autovec-opt
> | ...
> +
>
> However, we leverage unspec instead of use to consume the FRM register
> because there are some restrictions from the combine pass. Some code
> path of try_combine may require the XVECLEN(pat, 0) == 2 for the
> recog_for_combine, and add new use will make the XVECLEN(pat, 0) == 3
> and result in the vfwmacc optimization failure. For example, in the
> test  widen-complicate-5.c and widen-8.c
>
> Finally, there will be other fma cases and they will be covered in
> the underlying patches.
>
> Signed-off-by: Pan Li 
> Co-Authored-By: Ju-Zhe Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc.
> * config/riscv/autovec.md: Ditto.
> * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test.
> ---
>  gcc/config/riscv/autovec-opt.md   | 32 ---
>  gcc/config/riscv/autovec.md   | 26 +++---
>  gcc/config/riscv/vector-iterators.md  |  2 +
>  .../rvv/base/float-point-frm-autovec-1.c  | 88 +++
>  4 files changed, 125 insertions(+), 23 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 99b609a99d9..4b07e80ad95 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -459,12 +459,14 @@ (define_insn_and_split "*pred_single_widen_mul"
>  ;; vect__13.182_33 = .FMA (vect__11.180_35, vect__8.176_40, vect__4.172_45);
>  (define_insn_and_split "*double_widen_fma"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (float_extend:VWEXTF
> -   (match_operand: 2 "register_operand"))
> - (float_extend:VWEXTF
> -   (match_operand: 3 "register_operand"))
> - (match_operand:VWEXTF 1 "register_operand")))]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (float_extend:VWEXTF
> + (match_operand: 2 "register_operand"))
> +   (float_extend:VWEXTF
> + (match_operand: 3 "register_operand"))
> +   (match_operand:VWEXTF 1 "register_operand"))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -475,16 +477,19 @@ (define_insn_and_split "*double_widen_fma"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; This helps to match ext + fma.
>  (define_insn_and_split "*single_widen_fma"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (float_extend:VWEXTF
> -   (match_operand: 2 "register_operand"))
> - (match_operand:VWEXTF 3 "register_operand")
> - (match_operand:VWEXTF 1 "register_operand")))]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (float_extend:VWEXTF
> + (match_operand: 2 "register_operand"))
> +   (match_operand:VWEXTF 3 "register_operand")
> +   (match_operand:VWEXTF 1 "register_operand"))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -501,7 +506,8 @@ (define_insn_and_split "*single_widen_fma"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; -
>  ;;  [FP] VFWNMSAC
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index acca4c22b90..4894986d2a5 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1126,22 +1126,27 @@ (define_insn_and_split "*fnma"
>  (define_expand "fma4"
>[(parallel
>  [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> -   (match_operand:VF 1 "register_operand")
> -   (match_operand:VF 2 "register_operand")
> -   (match_operand:VF 3 

Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ   <- intrinisc static rounding
> vfmsub  <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode, and the
> frm must be restored before the vfmsub insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +
> | frrm  a5
> | ...
> | fsrmi 4
> | vfadd   <- intrinsic static rounding.
> | ...
> | fsrm  a5
> | vfmsub  <- autovec/autovec-opt
> | ...
> +
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
> ---
>  gcc/config/riscv/autovec-opt.md   | 36 
>  gcc/config/riscv/autovec.md   | 30 ---
>  .../rvv/base/float-point-frm-autovec-2.c  | 88 +++
>  3 files changed, 127 insertions(+), 27 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 4b07e80ad95..732a51edacd 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma"
>  ;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
>  (define_insn_and_split "*double_widen_fms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (float_extend:VWEXTF
> -   (match_operand: 2 "register_operand"))
> - (float_extend:VWEXTF
> -   (match_operand: 3 "register_operand"))
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (float_extend:VWEXTF
> + (match_operand: 2 "register_operand"))
> +   (float_extend:VWEXTF
> + (match_operand: 3 "register_operand"))
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; This helps to match ext + fms.
>  (define_insn_and_split "*single_widen_fms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (float_extend:VWEXTF
> -   (match_operand: 2 "register_operand"))
> - (match_operand:VWEXTF 3 "register_operand")
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (float_extend:VWEXTF
> + (match_operand: 2 "register_operand"))
> +   (match_operand:VWEXTF 3 "register_operand")
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; -
>  ;;  [FP] VFWNMACC
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4894986d2a5..d9f1a10eb66 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma"
>  (define_expand "fms4"
>[(parallel
>  [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> -   (match_operand:VF 1 "register_operand")
> -   (match_operand:VF 2 "register_operand")
> -   (neg:VF
> - (match_operand:VF 3 "register_operand"
> + (unspec:VF
> +   [(fma:VF
> + (match_operand:VF 1 "register_operand")
> + (match_operand:VF 2 "register_operand")
> + (neg:VF
> +   (match_operand:VF 3 "register_operand")))
> +(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
>   (clobber (match_dup 4))])]
>"TARGET_VECTOR"
>{
>  operands[4] = gen_reg_rtx (Pmode);
> -  })
> +  }
> +  [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  (define_insn_and_split "*fms"
> 

Re: [PATCH] RISC-V: Add Vector cost model framework for RVV

[Kito Cheng via Gcc-patches]

LGTM, Awesome!! It seems a sign of the next big move for RISC-V vectorization!

On Thu, Aug 31, 2023 at 8:36 PM Robin Dapp  wrote:
>
> OK.  As it doesn't do anything and we'll be needing it anyway no harm
> in adding it.
>
> Regards
>  Robin

Re: [PATCH V3 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed

[Kito Cheng via Gcc-patches]

Could you rebase the patch again, it seems got some conflict with zcmt
which I commit in the past few days...

On Wed, Aug 30, 2023 at 9:54 AM Lehua Ding  wrote:
>
> Because functions which follow vector calling convention variant has
> callee-saved vector reigsters but functions which follow standard calling
> convention don't have. We need to distinguish which function callee is so that
> we can tell GCC exactly which vector registers callee will clobber. So I 
> encode
> the callee's calling convention information into the calls rtx pattern like
> AArch64. The old operand 2 and 3 of call pattern which copy from MIPS target 
> are
> useless and removed according to my analysis.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-sr.cc 
> (riscv_remove_unneeded_save_restore_calls): Pass riscv_cc.
> * config/riscv/riscv.cc (struct riscv_frame_info): Add new fileds.
> (riscv_frame_info::reset): Reset new fileds.
> (riscv_call_tls_get_addr): Pass riscv_cc.
> (riscv_function_arg): Return riscv_cc for call patterm.
> (riscv_insn_callee_abi): Implement TARGET_INSN_CALLEE_ABI.
> (riscv_save_reg_p): Add vector callee-saved check.
> (riscv_save_libcall_count): Add vector save area.
> (riscv_compute_frame_info): Ditto.
> (riscv_restore_reg): Update for type change.
> (riscv_for_each_saved_v_reg): New function save vector registers.
> (riscv_first_stack_step): Handle funciton with vector callee-saved 
> registers.
> (riscv_expand_prologue): Ditto.
> (riscv_expand_epilogue): Ditto.
> (riscv_output_mi_thunk): Pass riscv_cc.
> (TARGET_INSN_CALLEE_ABI): Implement TARGET_INSN_CALLEE_ABI.
> * config/riscv/riscv.md: Add CALLEE_CC operand for call pattern.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: New test.
> * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: New test.
> * gcc.target/riscv/rvv/base/abi-callee-saved-1.c: New test.
> * gcc.target/riscv/rvv/base/abi-callee-saved-2.c: New test.
> ---
>  gcc/config/riscv/riscv-sr.cc  |  12 +-
>  gcc/config/riscv/riscv.cc | 222 +++---
>  gcc/config/riscv/riscv.md |  43 +++-
>  .../rvv/base/abi-callee-saved-1-fixed-1.c |  85 +++
>  .../rvv/base/abi-callee-saved-1-fixed-2.c |  85 +++
>  .../riscv/rvv/base/abi-callee-saved-1.c   |  87 +++
>  .../riscv/rvv/base/abi-callee-saved-2.c   | 117 +
>  7 files changed, 606 insertions(+), 45 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c
>
> diff --git a/gcc/config/riscv/riscv-sr.cc b/gcc/config/riscv/riscv-sr.cc
> index 7248f04d68f..e6e17685df5 100644
> --- a/gcc/config/riscv/riscv-sr.cc
> +++ b/gcc/config/riscv/riscv-sr.cc
> @@ -447,12 +447,18 @@ riscv_remove_unneeded_save_restore_calls (void)
>&& !SIBCALL_REG_P (REGNO (target)))
>  return;
>
> +  /* Extract RISCV CC from the UNSPEC rtx.  */
> +  rtx unspec = XVECEXP (callpat, 0, 1);
> +  gcc_assert (GET_CODE (unspec) == UNSPEC
> + && XINT (unspec, 1) == UNSPEC_CALLEE_CC);
> +  riscv_cc cc = (riscv_cc) INTVAL (XVECEXP (unspec, 0, 0));
>rtx sibcall = NULL;
>if (set_target != NULL)
> -sibcall
> -  = gen_sibcall_value_internal (set_target, target, const0_rtx);
> +sibcall = gen_sibcall_value_internal (set_target, target, const0_rtx,
> + gen_int_mode (cc, SImode));
>else
> -sibcall = gen_sibcall_internal (target, const0_rtx);
> +sibcall
> +  = gen_sibcall_internal (target, const0_rtx, gen_int_mode (cc, SImode));
>
>rtx_insn *before_call = PREV_INSN (call);
>remove_insn (call);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index aa6b46d7611..09c9e09e83a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -108,6 +108,9 @@ struct GTY(())  riscv_frame_info {
>/* Likewise FPR X.  */
>unsigned int fmask;
>
> +  /* Likewise for vector registers.  */
> +  unsigned int vmask;
> +
>/* How much the GPR save/restore routines adjust sp (or 0 if unused).  */
>unsigned save_libcall_adjustment;
>
> @@ -115,6 +118,10 @@ struct GTY(())  riscv_frame_info {
>poly_int64 gp_sp_offset;
>poly_int64 fp_sp_offset;
>
> +  /* Top and bottom offsets of vector save areas from frame bottom.  */
> +  poly_int64 v_sp_offset_top;
> +  poly_int64 v_sp_offset_bottom;
> +
>/* Offset of virtual frame pointer from stack pointer/frame bottom */
>poly_int64 frame_pointer_offset;
>
> @@ -265,7 +272,7 @@ unsigned 

Re: [PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Kito Cheng via Gcc-patches]

Ok, I just went through the patchlist and found this patch seems
not committed yet, anyway I will mark this as commit now :)


On Thu, Aug 31, 2023 at 5:14 PM Tsukasa OI via Gcc-patches
 wrote:
>
> On 2023/08/31 18:10, Kito Cheng wrote:
> > Hi Tsukasa:
> >
> > I guess you might did something wrong during commit this patch and
> > "RISC-V: Add stub support for existing extensions"
> >
> > https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
> >
>
> It's fine.  That patch was a part of "RISC-V: Add stub support for
> existing extensions" (the only intent for subset submission was faster
> review but the bigger one is accepted earlier than I expected).
>
> Tsukasa

Re: [PATCH] RISC-V: Change vsetvl tail and mask policy to default policy

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Aug 31, 2023 at 5:07 PM Lehua Ding  wrote:
>
> This patch change the vsetvl policy to default policy
> (returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
> fixed policy. Any policy is now returned, allowing change to agnostic
> or undisturbed. In the future, users may be able to control the default
> policy, such as keeping agnostic by compiler options.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here.
> * config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx):
> Change to default policy.
> * config/riscv/riscv-vector-builtins-bases.cc: Change to default 
> policy.
> * config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete.
> * config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to 
> test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust.
> * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test.
>
> ---
>  gcc/config/riscv/riscv-protos.h   |  3 +++
>  gcc/config/riscv/riscv-v.cc   |  4 +++-
>  gcc/config/riscv/riscv-vector-builtins-bases.cc   |  8 
>  gcc/config/riscv/riscv-vsetvl.h   |  2 --
>  gcc/config/riscv/riscv.cc |  3 +--
>  .../riscv/rvv/base/binop_vx_constraint-171.c  |  4 ++--
>  .../riscv/rvv/base/binop_vx_constraint-173.c  |  4 ++--
>  gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 11 +++
>  8 files changed, 26 insertions(+), 13 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 92e30a10f3c..e145ee6c69b 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -406,6 +406,9 @@ enum mask_policy
>MASK_ANY = 2,
>  };
>
> +/* Return true if VALUE is agnostic or any policy.  */
> +#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
> +
>  enum class reduction_type
>  {
>UNORDERED,
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 427700192a3..6228ff3d92e 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -1672,9 +1672,11 @@ static rtx
>  gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl)
>  {
>unsigned int sew = get_sew (vmode);
> +  rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode);
> +  rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode);
>return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, 
> Pmode),
>  gen_int_mode (get_vlmul (vmode), Pmode),
> -const0_rtx, const0_rtx);
> +tail_policy, mask_policy);
>  }
>
>  /* GET VL * 2 rtx.  */
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 54582ee130c..8e679f72392 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -139,11 +139,11 @@ public:
>  /* LMUL.  */
>  e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode));
>
> -/* TA.  */
> -e.add_input_operand (Pmode, gen_int_mode (1, Pmode));
> +/* TAIL_ANY.  */
> +e.add_input_operand (Pmode, gen_int_mode (get_prefer_tail_policy (), 
> Pmode));
>
> -/* MU.  */
> -e.add_input_operand (Pmode, gen_int_mode (0, Pmode));
> +/* MASK_ANY.  */
> +e.add_input_operand (Pmode, gen_int_mode (get_prefer_mask_policy (), 
> Pmode));
>  return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode));
>}
>  };
> diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
> index 2a315e45f31..53549abfac5 100644
> --- a/gcc/config/riscv/riscv-vsetvl.h
> +++ b/gcc/config/riscv/riscv-vsetvl.h
> @@ -21,8 +21,6 @@ along with GCC; see the file COPYING3.  If not see
>  #ifndef GCC_RISCV_VSETVL_H
>  #define GCC_RISCV_VSETVL_H
>
> -#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
> -
>  namespace riscv_vector {
>
>  /* Classification of vsetvl instruction.  */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index d84fa2311fa..8bca8075713 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5246,8 +5246,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
> else if (code == CONST_INT)
>   {
> /* Tail && Mask policy.  */
> -   bool agnostic_p = UINTVAL (op) & 0x1;
> -   asm_fprintf (file, "%s", agnostic_p ? "a" : "u");
> +   asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
>   }
> else
>   output_operand_lossage ("invalid vector 

Re: [PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Kito Cheng via Gcc-patches]

Hi Tsukasa:

I guess you might did something wrong during commit this patch and
"RISC-V: Add stub support for existing extensions"

https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942

On Tue, Aug 29, 2023 at 4:55 PM Tsukasa OI via Gcc-patches
 wrote:
>
> On 2023/08/29 17:42, Kito Cheng wrote:
> > LGTM, did you have commit access for GCC repo? you should obtain it if
> > you don't have it yet, I think you are already an important member of
> > the RISC-V GNU toolchain community :)
>
> Not yet (only Binutils/GDB).  Jeff is mainly merging my changes to the
> trunk so far.
>
> Thanks for mentioning and sponsoring me for write access to GCC.  I
> truly appreciate that mentioning me as an important member and write
> access to the GCC repository will be also helpful.
>
> I'll contact GCC overseers later.
>
> Sincerely,
> Tsukasa
>
> >
> > https://gcc.gnu.org/gitwrite.html#authenticated , and you can add me
> > to the cc list as your sponsor.
> >
> >
> >
> > On Tue, Aug 29, 2023 at 11:42 AM Tsukasa OI via Gcc-patches
> >  wrote:
> >>
> >> From: Tsukasa OI 
> >>
> >> As the specification states, the 'Zcmt' extension depends on the 'Zca' and
> >> 'Zicsr' extensions.  This commit reflects this implication.
> >>
> >> gcc/ChangeLog:
> >>
> >> * common/config/riscv/riscv-common.cc
> >> (riscv_implied_info): Add implication from 'Zcmt' to 'Zicsr'.
> >> ---
> >>  gcc/common/config/riscv/riscv-common.cc | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> >> b/gcc/common/config/riscv/riscv-common.cc
> >> index a5b62cda3a09..1315c8a745ec 100644
> >> --- a/gcc/common/config/riscv/riscv-common.cc
> >> +++ b/gcc/common/config/riscv/riscv-common.cc
> >> @@ -142,6 +142,7 @@ static const riscv_implied_info_t riscv_implied_info[] 
> >> =
> >>{"zcb",  "zca"},
> >>{"zcmp", "zca"},
> >>{"zcmt", "zca"},
> >> +  {"zcmt", "zicsr"},
> >>
> >>{NULL, NULL}
> >>  };
> >> --
> >> 2.42.0
> >>
> >

[PATCH] RISC-V: Emit .note.GNU-stack for non-linux target as well

[Kito Cheng via Gcc-patches]

We only emit that on linux target before, that not problem before,
however Qemu has fix a bug to make qemu user mode honor PT_GNU_STACK[1],
that will cause problem when we test baremetal with qemu.

So the straightforward is enable that as well for non-linux toolchian,
the price is that will increase few bytes for each binary.

[1] https://github.com/qemu/qemu/commit/872f3d046f2381e3f416519e82df96bd60818311

gcc/ChangeLog:

* config/riscv/linux.h (TARGET_ASM_FILE_END): Move ...
* config/riscv/riscv.cc (TARGET_ASM_FILE_END): to here.
---
 gcc/config/riscv/linux.h  | 2 --
 gcc/config/riscv/riscv.cc | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
index 3e625e0f867..7323ff30f70 100644
--- a/gcc/config/riscv/linux.h
+++ b/gcc/config/riscv/linux.h
@@ -59,8 +59,6 @@ along with GCC; see the file COPYING3.  If not see
   -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
 %{static:-static}}"
 
-#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
-
 #define STARTFILE_PREFIX_SPEC  \
"/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
"/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "  \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5dc303f89c7..2b3ab862816 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9098,6 +9098,8 @@ riscv_frame_pointer_required (void)
 #define TARGET_ASM_FILE_START riscv_file_start
 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
 #undef TARGET_EXPAND_BUILTIN_VA_START
 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
-- 
2.40.1

Re: [PATCH] RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions

[Kito Cheng via Gcc-patches]

Thanks for the cleanup, the new interface is really much simpler than before!

Only few minor comment, you can go ahead to commit that after address
those comment.

(OK, I don't want to review whole patch again, it's really huge change :P

>
> -  void set_rounding_mode (enum floating_point_rounding_mode mode)
> +  void check_insn_flags ()

void check_insn_flags () const

>void emit_insn (enum insn_code icode, rtx *ops)
>{
>  int opno = 0;
> +int num_ops = 0;
>  /* It's true if any operand is memory operand.  */
>  bool any_mem_p = false;
> -/* It's true if all operands are mask operand.  */
> -bool all_mask_p = true;
> -if (m_has_dest_p)
> +
> +/* Add dest operand.  */
> +if (m_insn_flags & HAS_DEST_P)
>{
> any_mem_p |= MEM_P (ops[opno]);
> -   all_mask_p &= GET_MODE_CLASS (GET_MODE (ops[opno])) == 
> MODE_VECTOR_BOOL;
> add_output_operand (ops[opno++], m_dest_mode);
> +   num_ops += 1;

Drop this

>}
>
> -if (m_fully_unmasked_p)
> +/* Add mask operand.  */
> +if (m_insn_flags & USE_ONE_TRUE_MASK_P)
> +  add_input_operand (gen_scalar_move_mask (m_mask_mode), m_mask_mode);
> +else if (m_insn_flags & USE_ALL_TRUES_MASK_P)
>add_all_one_mask_operand ();
> +else if (m_insn_flags & HAS_MASK_P)
> +  {
> +   machine_mode mode = insn_data[(int) icode].operand[m_opno].mode;
> +   gcc_assert (mode != VOIDmode);
> +   add_input_operand (ops[opno++], mode);
> +   num_ops += 1;
> +  }

Drop this

> -if (!m_use_real_merge_p)
> +/* Add merge operand.  */
> +if (m_insn_flags & USE_VUNDEF_MERGE_P)
>add_vundef_operand ();
> +else if (m_insn_flags & HAS_MERGE_P)
> +  {
> +   machine_mode mode = insn_data[(int) icode].operand[m_opno].mode;
> +   gcc_assert (mode != VOIDmode);
> +   add_input_operand (ops[opno++], mode);
> +   num_ops += 1;
> +  }
> +
> +if (m_insn_flags & NULLARY_OP_P)
> +  num_ops += 0;
> +else if (m_insn_flags & UNARY_OP_P)
> +  num_ops += 1;
> +else if (m_insn_flags & BINARY_OP_P)
> +  num_ops += 2;
> +else if (m_insn_flags & TERNARY_OP_P)
> +  num_ops += 3;

num_ops = rather than += here.

> +else
> +  gcc_unreachable ();
>
> -for (; opno < m_op_num; opno++)
> +/* Add the remain operands.  */
> +for (; opno < num_ops; opno++)

for (;num_ops;num_ops--, opno++)

>{
> any_mem_p |= MEM_P (ops[opno]);
> -   all_mask_p &= GET_MODE_CLASS (GET_MODE (ops[opno])) == 
> MODE_VECTOR_BOOL;
> machine_mode mode = insn_data[(int) icode].operand[m_opno].mode;
> /* 'create_input_operand doesn't allow VOIDmode.
>According to vector.md, we may have some patterns that do not have
> @@ -194,46 +251,51 @@ public:
> add_input_operand (ops[opno], mode);
>}
>
> -if (m_needs_avl_p)
> +/* Add vl operand.  */
> +rtx len = m_vl_op;
> +machine_mode mode = VECTOR_MODE_P (m_dest_mode) ? m_dest_mode : 
> m_mask_mode;
> +if (m_vlmax_p)
>{
> -   rtx len = m_vl_op;
> -   machine_mode mode
> - = VECTOR_MODE_P (m_dest_mode) ? m_dest_mode : m_mask_mode;
> -   if (m_vlmax_p)
> +   if (riscv_v_ext_vls_mode_p (mode))
> + {
> +   /* VLS modes always set VSETVL by
> +  "vsetvl zero, rs1/imm".  */
> +   poly_uint64 nunits = GET_MODE_NUNITS (mode);
> +   len = gen_int_mode (nunits, Pmode);
> +   if (!satisfies_constraint_K (len))
> + len = force_reg (Pmode, len);
> +   m_vlmax_p = false;
> + }
> +   else if (const_vlmax_p (mode))
> + {
> +   /* Optimize VLS-VLMAX code gen, we can use vsetivli instead of
> +  the vsetvli to obtain the value of vlmax.  */
> +   poly_uint64 nunits = GET_MODE_NUNITS (mode);
> +   len = gen_int_mode (nunits, Pmode);
> +   m_vlmax_p = false;
> + }
> +   else if (can_create_pseudo_p ())
>   {
> -   if (riscv_v_ext_vls_mode_p (mode))
> - {
> -   /* VLS modes always set VSETVL by
> -  "vsetvl zero, rs1/imm".  */
> -   poly_uint64 nunits = GET_MODE_NUNITS (mode);
> -   len = gen_int_mode (nunits, Pmode);
> -   if (!satisfies_constraint_K (len))
> - len = force_reg (Pmode, len);
> -   m_vlmax_p = false; /* It has became NONVLMAX now.  */
> - }
> -   else if (const_vlmax_p (mode))
> - {
> -   /* Optimize VLS-VLMAX code gen, we can use vsetivli instead of
> -  the vsetvli to obtain the value of vlmax.  */
> -   poly_uint64 nunits = GET_MODE_NUNITS (mode);
> -   len = gen_int_mode (nunits, Pmode);
> -   m_vlmax_p = false; /* It has became NONVLMAX now.  */
> - }
> -   else if (can_create_pseudo_p ())
> -   

Re: [PATCH] RISC-V: Fix vsetvl pass ICE

[Kito Cheng via Gcc-patches]

OK for gcc 13 branch too, the general rule for backport is to wait one
week on trunk to make sure the fix is stable.


On Thu, Aug 31, 2023 at 8:08 AM juzhe.zh...@rivai.ai
 wrote:
>
> Ok for trunk. But not sure whether it's ok for GCC-13.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date: 2023-08-30 17:51
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
>
> PR target/111234
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc  |  2 +-
> .../gcc.target/riscv/rvv/vsetvl/pr111234.c| 19 +++
> 2 files changed, 20 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 1386d9250ca..a81bb53a521 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info 
> ,
>  new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
>else
>  {
> -  if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
> +  if (vsetvl_insn_p (rinsn))
> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
>else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> new file mode 100644
> index 000..ee5eec4a257
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> @@ -0,0 +1,19 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include 
> +
> +void
> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
> +{
> +  vint32m1_t va = *in;
> +  vbool32_t mask = *m;
> +  vint64m2_t vb
> += __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
> +  vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
> +
> +  if (b != 0)
> +vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 
> ());
> +
> +  *out = vc;
> +}
> --
> 2.36.3
>

Re: [PATCH 0/3] [RISC-V] support zcmp extension

[Kito Cheng via Gcc-patches]

Pass regression without introducing any new fail, push to trunk :)

On Tue, Aug 29, 2023 at 4:39 PM Fei Gao  wrote:
>
> Fei Gao (3):
>   [RISC-V] support cm.push cm.pop cm.popret in zcmp
>   [RISC-V] support cm.popretz in zcmp
>   [RISC-V] support cm.mva01s cm.mvsa01 in zcmp
>
>  gcc/config/riscv/iterators.md |   15 +
>  gcc/config/riscv/peephole.md  |   28 +
>  gcc/config/riscv/predicates.md|  107 ++
>  gcc/config/riscv/riscv-protos.h   |2 +
>  gcc/config/riscv/riscv.cc |  499 +-
>  gcc/config/riscv/riscv.h  |   25 +
>  gcc/config/riscv/riscv.md |4 +
>  gcc/config/riscv/zc.md| 1457 +
>  gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c   |   23 +
>  gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c   |  269 +++
>  gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c   |  269 +++
>  .../gcc.target/riscv/zcmp_push_fpr.c  |   34 +
>  .../gcc.target/riscv/zcmp_stack_alignment.c   |   24 +
>  13 files changed, 2705 insertions(+), 51 deletions(-)
>  create mode 100644 gcc/config/riscv/zc.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cm_mv_rv32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c
>
> --
> 2.17.1
>

Re: [PATCH] RISC-V: Document some -march special cases

[Kito Cheng via Gcc-patches]

I would prefer NOT to expose those --param on user manual since
generally those options are used for internal only, we should add -m
option and enable `--param=riscv-autovec-preference=scalable` by
default once we think it's stable enough.

On Wed, Aug 30, 2023 at 1:04 PM Palmer Dabbelt  wrote:
>
> Vineet just got bit by the autovec params, and a bunch of us forgot
> about the second one.
>
> gcc/ChangeLog:
>
> * doc/invoke.texi (RISC-V Options): Add some -march special
> cases.
> ---
>  gcc/doc/invoke.texi | 20 
>  1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index a32dabf0405..4a6cad21dcb 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -29242,10 +29242,22 @@ The default is @option{-misa-spec=20191213} unless 
> GCC has been configured
>  with @option{--with-isa-spec=} specifying a different default version.
>
>  @opindex march
> -@item -march=@var{ISA-string}
> -Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}).  ISA strings must 
> be
> -lower-case.  Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and
> -@samp{rv32imaf}.
> +@item -march=@var{subtarget}
> +Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}).  The 
> @var{subtarget}
> +string is similar to an ISA string, but has various subtle differences.
> +@var{subtarget} strings must be lower case.  Extension ordering and
> +dependencies may differ from the specification.  Additionally, the following
> +extensions are special cases:
> +@table @code
> +@item V
> +Enabling the V extension does not enable autovecorization, users must select
> +either @samp{--param=riscv-autovec-preference=scalable} or
> +@samp{--param=riscv-autovec-preference=fixed-vlmax} to decide between VLA and
> +VLS autovectorization.
> +@item Zihintpause
> +This extension is always enabled.
> +@end table
> +Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and 
> @samp{rv32imaf}.
>
>  When @option{-march=} is not specified, use the setting from @option{-mcpu}.
>
> --
> 2.41.0
>

Re: [PATCH] RISC-V: Make sure we get VL REG operand for VLMAX vsetvl

[Kito Cheng via Gcc-patches]

Lgtm

Juzhe-Zhong 於 2023年8月30日 週三，10:22寫道：

> Fix ICE in "vect" testsuite:
>
> FAIL: gcc.dg/vect/pr64495.c (internal compiler error: in df_uses_record,
> at df-scan.cc:2958)
> FAIL: gcc.dg/vect/pr64495.c (test for excess errors
>
> After this patch, all current found VSETVL PASS related bugs in "vect" are
> fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc
> (vector_insn_info::get_avl_or_vl_reg): Fix bug.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 73d672b083b..1386d9250ca 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2300,18 +2300,26 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl
> ()))
> -return ::get_vl (get_insn ()->rtl ());
> -
>if (get_avl_source ())
>  return get_avl_reg_rtx ();
>
> +  rtx_insn *rinsn = get_insn ()->rtl ();
> +  if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
> +{
> +  rtx vl = ::get_vl (rinsn);
> +  /* For VLMAX, we should make sure we get the
> +REG to emit 'vsetvl VL,zero' since the 'VL'
> +should be the REG according to RVV ISA.  */
> +  if (REG_P (vl))
> +   return vl;
> +}
> +
>/* A DIRTY (polluted EMPTY) block if:
> - get_insn is scalar move (no AVL or VL operand).
> - get_avl_source is null (no def in the current DIRTY block).
>   Then we trace the previous insn which must be the insn
>   already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ());
> +  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
>gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
>return ::get_vl (prev_rinsn);
>  }
> --
> 2.36.3
>
>

Re: [PATCH] RISC-V: Enable movmisalign for VLS modes

[Kito Cheng via Gcc-patches]

> +/* To support misalign data movement, we should use
> +   minimum element alignment load/store.  */
> +unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (mode));
> +poly_int64 nunits = GET_MODE_NUNITS (mode) * size;
> +machine_mode mode = riscv_vector::get_vector_mode (QImode, 
> nunits).require ();
> +operands[0] = gen_lowpart (mode, operands[0]);
> +operands[1] = gen_lowpart (mode, operands[1]);
> +if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
> +  operands[1] = force_reg (mode, operands[1]);

Does force_reg safe for movmisalign?

Re: [PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5

[Kito Cheng via Gcc-patches]

LGTM, thanks :)

On Tue, Aug 29, 2023 at 6:50 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be one ICE when build vect-multitypes-5.c similar as below:
>
> riscv64-unknown-elf-gcc -O3 \
>   -march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \
>   -fdiagnostics-plain-output -flto -ffat-lto-objects \
>   --param riscv-autovec-preference=scalable -Wno-psabi \
>   -ftree-vectorize -fno-tree-loop-distribute-patterns \
>   -fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \
>   gcc/testsuite/gcc.dg/vect/vect-multitypes-5.c -o test.elf -lm
>
> The below RTL is not well handled in riscv_legitimize_const_move, and
> then fall through to the default pass. Then the
> default force_const_mem will NULL_RTX, and will have ICE when operating
> one the NULL_RTX.
>
> (const:DI
>   (plus:DI
> (symbol_ref:DI ("ic") [flags 0x2] )
> (const_poly_int:DI [16, 16])))
>
> This patch would like to take care of this rtl in riscv_legitimize_const_move.
>
> Signed-off-by: Pan Li 
> Co-Authored-By: Ju-Zhe Zhong 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration.
> (riscv_legitimize_const_move): Handle ref plus const poly.
> ---
>  gcc/config/riscv/riscv.cc | 23 +++
>  1 file changed, 23 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 1d6e278ea90..bab6ed70b2d 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -366,6 +366,7 @@ static const struct riscv_tune_param 
> optimize_size_tune_info = {
>
>  static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
>  static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
> +static void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx);
>
>  /* Defining target-specific uses of __attribute__.  */
>  static const struct attribute_spec riscv_attribute_table[] =
> @@ -2118,6 +2119,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx 
> dest, rtx src)
>return;
>  }
>
> +  /* Handle below format.
> + (const:DI
> +   (plus:DI
> +(symbol_ref:DI ("ic") [flags 0x2] ) <- 
> op_0
> +(const_poly_int:DI [16, 16]) // <- op_1
> + ))
> +   */
> +  rtx src_op_0 = XEXP (src, 0);
> +
> +  if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS
> +&& CONST_POLY_INT_P (XEXP (src_op_0, 1)))
> +{
> +  rtx dest_tmp = gen_reg_rtx (mode);
> +  rtx tmp = gen_reg_rtx (mode);
> +
> +  riscv_emit_move (dest, XEXP (src_op_0, 0));
> +  riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1));
> +
> +  emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp)));
> +  return;
> +}
> +
>src = force_const_mem (mode, src);
>
>/* When using explicit relocs, constant pool references are sometimes
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Implement TLS Descriptors.

[Kito Cheng via Gcc-patches]

Hi Tatsuyuki:

Thanks your TLS desc implementation, it's looks already in good shape
now! just few minor comment :)


> @@ -121,6 +121,14 @@
> (T1_REGNUM  6)
> (S0_REGNUM  8)
> (S1_REGNUM  9)
> +   (A0_REGNUM  10)
> +   (A1_REGNUM  11)
> +   (A2_REGNUM  12)
> +   (A3_REGNUM  13)
> +   (A4_REGNUM  14)
> +   (A5_REGNUM  15)
> +   (A6_REGNUM  16)
> +   (A7_REGNUM  17)

Drop A1_REGNUM~A7_REGNUM, they seems unused.

> (S2_REGNUM  18)
> (S3_REGNUM  19)
> (S4_REGNUM  20)
> @@ -1869,6 +1877,18 @@
>[(set_attr "got" "load")
> (set_attr "mode" "")])
>
> +(define_insn "tlsdesc"

You can add @ to the pattern name ("@tlsdesc"), then you can
simplify riscv_legitimize_tls_address like that:

@@ -1908,7 +1898,7 @@ riscv_legitimize_tls_address (rtx loc)
 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
 dest = gen_reg_rtx (Pmode);

- emit_insn (riscv_tlsdesc (loc, GEN_INT (seqno)));
+ emit_insn (gen_tlsdesc (Pmode, loc, GEN_INT (seqno)));
 emit_insn (gen_add3_insn (dest, a0, tp));
 seqno++;
   }

> +  [(set (reg:P A0_REGNUM)
> +   (unspec:P
> +   [(match_operand:P 0 "symbolic_operand" "")
> + (match_operand:P 1 "const_int_operand")]
> +   UNSPEC_TLSDESC))
> +   (clobber (reg:SI T0_REGNUM))]
> +  "TARGET_TLSDESC"
> +  ".LT%1: auipc\ta0, 
> %%tlsdesc_hi(%0)\;\tt0,%%tlsdesc_load_lo(.LT%1)(a0)\;addi\ta0,a0,%%tlsdesc_add_lo(.LT%1)\;jalr\tt0,t0,%%tlsdesc_call(.LT%1)"

I would suggest using return rather than single long line, like below,
that would be easier to read :
{
 return ".LT%1: auipc\ta0, %%tlsdesc_hi(%0)\;"
"\tt0,%%tlsdesc_load_lo(.LT%1)(a0)\;"
"addi\ta0,a0,%%tlsdesc_add_lo(.LT%1)\;"
"jalr\tt0,t0,%%tlsdesc_call(.LT%1)"
}


> +  [(set_attr "type" "multi")

We need add length here, something like that: "(set_attr "length"
(const_int 16))"

> +   (set_attr "mode" "")])
> +
>  (define_insn "auipc"
>[(set (match_operand:P   0 "register_operand" "=r")
> (unspec:P
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 6304efebfd5..40b3ebf2a99 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -311,3 +311,17 @@ Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
>  -param=riscv-autovec-lmul=
>  Target RejectNegative Joined Enum(riscv_autovec_lmul) 
> Var(riscv_autovec_lmul) Init(RVV_M1)
>  -param=riscv-autovec-lmul= Set the RVV LMUL of 
> auto-vectorization in the RISC-V port.
> +
> +Enum
> +Name(tls_type) Type(enum riscv_tls_type)
> +The possible TLS dialects:
> +
> +EnumValue
> +Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)
> +
> +EnumValue
> +Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)
> +
> +mtls-dialect=
> +Target RejectNegative Joined Enum(tls_type) Var(riscv_tls_dialect) 
> Init(TLS_TRADITIONAL) Save

Could you add a configure option `--with-tls` to control the default
TLS dialect?

You can reference ARM:
gcc/gcc/config/arm/arm.h: grep "OPTION_DEFAULT_SPECS"
gcc/gcc/config.gcc: grep "with_tls"

> +Specify TLS dialect.
> \ No newline at end of file
> --
> 2.34.1
>

Re: [PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Kito Cheng via Gcc-patches]

LGTM, did you have commit access for GCC repo? you should obtain it if
you don't have it yet, I think you are already an important member of
the RISC-V GNU toolchain community :)

https://gcc.gnu.org/gitwrite.html#authenticated , and you can add me
to the cc list as your sponsor.



On Tue, Aug 29, 2023 at 11:42 AM Tsukasa OI via Gcc-patches
 wrote:
>
> From: Tsukasa OI 
>
> As the specification states, the 'Zcmt' extension depends on the 'Zca' and
> 'Zicsr' extensions.  This commit reflects this implication.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_implied_info): Add implication from 'Zcmt' to 'Zicsr'.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index a5b62cda3a09..1315c8a745ec 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -142,6 +142,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"zcb",  "zca"},
>{"zcmp", "zca"},
>{"zcmt", "zca"},
> +  {"zcmt", "zicsr"},
>
>{NULL, NULL}
>  };
> --
> 2.42.0
>

Re: [PATCH] RISC-V: Fix AVL/VL get ICE[VSETVL PASS]

[Kito Cheng via Gcc-patches]

Assuming prev is vsetvli instruction is kind of a strong assumption,
but it is guarded with gcc_assert, so it is a reasonable fix to me,
LGTM :)

On Tue, Aug 29, 2023 at 10:37 AM Juzhe-Zhong  wrote:
>
> Fix bunch of ICE in "vect" testsuite:
> FAIL: gcc.dg/vect/vect-alias-check-16.c (internal compiler error: 
> Segmentation fault)
> FAIL: gcc.dg/vect/vect-alias-check-16.c (test for excess errors)
> FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (internal 
> compiler error: Segmentation fault)
> FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (test for 
> excess errors)
> FAIL: gcc.dg/vect/vect-alias-check-20.c (internal compiler error: 
> Segmentation fault)
> FAIL: gcc.dg/vect/vect-alias-check-20.c (test for excess errors)
> FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (internal 
> compiler error: Segmentation fault)
> FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (test for 
> excess errors)
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): 
> New function.
> (pass_vsetvl::compute_local_properties): Fix bug.
> (pass_vsetvl::commit_vsetvls): Ditto.
> * config/riscv/riscv-vsetvl.h: New function.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 46 +---
>  gcc/config/riscv/riscv-vsetvl.h  |  1 +
>  2 files changed, 31 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index f7ae6c16bee..73d672b083b 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2290,6 +2290,32 @@ vector_insn_info::global_merge (const vector_insn_info 
> _info,
>return new_info;
>  }
>
> +/* Wrapper helps to return the AVL or VL operand for the
> +   vector_insn_info. Return AVL if the AVL is not VLMAX.
> +   Otherwise, return the VL operand.  */
> +rtx
> +vector_insn_info::get_avl_or_vl_reg (void) const
> +{
> +  gcc_assert (has_avl_reg ());
> +  if (!vlmax_avl_p (get_avl ()))
> +return get_avl ();
> +
> +  if (has_vl_op (get_insn ()->rtl ()) || vsetvl_insn_p (get_insn ()->rtl ()))
> +return ::get_vl (get_insn ()->rtl ());
> +
> +  if (get_avl_source ())
> +return get_avl_reg_rtx ();
> +
> +  /* A DIRTY (polluted EMPTY) block if:
> +   - get_insn is scalar move (no AVL or VL operand).
> +   - get_avl_source is null (no def in the current DIRTY block).
> + Then we trace the previous insn which must be the insn
> + already inserted in Phase 2 to get the VL operand for VLMAX.  */
> +  rtx_insn *prev_rinsn = PREV_INSN (get_insn ()->rtl ());
> +  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
> +  return ::get_vl (prev_rinsn);
> +}
> +
>  bool
>  vector_insn_info::update_fault_first_load_avl (insn_info *insn)
>  {
> @@ -3166,19 +3192,17 @@ pass_vsetvl::compute_local_properties (void)
> bitmap_clear_bit (m_vector_manager->vector_transp[curr_bb_idx], 
> i);
>   else if (expr->has_avl_reg ())
> {
> - rtx avl = vlmax_avl_p (expr->get_avl ())
> - ? get_vl (expr->get_insn ()->rtl ())
> - : expr->get_avl ();
> + rtx reg = expr->get_avl_or_vl_reg ();
>   for (const insn_info *insn : bb->real_nondebug_insns ())
> {
> - if (find_access (insn->defs (), REGNO (avl)))
> + if (find_access (insn->defs (), REGNO (reg)))
> {
>   bitmap_clear_bit (
> m_vector_manager->vector_transp[curr_bb_idx], i);
>   break;
> }
>   else if (vlmax_avl_p (expr->get_avl ())
> -  && find_access (insn->uses (), REGNO (avl)))
> +  && find_access (insn->uses (), REGNO (reg)))
> {
>   bitmap_clear_bit (
> m_vector_manager->vector_transp[curr_bb_idx], i);
> @@ -3649,17 +3673,7 @@ pass_vsetvl::commit_vsetvls (void)
>   = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, reaching_out, NULL_RTX);
>else if (vlmax_avl_p (reaching_out.get_avl ()))
> {
> - rtx vl = NULL_RTX;
> - /* For user VSETVL VL, AVL. We need to use VL operand here, so we
> -don't directly use get_avl_reg_rtx (). Instead, we use the VL
> -of the INSN->RTL ().  */
> - if (!reaching_out.get_avl_source ())
> -   {
> - gcc_assert (vsetvl_insn_p (reaching_out.get_insn ()->rtl ()));
> - vl = get_vl (reaching_out.get_insn ()->rtl ());
> -   }
> - else
> -   vl = reaching_out.get_avl_reg_rtx ();
> + rtx vl = reaching_out.get_avl_or_vl_reg ();
>   new_pat = gen_vsetvl_pat (VSETVL_NORMAL, reaching_out, vl);
> }
>else
> diff --git a/gcc/config/riscv/riscv-vsetvl.h 

Re: Re: [PATCH 0/2] support cm.push cm.pop cm.popret in zcmp and resolve confilct with shrink-wrap-separate

[Kito Cheng via Gcc-patches]

> 1. flag_shrink_wrap_separate seems better than flag_shrink_wrap.

(flag_)shrink_wrap_separate seems a sub optimization of
(flag_)shrink_wrap, so I am fine if flag_shrink_wrap_separate is
enough.

> 2. to pass the zcmp testcases, i will add fno-shrink-wrap-separate option.

OK

Re: [PATCH V4] RISC-V: Enable vec_int testsuite for RVV VLA vectorization

[Kito Cheng via Gcc-patches]

LGTM from my side, but I would like to wait Robin is ok too

Juzhe-Zhong 於 2023年8月28日 週一，19:43寫道：

> XPASS: gcc.dg/vect/no-scevccp-outer-12.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> XPASS: gcc.dg/vect/no-scevccp-outer-16.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> XPASS: gcc.dg/vect/no-scevccp-outer-17.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> XPASS: gcc.dg/vect/no-scevccp-outer-19.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> XPASS: gcc.dg/vect/no-scevccp-outer-21.c scan-tree-dump-times vect "OUTER
> LOOP VECTORIZED." 1
> FAIL: gcc.dg/vect/no-scevccp-outer-7.c scan-tree-dump-times vect
> "vect_recog_widen_mult_pattern: detected" 1
> FAIL: gcc.dg/vect/no-section-anchors-vect-31.c scan-tree-dump-times vect
> "Alignment of access forced using peeling" 2
> FAIL: gcc.dg/vect/no-section-anchors-vect-64.c scan-tree-dump-times vect
> "Alignment of access forced using peeling" 2
> FAIL: gcc.dg/vect/no-vfa-vect-101.c scan-tree-dump-times vect "can't
> determine dependence" 1
> FAIL: gcc.dg/vect/no-vfa-vect-102.c scan-tree-dump-times vect "possible
> dependence between data-refs" 1
> FAIL: gcc.dg/vect/no-vfa-vect-102a.c scan-tree-dump-times vect "possible
> dependence between data-refs" 1
> FAIL: gcc.dg/vect/no-vfa-vect-37.c scan-tree-dump-times vect "can't
> determine dependence" 2
> FAIL: gcc.dg/vect/pr57705.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 1 loop" 2
> FAIL: gcc.dg/vect/pr57705.c scan-tree-dump-times vect "vectorized 1 loop" 2
> FAIL: gcc.dg/vect/pr63341-1.c -flto -ffat-lto-objects execution test
> FAIL: gcc.dg/vect/pr63341-1.c execution test
> FAIL: gcc.dg/vect/pr63341-2.c -flto -ffat-lto-objects execution test
> FAIL: gcc.dg/vect/pr63341-2.c execution test
> FAIL: gcc.dg/vect/pr65310.c -flto -ffat-lto-objects  scan-tree-dump vect
> "can't force alignment"
> FAIL: gcc.dg/vect/pr65310.c -flto -ffat-lto-objects  scan-tree-dump-not
> vect "misalign = 0"
> FAIL: gcc.dg/vect/pr65310.c scan-tree-dump vect "can't force alignment"
> FAIL: gcc.dg/vect/pr65310.c scan-tree-dump-not vect "misalign = 0"
> FAIL: gcc.dg/vect/pr65518.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops in function" 2
> FAIL: gcc.dg/vect/pr65518.c scan-tree-dump-times vect "vectorized 0 loops
> in function" 2
> FAIL: gcc.dg/vect/pr68445.c -flto -ffat-lto-objects  scan-tree-dump vect
> "vectorizing stmts using SLP"
> FAIL: gcc.dg/vect/pr68445.c scan-tree-dump vect "vectorizing stmts using
> SLP"
> FAIL: gcc.dg/vect/pr88598-1.c -flto -ffat-lto-objects  scan-tree-dump-not
> optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr88598-1.c scan-tree-dump-not optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr88598-2.c -flto -ffat-lto-objects  scan-tree-dump-not
> optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr88598-2.c scan-tree-dump-not optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr88598-3.c -flto -ffat-lto-objects  scan-tree-dump-not
> optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr88598-3.c scan-tree-dump-not optimized "REDUC_PLUS"
> FAIL: gcc.dg/vect/pr94994.c -flto -ffat-lto-objects execution test
> FAIL: gcc.dg/vect/pr94994.c execution test
> FAIL: gcc.dg/vect/pr97835.c -flto -ffat-lto-objects  scan-tree-dump vect
> "vectorizing stmts using SLP"
> FAIL: gcc.dg/vect/pr97835.c scan-tree-dump vect "vectorizing stmts using
> SLP"
> FAIL: gcc.dg/vect/slp-1.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorizing stmts using SLP" 4
> FAIL: gcc.dg/vect/slp-1.c scan-tree-dump-times vect "vectorizing stmts
> using SLP" 4
> FAIL: gcc.dg/vect/slp-11a.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-11a.c scan-tree-dump-times vect "vectorized 0 loops"
> 1
> FAIL: gcc.dg/vect/slp-12a.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-12a.c scan-tree-dump-times vect "vectorized 0 loops"
> 1
> FAIL: gcc.dg/vect/slp-12c.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-12c.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorizing stmts using SLP" 0
> FAIL: gcc.dg/vect/slp-12c.c scan-tree-dump-times vect "vectorized 0 loops"
> 1
> FAIL: gcc.dg/vect/slp-12c.c scan-tree-dump-times vect "vectorizing stmts
> using SLP" 0
> FAIL: gcc.dg/vect/slp-15.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-15.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorizing stmts using SLP" 0
> FAIL: gcc.dg/vect/slp-15.c scan-tree-dump-times vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-15.c scan-tree-dump-times vect "vectorizing stmts
> using SLP" 0
> FAIL: gcc.dg/vect/slp-19a.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorized 0 loops" 1
> FAIL: gcc.dg/vect/slp-19a.c -flto -ffat-lto-objects  scan-tree-dump-times
> vect "vectorizing stmts using SLP" 0
> FAIL: gcc.dg/vect/slp-19a.c scan-tree-dump-times vect "vectorized 0 loops"
> 1

Re: [PATCH] RISC-V: Fix uninitialized probability for GIMPLE IR tests

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年8月28日 週一 19:40 寫道：

> This patch fix unitialized probability in GIMPLE IR code tests:
> FAIL: gcc.dg/vect/slp-reduc-10a.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10a.c (test for excess errors)
> FAIL: gcc.dg/vect/slp-reduc-10a.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10a.c -flto -ffat-lto-objects (test for excess
> errors)
> FAIL: gcc.dg/vect/slp-reduc-10b.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10b.c (test for excess errors)
> FAIL: gcc.dg/vect/slp-reduc-10b.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10b.c -flto -ffat-lto-objects (test for excess
> errors)
> FAIL: gcc.dg/vect/slp-reduc-10c.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10c.c (test for excess errors)
> FAIL: gcc.dg/vect/slp-reduc-10c.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10c.c -flto -ffat-lto-objects (test for excess
> errors)
> FAIL: gcc.dg/vect/slp-reduc-10d.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10d.c (test for excess errors)
> FAIL: gcc.dg/vect/slp-reduc-10d.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10d.c -flto -ffat-lto-objects (test for excess
> errors)
> FAIL: gcc.dg/vect/slp-reduc-10e.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10e.c (test for excess errors)
> FAIL: gcc.dg/vect/slp-reduc-10e.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/slp-reduc-10e.c -flto -ffat-lto-objects (test for excess
> errors)
> FAIL: gcc.dg/vect/vect-cond-arith-2.c (internal compiler error: in
> compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/vect-cond-arith-2.c (test for excess errors)
> FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects (internal
> compiler error: in compute_probabilities, at
> config/riscv/riscv-vsetvl.cc:4358)
> FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects (test for
> excess errors)
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion):
> Skip never probability.
> (pass_vsetvl::compute_probabilities): Fix unitialized probability.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 48e89fe2c03..f7ae6c16bee 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3272,6 +3272,10 @@ pass_vsetvl::earliest_fusion (void)
>   if (expr.empty_p ())
> continue;
>   edge eg = INDEX_EDGE (m_vector_manager->vector_edge_list, ed);
> + /* If it is the edge that we never reach, skip its possible PRE
> +fusion conservatively.  */
> + if (eg->probability == profile_probability::never ())
> +   break;
>   if (eg->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)
>   || eg->dest == EXIT_BLOCK_PTR_FOR_FN (cfun))
> break;
> @@ -4359,7 +4363,14 @@ pass_vsetvl::compute_probabilities (void)
>FOR_EACH_EDGE (e, ei, cfg_bb->succs)
> {
>   auto _prob = get_block_info (e->dest).probability;
> - if (!new_prob.initialized_p ())
> + /* Normally, the edge probability should be initialized.
> +However, some special testing code which is written in
> +GIMPLE IR style force the edge probility uninitialized,
> +we conservatively set it as never so that it will not
> +affect PRE (Phase 3 && Phse 4).  */
> + if (!e->probability.initialized_p ())
> +   new_prob = profile_probability::never ();
> + else if (!new_prob.initialized_p ())
> new_prob = curr_prob * e->probability;
>   else if (new_prob == profile_probability::always ())
> continue;
> --
> 2.36.3
>
>

Re: [PATCH V2] RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) block

[Kito Cheng via Gcc-patches]

LGTM, that's much clearer than v1 to me :)

On Mon, Aug 28, 2023 at 5:54 PM Juzhe-Zhong  wrote:
>
> This patch is fixing these bunch of ICE in "vect" testsuite:
> FAIL: gcc.dg/vect/no-scevccp-outer-2.c (internal compiler error: in 
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/no-scevccp-outer-2.c (test for excess errors)
> FAIL: gcc.dg/vect/pr109025.c (internal compiler error: in 
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/pr109025.c (test for excess errors)
> FAIL: gcc.dg/vect/pr109025.c -flto -ffat-lto-objects (internal compiler 
> error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/pr109025.c -flto -ffat-lto-objects (test for excess errors)
> FAIL: gcc.dg/vect/pr42604.c (internal compiler error: in 
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/pr42604.c (test for excess errors)
> FAIL: gcc.dg/vect/pr42604.c -flto -ffat-lto-objects (internal compiler error: 
> in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/pr42604.c -flto -ffat-lto-objects (test for excess errors)
> FAIL: gcc.dg/vect/vect-double-reduc-3.c (internal compiler error: in 
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/vect-double-reduc-3.c (test for excess errors)
> FAIL: gcc.dg/vect/vect-double-reduc-3.c -flto -ffat-lto-objects (internal 
> compiler error: in anticipatable_occurrence_p, at 
> config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/vect-double-reduc-3.c -flto -ffat-lto-objects (test for 
> excess errors)
> FAIL: gcc.dg/vect/vect-double-reduc-7.c (internal compiler error: in 
> anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/vect-double-reduc-7.c (test for excess errors)
> FAIL: gcc.dg/vect/vect-double-reduc-7.c -flto -ffat-lto-objects (internal 
> compiler error: in anticipatable_occurrence_p, at 
> config/riscv/riscv-vsetvl.cc:314)
> FAIL: gcc.dg/vect/vect-double-reduc-7.c -flto -ffat-lto-objects (test for 
> excess errors)
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion): Fix 
> bug.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 38 ++--
>  1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 682f795c8e1..48e89fe2c03 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3285,12 +3285,46 @@ pass_vsetvl::earliest_fusion (void)
>   gcc_assert (!(eg->flags & EDGE_ABNORMAL));
>   vector_insn_info new_info = vector_insn_info ();
>   profile_probability prob = src_block_info.probability;
> + /* We don't fuse user vsetvl into EMPTY or
> +DIRTY (EMPTY but polluted) block for these
> +following reasons:
> +
> +   - The user vsetvl instruction is configured as
> + no side effects that the previous passes
> + (GSCE, Loop-invariant, ..., etc)
> + should be able to do a good job on optimization
> + of user explicit vsetvls so we don't need to
> + PRE optimization (The user vsetvls should be
> + on the optimal local already before this pass)
> + again for user vsetvls in VSETVL PASS here
> + (Phase 3 && Phase 4).
> +
> +   - Allowing user vsetvls be optimized in PRE
> + optimization here (Phase 3 && Phase 4) will
> + complicate the codes so much so we prefer user
> + vsetvls be optimized in post-optimization
> + (Phase 5 && Phase 6).  */
> + if (vsetvl_insn_p (expr.get_insn ()->rtl ()))
> +   {
> + if (src_block_info.reaching_out.empty_p ())
> +   continue;
> + else if (src_block_info.reaching_out.dirty_p ()
> +  && !src_block_info.reaching_out.compatible_p 
> (expr))
> +   {
> + new_info.set_empty ();
> + /* Update probability as uninitialized status so that
> +we won't try to fuse any demand info into such EMPTY
> +block any more.  */
> + prob = profile_probability::uninitialized ();
> + update_block_info (eg->src->index, prob, new_info);
> + continue;
> +   }
> +   }
>
>   if (src_block_info.reaching_out.empty_p ())
> {
>   if (src_block_info.probability
> -   == profile_probability::uninitialized ()
> - || vsetvl_insn_p (expr.get_insn ()->rtl ()))
> + == 

Re: [PATCH 0/2] support cm.push cm.pop cm.popret in zcmp and resolve confilct with shrink-wrap-separate

[Kito Cheng via Gcc-patches]

I would prefer to decouple the shrink-wrap part by checking
flag_shrink_wrap, I mean let disable zcmp code gen if flag_shrink_wrap
is true for now, and a follow up patch series with shrink-wrap.[cc|h]
changes?

On Mon, Aug 28, 2023 at 3:48 PM Fei Gao  wrote:
>
> The first is a helper patch to allow targets to check shrink-wrap-separate 
> enabled or not.
> The second is zcmp extension implementation in RISC-V.
>
> Fei Gao (2):
>   allow target to check shrink-wrap-separate enabled or not
>   support cm.push cm.pop cm.popret in zcmp and resolve confilct with 
> shrink-wrap-separate
>
>  gcc/config/riscv/iterators.md |   15 +
>  gcc/config/riscv/predicates.md|   96 ++
>  gcc/config/riscv/riscv-protos.h   |2 +
>  gcc/config/riscv/riscv.cc |  455 ++-
>  gcc/config/riscv/riscv.h  |   25 +
>  gcc/config/riscv/riscv.md |2 +
>  gcc/config/riscv/zc.md| 1042 +
>  gcc/shrink-wrap.cc|   25 +-
>  gcc/shrink-wrap.h |1 +
>  gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c   |  256 
>  gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c   |  256 
>  .../gcc.target/riscv/zcmp_push_fpr.c  |   34 +
>  .../riscv/zcmp_shrink_wrap_separate.c |   93 ++
>  .../riscv/zcmp_shrink_wrap_separate2.c|   93 ++
>  .../gcc.target/riscv/zcmp_stack_alignment.c   |   24 +
>  15 files changed, 2357 insertions(+), 62 deletions(-)
>  create mode 100644 gcc/config/riscv/zc.md
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c
>
> --
> 2.17.1
>

Re: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block

[Kito Cheng via Gcc-patches]

What about that? I guess I don't really know how to determine if a
block is EMPTY?

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 682f795c8e1..784ab184c72 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3282,6 +3282,10 @@ pass_vsetvl::earliest_fusion (void)
 if (src_block_info.reaching_out.unknown_p ())
   break;

+ if (vsetvl_insn_p (expr.get_insn ()->rtl ())
+ && src_block_info.reaching_out.empty_p ())
+   continue;
+
 gcc_assert (!(eg->flags & EDGE_ABNORMAL));
 vector_insn_info new_info = vector_insn_info ();
 profile_probability prob = src_block_info.probability;

On Mon, Aug 28, 2023 at 5:09 PM juzhe.zh...@rivai.ai
 wrote:
>
> No. we can't.
>
> My goal is to forbid this following situation:
>
> bb 2:
> EMPTY (no any vsetvl and rvv insn)
> bb 3:
> user vsetvl.
>
> We forbid user vsetvl (bb 3) be move to bb 2 in earliest fusion since user 
> vsetvl has no side effects
> and we believe user vsetvl in bb 3 here is early enough.
>
> However, if we skip that as your patch, we will end up with missing this 
> optimization:
>
> bb 2:
> user vsetvl a5, a4, e8, mf4...
> vle8
> vse8
>
> bb 3:
> user vsetvl a5, a4, e16, mf2... -> In phase 1 && phase 2, the local 
> demand fusion will update it into (e32, m1)
> vle32
> vadd
> vse32
>
> If we skip at the top, we will be missing fuse user vsetvl (in bb 3 e32 m1) 
> into user vsetvl (in bb 2 e8 mf4).
>
> Thanks.
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-08-28 16:58
> To: Robin Dapp
> CC: Juzhe-Zhong; gcc-patches; kito.cheng
> Subject: Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block
> Is it possible to skip that at the topper level like that?
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 682f795c8e1..654d25de593 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3269,7 +3269,7 @@ pass_vsetvl::earliest_fusion (void)
>   for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
>{
>  auto  = *m_vector_manager->vector_exprs[i];
> - if (expr.empty_p ())
> + if (expr.empty_p () || vsetvl_insn_p (expr.get_insn ()->rtl ()))
>continue;
>  edge eg = INDEX_EDGE (m_vector_manager->vector_edge_list, ed);
>  if (eg->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)
>

Re: [PATCH] RISC-V: Disable user vsetvl fusion into EMPTY block

[Kito Cheng via Gcc-patches]

Is it possible to skip that at the topper level like that?

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 682f795c8e1..654d25de593 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3269,7 +3269,7 @@ pass_vsetvl::earliest_fusion (void)
  for (size_t i = 0; i < m_vector_manager->vector_exprs.length (); i++)
   {
 auto  = *m_vector_manager->vector_exprs[i];
- if (expr.empty_p ())
+ if (expr.empty_p () || vsetvl_insn_p (expr.get_insn ()->rtl ()))
   continue;
 edge eg = INDEX_EDGE (m_vector_manager->vector_edge_list, ed);
 if (eg->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)

Re: [PATCH] RISC-V: Enable vec_init testsuite for RVV VLA vectorization

[Kito Cheng via Gcc-patches]

> @@ -11100,6 +11101,15 @@ proc check_vect_support_and_set_flags { } {
>  }
>  } elseif [istarget amdgcn-*-*] {
>  set dg-do-what-default run
> +} elseif [istarget riscv64-*-*] {
> +   if [check_effective_target_riscv_vector_hw] {
> +   lappend DEFAULT_VECTCFLAGS "--param" 
> "riscv-autovec-preference=scalable"
> +   set dg-do-what-default run
> +   } else {
> +   lappend DEFAULT_VECTCFLAGS "-march=rv64gcv_zfh" "-mabi=lp64d"

I would suggest using `-march=rv64gcv` or `-march=rv64gcv_zvfh_zfh`?
Just zfh is not meaningful I think.

Re: [PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec

[Kito Cheng via Gcc-patches]

lgtm

On Fri, Aug 25, 2023 at 9:49 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ   <- intrinisc static rounding
> vfnmadd <- autovec/autovec-opt
>
> The autovec generated vfnmadd should take DYN mode, and the
> frm must be restored before the vfnmadd insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +
> | frrm  a5
> | ...
> | fsrmi 4
> | vfadd   <- intrinsic static rounding.
> | ...
> | fsrm  a5
> | vfnmadd <- autovec/autovec-opt
> | ...
> +
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test.
> ---
>  gcc/config/riscv/autovec-opt.md   | 38 
>  gcc/config/riscv/autovec.md   | 34 ---
>  .../rvv/base/float-point-frm-autovec-4.c  | 88 +++
>  3 files changed, 130 insertions(+), 30 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 54ca6df721c..2922f370a17 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -655,14 +655,16 @@ (define_insn_and_split "*single_widen_fms"
>  ;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
>  (define_insn_and_split "*double_widen_fnms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (float_extend:VWEXTF
> -   (match_operand: 3 "register_operand"))
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> + (match_operand: 3 "register_operand"))
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -673,18 +675,21 @@ (define_insn_and_split "*double_widen_fnms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; This helps to match ext + fnms.
>  (define_insn_and_split "*single_widen_fnms"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> -   (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (match_operand:VWEXTF 3 "register_operand")
> - (neg:VWEXTF
> -   (match_operand:VWEXTF 1 "register_operand"]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> +   (match_operand:VWEXTF 3 "register_operand")
> +   (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -701,4 +706,5 @@ (define_insn_and_split "*single_widen_fnms"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 28396c6175d..5f16ac53712 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1274,26 +1274,31 @@ (define_insn_and_split "*fms"
>  (define_expand "fnms4"
>[(parallel
>  [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> -   (neg:VF
> - (match_operand:VF 1 "register_operand"))
> -   (match_operand:VF 2 "register_operand")
> -   (neg:VF
> - (match_operand:VF 3 "register_operand"
> + (unspec:VF
> +   [(fma:VF
> + (neg:VF
> +   (match_operand:VF 1 "register_operand"))
> + (match_operand:VF 2 "register_operand")
> + (neg:VF
> +   (match_operand:VF 3 "register_operand")))
> +(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
>   (clobber (match_dup 4))])]
>"TARGET_VECTOR"
>{
>  operands[4] = gen_reg_rtx (Pmode);
> -  })
> +  }
> +  [(set (attr "frm_mode") (symbol_ref 

Re: [PATCH V2] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

[Kito Cheng via Gcc-patches]

>
>-  Phase 3 - Backward && forward demanded info propagation and fusion 
> across
>   blocks.
>

Need update comment here.

>-  Phase 6 - Propagate AVL between vsetvl instructions.

Need update comment here too.

> +/* Return true if the current VSETVL is dominated by preceding VSETVL.  */
> +static bool
> +vsetvl_dominated_by_p (const basic_block cfg_bb,
> +  const vector_insn_info ,
> +  const vector_insn_info , bool fuse_p)

"VSETVL1 is dominated by preceding VSETVL2." ?
and what's the definition of dominated?
it seems like not in the traditional sense of "dominate"?


> vector_insn_info::merge (const vector_insn_info _info,
> -enum merge_type type) const
> +enum merge_type type, int bb_index) const

I would suggest just split this into two funciton, local_merge and
global_merge, and remove merge_type,
generally I like generalized those function by arguments, but those
two are different enough after this change.


> +  /* Recompute the AVL source when bb_index*/

This sentence seems to be incomplete?


> + if (dest_block_info.probability > 
> src_block_info.probability)
> +   prob = dest_block_info.probability;

prob = std::max(dest_block_info.probability, src_block_info.probability);

> @@ -3720,6 +3138,8 @@ pass_vsetvl::compute_local_properties (void)
>for (const bb_info *bb : crtl->ssa->bbs ())
>  {
>unsigned int curr_bb_idx = bb->index ();
> +  if (curr_bb_idx == ENTRY_BLOCK || curr_bb_idx == EXIT_BLOCK)
> +   continue;
>const auto local_dem
> = m_vector_manager->vector_block_infos[curr_bb_idx].local_dem;
>const auto reaching_out

This small change seems could be a small optimization for early exit
for this loop and could be a separated patch? if so plz send a
separated, and pre-aproved for that :)



> + if (src_block_info.reaching_out.empty_p ())
> +   {
...
> + else if (src_block_info.reaching_out.dirty_p ())

Could you add more comment to explain more for each condition?

> +   {
> + rtx vl = NULL_RTX;
> + if (!reaching_out.get_avl_source ())
> +   {
> + gcc_assert (vsetvl_insn_p (reaching_out.get_insn ()->rtl ()));
> + vl = get_vl (reaching_out.get_insn ()->rtl ());
> +   }
> + else
> +   vl = reaching_out.get_avl_reg_rtx ();
> + new_pat = gen_vsetvl_pat (VSETVL_NORMAL, reaching_out, vl);
> +   }

need more comment here too

> +  edge eg;
> +  edge_iterator eg_iterator;
> +  FOR_EACH_EDGE (eg, eg_iterator, cfg_bb->succs)
> {
> - fprintf (dump_file,
> -  "\nInsert vsetvl insn %d at the end of :\n",
> -  INSN_UID (new_insn), cfg_bb->index);
> - print_rtl_single (dump_file, new_insn);
> + /* We should not get an abnormal edge here.  */
> + gcc_assert (!(eg->flags & EDGE_ABNORMAL));
> + if (m_vector_manager->vsetvl_dominated_by_all_preds_p (cfg_bb,
> +
> reaching_out))
> +   continue;
> +

Also need more comments here .

Re: [PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Aug 24, 2023 at 5:35 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ   <- intrinisc static rounding
> vfnmsub <- autovec/autovec-opt
>
> The autovec generated vfnmsub should take DYN mode, and the
> frm must be restored before the vfnmsub insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +
> | frrm  a5
> | ...
> | fsrmi 4
> | vfadd   <- intrinsic static rounding.
> | ...
> | fsrm  a5
> | vfnmsub <- autovec/autovec-opt
> | ...
> +
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: New test.
> ---
>  gcc/config/riscv/autovec-opt.md   | 34 ---
>  gcc/config/riscv/autovec.md   | 30 ---
>  .../rvv/base/float-point-frm-autovec-3.c  | 88 +++
>  3 files changed, 126 insertions(+), 26 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 732a51edacd..54ca6df721c 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -523,13 +523,15 @@ (define_insn_and_split "*single_widen_fma"
>  ;; vect__13.182_33 = .FNMA (vect__11.180_35, vect__8.176_40, vect__4.172_45);
>  (define_insn_and_split "*double_widen_fnma"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (float_extend:VWEXTF
> -   (match_operand: 3 "register_operand"))
> - (match_operand:VWEXTF 1 "register_operand")))]
> + (match_operand: 3 "register_operand"))
> +   (match_operand:VWEXTF 1 "register_operand"))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -540,17 +542,20 @@ (define_insn_and_split "*double_widen_fnma"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; This helps to match ext + fnma.
>  (define_insn_and_split "*single_widen_fnma"
>[(set (match_operand:VWEXTF 0 "register_operand")
> -   (fma:VWEXTF
> - (neg:VWEXTF
> -   (float_extend:VWEXTF
> - (match_operand: 2 "register_operand")))
> - (match_operand:VWEXTF 3 "register_operand")
> - (match_operand:VWEXTF 1 "register_operand")))]
> +   (unspec:VWEXTF
> + [(fma:VWEXTF
> +   (neg:VWEXTF
> + (float_extend:VWEXTF
> +   (match_operand: 2 "register_operand")))
> +   (match_operand:VWEXTF 3 "register_operand")
> +   (match_operand:VWEXTF 1 "register_operand"))
> +  (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -567,7 +572,8 @@ (define_insn_and_split "*single_widen_fnma"
>  DONE;
>}
>[(set_attr "type" "vfwmuladd")
> -   (set_attr "mode" "")])
> +   (set_attr "mode" "")
> +   (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;; -
>  ;;  [FP] VFWMSAC
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 0c1c546817a..28396c6175d 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1174,24 +1174,29 @@ (define_insn_and_split "*fma"
>  (define_expand "fnma4"
>[(parallel
>  [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> -   (neg:VF
> - (match_operand:VF 1 "register_operand"))
> -   (match_operand:VF 2 "register_operand")
> -   (match_operand:VF 3 "register_operand")))
> + (unspec:VF
> +   [(fma:VF
> + (neg:VF
> +   (match_operand:VF 1 "register_operand"))
> + (match_operand:VF 2 "register_operand")
> + (match_operand:VF 3 "register_operand"))
> +(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
>   (clobber (match_dup 4))])]
>"TARGET_VECTOR"
>{
>  operands[4] = gen_reg_rtx (Pmode);
> -  })
> +  }
> +  [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  (define_insn_and_split "*fnma"
>[(set 

Re: [PATCH v2] RISC-V: Refactor RVV class by frm_op_type template arg

[Kito Cheng via Gcc-patches]

LGTM

Pan Li via Gcc-patches  於 2023年8月22日 週二 12:20 寫道：

> From: Pan Li 
>
> Update in v2:
>
> * Added gcc_assert for vx format in binop.
> * Passed riscv/rvv.exp test.
>
> Original Log:
>
> As suggested by kito, we will add new frm_opt_type template arg
> to the op class, to avoid the duplicated function expand.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class binop_frm): Removed.
> (class reverse_binop_frm): Ditto.
> (class widen_binop_frm): Ditto.
> (class vfmacc_frm): Ditto.
> (class vfnmacc_frm): Ditto.
> (class vfmsac_frm): Ditto.
> (class vfnmsac_frm): Ditto.
> (class vfmadd_frm): Ditto.
> (class vfnmadd_frm): Ditto.
> (class vfmsub_frm): Ditto.
> (class vfnmsub_frm): Ditto.
> (class vfwmacc_frm): Ditto.
> (class vfwnmacc_frm): Ditto.
> (class vfwmsac_frm): Ditto.
> (class vfwnmsac_frm): Ditto.
> (class unop_frm): Ditto.
> (class vfrec7_frm): Ditto.
> (class binop): Add frm_op_type template arg.
> (class unop): Ditto.
> (class widen_binop): Ditto.
> (class widen_binop_fp): Ditto.
> (class reverse_binop): Ditto.
> (class vfmacc): Ditto.
> (class vfnmsac): Ditto.
> (class vfmadd): Ditto.
> (class vfnmsub): Ditto.
> (class vfnmacc): Ditto.
> (class vfmsac): Ditto.
> (class vfnmadd): Ditto.
> (class vfmsub): Ditto.
> (class vfwmacc): Ditto.
> (class vfwnmacc): Ditto.
> (class vfwmsac): Ditto.
> (class vfwnmsac): Ditto.
> (class float_misc): Ditto.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  | 571 +-
>  1 file changed, 143 insertions(+), 428 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 5ee7d3119db..54582ee130c 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -262,41 +262,21 @@ public:
> vremu/vsadd/vsaddu/vssub/vssubu
> vfadd/vfsub/
>  */
> -template
> +template
>  class binop : public function_base
>  {
>  public:
> -  rtx expand (function_expander ) const override
> +  bool has_rounding_mode_operand_p () const override
>{
> -switch (e.op_info->op)
> -  {
> -  case OP_TYPE_vx:
> -  case OP_TYPE_vf:
> -   return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
> -  case OP_TYPE_vv:
> -   return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
> -  default:
> -   gcc_unreachable ();
> -  }
> +return FRM_OP == HAS_FRM;
>}
> -};
> -
> -/* Implements below instructions for now.
> -   - vfadd
> -   - vfsub
> -   - vfmul
> -   - vfdiv
> -*/
> -template
> -class binop_frm : public function_base
> -{
> -public:
> -  bool has_rounding_mode_operand_p () const override { return true; }
>
>rtx expand (function_expander ) const override
>{
>  switch (e.op_info->op)
>{
> +  case OP_TYPE_vx:
> +   gcc_assert (FRM_OP == NO_FRM);
>case OP_TYPE_vf:
> return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
>case OP_TYPE_vv:
> @@ -307,365 +287,6 @@ public:
>}
>  };
>
> -/* Implements below instructions for frm
> -   - vfrsub
> -   - vfrdiv
> -*/
> -template
> -class reverse_binop_frm : public function_base
> -{
> -public:
> -  bool has_rounding_mode_operand_p () const override { return true; }
> -
> -public:
> -  rtx expand (function_expander ) const override
> -  {
> -return e.use_exact_insn (
> -  code_for_pred_reverse_scalar (CODE, e.vector_mode ()));
> -  }
> -};
> -
> -/* Implements below instructions for frm
> -   - vfwadd
> -   - vfwsub
> -   - vfwmul
> -*/
> -template
> -class widen_binop_frm : public function_base
> -{
> -public:
> -  bool has_rounding_mode_operand_p () const override { return true; }
> -
> -  rtx expand (function_expander ) const override
> -  {
> -switch (e.op_info->op)
> -  {
> -  case OP_TYPE_vv:
> -   return e.use_exact_insn (
> - code_for_pred_dual_widen (CODE, e.vector_mode ()));
> -  case OP_TYPE_vf:
> -   return e.use_exact_insn (
> - code_for_pred_dual_widen_scalar (CODE, e.vector_mode ()));
> -  case OP_TYPE_wv:
> -   if (CODE == PLUS)
> - return e.use_exact_insn (
> -   code_for_pred_single_widen_add (e.vector_mode ()));
> -   else
> - return e.use_exact_insn (
> -   code_for_pred_single_widen_sub (e.vector_mode ()));
> -  case OP_TYPE_wf:
> -   return e.use_exact_insn (
> - code_for_pred_single_widen_scalar (CODE, e.vector_mode ()));
> -  default:
> -   gcc_unreachable ();
> -  }
> -  }
> -};
> -
> -/* Implements below instructions for frm
> -   - vfmacc
> -*/
> -class 

Re: [PATCH v1] RISC-V: Fix one typo in autovec.md pattern comment

[Kito Cheng via Gcc-patches]

LGTM

Pan Li via Gcc-patches  於 2023年8月24日 週四 15:41 寫道：

> From: Pan Li 
>
> Fix below typo for the pattern comment.
>
> vfmsac => vfnmsac
> vfmsub => vfnmsub
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Fix typo.
> ---
>  gcc/config/riscv/autovec.md | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index d9f1a10eb66..18950ac7c4f 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1258,11 +1258,11 @@ (define_insn_and_split "*fms"
> (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
>  ;;
> -
> -;;  [FP] VFMSAC and VFMSUB
> +;;  [FP] VFNMSAC and VFNMSUB
>  ;;
> -
>  ;; Includes:
> -;; - vfmsac
> -;; - vfmsub
> +;; - vfnmsac
> +;; - vfnmsub
>  ;;
> -
>
>  (define_expand "fnms4"
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

[Kito Cheng via Gcc-patches]

It's really great improvement, it's drop some state like HARD_EMPTY
and DIRTY_WITH_KILLED_AVL which make this algorithm more easy to
understand!
also this also fundamentally improved the phase 3, although one
concern is the time complexity might be come more higher order,
(and it's already high enough in fact.)
but mostly those vectorized code are only appeard within the inner
most loop, so that is acceptable in generally

So I will try my best to review this closely to make it more close to
the perfect :)

I saw you has update serveral testcase, why update instead of add new testcase??
could you say more about why some testcase added __riscv_vadd_vv_i8mf8
or add some more dependency of vl variable?



> @@ -1423,8 +1409,13 @@ static bool
>  ge_sew_ratio_unavailable_p (const vector_insn_info ,
> const vector_insn_info )
>  {
> -  if (!info2.demand_p (DEMAND_LMUL) && info2.demand_p (DEMAND_GE_SEW))
> -return info1.get_sew () < info2.get_sew ();
> +  if (!info2.demand_p (DEMAND_LMUL))
> +{
> +  if (info2.demand_p (DEMAND_GE_SEW))
> +   return info1.get_sew () < info2.get_sew ();
> +  else if (!info2.demand_p (DEMAND_SEW))
> +   return false;
> +}

This seems relax the compatiblitly check to allow optimize more case,
if so this should be a sperated patch.

>return true;
>  }


> @@ -1815,7 +1737,7 @@ vector_insn_info::parse_insn (rtx_insn *rinsn)
>  return;
>if (optimize == 0 && !has_vtype_op (rinsn))
>  return;
> -  if (optimize > 0 && !vsetvl_insn_p (rinsn))
> +  if (optimize > 0 && vsetvl_discard_result_insn_p (rinsn))

I didn't get this change, could you explan few more about that? it was
early exit for non vsetvl insn, but now it allowed that now?

>  return;
>m_state = VALID;
>extract_insn_cached (rinsn);

> @@ -2206,9 +2128,9 @@ vector_insn_info::fuse_mask_policy (const 
> vector_insn_info ,
>
>  vector_insn_info
>  vector_insn_info::merge (const vector_insn_info _info,
> -enum merge_type type) const
> +enum merge_type type, unsigned bb_index) const
>  {
> -  if (!vsetvl_insn_p (get_insn ()->rtl ()))
> +  if (!vsetvl_insn_p (get_insn ()->rtl ()) && *this != merge_info)

Why need this exception?

>  gcc_assert (this->compatible_p (merge_info)
> && "Can't merge incompatible demanded infos");

> @@ -2403,18 +2348,22 @@ vector_infos_manager::get_all_available_exprs (
>  }
>
>  bool
> -vector_infos_manager::all_empty_predecessor_p (const basic_block cfg_bb) 
> const
> +vector_infos_manager::earliest_fusion_worthwhile_p (
> +  const basic_block cfg_bb) const
>  {
> -  hash_set pred_cfg_bbs = get_all_predecessors (cfg_bb);
> -  for (const basic_block pred_cfg_bb : pred_cfg_bbs)
> +  edge e;
> +  edge_iterator ei;
> +  profile_probability prob = profile_probability::uninitialized ();
> +  FOR_EACH_EDGE (e, ei, cfg_bb->succs)
>  {
> -  const auto _block_info = vector_block_infos[pred_cfg_bb->index];
> -  if (!pred_block_info.local_dem.valid_or_dirty_p ()
> - && !pred_block_info.reaching_out.valid_or_dirty_p ())
> +  if (prob == profile_probability::uninitialized ())
> +   prob = vector_block_infos[e->dest->index].probability;
> +  else if (prob == vector_block_infos[e->dest->index].probability)
> continue;
> -  return false;
> +  else
> +   return true;

Make sure I understand this correctly: it's worth if thoe edges has
different probability?

>  }
> -  return true;
> +  return false;

If all probability is same, then it's not worth?

Plz add few comments no matter my understand is right or not :)

>  }
>
>  bool

> @@ -2428,12 +2377,12 @@ vector_infos_manager::all_same_ratio_p (sbitmap 
> bitdata) const
>sbitmap_iterator sbi;
>
>EXECUTE_IF_SET_IN_BITMAP (bitdata, 0, bb_index, sbi)
> -  {
> -if (ratio == -1)
> -  ratio = vector_exprs[bb_index]->get_ratio ();
> -else if (vector_exprs[bb_index]->get_ratio () != ratio)
> -  return false;
> -  }
> +{
> +  if (ratio == -1)
> +   ratio = vector_exprs[bb_index]->get_ratio ();
> +  else if (vector_exprs[bb_index]->get_ratio () != ratio)
> +   return false;
> +}
>return true;
>  }

Split this into a NFC patch, you can commit that without asking review.

> @@ -907,8 +893,8 @@ change_insn (function_info *ssa, insn_change change, 
> insn_info *insn,
> ] UNSPEC_VPREDICATE)
> (plus:RVVM4DI (reg/v:RVVM4DI 104 v8 [orig:137 op1 ] [137])
> (sign_extend:RVVM4DI (vec_duplicate:RVVM4SI (reg:SI 15 a5
> -[140] (unspec:RVVM4DI [ (const_int 0 [0]) ] UNSPEC_VUNDEF))) 
> "rvv.c":8:12
> -2784 {pred_single_widen_addsvnx8di_scalar} (expr_list:REG_EQUIV
> +[140] (unspec:RVVM4DI [ (const_int 0 [0]) ] UNSPEC_VUNDEF)))
> +"rvv.c":8:12 2784 {pred_single_widen_addsvnx8di_scalar} 
> (expr_list:REG_EQUIV
>  (mem/c:RVVM4DI (reg:DI 10 a0 [142]) [1 +0 S[64, 64] A128])
> 

Re: [PATCH] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS

[Kito Cheng via Gcc-patches]

I think I could do some details review tomorrow on the plane, I am free
from the meeting hell tomorrow :p



Robin Dapp via Gcc-patches  於 2023年8月21日 週一 23:24
寫道：

> Hi Juzhe,
>
> thanks, this is a reasonable approach and improves readability noticeably.
> LGTM but I'd like to wait for other opinions (e.g. by Kito) as I haven't
> looked closely into the vsetvl pass before and cannot entirely review it
> quickly.  As we already have good test coverage there is not much that
> can go wrong IMHO.
>
> Regards
>  Robin
>

Re: [PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg

[Kito Cheng via Gcc-patches]

Just one nit from me: plz add assertion to OP_TYPE_vx to make sure NO
FRM_OP == HAS_FRM there

On Mon, Aug 21, 2023 at 11:04 PM Jeff Law via Gcc-patches
 wrote:
>
>
>
> On 8/17/23 20:53, Pan Li via Gcc-patches wrote:
> > From: Pan Li 
> >
> > As suggested by kito, we will add new frm_opt_type template arg
> > to the op class, to avoid the duplicated function expand.
> >
> > Signed-off-by: Pan Li 
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/riscv-vector-builtins-bases.cc
> >   (class binop_frm): Removed.
> >   (class reverse_binop_frm): Ditto.
> >   (class widen_binop_frm): Ditto.
> >   (class vfmacc_frm): Ditto.
> >   (class vfnmacc_frm): Ditto.
> >   (class vfmsac_frm): Ditto.
> >   (class vfnmsac_frm): Ditto.
> >   (class vfmadd_frm): Ditto.
> >   (class vfnmadd_frm): Ditto.
> >   (class vfmsub_frm): Ditto.
> >   (class vfnmsub_frm): Ditto.
> >   (class vfwmacc_frm): Ditto.
> >   (class vfwnmacc_frm): Ditto.
> >   (class vfwmsac_frm): Ditto.
> >   (class vfwnmsac_frm): Ditto.
> >   (class unop_frm): Ditto.
> >   (class vfrec7_frm): Ditto.
> >   (class binop): Add frm_op_type template arg.
> >   (class unop): Ditto.
> >   (class widen_binop): Ditto.
> >   (class widen_binop_fp): Ditto.
> >   (class reverse_binop): Ditto.
> >   (class vfmacc): Ditto.
> >   (class vfnmsac): Ditto.
> >   (class vfmadd): Ditto.
> >   (class vfnmsub): Ditto.
> >   (class vfnmacc): Ditto.
> >   (class vfmsac): Ditto.
> >   (class vfnmadd): Ditto.
> >   (class vfmsub): Ditto.
> >   (class vfwmacc): Ditto.
> >   (class vfwnmacc): Ditto.
> >   (class vfwmsac): Ditto.
> >   (class vfwnmsac): Ditto.
> >   (class float_misc): Ditto.
> So in the expand method, you added a case for OP_TYPE_vx.  I assume that
> was intentional -- but it's not mentioned anywhere in the ChangeLog.  So
> please update the ChangeLog if it was intentional or remove the change
> if it wasn't intentional.  Pre-approved with whichever change is
> appropriate.
>
> Thanks,
> Jeff

Re: [PATCH v1] RISC-V: Support RVV VFREDOSUM.VS rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

lgtm

On Thu, Aug 17, 2023 at 2:23 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFREDOSUM.VS as the below samples.
>
> * __riscv_vfredosum_vs_f32m1_f32m1_rm
> * __riscv_vfredosum_vs_f32m1_f32m1_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (vfredosum_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfredosum_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-redosum.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  |  2 ++
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  1 +
>  .../riscv/rvv/base/float-point-redosum.c  | 33 +++
>  4 files changed, 37 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 65f1d9c8ff7..ef2991359da 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -2539,6 +2539,7 @@ static CONSTEXPR const 
> widen_reducop vwredsumu_obj;
>  static CONSTEXPR const freducop vfredusum_obj;
>  static CONSTEXPR const freducop vfredusum_frm_obj;
>  static CONSTEXPR const freducop vfredosum_obj;
> +static CONSTEXPR const freducop vfredosum_frm_obj;
>  static CONSTEXPR const reducop vfredmax_obj;
>  static CONSTEXPR const reducop vfredmin_obj;
>  static CONSTEXPR const widen_freducop vfwredusum_obj;
> @@ -2797,6 +2798,7 @@ BASE (vwredsumu)
>  BASE (vfredusum)
>  BASE (vfredusum_frm)
>  BASE (vfredosum)
> +BASE (vfredosum_frm)
>  BASE (vfredmax)
>  BASE (vfredmin)
>  BASE (vfwredosum)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index fd1a84f3e68..da8412b66df 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -241,6 +241,7 @@ extern const function_base *const vwredsumu;
>  extern const function_base *const vfredusum;
>  extern const function_base *const vfredusum_frm;
>  extern const function_base *const vfredosum;
> +extern const function_base *const vfredosum_frm;
>  extern const function_base *const vfredmax;
>  extern const function_base *const vfredmin;
>  extern const function_base *const vfwredosum;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 90a83c02d52..80e65bfb14b 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -501,6 +501,7 @@ DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, 
> f_vs_ops)
>  DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops)
>
>  DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
> +DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
>
>  // 14.4. Vector Widening Floating-Point Reduction Instructions
>  DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
> new file mode 100644
> index 000..2e6a3c28a89
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
> @@ -0,0 +1,33 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat32m1_t
> +test_riscv_vfredosum_vs_f32m1_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2,
> +   size_t vl) {
> +  return __riscv_vfredosum_vs_f32m1_f32m1_rm (op1, op2, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfredosum_vs_f32m1_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
> +   vfloat32m1_t op2, size_t vl) {
> +  return __riscv_vfredosum_vs_f32m1_f32m1_rm_m (mask, op1, op2, 1, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfredosum_vs_f32m1_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2,
> +size_t vl) {
> +  return __riscv_vfredosum_vs_f32m1_f32m1 (op1, op2, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfredosum_vs_f32m1_f32m1_m (vbool32_t mask, vfloat32m1_t op1,
> +vfloat32m1_t op2, size_t vl) {
> +  return __riscv_vfredosum_vs_f32m1_f32m1_m (mask, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times 
> {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
> +/* 

Re: [PATCH v1] RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

ok

On Thu, Aug 17, 2023 at 3:26 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFWREDOSUM.VS as the below samples
>
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm
> * __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (widen_freducop): Add frm_opt_type template arg.
> (vfwredosum_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfwredosum_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  |  9 -
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  2 ++
>  .../riscv/rvv/base/float-point-wredosum.c | 33 +++
>  4 files changed, 44 insertions(+), 1 deletion(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index ef2991359da..abf03bab0da 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1866,10 +1866,15 @@ public:
>  };
>
>  /* Implements widening floating-point reduction instructions.  */
> -template
> +template
>  class widen_freducop : public function_base
>  {
>  public:
> +  bool has_rounding_mode_operand_p () const override
> +  {
> +return FRM_OP == HAS_FRM;
> +  }
> +
>bool apply_mask_policy_p () const override { return false; }
>
>rtx expand (function_expander ) const override
> @@ -2544,6 +2549,7 @@ static CONSTEXPR const reducop vfredmax_obj;
>  static CONSTEXPR const reducop vfredmin_obj;
>  static CONSTEXPR const widen_freducop vfwredusum_obj;
>  static CONSTEXPR const widen_freducop vfwredosum_obj;
> +static CONSTEXPR const widen_freducop 
> vfwredosum_frm_obj;
>  static CONSTEXPR const vmv vmv_x_obj;
>  static CONSTEXPR const vmv_s vmv_s_obj;
>  static CONSTEXPR const vmv vfmv_f_obj;
> @@ -2802,6 +2808,7 @@ BASE (vfredosum_frm)
>  BASE (vfredmax)
>  BASE (vfredmin)
>  BASE (vfwredosum)
> +BASE (vfwredosum_frm)
>  BASE (vfwredusum)
>  BASE (vmv_x)
>  BASE (vmv_s)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index da8412b66df..c1bb164a712 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -245,6 +245,7 @@ extern const function_base *const vfredosum_frm;
>  extern const function_base *const vfredmax;
>  extern const function_base *const vfredmin;
>  extern const function_base *const vfwredosum;
> +extern const function_base *const vfwredosum_frm;
>  extern const function_base *const vfwredusum;
>  extern const function_base *const vmv_x;
>  extern const function_base *const vmv_s;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 80e65bfb14b..da1157f5a56 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -507,6 +507,8 @@ DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, 
> no_mu_preds, f_vs_ops)
>  DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
>  DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
>
> +DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops)
> +
>  /* 15. Vector Mask Instructions.  */
>
>  // 15.1. Vector Mask-Register Logical Instructions
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
> new file mode 100644
> index 000..acf79569a22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
> @@ -0,0 +1,33 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat64m1_t
> +test_riscv_vfwredosum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2,
> +size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1_rm (op1, op2, 0, vl);
> +}
> +
> +vfloat64m1_t
> +test_vfwredosum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
> +vfloat64m1_t op2, size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl);
> +}
> +
> +vfloat64m1_t
> +test_riscv_vfwredosum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2,
> + size_t vl) {
> +  return __riscv_vfwredosum_vs_f32m1_f64m1 (op1, op2, vl);
> +}
> +
> +vfloat64m1_t

Re: [PATCH] RISC-V: Fix incorrect VTYPE fusion for floating point scalar move insn[PR111037]

[Kito Cheng via Gcc-patches]

LGTM, thanks :)

On Thu, Aug 17, 2023 at 1:59 PM Juzhe-Zhong  wrote:
>
> void foo(_Float16 y, int64_t *i64p)
> {
>   vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
>   vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
>   vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
>   asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> }
>
> zve64f:
> foo:
> vsetivlizero,1,e16,mf4,ta,ma
> vle64.v v1,0(a0)
> vfmv.s.fv2,fa0
> vsetvli zero,zero,e64,m1,ta,ma
> vadd.vv v1,v1,v1
>
> zve64d:
> foo:
> vsetivlizero,1,e64,m1,ta,ma
> vle64.v v1,0(a0)
> vfmv.s.fv2,fa0
> vadd.vv v1,v1,v1
>
> PR target111037
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (float_insn_valid_sew_p): New function.
> (second_sew_less_than_first_sew_p): Fix bug.
> (first_sew_less_than_second_sew_p): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr111037-1.c: New test.
> * gcc.target/riscv/rvv/base/pr111037-2.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 22 +--
>  .../gcc.target/riscv/rvv/base/pr111037-1.c| 15 +
>  .../gcc.target/riscv/rvv/base/pr111037-2.c|  8 +++
>  3 files changed, 43 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 08c487d82c0..79cbac01047 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1183,18 +1183,36 @@ second_ratio_invalid_for_first_lmul_p (const 
> vector_insn_info ,
>return calculate_sew (info1.get_vlmul (), info2.get_ratio ()) == 0;
>  }
>
> +static bool
> +float_insn_valid_sew_p (const vector_insn_info , unsigned int sew)
> +{
> +  if (info.get_insn () && info.get_insn ()->is_real ()
> +  && get_attr_type (info.get_insn ()->rtl ()) == TYPE_VFMOVFV)
> +{
> +  if (sew == 16)
> +   return TARGET_VECTOR_ELEN_FP_16;
> +  else if (sew == 32)
> +   return TARGET_VECTOR_ELEN_FP_32;
> +  else if (sew == 64)
> +   return TARGET_VECTOR_ELEN_FP_64;
> +}
> +  return true;
> +}
> +
>  static bool
>  second_sew_less_than_first_sew_p (const vector_insn_info ,
>   const vector_insn_info )
>  {
> -  return info2.get_sew () < info1.get_sew ();
> +  return info2.get_sew () < info1.get_sew ()
> +|| !float_insn_valid_sew_p (info1, info2.get_sew ());
>  }
>
>  static bool
>  first_sew_less_than_second_sew_p (const vector_insn_info ,
>   const vector_insn_info )
>  {
> -  return info1.get_sew () < info2.get_sew ();
> +  return info1.get_sew () < info2.get_sew ()
> +|| !float_insn_valid_sew_p (info2, info1.get_sew ());
>  }
>
>  /* return 0 if LMUL1 == LMUL2.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> new file mode 100644
> index 000..0b7b32fc3e6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-1.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void foo(_Float16 y, int64_t *i64p)
> +{
> +  vint64m1_t vx =__riscv_vle64_v_i64m1 (i64p, 1);
> +  vx = __riscv_vadd_vv_i64m1 (vx, vx, 1);
> +  vfloat16m1_t vy =__riscv_vfmv_s_f_f16m1 (y, 1);
> +  asm volatile ("# use %0 %1" : : "vr"(vx), "vr" (vy));
> +}
> +
> +/* { dg-final { scan-assembler-times 
> {vsetivli\s+zero,\s*1,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> new file mode 100644
> index 000..ac50da71726
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111037-2.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
> +
> +#include "pr111037-1.c"
> +
> +/* { dg-final { scan-assembler-times 
> {vsetivli\s+zero,\s*1,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-not {vsetvli} } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */
> --
> 2.36.3
>

Re: [PATCH v1] RISC-V: Support RVV VFREDUSUM.VS rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

Lgtm

Pan Li via Gcc-patches 於 2023年8月17日 週四，11:09寫道：

> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFREDUSUM.VS as the below samples.
>
> * __riscv_vfredusum_vs_f32m1_f32m1_rm
> * __riscv_vfredusum_vs_f32m1_f32m1_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class freducop): Add frm_op_type template arg.
> (vfredusum_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfredusum_frm): New intrinsic function def.
> * config/riscv/riscv-vector-builtins-shapes.cc
> (struct reduc_alu_frm_def): New class for frm shape.
> (SHAPE): New declaration.
> * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-redusum.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  |  9 -
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  2 +
>  .../riscv/riscv-vector-builtins-shapes.cc | 39 +++
>  .../riscv/riscv-vector-builtins-shapes.h  |  1 +
>  .../riscv/rvv/base/float-point-redusum.c  | 33 
>  6 files changed, 84 insertions(+), 1 deletion(-)
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index ad04647f9ba..65f1d9c8ff7 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1847,10 +1847,15 @@ public:
>  };
>
>  /* Implements floating-point reduction instructions.  */
> -template
> +template
>  class freducop : public function_base
>  {
>  public:
> +  bool has_rounding_mode_operand_p () const override
> +  {
> +return FRM_OP == HAS_FRM;
> +  }
> +
>bool apply_mask_policy_p () const override { return false; }
>
>rtx expand (function_expander ) const override
> @@ -2532,6 +2537,7 @@ static CONSTEXPR const reducop vredxor_obj;
>  static CONSTEXPR const widen_reducop vwredsum_obj;
>  static CONSTEXPR const widen_reducop vwredsumu_obj;
>  static CONSTEXPR const freducop vfredusum_obj;
> +static CONSTEXPR const freducop
> vfredusum_frm_obj;
>  static CONSTEXPR const freducop vfredosum_obj;
>  static CONSTEXPR const reducop vfredmax_obj;
>  static CONSTEXPR const reducop vfredmin_obj;
> @@ -2789,6 +2795,7 @@ BASE (vredxor)
>  BASE (vwredsum)
>  BASE (vwredsumu)
>  BASE (vfredusum)
> +BASE (vfredusum_frm)
>  BASE (vfredosum)
>  BASE (vfredmax)
>  BASE (vfredmin)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index c8c649c4bb0..fd1a84f3e68 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -239,6 +239,7 @@ extern const function_base *const vredxor;
>  extern const function_base *const vwredsum;
>  extern const function_base *const vwredsumu;
>  extern const function_base *const vfredusum;
> +extern const function_base *const vfredusum_frm;
>  extern const function_base *const vfredosum;
>  extern const function_base *const vfredmax;
>  extern const function_base *const vfredmin;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index cfbc125dcd8..90a83c02d52 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -500,6 +500,8 @@ DEF_RVV_FUNCTION (vfredosum, reduc_alu, no_mu_preds,
> f_vs_ops)
>  DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, f_vs_ops)
>  DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops)
>
> +DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
> +
>  // 14.4. Vector Widening Floating-Point Reduction Instructions
>  DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
>  DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> index 80329113af3..f8fdec863e6 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> @@ -371,6 +371,44 @@ struct narrow_alu_frm_def : public build_frm_base
>}
>  };
>
> +/* reduc_alu_frm_def class.  */
> +struct reduc_alu_frm_def : public build_frm_base
> +{
> +  char *get_name (function_builder , const function_instance ,
> + bool overloaded_p) const override
> +  {
> +char base_name[BASE_NAME_MAX_LEN] = {};
> +
> +normalize_base_name (base_name, instance.base_name, sizeof
> (base_name));
> +
> +b.append_base_name 

Re: [PATCH v1] RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

Lgtm

Pan Li via Gcc-patches 於 2023年8月17日 週四，10:19寫道：

> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFNCVT.F.{X|XU|F}.W as the below samples.
>
> * __riscv_vfncvt_f_x_w_f32m1_rm
> * __riscv_vfncvt_f_x_w_f32m1_rm_m
> * __riscv_vfncvt_f_xu_w_f32m1_rm
> * __riscv_vfncvt_f_xu_w_f32m1_rm_m
> * __riscv_vfncvt_f_f_w_f32m1_rm
> * __riscv_vfncvt_f_f_w_f32m1_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (class vfncvt_f): Add frm_op_type template arg.
> (vfncvt_f_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfncvt_f_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  | 10 ++-
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  3 +
>  .../riscv/rvv/base/float-point-ncvt-f.c   | 69 +++
>  4 files changed, 82 insertions(+), 1 deletion(-)
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index acadec2afca..ad04647f9ba 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1786,9 +1786,15 @@ public:
>}
>  };
>
> +template
>  class vfncvt_f : public function_base
>  {
>  public:
> +  bool has_rounding_mode_operand_p () const override
> +  {
> +return FRM_OP == HAS_FRM;
> +  }
> +
>rtx expand (function_expander ) const override
>{
>  if (e.op_info->op == OP_TYPE_f_w)
> @@ -2512,7 +2518,8 @@ static CONSTEXPR const
> vfncvt_x vfncvt_xu_obj;
>  static CONSTEXPR const vfncvt_x
> vfncvt_xu_frm_obj;
>  static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj;
>  static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj;
> -static CONSTEXPR const vfncvt_f vfncvt_f_obj;
> +static CONSTEXPR const vfncvt_f vfncvt_f_obj;
> +static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj;
>  static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
>  static CONSTEXPR const reducop vredsum_obj;
>  static CONSTEXPR const reducop vredmaxu_obj;
> @@ -2769,6 +2776,7 @@ BASE (vfncvt_xu_frm)
>  BASE (vfncvt_rtz_x)
>  BASE (vfncvt_rtz_xu)
>  BASE (vfncvt_f)
> +BASE (vfncvt_f_frm)
>  BASE (vfncvt_rod_f)
>  BASE (vredsum)
>  BASE (vredmaxu)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 9bd09a41960..c8c649c4bb0 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -226,6 +226,7 @@ extern const function_base *const vfncvt_xu_frm;
>  extern const function_base *const vfncvt_rtz_x;
>  extern const function_base *const vfncvt_rtz_xu;
>  extern const function_base *const vfncvt_f;
> +extern const function_base *const vfncvt_f_frm;
>  extern const function_base *const vfncvt_rod_f;
>  extern const function_base *const vredsum;
>  extern const function_base *const vredmaxu;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 1e0e989fc2a..cfbc125dcd8 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -474,6 +474,9 @@ DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu,
> full_preds, f_to_nf_f_w_ops)
>
>  DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds,
> f_to_ni_f_w_ops)
>  DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds,
> f_to_nu_f_w_ops)
> +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds,
> i_to_nf_x_w_ops)
> +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds,
> u_to_nf_xu_w_ops)
> +DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds,
> f_to_nf_f_w_ops)
>
>  /* 14. Vector Reduction Operations.  */
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
> new file mode 100644
> index 000..d6d4be5e98e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
> @@ -0,0 +1,69 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat32m1_t
> +test_riscv_vfncvt_f_x_w_f32m1_rm (vint64m2_t op1, size_t vl) {
> +  return __riscv_vfncvt_f_x_w_f32m1_rm (op1, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfncvt_f_x_w_f32m1_rm_m (vbool32_t mask, vint64m2_t op1, size_t vl) {
> +  return __riscv_vfncvt_f_x_w_f32m1_rm_m (mask, op1, 1, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfncvt_f_xu_w_f32m1_rm (vuint64m2_t op1, size_t vl) {
> +  return 

Re: [PATCH v1] RISC-V: Support RVV VFNCVT.XU.F.W rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Aug 17, 2023 at 9:23 AM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFNCVT.XU.F.W as the below samples.
>
> * __riscv_vfncvt_xu_f_w_u16mf2_rm
> * __riscv_vfncvt_xu_f_w_u16mf2_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (vfncvt_xu_frm_obj): New declaration.
> (BASE): Ditto.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfncvt_xu_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-ncvt-xu.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  |  2 ++
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  1 +
>  .../riscv/rvv/base/float-point-ncvt-xu.c  | 29 +++
>  4 files changed, 33 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 2f40eeaeda5..acadec2afca 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -2509,6 +2509,7 @@ static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
>  static CONSTEXPR const vfncvt_x vfncvt_x_obj;
>  static CONSTEXPR const vfncvt_x vfncvt_x_frm_obj;
>  static CONSTEXPR const vfncvt_x vfncvt_xu_obj;
> +static CONSTEXPR const vfncvt_x 
> vfncvt_xu_frm_obj;
>  static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj;
>  static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj;
>  static CONSTEXPR const vfncvt_f vfncvt_f_obj;
> @@ -2764,6 +2765,7 @@ BASE (vfwcvt_f)
>  BASE (vfncvt_x)
>  BASE (vfncvt_x_frm)
>  BASE (vfncvt_xu)
> +BASE (vfncvt_xu_frm)
>  BASE (vfncvt_rtz_x)
>  BASE (vfncvt_rtz_xu)
>  BASE (vfncvt_f)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index edff0de2715..9bd09a41960 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -222,6 +222,7 @@ extern const function_base *const vfwcvt_f;
>  extern const function_base *const vfncvt_x;
>  extern const function_base *const vfncvt_x_frm;
>  extern const function_base *const vfncvt_xu;
> +extern const function_base *const vfncvt_xu_frm;
>  extern const function_base *const vfncvt_rtz_x;
>  extern const function_base *const vfncvt_rtz_xu;
>  extern const function_base *const vfncvt_f;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 5e37bae318a..1e0e989fc2a 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -473,6 +473,7 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, 
> f_to_nf_f_w_ops)
>  DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops)
>
>  DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops)
> +DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops)
>
>  /* 14. Vector Reduction Operations.  */
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
> new file mode 100644
> index 000..82c3e1364bf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint16mf2_t
> +test_riscv_vfncvt_xu_f_w_u16mf2_rm (vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfncvt_xu_f_w_u16mf2_rm (op1, 0, vl);
> +}
> +
> +vuint16mf2_t
> +test_vfncvt_xu_f_w_u16mf2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) 
> {
> +  return __riscv_vfncvt_xu_f_w_u16mf2_rm_m (mask, op1, 1, vl);
> +}
> +
> +vuint16mf2_t
> +test_riscv_vfncvt_xu_f_w_u16mf2 (vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfncvt_xu_f_w_u16mf2 (op1, vl);
> +}
> +
> +vuint16mf2_t
> +test_vfncvt_xu_f_w_u16mf2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfncvt_xu_f_w_u16mf2_m (mask, op1, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfncvt\.xu\.f\.w\s+v[0-9]+,\s*v[0-9]+} 
> 4 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
> --
> 2.34.1
>

Re: [PATCH v2] RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API

[Kito Cheng via Gcc-patches]

ok

On Wed, Aug 16, 2023 at 4:10 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> This patch would like to support the rounding mode API for the
> VFWCVT.X.F.V as the below samples.
>
> * __riscv_vfwcvt_xu_f_v_u64m2_rm
> * __riscv_vfwcvt_xu_f_v_u64m2_rm_m
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc
> (BASE): New declaration.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfwcvt_xu_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test.
> ---
>  .../riscv/riscv-vector-builtins-bases.cc  |  2 ++
>  .../riscv/riscv-vector-builtins-bases.h   |  1 +
>  .../riscv/riscv-vector-builtins-functions.def |  1 +
>  .../riscv/rvv/base/float-point-wcvt-xu.c  | 29 +++
>  4 files changed, 33 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 22640745398..6621c77c3f2 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -2497,6 +2497,7 @@ static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj;
>  static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
>  static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj;
>  static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
> +static CONSTEXPR const vfwcvt_x 
> vfwcvt_xu_frm_obj;
>  static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
>  static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
>  static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
> @@ -2750,6 +2751,7 @@ BASE (vfcvt_f_frm)
>  BASE (vfwcvt_x)
>  BASE (vfwcvt_x_frm)
>  BASE (vfwcvt_xu)
> +BASE (vfwcvt_xu_frm)
>  BASE (vfwcvt_rtz_x)
>  BASE (vfwcvt_rtz_xu)
>  BASE (vfwcvt_f)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index dd711846cbe..6565740c597 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -215,6 +215,7 @@ extern const function_base *const vfcvt_f_frm;
>  extern const function_base *const vfwcvt_x;
>  extern const function_base *const vfwcvt_x_frm;
>  extern const function_base *const vfwcvt_xu;
> +extern const function_base *const vfwcvt_xu_frm;
>  extern const function_base *const vfwcvt_rtz_x;
>  extern const function_base *const vfwcvt_rtz_xu;
>  extern const function_base *const vfwcvt_f;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 4e6cc793447..22c039c8cbb 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -460,6 +460,7 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, 
> u_to_wf_xu_v_ops)
>  DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
>
>  DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
> +DEF_RVV_FUNCTION (vfwcvt_xu_frm, alu_frm, full_preds, f_to_wu_f_v_ops)
>
>  // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
>  DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
> new file mode 100644
> index 000..29449e79b69
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint64m2_t
> +test_riscv_vfwcvt_xu_f_v_u64m2_rm (vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfwcvt_xu_f_v_u64m2_rm (op1, 0, vl);
> +}
> +
> +vuint64m2_t
> +test_vfwcvt_xu_f_v_u64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfwcvt_xu_f_v_u64m2_rm_m (mask, op1, 1, vl);
> +}
> +
> +vuint64m2_t
> +test_riscv_vfwcvt_xu_f_v_u64m2 (vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfwcvt_xu_f_v_u64m2 (op1, vl);
> +}
> +
> +vuint64m2_t
> +test_vfwcvt_xu_f_v_u64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
> +  return __riscv_vfwcvt_xu_f_v_u64m2_m (mask, op1, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 
> 4 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
> --
> 2.34.1
>

Re: [PATCH v1] RISC-V: Fix one build error for template default arg

[Kito Cheng via Gcc-patches]

ok

On Wed, Aug 16, 2023 at 5:44 PM Pan Li via Gcc-patches
 wrote:
>
> From: Pan Li 
>
> In some build option combination, the default value may result in
> below error. This patch would like to fix it by passing a explict
> argument.
>
> riscv-vector-builtins-bases.cc:2495:24: error: invalid use of template-name \
>   ‘riscv_vector::vfcvt_f’ without an argument list
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: Use explicit argument.
> ---
>  gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 22640745398..18453e54b51 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -2492,7 +2492,7 @@ static CONSTEXPR const vfcvt_x 
> vfcvt_xu_obj;
>  static CONSTEXPR const vfcvt_x 
> vfcvt_xu_frm_obj;
>  static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
>  static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
> -static CONSTEXPR const vfcvt_f vfcvt_f_obj;
> +static CONSTEXPR const vfcvt_f vfcvt_f_obj;
>  static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj;
>  static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
>  static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj;
> --
> 2.34.1
>