Re: [PATCH][v2] tree-optimization/115144 - improve sinking destination choice

[Patrick O'Neill]

Relevant bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220

Patrick

On Sun, May 26, 2024 at 2:30 AM Li, Pan2  wrote:
>
> Hi Richard,
>
> Looks this commit may result one ICE similar as below when build the newlib, 
> feel free to ping me if you need one PR for this.
>
> CC RISC-V port for awareness.
>
> In file included from 
> /home/pli/gcc/111/riscv-gnu-toolchain/newlib/newlib/libc/stdlib/setenv_r.c:26:
> /home/pli/gcc/111/riscv-gnu-toolchain/newlib/newlib/libc/include/stdlib.h: In 
> function '_setenv_r':
> /home/pli/gcc/111/riscv-gnu-toolchain/newlib/newlib/libc/include/stdlib.h:212:9:
>  error: stmt with wrong VUSE
>   212 | int _setenv_r (struct _reent *, const char *__string, const char 
> *__value, int __overwrite);
>   | ^
> # .MEM_109 = VDEF <.MEM_67>
> *C_59 = 61;
> expected .MEM_106
> during GIMPLE pass: sink
> /home/pli/gcc/111/riscv-gnu-toolchain/newlib/newlib/libc/include/stdlib.h:212:9:
>  internal compiler error: verify_ssa failed
>
> Pan
>
>
> -Original Message-
> From: Richard Biener 
> Sent: Friday, May 24, 2024 7:01 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH][v2] tree-optimization/115144 - improve sinking destination 
> choice
>
> When sinking code closer to its uses we already try to minimize the
> distance we move by inserting at the start of the basic-block.  The
> following makes sure to sink closest to the control dependence
> check of the region we want to sink to as well as make sure to
> ignore control dependences that are only guarding exceptional code.
> This restores somewhat the old profile check but without requiring
> nearly even probabilities.  The patch also makes sure to not give
> up completely when the best sink location is one we do not want to
> sink to but possibly then choose the next best one.
>
> This addresses fallout observed in building libgo.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
>
> PR tree-optimization/115144
> * tree-ssa-sink.cc (do_not_sink): New function, split out
> from ...
> (select_best_block): Here.  First pick valid block to
> sink to.  From that search for the best valid block,
> avoiding sinking across conditions to exceptional code.
> (sink_code_in_bb): When updating vuses of stores in
> paths we do not sink a store to make sure we didn't
> pick a dominating sink location.
>
> * gcc.dg/tree-ssa/ssa-sink-22.c: New testcase.
> ---
>  gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-22.c |  14 +++
>  gcc/tree-ssa-sink.cc| 106 +---
>  2 files changed, 86 insertions(+), 34 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-22.c
>
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-22.c 
> b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-22.c
> new file mode 100644
> index 000..e35626d4070
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-22.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fdump-tree-sink1-details" } */
> +
> +extern void abort (void);
> +
> +int foo (int x, int y, int f)
> +{
> +  int tem = x / y;
> +  if (f)
> +abort ();
> +  return tem;
> +}
> +
> +/* { dg-final { scan-tree-dump-not "Sinking" "sink1" } } */
> diff --git a/gcc/tree-ssa-sink.cc b/gcc/tree-ssa-sink.cc
> index 2188b7523c7..b0fe871cf1e 100644
> --- a/gcc/tree-ssa-sink.cc
> +++ b/gcc/tree-ssa-sink.cc
> @@ -172,6 +172,39 @@ nearest_common_dominator_of_uses (def_operand_p def_p, 
> bool *debug_stmts)
>return commondom;
>  }
>
> +/* Return whether sinking STMT from EARLY_BB to BEST_BB should be avoided.  
> */
> +
> +static bool
> +do_not_sink (gimple *stmt, basic_block early_bb, basic_block best_bb)
> +{
> +  /* Placing a statement before a setjmp-like function would be invalid
> + (it cannot be reevaluated when execution follows an abnormal edge).
> + If we selected a block with abnormal predecessors, just punt.  */
> +  if (bb_has_abnormal_pred (best_bb))
> +return true;
> +
> +  /* If the latch block is empty, don't make it non-empty by sinking
> + something into it.  */
> +  if (best_bb == early_bb->loop_father->latch
> +  && empty_block_p (best_bb))
> +return true;
> +
> +  /* Avoid turning an unconditional read into a conditional one when we
> + still might want to perform vectorization.  */
> +  if (best_bb->loop_father == early_bb->loop_father
> +  && loop_outer (best_bb->loop_father)
> +  && !best_bb->loop_father->inner
> +  && gimple_vuse (stmt)
> +  && !gimple_vdef (stmt)
> +  && flag_tree_loop_vectorize
> +  && !(cfun->curr_properties & PROP_loop_opts_done)
> +  && dominated_by_p (CDI_DOMINATORS, best_bb->loop_father->latch, 
> early_bb)
> +  && !dominated_by_p (CDI_DOMINATORS, best_bb->loop_father->latch, 
> best_bb))
> +return true;
> +
> +  return false;
> +}
> +
>  /* Given EARLY_BB and LATE_BB, two blocks in a path through the 

Re: [PATCH 1/2] RISC-V: Add tests for cpymemsi expansion

[Patrick O'Neill]

On 5/14/24 22:00, Christoph Müllner wrote:

On Fri, May 10, 2024 at 6:01 AM Patrick O'Neill  wrote:

Hi Christoph,

cpymemsi-1.c fails on a subset of newlib targets.

"UNRESOLVED: gcc.target/riscv/cpymemsi-1.c   -O0  compilation failed to
produce executable"

Full list of failing targets here (New Failures section):
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/906

Thanks for reporting!
I'm having a hard time figuring out what the issue is here, as I can't
reproduce it locally.
This test is an execution test ("dg-do run"), so I wonder if this
might be the issue?


riscv-gnu-toolchain configure command: ../configure --prefix=$(pwd) 
-with-arch=rv32imac_zba_zbb_zbc_zbs -with-abi=ilp32


Here's the verbose logs:

Executing on host: 
/scratch/tc-testing/tc-upstream/build/build-gcc-newlib-stage2/gcc/xgcc 
-B/scratch/tc-testing/tc-upstream/build/build-gcc-newlib-stage2/gcc/  
/scratch/tc-testing/tc-upstream/gcc/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
 -march=rv32imac_zba_zbb_zbc_zbs -mabi=ilp32 -mcmodel=medlow   
-fdiagnostics-plain-output    -O0  -march=rv32gc -save-temps -g0 -fno-lto 
-DRUN_FRACTION=11  -lm  -o ./cpymemsi-1.exe    (timeout = 1200)
spawn -ignore SIGHUP 
/scratch/tc-testing/tc-upstream/build/build-gcc-newlib-stage2/gcc/xgcc 
-B/scratch/tc-testing/tc-upstream/build/build-gcc-newlib-stage2/gcc/ 
/scratch/tc-testing/tc-upstream/gcc/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
-march=rv32imac_zba_zbb_zbc_zbs -mabi=ilp32 -mcmodel=medlow 
-fdiagnostics-plain-output -O0 -march=rv32gc -save-temps -g0 -fno-lto 
-DRUN_FRACTION=11 -lm -o ./cpymemsi-1.exe
xgcc: fatal error: Cannot find suitable multilib set for 
'-march=rv32imafdc_zicsr_zifencei'/'-mabi=ilp32'
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/cpymemsi-1.c   -O0  (test for excess errors)

Looks like it's only failing on targets without the 'f' extension so 
maybe we need to add a riscv_f to avoid running on non-f targets 
(similar to what we have for riscv_v)?


Patrick

Re: [PATCH v2 2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

[Patrick O'Neill]

On 5/13/24 20:36, Jeff Law wrote:



On 5/13/24 6:54 PM, Patrick O'Neill wrote:


On 5/13/24 13:28, Jeff Law wrote:



On 5/13/24 12:49 PM, Vineet Gupta wrote:
If the constant used for stack offset can be expressed as sum of 
two S12
values, the constant need not be materialized (in a reg) and 
instead the

two S12 bits can be added to instructions involved with frame pointer.
This avoids burning a register and more importantly can often get down
to be 2 insn vs. 3.

The prev patches to generally avoid LUI based const materialization 
didn't

fix this PR and need this directed fix in funcion prologue/epilogue
expansion.

This fix doesn't move the neddle for SPEC, at all, but it is still a
win considering gcc generates one insn fewer than llvm for the test 
;-)


    gcc-13.1 release   |  gcc 230823 | |
   |    g6619b3d4c15c    |   This patch | 
clang/llvm
- 

li  t0,-4096 | li    t0,-4096  | addi sp,sp,-2048 | 
addi sp,sp,-2048
addi    t0,t0,2016   | addi  t0,t0,2032    | add sp,sp,-16   | addi 
sp,sp,-32
li  a4,4096  | add   sp,sp,t0  | add a5,sp,a0    | add 
a1,sp,16
add sp,sp,t0 | addi  a5,sp,-2032   | sb zero,0(a5)  | add 
a0,a0,a1
li  a5,-4096 | add   a0,a5,a0  | addi sp,sp,2032  | sb 
zero,0(a0)
addi    a4,a4,-2032  | li    t0, 4096  | addi sp,sp,32    | 
addi sp,sp,2032
add a4,a4,a5 | sb    zero,2032(a0) | ret   | 
addi sp,sp,48

addi    a5,sp,16 | addi  t0,t0,-2032 |   | ret
add a5,a4,a5 | add   sp,sp,t0  |
add a0,a5,a0 | ret |
li  t0,4096  |
sd  a5,8(sp) |
sb  zero,2032(a0)|
addi    t0,t0,-2016  |
add sp,sp,t0 |
ret  |

gcc/ChangeLog:
PR target/105733
* config/riscv/riscv.h: New macros for with aligned offsets.
* config/riscv/riscv.cc (riscv_split_sum_of_two_s12): New
function to split a sum of two s12 values into constituents.
(riscv_expand_prologue): Handle offset being sum of two S12.
(riscv_expand_epilogue): Ditto.
* config/riscv/riscv-protos.h (riscv_split_sum_of_two_s12): New.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105733.c: New Test.
* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Adjust to not
expect LUI 4096.
* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.





@@ -8074,14 +8111,26 @@ riscv_expand_epilogue (int style)
  }
    else
  {
-  if (!SMALL_OPERAND (adjust_offset.to_constant ()))
+  HOST_WIDE_INT adj_off_value = adjust_offset.to_constant ();
+  if (SMALL_OPERAND (adj_off_value))
+    {
+  adjust = GEN_INT (adj_off_value);
+    }
+  else if (SUM_OF_TWO_S12_ALGN (adj_off_value))
+    {
+  HOST_WIDE_INT base, off;
+  riscv_split_sum_of_two_s12 (adj_off_value, , );
+  insn = gen_add3_insn (stack_pointer_rtx, 
hard_frame_pointer_rtx,

+    GEN_INT (base));
+  RTX_FRAME_RELATED_P (insn) = 1;
+  adjust = GEN_INT (off);
+    }
So this was the hunk that we identified internally as causing 
problems with libgomp's testsuite.  We never fully chased it down as 
this hunk didn't seem terribly important performance wise -- we just 
set it aside.  The thing is it looked basically correct to me.  So 
the failure was certainly unexpected, but it was consistent.


So I think the question is whether or not the CI system runs the 
libgomp testsuite, particularly in the rv64 linux configuration. If 
it does, and it passes, then we're good. I'm still finding my way 
around the configuration, so I don't know if the CI system Edwin & 
Patrick have built tests libgomp or not.


I poked around the .sum files in pre/postcommit and we do run tests 
like:


PASS: c-c++-common/gomp/affinity-2.c  (test for errors, line 45)

I was able to find the summary info:


Tests that now fail, but worked before (15 tests):
libgomp: libgomp.fortran/simd7.f90   -O0  execution test
libgomp: libgomp.fortran/task2.f90   -O0  execution test
libgomp: libgomp.fortran/vla2.f90   -O0  execution test
libgomp: libgomp.fortran/vla3.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test

libgomp: libgomp.fortran/vla3.f90   -O3 -g  execution test
libgomp: libgomp.fortran/vla4.f90   -O1  execution test
libgomp: libgomp.fortran/vla4.f90   -O2  execution test
libgomp: libgomp.fortran/vla4.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test

libgomp: libgomp.fortran/vla4.f90   -O3 -g  execution test
libgomp: libgomp.fortran/

Re: [PATCH v2 2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

[Patrick O'Neill]

On 5/13/24 13:28, Jeff Law wrote:



On 5/13/24 12:49 PM, Vineet Gupta wrote:

If the constant used for stack offset can be expressed as sum of two S12
values, the constant need not be materialized (in a reg) and instead the
two S12 bits can be added to instructions involved with frame pointer.
This avoids burning a register and more importantly can often get down
to be 2 insn vs. 3.

The prev patches to generally avoid LUI based const materialization 
didn't

fix this PR and need this directed fix in funcion prologue/epilogue
expansion.

This fix doesn't move the neddle for SPEC, at all, but it is still a
win considering gcc generates one insn fewer than llvm for the test ;-)

    gcc-13.1 release   |  gcc 230823 | |
   |    g6619b3d4c15c    |   This patch |  
clang/llvm
- 

li  t0,-4096 | li    t0,-4096  | addi  sp,sp,-2048 | addi 
sp,sp,-2048
addi    t0,t0,2016   | addi  t0,t0,2032    | add   sp,sp,-16   | addi 
sp,sp,-32
li  a4,4096  | add   sp,sp,t0  | add   a5,sp,a0    | add  
a1,sp,16
add sp,sp,t0 | addi  a5,sp,-2032   | sb    zero,0(a5)  | add  
a0,a0,a1
li  a5,-4096 | add   a0,a5,a0  | addi  sp,sp,2032  | sb   
zero,0(a0)
addi    a4,a4,-2032  | li    t0, 4096  | addi  sp,sp,32    | addi 
sp,sp,2032
add a4,a4,a5 | sb    zero,2032(a0) | ret   | addi 
sp,sp,48

addi    a5,sp,16 | addi  t0,t0,-2032   |   | ret
add a5,a4,a5 | add   sp,sp,t0  |
add a0,a5,a0 | ret |
li  t0,4096  |
sd  a5,8(sp) |
sb  zero,2032(a0)|
addi    t0,t0,-2016  |
add sp,sp,t0 |
ret  |

gcc/ChangeLog:
PR target/105733
* config/riscv/riscv.h: New macros for with aligned offsets.
* config/riscv/riscv.cc (riscv_split_sum_of_two_s12): New
function to split a sum of two s12 values into constituents.
(riscv_expand_prologue): Handle offset being sum of two S12.
(riscv_expand_epilogue): Ditto.
* config/riscv/riscv-protos.h (riscv_split_sum_of_two_s12): New.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr105733.c: New Test.
* gcc.target/riscv/rvv/autovec/vls/spill-1.c: Adjust to not
expect LUI 4096.
* gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.





@@ -8074,14 +8111,26 @@ riscv_expand_epilogue (int style)
  }
    else
  {
-  if (!SMALL_OPERAND (adjust_offset.to_constant ()))
+  HOST_WIDE_INT adj_off_value = adjust_offset.to_constant ();
+  if (SMALL_OPERAND (adj_off_value))
+    {
+  adjust = GEN_INT (adj_off_value);
+    }
+  else if (SUM_OF_TWO_S12_ALGN (adj_off_value))
+    {
+  HOST_WIDE_INT base, off;
+  riscv_split_sum_of_two_s12 (adj_off_value, , );
+  insn = gen_add3_insn (stack_pointer_rtx, 
hard_frame_pointer_rtx,

+    GEN_INT (base));
+  RTX_FRAME_RELATED_P (insn) = 1;
+  adjust = GEN_INT (off);
+    }
So this was the hunk that we identified internally as causing problems 
with libgomp's testsuite.  We never fully chased it down as this hunk 
didn't seem terribly important performance wise -- we just set it 
aside.  The thing is it looked basically correct to me.  So the 
failure was certainly unexpected, but it was consistent.


So I think the question is whether or not the CI system runs the 
libgomp testsuite, particularly in the rv64 linux configuration. If it 
does, and it passes, then we're good.  I'm still finding my way around 
the configuration, so I don't know if the CI system Edwin & Patrick 
have built tests libgomp or not.


I poked around the .sum files in pre/postcommit and we do run tests like:

PASS: c-c++-common/gomp/affinity-2.c  (test for errors, line 45)

I'm not familar with libgomp so I don't know if that's the same libgomp 
tests you're referring to.


Patrick



If it isn't run, then we'll need to do a run to test that.  I'm set up 
here to do that if needed.   I can just drop this version into our 
internal tree, trigger an internal CI run and see if it complains :-)


If it does complain, then we know where to start investigations.




Jeff

Re: [PATCH 1/2] RISC-V: Add tests for cpymemsi expansion

[Patrick O'Neill]

Hi Christoph,

cpymemsi-1.c fails on a subset of newlib targets.

"UNRESOLVED: gcc.target/riscv/cpymemsi-1.c   -O0  compilation failed to 
produce executable"


Full list of failing targets here (New Failures section): 
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/906


Thanks,

Patrick

On 5/7/24 22:52, Christoph Müllner wrote:

cpymemsi expansion was available for RISC-V since the initial port.
However, there are not tests to detect regression.
This patch adds such tests.

Three of the tests target the expansion requirements (known length and
alignment). One test reuses an existing memcpy test from the by-pieces
framework (gcc/testsuite/gcc.dg/torture/inline-mem-cpy-1.c).

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cpymemsi-1.c: New test.
* gcc.target/riscv/cpymemsi-2.c: New test.
* gcc.target/riscv/cpymemsi-3.c: New test.
* gcc.target/riscv/cpymemsi.c: New test.

Signed-off-by: Christoph Müllner 
---

[Committed] RISC-V: Add testcase for pr114734

[Patrick O'Neill]

On 4/30/24 15:03, Jeff Law wrote:


On 4/30/24 2:36 PM, Patrick O'Neill wrote:

gcc/testsuite/ChangeLog:

PR middle-end/114734

* gcc.target/riscv/rvv/autovec/pr114734.c: New test.

OK
jeff


Committed.

Patrick

Re: [committed] [RISC-V] Improve floor, ceil & related operations for RISC-V

[Patrick O'Neill]

Hi Jeff,


It looks like this patch's gcc.target/riscv/round_64.c testcase doesn't 
pass when run with newlib.


It also introduced:

FAIL: gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-2.c execution 
test


on rv32gcv newlib/linux.


Precommit with a few targets: 
https://github.com/ewlu/gcc-precommit-ci/issues/1454


Postcommit with all targets: 
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/853


Untrimmed postcommit output: 
https://github.com/patrick-rivos/gcc-postcommit-ci/actions/runs/8899731577/job/24456991643#step:8:132



Thanks,

Patrick


On 4/30/24 08:46, Jeff Law wrote:

This is almost exclusively Jivan's work.  His original post:



https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg336483.html





This patch is primarily meant to improve the code we generate for FP 
rounding such as ceil/floor.  It also addresses some unnecessary sign 
extensions in the same areas.


RISC-V's FP conversions have a bit of undesirable behavior that make 
them non-suitable as-is for ceil/floor and other related functions. 
These deficiencies are addressed in the Zfa extension, but there's no 
reason not to pick up a nice improvement when we can.


Basically we can still use the basic FP conversions for floor/ceil and 
friends when we don't care about inexact exceptions by checking for 
the special cases first, then emitting the conversion when the special 
cases don't apply.  That's still much faster than calling into glibc.


The redundant sign extensions are eliminated using the same trick 
Jivan added last year, just in a few more places ;-)


This eliminates roughly 10% of the dynamic instruction count for 
imagick.  But more importantly it's about a 17% performance 
improvement for that workload within spec.


This has been bootstrapped as well as regression tested in a cross 
environment.  It's also successfully built & run specint/specfp 
correctly.


Pushing to the trunk and the coordination branch momentarily.


Jeff

[PATCH] RISC-V: Add testcase for pr114734

[Patrick O'Neill]

gcc/testsuite/ChangeLog:

PR middle-end/114734

* gcc.target/riscv/rvv/autovec/pr114734.c: New test.

Signed-off-by: Patrick O'Neill 
---
Tested on rv64gcv before and after Richard Biener's fix:
4d3a5618de5a949c61605f545f90e81bc502
---
 .../gcc.target/riscv/rvv/autovec/pr114734.c   | 25 +++
 1 file changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644
index 000..b605d992aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3 
-mrvv-vector-bits=zvl  } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+  for (int m = 0; m < 18; ++m)
+f[m] = 3;
+  for (int m = 0; m < 18; m += 1)
+for (int n = 0; n < 18; n += 3) {
+  a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+  b[n] = f[n] ? -i[m] : 0;
+}
+  for (long n = 0; n < 8; ++n)
+z = a[n];
+  if (b[15] != 0)
+__builtin_abort();
+}
-- 
2.34.1

Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

[Patrick O'Neill]

Hi Pan,

Sorry about that. It looks like there was difference between my local 
machine and CI machine.


From the CI it looks like we're back to the failure list we had on friday.

I'll do some local testing to manually confirm this.

Thanks,
Patrick

On 4/22/24 23:50, Li, Pan2 wrote:


Hi Patrick,

After some investigation and double confirm, I think the 
gcc.dg/graphite/pr111878.c ice may have nothing to do
with the patches of revert series as it exists for quit a while. It may related 
to below commit

2e7abd09621a4401d44f4513adf126bce4b4828b RISC-V: Block VLSmodes according to 
TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

Could you please help to double check about it *manually*? Here is my step(s) 
for your reference and I will take care of this failure soon.

../__RISC-V_INSTALL___RV64/bin/riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (GCC) 14.0.0 20231205 (experimental)
Copyright (C) 2023 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

1. download isl-0.24, let isl -> /some-where/riscv-gnu-toolchain/gcc/isl-0.24
2. mkdir __BUILD__ && cd __BUILD__ && ../configure \
   --target=riscv64-unknown-elf \
   --prefix=${INSTALL_DIR} \
   --disable-shared \
   --enable-threads \
   --enable-tls \
   --enable-languages=c,c++,fortran \
   --with-system-zlib \
   --with-newlib \
   --disable-libmudflap \
   --disable-libssp \
   --disable-libquadmath \
   --disable-libgomp \
   --enable-nls \
   --disable-tm-clone-registry \
   --src=`pwd`/../ \
   --with-abi=lp64d \
   --with-arch=rv64gcv \
   --with-tune=rocket \
   --with-isa-spec=20191213 \
   CFLAGS_FOR_BUILD="-O0 -g" \
   CXXFLAGS_FOR_BUILD="-O0 -g" \
   CFLAGS_FOR_TARGET="-O0  -g" \
   CXXFLAGS_FOR_TARGET="-O0 -g" \
   BOOT_CFLAGS="-O0 -g" \
   CFLAGS="-O0 -g" \
   CXXFLAGS="-O0 -g" \
   GM2FLAGS_FOR_TARGET="-O0 -g" \
   GOCFLAGS_FOR_TARGET="-O0 -g" \
   GDCFLAGS_FOR_TARGET="-O0 -g"
make -j $(nproc) all-gcc && make install-gcc
3. ../__RISC-V_INSTALL___RV64/bin/riscv64-unknown-elf-gcc 
gcc/testsuite/gcc.dg/graphite/pr111878.c -O3 -fgraphite-identity 
-fsave-optimization-record -march=rv64gcv -mabi=lp64d -c -S -o -

Pan

-Original Message-
From: Li, Pan2
Sent: Tuesday, April 23, 2024 10:32 AM
To: Patrick O'Neill ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: RE: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d 
and e65aaf8efe1

Thanks Patrick.

Turn out that the make report cannot tell the error like below and then the 
graphite.exp test will never run.
That explains why I missed test failures, will take care of it ASAP.

sorry, unimplemented: Graphite loop optimizations cannot be used (isl is not 
available)

Pan

-Original Message-
From: Patrick O'Neill 
Sent: Tuesday, April 23, 2024 8:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d 
and e65aaf8efe1

This patch in particular does not cause any more regressions. It's one
of the other reverts from the weekend.

Before the reverts [1]:
                      |  gcc |
g++ | gfortran |
      rv64gcv/  lp64d/ medlow |   48/    32 |     12/    3|   12 /    2

After the reverts:
                      |  gcc |
g++ | gfortran |
      rv64gcv/  lp64d/ medlow |   50 /    33 |   12 / 3 |   26 / 7 |


gcc new fails:
FAIL: gcc.dg/graphite/pr111878.c (internal compiler error: in
extract_insn, at recog.cc:2812)
FAIL: gcc.dg/graphite/pr111878.c (test for excess errors)

gfortran new fails:
FAIL: gfortran.dg/graphite/id-27.f90   -O  (internal compiler error: in
extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/id-27.f90   -O  (test for excess errors)
FAIL: gfortran.dg/graphite/pr14741.f90   -O  (internal compiler error:
in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/pr14741.f90   -O  (test for excess errors)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
compiler error: in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  (test for
excess errors)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (internal compiler
error: in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (test for excess errors)
FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
compiler error: in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphit

Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

[Patrick O'Neill]

This patch in particular does not cause any more regressions. It's one 
of the other reverts from the weekend.


Before the reverts [1]:
                    |  gcc |  
g++ | gfortran |

    rv64gcv/  lp64d/ medlow |   48/    32 |     12/    3|   12 /    2

After the reverts:
                    |  gcc |  
g++ | gfortran |

    rv64gcv/  lp64d/ medlow |   50 /    33 |   12 / 3 |   26 / 7 |


gcc new fails:
FAIL: gcc.dg/graphite/pr111878.c (internal compiler error: in 
extract_insn, at recog.cc:2812)

FAIL: gcc.dg/graphite/pr111878.c (test for excess errors)

gfortran new fails:
FAIL: gfortran.dg/graphite/id-27.f90   -O  (internal compiler error: in 
extract_insn, at recog.cc:2812)

FAIL: gfortran.dg/graphite/id-27.f90   -O  (test for excess errors)
FAIL: gfortran.dg/graphite/pr14741.f90   -O  (internal compiler error: 
in extract_insn, at recog.cc:2812)

FAIL: gfortran.dg/graphite/pr14741.f90   -O  (test for excess errors)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal 
compiler error: in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (test for 
excess errors)
FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (internal compiler 
error: in extract_insn, at recog.cc:2812)

FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (test for excess errors)
FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal 
compiler error: in extract_insn, at recog.cc:2812)
FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (test for 
excess errors)
FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (internal compiler 
error: in extract_insn, at recog.cc:2812)

FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (test for excess errors)
FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (internal compiler 
error: in extract_insn, at recog.cc:2812)

FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (test for excess errors)


For future reference, the precommit does not do well with many unrelated 
patches that are dependent on eachother.
In the future sending these as a series would allow precommit to 
properly test them (as always you can see the testing results on 
patchworks).


Thanks,
Patrick

[1] https://github.com/patrick-rivos/gcc-postcommit-ci/issues/801

On 4/22/24 12:55, Patrick O'Neill wrote:

Hi Pan,

I was running the testsuite for this and noticed an ICE scroll by when 
this patch is applied to cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 for 
rv64gcv:


FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal 
compiler error: in extract_insn, at recog.cc:2812)


I'll send the full list of new failures once the runs finish.

Thanks,
Patrick

On 4/22/24 06:47, pan2...@intel.com wrote:

From: Pan Li 

After we reverted below 2 commits, the reference to attr need some
adjustment as the group_overlap is no longer available.

* RISC-V: Robostify the W43, W86, W87 constraint enabled attribute
* RISC-V: Rename vconstraint into group_overlap

The below tests are passed for this patch.

* The rv64gcv fully regression tests.

gcc/ChangeLog:

* config/riscv/vector-crypto.md:

Signed-off-by: Pan Li 
---
  gcc/config/riscv/vector-crypto.md | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/vector-crypto.md 
b/gcc/config/riscv/vector-crypto.md

index 519c6a10d94..23dc549e5b8 100755
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -322,7 +322,7 @@ (define_insn "@pred_vwsll_scalar"
    "vwsll.v%o4\t%0,%3,%4%p1"
    [(set_attr "type" "vwsll")
 (set_attr "mode" "")
-   (set_attr "group_overlap" 
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
+   (set_attr "vconstraint" 
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,no,no")])

    ;; vbrev.v vbrev8.v vrev8.v
  (define_insn "@pred_v"

Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1

[Patrick O'Neill]

Hi Pan,

I was running the testsuite for this and noticed an ICE scroll by when 
this patch is applied to cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 for 
rv64gcv:


FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  (internal 
compiler error: in extract_insn, at recog.cc:2812)


I'll send the full list of new failures once the runs finish.

Thanks,
Patrick

On 4/22/24 06:47, pan2...@intel.com wrote:

From: Pan Li 

After we reverted below 2 commits, the reference to attr need some
adjustment as the group_overlap is no longer available.

* RISC-V: Robostify the W43, W86, W87 constraint enabled attribute
* RISC-V: Rename vconstraint into group_overlap

The below tests are passed for this patch.

* The rv64gcv fully regression tests.

gcc/ChangeLog:

* config/riscv/vector-crypto.md:

Signed-off-by: Pan Li 
---
  gcc/config/riscv/vector-crypto.md | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/vector-crypto.md 
b/gcc/config/riscv/vector-crypto.md
index 519c6a10d94..23dc549e5b8 100755
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -322,7 +322,7 @@ (define_insn "@pred_vwsll_scalar"
"vwsll.v%o4\t%0,%3,%4%p1"
[(set_attr "type" "vwsll")
 (set_attr "mode" "")
-   (set_attr "group_overlap" 
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
+   (set_attr "vconstraint" 
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,no,no")])
  
  ;; vbrev.v vbrev8.v vrev8.v

  (define_insn "@pred_v"

Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and xfail tests

[Patrick O'Neill]

Hi Pan,


I'm not sure I'm following.  Did we miss something that should have been
covered?  Like only an overlap on the srcs but not the dest?
Are there testcases that fail?  If so we should definitely have one.

Can you give some additional information on why these reverts are needed?
+1 to the request for a failing testcase if there is one.Patrick

If something is broken then indeed we should revert it.

Yes, we may need to support these in gcc-15.


... why not just revert everything and xfail all the tests in a
follow up?  Your patch is essentially a revert but doesn't look like
it.  I'd rather we let a revert be a revert and adjust the tests
separately so it becomes clear.

Sure, will revert b3b2799b872 and then file the patch for the xfail tests.

Pan

[Committed] RISC-V: Require a extension for ztso testcases with atomic insns

[Patrick O'Neill]

On 3/22/24 07:22, Palmer Dabbelt wrote:

On Thu, 21 Mar 2024 10:00:24 PDT (-0700), Patrick O'Neill wrote:

Use dg_add_options riscv_a to add atomic extension when running compile
tests on non-a targets.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add
  dg_add_options riscv_a
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.

Signed-off-by: Patrick O'Neill 


Presumably these trip up on the non-A targets that Edwin's just adding 
to the

testers?  They'd also trip up anyone running newlib/mulilib tests.

Either way they look right to me, so

Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

Thanks!


Committed - Thanks!

And yes, this was in response to the rv32/64imc_* targets that Edwin was 
adding to ci.


Patrick

[PATCH] RISC-V: Require a extension for ztso testcases with atomic insns

[Patrick O'Neill]

Use dg_add_options riscv_a to add atomic extension when running compile
tests on non-a targets.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add
  dg_add_options riscv_a
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.

Signed-off-by: Patrick O'Neill 
---
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c| 1 +
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c| 1 +
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c| 1 +
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c| 1 +
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c| 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-1.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-2.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-3.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-4.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-5.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-6.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-7.c | 1 +
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c  | 1 +
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c  | 1 +
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c  | 1 +
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c  | 1 +
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c  | 1 +
 17 files changed, 17 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index 65a4351025d..a9edc33ff39 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index 03da6b04de0..ad843402bcc 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
index 695306e9d6f..bdae5bb83a6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
index e7e5ac7cc88..815a72f1e56 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op m

Re: [PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

[Patrick O'Neill]

On 2/28/24 07:02, Palmer Dabbelt wrote:

On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote:



On 2/28/24 05:23, Kito Cheng wrote:
atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic 
operation on
RV64, however lr.w is doing sign extend to DI and compare 
instruction only have
DI mode on RV64, so the expected value should be sign extend before 
compare as

well, so that we can get right compare result.

gcc/ChangeLog:

PR target/114130
* config/riscv/sync.md (atomic_compare_and_swap): Sign
extend the expected value if needed.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr114130.c: New.

Nearly rejected this as I think the description was a bit ambiguous and
I thought you were extending the result of the lr.w.  But it's actually
the other value you're ensuring gets properly extended.


I had the same response, but after reading it I'm not quite sure how 
to say it better.



OK.


I was looking at the code to try and ask if we have the same bug for 
the short inline CAS routines, but I've got to run to some meetings...


I don't think subword AMO CAS is impacted.

As part of the CAS we mask both the expected value [2] and the retrieved 
value[1] before comparing.


- Patrick

[1]: 
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/riscv/sync.md;h=54bb0a66518ae353fa4ed640339213bf5da6682c;hb=refs/heads/master#l495
[2]: 
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/riscv/sync.md;h=54bb0a66518ae353fa4ed640339213bf5da6682c;hb=refs/heads/master#l459






Jeff

[RFC 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support

[Patrick O'Neill]

Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A.
* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather
than A.
* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather
than A.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc 
rather
than A.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
* lib/target-supports.exp: Add testsuite infrastructure support for
Zaamo and Zalrsc.

Signed-off-by: Patrick O'Neill 
---
 .../riscv/amo-table-a-6-amo-add-1.c   |  2 +-
 .../riscv/amo-table-a-6-amo-add-2.c   |  2 +-
 .../riscv/amo-table-a-6-amo-add-3.c   |  2 +-
 .../riscv/amo-table-a-6-amo-add-4.c   |  2 +-
 .../riscv/amo-table-a-6-amo-add-5.c   |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-1.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-2.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-3.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-4.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-5.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-6.c  |  2 +-
 .../riscv/amo-table-a-6-compare-exchange-7.c  |  2 +-
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |  2 +-
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |  2 +-
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |  2 +-
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |  2 +-
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |  2 +-
 .../riscv/amo-table-ztso-amo-add-1.c  |  1 +
 .../riscv/amo-table-ztso-amo-add-2.c  |  1 +
 .../riscv/amo-table-ztso-amo-add-3.c  |  1 +
 .../riscv/amo-table-ztso-amo-add-4.c  |  1 +
 .../riscv/amo-table-ztso-amo-add-5.c  |  1 +
 .../riscv/amo-table-ztso-compare-exchange-1.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-2.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-3.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-4.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-5.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-6.c |  1 +
 .../riscv/amo-table-ztso-compare-exchange-7.c |  1 +
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |  1 +
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |  1 +
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |  1 +
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |  1 +
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |  1 +
 gcc/testsuite/lib/target-supports.exp | 48 ++-
 35 files changed, 81 insertions(+), 18 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
index 8ab1a02b40c..9c2ba39789a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings

[RFC 3/3] RISC-V: Add Zalrsc amo-op patterns

[Patrick O'Neill]

All amo patterns can be represented with lrsc sequences.
Add these patterns as a fallback when Zaamo is not enabled.

gcc/ChangeLog:

* config/riscv/sync.md (atomic_): New expand 
pattern.
(amo_atomic_): Rename amo pattern.
(atomic_fetch_): New lrsc sequence pattern.
(lrsc_atomic_): New expand pattern.
(amo_atomic_fetch_): Rename amo pattern.
(lrsc_atomic_fetch_): New lrsc sequence pattern.
(atomic_exchange): New expand pattern.
(amo_atomic_exchange): Rename amo pattern.
(lrsc_atomic_exchange): New lrsc sequence pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test.

Signed-off-by: Patrick O'Neill 
--
rv64imfdc_zalrsc has the same testsuite results as rv64imafdc after this
patch is applied.
---
AFAIK there isn't a way to subtract an extension similar to dg-add-options.
As a result I needed to specify a -march string for
amo-zaamo-preferred-over-zalrsc.c instead of using testsuite infra.
---
 gcc/config/riscv/sync.md  | 124 +-
 .../riscv/amo-zaamo-preferred-over-zalrsc.c   |  17 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-1.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-2.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-3.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-4.c   |  19 +++
 .../gcc.target/riscv/amo-zalrsc-amo-add-5.c   |  19 +++
 7 files changed, 231 insertions(+), 5 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 0b4ac914327..a808c530291 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -86,7 +86,24 @@
 DONE;
   })

-(define_insn "atomic_"
+;; AMO ops
+
+(define_expand "atomic_"
+  [(any_atomic:GPR (match_operand:GPR 0 "memory_operand");; mem location
+  (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op
+   (match_operand:SI 2 "const_int_operand")];; model
+  "TARGET_ZAAMO || TARGET_ZALRSC"
+{
+  if (TARGET_ZAAMO)
+emit_insn (gen_amo_atomic_ (operands[0], operands[1],
+   operands[2]));
+  else
+emit_insn (gen_lrsc_atomic_ (operands[0], operands[1],
+operands[2]));
+  DONE;
+})
+
+(define_insn "amo_atomic_"
   [(set (match_operand:GPR 0 "memory_operand" "+A")
(unspec_volatile:GPR
  [(any_atomic:GPR (match_dup 0)
@@ -98,7 +115,44 @@
   [(set_attr "type" "atomic")
(set (attr "length") (const_int 4))])

-(define_insn "atomic_fetch_"
+(define_insn "lrsc_atomic_"
+  [(set (match_operand:GPR 0 "memory_operand" "+A")
+   (unspec_volatile:GPR
+ [(any_atomic:GPR (match_dup 0)
+(match_operand:GPR 1 "reg_or_0_operand" "rJ"))
+  (match_operand:SI 2 "const_int_operand")] ;; model
+UNSPEC_SYNC_OLD_OP))
+   (clobber (match_scratch:GPR 3 "="))]   ;; tmp_1
+  "!TARGET_ZAAMO && TARGET_ZALRSC"
+  {
+return "1:\;"
+  "lr.%I2\t%3, %0\;"
+  "\t%3, %3, %1\;"
+  "sc.%J2\t%3, %3, %0\;"
+  "bnez\t%3, 1b";
+  }
+  [(set_attr "type" "atomic")
+   (set (attr "length") (const_int 16))])
+
+;; AMO fetch ops
+
+(define_expand "atomic_fetch_"
+  [(match_operand:GPR 0 "register_operand") ;; old value at mem
+   (any_atomic:GPR (match_operand:GPR 1 "memory_operand");; mem location
+  (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op
+   (match_operand:SI 3 "const_int_operand")];; model
+  "TARGET_ZAAMO || TARGET_ZALRSC"
+  {
+if (TARGET_ZAAMO)
+  emit_insn (gen_amo_atomic_fetch_ (operands[0], 
operands[1],
+   operands[2], 
operands[3]));
+else
+  emit_insn (gen_lrsc_atomic_fetch_ (operands

[RFC 1/3] RISC-V: Add basic Zaamo and Zalrsc support

[Patrick O'Neill]

There is a proposal to split the A extension into two parts: Zaamo and Zalrsc.
This patch adds basic support by making the A extension imply Zaamo and
Zalrsc.

Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
* config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
* config/riscv/riscv.opt: Add Zaamo and Zalrsc
* config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
TARGET_ZALRSC.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-15.c: Adjust expected arch string.
* gcc.target/riscv/attribute-16.c: Ditto.
* gcc.target/riscv/attribute-17.c: Ditto.
* gcc.target/riscv/attribute-18.c: Ditto.
* gcc.target/riscv/pr110696.c: Ditto.

Signed-off-by: Edwin Lu 
Co-authored-by: Patrick O'Neill 
---
Tested with rv64imafdcv.
---
 gcc/common/config/riscv/riscv-common.cc   | 11 +--
 gcc/config/riscv/arch-canonicalize|  1 +
 gcc/config/riscv/riscv.opt|  6 +++-
 gcc/config/riscv/sync.md  | 30 +--
 gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
 gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
 gcc/testsuite/gcc.target/riscv/pr110696.c |  2 +-
 9 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 631ce8309a0..f5e709ccc95 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -77,6 +77,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"f", "zicsr"},
   {"d", "zicsr"},

+  {"a", "zaamo"},
+  {"a", "zalrsc"},
+
   {"zdinx", "zfinx"},
   {"zfinx", "zicsr"},
   {"zdinx", "zicsr"},
@@ -250,6 +253,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},

   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1501,9 +1506,11 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
   {"zicond",   _options::x_riscv_zi_subext, MASK_ZICOND},

-  {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
+  {"za64rs",  _options::x_riscv_za_subext, MASK_ZA64RS},
   {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
-  {"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
+  {"zawrs",   _options::x_riscv_za_subext, MASK_ZAWRS},
+  {"zaamo",   _options::x_riscv_za_subext, MASK_ZAAMO},
+  {"zalrsc",  _options::x_riscv_za_subext, MASK_ZALRSC},

   {"zba",_options::x_riscv_zb_subext, MASK_ZBA},
   {"zbb",_options::x_riscv_zb_subext, MASK_ZBB},
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 629bed85347..16d2f4118e1 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f", "zicsr"],
+  "a" : ["zaamo", "zalrsc"],
   "f" : ["zicsr"],
   "zdinx" : ["zfinx", "zicsr"],
   "zfinx" : ["zicsr"],
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index f6ff70b2b30..143f68b76da 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -238,7 +238,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext)
 TargetVariable
 int riscv_za_subext

-Mask(ZAWRS) Var(riscv_za_subext)
+Mask(ZAWRS)  Var(riscv_za_subext)
+
+Mask(ZAAMO)  Var(riscv_za_subext)
+
+Mask(ZALRSC) Var(riscv_za_subext)

 Mask(ZA64RS)  Var(riscv_za_subext)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 54bb0a66518..0b4ac914327 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -93,7 +93,7 @@
 (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
   (match_operand:SI 2 "const_int_operand")] ;; model
 UNSPEC_SYNC_OLD_OP))]
-  "TARGET_ATOMIC"
+  "TARGET_ZAAMO"
   "amo.%A2\tzero,%z1,%0"
   [(set_attr "type" "atomic")
(set (attr "length") (const_int 4))])
@@ -107,7 +107,7 @@
 (match_operand:GPR 2 "reg

[Committed] RISC-V: Add require-effective-target to pr113429 testcase

[Patrick O'Neill]

Committed.

Thanks for catching this.
Patrick

On 1/28/24 19:41, juzhe.zh...@rivai.ai wrote:

ok



juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2024-01-27 10:50
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* juzhe.zhong <mailto:juzhe.zh...@rivai.ai>; Patrick O'Neill
<mailto:patr...@rivosinc.com>
*Subject:* [PATCH] RISC-V: Add require-effective-target to
pr113429 testcase
The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64 and riscv_v fixes the issue.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr113429.c: Add
require-effective-target rv64 and riscv_v
    Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc newlib spike.
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
index 05c3eeecb94..a7f5db616d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -1,5 +1,7 @@
/* { dg-do run } */
/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-require-effective-target riscv_v } */
long a;
int b, c, d, e, f, g;
-- 
2.34.1

[PATCH] RISC-V: Add require-effective-target to pr113429 testcase

[Patrick O'Neill]

The pr113429 testcase fails with newlib spike runs. Adding
require-effective-target rv64 and riscv_v fixes the issue.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr113429.c: Add
require-effective-target rv64 and riscv_v

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc newlib spike.
---
 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
index 05c3eeecb94..a7f5db616d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -1,5 +1,7 @@
 /* { dg-do run } */
 /* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-require-effective-target riscv_v } */
 
 long a;
 int b, c, d, e, f, g;
-- 
2.34.1

Re: [Committed] RISC-V: Add regression test for vsetvl bug pr113429

[Patrick O'Neill]

What target/config are these failures on?
I tried rv64gcv, rv64gc, rv32gcv, and rv32gc with RUNTESTFLAGS="rvv.exp" 
and don't see these failures.


Thanks,
Patrick

On 1/25/24 23:20, juzhe.zh...@rivai.ai wrote:

This patch causes the following regression:

FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O0  (test for excess 
errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O1  (test for excess 
errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O2  (test for excess 
errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none  (test for excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects  (test for excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O3 
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
-finline-functions  (test for excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -O3 -g  (test for 
excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/pr113429.c   -Os  (test for excess 
errors)


I suggest you add :

/* { dg-require-effective-target rv64 } */
/* { dg-require-effective-target riscv_v } */


juzhe.zh...@rivai.ai

    *From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2024-01-24 09:20
*To:* juzhe.zh...@rivai.ai; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; law
<mailto:l...@gcc.gnu.org>; rdapp <mailto:rd...@gcc.gnu.org>;
vineetg <mailto:vine...@gcc.gnu.org>
*Subject:* [Committed] RISC-V: Add regression test for vsetvl bug
pr113429

The reduced testcase for pr113429 (cam4 failure) needed additional
modules so it wasn't committed.
The fuzzer found a c testcase that was also fixed with pr113429's fix.
Adding it as a regression test.
PR target/113429
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr113429.c: New test.
Signed-off-by: Patrick O'Neill
---
  .../gcc.target/riscv/rvv/vsetvl/pr113429.c| 70 +++
  1 file changed, 70 insertions(+)
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
new file mode 100644
index 000..05c3eeecb94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+
+long a;
+int b, c, d, e, f, g;
+short h, i, j;
+static int k = 3;
+static int l = 6;
+int m[5][7];
+signed char n;
+int *const o = 
+
+signed char(p)(signed char p1, signed char q) {
+  return p1 / q;
+}
+
+void s(unsigned p1) {
+  b = (b ^ p1) & 255;
+}
+
+static long t() {
+  long u;
+  signed char v;
+  d = 1;
+  for (; d <= 4; d++) {
+j = 0;
+for (; j <= 4; j++) {
+  v = 0;
+  for (; v <= 4; v++) {
+if (m[v][v])
+  continue;
+c = 0;
+for (; c <= 4; c++) {
+  n = 0;
+  for (; n <= 4; n++) {
+int *w = 
+long r = v;
+u = r == 0 ? a : a % r;
+h |= u;
+*w = g;
+--m[n][c];
+f &= *o;
+  }
+}
+if (p((i < 3) ^ 9, k))
+  ;
+else if (v)
+  return 0;
+  }
+}
+  }
+  return 1;
+}
+
+static char x() {
+  for (;;) {
+t();
+if (l)
+  return 0;
+  }
+}
+
+int main() {
+  x();
+  s(e & 255);
+  if (b == 0)
+return 0;
+  else
+return 1;
+}
-- 
2.34.1

[Committed] RISC-V: Don't make Ztso imply A

[Patrick O'Neill]

On 1/24/24 16:20, Palmer Dabbelt wrote:

On Wed, 24 Jan 2024 16:19:06 PST (-0800), jeffreya...@gmail.com wrote:



On 1/24/24 17:07, Patrick O'Neill wrote:

On 12/16/23 10:58, Jeff Law wrote:



On 12/15/23 17:14, Andrew Waterman wrote:
On Fri, Dec 15, 2023 at 1:38 PM Jeff Law  
wrote:




On 12/12/23 20:54, Palmer Dabbelt wrote:
I can't actually find anything in the ISA manual that makes Ztso 
imply

A.  In theory the memory ordering is just a different thing that
the set
of availiable instructions (ie, Ztso without A would still imply
TSO for
loads and stores).  It also seems like a configuration that 
could be

sane to build: without A it's all but impossible to write any
meaningful
multi-core code, and TSO is really cheap for a single core.

That said, I think it's kind of reasonable to provide A to users
asking
for Ztso.  So maybe even if this was a mistake it's the right 
thing to

do?

gcc/ChangeLog:

   * common/config/riscv/riscv-common.cc (riscv_implied_info):
   Remove {"ztso", "a"}.

I'd tend to think step #1 is to determine what the ISA intent is,
meaning engagement with RVI.

We've got time for that engagement and to adjust based on the 
result.

So I'd tend to defer until we know if Ztso should imply A or not.


Palmer is correct.  There is no coupling between Ztso and A. (And
there are uncontrived examples of such systems: e.g. embedded
processors without caches that don't support the LR/SC instructions,
but happen to be TSO.)

Thanks for the confirmation.  Palmer, commit whenever is convenient
for you.

jeff


I was going to commit on behalf of Palmer and saw this was marked as
Deferred in patchworks:
https://patchwork.sourceware.org/project/gcc/patch/20231213035405.2118-1-pal...@rivosinc.com/ 



Is this an old marking from before Andrew confirmed that they are
independent?

Yea, I put into deferred before Andrew chimed in.


OK, so I think we can just commit it?


Committed.

patrick

Re: [PATCH] RISC-V: Don't make Ztso imply A

[Patrick O'Neill]

On 12/16/23 10:58, Jeff Law wrote:



On 12/15/23 17:14, Andrew Waterman wrote:

On Fri, Dec 15, 2023 at 1:38 PM Jeff Law  wrote:




On 12/12/23 20:54, Palmer Dabbelt wrote:

I can't actually find anything in the ISA manual that makes Ztso imply
A.  In theory the memory ordering is just a different thing that 
the set
of availiable instructions (ie, Ztso without A would still imply 
TSO for

loads and stores).  It also seems like a configuration that could be
sane to build: without A it's all but impossible to write any 
meaningful

multi-core code, and TSO is really cheap for a single core.

That said, I think it's kind of reasonable to provide A to users 
asking

for Ztso.  So maybe even if this was a mistake it's the right thing to
do?

gcc/ChangeLog:

   * common/config/riscv/riscv-common.cc (riscv_implied_info):
   Remove {"ztso", "a"}.

I'd tend to think step #1 is to determine what the ISA intent is,
meaning engagement with RVI.

We've got time for that engagement and to adjust based on the result.
So I'd tend to defer until we know if Ztso should imply A or not.


Palmer is correct.  There is no coupling between Ztso and A. (And
there are uncontrived examples of such systems: e.g. embedded
processors without caches that don't support the LR/SC instructions,
but happen to be TSO.)
Thanks for the confirmation.  Palmer, commit whenever is convenient 
for you.


jeff


I was going to commit on behalf of Palmer and saw this was marked as 
Deferred in patchworks:

https://patchwork.sourceware.org/project/gcc/patch/20231213035405.2118-1-pal...@rivosinc.com/

Is this an old marking from before Andrew confirmed that they are 
independent?


Thanks,
Patrick

[Committed] RISC-V: Add regression test for vsetvl bug pr113429

[Patrick O'Neill]

The reduced testcase for pr113429 (cam4 failure) needed additional
modules so it wasn't committed.
The fuzzer found a c testcase that was also fixed with pr113429's fix.
Adding it as a regression test.

PR target/113429

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr113429.c: New test.

Signed-off-by: Patrick O'Neill
---
 .../gcc.target/riscv/rvv/vsetvl/pr113429.c| 70 +++
 1 file changed, 70 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
new file mode 100644
index 000..05c3eeecb94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+
+long a;
+int b, c, d, e, f, g;
+short h, i, j;
+static int k = 3;
+static int l = 6;
+int m[5][7];
+signed char n;
+int *const o = 
+
+signed char(p)(signed char p1, signed char q) {
+  return p1 / q;
+}
+
+void s(unsigned p1) {
+  b = (b ^ p1) & 255;
+}
+
+static long t() {
+  long u;
+  signed char v;
+  d = 1;
+  for (; d <= 4; d++) {
+j = 0;
+for (; j <= 4; j++) {
+  v = 0;
+  for (; v <= 4; v++) {
+if (m[v][v])
+  continue;
+c = 0;
+for (; c <= 4; c++) {
+  n = 0;
+  for (; n <= 4; n++) {
+int *w = 
+long r = v;
+u = r == 0 ? a : a % r;
+h |= u;
+*w = g;
+--m[n][c];
+f &= *o;
+  }
+}
+if (p((i < 3) ^ 9, k))
+  ;
+else if (v)
+  return 0;
+  }
+}
+  }
+  return 1;
+}
+
+static char x() {
+  for (;;) {
+t();
+if (l)
+  return 0;
+  }
+}
+
+int main() {
+  x();
+  s(e & 255);
+  if (b == 0)
+return 0;
+  else
+return 1;
+}
--
2.34.1

[PATCH] RISC-V: Add regression test for vsetvl bug pr113429

[Patrick O'Neill]

The reduced testcase for pr113429 (cam4 failure) needed additional
modules so it wasn't committed.
The fuzzer found a c testcase that was also fixed with pr113429's fix.
Adding it as a regression test.

PR 113429

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr113429.c: New test.

Signed-off-by: Patrick O'Neill 
---
 .../gcc.target/riscv/rvv/vsetvl/pr113429.c| 70 +++
 1 file changed, 70 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
new file mode 100644
index 000..05c3eeecb94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113429.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */
+
+long a;
+int b, c, d, e, f, g;
+short h, i, j;
+static int k = 3;
+static int l = 6;
+int m[5][7];
+signed char n;
+int *const o = 
+
+signed char(p)(signed char p1, signed char q) {
+  return p1 / q;
+}
+
+void s(unsigned p1) {
+  b = (b ^ p1) & 255;
+}
+
+static long t() {
+  long u;
+  signed char v;
+  d = 1;
+  for (; d <= 4; d++) {
+j = 0;
+for (; j <= 4; j++) {
+  v = 0;
+  for (; v <= 4; v++) {
+if (m[v][v])
+  continue;
+c = 0;
+for (; c <= 4; c++) {
+  n = 0;
+  for (; n <= 4; n++) {
+int *w = 
+long r = v;
+u = r == 0 ? a : a % r;
+h |= u;
+*w = g;
+--m[n][c];
+f &= *o;
+  }
+}
+if (p((i < 3) ^ 9, k))
+  ;
+else if (v)
+  return 0;
+  }
+}
+  }
+  return 1;
+}
+
+static char x() {
+  for (;;) {
+t();
+if (l)
+  return 0;
+  }
+}
+
+int main() {
+  x();
+  s(e & 255);
+  if (b == 0)
+return 0;
+  else
+return 1;
+}
-- 
2.34.1

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

[Patrick O'Neill]

On 12/20/23 10:41, Palmer Dabbelt wrote:

On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote:



On 12/20/23 11:21, Palmer Dabbelt wrote:


Yea, the implementation relies largely on just pushing stuff into the
constant pool, so we're largely independent ABI stuff with the likely
exception being relocations.


Ya, but I think we'd only need the relocations if we were going to try
relaxing stuff.  We'd kicked around some ideas there: we could
de-duplicate constant pools or inline smaller constants. That's all way
to complex to try and get into this upcoming binutils release, though
(doubly so with this LEB128 ABI break we're still trying to deal with).

Agreed.  And note that de-duplication is mostly implemented without need
for the target to do anything.  I was kindof amazed to see some of the
places it kicked in on other ports I've worked with.


I think all we'd need from GCC is some way to get the "this load is a 
constant pool address that can be messed with" relocation in there, 
the linker would do all the heavy lifting.  That's probably just a new 
assembler pseudo, so pretty much nothing on the compiler side of things.


In theory (and I did not test this), it should be possible to use 
large

code model codegen in a smaller mode and it should interoperate.  I
seriously pondered doing that as an additional test, then figured I 
had

other higher priority items on my list.


IMO we should test that.  At least the common case of a medlow libc
linked into medany programs should be easy.

+Patrick: let's add some configs to the CI for this?

I was pondering a one-off by turning on the large code model by default,
then doing a bootstrap & regression test in QEMU.  But integrated into
CI is even better.


OK, let's just add it to CI -- it'd be essentially the same testing, 
just it'll stick around.

ACK :)

Patrick




Jeff

[PATCH] RISC-V: Add -fno-vect-cost-model to pr112773 testcase

[Patrick O'Neill]

The testcase for pr112773 started passing after r14-6472-g8501edba91e
which was before the actual fix. This patch adds -fno-vect-cost-model
which prevents the testcase from passing due to the vls change.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/partial/pr112773.c: Add
-fno-vect-cost-model.

Signed-off-by: Patrick O'Neill 
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/pr112773.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/pr112773.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/pr112773.c
index 5f7374b0040..57104c9ebec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/pr112773.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/pr112773.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
+/* { dg-additional-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 
-fno-vect-cost-model" } */
 
 long long a;
 int b, c;
-- 
2.42.0

Re: [Committed] RISC-V: Fix PR112888 ICE

[Patrick O'Neill]

Committed on behalf of Juzhe since he was having internet issues.

Thanks,
Patrick

On 12/6/23 14:35, Juzhe-Zhong wrote:

Committed as it is ovbious.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (extract_single_source): new function.
(pre_vsetvl::compute_lcm_local_properties): Fix ICE.

---
  gcc/config/riscv/riscv-vsetvl.cc | 12 +---
  1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 68f0be7e81d..90477f331d7 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -596,6 +596,14 @@ extract_single_source (set_info *set)
return first_insn;
  }
  
+static insn_info *

+extract_single_source (def_info *def)
+{
+  if (!def)
+return nullptr;
+  return extract_single_source (dyn_cast (def));
+}
+
  static bool
  same_equiv_note_p (set_info *set1, set_info *set2)
  {
@@ -2692,9 +2700,7 @@ pre_vsetvl::compute_lcm_local_properties ()
  def_lookup dl = crtl->ssa->find_def (resource, insn);
  def_info *def
= dl.matching_set_or_last_def_of_prev_group ();
- gcc_assert (def);
- insn_info *def_insn = extract_single_source (
-   dyn_cast (def));
+ insn_info *def_insn = extract_single_source (def);
  if (def_insn && vsetvl_insn_p (def_insn->rtl ()))
{
  vsetvl_info def_info = vsetvl_info (def_insn);

Re: [Committed V2] RISC-V: Fix VSETVL PASS bug

[Patrick O'Neill]

Hi Juzhe,

An assert added in this patch is firing on a testcase on rv64gcv:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112888

Thanks,
Patrick

On 12/6/23 06:26, Juzhe-Zhong wrote:

As PR112855 mentioned, the VSETVL PASS insert vsetvli in unexpected location.

Due to 2 reasons:
1. incorrect transparant computation LCM data. We need to check VL operand defs 
and uses.
2. incorrect fusion of unrelated edge which is the edge never reach the vsetvl 
expression.

PR target/112855

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc 
(pre_vsetvl::compute_lcm_local_properties): Fix transparant LCM data.
(pre_vsetvl::earliest_fuse_vsetvl_info): Disable earliest fusion for 
unrelated edge.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112855.c: New test.

Re: [PATCH] tree-optimization/112827 - corrupt SCEV cache during SCCP

[Patrick O'Neill]

Relevant bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112848

Thanks,
Patrick

On Mon, Dec 4, 2023 at 11:20 PM Li, Pan2  wrote:

> Hi Richard,
>
> It looks like this patch result in one ICE for RISC-V backend for case
> tree-ssa.exp=ssa-sink-16.c, could you please help to double check about it?
> Any more information required please feel free to let me know. Thanks.
>
> compiler error: Segmentation fault
> 0x1903067 crash_signal
> ../../../../gcc/gcc/toplev.cc:316
> 0x111a24e loop_outer(loop const*)
> ../../../../gcc/gcc/cfgloop.h:549
> 0x1ac2143 find_uses_to_rename_use
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:424
> 0x1ac2295 find_uses_to_rename_stmt
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:464
> 0x1ac2456 find_uses_to_rename_bb
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:495
> 0x1ac2585 find_uses_to_rename
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:521
> 0x1ac267c rewrite_into_loop_closed_ssa_1
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:588
> 0x1ac2735 rewrite_into_loop_closed_ssa(bitmap_head*, unsigned int)
> ../../../../gcc/gcc/tree-ssa-loop-manip.cc:628
> 0x19682a3 repair_loop_structures
> ../../../../gcc/gcc/tree-cfgcleanup.cc:1190
> 0x196831d cleanup_tree_cfg(unsigned int)
> ../../../../gcc/gcc/tree-cfgcleanup.cc:1209
> 0x16e654b execute_function_todo
> ../../../../gcc/gcc/passes.cc:2057
> 0x16e534d do_per_function
> ../../../../gcc/gcc/passes.cc:1687
> 0x16e68b0 execute_todo
> ../../../../gcc/gcc/passes.cc:2142
>
> Pan
>
> -Original Message-
> From: Richard Biener 
> Sent: Monday, December 4, 2023 7:54 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] tree-optimization/112827 - corrupt SCEV cache during SCCP
>
> The following avoids corrupting the SCEV cache by my last change
> to propagate constant final values immediately.  The easiest fix
> is to keep a dead initialization around.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
>
> PR tree-optimization/112827
> * tree-scalar-evolution.cc (final_value_replacement_loop):
> Do not release SSA name but keep a dead initialization around.
>
> * gcc.dg/torture/pr112827-1.c: New testcase.
> * gcc.dg/torture/pr112827-2.c: Likewise.
> ---
>  gcc/testsuite/gcc.dg/torture/pr112827-1.c | 14 ++
>  gcc/testsuite/gcc.dg/torture/pr112827-2.c | 18 ++
>  gcc/tree-scalar-evolution.cc  |  9 +++--
>  3 files changed, 35 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.dg/torture/pr112827-1.c
>  create mode 100644 gcc/testsuite/gcc.dg/torture/pr112827-2.c
>
> diff --git a/gcc/testsuite/gcc.dg/torture/pr112827-1.c
> b/gcc/testsuite/gcc.dg/torture/pr112827-1.c
> new file mode 100644
> index 000..6838cbbe62f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/torture/pr112827-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +
> +int a, b, c, d, e;
> +int main() {
> +  for (; c; c++) {
> +for (a = 0; a < 2; a++)
> +  ;
> +for (; b; b++) {
> +  e = d;
> +  d = a;
> +}
> +  }
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.dg/torture/pr112827-2.c
> b/gcc/testsuite/gcc.dg/torture/pr112827-2.c
> new file mode 100644
> index 000..a7a2a70211b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/torture/pr112827-2.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +
> +short a, b[1], f;
> +char c, g;
> +int d, e;
> +int main() {
> +  for (; f; f++) {
> +for (d = 0; d < 2; d++)
> +  ;
> +if (a)
> +  for (g = 0; g < 2; g++)
> +for (c = 0; c < 2; c += b[d+g])
> +  ;
> +for (; e; e++)
> +  ;
> +  }
> +  return 0;
> +}
> diff --git a/gcc/tree-scalar-evolution.cc b/gcc/tree-scalar-evolution.cc
> index 065bcd0743d..7556d89e9f8 100644
> --- a/gcc/tree-scalar-evolution.cc
> +++ b/gcc/tree-scalar-evolution.cc
> @@ -3847,13 +3847,10 @@ final_value_replacement_loop (class loop *loop)
>def = unshare_expr (def);
>remove_phi_node (, false);
>
> -  /* Propagate constants immediately.  */
> +  /* Propagate constants immediately, but leave an unused
> initialization
> +around to avoid invalidating the SCEV cache.  */
>if (CONSTANT_CLASS_P (def))
> -   {
> - replace_uses_by (rslt, def);
> - release_ssa_name (rslt);
> - continue;
> -   }
> +   replace_uses_by (rslt, def);
>
>/* Create the replacement statements.  */
>gimple_seq stmts;
> --
> 2.35.3
>

Re: [PATCH 2/6] c: Turn int-conversion warnings into permerrors

[Patrick O'Neill]

That failure is is due to newlib files:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../*newlib*/newlib/libm/complex/ccoshl.c: 
In function 'ccoshl':


To build gcc w/ glibc with riscv-gnu-toolchain, run make linux.

A temporary fix for newlib is here:
https://github.com/patrick-rivos/riscv-gnu-toolchain/tree/35d8e8c486bd2f6e3e2e673db8d2b979309a6de4/fixups/newlib

On 12/1/23 17:53, 钟居哲 wrote:

No. GLIBC 2.37 also failed:

make[4]: Leaving directory 
'/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/build-newlib/riscv64-unknown-elf/newlib'

  CC       libm/complex/libm_a-casinhl.o
make[3]: *** [Makefile:5283: all] Error 2
make[3]: Leaving directory 
'/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/build-newlib/riscv64-unknown-elf/newlib'

make[2]: *** [Makefile:8492: all-target-newlib] Error 2
make[2]: Leaving directory 
'/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/build-newlib'

make[1]: *** [Makefile:879: all] Error 2
make[1]: Leaving directory 
'/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/build-newlib'

make: *** [Makefile:624: stamps/build-newlib] Error 2
make: *** Waiting for unfinished jobs
  CC       libm/complex/libm_a-csinhl.o
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/ccoshl.c: 
In function 'ccoshl':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/ccoshl.c:43:13: 
error: implicit declaration of function 'coshl'; did you mean 'coshf'? 
[-Wimplicit-function-declaration]

   43 |         w = coshl(x) * cosl(y) + (sinhl(x) * sinl(y)) * I;
      |             ^
      |             coshf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/ccoshl.c:43:24: 
error: implicit declaration of function 'cosl'; did you mean 'cosf'? 
[-Wimplicit-function-declaration]

   43 |         w = coshl(x) * cosl(y) + (sinhl(x) * sinl(y)) * I;
      |                        ^~~~
      |                        cosf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/clogl.c: 
In function 'clogl':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/ccoshl.c:43:35: 
error: implicit declaration of function 'sinhl'; did you mean 'sinhf'? 
[-Wimplicit-function-declaration]

   43 |         w = coshl(x) * cosl(y) + (sinhl(x) * sinl(y)) * I;
      |                                   ^
      |                                   sinhf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/clogl.c:42:13: 
error: implicit declaration of function 'logl'; did you mean 'logf'? 
[-Wimplicit-function-declaration]

   42 |         p = logl(rr);
      |             ^~~~
      |             logf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/ccoshl.c:43:46: 
error: implicit declaration of function 'sinl'; did you mean 'sinf'? 
[-Wimplicit-function-declaration]

   43 |         w = coshl(x) * cosl(y) + (sinhl(x) * sinl(y)) * I;
      |                                              ^~~~
      |                                              sinf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/clogl.c:43:14: 
error: implicit declaration of function 'atan2l'; did you mean 
'atan2f'? [-Wimplicit-function-declaration]

   43 |         rr = atan2l(cimagl(z), creall(z));
      |              ^~
      |              atan2f
  CC       libm/complex/libm_a-csinl.o
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/cexpl.c: 
In function 'cexpl':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/cexpl.c:43:13: 
error: implicit declaration of function 'expl'; did you mean 'expf'? 
[-Wimplicit-function-declaration]

   43 |         r = expl(x);
      |             ^~~~
      |             expf
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-linux-spike-debug/../../newlib/newlib/libm/complex/cexpl.c:44:17: 
error: implicit declaration of function 'cosl'; did you mean 'cosf'? 
[-Wimplicit-function-declaration]

   44 |         w = r * cosl(y) + r * sinl(y) * I;
      |                 ^~~~
      |                 cosf

Re: [PATCH 2/6] c: Turn int-conversion warnings into permerrors

[Patrick O'Neill]

Hi Juzhe,

I can confirm the failure on Newlib.
I'm not seeing any issues on glibc 2.37.
I haven't tried to build musl.

Since this patch promotes warnings to errors breakages were probably 
expected.

The fix may require changes to newlib to remove the errors.
I've hacked together a series of patches on top of newlib 4.3.0 that 
resolves these issues (but I think they'd need more work to be 
upstream-able):

https://github.com/patrick-rivos/riscv-gnu-toolchain/tree/35d8e8c486bd2f6e3e2e673db8d2b979309a6de4/fixups/newlib

@Thomas @Florian am I right in assuming that breakages were expected/the 
fix should come from fixing the warnings?


Thanks,
Patrick

On 12/1/23 16:33, 钟居哲 wrote:

Hi, This patch cause error on building newlib/glibc/musl on RISC-V port:

/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_access.c:8:40: 
error: passing argument 3 of 'syscall_errno' makes integer from 
pointer without a cast [-Wint-conversion]

    8 |   return syscall_errno (SYS_access, 2, file, mode, 0, 0, 0, 0);
      |                                        ^~~~
      |                                        |
      |                                        const char *
In file included from 
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_access.c:2:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/internal_syscall.h:66:38: 
note: expected 'long int' but argument is of type 'const char *'
   66 | syscall_errno(long n, int argc, long _a0, long _a1, long _a2, 
long _a3, long _a4, long _a5)

      |                                 ~^~~
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_utime.c:5:39: 
warning: 'struct utimbuf' declared inside parameter list will not be 
visible outside of this definition or declaration

    5 | _utime(const char *path, const struct utimbuf *times)
      |                                       ^~~
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_faccessat.c: 
In function '_faccessat':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_faccessat.c:7:50: 
error: passing argument 4 of 'syscall_errno' makes integer from 
pointer without a cast [-Wint-conversion]
    7 |   return syscall_errno (SYS_faccessat, 4, dirfd, file, mode, 
flags, 0, 0);

      | ^~~~
      |                                                  |
      | const char *
In file included from 
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_faccessat.c:2:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/internal_syscall.h:66:48: 
note: expected 'long int' but argument is of type 'const char *'
   66 | syscall_errno(long n, int argc, long _a0, long _a1, long _a2, 
long _a3, long _a4, long _a5)

      |                                           ~^~~
make[5]: *** [Makefile:3315: riscv/riscv_libgloss_a-sys_access.o] Error 1
make[5]: *** Waiting for unfinished jobs
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_open.c: 
In function '_open':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_open.c:8:38: 
error: passing argument 3 of 'syscall_errno' makes integer from 
pointer without a cast [-Wint-conversion]

    8 |   return syscall_errno (SYS_open, 3, name, flags, mode, 0, 0, 0);
      |                                      ^~~~
      |                                      |
      |                                      const char *
In file included from 
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_open.c:2:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/internal_syscall.h:66:38: 
note: expected 'long int' but argument is of type 'const char *'
   66 | syscall_errno(long n, int argc, long _a0, long _a1, long _a2, 
long _a3, long _a4, long _a5)

      |                                 ~^~~
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_openat.c: 
In function '_openat':
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_openat.c:7:47: 
error: passing argument 4 of 'syscall_errno' makes integer 

Re: [PATCH v1 1/1] RISC-V: Initial RV64E and LP64E support

[Patrick O'Neill]

Hi Tsukasa,

I'm seeing a new regression across all tested riscv targets:
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/224

Regression:

|FAIL: gcc.target/riscv/predef-13.c -O0 (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -O1 (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -O2 (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -O2 -flto -fno-use-linker-plugin 
-flto-partition=none (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -O2 -flto -fuse-linker-plugin 
-fno-fat-lto-objects (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -O3 -g (test for excess errors) FAIL: 
gcc.target/riscv/predef-13.c -Os (test for excess errors)|


Debug log:

Executing on host: 
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
 
-B/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
  
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-13.c
  -march=rv32gc -mabi=ilp32d -mcmodel=medlow   -fdiagnostics-plain-output
-O0  -march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2 -S   -o 
predef-13.s(timeout = 600)
spawn -ignore SIGHUP 
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
 
-B/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
 
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-13.c
 -march=rv32gc -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O0 
-march=rv32e -mabi=ilp32e -mcmodel=medlow -misa-spec=2.2 -S -o predef-13.s
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-13.c:
 In function 'main':
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-13.c:23:2:
 error: #error "__riscv_e"
compiler exited with status 1
FAIL: gcc.target/riscv/predef-13.c   -O0  (test for excess errors)
Excess errors:
/home/runner/work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-13.c:23:2:
 error: #error "__riscv_e"

I bisected it locally to commit 006e90e13441c3716b40616282b200a0ef689376 
(this patch):



./bin/riscv64-unknown-linux-gnu-gcc -march=rv32e -mabi=ilp32e -S 
../gcc/gcc/testsuite/gcc.target/riscv/predef-13.c

../gcc/gcc/testsuite/gcc.target/riscv/predef-13.c: In function 'main':
../gcc/gcc/testsuite/gcc.target/riscv/predef-13.c:23:2: error: #error 
"__riscv_e"
   23 | #error "__riscv_e"
  |  ^

Let me know if you need any additional info/investigation from me.

Thanks,
Patrick

On 11/24/23 02:18, Tsukasa OI wrote:

From: Tsukasa OI

Along with RV32E, RV64E is ratified.  Though ILP32E and LP64E ABIs are
still draft, it's worth supporting it.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_ext_version_table): Set version to ratified 2.0.
(riscv_subset_list::parse_std_ext): Allow RV64E.
* config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'.
* config/riscv/arch-canonicalize: Parse base ISA 'rv64e'.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Define different macro per XLEN.  Add handling for ABI_LP64E.
* config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi):
Add handling for ABI_LP64E.
* config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E.
* config/riscv/riscv.cc (riscv_option_override): Enhance error
handling to support RV64E and LP64E.
(riscv_conditional_register_usage): Change "RV32E" in a comment
to "RV32E/RV64E".
* config/riscv/riscv.h
(UNITS_PER_FP_ARG): Add handling for ABI_LP64E.
(STACK_BOUNDARY): Ditto.
(ABI_STACK_BOUNDARY): Ditto.
(MAX_ARGS_IN_REGISTERS): Ditto.
(ABI_SPEC): Add support for "lp64e".
* config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E.
* doc/invoke.texi: Add documentation of the LP64E ABI.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-1.c: Test for __riscv_64e.
* gcc.target/riscv/predef-2.c: Ditto.
* gcc.target/riscv/predef-3.c: Ditto.
* gcc.target/riscv/predef-4.c: Ditto.
* gcc.target/riscv/predef-5.c: Ditto.
* gcc.target/riscv/predef-6.c: Ditto.
* gcc.target/riscv/predef-7.c: Ditto.
* gcc.target/riscv/predef-8.c: Ditto.
* gcc.target/riscv/predef-9.c: New test for RV64E and LP64E,
based on predef-7.c.
---

Re: [RFC PATCH] RISC-V: Remove f{r,s}flags builtins

[Patrick O'Neill]

Hi Christoph,

The precommit-ci is seeing a large number of ICE segmentation faults as 
a result of this patch:

https://github.com/ewlu/gcc-precommit-ci/issues/796#issuecomment-1831853523

The failures aren't in riscv.exp testsuite files so that's likely why 
you didn't run into them in your testing.


Debug log:

/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.dg/c11-atomic-2.c:110:3:
 internal compiler error: Segmentation fault
0x133afb3 crash_signal
../../../gcc/gcc/toplev.cc:316
0x1678d1f contains_struct_check(tree_node*, tree_node_structure_enum, char 
const*, int, char const*)
../../../gcc/gcc/tree.h:3747
0x1678d1f build_call_expr_loc_array(unsigned int, tree_node*, int, tree_node**)
../../../gcc/gcc/tree.cc:10815
0x1679043 build_call_expr(tree_node*, int, ...)
../../../gcc/gcc/tree.cc:10865
0x17f816e riscv_atomic_assign_expand_fenv(tree_node**, tree_node**, tree_node**)
../../../gcc/gcc/config/riscv/riscv-builtins.cc:420
0xc5209b build_atomic_assign
../../../gcc/gcc/c/c-typeck.cc:4289
0xc60a47 build_modify_expr(unsigned int, tree_node*, tree_node*, tree_code, 
unsigned int, tree_node*, tree_node*)
../../../gcc/gcc/c/c-typeck.cc:6406
0xc85a61 c_parser_expr_no_commas
../../../gcc/gcc/c/c-parser.cc:9112
0xc85db1 c_parser_expression
../../../gcc/gcc/c/c-parser.cc:12725
0xc862bb c_parser_expression_conv
../../../gcc/gcc/c/c-parser.cc:12765
0xca3607 c_parser_statement_after_labels
../../../gcc/gcc/c/c-parser.cc:7755
0xc9f27e c_parser_compound_statement_nostart
../../../gcc/gcc/c/c-parser.cc:7242
0xc9f804 c_parser_compound_statement
../../../gcc/gcc/c/c-parser.cc:6527
0xca359c c_parser_statement_after_labels
../../../gcc/gcc/c/c-parser.cc:7590
0xca5713 c_parser_statement
../../../gcc/gcc/c/c-parser.cc:7561
0xca5713 c_parser_c99_block_statement
../../../gcc/gcc/c/c-parser.cc:7820
0xca6a2c c_parser_do_statement
../../../gcc/gcc/c/c-parser.cc:8194
0xca3d51 c_parser_statement_after_labels
../../../gcc/gcc/c/c-parser.cc:7605
0xc9f27e c_parser_compound_statement_nostart
../../../gcc/gcc/c/c-parser.cc:7242
0xc9f804 c_parser_compound_statement
../../../gcc/gcc/c/c-parser.cc:6527
Please submit a full bug report, with preprocessed source (by using 
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.
compiler exited with status 1
FAIL: gcc.dg/c11-atomic-2.c (internal compiler error: Segmentation fault)

Let me know if you need any additional info/investigation from me.

Thanks,
Patrick

On 11/29/23 03:49, Christoph Muellner wrote:

From: Christoph Müllner

We have two builtins which are undocumented and have no known users.
Further, they don't exist in LLVM (so are no portable).
This means they are in an unclear state of being supported or not.
Let's remove them get them out of this undecided state.

A discussion about making these builtins available in all
compilers was held many years ago with the decision to
not document them in the RISC-V C API documentation:
   https://github.com/riscv-non-isa/riscv-c-api-doc/pull/3

This is an RFC patch as this breaks existing code that uses
these builtins, even if we don't know if such code exists.

An alternative to this patch would be to document them
in gcc/doc/extend.texi (like has been done with __builtin_riscv_pause)
and put them into a supported state.

This patch removes two tests for these builtins.
A test of this patch did not trigger any regressions in riscv.exp.

Signed-off-by: Christoph Müllner

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc: Remove the builtins
__builtin_riscv_frflags and __builtin_riscv_fsflags.

gcc/testsuite/ChangeLog:

* g++.target/riscv/frflags.C: Removed.
* gcc.target/riscv/fsflags.c: Removed.
---
  gcc/config/riscv/riscv-builtins.cc   |  2 --
  gcc/testsuite/g++.target/riscv/frflags.C |  7 ---
  gcc/testsuite/gcc.target/riscv/fsflags.c | 16 
  3 files changed, 25 deletions(-)
  delete mode 100644 gcc/testsuite/g++.target/riscv/frflags.C
  delete mode 100644 gcc/testsuite/gcc.target/riscv/fsflags.c

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..1655492b246 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -188,8 +188,6 @@ static const struct riscv_builtin_description 
riscv_builtins[] = {
#include "riscv-scalar-crypto.def"
#include "corev.def"
  
-  DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),

-  DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
RISCV_BUILTIN (pause, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE, hint_pause),
  };
  
diff --git a/gcc/testsuite/g++.target/riscv/frflags.C b/gcc/testsuite/g++.target/riscv/frflags.C

deleted file mode 100644

[Committed] gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-check-1.F90 on non-vector targets

[Patrick O'Neill]

On 11/18/23 20:09, Jeff Law wrote:



On 11/15/23 17:03, Patrick O'Neill wrote:

Ping.

Testsuite fixup similar to:
https://inbox.sourceware.org/gcc-patches/974e9e5e-8f07-46dd-b9b9-db8aa4685...@gmail.com/T/#t 

https://inbox.sourceware.org/gcc-patches/7e78cd70-70c9-41b1-8a98-6977a1034...@rivosinc.com/T/#t 


OK.


Jeff


Committed.

Patrick

[PING] [PATCH] gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-check-1.F90 on non-vector targets

[Patrick O'Neill]

Ping.

Testsuite fixup similar to:
https://inbox.sourceware.org/gcc-patches/974e9e5e-8f07-46dd-b9b9-db8aa4685...@gmail.com/T/#t
https://inbox.sourceware.org/gcc-patches/7e78cd70-70c9-41b1-8a98-6977a1034...@rivosinc.com/T/#t

Patrick

On Thu, Nov 2, 2023 at 12:09 PM Patrick O'Neill  
wrote:


Testcases in gfortran.dg/vect/vect.exp rely on
check_vect_support_and_set_flags to set dg-do-what-default and avoid
running vector tests on non-vector targets. The three testcases in this
patch overwrite the default with dg-do run which causes issues
for non-vector targets.

Removing the dg-do run directive resolves this issue for non-vector
targets (while still running the tests on vector targets).

gcc/testsuite/ChangeLog:

* gfortran.dg/vect/pr107254.f90: Remove dg-do run directive.
* gfortran.dg/vect/pr85853.f90: Ditto.
* gfortran.dg/vect/vect-alias-check-1.F90: Ditto.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc & rv64gcv to make sure the testcases compile/run
as expected.

These files haven't been changed in a long time so I'm not sure why (or
if) this hasn't been run into by other people before.
---
 gcc/testsuite/gfortran.dg/vect/pr107254.f90   | 2 --
 gcc/testsuite/gfortran.dg/vect/pr85853.f90| 1 -
 gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90 | 1 -
 3 files changed, 4 deletions(-)

diff --git a/gcc/testsuite/gfortran.dg/vect/pr107254.f90 
b/gcc/testsuite/gfortran.dg/vect/pr107254.f90
index 85bcb5f3fa2..adce6bedc30 100644
--- a/gcc/testsuite/gfortran.dg/vect/pr107254.f90
+++ b/gcc/testsuite/gfortran.dg/vect/pr107254.f90
@@ -1,5 +1,3 @@
-! { dg-do run }
-
 subroutine dlartg( f, g, s, r )
   implicit none
   double precision :: f, g, r, s
diff --git a/gcc/testsuite/gfortran.dg/vect/pr85853.f90 
b/gcc/testsuite/gfortran.dg/vect/pr85853.f90
index 68f4a004324..4c0e3b81a09 100644
--- a/gcc/testsuite/gfortran.dg/vect/pr85853.f90
+++ b/gcc/testsuite/gfortran.dg/vect/pr85853.f90
@@ -1,5 +1,4 @@
 ! Taken from execute/where_2.f90, but with special flags.
-! { dg-do run }
 ! { dg-additional-options "-fno-tree-loop-vectorize" }

 ! Program to test the WHERE constructs
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90 
b/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
index 3014ff9f3b6..85ae9b151e3 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
@@ -1,4 +1,3 @@
-! { dg-do run }
 ! { dg-additional-options "-fno-inline" }

 #define N 200
--
2.34.1

Re: [PATCH] RISC-V: Fix ICE in non-canonical march parsing

[Patrick O'Neill]

Does relax mean no longer enforcing the canonical order of extensions?

Patrick

On 11/14/23 17:52, Kito Cheng wrote:


LGTM, and BTW...I am thinking we could relax the canonical order
during parsing, did you have interesting and time working on that
item?

On Wed, Nov 15, 2023 at 9:35 AM Patrick O'Neill  wrote:

Passing in a base extension in non-canonical order (i, e, g) causes GCC
to ICE:
xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e'
xgcc: internal compiler error: in add, at 
common/config/riscv/riscv-common.cc:671
...

This is fixed by skipping to the next extension when a non-canonical
order is detected.

gcc/ChangeLog:

 * common/config/riscv/riscv-common.cc
 (riscv_subset_list::parse_std_ext): Emit an error and skip to
 the next extension when a non-canonical ordering is detected.

[Committed] RISC-V: Fix ICE in non-canonical march parsing

[Patrick O'Neill]

Updated testcase names and committed.

Thanks,
Patrick

---

Passing in a base extension in non-canonical order (i, e, g) causes GCC
to ICE:
xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e'
xgcc: internal compiler error: in add, at 
common/config/riscv/riscv-common.cc:671
...

This is fixed by skipping to the next extension when a non-canonical
order is detected.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse_std_ext): Emit an error and skip to
the next extension when a non-canonical ordering is detected.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-27.c: New test.
* gcc.target/riscv/arch-28.c: New test.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc glibc on QEMU.
---
 gcc/common/config/riscv/riscv-common.cc  | 17 +
 gcc/testsuite/gcc.target/riscv/arch-27.c |  7 +++
 gcc/testsuite/gcc.target/riscv/arch-28.c |  7 +++
 3 files changed, 27 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-27.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-28.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..57fe856063e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1017,15 +1017,24 @@ riscv_subset_list::parse_std_ext (const char *p)
   std_ext = *p;
 
   /* Checking canonical order.  */
+  const char *prior_std_exts = std_exts;
+
   while (*std_exts && std_ext != *std_exts)
std_exts++;
 
   subset[0] = std_ext;
   if (std_ext != *std_exts && standard_extensions_p (subset))
-   error_at (m_loc,
- "%<-march=%s%>: ISA string is not in canonical order. "
- "%<%c%>",
- m_arch, *p);
+   {
+ error_at (m_loc,
+   "%<-march=%s%>: ISA string is not in canonical order. "
+   "%<%c%>",
+   m_arch, *p);
+ /* Extension ordering is invalid.  Ignore this extension and keep
+searching for other issues with remaining extensions.  */
+ std_exts = prior_std_exts;
+ p++;
+ continue;
+   }
 
   std_exts++;
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-27.c 
b/gcc/testsuite/gcc.target/riscv/arch-27.c
new file mode 100644
index 000..70143b2156f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-27.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64ge -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-error "ISA string is not in canonical order. 'e'" "" { target *-*-* } 
0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-28.c 
b/gcc/testsuite/gcc.target/riscv/arch-28.c
new file mode 100644
index 000..934399a7b3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-28.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imaefcv -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-error "ISA string is not in canonical order. 'e'" "" { target *-*-* } 
0 } */
-- 
2.34.1

[PATCH] RISC-V: Fix ICE in non-canonical march parsing

[Patrick O'Neill]

Passing in a base extension in non-canonical order (i, e, g) causes GCC
to ICE:
xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e'
xgcc: internal compiler error: in add, at 
common/config/riscv/riscv-common.cc:671
...

This is fixed by skipping to the next extension when a non-canonical
order is detected.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse_std_ext): Emit an error and skip to
the next extension when a non-canonical ordering is detected.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-27.c: New test.
* gcc.target/riscv/arch-28.c: New test.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc glibc on QEMU.
---
 gcc/common/config/riscv/riscv-common.cc  | 17 +
 gcc/testsuite/gcc.target/riscv/arch-24.c |  7 +++
 gcc/testsuite/gcc.target/riscv/arch-25.c |  7 +++
 3 files changed, 27 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-25.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 884d81c12aa..66aea71ea2c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -964,15 +964,24 @@ riscv_subset_list::parse_std_ext (const char *p)
   std_ext = *p;
 
   /* Checking canonical order.  */
+  const char *prior_std_exts = std_exts;
+
   while (*std_exts && std_ext != *std_exts)
std_exts++;
 
   subset[0] = std_ext;
   if (std_ext != *std_exts && standard_extensions_p (subset))
-   error_at (m_loc,
- "%<-march=%s%>: ISA string is not in canonical order. "
- "%<%c%>",
- m_arch, *p);
+   {
+ error_at (m_loc,
+   "%<-march=%s%>: ISA string is not in canonical order. "
+   "%<%c%>",
+   m_arch, *p);
+ /* Extension ordering is invalid.  Ignore this extension and keep
+searching for other issues with remaining extensions.  */
+ std_exts = prior_std_exts;
+ p++;
+ continue;
+   }
 
   std_exts++;
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-24.c 
b/gcc/testsuite/gcc.target/riscv/arch-24.c
new file mode 100644
index 000..70143b2156f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-24.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64ge -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-error "ISA string is not in canonical order. 'e'" "" { target *-*-* } 
0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c 
b/gcc/testsuite/gcc.target/riscv/arch-25.c
new file mode 100644
index 000..934399a7b3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-25.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imaefcv -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-error "ISA string is not in canonical order. 'e'" "" { target *-*-* } 
0 } */
-- 
2.34.1

Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Patrick O'Neill]

Hi Mary,

GCC tip-of-tree with this patch series applied fails to build glibc with:
--with-arch=rv32imac --with-abi=ilp32
--with-arch=rv32imafdc --with-abi=ilp32d

Failing command:
./bin/riscv32-unknown-elf-gcc 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/ 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/targ-include 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/newlib/libc/include 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/riscv32 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/libnosys 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/libgloss/riscv32 
-DPACKAGE_NAME=\"newlib\" -DPACKAGE_TARNAME=\"newlib\" 
-DPACKAGE_VERSION=\"4.1.0\" -DPACKAGE_STRING=\"newlib\ 4.1.0\" 
-DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -I. 
-I/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time 
-fno-builtin -DHAVE_NANOSLEEP  -O2 -D_POSIX_MODE -ffunction-sections 
-fdata-sections    -mcmodel=medlow -c -o lib_a-mktime.o `test -f 
'mktime.c' || echo 
'/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/'`mktime.c

during RTL pass: combine
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c: 
In function 'validate_structure':
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c:148:1: 
internal compiler error: Segmentation fault

  148 | }
  | ^
0x1276843 crash_signal
    ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
    ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
    ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
    ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
    ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
    ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
    ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
    ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source (by using 
-freport-bug).

Please include the complete backtrace with any bug report.
See  for instructions.

Creduced testcase:
./bin/riscv32-unknown-elf-gcc -O1 mktime.c -freport-bug
int a, b;
void c() { a = b % 7; }

during RTL pass: combine
mktime.c: In function 'c':
mktime.c:2:23: internal compiler error: Segmentation fault
    2 | void c() { a = b % 7; }
  |   ^
0x1276843 crash_signal
    ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
    ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
    ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
    ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
    ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
    ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
    ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
    ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See  for instructions.
Preprocessed source stored into /tmp/ccJL816S.out file, please attach 
this to your bugreport.


I've attached the -freport-bug output to this email.

Thanks,
Patrick

glibc: a704fd9a133bfb10510e18702f48a6a9c88dbbd5
gcc base hash: 2020bce38cf2e02cbd1097faa8f1fd6586364a7e

On 11/13/23 05:35, Mary Bennett wrote:

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
   Mary Bennett 
   Nandni Jamnadas 
   Pietra Ferreira 
   Charlie Keaney
   Jessica Mills
   Craig Blackmore 
   Simon Cook 
   Jeremy Bennett 
   Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
  patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
  gcc/common/config/riscv/riscv-common.cc   |  2 +
  gcc/config/riscv/constraints.md   |  6 +++
  

Re: [PATCH v3] libiberty: Use posix_spawn in pex-unix when available.

[Patrick O'Neill]

On 11/10/23 03:00, Prathamesh Kulkarni wrote:


On Thu, 5 Oct 2023 at 00:00, Brendan Shanks  wrote:

Hi,

This patch implements pex_unix_exec_child using posix_spawn when
available.

This should especially benefit recent macOS (where vfork just calls
fork), but should have equivalent or faster performance on all
platforms.
In addition, the implementation is substantially simpler than the
vfork+exec code path.

Tested on x86_64-linux.

Hi Brendan,
It seems this patch caused the following regressions on aarch64:


I'm also seeing the same failures on risc-v targets bisected to this commit.

Thanks,
Patrick



FAIL: g++.dg/modules/bad-mapper-1.C -std=c++17  at line 3 (test for
errors, line )
FAIL: g++.dg/modules/bad-mapper-1.C -std=c++17 (test for excess errors)
FAIL: g++.dg/modules/bad-mapper-1.C -std=c++2a  at line 3 (test for
errors, line )
FAIL: g++.dg/modules/bad-mapper-1.C -std=c++2a (test for excess errors)
FAIL: g++.dg/modules/bad-mapper-1.C -std=c++2b  at line 3 (test for
errors, line )
FAIL: g++.dg/modules/bad-mapper-1.C -std=c++2b (test for excess errors)

Looking at g++.log:
/home/tcwg-buildslave/workspace/tcwg_gnu_2/abe/snapshots/gcc.git~master/gcc/testsuite/g++.dg/modules/bad-mapper-1.C:
error: failed posix_spawnp mapper 'this-will-not-work'
In module imported at
/home/tcwg-buildslave/workspace/tcwg_gnu_2/abe/snapshots/gcc.git~master/gcc/testsuite/g++.dg/modules/bad-mapper-1.C:2:1:
unique1.bob: error: failed to read compiled module: No such file or directory
unique1.bob: note: compiled module file is 'gcm.cache/unique1.bob.gcm'
unique1.bob: note: imports must be built before being imported
unique1.bob: fatal error: returning to the gate for a mechanical issue
compilation terminated.

Link to log files:
https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/1159/artifact/artifacts/00-sumfiles/
Could you please investigate ?

Thanks,
Prathamesh

v2: Fix error handling (previously the function would be run twice in
case of error), and don't use a macro that changes control flow.

v3: Match file style for error-handling blocks, don't close
in/out/errdes on error, and check close() for errors.

libiberty/
 * configure.ac (AC_CHECK_HEADERS): Add spawn.h.
 (checkfuncs): Add posix_spawn, posix_spawnp.
 (AC_CHECK_FUNCS): Add posix_spawn, posix_spawnp.
 * configure, config.in: Rebuild.
 * pex-unix.c [HAVE_POSIX_SPAWN] (pex_unix_exec_child): New function.

Signed-off-by: Brendan Shanks
---
  libiberty/configure.ac |   8 +-
  libiberty/pex-unix.c   | 168 +
  2 files changed, 173 insertions(+), 3 deletions(-)

diff --git a/libiberty/configure.ac b/libiberty/configure.ac
index 0748c592704..2488b031bc8 100644
--- a/libiberty/configure.ac
+++ b/libiberty/configure.ac
@@ -289,7 +289,7 @@ AC_SUBST_FILE(host_makefile_frag)
  # It's OK to check for header files.  Although the compiler may not be
  # able to link anything, it had better be able to at least compile
  # something.
-AC_CHECK_HEADERS(sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h 
unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h 
fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h 
sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h 
sys/prctl.h)
+AC_CHECK_HEADERS(sys/file.h sys/param.h limits.h stdlib.h malloc.h string.h 
unistd.h strings.h sys/time.h time.h sys/resource.h sys/stat.h sys/mman.h 
fcntl.h alloca.h sys/pstat.h sys/sysmp.h sys/sysinfo.h machine/hal_sysinfo.h 
sys/table.h sys/sysctl.h sys/systemcfg.h stdint.h stdio_ext.h process.h 
sys/prctl.h spawn.h)
  AC_HEADER_SYS_WAIT
  AC_HEADER_TIME

@@ -412,7 +412,8 @@ funcs="$funcs setproctitle"
  vars="sys_errlist sys_nerr sys_siglist"

  checkfuncs="__fsetlocking canonicalize_file_name dup3 getrlimit getrusage \
- getsysinfo gettimeofday on_exit pipe2 psignal pstat_getdynamic 
pstat_getstatic \
+ getsysinfo gettimeofday on_exit pipe2 posix_spawn posix_spawnp psignal \
+ pstat_getdynamic pstat_getstatic \
   realpath setrlimit spawnve spawnvpe strerror strsignal sysconf sysctl \
   sysmp table times wait3 wait4"

@@ -435,7 +436,8 @@ if test "x" = "y"; then
  index insque \
  memchr memcmp memcpy memmem memmove memset mkstemps \
  on_exit \
-pipe2 psignal pstat_getdynamic pstat_getstatic putenv \
+pipe2 posix_spawn posix_spawnp psignal \
+pstat_getdynamic pstat_getstatic putenv \
  random realpath rename rindex \
  sbrk setenv setproctitle setrlimit sigsetmask snprintf spawnve spawnvpe \
   stpcpy stpncpy strcasecmp strchr strdup \
diff --git a/libiberty/pex-unix.c b/libiberty/pex-unix.c
index 33b5bce31c2..336799d1125 100644
--- a/libiberty/pex-unix.c
+++ b/libiberty/pex-unix.c
@@ -58,6 +58,9 @@ extern int errno;
  #ifdef HAVE_PROCESS_H
  #include 
  #endif
+#ifdef HAVE_SPAWN_H
+#include 
+#endif

  #ifdef vfork /* Autoconf may define this to fork for us. */
  # define VFORK_STRING "fork"
@@ 

[Committed] g++: Rely on dg-do-what-default to avoid running pr102788.cc on non-vector targets

[Patrick O'Neill]

On 11/9/23 17:20, Jeff Law wrote:



On 11/2/23 17:45, Patrick O'Neill wrote:

Testcases in g++.dg/vect rely on check_vect_support_and_set_flags
to set dg-do-what-default and avoid running vector tests on non-vector
targets. The three testcases in this patch overwrite the default with
dg-do run.

Removing the dg-do run directive resolves this issue for non-vector
targets (while still running the tests on vector targets).

gcc/testsuite/ChangeLog:

* g++.dg/vect/pr102788.cc: Remove dg-do run directive.
OK.  I'll note your patch has just one file patched, but your comment 
indicates three testcases have this problem.  Did you forget to 
include a couple changes?


If so, those are pre-approved as well.  Just post them for the 
archiver and commit.


Thanks,
jeff

Committed

The comment was mistakenly copy/pasted from 
https://inbox.sourceware.org/gcc-patches/20231102190911.66763-1-patr...@rivosinc.com/T/#u

Revised commit message to only mention the one testcase.

Thanks,
Patrick

Re: [PATCH] g++: Add require-effective-target to multi-input file testcase pr95401.cc

[Patrick O'Neill]

On 11/9/23 17:34, Jeff Law wrote:



On 11/3/23 00:18, Patrick O'Neill wrote:

On non-vector targets dejagnu attempts dg-do compile for pr95401.cc.
This produces a command like this:
g++ pr95401.cc pr95401a.cc -S -o pr95401.s

which isn't valid (gcc does not accept multiple input files when using
-S with -o).

This patch adds require-effective-target vect_int to avoid the case
where the testcase is invoked with dg-do compile.

gcc/testsuite/ChangeLog:

* g++.dg/vect/pr95401.cc: Add require-effective-target vect_int.
Sorry, I must be missing something here.  I fail to see how adding an 
effective target check would/should impact the problem you've 
described above with the dg-additional-sources interaction with -S.


It's not intuitive (& probably not the cleanest way of solving it).

pr95401.cc is an invalid testcase when run with dg-do compile (for the 
reasons above).


pr95401.cc 
<https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/g%2B%2B.dg/vect/pr95401.cc;h=6a56dab095722b01d912416352df17f0d91dfd27;hb=HEAD> 
does not define a dg-do, which means it uses the testcase uses 
dg-do-what-default 
<https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/g%2B%2B.dg/vect/vect.exp;h=fc77120a83173c65ad147e8bb7c29ac82f06bb6d;hb=HEAD#l30> 
to determine what to do.
dg-do-what-default is set by target-supports.exp 
<https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/testsuite/lib/target-supports.exp;h=1a7bea96c1e4ccb8ef30ac7012c04e8d44c5ad01;hb=HEAD#l11532>.


The two options here are set dg-do-what-default run or compile.
On non-vector targets the pr95401 is set to compile (which is invalid).

Ideally we would say if dg-do-what-default == compile don't run, but 
AFAIK that isn't possible.
I didn't want to duplicate the check_vect_support_and_set_flags logic to 
return true/false since that'll probably get out of sync.


I used require-effective-target vect_int as a proxy for 
check_vect_support_and_set_flags (also since the testcase only contains 
integer arrays).


That way we do this now:
dg-do-what-default run -> run
dg-do-what-default compile -> skip test

If there's a cleaner/better approach I'm happy to revise.

Patrick



Jeff

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

[Patrick O'Neill]

Thanks for pointing this out Juzhe, we're investigating how the CI got 
confused here. We'll let you know what we find out.


Patrick


On 11/7/23 14:48, 钟居哲 wrote:

Plz note those FAILs are not caused by this patch.
They are caused by this commit:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c42741ad95af3a1e3ac07350da4c3a94865ed63

It seems that precommit CI faild to locate the real root cause.


juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-11-08 03:21
*To:* pan2.li <mailto:pan2...@intel.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
*CC:* juzhe.zhong <mailto:juzhe.zh...@rivai.ai>; yanzhang.wang
<mailto:yanzhang.w...@intel.com>; kito.cheng
<mailto:kito.ch...@gmail.com>
*Subject:* Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff
size autovec

Ah sorry for the noise - I just saw that this was resolved with a
subsequent patch:

Precommit run:
https://github.com/ewlu/gcc-precommit-ci/issues/608#issuecomment-1798058721

Patrick

    On 11/7/23 11:17, Patrick O'Neill wrote:

Hi Pan,
This patch (9acea4376fd98696ba51e59f417c94911a4d8248) 
causes|||cond_widen_reduc-2.c to start failing on: linux/newlib: rv32/64gc 
||linux/newlib: ||rv32gcv ||linux/newlib: ||rv32/64gc|_zba_zbb_zbc_zbs|||FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2 FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 Debug log
output: spawn -ignore SIGHUP

/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc

-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/

/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow
-fdiagnostics-plain-output -ftree-vectorize -O2 --param
riscv-autovec-lmul=dynamic -march=rv64gcv_zvfh_zvl128b
-mabi=lp64d --param riscv-autovec-preference=scalable --param
riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math
-ffat-lto-objects -fno-ident -S -o cond_widen_reduc-2.s PASS:
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c (test for
excess errors)
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c:
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c:
\\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c:
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
scan-assembler-times
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 Executing on
host:

/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc

-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/

/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow
-fdiagnostics-plain-output -ftree-vectorize -O2 --param
riscv-autovec-lmul=dynamic --param
riscv-autovec-preference=fixed-vlmax --param
riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math -lm -o
./cond_widen_reduc_run-1.exe (timeout = 600) These failures are
still on trunk (b7d05f13e86bf49bfb78c9876deba388efc6082e).
Thanks, Patrick Postcommit CI bisection:
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/130 |
On 11/5/23 01:30,pan2...@intel.com  wrote:

From: Pan Li
This patch would like to support the FP below API auto vectorization
with different type size
+-+---+--+
| API | RV64  | RV32 |
+-+---+--+
| irint   | DF => SI  | DF => SI |
| irintf  | - | -

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

[Patrick O'Neill]

Ah sorry for the noise - I just saw that this was resolved with a 
subsequent patch:


Precommit run: 
https://github.com/ewlu/gcc-precommit-ci/issues/608#issuecomment-1798058721


Patrick

On 11/7/23 11:17, Patrick O'Neill wrote:

Hi Pan,

This patch (9acea4376fd98696ba51e59f417c94911a4d8248) causes|||cond_widen_reduc-2.c to start failing on: linux/newlib: rv32/64gc ||linux/newlib: ||rv32gcv ||linux/newlib: ||rv32/64gc|_zba_zbb_zbc_zbs|||FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times 
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2 FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
3 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times 
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 Debug log output: 
spawn -ignore SIGHUP 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output 
-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic 
-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param 
riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 
-fno-vect-cost-model -ffast-math -ffat-lto-objects -fno-ident -S -o 
cond_widen_reduc-2.s PASS: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c (test for 
excess errors) gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times 
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times 
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 2 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
3 gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times 
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 Executing on 
host: 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c 
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output 
-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic --param 
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 
-fno-vect-cost-model -ffast-math -lm -o ./cond_widen_reduc_run-1.exe 
(timeout = 600) These failures are still on trunk 
(b7d05f13e86bf49bfb78c9876deba388efc6082e). Thanks, Patrick Postcommit 
CI bisection: 
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/130 |

On 11/5/23 01:30,pan2...@intel.com  wrote:

From: Pan Li

This patch would like to support the FP below API auto vectorization
with different type size

+-+---+--+
| API | RV64  | RV32 |
+-+---+--+
| irint   | DF => SI  | DF => SI |
| irintf  | - | -|
| lrint   | - | DF => SI |
| lrintf  | SF => DI  | -|
| llrint  | - | -|
| llrintf | SF => DI  | SF => DI |
+-+---+--+

Given below code:
void
test_lrintf (long *out, float *in, unsigned count)
{
   for (unsigned i = 0; i < count; i++)
 out[i] = __builtin_lrintf (in[i]);
}

Before this patch:
test_lrintf:
   beq a2,zero,.L8
   sllia5,a2,32
   srlia2,a5,30
   add a4,a1,a2
.L3:
   flw fa5,0(a1)
   addia1,a1,4
   addia0,a0,8
   fcvt.l.s a5,fa5,dyn
   sd  a5,-8(a0)
   bne a1,a4,.L3

After this patch:
test_lrintf:
   beq a2,zero,.L8
   sllia2,a2,32
   srlia2,a2,32
.L3:
   vsetvli a5,a2,e32,mf2,ta,ma
   vle32.v v2,0(a1)
   sllia3,a5,2
   sllia4,a5,3
   vfwcvt.x.f.vv1,v2
   sub a2,a2,a5
   vse64.v v1,0(a0)
   add a1,a1,a3
   add a0,a0,a4
   bne a2,zero,.L3

Unfortunately, the HF mode is not include due to it requires
additional middle-end support from internal-fun.def.

gcc/ChangeLog:

* config/riscv/autovec.md: Remove the size check of lrint.
* config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): 

Re: [PATCH v1] RISC-V: Support FP rint to i/l/ll diff size autovec

[Patrick O'Neill]

Hi Pan,

This patch (9acea4376fd98696ba51e59f417c94911a4d8248) causes|||cond_widen_reduc-2.c to start failing on: linux/newlib: rv32/64gc ||linux/newlib: ||rv32gcv ||linux/newlib: ||rv32/64gc|_zba_zbb_zbc_zbs|||FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
2 FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
3 Debug log output: spawn -ignore SIGHUP 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output 
-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic 
-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param 
riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 
-fno-vect-cost-model -ffast-math -ffat-lto-objects -fno-ident -S -o 
cond_widen_reduc-2.s PASS: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c (test for excess 
errors) gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvfwredusum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
2 gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsum\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 3 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: 
\\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t found 0 times FAIL: 
gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c 
scan-assembler-times \\tvwredsumu\\.vs\\tv[0-9]+,v[0-9]+,v[0-9]+,v0\\.t 
3 Executing on host: 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c 
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output 
-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic --param 
riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 
-fno-vect-cost-model -ffast-math -lm -o ./cond_widen_reduc_run-1.exe 
(timeout = 600) These failures are still on trunk 
(b7d05f13e86bf49bfb78c9876deba388efc6082e). Thanks, Patrick Postcommit 
CI bisection: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/130 |


On 11/5/23 01:30,pan2...@intel.com  wrote:


From: Pan Li

This patch would like to support the FP below API auto vectorization
with different type size

+-+---+--+
| API | RV64  | RV32 |
+-+---+--+
| irint   | DF => SI  | DF => SI |
| irintf  | - | -|
| lrint   | - | DF => SI |
| lrintf  | SF => DI  | -|
| llrint  | - | -|
| llrintf | SF => DI  | SF => DI |
+-+---+--+

Given below code:
void
test_lrintf (long *out, float *in, unsigned count)
{
   for (unsigned i = 0; i < count; i++)
 out[i] = __builtin_lrintf (in[i]);
}

Before this patch:
test_lrintf:
   beq a2,zero,.L8
   sllia5,a2,32
   srlia2,a5,30
   add a4,a1,a2
.L3:
   flw fa5,0(a1)
   addia1,a1,4
   addia0,a0,8
   fcvt.l.s a5,fa5,dyn
   sd  a5,-8(a0)
   bne a1,a4,.L3

After this patch:
test_lrintf:
   beq a2,zero,.L8
   sllia2,a2,32
   srlia2,a2,32
.L3:
   vsetvli a5,a2,e32,mf2,ta,ma
   vle32.v v2,0(a1)
   sllia3,a5,2
   sllia4,a5,3
   vfwcvt.x.f.vv1,v2
   sub a2,a2,a5
   vse64.v v1,0(a0)
   add a1,a1,a3
   add a0,a0,a4
   bne a2,zero,.L3

Unfortunately, the HF mode is not include due to it requires
additional middle-end support from internal-fun.def.

gcc/ChangeLog:

* config/riscv/autovec.md: Remove the size check of lrint.
* config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
emit func impl.
(emit_vec_widden_cvt_x_f): New help emit func impl.
(emit_vec_rounding_to_integer): New func impl to emit the
rounding from FP to integer.
(expand_vec_lrint): Leverage 

[PATCH] g++: Add require-effective-target to multi-input file testcase pr95401.cc

[Patrick O'Neill]

On non-vector targets dejagnu attempts dg-do compile for pr95401.cc.
This produces a command like this:
g++ pr95401.cc pr95401a.cc -S -o pr95401.s

which isn't valid (gcc does not accept multiple input files when using
-S with -o).

This patch adds require-effective-target vect_int to avoid the case
where the testcase is invoked with dg-do compile.

gcc/testsuite/ChangeLog:

* g++.dg/vect/pr95401.cc: Add require-effective-target vect_int.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc & rv64gcv to make sure the testcase runs/doesn't
compile as expected.

Somewhat related/similar problem (running vector test on non-vector
target):
https://inbox.sourceware.org/gcc-patches/20231102190911.66763-1-patr...@rivosinc.com/T/#u
https://inbox.sourceware.org/gcc-patches/20231102234527.77231-1-patr...@rivosinc.com/T/#u

Ideally we would have a way to ban a dejagnu dg-do or an equivalent to
check_vect_support_and_set_flags that returns true/false based on
if it emits run/compile as the default dg-do command.
require-effective-target seems to be a reasonable alternative.
pr95401.cc and pr95401a.cc only use int variables and arrays.
---
 gcc/testsuite/g++.dg/vect/pr95401.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/vect/pr95401.cc 
b/gcc/testsuite/g++.dg/vect/pr95401.cc
index 6a56dab0957..6a1b65ff0e7 100644
--- a/gcc/testsuite/g++.dg/vect/pr95401.cc
+++ b/gcc/testsuite/g++.dg/vect/pr95401.cc
@@ -1,5 +1,6 @@
 // { dg-additional-options "-mavx2 -O3" { target avx2_runtime } }
 // { dg-additional-sources pr95401a.cc }
+// { dg-require-effective-target vect_int }
 
 extern int var_9;
 extern unsigned var_14;
-- 
2.34.1

[PATCH] g++: Rely on dg-do-what-default to avoid running pr102788.cc on non-vector targets

[Patrick O'Neill]

Testcases in g++.dg/vect rely on check_vect_support_and_set_flags
to set dg-do-what-default and avoid running vector tests on non-vector
targets. The three testcases in this patch overwrite the default with
dg-do run.

Removing the dg-do run directive resolves this issue for non-vector
targets (while still running the tests on vector targets).

gcc/testsuite/ChangeLog:

* g++.dg/vect/pr102788.cc: Remove dg-do run directive.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc & rv64gcv to make sure the testcases compile/run
as expected.

Similar to 
https://inbox.sourceware.org/gcc-patches/20231102190911.66763-1-patr...@rivosinc.com/T/#u
---
 gcc/testsuite/g++.dg/vect/pr102788.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/vect/pr102788.cc 
b/gcc/testsuite/g++.dg/vect/pr102788.cc
index fa9c366fe56..032fa29fc72 100644
--- a/gcc/testsuite/g++.dg/vect/pr102788.cc
+++ b/gcc/testsuite/g++.dg/vect/pr102788.cc
@@ -1,4 +1,3 @@
-// { dg-do run }
 // { dg-additional-options "-O3" }

 unsigned long long int var_4 = 235;
--
2.34.1

Re: [PATCH v1] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator

[Patrick O'Neill]

Hi Pan,

This patch is causing new failures (ICEs) on trunk:
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/110

Pre-commit CI run:
https://github.com/ewlu/gcc-precommit-ci/issues/553#issuecomment-1790688172

New rv32gcv failures:

|FAIL: gcc.dg/vect/fast-math-bb-slp-call-2.c (internal compiler error: 
in expand_vec_lrint, at config/riscv/riscv-v.cc:4134) FAIL: 
gcc.dg/vect/fast-math-bb-slp-call-2.c (test for excess errors) FAIL: 
gcc.dg/vect/fast-math-vect-call-2.c (internal compiler error: in 
expand_vec_lrint, at config/riscv/riscv-v.cc:4134) FAIL: 
gcc.dg/vect/fast-math-vect-call-2.c (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O0 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O0 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O1 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O1 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O2 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O2 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O3 -g (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O3 -g (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -Os (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -Os (test for excess errors) |


New rv64gcv failures:

|FAIL: gfortran.dg/pr32533.f90 -O0 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O0 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O1 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O1 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O2 (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O2 (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -O3 -g (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -O3 -g (test for excess errors) FAIL: 
gfortran.dg/pr32533.f90 -Os (internal compiler error: in 
expand_vec_lround, at config/riscv/riscv-v.cc:4144) FAIL: 
gfortran.dg/pr32533.f90 -Os (test for excess errors)|


Please let me know if you need any additional information.

Thanks,
Patrick

On 11/2/23 05:13, Li, Pan2 wrote:


Committed, thanks Juzhe.

Pan

*From:*juzhe.zhong 
*Sent:* Thursday, November 2, 2023 8:04 PM
*To:* Li, Pan2 
*Cc:* gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, 
Yanzhang ; kito.ch...@gmail.com
*Subject:* Re: [PATCH v1] RISC-V: Refactor prefix [I/L/LL] rounding 
API autovec iterator


lgtm

 Replied Message 

From



pan2...@intel.com 

Date



11/02/2023 19:48

To



gcc-patches@gcc.gnu.org 



Cc



juzhe.zh...@rivai.ai ,
pan2...@intel.com ,
yanzhang.w...@intel.com 
,

kito.ch...@gmail.com 

Subject



[PATCH v1] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator

[PATCH] gfortran: Rely on dg-do-what-default to avoid running pr85853.f90, pr107254.f90 and vect-alias-check-1.F90 on non-vector targets

[Patrick O'Neill]

Testcases in gfortran.dg/vect/vect.exp rely on
check_vect_support_and_set_flags to set dg-do-what-default and avoid
running vector tests on non-vector targets. The three testcases in this
patch overwrite the default with dg-do run which causes issues
for non-vector targets.

Removing the dg-do run directive resolves this issue for non-vector
targets (while still running the tests on vector targets).

gcc/testsuite/ChangeLog:

* gfortran.dg/vect/pr107254.f90: Remove dg-do run directive.
* gfortran.dg/vect/pr85853.f90: Ditto.
* gfortran.dg/vect/vect-alias-check-1.F90: Ditto.

Signed-off-by: Patrick O'Neill 
---
Tested using rv64gc & rv64gcv to make sure the testcases compile/run
as expected.

These files haven't been changed in a long time so I'm not sure why (or
if) this hasn't been run into by other people before.
---
 gcc/testsuite/gfortran.dg/vect/pr107254.f90   | 2 --
 gcc/testsuite/gfortran.dg/vect/pr85853.f90| 1 -
 gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90 | 1 -
 3 files changed, 4 deletions(-)

diff --git a/gcc/testsuite/gfortran.dg/vect/pr107254.f90 
b/gcc/testsuite/gfortran.dg/vect/pr107254.f90
index 85bcb5f3fa2..adce6bedc30 100644
--- a/gcc/testsuite/gfortran.dg/vect/pr107254.f90
+++ b/gcc/testsuite/gfortran.dg/vect/pr107254.f90
@@ -1,5 +1,3 @@
-! { dg-do run }
-
 subroutine dlartg( f, g, s, r )
   implicit none
   double precision :: f, g, r, s
diff --git a/gcc/testsuite/gfortran.dg/vect/pr85853.f90 
b/gcc/testsuite/gfortran.dg/vect/pr85853.f90
index 68f4a004324..4c0e3b81a09 100644
--- a/gcc/testsuite/gfortran.dg/vect/pr85853.f90
+++ b/gcc/testsuite/gfortran.dg/vect/pr85853.f90
@@ -1,5 +1,4 @@
 ! Taken from execute/where_2.f90, but with special flags.
-! { dg-do run }
 ! { dg-additional-options "-fno-tree-loop-vectorize" }
 
 ! Program to test the WHERE constructs
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90 
b/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
index 3014ff9f3b6..85ae9b151e3 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-alias-check-1.F90
@@ -1,4 +1,3 @@
-! { dg-do run }
 ! { dg-additional-options "-fno-inline" }
 
 #define N 200
-- 
2.34.1

[Committed] RISC-V: Use riscv_subword_address for atomic_test_and_set

[Patrick O'Neill]

On 11/1/23 12:00, Jeff Law wrote:



On 11/1/23 10:14, Patrick O'Neill wrote:

Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subword_address.

gcc/ChangeLog:

* config/riscv/sync.md:  Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.
OK.  No strong opinions on the extraneous move at -O0.  It does make a 
tiny bit of work for the optimizers, but I doubt it matters in practice.


Your call if you want to fix that as a follow-up or not.

jeff

Committed.

I think I'll leave it as-is since IMO sync.md is more readable when 
those statements are broken up.
If someone finds issue with it in the future we can easily apply the 
diff from the patch.


Thanks,
Patrick

[Committed] RISC-V: Enable ztso tests on rv32

[Patrick O'Neill]

On 11/1/23 12:03, Jeff Law wrote:



On 10/31/23 17:25, Patrick O'Neill wrote:
This patch transitions the ztso testcases to use the testsuite 
infrastructure,

enabling the tests on both rv64 and rv32 targets.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso 
extension to

dg-options for dg-do compile.
 * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
 * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
 * lib/target-supports.exp: Add testing infrastructure to 
require the

Ztso extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill 
---
Before committing v1, I ran the full testsuite as a sanity check and 
found
failures that don't happen when running the testcases individually. 
v2 fixes

those failures using common-sense fixes.
OK for the trunk.  Thanks for doing the deeper testing and addressing 
the issues that showed up.


Committed.

Thanks,
Patrick

Re: [PATCH] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

[Patrick O'Neill]

On 11/1/23 12:19, Vineet Gupta wrote:



On 11/1/23 12:11, Jeff Law wrote:



On 10/31/23 12:35, Vineet Gupta wrote:

riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.

The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't work, but stepping thru the
debugger shows old code didn't and fixed does.

This showed up when testing Ajit's REE ABI extension series which 
probes
the ABI (using a NULL tree type) and ends up hitting the libcall 
code path.


[Usual caveat, I'll wait for Pre-commit CI to run the tests and report]

gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_promote_function_mode): Fix mode
  returned for libcall case.
Macro that change their arguments are evil ;(   I think Juzhe's patch 
in this space a few months back wasn't supposed to change behavior.


Oh, its a regression. I can add a Fixes: tag



OK once CI finishes without regressions.


Thx,
-Vineet


It passes precommit CI without any new failures:
https://github.com/ewlu/gcc-precommit-ci/issues/526#issuecomment-1787891174

Tested-by: Patrick O'Neill 

Thanks,
Patrick

[PATCH v2] RISC-V: Use riscv_subword_address for atomic_test_and_set

[Patrick O'Neill]

Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subword_address.

gcc/ChangeLog:

* config/riscv/sync.md:  Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.

Signed-off-by: Patrick O'Neill 
---
Changelog:
v2: Comment out the diff in the foreword so git doesn't get confused
when applying the patch
---
Tested using r14-5040-g5dc2ba333f8.

This patch causes this codegen to regress (adds a mv) but *only* on -O0.

extern void abort();

short x;

int main()
{
  if ( __atomic_test_and_set(, __ATOMIC_SEQ_CST))
abort();
}

Baseline:

main:
addisp,sp,-16
sd  ra,8(sp)
sd  s0,0(sp)
addis0,sp,16
lui a5,%hi(x)
addia5,a5,%lo(x)
andia4,a5,-4
andia5,a5,3
li  a3,1
slliw   a5,a5,3
sllwa2,a3,a5
amoor.w.aqrla3,a2,0(a4)
srlwa5,a3,a5
andia5,a5,0xff
beq a5,zero,.L2
callabort
.L2:
li  a5,0
mv  a0,a5
ld  ra,8(sp)
ld  s0,0(sp)
addisp,sp,16
jr  ra

After patch there is an additional mv:

main:
addisp,sp,-16
sd  ra,8(sp)
sd  s0,0(sp)
addis0,sp,16
lui a5,%hi(x)
addia5,a5,%lo(x)
andia3,a5,-4
andia5,a5,3
slliw   a5,a5,3
li  a4,1
sllwa2,a4,a5
amoor.w.aqrla4,a2,0(a3)
srawa4,a4,a5
>   mv  a5,a4
andia5,a5,0xff
beq a5,zero,.L2
callabort
.L2:
li  a5,0
mv  a0,a5
ld  ra,8(sp)
ld  s0,0(sp)
addisp,sp,16
jr  ra

This can be fixed using:
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index ad4751febd2..a9539977321 100644
> --- a/gcc/config/riscv/sync.md
> +++ b/gcc/config/riscv/sync.md
> @@ -530,10 +530,9 @@

>emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));

> -  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
> -gen_lowpart (QImode, shift)));
> -
> -  emit_move_insn (operands[0], gen_lowpart (QImode, old));
> +  emit_move_insn (gen_lowpart (SImode, operands[0]),
> + gen_rtx_ASHIFTRT (SImode, old,
> +   gen_lowpart (QImode, shift)));

>DONE;
>  })

But I think it hurts read/grokability of the .md sequence. If it's worth
changing for -O0 generated sequences, let me know and I'll send a follow
up patch.
---
 gcc/config/riscv/sync.md | 41 +---
 1 file changed, 17 insertions(+), 24 deletions(-)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6ff3493b5ce..ad4751febd2 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -504,43 +504,36 @@
(set (attr "length") (const_int 28))])

 (define_expand "atomic_test_and_set"
-  [(match_operand:QI 0 "register_operand" "") ;; bool output
+  [(match_operand:QI 0 "register_operand" "");; bool output
(match_operand:QI 1 "memory_operand" "+A");; memory
-   (match_operand:SI 2 "const_int_operand" "")]   ;; model
+   (match_operand:SI 2 "const_int_operand" "")]  ;; model
   "TARGET_ATOMIC"
 {
   /* We have no QImode atomics, so use the address LSBs to form a mask,
  then use an aligned SImode atomic.  */
-  rtx result = operands[0];
+  rtx old = gen_reg_rtx (SImode);
   rtx mem = operands[1];
   rtx model = operands[2];
-  rtx addr = force_reg (Pmode, XEXP (mem, 0));
-
-  rtx aligned_addr = gen_reg_rtx (Pmode);
-  emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));
+  rtx set = gen_reg_rtx (QImode);
+  rtx aligned_mem = gen_reg_rtx (SImode);
+  rtx shift = gen_reg_rtx (SImode);

-  rtx aligned_mem = change_address (mem, SImode, aligned_addr);
-  set_mem_alias_set (aligned_mem, 0);
+  /* Unused.  */
+  rtx _mask = gen_reg_rtx (SImode);
+  rtx _not_mask = gen_reg_rtx (SImode);

-  rtx offset = gen_reg_rtx (SImode);
-  emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
-  GEN_INT (3)));
+  riscv_subword_address (mem, _mem, , &_mask, &_not_mask);

-  rtx tmp = gen_reg_rtx (SImode);
-  emit_move_insn (tmp, GEN_INT (1));
+  emit_move_insn (set, GEN_INT (1));
+  rtx shifted_set = gen_reg_rtx (SImode);
+  riscv_lshift_subword (QImode, set, shift, _set);

-  rtx shmt = gen_reg_rtx (SImode);
-  emit_move_insn (shmt, gen_rtx_ASHIFT (SImode, off

Re: [PATCH] RISC-V: Support strided load/store

[Patrick O'Neill]

Hi Juzhe,

The pre-commit CI is seeing these new failures after applying this patch 
[1]:


|FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_load-1.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 132 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_store-1.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 66 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/mask_strided_store-1.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_STORE" 66 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 66 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-3.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_LOAD" 55 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_STORE" 66 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_STORE" 44 FAIL: 
gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_STORE" 55 |


Example debug log:
|
Executing on host: 
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
-march=rv32gc_zba_zbb_zbc_zbs -mabi=ilp32d -mcmodel=medlow 
-fdiagnostics-plain-output   -march=rv64gcv_zvfh -mabi=lp64d -O3 --param 
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math 
-fdump-tree-optimized-details -S   -o strided_store-3.s    (timeout = 600)
spawn -ignore SIGHUP 
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc 
-B/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ 
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
-march=rv32gc_zba_zbb_zbc_zbs -mabi=ilp32d -mcmodel=medlow 
-fdiagnostics-plain-output -march=rv64gcv_zvfh -mabi=lp64d -O3 --param 
riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math 
-fdump-tree-optimized-details -S -o strided_store-3.s
PASS: gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
(test for excess errors)
gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c: pattern 
found 0 times
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
scan-tree-dump-times optimized " .MASK_LEN_STRIDED_STORE" 55
PASS: gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
scan-tree-dump-not optimized " .SCATTER_STORE"
PASS: gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-3.c 
scan-tree-dump-not optimized " .MASK_SCATTER_STORE"|


If these failures are due to the missing middle-end bits then feel free 
to ignore :-)


Thanks,
Patrick

[1]: 
https://github.com/ewlu/gcc-precommit-ci/issues/524#issuecomment-1787004837


On 10/31/23 13:26, Robin Dapp wrote:

Hi Juzhe,

LGTM once the middle-end parts are in.  Just tiny nits.
Nothing that would warrant a V2, though.


+;; =
+;; == Stried Load/Store

missing a 'd' here.
  

+(define_predicate "vector_stride_extension_operand"
+  (ior (and (match_operand 0 "immediate_operand")
+(match_test "Pmode == DImode"))
+   (and (match_operand 0 "const_0_operand")
+(match_test "Pmode == SImode"
+

This could use a comment why we allow only sign extension
for 32 bit.  Also the linter complains about spaces vs tabs.

Regards
  Robin

[PATCH] RISC-V: Use riscv_subword_address for atomic_test_and_set

[Patrick O'Neill]

Other subword atomic patterns use riscv_subword_address to calculate
the aligned address, shift amount, mask and !mask. atomic_test_and_set
was implemented before the common function was added. After this patch
all subword atomic patterns use riscv_subword_address.

gcc/ChangeLog:

* config/riscv/sync.md:  Use riscv_subword_address function to
calculate the address and shift in atomic_test_and_set.

Signed-off-by: Patrick O'Neill 
---
Tested using r14-5040-g5dc2ba333f8.

This patch causes this codegen to regress (adds a mv) but *only* on -O0.

extern void abort();

short x;

int main()
{
  if ( __atomic_test_and_set(, __ATOMIC_SEQ_CST))
abort();
}

Baseline:

main:
addisp,sp,-16
sd  ra,8(sp)
sd  s0,0(sp)
addis0,sp,16
lui a5,%hi(x)
addia5,a5,%lo(x)
andia4,a5,-4
andia5,a5,3
li  a3,1
slliw   a5,a5,3
sllwa2,a3,a5
amoor.w.aqrla3,a2,0(a4)
srlwa5,a3,a5
andia5,a5,0xff
beq a5,zero,.L2
callabort
.L2:
li  a5,0
mv  a0,a5
ld  ra,8(sp)
ld  s0,0(sp)
addisp,sp,16
jr  ra

After patch there is an additional mv:

main:
addisp,sp,-16
sd  ra,8(sp)
sd  s0,0(sp)
addis0,sp,16
lui a5,%hi(x)
addia5,a5,%lo(x)
andia3,a5,-4
andia5,a5,3
slliw   a5,a5,3
li  a4,1
sllwa2,a4,a5
amoor.w.aqrla4,a2,0(a3)
srawa4,a4,a5
>   mv  a5,a4
andia5,a5,0xff
beq a5,zero,.L2
callabort
.L2:
li  a5,0
mv  a0,a5
ld  ra,8(sp)
ld  s0,0(sp)
addisp,sp,16
jr  ra

This can be fixed using:
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index ad4751febd2..a9539977321 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -530,10 +530,9 @@

   emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));

-  emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
-gen_lowpart (QImode, shift)));
-
-  emit_move_insn (operands[0], gen_lowpart (QImode, old));
+  emit_move_insn (gen_lowpart (SImode, operands[0]),
+ gen_rtx_ASHIFTRT (SImode, old,
+   gen_lowpart (QImode, shift)));

   DONE;
 })

But I think it hurts read/grokability of the .md sequence. If it's worth
changing for -O0 generated sequences, let me know and I'll send a follow
up patch.
---
 gcc/config/riscv/sync.md | 41 +---
 1 file changed, 17 insertions(+), 24 deletions(-)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6ff3493b5ce..ad4751febd2 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -504,43 +504,36 @@
(set (attr "length") (const_int 28))])

 (define_expand "atomic_test_and_set"
-  [(match_operand:QI 0 "register_operand" "") ;; bool output
+  [(match_operand:QI 0 "register_operand" "");; bool output
(match_operand:QI 1 "memory_operand" "+A");; memory
-   (match_operand:SI 2 "const_int_operand" "")]   ;; model
+   (match_operand:SI 2 "const_int_operand" "")]  ;; model
   "TARGET_ATOMIC"
 {
   /* We have no QImode atomics, so use the address LSBs to form a mask,
  then use an aligned SImode atomic.  */
-  rtx result = operands[0];
+  rtx old = gen_reg_rtx (SImode);
   rtx mem = operands[1];
   rtx model = operands[2];
-  rtx addr = force_reg (Pmode, XEXP (mem, 0));
-
-  rtx aligned_addr = gen_reg_rtx (Pmode);
-  emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));
+  rtx set = gen_reg_rtx (QImode);
+  rtx aligned_mem = gen_reg_rtx (SImode);
+  rtx shift = gen_reg_rtx (SImode);

-  rtx aligned_mem = change_address (mem, SImode, aligned_addr);
-  set_mem_alias_set (aligned_mem, 0);
+  /* Unused.  */
+  rtx _mask = gen_reg_rtx (SImode);
+  rtx _not_mask = gen_reg_rtx (SImode);

-  rtx offset = gen_reg_rtx (SImode);
-  emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
-  GEN_INT (3)));
+  riscv_subword_address (mem, _mem, , &_mask, &_not_mask);

-  rtx tmp = gen_reg_rtx (SImode);
-  emit_move_insn (tmp, GEN_INT (1));
+  emit_move_insn (set, GEN_INT (1));
+  rtx shifted_set = gen_reg_rtx (SImode);
+  riscv_lshift_subword (QImode, set, shift, _set);

-  rtx shmt = gen_reg_rtx (SImode);
-  emit_move_insn (shmt, gen_rtx_ASHIFT (SImode, offset, GEN_INT (3)));
+  emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));

-  rtx word = gen_reg_rtx (SImode);
-  emit_move_insn (word, gen_rtx_ASH

[PATCH v2] RISC-V: Enable ztso tests on rv32

[Patrick O'Neill]

This patch transitions the ztso testcases to use the testsuite infrastructure,
enabling the tests on both rv64 and rv32 targets.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the
Ztso extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill 
---
Before committing v1, I ran the full testsuite as a sanity check and found
failures that don't happen when running the testcases individually. v2 fixes
those failures using common-sense fixes.

Changelog:
v1 -> v2:
target-supports.exp
 - Fix typo `riscv_ext_a` -> `riscv_ext_ztso`
 - Add ztso to `check_effective_target_riscv_zvfh_ok`
---
 .../riscv/amo-table-ztso-amo-add-1.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-2.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-3.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-4.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-5.c  |  3 ++-
 .../riscv/amo-table-ztso-compare-exchange-1.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-2.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-3.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-4.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-5.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-6.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-7.c |  2 +-
 .../gcc.target/riscv/amo-table-ztso-fence-1.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-2.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-3.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-4.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-5.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-1.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-2.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-3.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-1.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-2.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-3.c |  3 ++-
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |  2 +-
 gcc/testsuite/lib/target-supports.exp | 25 ++-
 29 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index a88d08eb3f4..65a4351025d 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-am

[Committed 2/2] RISC-V: Require a extension for testcases with atomic insns

[Patrick O'Neill]

On 10/31/23 06:07, Jeff Law wrote:



On 10/30/23 18:49, Patrick O'Neill wrote:
Add testsuite infrastructure for the A extension and use it to 
require the A
extension for dg-do run and add the add extension for non-A dg-do 
compile.


gcc/testsuite/ChangeLog:

 * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A 
extension to

dg-options for dg-do compile.
 * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
 * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
 * gcc.target/riscv/inline-atomics-2.c: Ditto.
 * gcc.target/riscv/inline-atomics-3.c: Require A extension 
for dg-do

run.
 * gcc.target/riscv/inline-atomics-4.c: Ditto.
 * gcc.target/riscv/inline-atomics-5.c: Ditto.
 * gcc.target/riscv/inline-atomics-6.c: Ditto.
 * gcc.target/riscv/inline-atomics-7.c: Ditto.
 * gcc.target/riscv/inline-atomics-8.c: Ditto.
 * lib/target-supports.exp: Add testing infrastructure to 
require the A

extension or add it to an existing -march.

OK
jeff

Committed

Patrick

[Committed 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

[Patrick O'Neill]

On 10/31/23 06:05, Jeff Law wrote:



On 10/30/23 18:49, Patrick O'Neill wrote:
Non-atomic targets are currently prevented from using the optimized 
fencing for

seq_cst load/seq_cst store. This patch removes that constraint.

gcc/ChangeLog:

* config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove
TARGET_ATOMIC constraint
(atomic_store_rvwmo): Ditto.
* config/riscv/sync-ztso.md (atomic_load_ztso): Ditto.
(atomic_store_ztso): Ditto.
* config/riscv/sync.md (atomic_load): Ditto.
(atomic_store): Ditto.

OK
jeff

Committed

Patrick

[PATCH 2/2] RISC-V: Require a extension for testcases with atomic insns

[Patrick O'Neill]

Add testsuite infrastructure for the A extension and use it to require the A
extension for dg-do run and add the add extension for non-A dg-do compile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Add A extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/inline-atomics-2.c: Ditto.
* gcc.target/riscv/inline-atomics-3.c: Require A extension for dg-do
run.
* gcc.target/riscv/inline-atomics-4.c: Ditto.
* gcc.target/riscv/inline-atomics-5.c: Ditto.
* gcc.target/riscv/inline-atomics-6.c: Ditto.
* gcc.target/riscv/inline-atomics-7.c: Ditto.
* gcc.target/riscv/inline-atomics-8.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the A
extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill 
---
This patch relies on the previous one in the series. If applied seperately,
amo-table-a-6-store-compat-3.c and amo-table-a-6-load-3.c must be updated to
require the A extension as those testcases check for the optimized fences.
---
 .../riscv/amo-table-a-6-amo-add-1.c   |  1 +
 .../riscv/amo-table-a-6-amo-add-2.c   |  1 +
 .../riscv/amo-table-a-6-amo-add-3.c   |  1 +
 .../riscv/amo-table-a-6-amo-add-4.c   |  1 +
 .../riscv/amo-table-a-6-amo-add-5.c   |  1 +
 .../riscv/amo-table-a-6-compare-exchange-1.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-2.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-3.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-4.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-5.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-6.c  |  1 +
 .../riscv/amo-table-a-6-compare-exchange-7.c  |  1 +
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |  1 +
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |  1 +
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |  1 +
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |  1 +
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |  1 +
 .../gcc.target/riscv/inline-atomics-2.c   |  3 ++-
 .../gcc.target/riscv/inline-atomics-3.c   |  2 +-
 .../gcc.target/riscv/inline-atomics-4.c   |  2 +-
 .../gcc.target/riscv/inline-atomics-5.c   |  2 +-
 .../gcc.target/riscv/inline-atomics-6.c   |  2 +-
 .../gcc.target/riscv/inline-atomics-7.c   |  2 +-
 .../gcc.target/riscv/inline-atomics-8.c   |  2 +-
 gcc/testsuite/lib/target-supports.exp | 23 +++
 25 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
index 071a33928fe..8ab1a02b40c 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
index d6b2d91db2a..a5a841abdcd 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c 
b/gcc/testsuite/gcc.target/risc

[PATCH 1/2] RISC-V: Let non-atomic targets use optimized amo loads/stores

[Patrick O'Neill]

Non-atomic targets are currently prevented from using the optimized fencing for
seq_cst load/seq_cst store. This patch removes that constraint.

gcc/ChangeLog:

* config/riscv/sync-rvwmo.md (atomic_load_rvwmo): Remove
TARGET_ATOMIC constraint
(atomic_store_rvwmo): Ditto.
* config/riscv/sync-ztso.md (atomic_load_ztso): Ditto.
(atomic_store_ztso): Ditto.
* config/riscv/sync.md (atomic_load): Ditto.
(atomic_store): Ditto.

Signed-off-by: Patrick O'Neill 
---
 gcc/config/riscv/sync-rvwmo.md | 4 ++--
 gcc/config/riscv/sync-ztso.md  | 4 ++--
 gcc/config/riscv/sync.md   | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index cb641ea9ec3..c35eae15334 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -52,7 +52,7 @@
[(match_operand:GPR 1 "memory_operand" "A")
 (match_operand:SI 2 "const_int_operand")]  ;; model
 UNSPEC_ATOMIC_LOAD))]
-  "TARGET_ATOMIC && !TARGET_ZTSO"
+  "!TARGET_ZTSO"
   {
 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 model = memmodel_base (model);
@@ -78,7 +78,7 @@
[(match_operand:GPR 1 "reg_or_0_operand" "rJ")
 (match_operand:SI 2 "const_int_operand")]  ;; model
 UNSPEC_ATOMIC_STORE))]
-  "TARGET_ATOMIC && !TARGET_ZTSO"
+  "!TARGET_ZTSO"
   {
 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 7bb15b7ab8c..6fdfa912a2c 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -46,7 +46,7 @@
[(match_operand:GPR 1 "memory_operand" "A")
 (match_operand:SI 2 "const_int_operand")]  ;; model
 UNSPEC_ATOMIC_LOAD))]
-  "TARGET_ATOMIC && TARGET_ZTSO"
+  "TARGET_ZTSO"
   {
 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 model = memmodel_base (model);
@@ -66,7 +66,7 @@
[(match_operand:GPR 1 "reg_or_0_operand" "rJ")
 (match_operand:SI 2 "const_int_operand")]  ;; model
 UNSPEC_ATOMIC_STORE))]
-  "TARGET_ATOMIC && TARGET_ZTSO"
+  "TARGET_ZTSO"
   {
 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6ff3493b5ce..ec9d4b4f59e 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -60,7 +60,7 @@
   [(match_operand:GPR 0 "register_operand")
(match_operand:GPR 1 "memory_operand")
(match_operand:SI 2 "const_int_operand")] ;; model
-  "TARGET_ATOMIC"
+  ""
   {
 if (TARGET_ZTSO)
   emit_insn (gen_atomic_load_ztso (operands[0], operands[1],
@@ -75,7 +75,7 @@
   [(match_operand:GPR 0 "memory_operand")
(match_operand:GPR 1 "reg_or_0_operand")
(match_operand:SI 2 "const_int_operand")] ;; model
-  "TARGET_ATOMIC"
+  ""
   {
 if (TARGET_ZTSO)
   emit_insn (gen_atomic_store_ztso (operands[0], operands[1],
--
2.34.1

[PATCH] RISC-V: Enable ztso tests on rv32

[Patrick O'Neill]

This patch transitions the ztso testcases to use the testsuite infrastructure,
enabling the tests on both rv64 and rv32 targets.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Ztso extension to
dg-options for dg-do compile.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
* lib/target-supports.exp: Add testing infrastructure to require the
Ztso extension or add it to an existing -march.

Signed-off-by: Patrick O'Neill 
---
 .../riscv/amo-table-ztso-amo-add-1.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-2.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-3.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-4.c  |  3 ++-
 .../riscv/amo-table-ztso-amo-add-5.c  |  3 ++-
 .../riscv/amo-table-ztso-compare-exchange-1.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-2.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-3.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-4.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-5.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-6.c |  2 +-
 .../riscv/amo-table-ztso-compare-exchange-7.c |  2 +-
 .../gcc.target/riscv/amo-table-ztso-fence-1.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-2.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-3.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-4.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-fence-5.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-1.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-2.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-load-3.c  |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-1.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-2.c |  3 ++-
 .../gcc.target/riscv/amo-table-ztso-store-3.c |  3 ++-
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |  2 +-
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |  2 +-
 gcc/testsuite/lib/target-supports.exp | 23 +++
 29 files changed, 67 insertions(+), 28 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index a88d08eb3f4..65a4351025d 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index ebd240f9dd2..03da6b04de0 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings the Ztso suggested mapping.  */
-/* {

[Committed] RISC-V: Make rv32i_zcmp testcase more robust

[Patrick O'Neill]

On 10/30/23 09:55, Jeff Law wrote:



On 10/30/23 10:37, Patrick O'Neill wrote:

GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.popret insns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
range of 1-9 for cm.push and cm.popret insns.

OK
jeff


Committed.

Patrick

Re: [PATCH v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump

[Patrick O'Neill]

On 10/29/23 20:21, Vineet Gupta wrote:

RV64 compare and branch instructions only support 64-bit operands.
At Expand time, the backend conservatively zero/sign extends
its operands even if not needed, such as incoming 32-bit function args
which ABI/ISA guarantee to be sign-extended already.

And subsequently REE fails to eliminate them as
"missing defintion(s)" or "multiple definition(s)
since function args don't have explicit definition.

So during expand riscv_extend_comparands (), if an operand is a
subreg-promoted SI with inner DI, which is representative of a function
arg, just peel away the subreg to expose the DI, eliding the sign
extension. As Jeff noted this routine is also used in if-conversion so
also helps there.

Note there's currently patches floating around to improve REE and also a
new pass to eliminate unneccesary extensions, but it is still beneficial
to not generate those extra extensions in first place. It is obviously
less work for post-reload passes such as REE, but even for earlier
passes, such as combine, having to deal with one less thing and ensuing
fewer combinations is a win too.

Way too many existing tests used to observe this issue.
e.g. gcc.c-torture/compile/20190827-1.c -O2 -march=rv64gc
It elimiates the SEXT.W

Tested with rv64gc with no regressions, I'm relying on PAtrick's
pre-commit CI to do the full testing.

Testing on the pre-commit CI has completed.
https://github.com/ewlu/gcc-precommit-ci/issues/499#issuecomment-1784446631

The patch was applied to this baseline:
https://github.com/gcc-mirror/gcc/commit/c6929b085580cf00cbc52b0f5b0afe2b9caa2a22

and no new failures or resolved failures were found when running the 
testsuite.


Tested-by: Patrick O'Neill 

Thanks!
Patrick


gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sign_extend_if_not_subreg_prom): New.
* (riscv_extend_comparands): Call New function on operands.

Signed-off-by: Vineet Gupta 
---
Changes since v2:
   - Fix linting issues flagged by pre-commit CI
Changes since v1:
   - Elide sign extension for 32-bit operarnds only
   - Apply elison for both arguments
---
  gcc/config/riscv/riscv.cc | 23 +--
  1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ca9a2ca81d53..269beb3b159b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3678,6 +3678,24 @@ riscv_zero_if_equal (rtx cmp0, rtx cmp1)
   cmp0, cmp1, 0, 0, OPTAB_DIRECT);
  }
  
+/* Helper function for riscv_extend_comparands to Sign-extend the OP.

+   However if the OP is SI subreg promoted with an inner DI, such as
+   (subreg/s/v:SI (reg/v:DI) 0)
+   just peel off the SUBREG to get DI, avoiding extraneous extension.  */
+
+static void
+riscv_sign_extend_if_not_subreg_prom (rtx *op)
+{
+  if (GET_MODE (*op) == SImode
+  && GET_CODE (*op) == SUBREG
+  && SUBREG_PROMOTED_VAR_P (*op)
+  && GET_MODE_SIZE (GET_MODE (XEXP (*op, 0))).to_constant ()
+== GET_MODE_SIZE (word_mode))
+*op = XEXP (*op, 0);
+  else
+*op = gen_rtx_SIGN_EXTEND (word_mode, *op);
+}
+
  /* Sign- or zero-extend OP0 and OP1 for integer comparisons.  */
  
  static void

@@ -3707,9 +3725,10 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx 
*op1)
}
else
{
- *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0);
+ riscv_sign_extend_if_not_subreg_prom (op0);
+
  if (*op1 != const0_rtx)
-   *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1);
+   riscv_sign_extend_if_not_subreg_prom (op1);
}
  }
  }

[PATCH] RISC-V: Make rv32i_zcmp testcase more robust

[Patrick O'Neill]

GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.popret insns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
range of 1-9 for cm.push and cm.popret insns.

Signed-off-by: Patrick O'Neill 
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c 
b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
index ea562b7a233..1e1a8be8705 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
@@ -26,9 +26,9 @@ f2 (void);
 /*
 **test1:
 ** ...
-** cm.push {ra, s0-s4}, -80
+** cm.push {ra, s0-s[1-9]}, -80
 ** ...
-** cm.popret   {ra, s0-s4}, 80
+** cm.popret   {ra, s0-s[1-9]}, 80
 ** ...
 */
 int
@@ -50,9 +50,9 @@ test1 ()
 /*
 **test2_step1_0_size:
 ** ...
-** cm.push {ra, s0-s1}, -64
+** cm.push {ra, s0-s[1-9]}, -64
 ** ...
-** cm.popret   {ra, s0-s1}, 64
+** cm.popret   {ra, s0-s[1-9]}, 64
 ** ...
 */
 int
@@ -70,9 +70,9 @@ test2_step1_0_size ()
 /*
 **test3:
 ** ...
-** cm.push {ra, s0-s4}, -80
+** cm.push {ra, s0-s[1-9]}, -80
 ** ...
-** cm.popret   {ra, s0-s4}, 80
+** cm.popret   {ra, s0-s[1-9]}, 80
 ** ...
 */
 float
-- 
2.34.1

Re: [PATCH] RISC-V: Make stack_save_restore_2 more robust

[Patrick O'Neill]

On 10/27/23 11:02, Jeff Law wrote:



On 10/27/23 11:56, Patrick O'Neill wrote:

GCC recently changed to emit __riscv_restore_5 which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any number after __riscv_save_ and __riscv_restore_.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/stack_save_restore_2.c: Accept any number
after __riscv_save_ and __riscv_restore_.

OK
jeff


Committed

Patrick

[PATCH] RISC-V: Make stack_save_restore_2 more robust

[Patrick O'Neill]

GCC recently changed to emit __riscv_restore_5 which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any number after __riscv_save_ and __riscv_restore_.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/stack_save_restore_2.c: Accept any number
after __riscv_save_ and __riscv_restore_.

Signed-off-by: Patrick O'Neill 
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
 gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c 
b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
index 4c549cb11ae..5f0389243b1 100644
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
@@ -7,7 +7,7 @@ float getf();
 
 /*
 ** bar:
-** callt0,__riscv_save_(3|4)
+** callt0,__riscv_save_[0-9]+
 ** addisp,sp,-[0-9]+
 ** ...
 ** li  t0,-[0-9]+
@@ -17,7 +17,7 @@ float getf();
 ** add sp,sp,t0
 ** ...
 ** addisp,sp,[0-9]+
-** tail__riscv_restore_(3|4)
+** tail__riscv_restore_[0-9]+
 */
 int bar()
 {
-- 
2.34.1

Re: [committed] RISC-V: Make stack_save_restore tests more robust

[Patrick O'Neill]

On 8/25/23 15:36, Jeff Law wrote:
Spurred by Jivan's patch and a desire for cleaner testresults, I went 
ahead and make the stack_save_restore tests independent of the precise 
stack size by using a regexp.


Pushed to the trunk.

Jeff


Hi Jeff, A recent change that I'm still bisecting [1] caused 
stack_save_restore_2.c to start failing.


Debug log:

Executing on host: 
/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
 
-B/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
  
/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
  -march=rv32gcv -mabi=ilp32d -mcmodel=medlow   -fdiagnostics-plain-output
-O0  -march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns 
-fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto -S   -o 
stack_save_restore_2.s(timeout = 600)
spawn -ignore SIGHUP 
/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
 
-B/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
 
/github/patrick-postcommit-runner-1/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
 -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O0 
-march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns 
-fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto -S -o 
stack_save_restore_2.s
PASS: gcc.target/riscv/stack_save_restore_2.c   -O0  (test for excess errors)
body: \tcallt0,__riscv_save_(3|4)
\taddi  sp,sp,-[0-9]+
.*\tli  t0,-[0-9]+
\tadd   sp,sp,t0
.*\tli  t0,[0-9]+
\tadd   sp,sp,t0
.*\taddisp,sp,[0-9]+
\ttail  __riscv_restore_(3|4)

against:callt0,__riscv_save_5
addisp,sp,-2016
fsw fs0,2012(sp)
fsw fs1,2008(sp)
fsw fs2,2004(sp)
fsw fs3,2000(sp)
fsw fs4,1996(sp)
li  t0,-12288
add sp,sp,t0
callgetf
fmv.s   fs1,fa0
callgetf
fmv.s   fs4,fa0
callgetf
fmv.s   fs3,fa0
callgetf
fmv.s   fs2,fa0
li  s0,0
fmv.s.x fs0,zero
lui a5,%hi(.LC0)
lw  s2,%lo(.LC0)(a5)
lw  s3,%lo(.LC0+4)(a5)
addis4,sp,1984
li  s1,4096
addis1,s1,-528
callmy_getchar
call__floatsidf
mv  a2,s2
mv  a3,s3
call__muldf3
call__truncdfsf2
sllia5,s0,2
add a5,s4,a5
fsw fa0,-1984(a5)
flw fa5,-1984(a5)
fadd.s  fs0,fs0,fa5
addis0,s0,1
bne s0,s1,.L2
fadd.s  fa5,fs1,fs0
fadd.s  fa5,fa5,fs4
fadd.s  fa5,fa5,fs3
fadd.s  fa5,fa5,fs2
fcvt.w.s a0,fa5,rtz
li  t0,12288
add sp,sp,t0
flw fs0,2012(sp)
flw fs1,2008(sp)
flw fs2,2004(sp)
flw fs3,2000(sp)
flw fs4,1996(sp)
addisp,sp,2016
tail__riscv_restore_5

FAIL: gcc.target/riscv/stack_save_restore_2.c   -O0   check-function-bodies bar

It looks like the issue is that your regex matches
__riscv_save_(3|4) where now gcc emits __riscv_restore_5.

Would it be OK to update the regex to also accept 5 (& are we going to 
bump into this again)?


diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c 
b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c

index 4c549cb11ae..bc95736cf8e 100644
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
@@ -7,7 +7,7 @@ float getf();

 /*
 ** bar:
-** call    t0,__riscv_save_(3|4)
+** call    t0,__riscv_save_(3|4|5)
 ** addi    sp,sp,-[0-9]+
 ** ...
 ** li  t0,-[0-9]+
@@ -17,7 +17,7 @@ float getf();
 ** add sp,sp,t0
 ** ...
 ** addi    sp,sp,[0-9]+
-** tail    __riscv_restore_(3|4)
+** tail    __riscv_restore_(3|4|5)
 */
 int bar()
 {

If we're going to run into this again, it might make sense to allow a 
wider range of numbers (up to 9):


diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c 
b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c

index 4c549cb11ae..1d5b950130e 100644
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
@@ -7,7 +7,7 @@ float getf();

 /*
 ** bar:
-** call    t0,__riscv_save_(3|4)
+** call    t0,__riscv_save_([3-9])
 ** addi    sp,sp,-[0-9]+
 ** ...
 ** li  t0,-[0-9]+
@@ -17,7 +17,7 @@ 

Re: [Ready to commit V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

[Patrick O'Neill]

On 10/26/23 11:15, Robin Dapp wrote:


rv32gcv:
FAIL: gfortran.dg/intrinsic_pack_6.f90   -O2  execution test
FAIL: gfortran.dg/intrinsic_pack_6.f90   -O3 -g  execution test
FAIL: gfortran.dg/matmul_3.f90   -O2  execution test
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  -O2
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  -O2 
-fbounds-check
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  -O2 
-fomit-frame-pointer -finline-functions
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  -O3 -g

rv64gcv:
FAIL: gfortran.dg/matmul_6.f90   -O2  execution test

Those might also flip flop, I have them seen FAIL and PASS before
randomly.  It looks like there is at least 10 of those, really need
to figure out the root cause...

Regards
  Robin


I've seen the same thing on CI for some of these failures on rv32gcv but always 
as a group:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111969

Example CI run with the flaky group:
https://github.com/patrick-rivos/gcc-postcommit-ci/issues/75

The fact that some are resolved while not resolving the full group makes me 
hopeful that:
FAIL: gfortran.dg/intrinsic_pack_6.f90  execution test
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution
are really resolved

I haven't seen these testcases be flaky on CI:
FAIL: gfortran.dg/matmul_3.f90   -O2  execution test
FAIL: gfortran.dg/matmul_6.f90   -O2  execution test

Patrick

Re: [Ready to commit V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

[Patrick O'Neill]

popcount and mask_gather_load_run fails seem to be an issue with my 
setup or a bug with QEMU based on the v2 discussion :-)


OK with me regarding testing (I don't have the authority to approve a 
patch, but Kito already said LGTM):

https://inbox.sourceware.org/gcc-patches/CALLt3ThXmk4pey2QhSUvK183uuK3oY5bU=a4m8qyv-6uukb...@mail.gmail.com/

Thanks for your patience and the revisions!

Your patch resolves these failures on glibc qemu:

rv32gcv:
FAIL: gfortran.dg/intrinsic_pack_6.f90   -O2  execution test
FAIL: gfortran.dg/intrinsic_pack_6.f90   -O3 -g  execution test
FAIL: gfortran.dg/matmul_3.f90   -O2  execution test
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  -O2
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  
-O2 -fbounds-check
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  
-O2 -fomit-frame-pointer -finline-functions
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,  
-O3 -g


rv64gcv:
FAIL: gfortran.dg/matmul_6.f90   -O2  execution test

Tested-by: Patrick O'Neill 

Patrick

On 10/26/23 01:13, Juzhe-Zhong wrote:

This patch addresses the redundant AVL/VL toggling in RVV partial 
auto-vectorization
which is a known issue for a long time and I finally find the time to address 
it.

Consider a simple vector addition operation:

https://godbolt.org/z/7hfGfEjW3

void
foo (int *__restrict a,
  int *__restrict b,
  int *__restrict n)
{
   for (int i = 0; i < n; i++)
   a[i] = a[i] + b[i];
}

Optimized IR:

Loop body:
   _38 = .SELECT_VL (ivtmp_36, POLY_INT_CST [4, 4]);  
-> vsetvli a5,a2,e8,mf4,ta,ma
   ...
   vect__4.8_27 = .MASK_LEN_LOAD (vectp_a.6_29, 32B, { -1, ... }, _38, 0);
-> vle32.v v2,0(a0)
   vect__6.11_20 = .MASK_LEN_LOAD (vectp_b.9_25, 32B, { -1, ... }, _38, 0);   
-> vle32.v v1,0(a1)
   vect__7.12_19 = vect__6.11_20 + vect__4.8_27;  
-> vsetvli a6,zero,e32,m1,ta,ma + vadd.vv v1,v1,v2
   .MASK_LEN_STORE (vectp_a.13_11, 32B, { -1, ... }, _38, 0, vect__7.12_19);  
-> vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a4)

We can see 2 redundant vsetvls inside the loop body due to AVL/VL toggling.
The AVL/VL toggling is because we are missing LEN information in simple 
PLUS_EXPR GIMPLE assignment:

vect__7.12_19 = vect__6.11_20 + vect__4.8_27;

GCC apply partial predicate load/store and un-predicated full vector operation 
on partial vectorization.
Such flow are used by all other targets like ARM SVE (RVV also uses such flow):

ARM SVE:

.L3:

 ld1wz30.s, p7/z, [x0, x3, lsl 2]   -> predicated load
 ld1wz31.s, p7/z, [x1, x3, lsl 2]   -> predicated load
 add z31.s, z31.s, z30.s-> un-predicated add
 st1wz31.s, p7, [x0, x3, lsl 2] -> predicated store

Such vectorization flow causes AVL/VL toggling on RVV so we need AVL 
propagation PASS for it.

Also, It's very unlikely that we can apply predicated operations on all 
vectorization for following reasons:

1. It's very heavy workload to support them on all vectorization and we don't 
see any benefits if we can handle that on targets backend.
2. Changing Loop vectorizer for it will make code base ugly and hard to 
maintain.
3. We will need so many patterns for all operations. Not only COND_LEN_ADD, 
COND_LEN_SUB, 
We also need COND_LEN_EXTEND, , COND_LEN_CEIL, ... .. over 100+ 
patterns, unreasonable number of patterns.

To conclude, we prefer un-predicated operations here, and design a nice and 
clean AVL propagation PASS for it to elide the redundant vsetvls
due to AVL/VL toggling.

The second question is that why we separate a PASS called AVL propagation. Why 
not optimize it in VSETVL PASS (We definitetly can optimize AVL in VSETVL PASS)

Frankly, I was planning to address such issue in VSETVL PASS that's why we 
recently refactored VSETVL PASS. However, I changed my mind recently after 
several
experiments and tries.

The reasons as follows:

1. For code base management and maintainience. Current VSETVL PASS is 
complicated enough and aleady has enough aggressive and fancy optimizations 
which
turns out it can always generate optimal codegen in most of the cases. It's 
not a good idea keep adding more features into VSETVL PASS to make VSETVL
 PASS become heavy and heavy again, then we will need to refactor it 
again in the future.
 Actuall, the VSETVL PASS is very stable and optimal after the recent 
refactoring. Hopefully, we should not change VSETVL PASS any more except the 
minor
 fixes.

2. vsetvl insertion (VSETVL PASS does this thing) and AVL propagation are 2 
different things,  I don't think we should fuse them into same PASS.

3. VSETVL PASS is an post-RA PASS, wheras AVL propagtion should be done before 
RA which can reduce register allocation.

4. This patch's AVL propagation PASS only does AVL propagation for RVV partial 
auto-vectorizatio

[Committed] RISC-V: Pass abi to g++ rvv testsuite

[Patrick O'Neill]

On 10/26/23 06:30, Jeff Law wrote:



On 10/25/23 18:13, Patrick O'Neill wrote:

On rv32gcv testcases like g++.target/riscv/rvv/base/bug-22.C fail with:
FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors)
Excess errors:
cc1plus: error: ABI requires '-march=rv32'

This patch adds the -mabi argument to g++ rvv tests.

gcc/testsuite/ChangeLog:

 * g++.target/riscv/rvv/rvv.exp: Add -mabi argument to CFLAGS.

OK.
jeff


Committed, thanks.

Patrick

[PATCH] RISC-V: Pass abi to g++ rvv testsuite

[Patrick O'Neill]

On rv32gcv testcases like g++.target/riscv/rvv/base/bug-22.C fail with:
FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors)
Excess errors:
cc1plus: error: ABI requires '-march=rv32'

This patch adds the -mabi argument to g++ rvv tests.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/rvv.exp: Add -mabi argument to CFLAGS.

Signed-off-by: Patrick O'Neill 
---
Resolved failures:
FAIL: g++.target/riscv/rvv/base/bug-18.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-19.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-20.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-21.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors)
---
 gcc/testsuite/g++.target/riscv/rvv/rvv.exp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp 
b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
index c30d6e93144..5b01e4e05d2 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/g++.target/riscv/rvv/rvv.exp
@@ -28,15 +28,17 @@ if ![istarget riscv*-*-*] then {
 load_lib g++-dg.exp
 
 set gcc_march "rv64gcv_zfh"
+set gcc_mabi  "lp64d"
 if [istarget riscv32-*-*] then {
   set gcc_march "rv32gcv_zfh"
+  set gcc_mabi  "ilp32d"
 }
 
 # Initialize `dg'.
 dg-init
 
 # Main loop.
-set CFLAGS "-march=$gcc_march -O3"
+set CFLAGS "-march=$gcc_march -mabi=$gcc_mabi -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.C]] \
"" $CFLAGS
 
-- 
2.34.1

Re: [PATCH] RISC-V: Add AVL propagation PASS for RVV auto-vectorization

[Patrick O'Neill]

The CI just picked it up: 
https://github.com/ewlu/gcc-precommit-ci/issues/449#issue-1958483272
Since it doesn't apply to the CI's baseline hash it's only performing a 
build.

I'll re-run it in the morning once the baseline has been updated.

In the meantime I started a full build+test run on my local machine.
I'll send you the results in ~10 hours - morning my time :-)

Patrick

On 10/23/23 20:44, juzhe.zh...@rivai.ai wrote:

CCing Patrick...

Hi, @Patrick.
Could you apply this patch and trigger your regression CI?

I don't have an environment to test fortran for now (I only test it on 
C/C++).


Thanks.


juzhe.zh...@rivai.ai

*From:* Juzhe-Zhong 
*Date:* 2023-10-24 11:32
*To:* gcc-patches 
*CC:* kito.cheng ; kito.cheng
; jeffreyalaw
; rdapp.gcc
; Juzhe-Zhong

*Subject:* [PATCH] RISC-V: Add AVL propagation PASS for RVV
auto-vectorization
This patch addresses the redundant AVL/VL toggling in RVV partial
auto-vectorization
which is a known issue for a long time and I finally find the time
to address it.
Consider a simple vector addition operation:
https://godbolt.org/z/7hfGfEjW3
void
foo (int *__restrict a,
 int *__restrict b,
 int *__restrict n)
{
  for (int i = 0; i < n; i++)
  a[i] = a[i] + b[i];
}
Optimized IR:
Loop body:
  _38 = .SELECT_VL (ivtmp_36, POLY_INT_CST [4,
4]);  -> vsetvli a5,a2,e8,mf4,ta,ma
  ...
  vect__4.8_27 = .MASK_LEN_LOAD (vectp_a.6_29, 32B, { -1, ... },
_38, 0);    -> vle32.v v2,0(a0)
  vect__6.11_20 = .MASK_LEN_LOAD (vectp_b.9_25, 32B, { -1, ... },
_38, 0);   -> vle32.v v1,0(a1)
  vect__7.12_19 = vect__6.11_20 +
vect__4.8_27;  -> vsetvli
a6,zero,e32,m1,ta,ma + vadd.vv v1,v1,v2
  .MASK_LEN_STORE (vectp_a.13_11, 32B, { -1, ... }, _38, 0,
vect__7.12_19);  -> vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a4)
We can see 2 redundant vsetvls inside the loop body due to AVL/VL
toggling.
The AVL/VL toggling is because we are missing LEN information in
simple PLUS_EXPR GIMPLE assignment:
vect__7.12_19 = vect__6.11_20 + vect__4.8_27;
GCC apply partial predicate load/store and un-predicated full
vector operation on partial vectorization.
Such flow are used by all other targets like ARM SVE (RVV also
uses such flow):
ARM SVE:
.L3:
    ld1w    z30.s, p7/z, [x0, x3, lsl 2]   -> predicated load
    ld1w    z31.s, p7/z, [x1, x3, lsl 2]   -> predicated load
    add z31.s, z31.s, z30.s    -> un-predicated add
    st1w    z31.s, p7, [x0, x3, lsl 2] -> predicated store
Such vectorization flow causes AVL/VL toggling on RVV so we need
AVL propagation PASS for it.
Also, It's very unlikely that we can apply predicated operations
on all vectorization for following reasons:
1. It's very heavy workload to support them on all vectorization
and we don't see any benefits if we can handle that on targets
backend.
2. Changing Loop vectorizer for it will make code base ugly and
hard to maintain.
3. We will need so many patterns for all operations. Not only
COND_LEN_ADD, COND_LEN_SUB, 
   We also need COND_LEN_EXTEND, , COND_LEN_CEIL, ... .. over
100+ patterns, unreasonable number of patterns.
To conclude, we prefer un-predicated operations here, and design a
nice and clean AVL propagation PASS for it to elide the redundant
vsetvls
due to AVL/VL toggling.
The second question is that why we separate a PASS called AVL
propagation. Why not optimize it in VSETVL PASS (We definitetly
can optimize AVL in VSETVL PASS)
Frankly, I was planning to address such issue in VSETVL PASS
that's why we recently refactored VSETVL PASS. However, I changed
my mind recently after several
experiments and tries.
The reasons as follows:
1. For code base management and maintainience. Current VSETVL PASS
is complicated enough and aleady has enough aggressive and fancy
optimizations which
   turns out it can always generate optimal codegen in most of the
cases. It's not a good idea keep adding more features into VSETVL
PASS to make VSETVL
PASS become heavy and heavy again, then we will need to refactor
it again in the future.
Actuall, the VSETVL PASS is very stable and optimal after the
recent refactoring. Hopefully, we should not change VSETVL PASS
any more except the minor
fixes.
2. vsetvl insertion (VSETVL PASS does this thing) and AVL
propagation are 2 different things,  I don't think we should fuse

Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

IIRC --enable-checking=yes does not turn on RTL checking.
You need to pass in rtl explicitly using --enable-checking=rtl
You can also pass in a list of checks like this: --enable-checking=yes,rtl

Patrick

On 10/23/23 17:51, juzhe.zh...@rivai.ai wrote:

I don't have such issue:

[jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$~/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc 
-v

Using built-in specs.
COLLECT_GCC=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/libexec/gcc/riscv64-unknown-elf/14.0.0/lto-wrapper
Target: riscv64-unknown-elf
Configured with: 
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/../../gcc/configure 
--target=riscv64-unknown-elf 
--prefix=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install 
--disable-shared --disable-threads --enable-languages=c,c++ 
--with-pkgversion=g70b66ac9bcb-dirty --with-system-zlib --enable-tls 
--with-newlib 
--with-sysroot=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/riscv64-unknown-elf 
--with-native-system-header-dir=/include --disable-libmudflap 
--disable-libssp --disable-libquadmath --disable-libgomp --disable-nls 
--disable-tm-clone-registry --src=../../../gcc --enable-checking=yes 
--disable-multilib --with-abi=lp64d --with-arch=rv64gcv_zfh_zvfh 
--with-tune=rocket --with-isa-spec=20191213 CFLAGS='-O0 -g3' 
CXXFLAGS='-O0 -g3' 'CFLAGS_FOR_TARGET=-Os    -mcmodel=medany' 
'CXXFLAGS_FOR_TARGET=-Os    -mcmodel=medany'

Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)



juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 07:42
*To:* 钟居哲 <mailto:juzhe.zh...@rivai.ai>; 丁乐华
<mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
Jeff Law <mailto:jeffreya...@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
*Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

When configuring, pass in --enable-checking=rtl
If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl

The -freport-bug output attached to the bug report has the full
configure command used:
/scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking
--with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot
--with-newlib --without-headers --disable-shared --disable-threads
--with-system-zlib --enable-tls --enable-languages=c
--disable-libatomic --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libgomp --disable-nls
--disable-bootstrap --src=../../gcc --enable-checking=rtl
--disable-multilib --with-abi=lp64d --with-arch=rv64gcv
--with-tune=rocket --with-isa-spec=20191213
'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'
'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'

On 10/23/23 15:50, 钟居哲 wrote:

I didn't reproduce it. How to enable RTL checking ?

----
    juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 06:46
*To:* 钟居哲 <mailto:juzhe.zh...@rivai.ai>; 丁乐华
<mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer
<mailto:pal...@rivosinc.com>; Jeff Law
<mailto:jeffreya...@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
*Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

You're on top of it - thanks for fixing this! I'll send the
testcase.

Unrelated to this failure, I'm seeing a build failure on
glibc rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick

On 10/23/23 14:41, 钟居哲 wrote:

I have fixed it:

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if
you confirm it has been fixed on the trunk.

Thanks.
-----------

Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

When configuring, pass in --enable-checking=rtl
If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl

The -freport-bug output attached to the bug report has the full 
configure command used:
/scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure 
--target=riscv64-unknown-linux-gnu 
--prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking 
--with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot 
--with-newlib --without-headers --disable-shared --disable-threads 
--with-system-zlib --enable-tls --enable-languages=c --disable-libatomic 
--disable-libmudflap --disable-libssp --disable-libquadmath 
--disable-libgomp --disable-nls --disable-bootstrap --src=../../gcc 
--enable-checking=rtl --disable-multilib --with-abi=lp64d 
--with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 
'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2    
-mcmodel=medlow'


On 10/23/23 15:50, 钟居哲 wrote:

I didn't reproduce it. How to enable RTL checking ?


juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 06:46
*To:* 钟居哲 <mailto:juzhe.zh...@rivai.ai>; 丁乐华
<mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
Jeff Law <mailto:jeffreya...@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
*Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc
rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick

On 10/23/23 14:41, 钟居哲 wrote:

I have fixed it:

https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you
confirm it has been fixed on the trunk.

Thanks.
----
    juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 02:30
*To:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer
<mailto:pal...@rivosinc.com>; Jeff Law
<mailto:jeffreya...@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>; 钟居哲
<mailto:juzhe.zh...@rivai.ai>
*Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
This patch causes a build failure with newlib 4.1.0 with
-march=rv64gv_zbb.
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
Thanks,
Patrick
On 10/19/23 20:58, Lehua Ding wrote:
    > Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g
execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
    >> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g
execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill 
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI
in your
>>> github  so that we can see the full running result.
>>>
>>> 

Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc 
rv32/64gcv when RTL checking is enabled.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick

On 10/23/23 14:41, 钟居哲 wrote:

I have fixed it:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you confirm 
it has been fixed on the trunk.


Thanks.

juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 02:30
*To:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
Jeff Law <mailto:jeffreya...@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>; 钟居哲 <mailto:juzhe.zh...@rivai.ai>
*Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
This patch causes a build failure with newlib 4.1.0 with
-march=rv64gv_zbb.
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
Thanks,
Patrick
On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
    >> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill 
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>>


>>>
>>> juzhe.zh...@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.d...@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zh...@rivai.ai>; kito.cheng
>>> <mailto:kito.ch...@gmail.com>; rdapp.gcc
>>> <mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreya...@gmail.com>; lehua.ding
>>> <mailto:lehua.d...@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order
to make
>>>     the code
>>>     easier to modify and understand. This patch does several
things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1,
2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The
Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward
direction.
>>>   

Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

Hi Lehua,

This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.

I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941

Thanks,
Patrick

On 10/19/23 20:58, Lehua Ding wrote:

Committed, thanks Patrick and Juzhe.

On 2023/10/20 2:04, Patrick O'Neill wrote:

I tested it this morning on my machine and it passed!

Tested against:
04d6c74564b7eb51660a00b35353aeab706b5a50

Using targets:
glibc rv32gcv qemu
glibc rv64gcv qemu

This patch series does not introduce any new failures.

Here's a list of *resolved* failures by this patch series:
rv64gcv:
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
-finline-functions  execution test

FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

rv32gcv:
FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
-finline-functions  execution test

FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

Thanks for the quick revision Lehua!

Tested-by: Patrick O'Neill 

Patrick

On 10/19/23 01:50, 钟居哲 wrote:

LGTM now. But wait for Patrick CI testing.

Hi, @Patrick. Could you apply this patch and trigger CI in your 
github  so that we can see the full running result.


Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
<https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>


 


juzhe.zh...@rivai.ai

    *From:* Lehua Ding <mailto:lehua.d...@rivai.ai>
    *Date:* 2023-10-19 16:33
    *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
    *CC:* juzhe.zhong <mailto:juzhe.zh...@rivai.ai>; kito.cheng
    <mailto:kito.ch...@gmail.com>; rdapp.gcc
    <mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
    jeffreyalaw <mailto:jeffreya...@gmail.com>; lehua.ding
    <mailto:lehua.d...@rivai.ai>
    *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
    This patch refactors and cleanups the vsetvl pass in order to make
    the code
    easier to modify and understand. This patch does several things:
    1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
    only maintain
       and modify this virtual CFG. Phase 4 performs insertion,
    modification and
       deletion of vsetvl insns based on the virtual CFG. The Basic
    block in the
       virtual CFG is called vsetvl_block_info and the vsetvl
    information inside
       is called vsetvl_info.
    2. Combine Phase 1 and 2 into a single Phase 1 and unified the
    demand system,
       this Phase only fuse local vsetvl info in forward direction.
    3. Refactor Phase 3, change the logic for determining whether to
    uplift vsetvl
       info to a pred basic block to a more unified method that there
    is a vsetvl
       info in the vsetvl defintion reaching in compatible with it.
    4. Place all modification operations to the RTL in Phase 4 and
    Phase 5.
       Phase 4 is responsible for inserting, modifying and deleting 
vsetvl

       instructions based on fully optimized vsetvl infos. Phase 5
    removes the avl
       operand from the RVV instruction and removes the unused dest
    operand
       register from the vsetvl insns.
    These modifications resulted in some testcases needing to be
    updated. The reasons
    for updating are summarized below:
    1. more optimized
vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
       vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
    2. less unnecessary fusion
    avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
    3. local fuse direction (backward -> forward)
       scalar_move-1.c/
    4. add some bugfix testcases.
       pr111037-3.c/pr111037-4.c
       avl_single-89.c
    PR target/111037
    PR target/111234
    PR target/111725
    Lehua Ding (11):
      RISC-V: P1: Refactor
    avl_info/vl_vtype_info/vector_insn_info/vector_block_info
      RISC-V: P2: Refactor and cleanup demand system
      RISC-V: P3: Refactor vector_infos_manager
      RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
      RISC-V: P5: combine phase 1 and 2
      RISC-V: P6: Add computing reaching definition data flow
      RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
      RISC-V: P8: Refactor emit-vsetvl phase and delete post 
optimization

      RISC-V: P9: Cleanup and reorganize helper functions
      RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
      RISC-V: P11: Adjust and add testcases
    gcc/config/riscv/riscv-vsetvl.cc  | 6502 
+++--

    gcc/config/riscv/riscv-vsetvl.def |  641 +-
    gcc/config/riscv/riscv-vsetvl.h   |  488 --
    gcc/config/riscv/t-riscv  

Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

I tested it this morning on my machine and it passed!

Tested against:
04d6c74564b7eb51660a00b35353aeab706b5a50

Using targets:
glibc rv32gcv qemu
glibc rv64gcv qemu

This patch series does not introduce any new failures.

Here's a list of *resolved* failures by this patch series:
rv64gcv:
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test

FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

rv32gcv:
FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test

FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

Thanks for the quick revision Lehua!

Tested-by: Patrick O'Neill 

Patrick

On 10/19/23 01:50, 钟居哲 wrote:

LGTM now. But wait for Patrick CI testing.

Hi, @Patrick. Could you apply this patch and trigger CI in your 
github  so that we can see the full running result.


Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
<https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>



juzhe.zh...@rivai.ai

*From:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*Date:* 2023-10-19 16:33
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* juzhe.zhong <mailto:juzhe.zh...@rivai.ai>; kito.cheng
<mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal...@rivosinc.com>;
jeffreyalaw <mailto:jeffreya...@gmail.com>; lehua.ding
<mailto:lehua.d...@rivai.ai>
*Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
This patch refactors and cleanups the vsetvl pass in order to make
the code
easier to modify and understand. This patch does several things:
1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
only maintain
   and modify this virtual CFG. Phase 4 performs insertion,
modification and
   deletion of vsetvl insns based on the virtual CFG. The Basic
block in the
   virtual CFG is called vsetvl_block_info and the vsetvl
information inside
   is called vsetvl_info.
2. Combine Phase 1 and 2 into a single Phase 1 and unified the
demand system,
   this Phase only fuse local vsetvl info in forward direction.
3. Refactor Phase 3, change the logic for determining whether to
uplift vsetvl
   info to a pred basic block to a more unified method that there
is a vsetvl
   info in the vsetvl defintion reaching in compatible with it.
4. Place all modification operations to the RTL in Phase 4 and
Phase 5.
   Phase 4 is responsible for inserting, modifying and deleting vsetvl
   instructions based on fully optimized vsetvl infos. Phase 5
removes the avl
   operand from the RVV instruction and removes the unused dest
operand
   register from the vsetvl insns.
These modifications resulted in some testcases needing to be
updated. The reasons
for updating are summarized below:
1. more optimized
vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
   vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
2. less unnecessary fusion
avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
3. local fuse direction (backward -> forward)
   scalar_move-1.c/
4. add some bugfix testcases.
   pr111037-3.c/pr111037-4.c
   avl_single-89.c
PR target/111037
PR target/111234
PR target/111725
Lehua Ding (11):
  RISC-V: P1: Refactor
avl_info/vl_vtype_info/vector_insn_info/vector_block_info
  RISC-V: P2: Refactor and cleanup demand system
  RISC-V: P3: Refactor vector_infos_manager
  RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
  RISC-V: P5: combine phase 1 and 2
  RISC-V: P6: Add computing reaching definition data flow
  RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
  RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
  RISC-V: P9: Cleanup and reorganize helper functions
  RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
  RISC-V: P11: Adjust and add testcases
gcc/config/riscv/riscv-vsetvl.cc  | 6502 +++--
gcc/config/riscv/riscv-vsetvl.def |  641 +-
gcc/config/riscv/riscv-vsetvl.h   |  488 --
gcc/config/riscv/t-riscv  |    2 +-
.../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
.../riscv/rvv/vsetvl/avl_single-104.c |   35 +
.../riscv/rvv/vsetvl/avl_single-105.c |   23 +
.../riscv/rvv/vsetvl/avl_single-106.c |   34 +
.../riscv/rvv/vsetvl/avl_single-107.c |   41 +

Re: [PATCH V2 00/14] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

-stage2/gcc/ 
/work/home/lding/open-source/riscv-gnu-toolchain-pu
sh/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c 
-march=rv64gcv_zvfh_zfh -mabi=lp64d -mcmodel=medany 
-fdiagnostics-plain-output -ftree-vectorize
 -O3 --param riscv-autovec-lmul=m4 
--param=riscv-autovec-preference=scalable -fno-vect-cost-model -lm -o 
./cond_convert_float2int_run-1.exe
PASS: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c 
(test for excess errors)

spawn riscv64-unknown-elf-run ./cond_convert_float2int_run-1.exe
bbl loader


On 2023/10/18 4:25, Patrick O'Neill wrote:

Hi Lehua!

I ran the gcc testsuite on qemu before/after applying your patches to 
305034e3 rv32/64gcv [1].


Baseline
    = Summary of gcc testsuite =
 | # of unexpected case / # of unique 
unexpected case

 |  gcc |  g++ | gfortran |
 rv32gcv/ ilp32d/ medlow |  208 /    78 |   29 /    17 | 71 /    
24 |
 rv64gcv/  lp64d/ medlow |  101 /    54 |   13 / 4 | 33 /    
13 |


After applying patch series:
    = Summary of gcc testsuite =
 | # of unexpected case / # of unique 
unexpected case

 |  gcc |  g++ | gfortran |
 rv32gcv/ ilp32d/ medlow |  256 /    96 |   29 /    17 | 69 /    
23 |
 rv64gcv/  lp64d/ medlow |  152 /    74 |   13 / 4 | 31 /    
12 |


I'm seeing:
20 new unique gcc failures on rv64gcv [2]
18 new unique gcc failures on rv32gcv [3]

Thanks,
Patrick

[1] Build commands:
git clone https://github.com/patrick-rivos/riscv-gnu-toolchain.git
cd riscv-gnu-toolchain
git submodule update --init gcc
cd gcc
git checkout 305034e3
cd ..
mkdir build
cd build
../configure --prefix=$(pwd) 
--with-multilib-generator="rv64gcv-lp64d--;rv32gcv-ilp32d--"

make report-linux -j32

Note: If you'd prefer to use upstream riscv-gnu-toolchain, I'm pretty 
sure you can do

mkdir build-64
cd build-64
../configure --prefix=$(pwd) --with-arch=rv64gcv --with-abi=lp64d
cd ..
mkdir build-32
cd build-32
../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=lp32d
This'll make 2 folders, so run make report-linux in each of them.

[2] rv64gcv New failures:
FAIL: gcc.dg/vect/slp-7.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/slp-7.c execution test
FAIL: gcc.target/riscv/zero-scratch-regs-2.c   -O3 -g 
scan-assembler-not \\mvsetvli
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O1 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none scan-assembler-times 
vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times 
vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -Os 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O1 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none scan-assembler-times 
vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times 
vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -Os 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O1 
scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 
scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none scan-assembler-times 
vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times 
vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O1 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none scan-assembler-times 
vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times 
vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -Os 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O1 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none scan-assembler-times 
vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan

Re: [PATCH V2 00/14] Refactor and cleanup vsetvl pass

[Patrick O'Neill]

Hi Lehua!

I ran the gcc testsuite on qemu before/after applying your patches to 
305034e3 rv32/64gcv [1].


Baseline
   = Summary of gcc testsuite =
    | # of unexpected case / # of unique 
unexpected case

    |  gcc |  g++ | gfortran |
    rv32gcv/ ilp32d/ medlow |  208 /    78 |   29 /    17 |   71 /    24 |
    rv64gcv/  lp64d/ medlow |  101 /    54 |   13 / 4 |   33 /    13 |

After applying patch series:
   = Summary of gcc testsuite =
    | # of unexpected case / # of unique 
unexpected case

    |  gcc |  g++ | gfortran |
    rv32gcv/ ilp32d/ medlow |  256 /    96 |   29 /    17 |   69 /    23 |
    rv64gcv/  lp64d/ medlow |  152 /    74 |   13 / 4 |   31 /    12 |

I'm seeing:
20 new unique gcc failures on rv64gcv [2]
18 new unique gcc failures on rv32gcv [3]

Thanks,
Patrick

[1] Build commands:
git clone https://github.com/patrick-rivos/riscv-gnu-toolchain.git
cd riscv-gnu-toolchain
git submodule update --init gcc
cd gcc
git checkout 305034e3
cd ..
mkdir build
cd build
../configure --prefix=$(pwd) 
--with-multilib-generator="rv64gcv-lp64d--;rv32gcv-ilp32d--"

make report-linux -j32

Note: If you'd prefer to use upstream riscv-gnu-toolchain, I'm pretty 
sure you can do

mkdir build-64
cd build-64
../configure --prefix=$(pwd) --with-arch=rv64gcv --with-abi=lp64d
cd ..
mkdir build-32
cd build-32
../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=lp32d
This'll make 2 folders, so run make report-linux in each of them.

[2] rv64gcv New failures:
FAIL: gcc.dg/vect/slp-7.c -flto -ffat-lto-objects execution test
FAIL: gcc.dg/vect/slp-7.c execution test
FAIL: gcc.target/riscv/zero-scratch-regs-2.c   -O3 -g scan-assembler-not 
\\mvsetvli
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O1 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-34.c   -Os 
scan-assembler-times vsetvli 1
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O1 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-37.c   -Os 
scan-assembler-times vsetvli 3
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O1 
scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 
scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-38.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 4
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O1 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-47.c   -Os 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O1 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-48.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-49.c   -O1 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-49.c   -O2 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-49.c   -O2 -flto 
-fno-use-linker-plugin -flto-partition=none   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-49.c   -O2 -flto 
-fuse-linker-plugin -fno-fat-lto-objects   scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-49.c   -Os 
scan-assembler-times vsetvli 2
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-65.c   -O2 

Re: [RFC gcc13 backport 0/3] Add Ztso atomic mappings

[Patrick O'Neill]

On 10/4/23 08:53, Jeff Law wrote:



On 10/3/23 16:26, Patrick O'Neill wrote:

I vaugely recall some discussion about backporting the Ztso mappings
along with the RVWMO mappings. Now that the RVWMO mappings have been
backported for 13.3, is there interest in also backporting the Ztso
mappings?

Tested using for regressions using rv32gc/rv64gc glibc.

Jeff Law (1):
   [RISCV][committed] Remove spurious newline in ztso sequence

Patrick O'Neill (2):
   RISC-V: Add Ztso atomic mappings
   RISC-V: Specify -mabi for ztso testcases
I recall discussing Ztso mappings, but not the final conclusion. I 
think the final decision comes down to the motivation behind the changes.


If they're primarily optimized sequences utilizing the stronger 
ordering guarantees from Ztso, then it's probably not a good candidate 
for gcc-13.  If the primary motivation is to make it easier to port 
code from targets with stronger memory models (ie x86), then the Ztso 
work is a reasonable candidate for backporting.


Jeff


Discussed during the GCC patchworks meeting.

The Ztso mappings are a subset of RVWMO fences/ordering constraints
(it's an optimization change) [1].
This backport also makes tip-of-tree sync.md files match gcc 13.3+ which
simplifies future atomic-related backports.

If in the future someone needs Ztso/there is a need to backport we can
re-evaluate this backport then.

Thanks
Patrick

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391

[Committed] RISC-V: Use stdint-gcc.h in rvv testsuite

[Patrick O'Neill]

Committed, thanks!

Patrick

On 10/5/23 17:51, Kito Cheng wrote:

LGTM

Patrick O'Neill  於 2023年10月6日 週五 07:46 寫道：

stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.

Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e.

gcc/testsuite/ChangeLog:

        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h:
        Replace stdint.h with stdint-gcc.h.
        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h:
        Ditto.
        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h:
        Ditto.
        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h:
        Ditto.
        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h:
        Ditto.
        *
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h:
        Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h:
        Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h:
        Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Ditto.
        * gcc.target/riscv/rvv/autovec/pr111232.c: Ditto.
        * gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Ditto.
        * gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vls-vlmax/perm.h: Ditto.
        * gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
        * gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
        * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.

Signed-off-by: Patrick O'Neill 
---
Changes from v1:
- Avoid changing riscv_vector.h

Failures looked like this:
In file included from
/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
              from
/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
              from
/riscv-gnu-toolchain/build/sysroot/usr/include/stdint.h:26,
              from

/riscv-gnu-toolchain/build/lib/gcc/riscv32-unknown-linux-gnu/14.0.0/include/stdint.h:9,
              from
/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/stdint.h:9,
              from

/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/riscv_vector.h:28,
              from

/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c:4:
/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:8:11:
fatal error: gnu/stubs-ilp32.h: No such file or directory

Resolves these failures on rv32gcv (non-multilib):
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
(test for excess errors)
FAIL:
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec

[PATCH v2] RISC-V: Use stdint-gcc.h in rvv testsuite

[Patrick O'Neill]

stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.

Tested using glibc rv32gcv and rv64gcv on r14-4381-g7eb5ce7f58e.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h:
Replace stdint.h with stdint-gcc.h.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h:
Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/pr111232.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/cvt-0.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/cvt-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm.h: Ditto.
* gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto.
* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.

Signed-off-by: Patrick O'Neill 
---
Changes from v1:
- Avoid changing riscv_vector.h

Failures looked like this:
In file included from 
/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
  from 
/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
  from /riscv-gnu-toolchain/build/sysroot/usr/include/stdint.h:26,
  from 
/riscv-gnu-toolchain/build/lib/gcc/riscv32-unknown-linux-gnu/14.0.0/include/stdint.h:9,
  from 
/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/stdint.h:9,
  from 
/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/include/riscv_vector.h:28,
  from 
/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c:4:
/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:8:11: fatal error: 
gnu/stubs-ilp32.h: No such file or directory

Resolves these failures on rv32gcv (non-multilib):
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c (test 
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c (test for 
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c (test for 
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/partial/slp-9.c (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/pr111232.c -O3 -ftree-vectorize (test for 
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/unop/cvt-0.c (test for excess errors

[Committed] RISC-V: Test memcpy inlined on riscv_v

[Patrick O'Neill]

On 10/5/23 15:14, Jeff Law wrote:



On 10/4/23 16:55, Patrick O'Neill wrote:

Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr90263.c: Skip riscv_v targets.
* gcc.target/riscv/rvv/base/pr90263.c: New test.

OK
jeff

Committed.
Patrick

Re: [PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v

[Patrick O'Neill]

On 10/4/23 15:29, Jeff Law wrote:



On 10/4/23 16:21, Patrick O'Neill wrote:


On 10/4/23 15:14, Jeff Law wrote:



On 10/4/23 15:57, Patrick O'Neill wrote:

Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr90263.c: xfail riscv_v targets.
Or rather than XFAIL skip the test?  XFAIL kind of implies its 
something we'd like to fix.  But in this case we don't want a memcpy 
call as the inlined vector implementation is almost certainly better.

Ah. Since XFAIL notifies us if a test starts passing (via xpass) I
thought it would help us ensure the test doesn't start passing
on riscv_v. I didn't know it implied something needed to be fixed.

I'll rework it to skip riscv_v targets.

Hopefully that works.

If you wanted a test to verify that we don't go backwards and start 
emitting a memcpy, you can set up a test like


// dg-directives
#include "pr90263.c"

// dg directives for scanning

Where the scanning verifies that we don't have a call to memcpy. The 
kind of neat thing here is the dg directives in the included file are 
ignored, so you can use the same test sources in multiple ways.


Given this is kindof specific to risc-v, it might make more sense in 
the riscv directory.


Jeff


Title changed/superseded by:
https://inbox.sourceware.org/gcc-patches/20231004225527.930610-1-patr...@rivosinc.com/T/#u

Patrick

[PATCH v2] RISC-V: Test memcpy inlined on riscv_v

[Patrick O'Neill]

Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr90263.c: Skip riscv_v targets.
* gcc.target/riscv/rvv/base/pr90263.c: New test.

Signed-off-by: Patrick O'Neill 
Co-authored-by: Joern Rennecke 
---
Changes from v1:
[PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v
- Skip test rather than xfailing for riscv_v.
- Add testcase to ensure memcpy is not emitted on riscv_v.
---
 gcc/testsuite/gcc.dg/pr90263.c| 1 +
 gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c | 7 +++
 2 files changed, 8 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c

diff --git a/gcc/testsuite/gcc.dg/pr90263.c b/gcc/testsuite/gcc.dg/pr90263.c
index 3222a5331c1..831e098783b 100644
--- a/gcc/testsuite/gcc.dg/pr90263.c
+++ b/gcc/testsuite/gcc.dg/pr90263.c
@@ -2,6 +2,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
 /* { dg-require-effective-target glibc } */
+/* { dg-skip-if "riscv_v uses an inline memcpy routine" { riscv_v } }*/

 int *f (int *p, int *q, long n)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c
new file mode 100644
index 000..7308428e2c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr90263.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target glibc } */
+
+#include "../../../../gcc.dg/pr90263.c"
+
+/* { dg-final { scan-assembler-not "memcpy" { target { riscv_v } } } } */
--
2.34.1

Re: [PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v

[Patrick O'Neill]

On 10/4/23 15:14, Jeff Law wrote:



On 10/4/23 15:57, Patrick O'Neill wrote:

Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr90263.c: xfail riscv_v targets.
Or rather than XFAIL skip the test?  XFAIL kind of implies its 
something we'd like to fix.  But in this case we don't want a memcpy 
call as the inlined vector implementation is almost certainly better.

Ah. Since XFAIL notifies us if a test starts passing (via xpass) I
thought it would help us ensure the test doesn't start passing
on riscv_v. I didn't know it implied something needed to be fixed.

I'll rework it to skip riscv_v targets.

Thanks,
Patrick


You might be able to use riscv_v in a dg-skip-if directive.  Not sure.


Jeff

[PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v

[Patrick O'Neill]

Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.

gcc/testsuite/ChangeLog:

* gcc.dg/pr90263.c: xfail riscv_v targets.

Signed-off-by: Patrick O'Neill 
Co-authored-by: Joern Rennecke 
---
 gcc/testsuite/gcc.dg/pr90263.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/pr90263.c b/gcc/testsuite/gcc.dg/pr90263.c
index 3222a5331c1..13f4a85fa0f 100644
--- a/gcc/testsuite/gcc.dg/pr90263.c
+++ b/gcc/testsuite/gcc.dg/pr90263.c
@@ -9,4 +9,4 @@ int *f (int *p, int *q, long n)
 }

 /* { dg-final { scan-assembler "mempcpy" { target { i?86-*-* x86_64-*-* } } } 
} */
-/* { dg-final { scan-assembler "memcpy" { target { ! { i?86-*-* x86_64-*-* } } 
} } } */
+/* { dg-final { scan-assembler "memcpy" { target { ! { i?86-*-* x86_64-*-* } } 
xfail { riscv_v } } } } */
--
2.34.1

Re: [RISC-V]: Re: cpymem for RISCV with v extension

[Patrick O'Neill]

On 10/4/23 12:19, Joern Rennecke wrote:


On Wed, 4 Oct 2023 at 18:38, Patrick O'Neill  wrote:

Hi Joern,

I'm seeing new failures introduced by this patch
(9464e72bcc9123b619215af8cfef491772a3ebd9).

On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy

My testing didn't flag this because I used elf targets.  The
expected behaviour now is to use vector instructions for rvv.
so we shouldn't expect memcpy to appear there.  I think the
rvv case is suitably covered by the new tests, so we just
have to avoid the failure here.  Does the attached patch work for you?


Thanks for the quick response. I'm glad to hear the behavior is expected :)
The attached patch works, just needed some syntax changes:
ERROR: gcc.dg/pr90263.c: error executing dg-final: syntax error in target selector 
"target i?86-*-* x86_64-*-* riscv_v"
Diff w/ syntax changes:
diff --git a/gcc/testsuite/gcc.dg/pr90263.c b/gcc/testsuite/gcc.dg/pr90263.c
index 3222a5331c1..4044e6b1544 100644
--- a/gcc/testsuite/gcc.dg/pr90263.c
+++ b/gcc/testsuite/gcc.dg/pr90263.c
@@ -9,4 +9,4 @@ int *f (int *p, int *q, long n)
 }

 /* { dg-final { scan-assembler "mempcpy" { target { i?86-*-* x86_64-*-* } } } 
} */
-/* { dg-final { scan-assembler "memcpy" { target { ! { i?86-*-* x86_64-*-* } } 
} } } */
+/* { dg-final { scan-assembler "memcpy" { target { ! { { i?86-*-* x86_64-*-* } 
|| { riscv_v } } } } } } */

I'll send it as a patch shortly.

Patrick


FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,
-O2 -fomit-frame-pointer -finline-functions -funroll-loops

There seems to be an issue with my test setup regarding fortran, I'll
have to investigate.

Re: [RISC-V]: Re: cpymem for RISCV with v extension

[Patrick O'Neill]

Hi Joern,

I'm seeing new failures introduced by this patch 
(9464e72bcc9123b619215af8cfef491772a3ebd9).


On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,  
-O2 -fomit-frame-pointer -finline-functions -funroll-loops


Debug log for intrinsic_count.f90:
spawn riscv64-unknown-linux-gnu-run 
/scratch/tc-testing/tc-410-break/build/build-gcc-linux-stage2/gcc/testsuite/gfortran9/intrinsic_count.x

STOP 2
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,  
-O2 -fomit-frame-pointer -finline-functions -funroll-loops


It's worth noting that intrinsic_count.f90 had failures prior to this 
patch for other option combinations:

FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,  -O2
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,  
-O2 -fbounds-check
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,  
-O2 -fomit-frame-pointer -finline-functions


Thanks,
Patrick

On 10/1/23 19:43, Joern Rennecke wrote:

On Tue, 15 Aug 2023 at 15:06, Jeff Law  wrote:
  >

On 8/15/23 03:16, juzhe.zh...@rivai.ai wrote:

The new  patch looks reasonable to me now. Thanks for fixing it.

Could you append testcase after finishing test infrastructure ?
I prefer this patch with testcase after infrastructure.

So let's call this an ACK, but ask that Joern not commit until the
testsuite bits are in place.

Beyond the adding of tests, the patch needed some changes because of the
Refactoring of emit_{vlmax,nonvlmax}_xxx functions .
Attached is the committed version.

[RFC gcc13 backport 1/3] RISC-V: Add Ztso atomic mappings

[Patrick O'Neill]

The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized atomic mappings than the RVWMO mappings.

This PR implements the Ztso psABI mappings[1].

[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391

2023-08-08 Patrick O'Neill 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a' extension.
* config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
(TARGET_ZTSO): New target.
* config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add
Ztso case.
(riscv_memmodel_needs_amo_release): Add Ztso case.
(riscv_print_operand): Add Ztso case for LR/SC annotations.
* config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md.
* config/riscv/riscv.opt: Add Ztso target variable.
* config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or
Ztso specific insn.
(atomic_load): Expand to RVWMO or Ztso specific insn.
(atomic_store): Expand to RVWMO or Ztso specific insn.
* config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO
specific load/store/fence mappings.
* config/riscv/sync-ztso.md: New file. Seperate out Ztso
specific load/store/fence mappings.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test.
* gcc.target/riscv/amo-table-ztso-fence-1.c: New test.
* gcc.target/riscv/amo-table-ztso-fence-2.c: New test.
* gcc.target/riscv/amo-table-ztso-fence-3.c: New test.
* gcc.target/riscv/amo-table-ztso-fence-4.c: New test.
* gcc.target/riscv/amo-table-ztso-fence-5.c: New test.
* gcc.target/riscv/amo-table-ztso-load-1.c: New test.
* gcc.target/riscv/amo-table-ztso-load-2.c: New test.
* gcc.target/riscv/amo-table-ztso-load-3.c: New test.
* gcc.target/riscv/amo-table-ztso-store-1.c: New test.
* gcc.target/riscv/amo-table-ztso-store-2.c: New test.
* gcc.target/riscv/amo-table-ztso-store-3.c: New test.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test.

Signed-off-by: Patrick O'Neill 
---
 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/riscv-opts.h |   4 +
 gcc/config/riscv/riscv.cc |  20 +++-
 gcc/config/riscv/riscv.md |   2 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/config/riscv/sync-rvwmo.md|  96 +++
 gcc/config/riscv/sync-ztso.md |  80 +
 gcc/config/riscv/sync.md  | 111 ++
 .../riscv/amo-table-ztso-amo-add-1.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-2.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-3.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-4.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-5.c  |  15 +++
 .../riscv/amo-table-ztso-compare-exchange-1.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-2.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-3.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-4.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-5.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-6.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-7.c |  10 ++
 .../gcc.target/riscv/amo-table-ztso-fence-1.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-2.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-3.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-4.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-5.c |  15 +++
 .../gcc.target/riscv/amo-table-ztso-load-1.c  |  16 +++
 .../gcc.target/riscv/amo-table-ztso-load-2.c  |  16 +++
 .../gcc.target/riscv/amo-table-ztso-load-3.c  |  17 +++
 .../gcc.target/riscv/amo-table-ztso-store-1.c |  16

[RFC gcc13 backport 2/3] RISC-V: Specify -mabi for ztso testcases

[Patrick O'Neill]

On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'

2023-08-11 Patrick O'Neill 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add -mabi=lp64d
to dg-options.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-fence-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-store-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.

Signed-off-by: Patrick O'Neill 
---
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c   | 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-1.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-2.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-3.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-4.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-5.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-6.c| 2 +-
 .../gcc.target/riscv/amo-table-ztso-compare-exchange-7.c| 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-5.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-1.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-2.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-3.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-3.c | 2 +-
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c | 2 +-
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c | 2 +-
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c | 2 +-
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c | 2 +-
 .../gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c | 2 +-
 28 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index a7097e9aab9..a88d08eb3f4 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-options "-march=rv64id_ztso -O3" } */
+/* { dg-options "-march=rv64id_ztso -mabi=lp64d -O3" } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c 
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index 8e993903439..ebd240f9dd2 100644
--- a/gcc/tes

[RFC gcc13 backport 3/3] [RISCV][committed] Remove spurious newline in ztso sequence

[Patrick O'Neill]

From: Jeff Law 

amo-table-ztso-load-3 the coordination branch after merging up the Ztso changes
due to a spurious newline in the output causing scan-function-body to fail.
There's probably an over-zealous .* or similar regexp in the framework.  I
didn't see it in a quick scan, but could have easily missed it.

Regardless, fixing the extraneous newline is easy :-)

gcc/
* config/riscv/sync-ztso.md (atomic_load_ztso): Avoid extraenous
newline.

Signed-off-by: Patrick O'Neill 
---
 gcc/config/riscv/sync-ztso.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 91c2a48c069..ed94471b96b 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -52,7 +52,7 @@
 
 if (model == MEMMODEL_SEQ_CST)
   return "fence\trw,rw\;"
-"l\t%0,%1\;";
+"l\t%0,%1";
 else
   return "l\t%0,%1";
   }
@@ -77,4 +77,4 @@
   return "s\t%z1,%0";
   }
   [(set_attr "type" "atomic")
-   (set (attr "length") (const_int 8))])
\ No newline at end of file
+   (set (attr "length") (const_int 8))])
-- 
2.34.1

[RFC gcc13 backport 0/3] Add Ztso atomic mappings

[Patrick O'Neill]

I vaugely recall some discussion about backporting the Ztso mappings
along with the RVWMO mappings. Now that the RVWMO mappings have been
backported for 13.3, is there interest in also backporting the Ztso
mappings?

Tested using for regressions using rv32gc/rv64gc glibc.

Jeff Law (1):
  [RISCV][committed] Remove spurious newline in ztso sequence

Patrick O'Neill (2):
  RISC-V: Add Ztso atomic mappings
  RISC-V: Specify -mabi for ztso testcases

 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/riscv-opts.h |   4 +
 gcc/config/riscv/riscv.cc |  20 +++-
 gcc/config/riscv/riscv.md |   2 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/config/riscv/sync-rvwmo.md|  96 +++
 gcc/config/riscv/sync-ztso.md |  80 +
 gcc/config/riscv/sync.md  | 111 ++
 .../riscv/amo-table-ztso-amo-add-1.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-2.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-3.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-4.c  |  15 +++
 .../riscv/amo-table-ztso-amo-add-5.c  |  15 +++
 .../riscv/amo-table-ztso-compare-exchange-1.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-2.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-3.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-4.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-5.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-6.c |  10 ++
 .../riscv/amo-table-ztso-compare-exchange-7.c |  10 ++
 .../gcc.target/riscv/amo-table-ztso-fence-1.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-2.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-3.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-4.c |  14 +++
 .../gcc.target/riscv/amo-table-ztso-fence-5.c |  15 +++
 .../gcc.target/riscv/amo-table-ztso-load-1.c  |  16 +++
 .../gcc.target/riscv/amo-table-ztso-load-2.c  |  16 +++
 .../gcc.target/riscv/amo-table-ztso-load-3.c  |  17 +++
 .../gcc.target/riscv/amo-table-ztso-store-1.c |  16 +++
 .../gcc.target/riscv/amo-table-ztso-store-2.c |  16 +++
 .../gcc.target/riscv/amo-table-ztso-store-3.c |  17 +++
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |  10 ++
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |  10 ++
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |  10 ++
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |  10 ++
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |  10 ++
 36 files changed, 612 insertions(+), 74 deletions(-)
 create mode 100644 gcc/config/riscv/sync-rvwmo.md
 create mode 100644 gcc/config/riscv/sync-ztso.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-fence-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-load-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-ztso-store-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c

--
2.34.1

[Committed] RISC-V: Unescape chars in pr111566.f90 test

[Patrick O'Neill]

On 10/3/23 14:55, Jeff Law wrote:



On 10/3/23 14:19, Patrick O'Neill wrote:

Some characters are escaped which causes the testcase to fail. This
patch restores the original characters.

Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/fortran/pr111566.f90: Restore escaped
characters.

LOL.  Yea, this is OK.

jeff


Committed.

Patrick

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

[Patrick O'Neill]

On 10/2/23 06:57, Kito Cheng wrote:


On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill  wrote:

stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.

Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075.

gcc/ChangeLog:

  * config/riscv/riscv_vector.h (__RISCV_VECTOR_H): Replace
  stdint.h with stdint-gcc.h

I don't think this will work when testing an installed compiler which I do.

Thanks,
Andrew

In the riscv target testsuite (gcc.target/riscv) all occurrences of
#include  are currently constrained to the rvv/ subdirectory.
All non-vector tests use #include  rather than
#include . Have you encountered any issues when testing
installations with non-vector tests?

I think the concern is to replace stdint.h with stdint-gcc.h for riscv_vector.h,
that means users MAY include stdint-gcc.h *AND* stdint.h, stdint.h the later
one generally is provided by libc, and stdint-gcc.h typically are not included.

Other than the changes in "riscv_vector.h", everything else looks fine to me.


Ah okay, I'll retest and send a v2 that omits the riscv_vector.h change. 
Thanks, Patrick

[PATCH] RISC-V: Unescape chars in pr111566.f90 test

[Patrick O'Neill]

Some characters are escaped which causes the testcase to fail. This
patch restores the original characters.

Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/fortran/pr111566.f90: Restore escaped
characters.

Signed-off-by: Patrick O'Neill 
---
 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
index 265e913b299..2e30dc9bfaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
@@ -1,11 +1,11 @@
 ! { dg-do compile }
-! { dg-options -march=rv64gcv -mabi=lp64d -Ofast 
-fallow-argument-mismatch -fmax-stack-var-size=65536 -S  -std=legacy -w }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch 
-fmax-stack-var-size=65536 -S  -std=legacy -w" }

 module a
   integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
 end module a
 module b
-  use a,  c = shr_kind_r8
+  use a,  c => shr_kind_r8
 contains
   subroutine d(cg , km, i1, i2)
 real (c) ch(i2,km)
@@ -22,7 +22,7 @@ contains
 enddo
 if ( cq == 0 ) then
do i=i1,i2
-  if( cr =  cs ) then
+  if( cr <=  cs ) then
  cg= sign( min(ct,   cg),  cg)
   endif
enddo
--
2.34.1

[Committed] RISC-V: Use safe_grow_cleared for vector info [PR111469]

[Patrick O'Neill]

Committed. Thanks Juzhe!

I had to adjust the changelog's PR formatting to get the pre-commit 
hooks to accept it.

Here's the committed patch:

From f446cf5d58568e406cc81f434a63b3045942e9a9 Mon Sep 17 00:00:00 2001
From: Patrick O'Neill 
Date: Sat, 30 Sep 2023 15:50:11 -0700
Subject: [PATCH] RISC-V: Use safe_grow_cleared for vector info [PR111649]

Resolves a riscv*-*-* bootstrap failure due to a newly-turned-on assert.

2023-09-30  Jakub Jelinek 

gcc/ChangeLog:

    PR target/111649

    * config/riscv/riscv-vsetvl.cc 
(vector_infos_manager::vector_infos_manager):

    Replace safe_grow with safe_grow_cleared.
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649

Fix authored by Jakub Jelinek.

Tested for regressions using multilib riscv glibc rv32gcv, rv64gcv
---
 gcc/config/riscv/riscv-vsetvl.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
b/gcc/config/riscv/riscv-vsetvl.cc

index af8c31d873c..4b06d93e7f9 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2417,8 +2417,8 @@ vector_infos_manager::vector_infos_manager ()
   vector_antin = nullptr;
   vector_antout = nullptr;
   vector_earliest = nullptr;
-  vector_insn_infos.safe_grow (get_max_uid ());
-  vector_block_infos.safe_grow (last_basic_block_for_fn (cfun));
+  vector_insn_infos.safe_grow_cleared (get_max_uid ());
+  vector_block_infos.safe_grow_cleared (last_basic_block_for_fn (cfun));
   if (!optimize)
 {
   basic_block cfg_bb;
--
2.34.1

On 9/30/23 16:03, 钟居哲 wrote:

LGTM.


juzhe.zh...@rivai.ai

*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-01 07:00
*To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong
<mailto:juzhe.zh...@rivai.ai>
*CC:* jakub <mailto:ja...@redhat.com>; pinskia
<mailto:pins...@gcc.gnu.org>; JeffreyALaw
<mailto:jeffreya...@gmail.com>; gnu-toolchain
<mailto:gnu-toolch...@rivosinc.com>; Patrick O'Neill
<mailto:patr...@rivosinc.com>
*Subject:* [PATCH] RISC-V: Use safe_grow_cleared for vector info
[PR111469]
Resolves a riscv*-*-* bootstrap failure due to a newly-turned-on
assert.
2023-09-30  Jakub Jelinek 
PR target/111649
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager):
Replace safe_grow with safe_grow_cleared.
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649
Fix authored by Jakub Jelinek.
Tested for regressions using multilib riscv glibc rv32gcv, rv64gcv
---
gcc/config/riscv/riscv-vsetvl.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc
b/gcc/config/riscv/riscv-vsetvl.cc
index af8c31d873c..4b06d93e7f9 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2417,8 +2417,8 @@ vector_infos_manager::vector_infos_manager ()
   vector_antin = nullptr;
   vector_antout = nullptr;
   vector_earliest = nullptr;
-  vector_insn_infos.safe_grow (get_max_uid ());
-  vector_block_infos.safe_grow (last_basic_block_for_fn (cfun));
+  vector_insn_infos.safe_grow_cleared (get_max_uid ());
+  vector_block_infos.safe_grow_cleared (last_basic_block_for_fn
(cfun));
   if (!optimize)
 {
   basic_block cfg_bb;
--
2.34.1

[PATCH] RISC-V: Use safe_grow_cleared for vector info [PR111469]

[Patrick O'Neill]

Resolves a riscv*-*-* bootstrap failure due to a newly-turned-on assert.

2023-09-30  Jakub Jelinek  

PR target/111649

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc 
(vector_infos_manager::vector_infos_manager):
Replace safe_grow with safe_grow_cleared.
---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649

Fix authored by Jakub Jelinek.

Tested for regressions using multilib riscv glibc rv32gcv, rv64gcv
---
 gcc/config/riscv/riscv-vsetvl.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index af8c31d873c..4b06d93e7f9 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2417,8 +2417,8 @@ vector_infos_manager::vector_infos_manager ()
   vector_antin = nullptr;
   vector_antout = nullptr;
   vector_earliest = nullptr;
-  vector_insn_infos.safe_grow (get_max_uid ());
-  vector_block_infos.safe_grow (last_basic_block_for_fn (cfun));
+  vector_insn_infos.safe_grow_cleared (get_max_uid ());
+  vector_block_infos.safe_grow_cleared (last_basic_block_for_fn (cfun));
   if (!optimize)
 {
   basic_block cfg_bb;
--
2.34.1

Re: [PATCH] vec.h: Guard most of static assertions for GCC >= 5

[Patrick O'Neill]

Hi Jakub,

A follow-up commit of yours (9d249b7e31e) is causing bootstrap failures 
for riscv*-*-* targets.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649

Patrick

On 9/29/23 03:42, Jakub Jelinek wrote:

Hi!

As reported by Jonathan on IRC, my vec.h patch broke build with GCC 4.8.x
or 4.9.x as system compiler, e.g. on CFarm.
The problem is that while all of
std::is_trivially_{destructible,copyable,default_constructible} traits
are in C++, only std::is_trivially_destructible has been implemented in GCC
4.8, the latter two were added only in GCC 5.
Only std::is_trivially_destructible is the really important one though,
which is used to decide what pop returns and whether to invoke the
destructors or not.  The rest are solely used in static_asserts and as such
I think it is acceptable if we don't assert those when built with GCC 4.8
or 4.9, anybody doing bootstrap from those system compilers or doing builds
with newer GCC will catch that.

So, the following patch guards those for 5+.
If we switch to C++14 later on and start requiring newer version of system
GCC as well (do we require GCC >= 5 which claims the last C++14 language
features, or what provides all C++14 library features, or GCC >= 6 which
uses -std=c++14 by default?), this patch then can be reverted.

Ok for trunk?

2023-09-29  Jakub Jelinek  

* vec.h (quick_insert, ordered_remove, unordered_remove,
block_remove, qsort, sort, stablesort, quick_grow): Guard
std::is_trivially_{copyable,default_constructible} and
vec_detail::is_trivially_copyable_or_pair static assertions
with GCC_VERSION >= 5000.
(vec_detail::is_trivially_copyable_or_pair): Guard definition
with GCC_VERSION >= 5000.

--- gcc/vec.h.jj2023-09-29 10:59:09.830551963 +0200
+++ gcc/vec.h   2023-09-29 12:29:32.676428677 +0200
@@ -1086,7 +1086,12 @@ vec::quick_insert (unsig
  {
gcc_checking_assert (length () < allocated ());
gcc_checking_assert (ix <= length ());
+#if GCC_VERSION >= 5000
+  /* GCC 4.8 and 4.9 only implement std::is_trivially_destructible,
+ but not std::is_trivially_copyable nor
+ std::is_trivially_default_constructible.  */
static_assert (std::is_trivially_copyable ::value, "");
+#endif
T *slot =  ()[ix];
memmove (slot + 1, slot, (m_vecpfx.m_num++ - ix) * sizeof (T));
*slot = obj;
@@ -1102,7 +1107,9 @@ inline void
  vec::ordered_remove (unsigned ix)
  {
gcc_checking_assert (ix < length ());
+#if GCC_VERSION >= 5000
static_assert (std::is_trivially_copyable ::value, "");
+#endif
T *slot =  ()[ix];
memmove (slot, slot + 1, (--m_vecpfx.m_num - ix) * sizeof (T));
  }
@@ -1150,7 +1157,9 @@ inline void
  vec::unordered_remove (unsigned ix)
  {
gcc_checking_assert (ix < length ());
+#if GCC_VERSION >= 5000
static_assert (std::is_trivially_copyable ::value, "");
+#endif
T *p = address ();
p[ix] = p[--m_vecpfx.m_num];
  }
@@ -1164,13 +1173,16 @@ inline void
  vec::block_remove (unsigned ix, unsigned len)
  {
gcc_checking_assert (ix + len <= length ());
+#if GCC_VERSION >= 5000
static_assert (std::is_trivially_copyable ::value, "");
+#endif
T *slot =  ()[ix];
m_vecpfx.m_num -= len;
memmove (slot, slot + len, (m_vecpfx.m_num - ix) * sizeof (T));
  }
  
  
+#if GCC_VERSION >= 5000

  namespace vec_detail
  {
/* gcc_{qsort,qsort_r,stablesort_r} implementation under the hood
@@ -1189,6 +1201,7 @@ namespace vec_detail
: std::integral_constant::value
  && std::is_trivially_copyable::value> { };
  }
+#endif
  
  /* Sort the contents of this vector with qsort.  CMP is the comparison

 function to pass to qsort.  */
@@ -1197,7 +1210,9 @@ template
  inline void
  vec::qsort (int (*cmp) (const void *, const void *))
  {
+#if GCC_VERSION >= 5000
static_assert (vec_detail::is_trivially_copyable_or_pair ::value, "");
+#endif
if (length () > 1)
  gcc_qsort (address (), length (), sizeof (T), cmp);
  }
@@ -1210,7 +1225,9 @@ inline void
  vec::sort (int (*cmp) (const void *, const void *, void *),
   void *data)
  {
+#if GCC_VERSION >= 5000
static_assert (vec_detail::is_trivially_copyable_or_pair ::value, "");
+#endif
if (length () > 1)
  gcc_sort_r (address (), length (), sizeof (T), cmp, data);
  }
@@ -1223,7 +1240,9 @@ inline void
  vec::stablesort (int (*cmp) (const void *, const void *,
 void *), void *data)
  {
+#if GCC_VERSION >= 5000
static_assert (vec_detail::is_trivially_copyable_or_pair ::value, "");
+#endif
if (length () > 1)
  gcc_stablesort_r (address (), length (), sizeof (T), cmp, data);
  }
@@ -1396,7 +1415,9 @@ inline void
  vec::quick_grow (unsigned len)
  {
gcc_checking_assert (length () <= len && len <= m_vecpfx.m_alloc);
+#if GCC_VERSION >= 5000
  //  static_assert (std::is_trivially_default_constructible ::value, "");
+#endif
m_vecpfx.m_num = len;
  }
  


Jakub