date:20161026

[gem5-dev] changeset in gem5: ruby: Allow multiple outstanding DMA requests

2016-10-26 Thread Michael LeBeane

changeset 0bf388858d1e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0bf388858d1e
description:
ruby: Allow multiple outstanding DMA requests
DMA sequencers and protocols can currently only issue one DMA access at
a time. This patch implements the necessary functionality to support
multiple outstanding DMA requests in Ruby.

diffstat:

 src/mem/protocol/MESI_Two_Level-dma.sm  |  84 
 src/mem/protocol/MI_example-dma.sm  |  86 +++-
 src/mem/protocol/MOESI_CMP_directory-dma.sm |   4 +-
 src/mem/protocol/MOESI_CMP_token-dma.sm |  84 +++-
 src/mem/protocol/MOESI_hammer-dma.sm|  86 +++-
 src/mem/protocol/RubySlicc_Types.sm |   4 +-
 src/mem/ruby/system/DMASequencer.cc |  84 +++-
 src/mem/ruby/system/DMASequencer.hh |  23 +--
 src/mem/ruby/system/Sequencer.py|   1 +
 9 files changed, 360 insertions(+), 96 deletions(-)

diffs (truncated from 859 to 300 lines):

diff -r 5e7599457b97 -r 0bf388858d1e src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.smWed Oct 26 22:48:33 2016 -0400
+++ b/src/mem/protocol/MESI_Two_Level-dma.smWed Oct 26 22:48:37 2016 -0400
@@ -50,15 +50,38 @@
 Ack,  desc="DMA write to memory completed";
   }
 
-  State cur_state;
+  structure(TBE, desc="...") {
+State TBEState,desc="Transient state";
+DataBlock DataBlk, desc="Data";
+  }
+
+  structure(TBETable, external = "yes") {
+TBE lookup(Addr);
+void allocate(Addr);
+void deallocate(Addr);
+bool isPresent(Addr);
+  }
+
+  void set_tbe(TBE b);
+  void unset_tbe();
+  void wakeUpAllBuffers();
+
+  TBETable TBEs, template="", constructor="m_number_of_TBEs";
+
   Tick clockEdge();
 
-  State getState(Addr addr) {
-return cur_state;
+  State getState(TBE tbe, Addr addr) {
+if (is_valid(tbe)) {
+return tbe.TBEState;
+} else {
+return State:READY;
+}
   }
 
-  void setState(Addr addr, State state) {
-cur_state := state;
+  void setState(TBE tbe, Addr addr, State state) {
+if (is_valid(tbe)) {
+tbe.TBEState := state;
+}
   }
 
   AccessPermission getAccessPermission(Addr addr) {
@@ -82,9 +105,9 @@
 if (dmaRequestQueue_in.isReady(clockEdge())) {
   peek(dmaRequestQueue_in, SequencerMsg) {
 if (in_msg.Type == SequencerRequestType:LD ) {
-  trigger(Event:ReadRequest, in_msg.LineAddress);
+  trigger(Event:ReadRequest, in_msg.LineAddress, 
TBEs[in_msg.LineAddress]);
 } else if (in_msg.Type == SequencerRequestType:ST) {
-  trigger(Event:WriteRequest, in_msg.LineAddress);
+  trigger(Event:WriteRequest, in_msg.LineAddress, 
TBEs[in_msg.LineAddress]);
 } else {
   error("Invalid request type");
 }
@@ -96,9 +119,11 @@
 if (dmaResponseQueue_in.isReady(clockEdge())) {
   peek( dmaResponseQueue_in, ResponseMsg) {
 if (in_msg.Type == CoherenceResponseType:ACK) {
-  trigger(Event:Ack, makeLineAddress(in_msg.addr));
+  trigger(Event:Ack, makeLineAddress(in_msg.addr),
+  TBEs[makeLineAddress(in_msg.addr)]);
 } else if (in_msg.Type == CoherenceResponseType:DATA) {
-  trigger(Event:Data, makeLineAddress(in_msg.addr));
+  trigger(Event:Data, makeLineAddress(in_msg.addr),
+  TBEs[makeLineAddress(in_msg.addr)]);
 } else {
   error("Invalid response type");
 }
@@ -133,15 +158,30 @@
   }
 
   action(a_ackCallback, "a", desc="Notify dma controller that write request 
completed") {
-dma_sequencer.ackCallback();
+dma_sequencer.ackCallback(address);
   }
 
   action(d_dataCallback, "d", desc="Write data to dma sequencer") {
-peek (dmaResponseQueue_in, ResponseMsg) {
-  dma_sequencer.dataCallback(in_msg.DataBlk);
+dma_sequencer.dataCallback(tbe.DataBlk, address);
+  }
+
+  action(t_updateTBEData, "t", desc="Update TBE Data") {
+assert(is_valid(tbe));
+peek( dmaResponseQueue_in, ResponseMsg) {
+tbe.DataBlk := in_msg.DataBlk;
 }
   }
 
+  action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+TBEs.allocate(address);
+set_tbe(TBEs[address]);
+  }
+
+  action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+TBEs.deallocate(address);
+unset_tbe();
+  }
+
   action(p_popRequestQueue, "p", desc="Pop request queue") {
 dmaRequestQueue_in.dequeue(clockEdge());
   }
@@ -150,23 +190,43 @@
 dmaResponseQueue_in.dequeue(clockEdge());
   }
 
+  action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+stall_and_wait(dmaRequestQueue_in, address);
+  }
+
+  action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+wakeUpAllBuffers();
+  }
+
   transition(READY, ReadRequest, BUSY_RD) {
+v_allocateTBE;
 s_sendReadRequest;

[gem5-dev] changeset in gem5: gpu-compute, arch: add some methods to the ba...

2016-10-26 Thread Tony Gutierrez

changeset 3027d6c34fa4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3027d6c34fa4
description:
gpu-compute, arch: add some methods to the base inst classes for ISA 
support

diffstat:

 src/arch/hsail/insts/gpu_static_inst.hh |  1 +
 src/gpu-compute/gpu_static_inst.hh  |  9 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diffs (37 lines):

diff -r 9d19bb965564 -r 3027d6c34fa4 src/arch/hsail/insts/gpu_static_inst.hh
--- a/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:46:58 2016 -0400
+++ b/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:47:01 2016 -0400
@@ -56,6 +56,7 @@
 void generateDisassembly();
 const std::string ();
 uint32_t instSize() { return 4; }
+bool isValid() const override { return true; }
 
   protected:
 HsailCode *hsailCode;
diff -r 9d19bb965564 -r 3027d6c34fa4 src/gpu-compute/gpu_static_inst.hh
--- a/src/gpu-compute/gpu_static_inst.hhWed Oct 26 22:46:58 2016 -0400
+++ b/src/gpu-compute/gpu_static_inst.hhWed Oct 26 22:47:01 2016 -0400
@@ -84,6 +84,8 @@
 virtual int numDstRegOperands() = 0;
 virtual int numSrcRegOperands() = 0;
 
+virtual bool isValid() const = 0;
+
 /*
  * Most instructions (including all HSAIL instructions)
  * are vector ops, so _scalarOp will be false by default.
@@ -109,6 +111,13 @@
 fatal("calling initiateAcc() on a non-memory instruction.\n");
 }
 
+// only used for memory instructions
+virtual void
+completeAcc(GPUDynInstPtr gpuDynInst)
+{
+fatal("calling completeAcc() on a non-memory instruction.\n");
+}
+
 virtual uint32_t getTargetPc() { return 0; }
 
 /**
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[gem5-dev] changeset in gem5: ruby: make a RequestDesc class instead of std...

2016-10-26 Thread Tony Gutierrez

changeset 9d19bb965564 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9d19bb965564
description:
ruby: make a RequestDesc class instead of std::pair

the RequestDesc was previously implemented as a std::pair, which made
the implementation overly complex and error prone. here we encapsulate 
the
packet, primary, and secondary types all in a single data structure with
all members properly intialized in a ctor

diffstat:

 src/mem/ruby/system/GPUCoalescer.cc |  28 
 src/mem/ruby/system/GPUCoalescer.hh |  22 +++---
 2 files changed, 31 insertions(+), 19 deletions(-)

diffs (129 lines):

diff -r 725fef71f376 -r 9d19bb965564 src/mem/ruby/system/GPUCoalescer.cc
--- a/src/mem/ruby/system/GPUCoalescer.cc   Wed Oct 26 14:50:54 2016 -0400
+++ b/src/mem/ruby/system/GPUCoalescer.cc   Wed Oct 26 22:46:58 2016 -0400
@@ -625,9 +625,8 @@
 int len = reqCoalescer[request_line_address].size();
 std::vector mylist;
 for (int i = 0; i < len; ++i) {
-PacketPtr pkt = reqCoalescer[request_line_address][i].first;
-assert(type ==
-   reqCoalescer[request_line_address][i].second[PrimaryType]);
+PacketPtr pkt = reqCoalescer[request_line_address][i].pkt;
+assert(type == reqCoalescer[request_line_address][i].primaryType);
 request_address = pkt->getAddr();
 request_line_address = makeLineAddress(pkt->getAddr());
 if (pkt->getPtr()) {
@@ -848,25 +847,22 @@
 // let us see if we can coalesce this request with the previous
 // requests from this cycle
 } else if (primary_type !=
-   reqCoalescer[line_addr][0].second[PrimaryType]) {
+   reqCoalescer[line_addr][0].primaryType) {
 // can't coalesce loads, stores and atomics!
 return RequestStatus_Aliased;
 } else if (pkt->req->isLockedRMW() ||
-   reqCoalescer[line_addr][0].first->req->isLockedRMW()) {
+   reqCoalescer[line_addr][0].pkt->req->isLockedRMW()) {
 // can't coalesce locked accesses, but can coalesce atomics!
 return RequestStatus_Aliased;
 } else if (pkt->req->hasContextId() && pkt->req->isRelease() &&
pkt->req->contextId() !=
-   reqCoalescer[line_addr][0].first->req->contextId()) {
+   reqCoalescer[line_addr][0].pkt->req->contextId()) {
 // can't coalesce releases from different wavefronts
 return RequestStatus_Aliased;
 }
 
 // in addition to the packet, we need to save both request types
-reqCoalescer[line_addr].push_back(
-RequestDesc(pkt, std::vector()) );
-reqCoalescer[line_addr].back().second.push_back(primary_type);
-reqCoalescer[line_addr].back().second.push_back(secondary_type);
+reqCoalescer[line_addr].emplace_back(pkt, primary_type, secondary_type);
 if (!issueEvent.scheduled())
 schedule(issueEvent, curTick());
 // TODO: issue hardware prefetches here
@@ -910,7 +906,7 @@
 std::vector< std::pair > atomicOps;
 uint32_t tableSize = reqCoalescer[line_addr].size();
 for (int i = 0; i < tableSize; i++) {
-PacketPtr tmpPkt = reqCoalescer[line_addr][i].first;
+PacketPtr tmpPkt = reqCoalescer[line_addr][i].pkt;
 uint32_t tmpOffset = (tmpPkt->getAddr()) - line_addr;
 uint32_t tmpSize = tmpPkt->getSize();
 if (tmpPkt->isAtomicOp()) {
@@ -1020,12 +1016,12 @@
 // can be coalesced with the first request. So, only
 // one request is issued per cacheline.
 RequestDesc info = reqCoalescer[newRequests[i]][0];
-PacketPtr pkt = info.first;
+PacketPtr pkt = info.pkt;
 DPRINTF(GPUCoalescer, "Completing for newReq %d: paddr %#x\n",
 i, pkt->req->getPaddr());
 // Insert this request to the read/writeRequestTables. These tables
 // are used to track aliased requests in makeRequest subroutine
-bool found = insertRequest(pkt, info.second[PrimaryType]);
+bool found = insertRequest(pkt, info.primaryType);
 
 if (found) {
 panic("GPUCoalescer::makeRequest should never be called if the "
@@ -1033,7 +1029,7 @@
 }
 
 // Issue request to ruby subsystem
-issueRequest(pkt, info.second[SecondaryType]);
+issueRequest(pkt, info.secondaryType);
 }
 newRequests.clear();
 
@@ -1107,9 +1103,9 @@
 int len = reqCoalescer[request_line_address].size();
 std::vector mylist;
 for (int i = 0; i < len; ++i) {
-PacketPtr pkt = reqCoalescer[request_line_address][i].first;
+PacketPtr pkt = reqCoalescer[request_line_address][i].pkt;
 assert(srequest->m_type ==
-   reqCoalescer[request_line_address][i].second[PrimaryType]);
+   reqCoalescer[request_line_address][i].primaryType);
 request_address = (pkt->getAddr());

[gem5-dev] changeset in gem5: hsail, gpu-compute: remove doGm/SmReturn add ...

2016-10-26 Thread Tony Gutierrez

changeset bc1f702c25b9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bc1f702c25b9
description:
hsail, gpu-compute: remove doGm/SmReturn add completeAcc

we are removing doGmReturn from the GM pipe, and adding completeAcc()
implementations for the HSAIL mem ops. the behavior in doGmReturn is
dependent on HSAIL and HSAIL mem ops, however the completion phase
of memory ops in machine ISA can be very different, even amongst 
individual
machine ISA mem ops. so we remove this functionality from the pipeline 
and
allow it to be implemented by the individual instructions.

diffstat:

 src/arch/hsail/insts/mem.hh   |  140 +++
 src/gpu-compute/global_memory_pipeline.cc |  153 +++--
 src/gpu-compute/global_memory_pipeline.hh |8 +-
 src/gpu-compute/gpu_dyn_inst.cc   |6 +
 src/gpu-compute/gpu_dyn_inst.hh   |4 +
 src/gpu-compute/local_memory_pipeline.cc  |  126 +---
 src/gpu-compute/local_memory_pipeline.hh  |8 +-
 7 files changed, 225 insertions(+), 220 deletions(-)

diffs (truncated from 589 to 300 lines):

diff -r e772fdcd3809 -r bc1f702c25b9 src/arch/hsail/insts/mem.hh
--- a/src/arch/hsail/insts/mem.hh   Wed Oct 26 22:47:11 2016 -0400
+++ b/src/arch/hsail/insts/mem.hh   Wed Oct 26 22:47:19 2016 -0400
@@ -36,9 +36,12 @@
 #ifndef __ARCH_HSAIL_INSTS_MEM_HH__
 #define __ARCH_HSAIL_INSTS_MEM_HH__
 
+#include 
+
 #include "arch/hsail/insts/decl.hh"
 #include "arch/hsail/insts/gpu_static_inst.hh"
 #include "arch/hsail/operand.hh"
+#include "gpu-compute/compute_unit.hh"
 
 namespace HsailISA
 {
@@ -491,6 +494,86 @@
 gpuDynInst->updateStats();
 }
 
+void
+completeAcc(GPUDynInstPtr gpuDynInst) override
+{
+typedef typename MemDataType::CType c1;
+
+constexpr bool is_vt_32 = DestDataType::vgprType == VT_32;
+
+/**
+  * this code essentially replaces the long if-else chain
+  * that was in used GlobalMemPipeline::exec() to infer the
+  * size (single/double) and type (floating point/integer) of
+  * the destination register. this is needed for load
+  * instructions because the loaded value and the
+  * destination type can be of different sizes, and we also
+  * need to know if the value we're writing back is floating
+  * point and signed/unsigned, so we can properly cast the
+  * writeback value
+  */
+typedef typename std::conditional::type>::type,
+typename std::conditional::type>::type>::type c0;
+
+
+Wavefront *w = gpuDynInst->wavefront();
+
+std::vector regVec;
+// iterate over number of destination register operands since
+// this is a load
+for (int k = 0; k < num_dest_operands; ++k) {
+assert((sizeof(c1) * num_dest_operands)
+   <= MAX_WIDTH_FOR_MEM_INST);
+
+int dst = this->dest.regIndex() + k;
+if (num_dest_operands > MAX_REGS_FOR_NON_VEC_MEM_INST)
+dst = dest_vect[k].regIndex();
+// virtual->physical VGPR mapping
+int physVgpr = w->remap(dst, sizeof(c0), 1);
+// save the physical VGPR index
+regVec.push_back(physVgpr);
+
+c1 *p1 =
+&((c1*)gpuDynInst->d_data)[k * w->computeUnit->wfSize()];
+
+for (int i = 0; i < w->computeUnit->wfSize(); ++i) {
+if (gpuDynInst->exec_mask[i]) {
+DPRINTF(GPUReg, "CU%d, WF[%d][%d], lane %d: "
+"$%s%d <- %d global ld done (src = wavefront "
+"ld inst)\n", w->computeUnit->cu_id, w->simdId,
+w->wfSlotId, i, sizeof(c0) == 4 ? "s" : "d",
+dst, *p1);
+// write the value into the physical VGPR. This is a
+// purely functional operation. No timing is modeled.
+w->computeUnit->vrf[w->simdId]->write(physVgpr,
+*p1, i);
+}
+++p1;
+}
+}
+
+// Schedule the write operation of the load data on the VRF.
+// This simply models the timing aspect of the VRF write operation.
+

[gem5-dev] changeset in gem5: gpu-compute, hsail: call discardFetch() from ...

2016-10-26 Thread Tony Gutierrez

changeset c3b4d57a15c5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c3b4d57a15c5
description:
gpu-compute, hsail: call discardFetch() from the WF

because every taken branch causes fetch to be discarded, we move the 
call
to the WF to avoid to have to call it from each and every branch 
instruction
type.

diffstat:

 src/arch/hsail/insts/branch.hh |  3 ---
 src/gpu-compute/wavefront.cc   |  2 ++
 2 files changed, 2 insertions(+), 3 deletions(-)

diffs (39 lines):

diff -r bc1f702c25b9 -r c3b4d57a15c5 src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:19 2016 -0400
+++ b/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:27 2016 -0400
@@ -133,7 +133,6 @@
 // Rpc and execution mask remain the same
 w->pc(getTargetPc());
 }
-w->discardFetch();
 }
 
 class BrnDirectInst : public BrnInstBase
@@ -293,7 +292,6 @@
 w->pushToReconvergenceStack(true_pc, rpc, true_mask);
 }
 assert(w->pc() != curr_pc);
-w->discardFetch();
 }
 
 
@@ -405,7 +403,6 @@
 // Rpc and execution mask remain the same
 w->pc(getTargetPc());
 }
-w->discardFetch();
 }
 
 class BrDirectInst : public BrInstBase
diff -r bc1f702c25b9 -r c3b4d57a15c5 src/gpu-compute/wavefront.cc
--- a/src/gpu-compute/wavefront.cc  Wed Oct 26 22:47:19 2016 -0400
+++ b/src/gpu-compute/wavefront.cc  Wed Oct 26 22:47:27 2016 -0400
@@ -675,6 +675,8 @@
 } else {
 instructionBuffer.pop_front();
 }
+} else {
+discardFetch();
 }
 
 if (computeUnit->shader->hsail_mode==Shader::SIMT) {
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[gem5-dev] changeset in gem5: dev: Add 'simLength' parameter in EthPacketData

2016-10-26 Thread mlebeane

changeset 5e7599457b97 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5e7599457b97
description:
dev: Add 'simLength' parameter in EthPacketData
Currently, all the network devices create a 16K buffer for the 'data' 
field
in EthPacketData, and use 'length' to keep track of the size of the 
packet
in the buffer.  This patch introduces the 'simLength' parameter to
EthPacketData, which is used to hold the effective length of the packet 
used
for all timing calulations in the simulator.  Serialization is 
performed using
only the useful data in the packet ('length') and not necessarily the 
entire
original buffer.

diffstat:

 src/dev/net/dist_etherlink.cc |   4 ++--
 src/dev/net/dist_iface.cc |   9 +
 src/dev/net/dist_packet.hh|   6 ++
 src/dev/net/etherbus.cc   |   2 +-
 src/dev/net/etherlink.cc  |   6 +++---
 src/dev/net/etherpkt.cc   |   8 +++-
 src/dev/net/etherpkt.hh   |  24 ++--
 src/dev/net/etherswitch.cc|   2 +-
 src/dev/net/ethertap.cc   |   1 +
 src/dev/net/i8254xGBe.cc  |   7 +--
 src/dev/net/ns_gige.cc|   6 --
 src/dev/net/pktfifo.cc|   2 +-
 src/dev/net/sinic.cc  |   3 ++-
 src/dev/net/tcp_iface.cc  |   1 +
 14 files changed, 53 insertions(+), 28 deletions(-)

diffs (truncated from 333 to 300 lines):

diff -r 7d4d424c9f17 -r 5e7599457b97 src/dev/net/dist_etherlink.cc
--- a/src/dev/net/dist_etherlink.cc Wed Oct 26 22:48:28 2016 -0400
+++ b/src/dev/net/dist_etherlink.cc Wed Oct 26 22:48:33 2016 -0400
@@ -197,7 +197,7 @@
 }
 
 packet = pkt;
-Tick delay = (Tick)ceil(((double)pkt->length * ticksPerByte) + 1.0);
+Tick delay = (Tick)ceil(((double)pkt->simLength * ticksPerByte) + 1.0);
 if (delayVar != 0)
 delay += random_mt.random(0, delayVar);
 
@@ -233,7 +233,7 @@
 bool packet_exists;
 UNSERIALIZE_SCALAR(packet_exists);
 if (packet_exists) {
-packet = make_shared(16384);
+packet = make_shared();
 packet->unserialize("packet", cp);
 }
 
diff -r 7d4d424c9f17 -r 5e7599457b97 src/dev/net/dist_iface.cc
--- a/src/dev/net/dist_iface.cc Wed Oct 26 22:48:28 2016 -0400
+++ b/src/dev/net/dist_iface.cc Wed Oct 26 22:48:33 2016 -0400
@@ -407,7 +407,7 @@
 Desc d = descQueue.front();
 descQueue.pop();
 d.sendTick = curTick();
-d.sendDelay = d.packet->size(); // assume 1 tick/byte max link speed
+d.sendDelay = d.packet->simLength; // assume 1 tick/byte max link speed
 v.push_back(d);
 }
 
@@ -493,7 +493,7 @@
 {
 UNSERIALIZE_SCALAR(sendTick);
 UNSERIALIZE_SCALAR(sendDelay);
-packet = std::make_shared(16384);
+packet = std::make_shared();
 packet->unserialize("rxPacket", cp);
 }
 
@@ -583,14 +583,15 @@
 header.sendTick  = curTick();
 header.sendDelay = send_delay;
 
-header.dataPacketLength = pkt->size();
+header.dataPacketLength = pkt->length;
+header.simLength = pkt->simLength;
 
 // Send out the packet and the meta info.
 sendPacket(header, pkt);
 
 DPRINTF(DistEthernetPkt,
 "DistIface::sendDataPacket() done size:%d send_delay:%llu\n",
-pkt->size(), send_delay);
+pkt->length, send_delay);
 }
 
 void
diff -r 7d4d424c9f17 -r 5e7599457b97 src/dev/net/dist_packet.hh
--- a/src/dev/net/dist_packet.hhWed Oct 26 22:48:28 2016 -0400
+++ b/src/dev/net/dist_packet.hhWed Oct 26 22:48:33 2016 -0400
@@ -86,6 +86,11 @@
  */
 MsgType msgType;
 Tick sendTick;
+/**
+ * Length used for modeling timing in the simulator.
+ * (from EthPacketData::simLength).
+ */
+unsigned simLength;
 union {
 Tick sendDelay;
 Tick syncRepeat;
@@ -93,6 +98,7 @@
 union {
 /**
  * Actual length of the simulated Ethernet packet.
+ * (from EthPacketData::length).
  */
 unsigned dataPacketLength;
 struct {
diff -r 7d4d424c9f17 -r 5e7599457b97 src/dev/net/etherbus.cc
--- a/src/dev/net/etherbus.cc   Wed Oct 26 22:48:28 2016 -0400
+++ b/src/dev/net/etherbus.cc   Wed Oct 26 22:48:33 2016 -0400
@@ -98,7 +98,7 @@
 
 packet = pkt;
 sender = sndr;
-int delay = (int)ceil(((double)pkt->length * ticksPerByte) + 1.0);
+int delay = (int)ceil(((double)pkt->simLength * ticksPerByte) + 1.0);
 DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
 delay, ticksPerByte);
 schedule(event, curTick() + delay);
diff -r 7d4d424c9f17 -r 5e7599457b97 src/dev/net/etherlink.cc
--- a/src/dev/net/etherlink.cc  Wed Oct 26 22:48:28 2016 -0400
+++ b/src/dev/net/etherlink.cc  Wed Oct 26 22:48:33 2016 -0400
@@ -192,7 +192,7 @@
 DDUMP(EthernetData, pkt->data, pkt->length);
 
 packet = pkt;
-Tick delay =

[gem5-dev] changeset in gem5: gpu-compute, hsail: pass GPUDynInstPtr to get...

2016-10-26 Thread Tony Gutierrez

changeset c7453f485a5f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7453f485a5f
description:
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()

for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, 
or are
an immediate.

for machine ISA, however, an op selector may specify special registers, 
or
may specify special SGPRs with an alias op selector value. the location 
of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the 
relative
positions of the special register values.

diffstat:

 src/arch/hsail/insts/branch.hh  |  12 +-
 src/arch/hsail/insts/decl.hh|  44 +++-
 src/arch/hsail/insts/mem.hh |  18 +++---
 src/gpu-compute/condition_register_state.cc |   6 +-
 src/gpu-compute/condition_register_state.hh |   2 +-
 src/gpu-compute/gpu_dyn_inst.cc |  10 +-
 src/gpu-compute/gpu_dyn_inst.hh |   3 +-
 src/gpu-compute/gpu_static_inst.hh  |  13 +++-
 src/gpu-compute/vector_register_file.cc |   6 +-
 9 files changed, 84 insertions(+), 30 deletions(-)

diffs (truncated from 341 to 300 lines):

diff -r d1ad31187fa5 -r c7453f485a5f src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:47 2016 -0400
+++ b/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:49 2016 -0400
@@ -95,7 +95,9 @@
 return target.opSize();
 }
 
-int getRegisterIndex(int operandIndex) override {
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+{
 assert(operandIndex >= 0 && operandIndex < getNumOperands());
 return target.regIndex();
 }
@@ -223,7 +225,9 @@
 else
 return 1;
 }
-int getRegisterIndex(int operandIndex) override {
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+{
 assert(operandIndex >= 0 && operandIndex < getNumOperands());
 if (!operandIndex)
 return target.regIndex();
@@ -370,7 +374,9 @@
 assert(operandIndex >= 0 && operandIndex < getNumOperands());
 return target.opSize();
 }
-int getRegisterIndex(int operandIndex) override {
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+{
 assert(operandIndex >= 0 && operandIndex < getNumOperands());
 return target.regIndex();
 }
diff -r d1ad31187fa5 -r c7453f485a5f src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh  Wed Oct 26 22:47:47 2016 -0400
+++ b/src/arch/hsail/insts/decl.hh  Wed Oct 26 22:47:49 2016 -0400
@@ -178,7 +178,9 @@
 else
 return dest.opSize();
 }
-int getRegisterIndex(int operandIndex) {
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+{
 assert(operandIndex >= 0 && operandIndex < getNumOperands());
 
 if (operandIndex < NumSrcOperands)
@@ -313,7 +315,10 @@
 else
 return dest.opSize();
 }
-int getRegisterIndex(int operandIndex) {
+
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+{
 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
 if (!operandIndex)
 return src0.regIndex();
@@ -477,7 +482,10 @@
 else
 return dest.opSize();
 }
-int getRegisterIndex(int operandIndex) {
+
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+{
 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
 if (!operandIndex)
 return src0.regIndex();
@@ -643,7 +651,7 @@
 return -1;
 
 //handle positive and negative numbers
-T tmp = (src0 < 0) ? (~src0) : (src0);
+T tmp = ((int64_t)src0 < 0) ? (~src0) : (src0);
 
 //the starting pos is MSB
 int pos = 8 * sizeof(T) - 1;
@@ -732,7 +740,12 @@
 bool isSrcOperand(int operandIndex) { return false; }
 bool isDstOperand(int operandIndex) { return false; }
 int getOperandSize(int operandIndex) { return 0; }
-int getRegisterIndex(int operandIndex) { return -1; }
+
+int
+getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+{
+return -1;
+}
 
 int numSrcRegOperands() { return 0; }
 int numDstRegOperands() { return 0; }
@@ -777,10 +790,14 @@

[gem5-dev] changeset in gem5: gpu-compute: use System cache line size in th...

2016-10-26 Thread Tony Gutierrez

changeset d1ad31187fa5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1ad31187fa5
description:
gpu-compute: use System cache line size in the GPU

diffstat:

 src/gpu-compute/compute_unit.cc |  3 ++-
 src/gpu-compute/compute_unit.hh |  3 +++
 src/gpu-compute/fetch_unit.cc   |  4 ++--
 src/gpu-compute/shader.cc   |  4 ++--
 4 files changed, 9 insertions(+), 5 deletions(-)

diffs (70 lines):

diff -r c63431b7bbeb -r d1ad31187fa5 src/gpu-compute/compute_unit.cc
--- a/src/gpu-compute/compute_unit.cc   Wed Oct 26 22:47:43 2016 -0400
+++ b/src/gpu-compute/compute_unit.cc   Wed Oct 26 22:47:47 2016 -0400
@@ -75,7 +75,8 @@
 req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
 resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
 _masterId(p->system->getMasterId(name() + ".ComputeUnit")),
-lds(*p->localDataStore), globalSeqNum(0),  wavefrontSize(p->wfSize),
+lds(*p->localDataStore), _cacheLineSize(p->system->cacheLineSize()),
+globalSeqNum(0), wavefrontSize(p->wfSize),
 kernelLaunchInst(new KernelLaunchStaticInst())
 {
 /**
diff -r c63431b7bbeb -r d1ad31187fa5 src/gpu-compute/compute_unit.hh
--- a/src/gpu-compute/compute_unit.hh   Wed Oct 26 22:47:43 2016 -0400
+++ b/src/gpu-compute/compute_unit.hh   Wed Oct 26 22:47:47 2016 -0400
@@ -390,6 +390,8 @@
 int32_t
 getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const;
 
+int cacheLineSize() const { return _cacheLineSize; }
+
 bool
 sendToLds(GPUDynInstPtr gpuDynInst) __attribute__((warn_unused_result));
 
@@ -767,6 +769,7 @@
 uint64_t getAndIncSeqNum() { return globalSeqNum++; }
 
   private:
+const int _cacheLineSize;
 uint64_t globalSeqNum;
 int wavefrontSize;
 GPUStaticInst *kernelLaunchInst;
diff -r c63431b7bbeb -r d1ad31187fa5 src/gpu-compute/fetch_unit.cc
--- a/src/gpu-compute/fetch_unit.cc Wed Oct 26 22:47:43 2016 -0400
+++ b/src/gpu-compute/fetch_unit.cc Wed Oct 26 22:47:47 2016 -0400
@@ -132,10 +132,10 @@
 
 // Since this is an instruction prefetch, if you're split then just finish
 // out the current line.
-unsigned block_size = RubySystem::getBlockSizeBytes();
+int block_size = computeUnit->cacheLineSize();
 // check for split accesses
 Addr split_addr = roundDown(vaddr + block_size - 1, block_size);
-unsigned size = block_size;
+int size = block_size;
 
 if (split_addr > vaddr) {
 // misaligned access, just grab the rest of the line
diff -r c63431b7bbeb -r d1ad31187fa5 src/gpu-compute/shader.cc
--- a/src/gpu-compute/shader.cc Wed Oct 26 22:47:43 2016 -0400
+++ b/src/gpu-compute/shader.cc Wed Oct 26 22:47:47 2016 -0400
@@ -224,7 +224,7 @@
 Shader::doFunctionalAccess(RequestPtr req, MemCmd cmd, void *data,
bool suppress_func_errors, int cu_id)
 {
-unsigned block_size = RubySystem::getBlockSizeBytes();
+int block_size = cuList.at(cu_id)->cacheLineSize();
 unsigned size = req->getSize();
 
 Addr tmp_addr;
@@ -342,7 +342,7 @@
 {
 uint8_t *data_buf = (uint8_t*)ptr;
 
-for (ChunkGenerator gen(address, size, RubySystem::getBlockSizeBytes());
+for (ChunkGenerator gen(address, size, cuList.at(cu_id)->cacheLineSize());
  !gen.done(); gen.next()) {
 Request *req = new Request(0, gen.addr(), gen.size(), 0,
cuList[0]->masterId(), 0, 0, 0);
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[gem5-dev] changeset in gem5: gpu-compute: move disassemle() implementation...

2016-10-26 Thread Tony Gutierrez

changeset 6d5fc65d64bd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6d5fc65d64bd
description:
gpu-compute: move disassemle() implementation to GPUStaticInst

diffstat:

 src/arch/hsail/insts/gpu_static_inst.cc |  11 ---
 src/arch/hsail/insts/gpu_static_inst.hh |   1 -
 src/gpu-compute/gpu_static_inst.cc  |  10 ++
 src/gpu-compute/gpu_static_inst.hh  |   2 +-
 4 files changed, 11 insertions(+), 13 deletions(-)

diffs (59 lines):

diff -r 3027d6c34fa4 -r 6d5fc65d64bd src/arch/hsail/insts/gpu_static_inst.cc
--- a/src/arch/hsail/insts/gpu_static_inst.cc   Wed Oct 26 22:47:01 2016 -0400
+++ b/src/arch/hsail/insts/gpu_static_inst.cc   Wed Oct 26 22:47:05 2016 -0400
@@ -50,15 +50,4 @@
 {
 disassembly = opcode;
 }
-
-const std::string&
-HsailGPUStaticInst::disassemble()
-{
-if (disassembly.empty()) {
-generateDisassembly();
-assert(!disassembly.empty());
-}
-
-return disassembly;
-}
 } // namespace HsailISA
diff -r 3027d6c34fa4 -r 6d5fc65d64bd src/arch/hsail/insts/gpu_static_inst.hh
--- a/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:47:01 2016 -0400
+++ b/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:47:05 2016 -0400
@@ -54,7 +54,6 @@
   public:
 HsailGPUStaticInst(const BrigObject *obj, const std::string );
 void generateDisassembly();
-const std::string ();
 uint32_t instSize() { return 4; }
 bool isValid() const override { return true; }
 
diff -r 3027d6c34fa4 -r 6d5fc65d64bd src/gpu-compute/gpu_static_inst.cc
--- a/src/gpu-compute/gpu_static_inst.ccWed Oct 26 22:47:01 2016 -0400
+++ b/src/gpu-compute/gpu_static_inst.ccWed Oct 26 22:47:05 2016 -0400
@@ -40,3 +40,13 @@
   _instNum(0), _scalarOp(false)
 {
 }
+const std::string&
+GPUStaticInst::disassemble()
+{
+if (disassembly.empty()) {
+generateDisassembly();
+assert(!disassembly.empty());
+}
+
+return disassembly;
+}
diff -r 3027d6c34fa4 -r 6d5fc65d64bd src/gpu-compute/gpu_static_inst.hh
--- a/src/gpu-compute/gpu_static_inst.hhWed Oct 26 22:47:01 2016 -0400
+++ b/src/gpu-compute/gpu_static_inst.hhWed Oct 26 22:47:05 2016 -0400
@@ -72,7 +72,7 @@
 
 virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
 virtual void generateDisassembly() = 0;
-virtual const std::string () = 0;
+const std::string& disassemble();
 virtual int getNumOperands() = 0;
 virtual bool isCondRegister(int operandIndex) = 0;
 virtual bool isScalarRegister(int operandIndex) = 0;
___
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[gem5-dev] changeset in gem5: gpu-compute: add gpu_isa.hh to switch hdrs, a...

2016-10-26 Thread Tony Gutierrez

changeset 80c30bd0c7d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=80c30bd0c7d6
description:
gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF

the GPUISA class is meant to encapsulate any ISA-specific behavior - 
special
register accesses, isa-specific WF/kernel state, etc. - in a generic 
enough
way so that it may be used in ISA-agnostic code.

gpu-compute: use the GPUISA object to advance the PC

the GPU model treats the PC as a pointer to individual instruction 
objects -
which are store in a contiguous array - and not a byte address to be 
fetched
from the real memory system. this is ok for HSAIL because all 
instructions
are considered by the model to be the same size.

in machine ISA, however, instructions may be 32b or 64b, and branches 
are
calculated by advancing the PC by the number of words (4 byte chunks) it
needs to advance in the real instruction stream. because of this there 
is
a mismatch between the PC we use to index into the instruction array, 
and
the actual byte address PC the ISA expects. here we move the PC advance
calculation to the ISA so that differences in the instrucion sizes may 
be
accounted for in generic way.

diffstat:

 src/arch/SConscript |   1 +
 src/arch/hsail/gpu_isa.hh   |  82 +
 src/gpu-compute/fetch_unit.cc   |  25 ++-
 src/gpu-compute/gpu_exec_context.cc |  15 ++-
 src/gpu-compute/gpu_exec_context.hh |   7 +++
 src/gpu-compute/wavefront.cc|   4 +-
 src/gpu-compute/wavefront.hh|   9 
 7 files changed, 139 insertions(+), 4 deletions(-)

diffs (247 lines):

diff -r 0a65922d564d -r 80c30bd0c7d6 src/arch/SConscript
--- a/src/arch/SConscript   Wed Oct 26 22:47:30 2016 -0400
+++ b/src/arch/SConscript   Wed Oct 26 22:47:38 2016 -0400
@@ -71,6 +71,7 @@
 if env['BUILD_GPU']:
 gpu_isa_switch_hdrs = Split('''
 gpu_decoder.hh
+gpu_isa.hh
 gpu_types.hh
 ''')
 
diff -r 0a65922d564d -r 80c30bd0c7d6 src/arch/hsail/gpu_isa.hh
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/src/arch/hsail/gpu_isa.hh Wed Oct 26 22:47:38 2016 -0400
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its 
contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_HSAIL_GPU_ISA_HH__
+#define __ARCH_HSAIL_GPU_ISA_HH__
+
+#include 
+
+#include "base/misc.hh"
+#include "gpu-compute/misc.hh"
+
+class Wavefront;
+
+namespace HsailISA
+{
+typedef uint64_t MiscReg;
+
+class GPUISA
+{
+  public:
+GPUISA(Wavefront ) : wavefront(wf)
+{
+}
+
+void
+writeMiscReg(int opIdx, MiscReg operandVal)
+{
+fatal("HSAIL does not implement misc registers yet\n");
+}
+
+MiscReg
+readMiscReg(int opIdx) const
+{
+fatal("HSAIL does not implement misc registers yet\n");
+}
+
+bool hasScalarUnit() const { return false; }
+
+uint32_t
+advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
+{
+return old_pc + 1;
+}
+
+  private:
+Wavefront 
+};
+}
+
+#endif // __ARCH_HSAIL_GPU_ISA_HH__
diff -r 0a65922d564d -r 80c30bd0c7d6

[gem5-dev] changeset in gem5: gpu-compute: add instruction mix stats for th...

2016-10-26 Thread Tony Gutierrez

changeset 0a65922d564d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0a65922d564d
description:
gpu-compute: add instruction mix stats for the gpu

diffstat:

 src/gpu-compute/compute_unit.cc |  141 
 src/gpu-compute/compute_unit.hh |   25 +++
 src/gpu-compute/wavefront.cc|4 +
 3 files changed, 170 insertions(+), 0 deletions(-)

diffs (208 lines):

diff -r c3b4d57a15c5 -r 0a65922d564d src/gpu-compute/compute_unit.cc
--- a/src/gpu-compute/compute_unit.cc   Wed Oct 26 22:47:27 2016 -0400
+++ b/src/gpu-compute/compute_unit.cc   Wed Oct 26 22:47:30 2016 -0400
@@ -1408,6 +1408,114 @@
 {
 MemObject::regStats();
 
+vALUInsts
+.name(name() + ".valu_insts")
+.desc("Number of vector ALU insts issued.")
+;
+vALUInstsPerWF
+.name(name() + ".valu_insts_per_wf")
+.desc("The avg. number of vector ALU insts issued per-wavefront.")
+;
+sALUInsts
+.name(name() + ".salu_insts")
+.desc("Number of scalar ALU insts issued.")
+;
+sALUInstsPerWF
+.name(name() + ".salu_insts_per_wf")
+.desc("The avg. number of scalar ALU insts issued per-wavefront.")
+;
+instCyclesVALU
+.name(name() + ".inst_cycles_valu")
+.desc("Number of cycles needed to execute VALU insts.")
+;
+instCyclesSALU
+.name(name() + ".inst_cycles_salu")
+.desc("Number of cycles needed to execute SALU insts.")
+;
+threadCyclesVALU
+.name(name() + ".thread_cycles_valu")
+.desc("Number of thread cycles used to execute vector ALU ops. "
+  "Similar to instCyclesVALU but multiplied by the number of "
+  "active threads.")
+;
+vALUUtilization
+.name(name() + ".valu_utilization")
+.desc("Percentage of active vector ALU threads in a wave.")
+;
+ldsNoFlatInsts
+.name(name() + ".lds_no_flat_insts")
+.desc("Number of LDS insts issued, not including FLAT "
+  "accesses that resolve to LDS.")
+;
+ldsNoFlatInstsPerWF
+.name(name() + ".lds_no_flat_insts_per_wf")
+.desc("The avg. number of LDS insts (not including FLAT "
+  "accesses that resolve to LDS) per-wavefront.")
+;
+flatVMemInsts
+.name(name() + ".flat_vmem_insts")
+.desc("The number of FLAT insts that resolve to vmem issued.")
+;
+flatVMemInstsPerWF
+.name(name() + ".flat_vmem_insts_per_wf")
+.desc("The average number of FLAT insts that resolve to vmem "
+  "issued per-wavefront.")
+;
+flatLDSInsts
+.name(name() + ".flat_lds_insts")
+.desc("The number of FLAT insts that resolve to LDS issued.")
+;
+flatLDSInstsPerWF
+.name(name() + ".flat_lds_insts_per_wf")
+.desc("The average number of FLAT insts that resolve to LDS "
+  "issued per-wavefront.")
+;
+vectorMemWrites
+.name(name() + ".vector_mem_writes")
+.desc("Number of vector mem write insts (excluding FLAT insts).")
+;
+vectorMemWritesPerWF
+.name(name() + ".vector_mem_writes_per_wf")
+.desc("The average number of vector mem write insts "
+  "(excluding FLAT insts) per-wavefront.")
+;
+vectorMemReads
+.name(name() + ".vector_mem_reads")
+.desc("Number of vector mem read insts (excluding FLAT insts).")
+;
+vectorMemReadsPerWF
+.name(name() + ".vector_mem_reads_per_wf")
+.desc("The avg. number of vector mem read insts (excluding "
+  "FLAT insts) per-wavefront.")
+;
+scalarMemWrites
+.name(name() + ".scalar_mem_writes")
+.desc("Number of scalar mem write insts.")
+;
+scalarMemWritesPerWF
+.name(name() + ".scalar_mem_writes_per_wf")
+.desc("The average number of scalar mem write insts per-wavefront.")
+;
+scalarMemReads
+.name(name() + ".scalar_mem_reads")
+.desc("Number of scalar mem read insts.")
+;
+scalarMemReadsPerWF
+.name(name() + ".scalar_mem_reads_per_wf")
+.desc("The average number of scalar mem read insts per-wavefront.")
+;
+
+vALUInstsPerWF = vALUInsts / completedWfs;
+sALUInstsPerWF = sALUInsts / completedWfs;
+vALUUtilization = (threadCyclesVALU / (64 * instCyclesVALU)) * 100;
+ldsNoFlatInstsPerWF = ldsNoFlatInsts / completedWfs;
+flatVMemInstsPerWF = flatVMemInsts / completedWfs;
+flatLDSInstsPerWF = flatLDSInsts / completedWfs;
+vectorMemWritesPerWF = vectorMemWrites / completedWfs;
+vectorMemReadsPerWF = vectorMemReads / completedWfs;
+scalarMemWritesPerWF = scalarMemWrites / completedWfs;
+scalarMemReadsPerWF = scalarMemReads / completedWfs;
+
 tlbCycles
 .name(name() + ".tlb_cycles")
 .desc("total number of

[gem5-dev] changeset in gem5: gpu-compute: support in-order data delivery i...

2016-10-26 Thread Tony Gutierrez

changeset 7d4d424c9f17 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7d4d424c9f17
description:
gpu-compute: support in-order data delivery in GM pipe

this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the buffer is implemented as
a stl ordered map, which sorts the request in program order by
using their sequence ID. when requests return to the GM pipeline
they are marked as done. only the oldest request may be serviced
from the ordered buffer, and only if is marked as done.

the FIFO response buffers are kept and used in OoO delivery mode

diffstat:

 configs/example/apu_se.py |8 +-
 src/arch/hsail/insts/decl.hh  |2 +-
 src/arch/hsail/insts/mem_impl.hh  |   16 +-
 src/arch/hsail/insts/pseudo_inst.cc   |6 +-
 src/gpu-compute/GPU.py|2 +
 src/gpu-compute/compute_unit.cc   |   12 +--
 src/gpu-compute/global_memory_pipeline.cc |  124 +
 src/gpu-compute/global_memory_pipeline.hh |   49 +++-
 8 files changed, 173 insertions(+), 46 deletions(-)

diffs (truncated from 430 to 300 lines):

diff -r c7453f485a5f -r 7d4d424c9f17 configs/example/apu_se.py
--- a/configs/example/apu_se.py Wed Oct 26 22:47:49 2016 -0400
+++ b/configs/example/apu_se.py Wed Oct 26 22:48:28 2016 -0400
@@ -153,7 +153,9 @@
   help = 'fast forward using kvm until the m5_switchcpu'
   ' pseudo-op is encountered, then switch cpus. subsequent'
   ' m5_switchcpu pseudo-ops will toggle back and forth')
-
+parser.add_option('--outOfOrderDataDelivery', action='store_true',
+  default=False, help='enable OoO data delivery in the GM'
+  ' pipeline')
 
 Ruby.define_options(parser)
 
@@ -248,7 +250,9 @@
  localDataStore = \
  LdsState(banks = options.numLdsBanks,
   bankConflictPenalty = \
-  options.ldsBankConflictPenalty)))
+  options.ldsBankConflictPenalty),
+ out_of_order_data_delivery =
+ options.outOfOrderDataDelivery))
 wavefronts = []
 vrfs = []
 for j in xrange(options.simds_per_cu):
diff -r c7453f485a5f -r 7d4d424c9f17 src/arch/hsail/insts/decl.hh
--- a/src/arch/hsail/insts/decl.hh  Wed Oct 26 22:47:49 2016 -0400
+++ b/src/arch/hsail/insts/decl.hh  Wed Oct 26 22:48:28 2016 -0400
@@ -1082,7 +1082,7 @@
 
 gpuDynInst->useContinuation = false;
 GlobalMemPipeline* gmp = &(w->computeUnit->globalMemoryPipe);
-gmp->getGMReqFIFO().push(gpuDynInst);
+gmp->issueRequest(gpuDynInst);
 
 w->wrGmReqsInPipe--;
 w->rdGmReqsInPipe--;
diff -r c7453f485a5f -r 7d4d424c9f17 src/arch/hsail/insts/mem_impl.hh
--- a/src/arch/hsail/insts/mem_impl.hh  Wed Oct 26 22:47:49 2016 -0400
+++ b/src/arch/hsail/insts/mem_impl.hh  Wed Oct 26 22:48:28 2016 -0400
@@ -263,7 +263,7 @@
 }
 }
 
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsRdGm++;
 w->rdGmReqsInPipe--;
 break;
@@ -288,7 +288,7 @@
 }
 }
 
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsRdGm++;
 w->rdGmReqsInPipe--;
 break;
@@ -312,7 +312,7 @@
 }
 }
 
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsRdGm++;
 w->rdGmReqsInPipe--;
 break;
@@ -330,7 +330,7 @@
 }
 }
 }
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsRdGm++;
 w->rdGmReqsInPipe--;
 break;
@@ -440,7 +440,7 @@
 }
 }
 
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsWrGm++;
 w->wrGmReqsInPipe--;
 break;
@@ -460,7 +460,7 @@
 }
 }
 
-w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
+w->computeUnit->globalMemoryPipe.issueRequest(m);
 w->outstandingReqsWrGm++;
 w->wrGmReqsInPipe--;
 break;
@@ -486,7 +486,7 @@

[gem5-dev] changeset in gem5: gpu-compute, hsail: make the PC a byte addres...

2016-10-26 Thread Tony Gutierrez

changeset c63431b7bbeb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c63431b7bbeb
description:
gpu-compute, hsail: make the PC a byte address, not an instruction index

currently the PC is incremented on an instruction granularity, and not 
as an
instruction's byte address. machine ISA instructions assume the PC is a 
byte
address, and is incremented accordingly. here we make the GPU model, 
and the
HSAIL instructions treat the PC as a byte address as well.

diffstat:

 src/arch/hsail/gpu_isa.hh   |   3 ++-
 src/arch/hsail/gpu_types.hh |   2 +-
 src/arch/hsail/insts/branch.hh  |   4 ++--
 src/arch/hsail/insts/gpu_static_inst.hh |   3 ++-
 src/gpu-compute/cl_driver.cc|   5 +++--
 src/gpu-compute/fetch_unit.cc   |   5 ++---
 src/gpu-compute/gpu_static_inst.cc  |   2 +-
 src/gpu-compute/gpu_static_inst.hh  |   8 ++--
 src/gpu-compute/hsail_code.cc   |  17 -
 src/gpu-compute/kernel_cfg.cc   |  29 ++---
 src/gpu-compute/kernel_cfg.hh   |   2 +-
 11 files changed, 46 insertions(+), 34 deletions(-)

diffs (truncated from 301 to 300 lines):

diff -r 80c30bd0c7d6 -r c63431b7bbeb src/arch/hsail/gpu_isa.hh
--- a/src/arch/hsail/gpu_isa.hh Wed Oct 26 22:47:38 2016 -0400
+++ b/src/arch/hsail/gpu_isa.hh Wed Oct 26 22:47:43 2016 -0400
@@ -38,6 +38,7 @@
 
 #include 
 
+#include "arch/hsail/gpu_types.hh"
 #include "base/misc.hh"
 #include "gpu-compute/misc.hh"
 
@@ -71,7 +72,7 @@
 uint32_t
 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
 {
-return old_pc + 1;
+return old_pc + sizeof(RawMachInst);
 }
 
   private:
diff -r 80c30bd0c7d6 -r c63431b7bbeb src/arch/hsail/gpu_types.hh
--- a/src/arch/hsail/gpu_types.hh   Wed Oct 26 22:47:38 2016 -0400
+++ b/src/arch/hsail/gpu_types.hh   Wed Oct 26 22:47:43 2016 -0400
@@ -51,7 +51,7 @@
 // our model uses to represent an actual instruction. In
 // the case of HSAIL this is just an index into a list of
 // instruction objects.
-typedef uint64_t RawMachInst;
+typedef uint32_t RawMachInst;
 
 // The MachInst is a representation of an instruction
 // that has more information than just the machine code.
diff -r 80c30bd0c7d6 -r c63431b7bbeb src/arch/hsail/insts/branch.hh
--- a/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:38 2016 -0400
+++ b/src/arch/hsail/insts/branch.hhWed Oct 26 22:47:43 2016 -0400
@@ -257,7 +257,7 @@
 {
 Wavefront *w = gpuDynInst->wavefront();
 
-const uint32_t curr_pc = w->pc();
+const uint32_t curr_pc M5_VAR_USED = w->pc();
 const uint32_t curr_rpc = w->rpc();
 const VectorMask curr_mask = w->execMask();
 
@@ -281,7 +281,7 @@
 }
 
 // not taken branch
-const uint32_t false_pc = curr_pc + 1;
+const uint32_t false_pc = nextInstAddr();
 assert(true_pc != false_pc);
 if (false_pc != rpc && true_mask.count() < curr_mask.count()) {
 VectorMask false_mask = curr_mask & ~true_mask;
diff -r 80c30bd0c7d6 -r c63431b7bbeb src/arch/hsail/insts/gpu_static_inst.hh
--- a/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:47:38 2016 -0400
+++ b/src/arch/hsail/insts/gpu_static_inst.hh   Wed Oct 26 22:47:43 2016 -0400
@@ -42,6 +42,7 @@
  * Defines the base class representing HSAIL GPU static instructions.
  */
 
+#include "arch/hsail/gpu_types.hh"
 #include "gpu-compute/gpu_static_inst.hh"
 
 class BrigObject;
@@ -54,7 +55,7 @@
   public:
 HsailGPUStaticInst(const BrigObject *obj, const std::string );
 void generateDisassembly();
-uint32_t instSize() { return 4; }
+int instSize() const override { return sizeof(RawMachInst); }
 bool isValid() const override { return true; }
 
   protected:
diff -r 80c30bd0c7d6 -r c63431b7bbeb src/gpu-compute/cl_driver.cc
--- a/src/gpu-compute/cl_driver.cc  Wed Oct 26 22:47:38 2016 -0400
+++ b/src/gpu-compute/cl_driver.cc  Wed Oct 26 22:47:43 2016 -0400
@@ -79,7 +79,7 @@
 kernelInfo[i].code_offs = code_offs;
 
 name_offs += k->name().size() + 1;
-code_offs += k->numInsts() * sizeof(GPUStaticInst*);
+code_offs += k->numInsts() * sizeof(TheGpuISA::RawMachInst);
 }
 }
 
@@ -130,7 +130,8 @@
 HsaCode *k = kernels[i];
 // add one for terminating '\0'
 sizes->string_table_size += k->name().size() + 1;
-sizes->code_size += k->numInsts() * sizeof(GPUStaticInst*);
+sizes->code_size +=
+k->numInsts() * sizeof(TheGpuISA::RawMachInst);
 }
 
 sizes.copyOut(tc->getMemProxy());
diff -r 80c30bd0c7d6 -r c63431b7bbeb src/gpu-compute/fetch_unit.cc
--- a/src/gpu-compute/fetch_unit.cc Wed Oct 26 22:47:38 2016 -0400
+++ b/src/gpu-compute/fetch_unit.cc

[gem5-dev] changeset in gem5: gpu-compute: remove inst enums and use bit fl...

2016-10-26 Thread Tony Gutierrez

changeset e772fdcd3809 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e772fdcd3809
description:
gpu-compute: remove inst enums and use bit flag for attributes

this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple set of attribute flags that can be set in the base
instruction class are used. this will help unify the attributes of HSAIL
and machine ISA instructions within the model itself.

because the static instrution now carries the attributes, a GPUDynInst
must carry a pointer to a valid GPUStaticInst so a new static kernel 
launch
instruction is added, which carries the attributes needed to perform a
the kernel launch.

diffstat:

 src/arch/hsail/SConscript |1 -
 src/arch/hsail/generic_types.cc   |   47 --
 src/arch/hsail/generic_types.hh   |   16 -
 src/arch/hsail/insts/branch.hh|   14 +-
 src/arch/hsail/insts/decl.hh  |  125 +-
 src/arch/hsail/insts/main.cc  |5 +-
 src/arch/hsail/insts/mem.cc   |   63 --
 src/arch/hsail/insts/mem.hh   |  648 ++---
 src/arch/hsail/insts/mem_impl.hh  |   25 -
 src/arch/hsail/insts/pseudo_inst.cc   |   31 +-
 src/gpu-compute/GPU.py|  108 -
 src/gpu-compute/GPUStaticInstFlags.py |  111 +
 src/gpu-compute/SConscript|1 +
 src/gpu-compute/code_enums.hh |  116 -
 src/gpu-compute/compute_unit.cc   |   26 +-
 src/gpu-compute/compute_unit.hh   |1 +
 src/gpu-compute/global_memory_pipeline.cc |   23 +-
 src/gpu-compute/gpu_dyn_inst.cc   |  382 -
 src/gpu-compute/gpu_dyn_inst.hh   |  215 -
 src/gpu-compute/gpu_static_inst.cc|6 +-
 src/gpu-compute/gpu_static_inst.hh|  169 ++-
 src/gpu-compute/kernel_cfg.cc |   10 +-
 src/gpu-compute/lds_state.cc  |7 +-
 src/gpu-compute/lds_state.hh  |1 -
 src/gpu-compute/local_memory_pipeline.cc  |9 +-
 src/gpu-compute/shader.hh |1 -
 src/gpu-compute/vector_register_file.cc   |5 +-
 src/gpu-compute/wavefront.cc  |  207 ++--
 28 files changed, 1257 insertions(+), 1116 deletions(-)

diffs (truncated from 3777 to 300 lines):

diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/SConscript
--- a/src/arch/hsail/SConscript Wed Oct 26 22:47:05 2016 -0400
+++ b/src/arch/hsail/SConscript Wed Oct 26 22:47:11 2016 -0400
@@ -43,7 +43,6 @@
 env.Command(['insts/gen_decl.hh', 'gpu_decoder.cc', 'insts/gen_exec.cc'],
 'gen.py', '$SOURCE $TARGETS')
 
-Source('generic_types.cc')
 Source('gpu_decoder.cc')
 Source('insts/branch.cc')
 Source('insts/gen_exec.cc')
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/generic_types.cc
--- a/src/arch/hsail/generic_types.cc   Wed Oct 26 22:47:05 2016 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,47 +0,0 @@
-#include "arch/hsail/generic_types.hh"
-#include "base/misc.hh"
-
-using namespace Brig;
-
-namespace HsailISA
-{
-Enums::GenericMemoryOrder
-getGenericMemoryOrder(BrigMemoryOrder brig_memory_order)
-{
-switch(brig_memory_order) {
-  case BRIG_MEMORY_ORDER_NONE:
-return Enums::MEMORY_ORDER_NONE;
-  case BRIG_MEMORY_ORDER_RELAXED:
-return Enums::MEMORY_ORDER_RELAXED;
-  case BRIG_MEMORY_ORDER_SC_ACQUIRE:
-return Enums::MEMORY_ORDER_SC_ACQUIRE;
-  case BRIG_MEMORY_ORDER_SC_RELEASE:
-return Enums::MEMORY_ORDER_SC_RELEASE;
-  case BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
-return Enums::MEMORY_ORDER_SC_ACQUIRE_RELEASE;
-  default:
-fatal("HsailISA::MemInst::getGenericMemoryOrder -> ",
-  "bad BrigMemoryOrder\n");
-}
-}
-
-Enums::GenericMemoryScope
-getGenericMemoryScope(BrigMemoryScope brig_memory_scope)
-{
-switch(brig_memory_scope) {
-  case BRIG_MEMORY_SCOPE_NONE:
-return Enums::MEMORY_SCOPE_NONE;
-  case BRIG_MEMORY_SCOPE_WORKITEM:
-return Enums::MEMORY_SCOPE_WORKITEM;
-  case BRIG_MEMORY_SCOPE_WORKGROUP:
-return Enums::MEMORY_SCOPE_WORKGROUP;
-  case BRIG_MEMORY_SCOPE_AGENT:
-return Enums::MEMORY_SCOPE_DEVICE;
-  case BRIG_MEMORY_SCOPE_SYSTEM:
-return Enums::MEMORY_SCOPE_SYSTEM;
-  default:
-fatal("HsailISA::MemInst::getGenericMemoryScope -> ",
-  "bad BrigMemoryScope\n");
-}
-}
-} // namespace HsailISA
diff -r 6d5fc65d64bd -r e772fdcd3809 src/arch/hsail/generic_types.hh
--- a/src/arch/hsail/generic_types.hh   Wed Oct 26 22:47:05 2016 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,16 +0,0 @@
-#ifndef __ARCH_HSAIL_GENERIC_TYPES_HH__

[gem5-dev] SynchroTrace trace player on ReviewBoard

2016-10-26 Thread Curtis Dunham

Hello all,
The SynchroTrace project [2] provides multi-threaded traces that are 
synchronization-aware.  I have posted to ReviewBoard a patch [1] providing the 
trace replayer part of the project.  The traces themselves are generated using 
a separate tool; we understand that there may be concerns about this.  Still, 
we hope the community sees the value in this functionality.

We look forward to your feedback.


Thanks,
Curtis Dunham

[1] http://reviews.gem5.org/r/3687/
[2] http://dpac.ece.drexel.edu/current-research-projects/synchrotrace/
IMPORTANT NOTICE: The contents of this email and any attachments are 
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please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.

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[gem5-dev] Review Request 3687: cpu: Add a SynchroTrace replay model

2016-10-26 Thread Curtis Dunham


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3687/
---

Review request for Default.


Repository: gem5


Description
---

cpu: Add a SynchroTrace replay model

SynchroTrace's trace replay is a 1-CPI timing model that interfaces with
the multi-threaded traces from Sigil to inject traffic into the detailed
memory model. The high-level description of the execution flow is in
src/cpu/testers/synchrotrace/SynchroTrace.hh

The following is included in this patch:
 * The main SynchroTrace trace replay file
 * SynchroTrace parser file which processes Sigil Traces into
   SynchroTrace events
 * A front-end python configuration script with a default two-level
   cache hierarchy.

Change-Id: I6c89894d95974d838bc9ee3b9e468a4032f6613a


Diffs
-

  configs/example/synchrotrace_classic_memory.py PRE-CREATION 
  src/cpu/testers/synchrotrace/SConscript PRE-CREATION 
  src/cpu/testers/synchrotrace/SynchroTrace.py PRE-CREATION 
  src/cpu/testers/synchrotrace/st_event.hh PRE-CREATION 
  src/cpu/testers/synchrotrace/st_parser.hh PRE-CREATION 
  src/cpu/testers/synchrotrace/st_parser.cc PRE-CREATION 
  src/cpu/testers/synchrotrace/synchro_trace.hh PRE-CREATION 
  src/cpu/testers/synchrotrace/synchro_trace.cc PRE-CREATION 

Diff: http://reviews.gem5.org/r/3687/diff/


Testing
---


Thanks,

Curtis Dunham

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Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

2016-10-26 Thread Andreas Hansson


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---


Somehow the patch is not displaying. Did you use hg postreview?

- Andreas Hansson


On Oct. 26, 2016, 4:26 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3686/
> ---
> 
> (Updated Oct. 26, 2016, 4:26 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch simplifies the implementation of the SystemC TLM slave port.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.hh c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
>   util/tlm/sc_slave_port.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
> 
> Diff: http://reviews.gem5.org/r/3686/diff/
> 
> 
> Testing
> ---
> 
> Example applications are still running.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

2016-10-26 Thread Andreas Hansson


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http://reviews.gem5.org/r/3528/#review8989
---


Some of the files are not displaying ok. Did you post the review using hg 
postreview?


util/tlm/examples/master_port/Makefile (line 37)


Same as previous patch. This should use pkt-config.



util/tlm/examples/master_port/Makefile (line 40)


An assignment to a name would be good for these paths. GEM5_ROOT or similar



util/tlm/examples/master_port/main.cc (line 101)


gem5 has a random_mt that you should preferably use



util/tlm/examples/master_port/main.cc (line 187)


Same as the other patch. Why not use the response string size?



util/tlm/sc_master_port.hh (line 32)


Not convention



util/tlm/sc_master_port.hh (line 49)


Could you provide a bit more comments here around what is assumed, how it 
does what it does, what it doesn't do, etc



util/tlm/sc_master_port.cc (line 32)


Same as the header



util/tlm/sc_master_port.cc (line 73)


Is it assumed that the request is deleted elsewhere?



util/tlm/sc_master_port.cc (line 81)


comma on the line before

name,
other name



util/tlm/sc_master_port.cc (line 90)


Why the re-interpret cast?



util/tlm/sc_master_port.cc (line 98)


it is not a big problem, but technically gem5 can change mode during the 
simulation.

The API for this is involving calls to drain and drain resume etc. We don't 
have to fix it now, but it may be worth at least warning if any of these 
functions are called.



util/tlm/sc_master_port.cc (line 116)


could we base this on the response string rather to avoid buffer overflows? 
:-)



util/tlm/sc_master_port.cc (line 126)


odd indentation



util/tlm/sc_master_port.cc (line 138)


what is this checking?


- Andreas Hansson


On Oct. 26, 2016, 4:23 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Oct. 26, 2016, 4:23 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch adds a Master Port that allows 
> the TLM world to send requests to the gem5 world. Furthermore, the patch 
> provides a simple example application based on a TLM traffic generator.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
>   util/tlm/examples/master_port/Makefile PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/Makefile 
> c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/README c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory is part of the patch.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

2016-10-26 Thread Andreas Hansson


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---


Thanks for this. There are a few minor issues and style questions.


util/tlm/Makefile (line 4)


Just add the additional Copyright line before "All rights reserved."



util/tlm/Makefile (line 10)


Please avoid changing whitespace (even if it is wrong). That should be done 
separately.



util/tlm/Makefile (line 35)


Just leave Authors on the top line and indent your name.



util/tlm/Makefile (line 42)


Both of these lines should use pkg-config.

I would suggest to do that as a separate patch though, and do it _before_ 
this patch.



util/tlm/Makefile (line 45)


could you make a define for the directory rather?



util/tlm/Makefile (line 49)


c++11



util/tlm/Makefile (line 86)


This is a bit dubious, is it not?



util/tlm/examples/slave_port/main.cc (line 6)


Same as before.



util/tlm/main.cc (line 6)


Same as before



util/tlm/main.cc (line 97)


keep the comma on the first line

name,
other name,
yet another name



util/tlm/main.cc (line 132)


spurious change



util/tlm/main.cc (line 163)


fits on the line? less than 78 char?



util/tlm/main.cc (line 195)


again, spurious change



util/tlm/main.cc (line 206)


i'm not sure why this has changed



util/tlm/main.cc (line 219)


ame here



util/tlm/main.cc (line 228)


yet another one



util/tlm/payload_event.hh (line 6)


Same as before



util/tlm/payload_event.hh (line 50)


Great. Could you provide a bit more comments though. At the moment it is 
difficult to grasp.



util/tlm/sc_port.hh (line 6)


Same as before



util/tlm/sc_port.cc (line 89)


You may want to call this SCSlavePort or TLMSlavePort or similar to avoid 
confusion.



util/tlm/sim_control.hh (line 6)


Same as before


- Andreas Hansson


On Oct. 26, 2016, 4:11 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3527/
> ---
> 
> (Updated Oct. 26, 2016, 4:11 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch restructures the existing 
> source code in util/tlm in order to allow for code reuse and a clear file 
> structure whenn adding a master port implementation.
> 
> 
> Diffs
> -
> 
>   configs/common/MemConfig.py b3d5f0e9e258 
>   util/tlm/Makefile b3d5f0e9e258 
>   util/tlm/README b3d5f0e9e258 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/main.cc b3d5f0e9e258 
>   util/tlm/payload_event.hh PRE-CREATION 
>   util/tlm/run_gem5.sh b3d5f0e9e258 
>   util/tlm/sc_port.hh b3d5f0e9e258 
>   util/tlm/sc_port.cc b3d5f0e9e258 
>   util/tlm/sc_target.hh b3d5f0e9e258 
>   util/tlm/sc_target.cc b3d5f0e9e258 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/tgen.cfg b3d5f0e9e258 
>   util/tlm/tlm.py b3d5f0e9e258 
>   util/tlm/tlm_elastic.py b3d5f0e9e258 
> 
> Diff: http://reviews.gem5.org/r/3527/diff/
> 
> 
> Testing
> ---
> 
> The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
> compile and run error free.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3480: misc: add a MasterId to the ExternalPort

2016-10-26 Thread Andreas Hansson


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---

Ship it!


Ship It!

- Andreas Hansson


On Oct. 26, 2016, 4:06 p.m., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3480/
> ---
> 
> (Updated Oct. 26, 2016, 4:06 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The Request constructor requires a MasterID. However, an external transactor 
> has no chance of getting a MasterID as it does not have a pointer to the 
> System. This patch adds a MasterID to ExternalMaster in order to allow 
> external modules to genrerate Packets.
> 
> 
> Diffs
> -
> 
>   src/mem/ExternalMaster.py b3d5f0e9e258 
>   src/mem/external_master.hh b3d5f0e9e258 
>   src/mem/external_master.cc b3d5f0e9e258 
> 
> Diff: http://reviews.gem5.org/r/3480/diff/
> 
> 
> Testing
> ---
> 
> Used in a SystemC transactor
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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[gem5-dev] changeset in gem5: config: Break out base options for usage with...

2016-10-26 Thread Andreas Hansson

changeset 725fef71f376 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=725fef71f376
description:
config: Break out base options for usage with NULL ISA

This patch breaks out the most basic configuration options into a set
of base options, to allow them to be used also by scripts that do not
involve any ISA, and thus no actual CPUs or devices.

The patch also fixes a few modules so that they can be imported in a
NULL build, and avoid dragging in FSConfig every time Options is
imported.

diffstat:

 configs/common/CpuConfig.py |2 +-
 configs/common/FSConfig.py  |2 +-
 configs/common/Options.py   |  141 +--
 configs/common/PlatformConfig.py|2 +-
 configs/common/Simulation.py|4 +-
 configs/example/garnet_synth_traffic.py |2 +-
 configs/example/ruby_direct_test.py |2 +-
 configs/example/ruby_gpu_random_test.py |2 +-
 configs/example/ruby_mem_test.py|2 +-
 configs/example/ruby_random_test.py |2 +-
 10 files changed, 87 insertions(+), 74 deletions(-)

diffs (truncated from 302 to 300 lines):

diff -r b3d5f0e9e258 -r 725fef71f376 configs/common/CpuConfig.py
--- a/configs/common/CpuConfig.py   Wed Oct 19 06:20:04 2016 -0400
+++ b/configs/common/CpuConfig.py   Wed Oct 26 14:50:54 2016 -0400
@@ -70,7 +70,7 @@
 return issubclass(cls, m5.objects.BaseCPU) and \
 not cls.abstract and \
 not issubclass(cls, m5.objects.CheckerCPU)
-except TypeError:
+except (TypeError, AttributeError):
 return False
 
 def get(name):
diff -r b3d5f0e9e258 -r 725fef71f376 configs/common/FSConfig.py
--- a/configs/common/FSConfig.pyWed Oct 19 06:20:04 2016 -0400
+++ b/configs/common/FSConfig.pyWed Oct 26 14:50:54 2016 -0400
@@ -42,7 +42,7 @@
 from m5.objects import *
 from Benchmarks import *
 from m5.util import *
-import PlatformConfig
+from common import PlatformConfig
 
 # Populate to reflect supported os types per target ISA
 os_types = { 'alpha' : [ 'linux' ],
diff -r b3d5f0e9e258 -r 725fef71f376 configs/common/Options.py
--- a/configs/common/Options.py Wed Oct 19 06:20:04 2016 -0400
+++ b/configs/common/Options.py Wed Oct 26 14:50:54 2016 -0400
@@ -41,13 +41,11 @@
 import m5
 from m5.defines import buildEnv
 from m5.objects import *
-from Benchmarks import *
+from common.Benchmarks import *
 
-import CpuConfig
-import MemConfig
-import PlatformConfig
-
-from FSConfig import os_types
+from common import CpuConfig
+from common import MemConfig
+from common import PlatformConfig
 
 def _listCpuTypes(option, opt, value, parser):
 CpuConfig.print_cpu_list()
@@ -61,15 +59,10 @@
 PlatformConfig.print_platform_list()
 sys.exit(0)
 
-def addCommonOptions(parser):
-# system options
-parser.add_option("--list-cpu-types",
-  action="callback", callback=_listCpuTypes,
-  help="List available CPU types")
-parser.add_option("--cpu-type", type="choice", default="atomic",
-  choices=CpuConfig.cpu_names(),
-  help = "type of cpu to run with")
-parser.add_option("--checker", action="store_true");
+# Add the very basic options that work also in the case of the no ISA
+# being used, and consequently no CPUs, but rather various types of
+# testers and traffic generators.
+def addNoISAOptions(parser):
 parser.add_option("-n", "--num-cpus", type="int", default=1)
 parser.add_option("--sys-voltage", action="store", type="string",
   default='1.0V',
@@ -79,6 +72,73 @@
   default='1GHz',
   help = """Top-level clock for blocks running at system
   speed""")
+
+# Memory Options
+parser.add_option("--list-mem-types",
+  action="callback", callback=_listMemTypes,
+  help="List available memory types")
+parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
+  choices=MemConfig.mem_names(),
+  help = "type of memory to use")
+parser.add_option("--mem-channels", type="int", default=1,
+  help = "number of memory channels")
+parser.add_option("--mem-ranks", type="int", default=None,
+  help = "number of memory ranks per channel")
+parser.add_option("--mem-size", action="store", type="string",
+  default="512MB",
+  help="Specify the physical memory size (single memory)")
+
+
+parser.add_option("--memchecker", action="store_true")
+
+# Cache Options
+parser.add_option("--external-memory-system", type="string",
+  help="use external ports of this port_type for caches")
+parser.add_option("--tlm-memory", type="string",
+  help="use external port

[gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

2016-10-26 Thread Christian Menard


---
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http://reviews.gem5.org/r/3686/
---

Review request for Default.


Repository: gem5


Description
---

This patch simplifies the implementation of the SystemC TLM slave port.


Diffs
-

  util/tlm/sc_slave_port.hh c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
  util/tlm/sc_slave_port.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 

Diff: http://reviews.gem5.org/r/3686/diff/


Testing
---

Example applications are still running.


Thanks,

Christian Menard

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

2016-10-26 Thread Christian Menard


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---

(Updated Oct. 26, 2016, 4:23 p.m.)


Review request for Default.


Changes
---

Updated the diff: rebased on 11691 and generated with mq


Repository: gem5


Description
---

The current TLM code only provides a Slave Port that allows the gem5 world to 
send requests to the the TLM world. This patch adds a Master Port that allows 
the TLM world to send requests to the gem5 world. Furthermore, the patch 
provides a simple example application based on a TLM traffic generator.


Diffs (updated)
-

  util/tlm/sc_master_port.cc PRE-CREATION 
  util/tlm/sim_control.cc c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
  util/tlm/examples/master_port/Makefile PRE-CREATION 
  util/tlm/examples/master_port/main.cc PRE-CREATION 
  util/tlm/examples/master_port/tlm.py PRE-CREATION 
  util/tlm/examples/slave_port/Makefile 
c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 
  util/tlm/sc_master_port.hh PRE-CREATION 
  util/tlm/README c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 

Diff: http://reviews.gem5.org/r/3528/diff/


Testing
---

A simple example application consisting of a TLM traffic generator and a gem5 
memory is part of the patch.


Thanks,

Christian Menard

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Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

2016-10-26 Thread Christian Menard


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---

(Updated Oct. 26, 2016, 4:11 p.m.)


Review request for Default.


Changes
---

Updated the diff: rebased on 11691 and generated with mq


Repository: gem5


Description
---

The current TLM code only provides a Slave Port that allows the gem5 world to 
send requests to the the TLM world. This patch restructures the existing source 
code in util/tlm in order to allow for code reuse and a clear file structure 
whenn adding a master port implementation.


Diffs (updated)
-

  configs/common/MemConfig.py b3d5f0e9e258 
  util/tlm/Makefile b3d5f0e9e258 
  util/tlm/README b3d5f0e9e258 
  util/tlm/examples/slave_port/main.cc PRE-CREATION 
  util/tlm/main.cc b3d5f0e9e258 
  util/tlm/payload_event.hh PRE-CREATION 
  util/tlm/run_gem5.sh b3d5f0e9e258 
  util/tlm/sc_port.hh b3d5f0e9e258 
  util/tlm/sc_port.cc b3d5f0e9e258 
  util/tlm/sc_target.hh b3d5f0e9e258 
  util/tlm/sc_target.cc b3d5f0e9e258 
  util/tlm/sim_control.hh PRE-CREATION 
  util/tlm/tgen.cfg b3d5f0e9e258 
  util/tlm/tlm.py b3d5f0e9e258 
  util/tlm/tlm_elastic.py b3d5f0e9e258 

Diff: http://reviews.gem5.org/r/3527/diff/


Testing
---

The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
compile and run error free.


Thanks,

Christian Menard

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Re: [gem5-dev] Review Request 3480: misc: add a MasterId to the ExternalPort

2016-10-26 Thread Christian Menard


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3480/
---

(Updated Oct. 26, 2016, 4:06 p.m.)


Review request for Default.


Changes
---

updated the diff: rebased on 11691 and generated with mq


Repository: gem5


Description
---

The Request constructor requires a MasterID. However, an external transactor 
has no chance of getting a MasterID as it does not have a pointer to the 
System. This patch adds a MasterID to ExternalMaster in order to allow external 
modules to genrerate Packets.


Diffs (updated)
-

  src/mem/ExternalMaster.py b3d5f0e9e258 
  src/mem/external_master.hh b3d5f0e9e258 
  src/mem/external_master.cc b3d5f0e9e258 

Diff: http://reviews.gem5.org/r/3480/diff/


Testing
---

Used in a SystemC transactor


Thanks,

Christian Menard

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Re: [gem5-dev] Base cpu modification

2016-10-26 Thread Jason Lowe-Power

Hi,

What's the interface to the scratchpad? Are you adding new ISA extensions,
or is it a memory-mapped device. If it's a memory-mapped device, you should
be able to connect it to the CPU via the ports interface. Something like
add a crossbar between the CPU and the L1D and have the L1D only respond to
a subset of physical addresses and your scratchpad respond to the other
physical addresses.

If you're adding ISA extensions... I doubt you're going to convince us to
modify an ISA with non-standard extensions.

I guess my question is this: In a real implementation, what would the
interface be, and how much would you really need to modify the CPU
implementation? Again, it's best if you can find a way to decouple the
interface from a specific CPU implementation as much as possible.

The idea of a scratchpad is definitely interesting, and if we can find a
way to integrate your code as an optional device I think it would be good
to have in gem5!

Cheers,
Jason


On Wed, Oct 26, 2016 at 8:09 AM Pierre-Yves Péneau <
pierre-yves.pen...@lirmm.fr> wrote:

> Hi Jason,
>
> On 10/26/2016 12:27 AM, Jason Lowe-Power wrote:
> > Hello,
> >
> > Could you give us some more details on what you're proposing. What is
> this
> > "component"? Do you expect that many people in the community will
> need/want
> > to use this component? If so, then it may make sense to incorporate some
> > changes to the BaseCPU object.
>
> I would like to implement a generic scratchpad memory (SPM) module. For
> sure, not everyone will use these feature, but it's something lacking in
> gem5 (other simulator also). SPM are under investigation in the
> electronic research community for many years and I can't find a
> reasonably good implementation on the web.
>
> For now I am using an homemade implementation in gem5 but it's not clean
> enough to be published. I am thinking of refactoring my code and propose
> it to the community.
>
> > The way I see it is you have three high-level options:
> > 1) Make changes to the BaseCPU. This will likely be the most work to get
> > the community to accept. Unless it's a change that almost everyone will
> be
> > using, I doubt we will want to incorporate it.
> > 2) Make your changes very modular. Modular in the sense that if someone
> > wants to use gem5 without using your new component they'll never knew you
> > added it. This should be more that just adding a default "off" parameter.
> > The key goal is to be the least invasive as possible.
> > 3) Post your code on a fork of gem5. Sometimes you have to make major
> > modifications to central components to complete your research objective.
> In
> > this case, it may be better just to post your code somewhere like github.
> > Or to go the route we did with gem5-gpu and make it an "external"
> > component. Though this has the drawback of trying to keep it up to date
> > with the mainline.
>
> Thanks for the advices.
>
> > In conclusion, if you can give us more information we'll be able to guide
> > you better.
> >
> > Cheers,
> > Jason
> >
> > On Tue, Oct 25, 2016 at 9:29 AM Pierre-Yves Péneau <
> > pierre-yves.pen...@lirmm.fr> wrote:
> >
> >> Hi all,
> >>
> >> I would like to add a new hardware component in gem5. This component
> >> will be at the same level than L1 caches. I am planning to modify the
> >> base cpu to add a new port and use it to communicate with my component.
> >>
> >> Eventually, I would like to share my work with the gem5 community.
> >> Louisa Bessad (from my lab) had a discussion with Gabor Dozsa from ARM
> >> and told me that any modification to the base cpu must be strongly
> >> justified to the developers, and so could be very hard to merge in gem5.
> >>
> >> So, my questions are:
> >> - can I do what I want without modifying the base cpu ?
> >> - if not, what are the chances that my work will be accepted ?
> >>
> >> Thank you all.
> >>
> >> --
> >> +-+
> >> | Pierre-Yves Péneau - PhD student |  first.last at lirmm.fr  |
> >> | LIRMM / CNRS - SYSMIC team   |+ 33 4 67 41 86 33
> <+33%204%2067%2041%2086%2033>
> >> <+33%204%2067%2041%2086%2033>|
> >> | Building 4 Office H2.2   |http://walafc0.org|
> >> +-+
> >> ___
> >> gem5-dev mailing list
> >> gem5-dev@gem5.org
> >> http://m5sim.org/mailman/listinfo/gem5-dev
> >>
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
> >
>
> --
> +-+
> | Pierre-Yves Péneau - PhD student |  first.last at lirmm.fr  |
> | LIRMM / CNRS - SYSMIC team   |+ 33 4 67 41 86 33
> <+33%204%2067%2041%2086%2033>|
> | Building 4 Office H2.2   |http://walafc0.org|
> +-+
>

Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-26 Thread Andreas Hansson


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---



src/mem/cache/tags/base_set_assoc.hh (line 233)


If you don't mind changing it, could we keep the operator on the first line?

The same goes for the condition in the if statement.

I am not sure if this is actually captured in the style, but it is 
definitley convention.

The same goes for the copy in FA-LRU

Thanks!


- Andreas Hansson


On Oct. 25, 2016, 9:18 a.m., Sophiane SENNI wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
> 
> (Updated Oct. 25, 2016, 9:18 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:74be5cba513a
> ---
> mem: Split the hit_latency into tag_latency and data_latency
> 
> If the cache access mode is parallel, i.e. "sequential_access" parameter
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True",
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
> 
> 
> Diffs
> -
> 
>   configs/common/Caches.py 4aac82f10951 
>   configs/common/O3_ARM_v7a.py 4aac82f10951 
>   configs/example/arm/devices.py 4aac82f10951 
>   configs/learning_gem5/part1/caches.py 4aac82f10951 
>   src/mem/cache/Cache.py 4aac82f10951 
>   src/mem/cache/base.hh 4aac82f10951 
>   src/mem/cache/base.cc 4aac82f10951 
>   src/mem/cache/tags/Tags.py 4aac82f10951 
>   src/mem/cache/tags/base.hh 4aac82f10951 
>   src/mem/cache/tags/base.cc 4aac82f10951 
>   src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.cc 4aac82f10951 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> ---
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-10-26 Thread Cron Daemon

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic: 
passed.
* build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby: 
passed.* 
build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing: passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer:
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* 
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build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer:
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* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer:
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* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level:
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* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level:
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* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory:
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* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token:
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token:
 passed.* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
 * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
*

[gem5-dev] changeset in gem5: ruby: Allow multiple outstanding DMA requests

[gem5-dev] changeset in gem5: gpu-compute, arch: add some methods to the ba...

[gem5-dev] changeset in gem5: ruby: make a RequestDesc class instead of std...

[gem5-dev] changeset in gem5: hsail, gpu-compute: remove doGm/SmReturn add ...

[gem5-dev] changeset in gem5: gpu-compute, hsail: call discardFetch() from ...

[gem5-dev] changeset in gem5: dev: Add 'simLength' parameter in EthPacketData

[gem5-dev] changeset in gem5: gpu-compute, hsail: pass GPUDynInstPtr to get...

[gem5-dev] changeset in gem5: gpu-compute: use System cache line size in th...

[gem5-dev] changeset in gem5: gpu-compute: move disassemle() implementation...

[gem5-dev] changeset in gem5: gpu-compute: add gpu_isa.hh to switch hdrs, a...

[gem5-dev] changeset in gem5: gpu-compute: add instruction mix stats for th...

[gem5-dev] changeset in gem5: gpu-compute: support in-order data delivery i...

[gem5-dev] changeset in gem5: gpu-compute, hsail: make the PC a byte addres...

[gem5-dev] changeset in gem5: gpu-compute: remove inst enums and use bit fl...

[gem5-dev] SynchroTrace trace player on ReviewBoard

[gem5-dev] Review Request 3687: cpu: Add a SynchroTrace replay model

Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

Re: [gem5-dev] Review Request 3480: misc: add a MasterId to the ExternalPort

[gem5-dev] changeset in gem5: config: Break out base options for usage with...

[gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM slave port

Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

Re: [gem5-dev] Review Request 3480: misc: add a MasterId to the ExternalPort

Re: [gem5-dev] Base cpu modification

Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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