[gem5-dev] Change in gem5/gem5[develop]: arch: Delete a few unused vector register types/constants.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42003 )



Change subject: arch: Delete a few unused vector register types/constants.
..

arch: Delete a few unused vector register types/constants.

These are used internally in ARM, but dummy versions of them were being
published by all ISAs even though nobody was consuming them.

Change-Id: I93d9e53c503e375a2f901bb6f7f4c00a7cdadb20
---
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
8 files changed, 1 insertion(+), 30 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 86e3b83..432cccf 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -376,10 +376,7 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredReg = VecPredRegT;
-using DummyConstVecPredReg = VecPredRegT;
-using DummyVecPredRegContainer = DummyVecPredReg::Container;
-constexpr size_t DummyVecPredRegSizeBits = 8;
+using DummyVecPredRegContainer = VecPredRegContainer<8>;
 /// @}

 #endif  // __ARCH_GENERIC_VEC_PRED_REG_HH__
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 1f0df1c..caa2d34 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -264,8 +264,6 @@
 constexpr unsigned DummyNumVecElemPerVecReg = 2;
 using DummyVecRegContainer =
 VecRegContainer;
-constexpr size_t DummyVecRegSizeBytes = DummyNumVecElemPerVecReg *
-sizeof(DummyVecElem);
 /** @} */

 #endif /* __ARCH_GENERIC_VEC_REG_HH__ */
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 4ca73d8..a19b174 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -272,13 +272,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to MIPS
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 } // namespace MipsISA

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index aa01945..27a481e 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -51,13 +51,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to null
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 }

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 5f5f67b..5395149 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -41,13 +41,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to Power
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 126132f..445cef4 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -95,13 +95,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;

 // Not applicable to RISC-V
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
 using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;

 const int NumIntArchRegs = 32;
 const int NumMicroIntRegs = 1;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index bf92f02..73946db 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -42,13 +42,9 @@
 using VecElem = ::DummyVecElem;
 using VecRegContainer = ::DummyVecRegContainer;
 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = 

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,gpu-compute: Further simplify VecRegContainer.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41995 )



Change subject: arch,cpu,gpu-compute: Further simplify VecRegContainer.
..

arch,cpu,gpu-compute: Further simplify VecRegContainer.

Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/nativetrace.cc
M src/arch/arm/registers.hh
M src/arch/gcn3/operand.hh
M src/arch/gcn3/registers.hh
M src/arch/generic/vec_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/cpu/o3/rename_map.cc
M src/gpu-compute/wavefront.cc
16 files changed, 58 insertions(+), 191 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c7f82e0..c86cd17 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2348,15 +2348,6 @@
 }

 void
-ISA::zeroSveVecRegUpperPart(VecRegContainer , unsigned eCount)
-{
-auto vv = vc.as();
-for (int i = 2; i < eCount; ++i) {
-vv[i] = 0;
-}
-}
-
-void
 ISA::serialize(CheckpointOut ) const
 {
 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 7888229..62979fc 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -852,8 +852,16 @@

 unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *  
128; }


-static void zeroSveVecRegUpperPart(VecRegContainer ,
-   unsigned eCount);
+template 
+static void
+zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
+{
+static_assert(sizeof(Elem) <= sizeof(uint64_t));
+eCount *= (sizeof(uint64_t) / sizeof(Elem));
+for (int i = 16 / sizeof(Elem); i < eCount; ++i) {
+v[i] = 0;
+}
+}

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;
diff --git a/src/arch/arm/isa/templates/sve_mem.isa  
b/src/arch/arm/isa/templates/sve_mem.isa

index f635870..9b1ab84 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -170,7 +170,7 @@

 %(rden_code)s;

-fault = readMemAtomic(xc, EA, memData.raw_ptr(),
+fault = readMemAtomic(xc, EA, memData.as(),
 memAccessSize, this->memAccessFlags, rdEn);

 %(fault_code)s;
@@ -228,7 +228,7 @@
 auto memDataView = memData.as();

 if (xc->readMemAccPredicate()) {
-memcpy(memData.raw_ptr(), pkt->getPtr(),
+memcpy(memData.as(), pkt->getPtr(),
pkt->getSize());
 }

@@ -265,7 +265,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemAtomic(xc, memData.raw_ptr(),
+fault = writeMemAtomic(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -303,7 +303,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemTiming(xc, memData.raw_ptr(),
+fault = writeMemTiming(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -1001,7 +1001,7 @@
 auto memDataView = memData.as();

 if (fault == NoFault) {
-fault = readMemAtomic(xc, EA, memData.raw_ptr(),
+fault = readMemAtomic(xc, EA, memData.as(),
 memAccessSize, this->memAccessFlags,
 std::vector(memAccessSize, true));
 %(memacc_code)s;
@@ -1059,7 +1059,7 @@
 ArmISA::VecRegContainer memData;
 auto memDataView = memData.as();

-memcpy(memData.raw_ptr(), pkt->getPtr(),
+memcpy(memData.as(), pkt->getPtr(),
 pkt->getSize());

 if (fault == NoFault) {
@@ -1100,7 +1100,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemAtomic(xc, memData.raw_ptr(),
+fault = writeMemAtomic(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

@@ -1138,7 +1138,7 @@
 }

 if (fault == NoFault) {
-fault = writeMemTiming(xc, memData.raw_ptr(),
+fault = writeMemTiming(xc, memData.as(),
 EA, memAccessSize, this->memAccessFlags, nullptr, wrEn);
 }

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 7075adb..f37ee4d 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -126,8 +126,7 @@
 changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);

 for (int i = 0; i < NumVecV7ArchRegs; i++) {
-auto vec(tc->readVecReg(RegId(VecRegClass,i))
-

[gem5-dev] Change in gem5/gem5[develop]: cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42001 )



Change subject: cpu: Use the built in << for VecReg and VecPredReg in  
ExeTrace.

..

cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.

There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
---
M src/cpu/exetrace.cc
1 file changed, 2 insertions(+), 23 deletions(-)



diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 76db4d7..cf4a734 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -116,31 +116,10 @@
 if (Debug::ExecResult && data_status != DataInvalid) {
 switch (data_status) {
   case DataVec:
-{
-ccprintf(outs, " D=0x[");
-auto dv = data.as_vec->as();
-for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
- i--) {
-ccprintf(outs, "%08x", dv[i]);
-if (i != 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_vec);
 break;
   case DataVecPred:
-{
-ccprintf(outs, " D=0b[");
-auto pv = data.as_pred->as();
-for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0;  
i--) {

-ccprintf(outs, pv[i] ? "1" : "0");
-if (i != 0 && i % 4 == 0) {
-ccprintf(outs, "_");
-}
-}
-ccprintf(outs, "]");
-}
+ccprintf(outs, " D=%s", *data.as_pred);
 break;
   default:
 ccprintf(outs, " D=%#018x", data.as_int);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42001
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I092c28143de286d765312122b81ce865a5184091
Gerrit-Change-Number: 42001
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Don't needlessly recreate ISA types in InstRecord.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42002 )



Change subject: sim: Don't needlessly recreate ISA types in InstRecord.
..

sim: Don't needlessly recreate ISA types in InstRecord.

The ISAs already define fully realized types. We don't need to
separately track what parameters they used and then feed them into the
same templates again elsewhere.

Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
---
M src/sim/insttracer.hh
1 file changed, 6 insertions(+), 7 deletions(-)



diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 636bf76..a2ecad4 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -94,8 +94,8 @@
 union {
 uint64_t as_int;
 double as_double;
-::VecRegContainer* as_vec;
-::VecPredRegContainer* as_pred;
+TheISA::VecRegContainer* as_vec;
+TheISA::VecPredRegContainer* as_pred;
 } data;

 /** @defgroup fetch_seq
@@ -201,17 +201,16 @@
 void setData(double d) { data.as_double = d; data_status = DataDouble;  
}


 void
-setData(::VecRegContainer& d)
+setData(TheISA::VecRegContainer& d)
 {
-data.as_vec = new ::VecRegContainer(d);
+data.as_vec = new TheISA::VecRegContainer(d);
 data_status = DataVec;
 }

 void
-setData(::VecPredRegContainer& d)
+setData(TheISA::VecPredRegContainer& d)
 {
-data.as_pred =
-new ::VecPredRegContainer(d);
+data.as_pred = new TheISA::VecPredRegContainer(d);
 data_status = DataVecPred;
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42002
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
Gerrit-Change-Number: 42002
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Separate printing and serialization of VecPredReg.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41999 )



Change subject: arch,cpu: Separate printing and serialization of VecPredReg.
..

arch,cpu: Separate printing and serialization of VecPredReg.

This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
---
M src/arch/generic/vec_pred_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 37 insertions(+), 29 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 6db0e1e..cdf5eb5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -44,6 +44,7 @@
 #include 

 #include "base/cprintf.hh"
+#include "sim/serialize_handlers.hh"

 template 
 class VecPredRegContainer;
@@ -145,18 +146,13 @@
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& p)
 {
-// 0-sized is not allowed
-os << '[' << p.container[0];
-for (int i = 0; i < p.NUM_BITS; ++i) {
-os << " " << (p.container[i] ? 1 : 0);
-}
-os << ']';
+// Size must be greater than 0.
+for (int i = 0; i < NUM_BITS; i++)
+ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ccprintf(os, "]");
 return os;
 }

-/// Returns a string representation of the register content.
-const std::string print() const { return csprintf("%s", *this); }
-
 /// Returns true if the first active element of the register is true.
 /// @param mask Input mask used to filter the predicates to be tested.
 /// @param actual_num_elems Actual number of vector elements  
considered for

@@ -318,18 +314,18 @@
 }
 }

-/// Returns a string representation of the register content.
-const std::string print() const { return csprintf("%s", *this); }
-
 friend std::ostream&
-operator<<(std::ostream& os, const MyClass& v)
+operator<<(std::ostream& os, const MyClass& p)
 {
-for (auto b: v.container) {
-os << csprintf("%d", b);
-}
+// Size must be greater than 0.
+for (int i = 0; i < NumBits; i++)
+ccprintf(os, "%s%d", i ? " " : "[", (int)p.container[i]);
+ccprintf(os, "]");
 return os;
 }

+friend ShowParam>;
+
 /// Create a view of this container.
 ///
 /// If NumElems is provided, the size of the container is  
bounds-checked,

@@ -359,17 +355,29 @@
 /// @}
 };

-/// Helper functions used for serialization/de-serialization
 template 
-inline bool
-to_number(const std::string& value, VecPredRegContainer& p)
+struct ParseParam>
 {
-int i = 0;
-for (const auto& c: value) {
-p[i] = (c == '1');
+static bool
+parse(const std::string , VecPredRegContainer )
+{
+int i = 0;
+for (const auto& c: s)
+value[i++] = (c == '1');
+return true;
 }
-return true;
-}
+};
+
+template 
+struct ShowParam>
+{
+static void
+show(std::ostream , const VecPredRegContainer )
+{
+for (auto b: value.container)
+ccprintf(os, "%d", b);
+}
+};

 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 6c6b9b3..65a5338 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -238,7 +238,7 @@

 DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
 "data %s\n", int(phys_reg->index()),
-vecPredRegFile[phys_reg->index()].print());
+vecPredRegFile[phys_reg->index()]);

 return vecPredRegFile[phys_reg->index()];
 }
@@ -322,7 +322,7 @@
 assert(phys_reg->isVecPredPhysReg());

 DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-int(phys_reg->index()), val.print());
+int(phys_reg->index()), val);

 vecPredRegFile[phys_reg->index()] = val;
 }
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8f65ea3..7a4a4b7 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -330,7 +330,7 @@
 const TheISA::VecPredRegContainer& regVal =
 readVecPredRegFlat(flatIndex);
 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -343,7 +343,7 @@
 getWritableVecPredRegFlat(flatIndex);
 DPRINTF(VecPredRegs,
 "Reading predicate reg %d (%d) as %s for modify.\n",
-reg.index(), flatIndex, regVal.print());
+reg.index(), flatIndex, regVal);
 return regVal;
 }

@@ -410,7 +410,7 @@
 

[gem5-dev] Change in gem5/gem5[develop]: arch: Remove unnecessary "typename"s from VecPredRegT.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41998 )



Change subject: arch: Remove unnecessary "typename"s from VecPredRegT.
..

arch: Remove unnecessary "typename"s from VecPredRegT.

Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index e932418..6db0e1e 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -83,14 +83,14 @@

 /// Reset the register to an all-false value.
 template
-typename std::enable_if_t reset() {  
container.reset(); }

+std::enable_if_t reset() { container.reset(); }

 /// Reset the register to an all-true value.
 template
-typename std::enable_if_t set() { container.set(); }
+std::enable_if_t set() { container.set(); }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator=(const MyClass& that)
 {
 container = that.container;
@@ -104,7 +104,7 @@
 }

 template
-typename std::enable_if_t
+std::enable_if_t
 operator[](size_t idx)
 {
 return container[idx * sizeof(VecElem)];
@@ -120,7 +120,7 @@

 /// Write a raw value in an element of the predicate register
 template
-typename std::enable_if_t
+std::enable_if_t
 set_raw(size_t idx, uint8_t val)
 {
 container.set_bits(idx * sizeof(VecElem), sizeof(VecElem), val);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41998
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
Gerrit-Change-Number: 41998
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Get rid of unused "Packed" vector predicate registers.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41996 )



Change subject: arch,sim: Get rid of unused "Packed" vector predicate  
registers.

..

arch,sim: Get rid of unused "Packed" vector predicate registers.

Change-Id: Iecff7476bbd775e113788ced469fe85a467feede
---
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/registers.hh
M src/arch/arm/types.hh
M src/arch/generic/vec_pred_reg.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/registers.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
M src/sim/insttracer.hh
11 files changed, 50 insertions(+), 78 deletions(-)



diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 03775ca..354fe65 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -2396,8 +2396,8 @@
 extraPrologCode = ''
 if isFlagSetting:
 code += '''
-VecPredRegT::Container  
c;
-VecPredRegT  
predOnes(c);

+VecPredRegT::Container c;
+VecPredRegT predOnes(c);
 for (unsigned i = 0; i < eCount; i++) {
 predOnes[i] = 1;
 }
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 62fb0d3..663b83a 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -61,10 +61,8 @@
 using VecRegContainer =
 ::VecRegContainer;

-using VecPredReg = ::VecPredRegT;
-using ConstVecPredReg = ::VecPredRegT;
+using VecPredReg = ::VecPredRegT;
+using ConstVecPredReg = ::VecPredRegT;
 using VecPredRegContainer = VecPredReg::Container;

 // Constants Related to the number of registers
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index fa877be..f2c997f 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -817,7 +817,6 @@

 constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
 constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes;
-constexpr unsigned VecPredRegHasPackedRepr = false;
 } // namespace ArmISA

 #endif
diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 84047f6..67ee9e5 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -43,7 +43,7 @@
 #include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"

-template 
+template 
 class VecPredRegContainer;

 /// Predicate register view.
@@ -54,32 +54,25 @@
 /// templated on the vector element type to simplify ISA definitions.
 /// @tparam VecElem Type of the vector elements.
 /// @tparam NumElems Number of vector elements making up the view.
-/// @tparam Packed True if the predicate register relies on a packed
-/// representation, i.e. adjacent bits refer to different vector elements
-/// irrespective of the vector element size (e.g. this is the case for
-/// AVX-512). If false, the predicate register relies on an unpacked
-/// representation, where each bit refers to the corresponding byte in a  
vector

-/// register (e.g. this is the case for ARM SVE).
 /// @tparam Const True if the underlying container can be modified through
 /// the view.
-template 
+template 
 class VecPredRegT
 {
   protected:
 /// Size of the register in bits.
-static constexpr size_t NUM_BITS = Packed ? NumElems :
-sizeof(VecElem) * NumElems;
+static constexpr size_t NUM_BITS = sizeof(VecElem) * NumElems;

   public:
 /// Container type alias.
 using Container = typename std::conditional<
 Const,
-const VecPredRegContainer,
-VecPredRegContainer>::type;
+const VecPredRegContainer,
+VecPredRegContainer>::type;

   protected:
 // Alias for this type
-using MyClass = VecPredRegT;
+using MyClass = VecPredRegT;
 /// Container corresponding to this view.
 Container& container;

@@ -88,13 +81,11 @@

 /// Reset the register to an all-false value.
 template
-typename std::enable_if_t
-reset() { container.reset(); }
+typename std::enable_if_t reset() {  
container.reset(); }


 /// Reset the register to an all-true value.
 template
-typename std::enable_if_t
-set() { container.set(); }
+typename std::enable_if_t set() { container.set(); }

 template
 typename std::enable_if_t
@@ -107,14 +98,14 @@
 const bool&
 operator[](size_t idx) const
 {
-return container[idx * (Packed ? 1 : sizeof(VecElem))];
+return container[idx * sizeof(VecElem)];
 }

 template
 typename std::enable_if_t
 operator[](size_t idx)
 {
-return container[idx * (Packed ? 1 : sizeof(VecElem))];
+return container[idx * sizeof(VecElem)];
 }

 /// Return an element of the predicate register as it appears
@@ -122,8 +113,7 @@
 uint8_t
 get_raw(size_t idx) const
 {
-return 

[gem5-dev] Change in gem5/gem5[develop]: arch: Collapse unused size parameter from "as" VecPredReg method.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42000 )



Change subject: arch: Collapse unused size parameter from "as" VecPredReg  
method.

..

arch: Collapse unused size parameter from "as" VecPredReg method.

Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 6 insertions(+), 12 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index cdf5eb5..86e3b83 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -333,24 +333,18 @@
 /// @tparam VecElem Type of the vector elements.
 /// @tparam NumElems Number of vector elements making up the view.
 /// @{
-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as() const
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTtrue>(*this);

 }

-template sizeof(VecElem)>

-VecPredRegT
+template 
+VecPredRegT
 as()
 {
-static_assert(NumBits % sizeof(VecElem) == 0 &&
-  sizeof(VecElem) * NumElems <= NumBits,
-  "Container size incompatible with view size");
-return VecPredRegT(*this);
+return VecPredRegTfalse>(*this);

 }
 /// @}
 };

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42000
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
Gerrit-Change-Number: 42000
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Stop using << and to_number for VecReg serialization.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41994 )



Change subject: arch,cpu: Stop using << and to_number for VecReg  
serialization.

..

arch,cpu: Stop using << and to_number for VecReg serialization.

Override ParseParam<>::parse and ShowParam<>::parse directly. This will
allow using a different format for serializing and displaying registers.

Also get rid of the print() methods. When any cprintf based mechanism is
used (like DPRINTF), the underlying mechanism will use << to output the
value. Since we already override <<, there's no reason to wrap that in a
method which calls csprintf which calls << anyway.

Change-Id: Id65b9a657507f2f2cdf9673fd961cfeb0590f48c
---
M src/arch/generic/vec_reg.hh
M src/cpu/o3/regfile.hh
M src/cpu/simple_thread.hh
3 files changed, 38 insertions(+), 44 deletions(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index c8e7938..48cd4bd 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -97,14 +97,13 @@
 #define __ARCH_GENERIC_VEC_REG_HH__

 #include 
-#include 
 #include 
 #include 
 #include 
-#include 

 #include "base/cprintf.hh"
 #include "base/logging.hh"
+#include "sim/serialize_handlers.hh"

 constexpr unsigned MaxVecRegLenInBytes = 4096;

@@ -175,8 +174,6 @@
 return os;
 }

-const std::string print() const { return csprintf("%s", *this); }
-
 /**
  * Cast to VecRegContainer&
  * It is useful to get the reference to the container for ISA tricks,
@@ -211,12 +208,6 @@
   public:
 VecRegContainer() {}
 VecRegContainer(const VecRegContainer &) = default;
-/* This is required for de-serialisation. */
-VecRegContainer(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), [0], SIZE);
-}

 /** Zero the container. */
 void zero() { memset(container.data(), 0, SIZE); }
@@ -239,17 +230,6 @@
 std::memcpy(container.data(), that.data(), SIZE);
 return *this;
 }
-
-/** From vector.
- * This is required for de-serialisation.
- * */
-MyClass&
-operator=(const std::vector& that)
-{
-assert(that.size() >= SIZE);
-std::memcpy(container.data(), that.data(), SIZE);
-return *this;
-}
 /** @} */

 /** Equality operator.
@@ -272,7 +252,6 @@
 return !operator==(that);
 }

-const std::string print() const { return csprintf("%s", *this); }
 /** Get pointer to bytes. */
 template 
 const Ret* raw_ptr() const { return (const Ret*)container.data(); }
@@ -313,19 +292,20 @@
 return VecRegT(*this);
 }

-/** @} */
-/**
- * Output operator.
- * Used for serialization.
- */
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& v)
 {
 for (auto& b: v.container) {
-os << csprintf("%02x", b);
+ccprintf(os, "%02x", b);
 }
 return os;
 }
+
+/** @} */
+/**
+ * Used for serialization.
+ */
+friend ShowParam;
 };

 /**
@@ -333,20 +313,34 @@
  */
 /** @{ */
 template 
-inline bool
-to_number(const std::string& value, VecRegContainer& v)
+struct ParseParam>
 {
-fatal_if(value.size() > 2 * VecRegContainer::size(),
- "Vector register value overflow at unserialize");
+static bool
+parse(const std::string , VecRegContainer )
+{
+fatal_if(s.size() > 2 * Sz,
+ "Vector register value overflow at unserialize");

-for (int i = 0; i < VecRegContainer::size(); i++) {
-uint8_t b = 0;
-if (2 * i < value.size())
-b = stoul(value.substr(i * 2, 2), nullptr, 16);
-v.template raw_ptr()[i] = b;
+for (int i = 0; i < Sz; i++) {
+uint8_t b = 0;
+if (2 * i < value.size())
+b = stoul(s.substr(i * 2, 2), nullptr, 16);
+value.template raw_ptr()[i] = b;
+}
+return true;
 }
-return true;
-}
+};
+
+template 
+struct ShowParam>
+{
+static void
+show(std::ostream , const VecRegContainer )
+{
+for (auto& b: value.container)
+ccprintf(os, "%02x", b);
+}
+};
 /** @} */

 /**
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 71f2e72..6c6b9b3 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -203,7 +203,7 @@

 DPRINTF(IEW, "RegFile: Access to vector register %i, has "
 "data %s\n", int(phys_reg->index()),
-vectorRegFile[phys_reg->index()].print());
+vectorRegFile[phys_reg->index()]);

 return vectorRegFile[phys_reg->index()];
 }
@@ -296,7 +296,7 @@
 assert(phys_reg->isVectorPhysReg());

 DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
-int(phys_reg->index()), val.print());
+

[gem5-dev] Change in gem5/gem5[develop]: arch: Break the dependence between (non)-predicate vector regs.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41997 )



Change subject: arch: Break the dependence between (non)-predicate vector  
regs.

..

arch: Break the dependence between (non)-predicate vector regs.

Change-Id: I6c3cd7c1ce9c5d509c332be9bfc107a329f1
---
M src/arch/generic/vec_pred_reg.hh
1 file changed, 5 insertions(+), 6 deletions(-)



diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index 67ee9e5..e932418 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -38,9 +38,11 @@

 #include 
 #include 
+#include 
+#include 
+#include 
 #include 

-#include "arch/generic/vec_reg.hh"
 #include "base/cprintf.hh"

 template 
@@ -372,11 +374,8 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredReg = VecPredRegT;
-using DummyConstVecPredReg = VecPredRegT;
+using DummyVecPredReg = VecPredRegT;
+using DummyConstVecPredReg = VecPredRegT;
 using DummyVecPredRegContainer = DummyVecPredReg::Container;
 constexpr size_t DummyVecPredRegSizeBits = 8;
 /// @}

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41997
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c3cd7c1ce9c5d509c332be9bfc107a329f1
Gerrit-Change-Number: 41997
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Simplify and correct style of VecReg types.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41993 )



Change subject: arch: Simplify and correct style of VecReg types.
..

arch: Simplify and correct style of VecReg types.

Change-Id: Ib15d2e03c3e9cabcf56b316d5c57d2e892ad255d
---
M src/arch/generic/vec_reg.hh
1 file changed, 23 insertions(+), 63 deletions(-)



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index 7828108..c8e7938 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -125,12 +125,14 @@
 template 
 class VecRegT
 {
+  private:
 /** Size of the register in bytes. */
 static constexpr inline size_t
 size()
 {
 return sizeof(VecElem) * NumElems;
 }
+
   public:
 /** Container type alias. */
 using Container = typename std::conditional
-typename std::enable_if_t
-zero() { container.zero(); }
-
-template
-typename std::enable_if_t
-operator=(const MyClass& that)
-{
-container = that.container;
-return *this;
-}
-
 /** Index operator. */
-const VecElem& operator[](size_t idx) const
+const VecElem &
+operator[](size_t idx) const
 {
 return container.template raw_ptr()[idx];
 }
@@ -173,25 +163,6 @@
 return container.template raw_ptr()[idx];
 }

-/** Equality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator==(const VecRegT& that) const
-{
-return container == that.container;
-}
-/** Inequality operator.
- * Required to compare thread contexts.
- */
-template
-bool
-operator!=(const VecRegT& that) const
-{
-return !operator==(that);
-}
-
 /** Output stream operator. */
 friend std::ostream&
 operator<<(std::ostream& os, const MyClass& vr)
@@ -205,6 +176,7 @@
 }

 const std::string print() const { return csprintf("%s", *this); }
+
 /**
  * Cast to VecRegContainer&
  * It is useful to get the reference to the container for ISA tricks,
@@ -223,10 +195,11 @@
 template 
 class VecRegContainer
 {
-  static_assert(SIZE > 0,
-  "Cannot create Vector Register Container of zero size");
-  static_assert(SIZE <= MaxVecRegLenInBytes,
-  "Vector Register size limit exceeded");
+  private:
+static_assert(SIZE > 0,
+"Cannot create Vector Register Container of zero size");
+static_assert(SIZE <= MaxVecRegLenInBytes,
+"Vector Register size limit exceeded");
   public:
 static constexpr inline size_t size() { return SIZE; };
 using Container = std::array;
@@ -251,16 +224,17 @@
 /** Assignment operators. */
 /** @{ */
 /** From VecRegContainer */
-MyClass& operator=(const MyClass& that)
+MyClass&
+operator=(const MyClass& that)
 {
 if ( == this)
 return *this;
-memcpy(container.data(), that.container.data(), SIZE);
-return *this;
+return *this = that.container;
 }

 /** From appropriately sized uint8_t[]. */
-MyClass& operator=(const Container& that)
+MyClass&
+operator=(const Container& that)
 {
 std::memcpy(container.data(), that.data(), SIZE);
 return *this;
@@ -269,7 +243,8 @@
 /** From vector.
  * This is required for de-serialisation.
  * */
-MyClass& operator=(const std::vector& that)
+MyClass&
+operator=(const std::vector& that)
 {
 assert(that.size() >= SIZE);
 std::memcpy(container.data(), that.data(), SIZE);
@@ -277,24 +252,6 @@
 }
 /** @} */

-/** Copy the contents into the input buffer. */
-/** @{ */
-/** To appropriately sized uint8_t[] */
-void copyTo(Container& dst) const
-{
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-
-/** To vector
- * This is required for serialisation.
- * */
-void copyTo(std::vector& dst) const
-{
-dst.resize(SIZE);
-std::memcpy(dst.data(), container.data(), SIZE);
-}
-/** @} */
-
 /** Equality operator.
  * Required to compare thread contexts.
  */
@@ -335,7 +292,8 @@
  */
 /** @{ */
 template 
-VecRegT as() const
+VecRegT
+as() const
 {
 static_assert(SIZE % sizeof(VecElem) == 0,
 "VecElem does not evenly divide the register size");
@@ -345,7 +303,8 @@
 }

 template 
-VecRegT as()
+VecRegT
+as()
 {
 static_assert(SIZE % sizeof(VecElem) == 0,
 "VecElem does not evenly divide the register size");
@@ -359,7 +318,8 @@
  * Output operator.
  * Used for serialization.
  */
-friend std::ostream& operator<<(std::ostream& os, const MyClass& v)
+friend std::ostream&
+operator<<(std::ostream& os, const MyClass& v)
 {
 for (auto& b: v.container) {
  

[gem5-dev] Re: vector register indexing modes and renaming?

[Gabe Black via gem5-dev]

Another question/clarification:

Does any data actually get shared between the two rename modes? I think you
said there is not, but now I can't find that. Would it work just as well to
have two register files which operate entirely independently? From what I
can tell the "V" registers of Neon in aarch64 overlap with the SVE
registers, and the "Q" registers of armv7 Neon overlap with the "S", "D",
"Q" registers of the same, but I think "V" and "Q" are independent? Maybe
reused but not guaranteed to alias?

BTW, test cases would be very helpful if possible. I've made good progress
cleaning away debris and am getting to the point where I'll want to make
changes which I'm a lot less comfortable making blind.

Gabe

On Thu, Feb 25, 2021 at 10:40 PM Gabe Black  wrote:

> I will ask within Arm if there's something we can provide to you.
>>> In the meantime I gave a quick look at NEON enabled libraries [1]; the
>>> Ne10 library provides a set of functions optimized for NEON  and a set
>>> of examples making use of it [2] (e.g FIR filter, GEMM etc etc).
>>>
>>> You could probably cross-compile those examples and use them in SE mode
>>> (recommending to use the O3 model)
>>>
>>
>>
>> Ok, thanks, I'll take a look. This might even be something we want in the
>> testing infrastructure? I might look into that when I have a chance.
>>
>
> I took a look at this, and unfortunately I don't think I can use it. The
> example only builds for armv7 and not aarch64, and when I tried to build it
> for armv7 I get a bunch of compiler errors. Do you have any other
> suggestions?
>
> Gabe
>
>>
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Explicitly set driver to NULL in constructor

[Kyle Roarty (Gerrit) via gem5-dev]

Kyle Roarty has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41973 )



Change subject: gpu-compute: Explicitly set driver to NULL in constructor
..

gpu-compute: Explicitly set driver to NULL in constructor

We have a fail_if in attachDriver to prevent driver from being
overwritten. However, the fail_if only checks for if the driver
is not NULL.

Previously in some cases, driver was set to garbage, which made
the fail_if trip the first time we were assigning the driver.

This patch explicitly sets driver to NULL in the constructor, thus
ensuring that it will be NULL the first time we call attachDriver

Change-Id: I325f6033e785025a912e3af3888c66cee0332f40
---
M src/gpu-compute/gpu_command_processor.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/gpu-compute/gpu_command_processor.cc  
b/src/gpu-compute/gpu_command_processor.cc

index da21076..4901a93 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -42,7 +42,7 @@
 #include "sim/syscall_emul_buf.hh"

 GPUCommandProcessor::GPUCommandProcessor(const Params )
-: HSADevice(p), dispatcher(*p.dispatcher)
+: HSADevice(p), dispatcher(*p.dispatcher), driver(NULL)
 {
 dispatcher.setCommandProcessor(this);
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41973
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I325f6033e785025a912e3af3888c66cee0332f40
Gerrit-Change-Number: 41973
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Re: Build failed in Jenkins: Weekly #9

[Kyle Roarty via gem5-dev]

I believe I've got the issue sorted for now.

The fail_if was simply checking if the driver was set to a not-null value, 
however, we didn't explicitly set the driver to null anywhere.

Now, the thing that's more interesting is that on certain processors, the 
driver was still null the first time we assigned it, whereas on others it 
wasn't. In particular, on a 3600 and 3900x, driver was still null. On other 
ones (a 1950x, whatever Bobby has, whatever Jenkins is using), it wasn't. Also, 
building for .opt vs .debug impacted if driver was null or not (.opt had the 
issue, .debug didn't).

Either way, explicitly setting driver to null in the constructor of 
GPUCommandProcessor fixes this. I'll post a patch right after sending this.

Kyle

From: Matt Sinclair 
Sent: Friday, February 26, 2021 4:21 PM
To: gem5 Developer List 
Cc: Kyle Roarty ; Bobby Bruce 
Subject: Re: [gem5-dev] Re: Build failed in Jenkins: Weekly #9

Just an FYI Bobby, it appears this commit: 
https://gem5-review.googlesource.com/c/public/gem5/+/39298 from you is the 
culprit from us bisecting the commits to find where this error occurs.

No idea why that would be attempting to reset the GPU driver.  We are still 
digging.

Matt

On Fri, Feb 26, 2021 at 2:03 PM Bobby Bruce via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
The script running on Jenkins is as follows:

```
docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd) 
gcr.io/gem5-test/gcn-gpu:latest \
bash -c "scons build/GCN3_X86/gem5.opt -j50 || (rm -rf build && scons 
build/GCN3_X86/gem5.opt -j50)"

wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square.o

mkdir -p tests/testing-results

docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd) 
gcr.io/gem5-test/gcn-gpu:latest \
build/GCN3_X86/gem5.opt configs/example/apu_se.py -n2 -c square.o
```

When I run this on my machine the bug is reproduced.

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 26, 2021 at 12:01 PM Kyle Roarty 
mailto:kroa...@wisc.edu>> wrote:
Hi Bobby,

I've been trying to replicate it myself, but I've had no luck doing so.

I built using the same commit (e100156a51deda7f50873faba069c2c3a6cde2e7) and 
command that were shown in the build log. I also used the pre-built square 
binary from dist.gem5, and used the same run command as shown in the build log.

There's only been like 1 change to the GCN/gpu-compute stuff since the last 
passing test (#6, although #7 didn't actually run square, it failed due to 
build timeout), and it doesn't touch anything related to that assert. My guess 
is the scons changes over the past few weeks somehow caused the failure, but 
I'm not sure why I'm not able to replicate the issue.

Are you building with the same commands as in the build log? If not, can you 
post them so that I can try to reproduce?

Kyle

From: Bobby Bruce mailto:bbr...@ucdavis.edu>>
Sent: Friday, February 26, 2021 1:28 PM
To: gem5 Developer List mailto:gem5-dev@gem5.org>>; Matt 
Sinclair mailto:msincl...@wisc.edu>>; Kyle Roarty 
mailto:kroa...@wisc.edu>>
Subject: Re: [gem5-dev] Build failed in Jenkins: Weekly #9

Matt, Kyle

The weekly tests are failing with a "fatal: fatal condition driver occurred: 
Should not overwrite driver." error." when running the GCN3 square tests. I've 
managed to recreate this issue on my end, so it appears to be genuine.

Could you look into this?

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 26, 2021 at 1:02 AM jenkins-no-reply--- via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
See 

Changes:

[gabe.black] cpu,mem: Add or remove parenthesis to make the compiler happy.

[gabe.black] misc: Fix mismatched struct/class "tags" and reenable that warning.

[baz21] arch-arm,sim: make compile on FreeBSD

[Giacomo Travaglini] base: Exclude the end of ChannelAddrRange

[Giacomo Travaglini] base: Remove duplicate isPow2 helper

[gabe.black] arch,cpu: Move getExecutingAsid to the ISA class.

[tiago.muck] mem-ruby: extended transaction profiling

[tiago.muck] mem-ruby: alternative interface for func. reads

[gabe.black] arm,kern: Stop using the getArgument function for kernel events.

[odanrc] base: Fix scientific number conversion in base/str

[odanrc] base: Clean up base/hostinfo

[odanrc] base: Remove hostname from hostinfo

[gabe.black] arch: Eliminate the getArgument function.

[Giacomo Travaglini] misc: Use PARAMS

[Giacomo Travaglini] misc: Remove unused params() definitions

[Bobby R. Bruce] base-stats,python: Expose DistInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose VectorInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose FormulaInfo via PyBind11

[Bobby R. Bruce] 

[gem5-dev] Change in gem5/gem5[develop]: base-stats,python: Add Python Stats

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38615 )


Change subject: base-stats,python: Add Python Stats
..

base-stats,python: Add Python Stats

This model is used to store and represent the "new" hierarchical stats
at the Python level. Over time these classes may be extended with
functions to ease in the analysis of gem5 stats. Though, for this
commit, such functions have been kept to a minimum.

`m5/pystats/loader.py` contains functions for translating the gem5   
`_m5.stats`

statistics exposed via Pybind11 to the Python Stats model. For example:

```
import m5.pystats.gem5stats as gem5stats

simstat = gem5stats.get_simstat(root)
```

All the python Stats model classes inherit from JsonSerializable meaning
they can be translated to JSON. For example:

```
import m5.pystats.gem5stats as gem5stats

simstat = gem5stats.get_simstat(root)
with open('test.json', 'w') as f:
simstat.dump(f)
```

The stats have also been exposed via the python statistics API. Via
command line, a JSON output may be specified with the argument
`--stats-file json://`.

Change-Id: I253a869f6b6d8c0de4dbed708892ee0cc33c5665
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38615
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/SConscript
A src/python/m5/ext/pystats/__init__.py
A src/python/m5/ext/pystats/group.py
A src/python/m5/ext/pystats/jsonserializable.py
A src/python/m5/ext/pystats/simstat.py
A src/python/m5/ext/pystats/statistic.py
A src/python/m5/ext/pystats/storagetype.py
A src/python/m5/ext/pystats/timeconversion.py
M src/python/m5/stats/__init__.py
A src/python/m5/stats/gem5stats.py
10 files changed, 945 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/SConscript b/src/python/SConscript
index 19f260a..57d5578 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -64,6 +64,15 @@
 PySource('m5.ext.pyfdt', 'm5/ext/pyfdt/pyfdt.py')
 PySource('m5.ext.pyfdt', 'm5/ext/pyfdt/__init__.py')

+PySource('m5.ext.pystats', 'm5/ext/pystats/__init__.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/jsonserializable.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/group.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/simstat.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/statistic.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/storagetype.py')
+PySource('m5.ext.pystats', 'm5/ext/pystats/timeconversion.py')
+PySource('m5.stats', 'm5/stats/gem5stats.py')
+
 Source('pybind11/core.cc', add_tags='python')
 Source('pybind11/debug.cc', add_tags='python')
 Source('pybind11/event.cc', add_tags='python')
diff --git a/src/python/m5/ext/pystats/__init__.py  
b/src/python/m5/ext/pystats/__init__.py

new file mode 100644
index 000..4ffac9a
--- /dev/null
+++ b/src/python/m5/ext/pystats/__init__.py
@@ -0,0 +1,41 @@
+# Copyright (c) 2020 The Regents of The University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from .jsonserializable import JsonSerializable
+from .group import Group
+from .simstat import SimStat
+from .statistic import Statistic
+from .storagetype import StorageType
+from .timeconversion import TimeConversion
+
+__all__ = [
+   "Group",
+   

[gem5-dev] Change in gem5/gem5[develop]: base-stats,python: Expose a stat's unit via PyBind11

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41753 )


Change subject: base-stats,python: Expose a stat's unit via PyBind11
..

base-stats,python: Expose a stat's unit via PyBind11

Change-Id: I77df868a6bc92e5bb0a39592b5aca8e0d259bb05
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41753
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/python/pybind11/stats.cc
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1e6773f..f1b1e9c 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -132,6 +132,9 @@
 py::class_>(
 m, "Info")
 .def_readwrite("name", ::Info::name)
+.def_property_readonly("unit", [](const Stats::Info ) {
+return info.unit->getUnitString();
+})
 .def_readonly("desc", ::Info::desc)
 .def_readonly("id", ::Info::id)
 .def_property_readonly("flags", [](const Stats::Info ) {



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41753
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I77df868a6bc92e5bb0a39592b5aca8e0d259bb05
Gerrit-Change-Number: 41753
Gerrit-PatchSet: 8
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base-stats,python: Add Units to the Python Stats

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41754 )


Change subject: base-stats,python: Add Units to the Python Stats
..

base-stats,python: Add Units to the Python Stats

Change-Id: Ic8d3c9a5c2bb7fbe51b8672b74b0e5fb17906a5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41754
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/python/m5/stats/gem5stats.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/stats/gem5stats.py  
b/src/python/m5/stats/gem5stats.py

index 3afc776..9446045 100644
--- a/src/python/m5/stats/gem5stats.py
+++ b/src/python/m5/stats/gem5stats.py
@@ -148,7 +148,7 @@

 def __get_scaler(statistic: _m5.stats.ScalarInfo) -> Scalar:
 value = statistic.value
-unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850.
+unit = statistic.unit
 description = statistic.desc
 # ScalarInfo uses the C++ `double`.
 datatype = StorageType["f64"]
@@ -161,7 +161,7 @@
  )

 def __get_distribution(statistic: _m5.stats.DistInfo) -> Distribution:
-unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850.
+unit = statistic.unit
 description = statistic.desc
 value = statistic.values
 bin_size = statistic.bucket_size
@@ -198,7 +198,7 @@
 for index in range(statistic.size):
 # All the values in a Vector are Scalar values
 value = statistic.value[index]
-unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850.
+unit = statistic.unit
 description = statistic.subdescs[index]
 # ScalarInfo uses the C++ `double`.
 datatype = StorageType["f64"]



4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41754
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic8d3c9a5c2bb7fbe51b8672b74b0e5fb17906a5e
Gerrit-Change-Number: 41754
Gerrit-PatchSet: 7
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Fixed System "work_item" stat name

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41833 )


Change subject: base-stats: Fixed System "work_item" stat name
..

base-stats: Fixed System "work_item" stat name

The name of this stat was prefixed with 'system.'. Something which is
unecessary and undesirable for the stats output.

Change-Id: I873a77927e1ae6bb52f66e9c935e91ef43649dcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41833
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/system.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/system.cc b/src/sim/system.cc
index 93902af..4a9c6cd 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -483,7 +483,7 @@
 std::stringstream namestr;
 ccprintf(namestr, "work_item_type%d", j);
 workItemStats[j]->init(20)
- .name(name() + "." + namestr.str())
+ .name(namestr.str())
  .desc("Run time stat for" + namestr.str())
  .prereq(*workItemStats[j]);
 }



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41833
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I873a77927e1ae6bb52f66e9c935e91ef43649dcd
Gerrit-Change-Number: 41833
Gerrit-PatchSet: 6
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim,base-stats: Fix leading "." bug when obtaining requestors

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41513 )


Change subject: sim,base-stats: Fix leading "." bug when obtaining  
requestors

..

sim,base-stats: Fix leading "." bug when obtaining requestors

When requestor id is requested, it is stripped of the System name via
the `stripSystemName` function in `system.cc`. However, there is a bug
in this code that leaves a leading ".". E.g.:

`system.cpu.mmu.dtb.walker` is stripped to `.cpu.mmu.dtb.walker`.

This patch fixes this issue.

Change-Id: I825cbc60c7f7eaa84c8a0150c30e9f2902cff6cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41513
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/sim/system.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/system.cc b/src/sim/system.cc
index 5600542..93902af 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -532,7 +532,7 @@
 System::stripSystemName(const std::string& requestor_name) const
 {
 if (startswith(requestor_name, name())) {
-return requestor_name.substr(name().size());
+return requestor_name.substr(name().size() + 1);
 } else {
 return requestor_name;
 }



5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41513
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I825cbc60c7f7eaa84c8a0150c30e9f2902cff6cb
Gerrit-Change-Number: 41513
Gerrit-PatchSet: 8
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Re: Build failed in Jenkins: Weekly #9

[Bobby Bruce via gem5-dev]

The script running on Jenkins is as follows:

```
docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd)
gcr.io/gem5-test/gcn-gpu:latest \
bash -c "scons build/GCN3_X86/gem5.opt -j50 || (rm -rf build && scons
build/GCN3_X86/gem5.opt -j50)"

wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square.o

mkdir -p tests/testing-results

docker run -u $UID:$GUID --volume $(pwd):$(pwd) -w $(pwd)
gcr.io/gem5-test/gcn-gpu:latest \
build/GCN3_X86/gem5.opt configs/example/apu_se.py -n2 -c square.o
```

When I run this on my machine the bug is reproduced.

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 26, 2021 at 12:01 PM Kyle Roarty  wrote:

> Hi Bobby,
>
> I've been trying to replicate it myself, but I've had no luck doing so.
>
> I built using the same commit (e100156a51deda7f50873faba069c2c3a6cde2e7)
> and command that were shown in the build log. I also used the pre-built
> square binary from dist.gem5, and used the same run command as shown in the
> build log.
>
> There's only been like 1 change to the GCN/gpu-compute stuff since the
> last passing test (#6, although #7 didn't actually run square, it failed
> due to build timeout), and it doesn't touch anything related to that
> assert. My guess is the scons changes over the past few weeks somehow
> caused the failure, but I'm not sure why I'm not able to replicate the
> issue.
>
> Are you building with the same commands as in the build log? If not, can
> you post them so that I can try to reproduce?
>
> Kyle
> --
> *From:* Bobby Bruce 
> *Sent:* Friday, February 26, 2021 1:28 PM
> *To:* gem5 Developer List ; Matt Sinclair <
> msincl...@wisc.edu>; Kyle Roarty 
> *Subject:* Re: [gem5-dev] Build failed in Jenkins: Weekly #9
>
> Matt, Kyle
>
> The weekly tests are failing with a "fatal: fatal condition driver
> occurred: Should not overwrite driver." error." when running the GCN3
> square tests. I've managed to recreate this issue on my end, so it appears
> to be genuine.
>
> Could you look into this?
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Feb 26, 2021 at 1:02 AM jenkins-no-reply--- via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
> See 
>
> Changes:
>
> [gabe.black] cpu,mem: Add or remove parenthesis to make the compiler happy.
>
> [gabe.black] misc: Fix mismatched struct/class "tags" and reenable that
> warning.
>
> [baz21] arch-arm,sim: make compile on FreeBSD
>
> [Giacomo Travaglini] base: Exclude the end of ChannelAddrRange
>
> [Giacomo Travaglini] base: Remove duplicate isPow2 helper
>
> [gabe.black] arch,cpu: Move getExecutingAsid to the ISA class.
>
> [tiago.muck] mem-ruby: extended transaction profiling
>
> [tiago.muck] mem-ruby: alternative interface for func. reads
>
> [gabe.black] arm,kern: Stop using the getArgument function for kernel
> events.
>
> [odanrc] base: Fix scientific number conversion in base/str
>
> [odanrc] base: Clean up base/hostinfo
>
> [odanrc] base: Remove hostname from hostinfo
>
> [gabe.black] arch: Eliminate the getArgument function.
>
> [Giacomo Travaglini] misc: Use PARAMS
>
> [Giacomo Travaglini] misc: Remove unused params() definitions
>
> [Bobby R. Bruce] base-stats,python: Expose DistInfo via Pybind11
>
> [Bobby R. Bruce] base-stats,python: Expose VectorInfo via Pybind11
>
> [Bobby R. Bruce] base-stats,python: Expose FormulaInfo via PyBind11
>
> [Bobby R. Bruce] base-stats,python: Update PyBind11 ScalarInfo fields to
> readonly
>
> [gabe.black] arch,cpu: Move the inUserMode function to the ISA object.
>
> [petery.hin] arch-riscv: Fixing interrupt handling order and effect of
> mideleg
>
> [petery.hin] arch-riscv: Added PMA support for RiscvTLB
>
> [petery.hin] arch-riscv: Implementation of CLINT
>
> [petery.hin] arch-riscv: PLIC Implementation
>
> [petery.hin] arch-riscv: RISC-V HiFive Platform implementation
>
> [petery.hin] arch-riscv: FS Linux config file for RISC-V
>
> [gabe.black] scons: Check for "make" when using LTO with gcc.
>
> [Giacomo Travaglini] dev-arm: Remove the A9GlobalTimer
>
> [kevlough] arch-x86: Adds rdtscp flag to cpuid for X86KvmCPU
>
> [gabe.black] scons: Enable the clang++ and clang tools.
>
> [gabe.black] scons: Use SCons' built in CXXVERSION instead of detecting
> our own.
>
> [gabe.black] scons: Remove an extraneous Exit().
>
> [gabe.black] scons: Eliminate CXX_V and main_dict_keys in SConstruct.
>
> [gabe.black] scons: Create a small helper function for disecting a build
> target path.
>
> [tiago.muck] mem-ruby: removed Message copy constructors
>
> [tiago.muck] mem-ruby: RubyRequest getter for request ptr
>
> [Bobby R. Bruce] misc: Adding 'make' to the compiler Dockerfiles
>
>
> --
> [...truncated 818.42 KB...]
> warn: coalescer.slave is deprecated. `slave` is 

[gem5-dev] Re: Build failed in Jenkins: Weekly #9

[Kyle Roarty via gem5-dev]

Hi Bobby,

I've been trying to replicate it myself, but I've had no luck doing so.

I built using the same commit (e100156a51deda7f50873faba069c2c3a6cde2e7) and 
command that were shown in the build log. I also used the pre-built square 
binary from dist.gem5, and used the same run command as shown in the build log.

There's only been like 1 change to the GCN/gpu-compute stuff since the last 
passing test (#6, although #7 didn't actually run square, it failed due to 
build timeout), and it doesn't touch anything related to that assert. My guess 
is the scons changes over the past few weeks somehow caused the failure, but 
I'm not sure why I'm not able to replicate the issue.

Are you building with the same commands as in the build log? If not, can you 
post them so that I can try to reproduce?

Kyle

From: Bobby Bruce 
Sent: Friday, February 26, 2021 1:28 PM
To: gem5 Developer List ; Matt Sinclair 
; Kyle Roarty 
Subject: Re: [gem5-dev] Build failed in Jenkins: Weekly #9

Matt, Kyle

The weekly tests are failing with a "fatal: fatal condition driver occurred: 
Should not overwrite driver." error." when running the GCN3 square tests. I've 
managed to recreate this issue on my end, so it appears to be genuine.

Could you look into this?

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 26, 2021 at 1:02 AM jenkins-no-reply--- via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
See 

Changes:

[gabe.black] cpu,mem: Add or remove parenthesis to make the compiler happy.

[gabe.black] misc: Fix mismatched struct/class "tags" and reenable that warning.

[baz21] arch-arm,sim: make compile on FreeBSD

[Giacomo Travaglini] base: Exclude the end of ChannelAddrRange

[Giacomo Travaglini] base: Remove duplicate isPow2 helper

[gabe.black] arch,cpu: Move getExecutingAsid to the ISA class.

[tiago.muck] mem-ruby: extended transaction profiling

[tiago.muck] mem-ruby: alternative interface for func. reads

[gabe.black] arm,kern: Stop using the getArgument function for kernel events.

[odanrc] base: Fix scientific number conversion in base/str

[odanrc] base: Clean up base/hostinfo

[odanrc] base: Remove hostname from hostinfo

[gabe.black] arch: Eliminate the getArgument function.

[Giacomo Travaglini] misc: Use PARAMS

[Giacomo Travaglini] misc: Remove unused params() definitions

[Bobby R. Bruce] base-stats,python: Expose DistInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose VectorInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose FormulaInfo via PyBind11

[Bobby R. Bruce] base-stats,python: Update PyBind11 ScalarInfo fields to 
readonly

[gabe.black] arch,cpu: Move the inUserMode function to the ISA object.

[petery.hin] arch-riscv: Fixing interrupt handling order and effect of mideleg

[petery.hin] arch-riscv: Added PMA support for RiscvTLB

[petery.hin] arch-riscv: Implementation of CLINT

[petery.hin] arch-riscv: PLIC Implementation

[petery.hin] arch-riscv: RISC-V HiFive Platform implementation

[petery.hin] arch-riscv: FS Linux config file for RISC-V

[gabe.black] scons: Check for "make" when using LTO with gcc.

[Giacomo Travaglini] dev-arm: Remove the A9GlobalTimer

[kevlough] arch-x86: Adds rdtscp flag to cpuid for X86KvmCPU

[gabe.black] scons: Enable the clang++ and clang tools.

[gabe.black] scons: Use SCons' built in CXXVERSION instead of detecting our own.

[gabe.black] scons: Remove an extraneous Exit().

[gabe.black] scons: Eliminate CXX_V and main_dict_keys in SConstruct.

[gabe.black] scons: Create a small helper function for disecting a build target 
path.

[tiago.muck] mem-ruby: removed Message copy constructors

[tiago.muck] mem-ruby: RubyRequest getter for request ptr

[Bobby R. Bruce] misc: Adding 'make' to the compiler Dockerfiles


--
[...truncated 818.42 KB...]
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is 

[gem5-dev] Re: Build failed in Jenkins: Weekly #9

[Bobby Bruce via gem5-dev]

Matt, Kyle

The weekly tests are failing with a "fatal: fatal condition driver
occurred: Should not overwrite driver." error." when running the GCN3
square tests. I've managed to recreate this issue on my end, so it appears
to be genuine.

Could you look into this?

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 26, 2021 at 1:02 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See 
>
> Changes:
>
> [gabe.black] cpu,mem: Add or remove parenthesis to make the compiler happy.
>
> [gabe.black] misc: Fix mismatched struct/class "tags" and reenable that
> warning.
>
> [baz21] arch-arm,sim: make compile on FreeBSD
>
> [Giacomo Travaglini] base: Exclude the end of ChannelAddrRange
>
> [Giacomo Travaglini] base: Remove duplicate isPow2 helper
>
> [gabe.black] arch,cpu: Move getExecutingAsid to the ISA class.
>
> [tiago.muck] mem-ruby: extended transaction profiling
>
> [tiago.muck] mem-ruby: alternative interface for func. reads
>
> [gabe.black] arm,kern: Stop using the getArgument function for kernel
> events.
>
> [odanrc] base: Fix scientific number conversion in base/str
>
> [odanrc] base: Clean up base/hostinfo
>
> [odanrc] base: Remove hostname from hostinfo
>
> [gabe.black] arch: Eliminate the getArgument function.
>
> [Giacomo Travaglini] misc: Use PARAMS
>
> [Giacomo Travaglini] misc: Remove unused params() definitions
>
> [Bobby R. Bruce] base-stats,python: Expose DistInfo via Pybind11
>
> [Bobby R. Bruce] base-stats,python: Expose VectorInfo via Pybind11
>
> [Bobby R. Bruce] base-stats,python: Expose FormulaInfo via PyBind11
>
> [Bobby R. Bruce] base-stats,python: Update PyBind11 ScalarInfo fields to
> readonly
>
> [gabe.black] arch,cpu: Move the inUserMode function to the ISA object.
>
> [petery.hin] arch-riscv: Fixing interrupt handling order and effect of
> mideleg
>
> [petery.hin] arch-riscv: Added PMA support for RiscvTLB
>
> [petery.hin] arch-riscv: Implementation of CLINT
>
> [petery.hin] arch-riscv: PLIC Implementation
>
> [petery.hin] arch-riscv: RISC-V HiFive Platform implementation
>
> [petery.hin] arch-riscv: FS Linux config file for RISC-V
>
> [gabe.black] scons: Check for "make" when using LTO with gcc.
>
> [Giacomo Travaglini] dev-arm: Remove the A9GlobalTimer
>
> [kevlough] arch-x86: Adds rdtscp flag to cpuid for X86KvmCPU
>
> [gabe.black] scons: Enable the clang++ and clang tools.
>
> [gabe.black] scons: Use SCons' built in CXXVERSION instead of detecting
> our own.
>
> [gabe.black] scons: Remove an extraneous Exit().
>
> [gabe.black] scons: Eliminate CXX_V and main_dict_keys in SConstruct.
>
> [gabe.black] scons: Create a small helper function for disecting a build
> target path.
>
> [tiago.muck] mem-ruby: removed Message copy constructors
>
> [tiago.muck] mem-ruby: RubyRequest getter for request ptr
>
> [Bobby R. Bruce] misc: Adding 'make' to the compiler Dockerfiles
>
>
> --
> [...truncated 818.42 KB...]
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
> warn: coalescer.slave is 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,misc: Add missing overrides for clang compilation

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41913 )


Change subject: arch-riscv,misc: Add missing overrides for clang compilation
..

arch-riscv,misc: Add missing overrides for clang compilation

The Clang compiler returns "missing override" errors without these.

Change-Id: I62af6c338b000123c924f0b3205551579bd5aeb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41913
Reviewed-by: Gabe Black 
Reviewed-by: Hoa Nguyen 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/riscv/isa.hh
M src/dev/riscv/clint.hh
M src/dev/riscv/rtc.hh
3 files changed, 7 insertions(+), 5 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 1c5dac3..7f03a17 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -97,8 +97,8 @@

 bool inUserMode() const override { return true; }

-void serialize(CheckpointOut ) const;
-void unserialize(CheckpointIn );
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;

 ISA(const Params );
 };
diff --git a/src/dev/riscv/clint.hh b/src/dev/riscv/clint.hh
index 7b1745c..1f213ce 100644
--- a/src/dev/riscv/clint.hh
+++ b/src/dev/riscv/clint.hh
@@ -139,7 +139,8 @@
  * SimObject functions
  */
 void init() override;
-Port & getPort(const std::string _name, PortID idx=InvalidPortID);
+Port & getPort(const std::string _name,
+   PortID idx=InvalidPortID) override;
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

diff --git a/src/dev/riscv/rtc.hh b/src/dev/riscv/rtc.hh
index bfd9071..42a2d29 100644
--- a/src/dev/riscv/rtc.hh
+++ b/src/dev/riscv/rtc.hh
@@ -70,9 +70,10 @@

 RiscvRTC(const Params );

-Port & getPort(const std::string _name, PortID idx=InvalidPortID);
+Port & getPort(const std::string _name,
+   PortID idx=InvalidPortID) override;

-void startup();
+void startup() override;

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41913
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62af6c338b000123c924f0b3205551579bd5aeb4
Gerrit-Change-Number: 41913
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Peter Yuen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add ACPI support for MADT

[Maximilian Stein (Gerrit) via gem5-dev]

Maximilian Stein has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41953 )



Change subject: arch-x86: Add ACPI support for MADT
..

arch-x86: Add ACPI support for MADT

This extends ACPI to support the MADT. This table contains information
about the interrupt system (Local APIC, IO-APIC) and partly replaces the
Intel MP tables.
The change is particularly needed to support other OSes than Linux that
do not support Intel MP.

This patch contains the necessary python and c++ classes to create MADT
records, setup the MADT itself, and extends the RSDP, RSDT, and XSDT.

Change-Id: I132226f46f4d54e2e0b964e2986004e3e5f5f347
Signed-off-by: Maximilian Stein 
---
M configs/common/FSConfig.py
M src/arch/x86/SConscript
M src/arch/x86/bios/ACPI.py
M src/arch/x86/bios/acpi.cc
M src/arch/x86/bios/acpi.hh
M src/arch/x86/fs_workload.cc
6 files changed, 619 insertions(+), 34 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6665225..98df117 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -501,6 +501,7 @@
 # Set up the Intel MP table
 base_entries = []
 ext_entries = []
+madt_records = []
 for i in range(numCPUs):
 bp = X86IntelMPProcessor(
 local_apic_id = i,
@@ -508,6 +509,11 @@
 enable = True,
 bootstrap = (i == 0))
 base_entries.append(bp)
+lapic = X86ACPIMadtLAPIC(
+acpi_processor_id=i,
+apic_id=i,
+flags=1)
+madt_records.append(lapic)
 io_apic = X86IntelMPIOAPIC(
 id = numCPUs,
 version = 0x11,
@@ -515,6 +521,8 @@
 address = 0xfec0)
 self.pc.south_bridge.io_apic.apic_id = io_apic.id
 base_entries.append(io_apic)
+madt_records.append(X86ACPIMadtIOAPIC(id=io_apic.id,
+address=io_apic.address, int_base=0))
 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 # but linux kernel cannot config PCI device if it was not connected to
 # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
@@ -534,6 +542,13 @@
 dest_io_apic_id = io_apic.id,
 dest_io_apic_intin = 16)
 base_entries.append(pci_dev4_inta)
+pci_dev4_inta_madt = X86ACPIMadtIntSourceOverride(
+bus_source = pci_dev4_inta.source_bus_id,
+irq_source = pci_dev4_inta.source_bus_irq,
+sys_int = pci_dev4_inta.dest_io_apic_intin,
+flags = 0
+)
+madt_records.append(pci_dev4_inta_madt)
 def assignISAInt(irq, apicPin):
 assign_8259_to_apic = X86IntelMPIOIntAssignment(
 interrupt_type = 'ExtInt',
@@ -553,6 +568,14 @@
 dest_io_apic_id = io_apic.id,
 dest_io_apic_intin = apicPin)
 base_entries.append(assign_to_apic)
+# acpi
+assign_to_apic_acpi = X86ACPIMadtIntSourceOverride(
+bus_source = 1,
+irq_source = irq,
+sys_int = apicPin,
+flags = 0
+)
+madt_records.append(assign_to_apic_acpi)
 assignISAInt(0, 2)
 assignISAInt(1, 1)
 for i in range(3, 15):
@@ -560,6 +583,13 @@
 workload.intel_mp_table.base_entries = base_entries
 workload.intel_mp_table.ext_entries = ext_entries

+madt = X86ACPIMadt(local_apic_address=0,
+records=madt_records, oem_id='madt')
+workload.acpi_description_table_pointer.rsdt.entries.append(madt)
+workload.acpi_description_table_pointer.xsdt.entries.append(madt)
+workload.acpi_description_table_pointer.oem_id = 'gem5'
+workload.acpi_description_table_pointer.rsdt.oem_id='gem5'
+workload.acpi_description_table_pointer.xsdt.oem_id='gem5'
 return self

 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index f790ec1..1fcf1dc 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -81,6 +81,7 @@
   "Page table walker state machine debugging")
 DebugFlag('Decoder', "Decoder debug output")
 DebugFlag('X86', "Generic X86 ISA debugging")
+DebugFlag('ACPI', "ACPI debugging")

 python_files = (
 '__init__.py',
diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py
index 77de42f..5dfcb4d 100644
--- a/src/arch/x86/bios/ACPI.py
+++ b/src/arch/x86/bios/ACPI.py
@@ -48,8 +48,8 @@
 oem_table_id = Param.String('', 'oem table ID')
 oem_revision = Param.UInt32(0, 'oem revision number for the table')

-creator_id = Param.String('',
-'string identifying the generator of the table')
+creator_id = Param.UInt32(0,
+'ID identifying the generator of the table')
 creator_revision = Param.UInt32(0,
 'revision number for the creator of the table')

@@ -67,6 +67,66 @@

 entries = 

[gem5-dev] Build failed in Jenkins: Weekly #9

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[gabe.black] cpu,mem: Add or remove parenthesis to make the compiler happy.

[gabe.black] misc: Fix mismatched struct/class "tags" and reenable that warning.

[baz21] arch-arm,sim: make compile on FreeBSD

[Giacomo Travaglini] base: Exclude the end of ChannelAddrRange

[Giacomo Travaglini] base: Remove duplicate isPow2 helper

[gabe.black] arch,cpu: Move getExecutingAsid to the ISA class.

[tiago.muck] mem-ruby: extended transaction profiling

[tiago.muck] mem-ruby: alternative interface for func. reads

[gabe.black] arm,kern: Stop using the getArgument function for kernel events.

[odanrc] base: Fix scientific number conversion in base/str

[odanrc] base: Clean up base/hostinfo

[odanrc] base: Remove hostname from hostinfo

[gabe.black] arch: Eliminate the getArgument function.

[Giacomo Travaglini] misc: Use PARAMS

[Giacomo Travaglini] misc: Remove unused params() definitions

[Bobby R. Bruce] base-stats,python: Expose DistInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose VectorInfo via Pybind11

[Bobby R. Bruce] base-stats,python: Expose FormulaInfo via PyBind11

[Bobby R. Bruce] base-stats,python: Update PyBind11 ScalarInfo fields to 
readonly

[gabe.black] arch,cpu: Move the inUserMode function to the ISA object.

[petery.hin] arch-riscv: Fixing interrupt handling order and effect of mideleg

[petery.hin] arch-riscv: Added PMA support for RiscvTLB

[petery.hin] arch-riscv: Implementation of CLINT

[petery.hin] arch-riscv: PLIC Implementation

[petery.hin] arch-riscv: RISC-V HiFive Platform implementation

[petery.hin] arch-riscv: FS Linux config file for RISC-V

[gabe.black] scons: Check for "make" when using LTO with gcc.

[Giacomo Travaglini] dev-arm: Remove the A9GlobalTimer

[kevlough] arch-x86: Adds rdtscp flag to cpuid for X86KvmCPU

[gabe.black] scons: Enable the clang++ and clang tools.

[gabe.black] scons: Use SCons' built in CXXVERSION instead of detecting our own.

[gabe.black] scons: Remove an extraneous Exit().

[gabe.black] scons: Eliminate CXX_V and main_dict_keys in SConstruct.

[gabe.black] scons: Create a small helper function for disecting a build target 
path.

[tiago.muck] mem-ruby: removed Message copy constructors

[tiago.muck] mem-ruby: RubyRequest getter for request ptr

[Bobby R. Bruce] misc: Adding 'make' to the compiler Dockerfiles


--
[...truncated 818.42 KB...]
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`
warn: coalescer.slave is deprecated. `slave` is now called `in_ports`