[gem5-dev] Re: Arm native build/test time jumped tremendously on apr 30

[Gabe Black via gem5-dev]

LTO was disabled for opt builds recently, since on low spec-ed or not very
parallel machines it really slowed things down. For big machines with lots
of cores, parallelizing the link (which you get with LTO on gcc for some
reason) actually speeds up the link a lot, and you can re-enable it with
--with-lto.

Gabe

On Wed, May 12, 2021 at 4:59 PM mike upton via gem5-dev 
wrote:

>
>1. scons: Revert "Enable LTO for opt, perf and prof builds."
>2. scons: Add `--with-lto` to enabled LTO; remove `--no-lto`
>3. base: Stop "using namespace Debug" in DPRINTF style macros.
>4. sim: Stop using DPRINTF_UNCONDITIONAL in the event class.
>5. base: Fill out the 'H' thread setting command in remote GDB.
>6. base: Make the BaseRemoteGDB class able to handle multiple TCs.
>7. arch-sparc: Use GuestABI to call pseudo insts.
>
>
> Hi, i was poking around my jenkins server and saw the build/test time on
> native aarch64 build and run went from 4 hrs to 8 hrs on apr 30.
>
> the above are the relevant commits.
>
> maybe the LTO flags? I cant tell if 1 and 2 cancel each other out.
>
> my arm build is on a 4 core raspberry pi 4, so pretty wimpy.
> have the arm folks seen something similar?
>
>
> ___
> gem5-dev mailing list -- gem5-dev@gem5.org
> To unsubscribe send an email to gem5-dev-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Arm native build/test time jumped tremendously on apr 30

[mike upton via gem5-dev]

   1. scons: Revert "Enable LTO for opt, perf and prof builds."
   2. scons: Add `--with-lto` to enabled LTO; remove `--no-lto`
   3. base: Stop "using namespace Debug" in DPRINTF style macros.
   4. sim: Stop using DPRINTF_UNCONDITIONAL in the event class.
   5. base: Fill out the 'H' thread setting command in remote GDB.
   6. base: Make the BaseRemoteGDB class able to handle multiple TCs.
   7. arch-sparc: Use GuestABI to call pseudo insts.


Hi, i was poking around my jenkins server and saw the build/test time on
native aarch64 build and run went from 4 hrs to 8 hrs on apr 30.

the above are the relevant commits.

maybe the LTO flags? I cant tell if 1 and 2 cancel each other out.

my arm build is on a 4 core raspberry pi 4, so pretty wimpy.
have the arm folks seen something similar?
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Get rid of the SET* macros in packet.cc.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45367 )


Change subject: mem: Get rid of the SET* macros in packet.cc.
..

mem: Get rid of the SET* macros in packet.cc.

Replace these with a helper function which merges attributes into a
unsigned long long which the bitset constructor can accept.

Change-Id: I36f809503a47c17b82dc75dee0d5bb8615eda27b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45367
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/mem/packet.cc
M src/mem/packet.hh
2 files changed, 76 insertions(+), 80 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 0783e0f..820a4bf 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -58,34 +58,24 @@
 #include "base/trace.hh"
 #include "mem/packet_access.hh"

-// The one downside to bitsets is that static initializers can get ugly.
-#define SET1(a1) (1 << (a1))
-#define SET2(a1, a2) (SET1(a1) | SET1(a2))
-#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3))
-#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4))
-#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5))
-#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6))
-#define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \
-  SET1(a7))
-
 const MemCmd::CommandInfo
 MemCmd::commandInfo[] =
 {
 /* InvalidCmd */
-{ 0, InvalidCmd, "InvalidCmd" },
+{ {}, InvalidCmd, "InvalidCmd" },
 /* ReadReq - Read issued by a non-caching agent such as a CPU or
  * device, with no restrictions on alignment. */
-{ SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" },
+{ {IsRead, IsRequest, NeedsResponse}, ReadResp, "ReadReq" },
 /* ReadResp */
-{ SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },
+{ {IsRead, IsResponse, HasData}, InvalidCmd, "ReadResp" },
 /* ReadRespWithInvalidate */
-{ SET4(IsRead, IsResponse, HasData, IsInvalidate),
+{ {IsRead, IsResponse, HasData, IsInvalidate},
 InvalidCmd, "ReadRespWithInvalidate" },
 /* WriteReq */
-{ SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData),
+{ {IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData},
 WriteResp, "WriteReq" },
 /* WriteResp */
-{ SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" },
+{ {IsWrite, IsResponse}, InvalidCmd, "WriteResp" },
 /* WriteCompleteResp - The WriteCompleteResp command is needed
  * because in the GPU memory model we use a WriteResp to indicate
  * that a write has reached the cache controller so we can free
@@ -93,148 +83,139 @@
  * completes we send a WriteCompleteResp to the CU so its wait
  * counters can be updated. Wait counters in the CU is how memory
  * dependences are handled in the GPU ISA. */
-{ SET2(IsWrite, IsResponse), InvalidCmd, "WriteCompleteResp" },
+{ {IsWrite, IsResponse}, InvalidCmd, "WriteCompleteResp" },
 /* WritebackDirty */
-{ SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
+{ {IsWrite, IsRequest, IsEviction, HasData, FromCache},
 InvalidCmd, "WritebackDirty" },
 /* WritebackClean - This allows the upstream cache to writeback a
  * line to the downstream cache without it being considered
  * dirty. */
-{ SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
+{ {IsWrite, IsRequest, IsEviction, HasData, FromCache},
 InvalidCmd, "WritebackClean" },
 /* WriteClean - This allows a cache to write a dirty block to a memory
below without evicting its copy. */
-{ SET4(IsWrite, IsRequest, HasData, FromCache),  
InvalidCmd, "WriteClean" },

+{ {IsWrite, IsRequest, HasData, FromCache}, InvalidCmd, "WriteClean" },
 /* CleanEvict */
-{ SET3(IsRequest, IsEviction, FromCache), InvalidCmd, "CleanEvict" },
+{ {IsRequest, IsEviction, FromCache}, InvalidCmd, "CleanEvict" },
 /* SoftPFReq */
-{ SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
+{ {IsRead, IsRequest, IsSWPrefetch, NeedsResponse},
 SoftPFResp, "SoftPFReq" },
 /* SoftPFExReq */
-{ SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest,
-   IsSWPrefetch, NeedsResponse), SoftPFResp, "SoftPFExReq" },
+{ {IsRead, NeedsWritable, IsInvalidate, IsRequest,
+   IsSWPrefetch, NeedsResponse}, SoftPFResp, "SoftPFExReq" },
 /* HardPFReq */
-{ SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache),
+{ {IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache},
 HardPFResp, "HardPFReq" },
 /* SoftPFResp */
-{ SET4(IsRead, IsResponse, IsSWPrefetch, 

[gem5-dev] Change in gem5/gem5[develop]: base: Stop using macros to handle nan in stats/text.cc.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45366 )


Change subject: base: Stop using macros to handle nan in stats/text.cc.
..

base: Stop using macros to handle nan in stats/text.cc.

c++ provides a standard way to retrieve the value of nan. Use that
instead of a function to compute it, or macros defined for c.

Change-Id: I483e8642d28cc3187682ce6bb7457b5e796cf61c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45366
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/stats/text.cc
1 file changed, 26 insertions(+), 41 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 718b65c..17d1e3b 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -48,6 +48,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 

@@ -56,28 +57,12 @@
 #include "base/stats/info.hh"
 #include "base/str.hh"

-#ifndef NAN
-float __nan();
-/** Define Not a number. */
-#define NAN (__nan())
-/** Need to define __nan() */
-#define __M5_NAN
-#endif
-
-#ifdef __M5_NAN
-float
-__nan()
+namespace
 {
-union
-{
-uint32_t ui;
-float f;
-} nan;

-nan.ui = 0x7fc0;
-return nan.f;
-}
-#endif
+constexpr auto Nan = std::numeric_limits::quiet_NaN();
+
+} // anonymous namespace

 namespace Stats {

@@ -342,8 +327,8 @@
 print.descriptions = descriptions;
 print.units = units;
 print.flags = flags;
-print.pdf = _total ? 0.0 : NAN;
-print.cdf = _total ? 0.0 : NAN;
+print.pdf = _total ? 0.0 : Nan;
+print.cdf = _total ? 0.0 : Nan;

 bool havesub = !subnames.empty();

@@ -389,8 +374,8 @@
 }

 if (flags.isSet(::Stats::total)) {
-print.pdf = NAN;
-print.cdf = NAN;
+print.pdf = Nan;
+print.cdf = Nan;
 print.name = base + "total";
 print.desc = desc;
 print.unitStr = unitStr;
@@ -472,8 +457,8 @@
 print.descriptions = descriptions;
 print.desc = desc;
 print.unitStr = unitStr;
-print.pdf = NAN;
-print.cdf = NAN;
+print.pdf = Nan;
+print.cdf = Nan;

 if (flags.isSet(oneline)) {
 print.name = base + "bucket_size";
@@ -494,16 +479,16 @@
 print(stream);

 print.name = base + "mean";
-print.value = data.samples ? data.sum / data.samples : NAN;
+print.value = data.samples ? data.sum / data.samples : Nan;
 print(stream);

 if (data.type == Hist) {
 print.name = base + "gmean";
-print.value = data.samples ? exp(data.logs / data.samples) : NAN;
+print.value = data.samples ? exp(data.logs / data.samples) : Nan;
 print(stream);
 }

-Result stdev = NAN;
+Result stdev = Nan;
 if (data.samples)
 stdev = sqrt((data.samples * data.squares - data.sum * data.sum) /
  (data.samples * (data.samples - 1.0)));
@@ -517,11 +502,11 @@
 size_t size = data.cvec.size();

 Result total = 0.0;
-if (data.type == Dist && data.underflow != NAN)
+if (data.type == Dist && data.underflow != Nan)
 total += data.underflow;
 for (off_type i = 0; i < size; ++i)
 total += data.cvec[i];
-if (data.type == Dist && data.overflow != NAN)
+if (data.type == Dist && data.overflow != Nan)
 total += data.overflow;

 if (total) {
@@ -529,7 +514,7 @@
 print.cdf = 0.0;
 }

-if (data.type == Dist && data.underflow != NAN) {
+if (data.type == Dist && data.underflow != Nan) {
 print.name = base + "underflows";
 print.update(data.underflow, total);
 print(stream);
@@ -565,22 +550,22 @@
 stream << std::endl;
 }

-if (data.type == Dist && data.overflow != NAN) {
+if (data.type == Dist && data.overflow != Nan) {
 print.name = base + "overflows";
 print.update(data.overflow, total);
 print(stream);
 }

-print.pdf = NAN;
-print.cdf = NAN;
+print.pdf = Nan;
+print.cdf = Nan;

-if (data.type == Dist && data.min_val != NAN) {
+if (data.type == Dist && data.min_val != Nan) {
 print.name = base + "min_value";
 print.value = data.min_val;
 print(stream);
 }

-if (data.type == Dist && data.max_val != NAN) {
+if (data.type == Dist && data.max_val != Nan) {
 print.name = base + "max_value";
 print.value = data.max_val;
 print(stream);
@@ -606,8 +591,8 @@
 print.descriptions = descriptions;
 print.units = units;
 print.precision = info.precision;
-print.pdf = NAN;
-print.cdf = NAN;
+print.pdf = Nan;
+print.cdf = Nan;

 print(*stream);
 }
@@ -810,8 +795,8 @@
 print.units = units;
 print.desc = desc;
 print.unitStr = unitStr;
-print.pdf 

[gem5-dev] Change in gem5/gem5[develop]: base: Stop both conditionally and unconditionally including cmath.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45365 )


Change subject: base: Stop both conditionally and unconditionally including  
cmath.

..

base: Stop both conditionally and unconditionally including cmath.

base/stats/text.cc was both conditionally (in two places) and  
unconditionally

including cmath. Once should be enough.

Change-Id: I941dfb8631eb71d1a8b423011022f78d628baa33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45365
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/stats/text.cc
1 file changed, 1 insertion(+), 11 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 26f1622..718b65c 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -42,19 +42,9 @@
 #define _GLIBCPP_USE_C99 1
 #endif

-#if defined(__sun)
-#include 
-
-#endif
-
-#include 
-
-#ifdef __SUNPRO_CC
-#include 
-
-#endif
 #include "base/stats/text.hh"

+#include 
 #include 
 #include 
 #include 

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45365
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I941dfb8631eb71d1a8b423011022f78d628baa33
Gerrit-Change-Number: 45365
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Cache Compressor Architecture

[Patrick Sheridan (psheridan) via gem5-dev]

Hello,

I am trying to better understand the cache compression architecture, though 
struggling a little with the DictionaryCompressor's pattern matching 
implementation.
In particular, am looking to get the actual compressed lines' data.

Unfortunately, it looks like, like Compressor::Base::CompressionData does not 
contain the actual data, and only its size.
In the specific case of Compressor::DictionaryCompressor::CompData, it does 
have a member, std::vector> entries; which contains 
the patterns, perhaps from which I could get the data.
However, it appears that, e.g. 
Compressor::DictionaryCompressor::DeltaPattern simply stores the original 
data as const DictionaryEntry bytes; (as noted in the comments) rather than the 
deltas.

>From this, it looks like it may be difficult to obtain the compressed cache 
>lines, but I wanted to check that I am looking at this correctly and in the 
>right place.

Regards,
Patrick
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename "memory" variables as "mem"

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45438 )



Change subject: mem: Rename "memory" variables as "mem"
..

mem: Rename "memory" variables as "mem"

Pave the way to a "memory" namespace by renaming all
the variables that have a naming conflict.

Change-Id: I8327256ed88f1791225fe158f023132850303472
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/semihosting.cc
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/dramsim2.cc
M src/mem/dramsim2.hh
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/sim/system.cc
12 files changed, 43 insertions(+), 43 deletions(-)



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7659de9..c6ad98f 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -553,9 +553,9 @@
 fatal_if(memories.size() < 1, "No memories reported from System");
 warn_if(memories.size() > 1, "Multiple physical memory ranges  
available. "

 "Using first range heap/stack.");
-const AddrRange memory = *memories.begin();
-const Addr mem_start = memory.start() + memReserve;
-Addr mem_end = memory.end();
+const AddrRange mem = *memories.begin();
+const Addr mem_start = mem.start() + memReserve;
+Addr mem_end = mem.end();

 // Make sure that 32-bit guests can access their memory.
 if (!aarch64) {
diff --git a/src/mem/cfi_mem.cc b/src/mem/cfi_mem.cc
index 0bcb180..de1348e 100644
--- a/src/mem/cfi_mem.cc
+++ b/src/mem/cfi_mem.cc
@@ -447,46 +447,46 @@

 CfiMemory::MemoryPort::MemoryPort(const std::string& _name,
  CfiMemory& _memory)
-: ResponsePort(_name, &_memory), memory(_memory)
+: ResponsePort(_name, &_memory), mem(_memory)
 { }

 AddrRangeList
 CfiMemory::MemoryPort::getAddrRanges() const
 {
 AddrRangeList ranges;
-ranges.push_back(memory.getAddrRange());
+ranges.push_back(mem.getAddrRange());
 return ranges;
 }

 Tick
 CfiMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-return memory.recvAtomic(pkt);
+return mem.recvAtomic(pkt);
 }

 Tick
 CfiMemory::MemoryPort::recvAtomicBackdoor(
 PacketPtr pkt, MemBackdoorPtr &_backdoor)
 {
-return memory.recvAtomicBackdoor(pkt, _backdoor);
+return mem.recvAtomicBackdoor(pkt, _backdoor);
 }

 void
 CfiMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-memory.recvFunctional(pkt);
+mem.recvFunctional(pkt);
 }

 bool
 CfiMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
-return memory.recvTimingReq(pkt);
+return mem.recvTimingReq(pkt);
 }

 void
 CfiMemory::MemoryPort::recvRespRetry()
 {
-memory.recvRespRetry();
+mem.recvRespRetry();
 }

 void
diff --git a/src/mem/cfi_mem.hh b/src/mem/cfi_mem.hh
index f2c65d3..e49a154 100644
--- a/src/mem/cfi_mem.hh
+++ b/src/mem/cfi_mem.hh
@@ -232,7 +232,7 @@
 class MemoryPort : public ResponsePort
 {
   private:
-CfiMemory& memory;
+CfiMemory& mem;

   public:
 MemoryPort(const std::string& _name, CfiMemory& _memory);
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index 6900b22..3e5ca46 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -353,38 +353,38 @@

 DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
  DRAMSim2& _memory)
-: ResponsePort(_name, &_memory), memory(_memory)
+: ResponsePort(_name, &_memory), mem(_memory)
 { }

 AddrRangeList
 DRAMSim2::MemoryPort::getAddrRanges() const
 {
 AddrRangeList ranges;
-ranges.push_back(memory.getAddrRange());
+ranges.push_back(mem.getAddrRange());
 return ranges;
 }

 Tick
 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-return memory.recvAtomic(pkt);
+return mem.recvAtomic(pkt);
 }

 void
 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-memory.recvFunctional(pkt);
+mem.recvFunctional(pkt);
 }

 bool
 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
 // pass it to the memory controller
-return memory.recvTimingReq(pkt);
+return mem.recvTimingReq(pkt);
 }

 void
 DRAMSim2::MemoryPort::recvRespRetry()
 {
-memory.recvRespRetry();
+mem.recvRespRetry();
 }
diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh
index a417c07..f3792ae 100644
--- a/src/mem/dramsim2.hh
+++ b/src/mem/dramsim2.hh
@@ -64,7 +64,7 @@

   private:

-DRAMSim2& memory;
+DRAMSim2& mem;

   public:

diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index bc96567..92b5797 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -351,38 +351,38 @@

 DRAMsim3::MemoryPort::MemoryPort(const std::string& _name,
  DRAMsim3& _memory)
-: ResponsePort(_name, &_memory), memory(_memory)
+: ResponsePort(_name, &_memory), mem(_memory)
 { }

 

[gem5-dev] Change in gem5/gem5[develop]: sim,misc: Rename Int namespace as as_uint64

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45436 )



Change subject: sim,misc: Rename Int namespace as as_uint64
..

sim,misc: Rename Int namespace as as_uint64

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sim_clock::Int became sim_clock::as_uint64.

"as_uint64" was chosen because "int" is a reserved
keyword, "uint64" would be a dangerous choice, and
this namespace acts as a selector of how to read the
internal variables.

Another possibility to resolve this would be to
remove the namespaces "Float" and "Int" and use
unions instead.

Change-Id: I65f47608d2212424bed1731c7f53d242d5a7d89a
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/semihosting.cc
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/rtc_pl031.cc
M src/dev/mc146818.cc
M src/dev/mc146818.hh
M src/dev/net/etherdump.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/serial/uart8250.cc
M src/gpu-compute/gpu_compute_driver.cc
M src/kern/freebsd/events.cc
M src/kern/linux/events.cc
M src/mem/cache/tags/base.cc
M src/mem/drampower.cc
M src/mem/dramsim2.cc
M src/mem/dramsim3.cc
M src/mem/xbar.cc
M src/sim/core.cc
M src/sim/core.hh
M src/sim/power/thermal_model.cc
M src/sim/pseudo_inst.cc
M src/sim/syscall_emul.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
30 files changed, 65 insertions(+), 62 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index bf96a3c..fb88fdb 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -40,7 +40,7 @@
 void
 ScxEvsCortexA76::setClkPeriod(Tick clk_period)
 {
-clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
+clockRateControl->set_mul_div(sim_clock::as_uint64::s, clk_period);
 }

 template 
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index 1c6e203..40aa6d3 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -39,7 +39,7 @@
 void
 ScxEvsCortexR52::setClkPeriod(Tick clk_period)
 {
-clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
+clockRateControl->set_mul_div(sim_clock::as_uint64::s, clk_period);
 }

 template 
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc  
b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc

index 98943e2..473d64c 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -254,7 +254,7 @@
 PL330::start_of_simulation()
 {
 // Set the clock rate using the divider inside the EVS.
-clockRateControl->set_mul_div(sim_clock::Int::s, clockPeriod);
+clockRateControl->set_mul_div(sim_clock::as_uint64::s, clockPeriod);
 }

 } // namespace fastmodel
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index f2a7280..7659de9 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -500,7 +500,7 @@
 ArmSemihosting::RetErrno
 ArmSemihosting::callClock(ThreadContext *tc)
 {
-return retOK(curTick() / (sim_clock::Int::s / 100));
+return retOK(curTick() / (sim_clock::as_uint64::s / 100));
 }

 ArmSemihosting::RetErrno
diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc
index 9df4dda..aa4456e 100644
--- a/src/dev/arm/energy_ctrl.cc
+++ b/src/dev/arm/energy_ctrl.cc
@@ -99,7 +99,7 @@
 break;
   case DVFS_HANDLER_TRANS_LATENCY:
 // Return transition latency in nanoseconds
-result = dvfsHandler->transLatency() / sim_clock::Int::ns;
+result = dvfsHandler->transLatency() / sim_clock::as_uint64::ns;
 DPRINTF(EnergyCtrl, "reading dvfs handler trans latency %d ns\n",
 result);
 break;
diff --git a/src/dev/arm/energy_ctrl.hh b/src/dev/arm/energy_ctrl.hh
index a68a55e..08a0e5a 100644
--- a/src/dev/arm/energy_ctrl.hh
+++ b/src/dev/arm/energy_ctrl.hh
@@ -164,7 +164,7 @@
 uint32_t perfLevelToRead;

 static uint32_t ticksTokHz(Tick period) {
-return (uint32_t)(sim_clock::Int::ms / period);
+return (uint32_t)(sim_clock::as_uint64::ms / period);
 }

 static uint32_t toMicroVolt(double voltage) {
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index 3597936..beea2b2 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -69,7 +69,8 @@

 switch (daddr) {
   case DataReg:
-data = timeVal + ((curTick() - lastWrittenTick) /  
sim_clock::Int::s);

+data = timeVal +
+((curTick() - lastWrittenTick) / sim_clock::as_uint64::s);
 break;
   case 

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Rename FastModel namespace as fastmodel

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45434 )



Change subject: fastmodel: Rename FastModel namespace as fastmodel
..

fastmodel: Rename FastModel namespace as fastmodel

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::FastModel became ::fastmodel.

Change-Id: I48e34952287e44e3fb932e13f4d006d616c1d982
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/fastmodel/CortexA76/thread_context.hh
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/fastmodel/PL330_DMAC/FastModelPL330.py
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.hh
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
M src/arch/arm/fastmodel/amba_ports.hh
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
M src/arch/arm/fastmodel/common/signal_receiver.hh
27 files changed, 68 insertions(+), 87 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index 0b0fa8d..f6f678b 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -38,7 +38,7 @@

 class FastModelCortexA76(IrisBaseCPU):
 type = 'FastModelCortexA76'
-cxx_class = 'FastModel::CortexA76'
+cxx_class = 'fastmodel::CortexA76'
 cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh'

 cntfrq = Param.UInt64(0x180, "Value for the CNTFRQ timer register")
@@ -136,7 +136,7 @@

 class FastModelCortexA76Cluster(SimObject):
 type = 'FastModelCortexA76Cluster'
-cxx_class = 'FastModel::CortexA76Cluster'
+cxx_class = 'fastmodel::CortexA76Cluster'
 cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh'

 cores = VectorParam.FastModelCortexA76(
@@ -366,7 +366,7 @@

 class FastModelScxEvsCortexA76x1(SystemC_ScModule):
 type = 'FastModelScxEvsCortexA76x1'
-cxx_class  
= 'FastModel::ScxEvsCortexA76'
+cxx_class  
= 'fastmodel::ScxEvsCortexA76'

 cxx_template_params = [ 'class Types' ]
 cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'

@@ -377,7 +377,7 @@

 class FastModelScxEvsCortexA76x2(SystemC_ScModule):
 type = 'FastModelScxEvsCortexA76x2'
-cxx_class  
= 'FastModel::ScxEvsCortexA76'
+cxx_class  
= 'fastmodel::ScxEvsCortexA76'

 cxx_template_params = [ 'class Types' ]
 cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'

@@ -389,7 +389,7 @@

 class FastModelScxEvsCortexA76x3(SystemC_ScModule):
 type = 'FastModelScxEvsCortexA76x3'
-cxx_class  
= 'FastModel::ScxEvsCortexA76'
+cxx_class  
= 'fastmodel::ScxEvsCortexA76'

 cxx_template_params = [ 'class Types' ]
 cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'

@@ -402,7 +402,7 @@

 class FastModelScxEvsCortexA76x4(SystemC_ScModule):
 type = 'FastModelScxEvsCortexA76x4'
-cxx_class  
= 'FastModel::ScxEvsCortexA76'
+cxx_class  
= 'fastmodel::ScxEvsCortexA76'

 cxx_template_params = [ 'class Types' ]
 cxx_header = 'arch/arm/fastmodel/CortexA76/evs.hh'

diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index 72ce17e..1957bc3 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -33,8 +33,7 @@
 #include "sim/core.hh"
 #include "systemc/tlm_bridge/gem5_to_tlm.hh"

-namespace FastModel
-{
+namespace fastmodel {

 void
 CortexA76::initState()
@@ -196,4 +195,4 @@
 }
 }

-} // namespace FastModel
+} // namespace fastmodel
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 8588f22..6ca7677 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -39,8 +39,7 @@

 class BaseCPU;

-namespace FastModel
-{
+namespace fastmodel {

 // The fast model exports a class called scx_evs_CortexA76x1 which  
represents
 // the subsystem described in LISA+. This class 

[gem5-dev] Change in gem5/gem5[develop]: base,dev,mem-ruby: Rename m5 namespace as gem5

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45437 )



Change subject: base,dev,mem-ruby: Rename m5 namespace as gem5
..

base,dev,mem-ruby: Rename m5 namespace as gem5

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::m5 became ::gem5.

Change-Id: I250b4354113fcd6005dc4144ae378552cb8f6717
Signed-off-by: Daniel R. Carvalho 
---
M src/base/coroutine.hh
M src/base/coroutine.test.cc
M src/base/stl_helpers.hh
M src/dev/arm/gic_v3_its.hh
M src/dev/arm/smmu_v3_proc.hh
M src/mem/ruby/common/SubBlock.cc
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/profiler/AddressProfiler.cc
M src/mem/ruby/profiler/Profiler.cc
10 files changed, 17 insertions(+), 13 deletions(-)



diff --git a/src/base/coroutine.hh b/src/base/coroutine.hh
index 594c1e8..9342bbf 100644
--- a/src/base/coroutine.hh
+++ b/src/base/coroutine.hh
@@ -41,10 +41,11 @@
 #include 
 #include 

+#include "base/compiler.hh"
 #include "base/fiber.hh"

-namespace m5
-{
+GEM5_DEPRECATED_NAMESPACE(m5, gem5);
+namespace gem5 {

 /**
  * This template defines a Coroutine wrapper type with a Boost-like
@@ -292,6 +293,6 @@
 CallerType caller;
 };

-} //namespace m5
+} //namespace gem5

 #endif // __BASE_COROUTINE_HH__
diff --git a/src/base/coroutine.test.cc b/src/base/coroutine.test.cc
index 771097a..47ffcf2 100644
--- a/src/base/coroutine.test.cc
+++ b/src/base/coroutine.test.cc
@@ -39,7 +39,7 @@

 #include "base/coroutine.hh"

-using namespace m5;
+using namespace gem5;

 /**
  * This test is checking if the Coroutine, once it's created
diff --git a/src/base/stl_helpers.hh b/src/base/stl_helpers.hh
index ae369b5..0e1660a 100644
--- a/src/base/stl_helpers.hh
+++ b/src/base/stl_helpers.hh
@@ -32,7 +32,10 @@
 #include 
 #include 

-namespace m5 {
+#include "base/compiler.hh"
+
+GEM5_DEPRECATED_NAMESPACE(m5, gem5);
+namespace gem5 {
 namespace stl_helpers {

 template 
@@ -84,6 +87,6 @@
 }

 } // namespace stl_helpers
-} // namespace m5
+} // namespace gem5

 #endif // __BASE_STL_HELPERS_HH__
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index e1688cd..7221e26 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -354,7 +354,7 @@
 using DTE = Gicv3Its::DTE;
 using ITTE = Gicv3Its::ITTE;
 using CTE = Gicv3Its::CTE;
-using Coroutine = m5::Coroutine;
+using Coroutine = gem5::Coroutine;
 using Yield = Coroutine::CallerType;

 ItsProcess(Gicv3Its &_its);
diff --git a/src/dev/arm/smmu_v3_proc.hh b/src/dev/arm/smmu_v3_proc.hh
index b55ec19..eaf5659 100644
--- a/src/dev/arm/smmu_v3_proc.hh
+++ b/src/dev/arm/smmu_v3_proc.hh
@@ -94,7 +94,7 @@
 class SMMUProcess : public Packet::SenderState
 {
   private:
-typedef m5::Coroutine Coroutine;
+typedef gem5::Coroutine Coroutine;

 Coroutine *coroutine;
 std::string myName;
diff --git a/src/mem/ruby/common/SubBlock.cc  
b/src/mem/ruby/common/SubBlock.cc

index 98fec99..e889a55 100644
--- a/src/mem/ruby/common/SubBlock.cc
+++ b/src/mem/ruby/common/SubBlock.cc
@@ -30,7 +30,7 @@

 #include "base/stl_helpers.hh"

-using m5::stl_helpers::operator<<;
+using gem5::stl_helpers::operator<<;

 SubBlock::SubBlock(Addr addr, int size)
 {
diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index a9d291a..6642fbc 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -49,7 +49,7 @@
 #include "debug/RubyQueue.hh"
 #include "mem/ruby/system/RubySystem.hh"

-using m5::stl_helpers::operator<<;
+using gem5::stl_helpers::operator<<;

 MessageBuffer::MessageBuffer(const Params )
 : SimObject(p), m_stall_map_size(0),
diff --git a/src/mem/ruby/network/simple/Switch.cc  
b/src/mem/ruby/network/simple/Switch.cc

index 2b9ad95..b10f27c 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -48,7 +48,7 @@
 #include "mem/ruby/network/MessageBuffer.hh"
 #include "mem/ruby/network/simple/SimpleNetwork.hh"

-using m5::stl_helpers::operator<<;
+using gem5::stl_helpers::operator<<;

 Switch::Switch(const Params )
   : BasicRouter(p),
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc  
b/src/mem/ruby/profiler/AddressProfiler.cc

index c54dae3..5e68c6d 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -37,7 +37,7 @@

 typedef AddressProfiler::AddressMap AddressMap;

-using m5::stl_helpers::operator<<;
+using gem5::stl_helpers::operator<<;

 // Helper functions
 AccessTraceForAddress&
diff --git a/src/mem/ruby/profiler/Profiler.cc  
b/src/mem/ruby/profiler/Profiler.cc

index 65f0153..01512e6 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -78,7 +78,7 @@

 #include "mem/ruby/system/Sequencer.hh"

-using 

[gem5-dev] Change in gem5/gem5[develop]: sim,misc: Rename Float namespace as as_double

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45435 )



Change subject: sim,misc: Rename Float namespace as as_double
..

sim,misc: Rename Float namespace as as_double

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sim_clock::Float became sim_clock::as_double.

"as_double" was chosen because "float" and "double"
are reserved keywords, and this namespace acts as
a selector of how to read the internal variables.
Another possibility to resolve this would be to
remove the namespaces "Float" and "Int" and use
unions instead.

Change-Id: I7b3d9c6e9ab547493d5596c7eda080a25509a730
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/semihosting.cc
M src/base/time.cc
M src/cpu/kvm/timer.hh
M src/cpu/kvm/x86_cpu.cc
M src/dev/arm/rv_ctrl.cc
M src/dev/intel_8254_timer.cc
M src/mem/comm_monitor.cc
M src/mem/qos/mem_ctrl.cc
M src/sim/core.cc
M src/sim/core.hh
M src/systemc/core/sc_time.cc
M src/systemc/utils/vcd.cc
12 files changed, 36 insertions(+), 35 deletions(-)



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 00c8396..f2a7280 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -506,7 +506,7 @@
 ArmSemihosting::RetErrno
 ArmSemihosting::callTime(ThreadContext *tc)
 {
-return retOK(timeBase + round(curTick() / sim_clock::Float::s));
+return retOK(timeBase + round(curTick() / sim_clock::as_double::s));
 }

 ArmSemihosting::RetErrno
diff --git a/src/base/time.cc b/src/base/time.cc
index 35e1260..66d9f1e 100644
--- a/src/base/time.cc
+++ b/src/base/time.cc
@@ -55,7 +55,7 @@
 {
 uint64_t secs = ticks / sim_clock::Frequency;
 ticks -= secs * sim_clock::Frequency;
-uint64_t nsecs = static_cast(ticks * sim_clock::Float::GHz);
+uint64_t nsecs = static_cast(ticks *  
sim_clock::as_double::GHz);

 set(secs, nsecs);
 }

@@ -63,7 +63,7 @@
 Time::getTick() const
 {
 return sec() * sim_clock::Frequency +
-static_cast(nsec() * sim_clock::Float::ns);
+static_cast(nsec() * sim_clock::as_double::ns);
 }

 std::string
diff --git a/src/cpu/kvm/timer.hh b/src/cpu/kvm/timer.hh
index cbfc9e4..c43bb46 100644
--- a/src/cpu/kvm/timer.hh
+++ b/src/cpu/kvm/timer.hh
@@ -129,7 +129,7 @@
  * @return Nanoseconds executed in VM converted to simulation ticks
  */
 Tick ticksFromHostNs(uint64_t ns) {
-return ns * hostFactor * sim_clock::Float::ns;
+return ns * hostFactor * sim_clock::as_double::ns;
 }

   protected:
@@ -147,7 +147,7 @@
  * @return Simulation ticks converted into nanoseconds on the host
  */
 uint64_t hostNs(Tick ticks) {
-return ticks / (sim_clock::Float::ns * hostFactor);
+return ticks / (sim_clock::as_double::ns * hostFactor);
 }

 /**
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 8d8b777..a69f904 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -1247,7 +1247,7 @@
 // Limit the run to 1 millisecond. That is hopefully enough to
 // reach an interrupt window. Otherwise, we'll just try again
 // later.
-return BaseKvmCPU::kvmRun(1 * sim_clock::Float::ms);
+return BaseKvmCPU::kvmRun(1 * sim_clock::as_double::ms);
 } else {
 DPRINTF(Drain, "kvmRunDrain: Delivering pending IO\n");

diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 63000bf..6daf9e7 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -66,12 +66,12 @@
 break;
   case Clock24:
 Tick clk;
-clk = sim_clock::Float::MHz * curTick() * 24;
+clk = sim_clock::as_double::MHz * curTick() * 24;
 pkt->setLE((uint32_t)(clk));
 break;
   case Clock100:
 Tick clk100;
-clk100 = sim_clock::Float::MHz * curTick() * 100;
+clk100 = sim_clock::as_double::MHz * curTick() * 100;
 pkt->setLE((uint32_t)(clk100));
 break;
   case Flash:
@@ -239,9 +239,9 @@
   RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
p.site, p.position, p.dcc, p.device)
 {
-if (sim_clock::Float::s  / p.freq > UINT32_MAX) {
+if (sim_clock::as_double::s  / p.freq > UINT32_MAX) {
 fatal("Oscillator frequency out of range: %f\n",
-sim_clock::Float::s  / p.freq / 1E6);
+sim_clock::as_double::s  / p.freq / 1E6);
 }

 _clockPeriod = p.freq;
@@ -286,7 +286,7 @@
 uint32_t
 RealViewOsc::read() const
 {
-const uint32_t freq(sim_clock::Float::s / _clockPeriod);
+const uint32_t freq(sim_clock::as_double::s / _clockPeriod);
 DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6);
 return freq;
 }
@@ -295,7 +295,7 @@
 RealViewOsc::write(uint32_t freq)
 {
 DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6);
-

[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Rename GuestABI namespace as guest_abi

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45433 )



Change subject: arch,sim: Rename GuestABI namespace as guest_abi
..

arch,sim: Rename GuestABI namespace as guest_abi

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::GuestABI became ::guest_abi.

Change-Id: I68700ef63479f1bb3eeab044b29dc09d86424608
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/arch/arm/aapcs64.test.cc
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/linux/se_workload.hh
M src/arch/arm/reg_abi.hh
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/mips/se_workload.hh
M src/arch/power/se_workload.hh
M src/arch/riscv/se_workload.hh
M src/arch/sparc/pseudo_inst_abi.hh
M src/arch/sparc/se_workload.hh
M src/arch/x86/linux/linux.hh
M src/arch/x86/linux/se_workload.hh
M src/arch/x86/pseudo_inst_abi.hh
M src/kern/linux/printk.hh
M src/sim/guest_abi.hh
M src/sim/guest_abi.test.cc
M src/sim/guest_abi/definition.hh
M src/sim/guest_abi/dispatch.hh
M src/sim/guest_abi/layout.hh
M src/sim/guest_abi/varargs.hh
M src/sim/proxy_ptr.hh
M src/sim/proxy_ptr.test.cc
M src/sim/syscall_abi.hh
M src/sim/syscall_desc.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
29 files changed, 128 insertions(+), 148 deletions(-)



diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index e1bd505..94cbbfd 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -63,8 +63,7 @@
 };
 };

-namespace GuestABI
-{
+namespace guest_abi {

 /*
  * Composite Types
@@ -355,7 +354,7 @@
 }
 };

-} // namespace GuestABI
+} // namespace guest_abi


 /*
@@ -426,8 +425,7 @@
 };
 };

-namespace GuestABI
-{
+namespace guest_abi {

 /*
  * Integer arguments and return values.
@@ -634,6 +632,6 @@
 }
 };

-} // namespace GuestABI
+} // namespace guest_abi

 #endif // __ARCH_ARM_AAPCS32_HH__
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 3f07105..ba9df96 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -63,8 +63,7 @@
 };
 };

-namespace GuestABI
-{
+namespace guest_abi {

 /*
  * Short Vectors
@@ -420,6 +419,6 @@
 }
 };

-} // namespace GuestABI
+} // namespace guest_abi

 #endif // __ARCH_ARM_AAPCS64_HH__
diff --git a/src/arch/arm/aapcs64.test.cc b/src/arch/arm/aapcs64.test.cc
index 69bbb83..8155d66 100644
--- a/src/arch/arm/aapcs64.test.cc
+++ b/src/arch/arm/aapcs64.test.cc
@@ -40,41 +40,41 @@
 using EightLongFloat = float[2];
 using SixteenLongFloat = double[2];

-EXPECT_FALSE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_FALSE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_FALSE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_FALSE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_FALSE(GuestABI::IsAapcs64ShortVector::value);
+EXPECT_FALSE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_FALSE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_FALSE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_FALSE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_FALSE(guest_abi::IsAapcs64ShortVector::value);

-EXPECT_TRUE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_TRUE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_TRUE(GuestABI::IsAapcs64ShortVector::value);
-EXPECT_TRUE(GuestABI::IsAapcs64ShortVector::value);
+EXPECT_TRUE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_TRUE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_TRUE(guest_abi::IsAapcs64ShortVector::value);
+EXPECT_TRUE(guest_abi::IsAapcs64ShortVector::value);
 }

 TEST(Aapcs64, IsAapcs64Hfa)
 {
 // Accept floating point arrays with up to 4 members.
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);

-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_TRUE(GuestABI::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_TRUE(guest_abi::IsAapcs64Hfa::value);

 // Too many members.
-EXPECT_FALSE(GuestABI::IsAapcs64Hfa::value);
-EXPECT_FALSE(GuestABI::IsAapcs64Hfa::value);
+EXPECT_FALSE(guest_abi::IsAapcs64Hfa::value);
+EXPECT_FALSE(guest_abi::IsAapcs64Hfa::value);

 // Wrong type of members, or not arrays.
-EXPECT_FALSE(GuestABI::IsAapcs64Hfa::value);
-

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename LockedMem namespace as locked_mem

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45432 )



Change subject: arch: Rename LockedMem namespace as locked_mem
..

arch: Rename LockedMem namespace as locked_mem

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

GenericISA::LockedMem became GenericISA::locked_mem.

Change-Id: Ia939d8cb27ba4ba19837b7b4d7cb2819c8d5daed
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/generic/locked_mem.hh
M src/arch/null/locked_mem.hh
M src/arch/power/locked_mem.hh
M src/arch/sparc/locked_mem.hh
M src/arch/x86/locked_mem.hh
5 files changed, 8 insertions(+), 7 deletions(-)



diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
index 66a8f43..031988f 100644
--- a/src/arch/generic/locked_mem.hh
+++ b/src/arch/generic/locked_mem.hh
@@ -47,14 +47,15 @@
  * Generic helper functions for locked memory accesses.
  */

+#include "base/compiler.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"

 namespace GenericISA
 {

-namespace LockedMem
-{
+GEM5_DEPRECATED_NAMESPACE(LockedMem, locked_mem);
+namespace locked_mem {

 template 
 inline void
@@ -88,7 +89,7 @@
 {
 }

-} // namespace LockedMem
+} // namespace locked_mem

 } // namespace Generic ISA

diff --git a/src/arch/null/locked_mem.hh b/src/arch/null/locked_mem.hh
index 876d8b9..8af3fdb 100644
--- a/src/arch/null/locked_mem.hh
+++ b/src/arch/null/locked_mem.hh
@@ -52,7 +52,7 @@
 namespace NullISA
 {

-using namespace GenericISA::LockedMem;
+using namespace GenericISA::locked_mem;

 } // namespace NullISA

diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index 153f602..5838490 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -42,7 +42,7 @@
 namespace PowerISA
 {

-using namespace GenericISA::LockedMem;
+using namespace GenericISA::locked_mem;

 } // namespace PowerISA

diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
index 5521828..eaa6bb9 100644
--- a/src/arch/sparc/locked_mem.hh
+++ b/src/arch/sparc/locked_mem.hh
@@ -40,7 +40,7 @@
 namespace SparcISA
 {

-using namespace GenericISA::LockedMem;
+using namespace GenericISA::locked_mem;

 } // namespace SparcISA

diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index 2ff4781..adea8b7 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -40,7 +40,7 @@
 namespace X86ISA
 {

-using namespace GenericISA::LockedMem;
+using namespace GenericISA::locked_mem;

 } // namespace X86ISA


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45432
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia939d8cb27ba4ba19837b7b4d7cb2819c8d5daed
Gerrit-Change-Number: 45432
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-x86,dev: Rename DeliveryMode namespace as delivery_mode

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45431 )



Change subject: arch-x86,dev: Rename DeliveryMode namespace as delivery_mode
..

arch-x86,dev: Rename DeliveryMode namespace as delivery_mode

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

X86ISA::DeliveryMode became X86ISA::delivery_mode.

Change-Id: Id1d83ba0ac7a4092ba796c608945a9cc17911430
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/interrupts.cc
M src/arch/x86/intmessage.hh
M src/dev/x86/i82094aa.cc
M src/dev/x86/pc.cc
4 files changed, 19 insertions(+), 18 deletions(-)



diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index be60586..9dee310 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -229,10 +229,10 @@
  * using the IRR/ISR registers, checking against the TPR, etc.
  * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
  */
-if (deliveryMode == DeliveryMode::Fixed ||
-deliveryMode == DeliveryMode::LowestPriority) {
+if (deliveryMode == delivery_mode::Fixed ||
+deliveryMode == delivery_mode::LowestPriority) {
 DPRINTF(LocalApic, "Interrupt is an %s.\n",
-DeliveryMode::names[deliveryMode]);
+delivery_mode::names[deliveryMode]);
 // Queue up the interrupt in the IRR.
 if (vector > IRRV)
 IRRV = vector;
@@ -244,22 +244,22 @@
 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
 }
 }
-} else if (!DeliveryMode::isReserved(deliveryMode)) {
+} else if (!delivery_mode::isReserved(deliveryMode)) {
 DPRINTF(LocalApic, "Interrupt is an %s.\n",
-DeliveryMode::names[deliveryMode]);
-if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
+delivery_mode::names[deliveryMode]);
+if (deliveryMode == delivery_mode::SMI && !pendingSmi) {
 pendingUnmaskableInt = pendingSmi = true;
 smiVector = vector;
-} else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
+} else if (deliveryMode == delivery_mode::NMI && !pendingNmi) {
 pendingUnmaskableInt = pendingNmi = true;
 nmiVector = vector;
-} else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt)  
{
+} else if (deliveryMode == delivery_mode::ExtInt  
&& !pendingExtInt) {

 pendingExtInt = true;
 extIntVector = vector;
-} else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
+} else if (deliveryMode == delivery_mode::INIT && !pendingInit) {
 pendingUnmaskableInt = pendingInit = true;
 initVector = vector;
-} else if (deliveryMode == DeliveryMode::SIPI &&
+} else if (deliveryMode == delivery_mode::SIPI &&
 !pendingStartup && !startedUp) {
 pendingUnmaskableInt = pendingStartup = true;
 startupVector = vector;
@@ -482,7 +482,7 @@
 int numContexts = sys->threads.size();
 switch (low.destShorthand) {
   case 0:
-if (message.deliveryMode == DeliveryMode::LowestPriority) {
+if (message.deliveryMode == delivery_mode::LowestPriority)  
{

 panic("Lowest priority delivery mode "
 "IPIs aren't implemented.\n");
 }
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 4910e27..bf96fa6 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -31,6 +31,7 @@

 #include "arch/x86/x86_traits.hh"
 #include "base/bitunion.hh"
+#include "base/compiler.hh"
 #include "base/types.hh"
 #include "dev/x86/intdev.hh"
 #include "mem/packet.hh"
@@ -48,8 +49,8 @@
 Bitfield<21> trigger;
 EndBitUnion(TriggerIntMessage)

-namespace DeliveryMode
-{
+GEM5_DEPRECATED_NAMESPACE(DeliveryMode, delivery_mode);
+namespace delivery_mode {
 enum IntDeliveryMode
 {
 Fixed = 0,
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index dabfe8c..5ae4315 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -187,7 +187,7 @@
 } else {
 TriggerIntMessage message = 0;
 message.destination = entry.dest;
-if (entry.deliveryMode == DeliveryMode::ExtInt) {
+if (entry.deliveryMode == delivery_mode::ExtInt) {
 assert(extIntPic);
 message.vector = extIntPic->getVector();
 } else {
@@ -200,7 +200,7 @@
 std::list apics;
 int numContexts = sys->threads.size();
 if (message.destMode == 0) {
-if (message.deliveryMode == DeliveryMode::LowestPriority) {
+if (message.deliveryMode == delivery_mode::LowestPriority) {
   

[gem5-dev] Change in gem5/gem5[develop]: sim: Rename InitParamKey namespace as init_param_key

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45430 )



Change subject: sim: Rename InitParamKey namespace as init_param_key
..

sim: Rename InitParamKey namespace as init_param_key

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

pseudo_inst::InitParamKey became pseudo_inst::init_param_key.

Change-Id: I4a9275a1745e1ed78db0ec99dc91f03ad6d5dfac
Signed-off-by: Daniel R. Carvalho 
---
M src/sim/pseudo_inst.cc
1 file changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index bd617f8..467edf1 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -79,8 +79,8 @@
  * @note Each key may be at most 16 characters (because we use
  * two 64-bit registers to pass in the key to the initparam function).
  */
-namespace InitParamKey
-{
+GEM5_DEPRECATED_NAMESPACE(InitParamKey, init_param_key);
+namespace init_param_key {

 /**
  *  The default key (empty string)
@@ -95,7 +95,7 @@
  */
 const std::string DIST_SIZE = "dist-size";

-} // namespace InitParamKey
+} // namespace init_param_key

 void
 arm(ThreadContext *tc)
@@ -284,11 +284,11 @@

 // Check key parameter to figure out what to return.
 const std::string key_str(key);
-if (key == InitParamKey::DEFAULT)
+if (key == init_param_key::DEFAULT)
 return tc->getCpuPtr()->system->init_param;
-else if (key == InitParamKey::DIST_RANK)
+else if (key == init_param_key::DIST_RANK)
 return DistIface::rankParam();
-else if (key == InitParamKey::DIST_SIZE)
+else if (key == init_param_key::DIST_SIZE)
 return DistIface::sizeParam();
 else
 panic("Unknown key for initparam pseudo instruction:\"%s\"",  
key_str);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45430
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a9275a1745e1ed78db0ec99dc91f03ad6d5dfac
Gerrit-Change-Number: 45430
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch,sim: Rename PseudoInst namespace as pseudo_inst

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45429 )



Change subject: arch,sim: Rename PseudoInst namespace as pseudo_inst
..

arch,sim: Rename PseudoInst namespace as pseudo_inst

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::PseudoInst became ::pseudo_inst.

Change-Id: Ie5a8f82a532e5158992ca260b4a24e7c6f311be9
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/isa/insts/m5ops.isa
M src/arch/arm/semihosting.cc
M src/arch/arm/tlb.cc
M src/arch/riscv/isa/formats/m5ops.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/tlb.cc
M src/sim/pseudo_inst.cc
M src/sim/pseudo_inst.hh
9 files changed, 49 insertions(+), 48 deletions(-)



diff --git a/src/arch/arm/isa/insts/m5ops.isa  
b/src/arch/arm/isa/insts/m5ops.isa

index fafb44b..4e508f0 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -40,7 +40,7 @@
 uint64_t ret;
 int func = bits(machInst, 23, 16);
 auto *tc = xc->tcBase();
-if (!PseudoInst::pseudoInst<%s>(tc, func, ret))
+if (!pseudo_inst::pseudoInst<%s>(tc, func, ret))
 fault = std::make_shared(machInst, true);
 '''
 gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op64", "PredOp",
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 6a52e07..88a604e 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -722,10 +722,10 @@
 ArmSemihosting::callGem5PseudoOp32(ThreadContext *tc, uint32_t  
encoded_func)

 {
 uint8_t func;
-PseudoInst::decodeAddrOffset(encoded_func, func);
+pseudo_inst::decodeAddrOffset(encoded_func, func);

 uint64_t ret;
-if (PseudoInst::pseudoInst(tc, func, ret))
+if (pseudo_inst::pseudoInst(tc, func, ret))
 return retOK(ret);
 else
 return retError(EINVAL);
@@ -735,10 +735,10 @@
 ArmSemihosting::callGem5PseudoOp64(ThreadContext *tc, uint64_t  
encoded_func)

 {
 uint8_t func;
-PseudoInst::decodeAddrOffset(encoded_func, func);
+pseudo_inst::decodeAddrOffset(encoded_func, func);

 uint64_t ret;
-if (PseudoInst::pseudoInst(tc, func, ret))
+if (pseudo_inst::pseudoInst(tc, func, ret))
 return retOK(ret);
 else
 return retError(EINVAL);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index c654f20..023f84b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -141,15 +141,15 @@

 if (m5opRange.contains(paddr)) {
 uint8_t func;
-PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
+pseudo_inst::decodeAddrOffset(paddr - m5opRange.start(), func);
 req->setLocalAccessor(
 [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
 {
 uint64_t ret;
 if (inAArch64(tc))
-PseudoInst::pseudoInst(tc, func, ret);
+pseudo_inst::pseudoInst(tc, func, ret);
 else
-PseudoInst::pseudoInst(tc, func, ret);
+pseudo_inst::pseudoInst(tc, func, ret);

 if (mode == Read)
 pkt->setLE(ret);
diff --git a/src/arch/riscv/isa/formats/m5ops.isa  
b/src/arch/riscv/isa/formats/m5ops.isa

index 986438b..edc965a 100644
--- a/src/arch/riscv/isa/formats/m5ops.isa
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -38,7 +38,7 @@
 def format M5Op() {{
 iop = InstObjParams(name, Name, 'PseudoOp', '''
 uint64_t result;
-PseudoInst::pseudoInst(xc->tcBase(), M5FUNC, result);
+pseudo_inst::pseudoInst(xc->tcBase(), M5FUNC,  
result);

 a0 = result''',
 ['IsNonSpeculative', 'IsSerializeAfter'])
 header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 1917207..9c85cdf 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1002,7 +1002,7 @@
 }
 // M5 special opcodes use the reserved IMPDEP2A opcode space
 0x37: BasicOperate::pseudo_inst({{
-if (!PseudoInst::pseudoInst(
+if (!pseudo_inst::pseudoInst(
 xc->tcBase(), M5FUNC)) {
 fault = std::make_shared();
 }
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index fe8a2bc..48f46d4 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -145,7 +145,7 @@
 // instructions.
 //0x04: loadall_or_reset_or_hang();
 0x4: BasicOperate::gem5Op({{
-bool recognized = PseudoInst::pseudoInst(
+bool recognized =  
pseudo_inst::pseudoInst(

[gem5-dev] Change in gem5/gem5[develop]: base,dev: Rename major and minor variables

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45427 )



Change subject: base,dev: Rename major and minor variables
..

base,dev: Rename major and minor variables

Add a _version prefix. This is needed because there is
no cpu namespace yet.

Pave the way for a minor namespace.

Change-Id: Ic76415672f5421b838efc0913345c4b929e601f2
Signed-off-by: Daniel R. Carvalho 
---
M src/base/vnc/vncserver.cc
M src/dev/storage/disk_image.cc
2 files changed, 12 insertions(+), 10 deletions(-)



diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index 3417fa5..7ecd3f9 100644
--- a/src/base/vnc/vncserver.cc
+++ b/src/base/vnc/vncserver.cc
@@ -387,20 +387,22 @@
 return;
 }

-uint32_t major, minor;
+uint32_t major_version, minor_version;

 // Figure out the major/minor numbers
-if (sscanf(version_string, "RFB %03d.%03d\n", , ) != 2) {
+if (sscanf(version_string, "RFB %03d.%03d\n", _version,
+_version) != 2) {
 warn(" Malformed protocol version %s\n", version_string);
 sendError("Malformed protocol version\n");
 detach();
 return;
 }

-DPRINTF(VNC, "Client request protocol version %d.%d\n", major, minor);
+DPRINTF(VNC, "Client request protocol version %d.%d\n", major_version,
+minor_version);

 // If it's not 3.X we don't support it
-if (major != 3 || minor < 2) {
+if (major_version != 3 || minor_version < 2) {
 warn("Unsupported VNC client version... disconnecting\n");
 uint8_t err = AuthInvalid;
 write();
@@ -408,7 +410,7 @@
 return;
 }
 // Auth is different based on version number
-if (minor < 7) {
+if (minor_version < 7) {
 uint32_t sec_type = htobe((uint32_t)AuthNone);
 if (!write(_type))
 return;
diff --git a/src/dev/storage/disk_image.cc b/src/dev/storage/disk_image.cc
index 50e8cf2..2bb702b 100644
--- a/src/dev/storage/disk_image.cc
+++ b/src/dev/storage/disk_image.cc
@@ -248,13 +248,13 @@
 if (memcmp(, "COWDISK!", sizeof(magic)) != 0)
 panic("Could not open %s: Invalid magic", file);

-uint32_t major, minor;
-SafeReadSwap(stream, major);
-SafeReadSwap(stream, minor);
+uint32_t major_version, minor_version;
+SafeReadSwap(stream, major_version);
+SafeReadSwap(stream, minor_version);

-if (major != VersionMajor && minor != VersionMinor)
+if (major_version != VersionMajor && minor_version != VersionMinor)
 panic("Could not open %s: invalid version %d.%d != %d.%d",
-  file, major, minor, VersionMajor, VersionMinor);
+  file, major_version, minor_version, VersionMajor,  
VersionMinor);


 uint64_t sector_count;
 SafeReadSwap(stream, sector_count);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45427
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic76415672f5421b838efc0913345c4b929e601f2
Gerrit-Change-Number: 45427
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Rename DecodeCache namespace as decode_cache

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45426 )



Change subject: arch,cpu: Rename DecodeCache namespace as decode_cache
..

arch,cpu: Rename DecodeCache namespace as decode_cache

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::DecodeCache became ::decode_cache.

Change-Id: Ia2b89b3fd802aae72a391786f7ea0a045de1fc2a
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/generic/decode_cache.hh
M src/arch/riscv/decoder.hh
M src/arch/x86/decoder.hh
M src/cpu/decode_cache.hh
4 files changed, 11 insertions(+), 10 deletions(-)



diff --git a/src/arch/generic/decode_cache.hh  
b/src/arch/generic/decode_cache.hh

index 84f90ca..b4caa72 100644
--- a/src/arch/generic/decode_cache.hh
+++ b/src/arch/generic/decode_cache.hh
@@ -40,13 +40,13 @@
 class BasicDecodeCache
 {
   private:
-DecodeCache::InstMap instMap;
+decode_cache::InstMap instMap;
 struct AddrMapEntry
 {
 StaticInstPtr inst;
 EMI machInst;
 };
-DecodeCache::AddrMap decodePages;
+decode_cache::AddrMap decodePages;

   public:
 /// Decode a machine instruction.
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index f1a9b2e..2b2cab5 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -45,7 +45,7 @@
 class Decoder : public InstDecoder
 {
   private:
-DecodeCache::InstMap instMap;
+decode_cache::InstMap instMap;
 bool aligned;
 bool mid;
 bool more;
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 6f51c1a..d9a7216 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -232,14 +232,14 @@

 typedef RegVal CacheKey;

-typedef DecodeCache::AddrMap DecodePages;
+typedef decode_cache::AddrMap DecodePages;
 DecodePages *decodePages = nullptr;
 typedef std::unordered_map AddrCacheMap;
 AddrCacheMap addrCacheMap;

-DecodeCache::InstMap *instMap = nullptr;
+decode_cache::InstMap *instMap = nullptr;
 typedef std::unordered_map<
-CacheKey, DecodeCache::InstMap *> InstCacheMap;
+CacheKey, decode_cache::InstMap *> InstCacheMap;
 static InstCacheMap instCacheMap;

 StaticInstPtr decodeInst(ExtMachInst mach_inst);
@@ -282,7 +282,7 @@
 if (imIter != instCacheMap.end()) {
 instMap = imIter->second;
 } else {
-instMap = new DecodeCache::InstMap;
+instMap = new decode_cache::InstMap;
 instCacheMap[m5Reg] = instMap;
 }
 }
diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh
index 20b6783..12791b9 100644
--- a/src/cpu/decode_cache.hh
+++ b/src/cpu/decode_cache.hh
@@ -32,10 +32,11 @@
 #include 

 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "cpu/static_inst_fwd.hh"

-namespace DecodeCache
-{
+GEM5_DEPRECATED_NAMESPACE(DecodeCache, decode_cache);
+namespace decode_cache {

 /// Hash for decoded instructions.
 template 
@@ -131,6 +132,6 @@
 }
 };

-} // namespace DecodeCache
+} // namespace decode_cache

 #endif // __CPU_DECODE_CACHE_HH__

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45426
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia2b89b3fd802aae72a391786f7ea0a045de1fc2a
Gerrit-Change-Number: 45426
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Rename Minor namespace as minor

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45428 )



Change subject: cpu-minor: Rename Minor namespace as minor
..

cpu-minor: Rename Minor namespace as minor

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Minor became ::minor.

Change-Id: I408aa3d269ed7454ed0f488bd363d521602e58af
Signed-off-by: Daniel R. Carvalho 
---
M src/cpu/minor/activity.cc
M src/cpu/minor/activity.hh
M src/cpu/minor/buffers.hh
M src/cpu/minor/cpu.cc
M src/cpu/minor/cpu.hh
M src/cpu/minor/decode.cc
M src/cpu/minor/decode.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/execute.hh
M src/cpu/minor/fetch1.cc
M src/cpu/minor/fetch1.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/func_unit.cc
M src/cpu/minor/func_unit.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/minor/pipe_data.cc
M src/cpu/minor/pipe_data.hh
M src/cpu/minor/pipeline.cc
M src/cpu/minor/pipeline.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/minor/stats.cc
M src/cpu/minor/stats.hh
M src/cpu/minor/trace.hh
29 files changed, 74 insertions(+), 97 deletions(-)



diff --git a/src/cpu/minor/activity.cc b/src/cpu/minor/activity.cc
index aefe65c..b91bd77 100644
--- a/src/cpu/minor/activity.cc
+++ b/src/cpu/minor/activity.cc
@@ -41,8 +41,7 @@

 #include "cpu/minor/trace.hh"

-namespace Minor
-{
+namespace minor {

 void
 MinorActivityRecorder::minorTrace() const
@@ -62,4 +61,4 @@
 MINORTRACE("activity=%d stages=%s\n", getActivityCount(),  
stages.str());

 }

-}
+} // namespace minor
diff --git a/src/cpu/minor/activity.hh b/src/cpu/minor/activity.hh
index 2872e6f..bc061f4 100644
--- a/src/cpu/minor/activity.hh
+++ b/src/cpu/minor/activity.hh
@@ -47,8 +47,7 @@

 #include "cpu/activity.hh"

-namespace Minor
-{
+namespace minor {

 /** ActivityRecorder with a Ticked interface */
 class MinorActivityRecorder : public ActivityRecorder
@@ -65,6 +64,6 @@
 { }
 };

-}
+} // namespace minor

 #endif /* __CPU_MINOR_ACTIVITY_HH__ */
diff --git a/src/cpu/minor/buffers.hh b/src/cpu/minor/buffers.hh
index 11ae83a..05f375e 100644
--- a/src/cpu/minor/buffers.hh
+++ b/src/cpu/minor/buffers.hh
@@ -56,8 +56,7 @@
 #include "cpu/minor/trace.hh"
 #include "cpu/timebuf.hh"

-namespace Minor
-{
+namespace minor {

 /** Interface class for data with reporting/tracing facilities.  This
  *  interface doesn't actually have to be used as other classes which need
@@ -654,6 +653,6 @@
 }
 };

-}
+} // namespace minor

 #endif /* __CPU_MINOR_BUFFERS_HH__ */
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 02f934c..31de890 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -50,15 +50,15 @@
 stats(this)
 {
 /* This is only written for one thread at the moment */
-Minor::MinorThread *thread;
+minor::MinorThread *thread;

 for (ThreadID i = 0; i < numThreads; i++) {
 if (FullSystem) {
-thread = new Minor::MinorThread(this, i, params.system,
+thread = new minor::MinorThread(this, i, params.system,
 params.mmu, params.isa[i]);
 thread->setStatus(ThreadContext::Halted);
 } else {
-thread = new Minor::MinorThread(this, i, params.system,
+thread = new minor::MinorThread(this, i, params.system,
 params.workload[i], params.mmu,
 params.isa[i]);
 }
@@ -73,9 +73,9 @@
 fatal("The Minor model doesn't support checking (yet)\n");
 }

-Minor::MinorDynInst::init();
+minor::MinorDynInst::init();

-pipeline = new Minor::Pipeline(*this, params);
+pipeline = new minor::Pipeline(*this, params);
 activityRecorder = pipeline->getActivityRecorder();

 fetchEventWrapper = NULL;
@@ -269,7 +269,7 @@

 /* Wake up the thread, wakeup the pipeline tick */
 threads[thread_id]->activate();
-wakeupOnEvent(Minor::Pipeline::CPUStageId);
+wakeupOnEvent(minor::Pipeline::CPUStageId);

 if (!threads[thread_id]->getUseForClone())//the thread is not cloned
 {
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index c26136d..0fbf39e 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -44,6 +44,7 @@
 #ifndef __CPU_MINOR_CPU_HH__
 #define __CPU_MINOR_CPU_HH__

+#include "base/compiler.hh"
 #include "cpu/minor/activity.hh"
 #include "cpu/minor/stats.hh"
 #include "cpu/base.hh"
@@ -51,15 +52,17 @@
 #include "enums/ThreadPolicy.hh"
 #include "params/MinorCPU.hh"

-namespace Minor
-{
+GEM5_DEPRECATED_NAMESPACE(Minor, minor);
+namespace minor {
+
 /** Forward declared to break the cyclic inclusion dependencies between
  *  pipeline and cpu */
 class Pipeline;

 /** Minor will use the SimpleThread state for now */
 typedef SimpleThread 

[gem5-dev] Change in gem5/gem5[develop]: misc: Rename BitfieldBackend namespace as bitfield_backend

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45425 )



Change subject: misc: Rename BitfieldBackend namespace as bitfield_backend
..

misc: Rename BitfieldBackend namespace as bitfield_backend

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::BitfieldBackend became ::bitfield_backend.

Change-Id: Ibf6c5a93baa9b07aab84dc4ee98960a57d925eaf
Signed-off-by: Daniel R. Carvalho 
---
M src/base/bitunion.hh
1 file changed, 16 insertions(+), 17 deletions(-)



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index 3b6ca16..a71e5ca 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -35,6 +35,7 @@
 #include 

 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "sim/serialize_handlers.hh"

 //  The following implements the BitUnion system of defining bitfields
@@ -168,8 +169,8 @@

 //This namespace is for classes which implement the backend of the BitUnion
 //stuff. Don't use any of these directly.
-namespace BitfieldBackend
-{
+GEM5_DEPRECATED_NAMESPACE(BitfieldBackend, bitfield_backend);
+namespace bitfield_backend {
 template
 class Unsigned
 {
@@ -401,14 +402,14 @@
 //overhead.
 #define __BitUnion(type, name) \
 class BitfieldUnderlyingClasses##name : \
-public BitfieldBackend::BitfieldTypes \
+public bitfield_backend::BitfieldTypes \
 { \
   protected: \
 typedef type __StorageType; \
-friend BitfieldBackend::BitUnionBaseType< \
-BitfieldBackend::BitUnionOperators< \
+friend bitfield_backend::BitUnionBaseType< \
+bitfield_backend::BitUnionOperators< \
 BitfieldUnderlyingClasses##name> >; \
-friend BitfieldBackend::BitUnionBaseType< \
+friend bitfield_backend::BitUnionBaseType< \
 BitfieldUnderlyingClasses##name>; \
   public: \
 union { \
@@ -425,7 +426,7 @@
 #define EndBitUnion(name) \
 }; \
 }; \
-typedef BitfieldBackend::BitUnionOperators< \
+typedef bitfield_backend::BitUnionOperators< \
 BitfieldUnderlyingClasses##name> name;

 //This sets up a bitfield which has other bitfields nested inside of it.  
The

@@ -495,8 +496,8 @@


 //These templates make it possible to define other templates related to
-//BitUnions without having to refer to internal typedefs or the  
BitfieldBackend

-//namespace.
+//BitUnions without having to refer to internal typedefs or the
+// bitfield_backend namespace.

 //To build a template specialization which works for all BitUnions, accept  
a

 //template argument T, and then use BitUnionType as an argument in the
@@ -513,10 +514,9 @@
  * @ingroup api_bitunion
  */
 template 
-using BitUnionType = BitfieldBackend::BitUnionOperators;
+using BitUnionType = bitfield_backend::BitUnionOperators;

-namespace BitfieldBackend
-{
+namespace bitfield_backend {
 template
 struct BitUnionBaseType
 {
@@ -534,7 +534,7 @@
  * @ingroup api_bitunion
  */
 template 
-using BitUnionBaseType = typename  
BitfieldBackend::BitUnionBaseType::Type;
+using BitUnionBaseType = typename  
bitfield_backend::BitUnionBaseType::Type;



 //An STL style hash structure for hashing BitUnions based on their base  
type.

@@ -552,8 +552,7 @@
 }


-namespace BitfieldBackend
-{
+namespace bitfield_backend {

 template
 static inline std::ostream &
@@ -585,7 +584,7 @@

 /**
  * A default << operator which casts a bitunion to its underlying type and
- * passes it to BitfieldBackend::bitfieldBackendPrinter.
+ * passes it to bitfield_backend::bitfieldBackendPrinter.
  *
  * @ingroup api_bitunion
  */
@@ -593,7 +592,7 @@
 std::ostream &
 operator << (std::ostream , const BitUnionType )
 {
-return BitfieldBackend::bitfieldBackendPrinter(
+return bitfield_backend::bitfieldBackendPrinter(
 os, (BitUnionBaseType)bu);
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45425
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibf6c5a93baa9b07aab84dc4ee98960a57d925eaf
Gerrit-Change-Number: 45425
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base-stats,misc: Rename Stats namespace as statistics

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45421 )



Change subject: base-stats,misc: Rename Stats namespace as statistics
..

base-stats,misc: Rename Stats namespace as statistics

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Stats became ::statistics.

"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.

Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/group.cc
M src/base/stats/group.hh
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/info.cc
M src/base/stats/info.hh
M src/base/stats/output.hh
M src/base/stats/storage.cc
M src/base/stats/storage.hh
M src/base/stats/storage.test.cc
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/base/stats/types.hh
M src/base/stats/units.hh
M src/base/stats/units.test.cc
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/stats.cc
M src/cpu/minor/stats.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/cpu/pred/loop_predictor.cc
M src/cpu/pred/loop_predictor.hh
M src/cpu/pred/statistical_corrector.cc
M src/cpu/pred/statistical_corrector.hh
M src/cpu/pred/tage_base.cc
M src/cpu/pred/tage_base.hh
M src/cpu/profile.cc
M src/cpu/simple/exec_context.hh
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/cpu/trace/trace_cpu.cc
M src/cpu/trace/trace_cpu.hh
M src/dev/arm/flash_device.cc
M src/dev/arm/flash_device.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/hdlcd.hh
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_caches.hh
M src/dev/arm/ufs_device.cc
M src/dev/arm/ufs_device.hh
M src/dev/net/etherdevice.cc
M src/dev/net/etherdevice.hh
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/dispatcher.cc
M src/gpu-compute/dispatcher.hh
M src/gpu-compute/exec_stage.cc
M src/gpu-compute/exec_stage.hh
M src/gpu-compute/fetch_stage.cc
M src/gpu-compute/fetch_stage.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/global_memory_pipeline.hh
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/local_memory_pipeline.cc
M src/gpu-compute/local_memory_pipeline.hh
M src/gpu-compute/register_file.cc
M src/gpu-compute/register_file.hh
M src/gpu-compute/schedule_stage.cc
M src/gpu-compute/schedule_stage.hh
M src/gpu-compute/scoreboard_check_stage.cc
M src/gpu-compute/scoreboard_check_stage.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
M src/gpu-compute/wavefront.cc
M src/gpu-compute/wavefront.hh
M src/learning_gem5/part2/simple_cache.cc
M src/learning_gem5/part2/simple_cache.hh
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
M 

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Rename Units namespace as units

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45415 )



Change subject: base-stats: Rename Units namespace as units
..

base-stats: Rename Units namespace as units

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

Stats::Units became Stats::units.

Change-Id: I9ce855b291db122d952098a090a2984b42152850
Signed-off-by: Daniel R. Carvalho 
---
M src/base/statistics.cc
M src/base/statistics.hh
M src/base/stats/info.hh
M src/base/stats/units.hh
M src/base/stats/units.test.cc
M src/cpu/base.cc
M src/cpu/minor/stats.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/trace/trace_cpu.cc
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/ufs_device.cc
M src/dev/net/etherdevice.cc
M src/dev/net/sinic.cc
M src/mem/abstract_mem.cc
M src/mem/cache/base.cc
M src/mem/cache/compressors/base.cc
M src/mem/cache/tags/base.cc
M src/mem/comm_monitor.cc
M src/mem/mem_ctrl.cc
M src/mem/mem_interface.cc
M src/sim/root.cc
25 files changed, 178 insertions(+), 176 deletions(-)



diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index fd44e16..e4cb8a5 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -138,7 +138,7 @@
 {
 }

-Formula::Formula(Group *parent, const char *name, const Units::Base *unit,
+Formula::Formula(Group *parent, const char *name, const units::Base *unit,
  const char *desc)
 : DataWrapVec(parent, name, unit, desc)
 {
@@ -152,7 +152,7 @@
 *this = r;
 }

-Formula::Formula(Group *parent, const char *name, const Units::Base *unit,
+Formula::Formula(Group *parent, const char *name, const units::Base *unit,
  const char *desc, const Temp )
 : DataWrapVec(parent, name, unit, desc)
 {
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index e96cc7b..6894901 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -242,7 +242,7 @@
 DataWrap(const DataWrap &) = delete;
 DataWrap =(const DataWrap &) = delete;

-DataWrap(Group *parent, const char *name, const Units::Base *unit,
+DataWrap(Group *parent, const char *name, const units::Base *unit,
  const char *desc)
 {
 auto info = new Info(self());
@@ -308,7 +308,7 @@
  * @return A reference to this stat.
  */
 Derived &
-unit(const Units::Base *_unit)
+unit(const units::Base *_unit)
 {
 this->info()->unit = _unit;
 return this->self();
@@ -373,7 +373,7 @@
 typedef InfoProxyType Info;

 DataWrapVec(Group *parent = nullptr, const char *name = nullptr,
-const Units::Base *unit = UNIT_UNSPECIFIED,
+const units::Base *unit = UNIT_UNSPECIFIED,
 const char *desc = nullptr)
 : DataWrap(parent, name, unit, desc)
 {}
@@ -455,7 +455,7 @@
 typedef InfoProxyType Info;

 DataWrapVec2d(Group *parent, const char *name,
-  const Units::Base *unit, const char *desc)
+  const units::Base *unit, const char *desc)
 : DataWrapVec(parent, name, unit, desc)
 {
 }
@@ -550,7 +550,7 @@

   public:
 ScalarBase(Group *parent = nullptr, const char *name = nullptr,
-   const Units::Base *unit = UNIT_UNSPECIFIED,
+   const units::Base *unit = UNIT_UNSPECIFIED,
const char *desc = nullptr)
 : DataWrap(parent, name, unit, desc)
 {
@@ -708,7 +708,7 @@

   public:
 ValueBase(Group *parent, const char *name,
-  const Units::Base *unit,
+  const units::Base *unit,
   const char *desc)
 : DataWrap(parent, name, unit, desc),
   proxy(NULL)
@@ -1012,7 +1012,7 @@

   public:
 VectorBase(Group *parent, const char *name,
-   const Units::Base *unit,
+   const units::Base *unit,
const char *desc)
 : DataWrapVec(parent, name, unit, desc),
   storage(nullptr), _size(0)
@@ -1155,7 +1155,7 @@

   public:
 Vector2dBase(Group *parent, const char *name,
- const Units::Base *unit,
+ const units::Base *unit,
  const char *desc)
 : DataWrapVec2d(parent, name, unit,  
desc),

   x(0), y(0), _size(0), storage(nullptr)
@@ -1316,7 +1316,7 @@

   public:
 DistBase(Group *parent, const char *name,
- const Units::Base *unit,
+ const units::Base *unit,
  const char *desc)
 : DataWrap(parent, name, unit, desc)
 {
@@ -1414,7 +1414,7 @@

   public:
 VectorDistBase(Group *parent, const char *name,
-   const Units::Base *unit,
+   const units::Base *unit,
const char *desc)
 : DataWrapVec(parent, name, unit,  

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename some linux loader variables as linuxLoader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45422 )



Change subject: arch: Rename some linux loader variables as linuxLoader
..

arch: Rename some linux loader variables as linuxLoader

Pave the way for a loader namespace.

Change-Id: Ie7c811e74424063ff773569e7ad9df9dde166d4f
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/linux/se_workload.cc
M src/arch/mips/linux/se_workload.cc
M src/arch/power/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/sparc/linux/se_workload.cc
M src/arch/x86/linux/se_workload.cc
6 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/linux/se_workload.cc  
b/src/arch/arm/linux/se_workload.cc

index da523fb..8080b2b 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -85,7 +85,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/mips/linux/se_workload.cc  
b/src/arch/mips/linux/se_workload.cc

index 2edb764..2c6b9d5 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -64,7 +64,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/power/linux/se_workload.cc  
b/src/arch/power/linux/se_workload.cc

index 864468f..90add2f 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -64,7 +64,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/riscv/linux/se_workload.cc  
b/src/arch/riscv/linux/se_workload.cc

index a59423e..7ffc5f6 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -68,7 +68,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/sparc/linux/se_workload.cc  
b/src/arch/sparc/linux/se_workload.cc

index 848f64b..1659163 100644
--- a/src/arch/sparc/linux/se_workload.cc
+++ b/src/arch/sparc/linux/se_workload.cc
@@ -66,7 +66,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace

diff --git a/src/arch/x86/linux/se_workload.cc  
b/src/arch/x86/linux/se_workload.cc

index f6f9d9a..66e4763 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -81,7 +81,7 @@
 }
 };

-LinuxLoader loader;
+LinuxLoader linuxLoader;

 } // anonymous namespace


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45422
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie7c811e74424063ff773569e7ad9df9dde166d4f
Gerrit-Change-Number: 45422
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename Linux namespace as linux

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45418 )



Change subject: arch: Rename Linux namespace as linux
..

arch: Rename Linux namespace as linux

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Linux became ::linux.

Change-Id: I3c34790530464b42ded795ce5b78719387a79a00
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/system.cc
M src/arch/generic/linux/threadinfo.hh
M src/arch/mips/linux/hwrpb.hh
M src/arch/mips/linux/thread_info.hh
M src/kern/linux/events.cc
M src/kern/linux/events.hh
M src/kern/linux/helpers.cc
M src/kern/linux/helpers.hh
M src/kern/linux/printk.cc
M src/kern/linux/printk.hh
11 files changed, 27 insertions(+), 29 deletions(-)



diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index e392a86..dc3071d 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -57,7 +57,7 @@
 #include "mem/physical.hh"
 #include "sim/stat_control.hh"

-using namespace Linux;
+using namespace linux;

 namespace ArmISA
 {
@@ -212,18 +212,18 @@

 const std::string dmesg_output = name() + ".dmesg";
 if (params().panic_on_panic) {
-kernelPanic = addKernelFuncEventOrPanic(
+kernelPanic = addKernelFuncEventOrPanic(
 "panic", "Kernel panic in simulated kernel", dmesg_output);
 } else {
-kernelPanic = addKernelFuncEventOrPanic(
+kernelPanic = addKernelFuncEventOrPanic(
 "panic", "Kernel panic in simulated kernel", dmesg_output);
 }

 if (params().panic_on_oops) {
-kernelOops = addKernelFuncEventOrPanic(
+kernelOops = addKernelFuncEventOrPanic(
 "oops_exit", "Kernel oops in guest", dmesg_output);
 } else {
-kernelOops = addKernelFuncEventOrPanic(
+kernelOops = addKernelFuncEventOrPanic(
 "oops_exit", "Kernel oops in guest", dmesg_output);
 }

@@ -267,7 +267,7 @@
 void
 FsLinux::dumpDmesg()
 {
-Linux::dumpDmesg(system->threads[0], std::cout);
+linux::dumpDmesg(system->threads[0], std::cout);
 }

 /**
@@ -282,7 +282,7 @@
 DumpStats::getTaskDetails(ThreadContext *tc, uint32_t ,
 uint32_t , std::string _task_str, int32_t ) {

-Linux::ThreadInfo ti(tc);
+linux::ThreadInfo ti(tc);
 Addr task_descriptor = tc->readIntReg(2);
 pid = ti.curTaskPID(task_descriptor);
 tgid = ti.curTaskTGID(task_descriptor);
@@ -304,7 +304,7 @@
 DumpStats64::getTaskDetails(ThreadContext *tc, uint32_t ,
 uint32_t , std::string _task_str, int32_t ) {

-Linux::ThreadInfo ti(tc);
+linux::ThreadInfo ti(tc);
 Addr task_struct = tc->readIntReg(1);
 pid = ti.curTaskPIDFromTaskStruct(task_struct);
 tgid = ti.curTaskTGIDFromTaskStruct(task_struct);
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 783366d..e8efb9c 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -51,7 +51,7 @@
 #include "dev/arm/gic_v2.hh"
 #include "mem/physical.hh"

-using namespace Linux;
+using namespace linux;
 using namespace ArmISA;

 ArmSystem::ArmSystem(const Params )
diff --git a/src/arch/generic/linux/threadinfo.hh  
b/src/arch/generic/linux/threadinfo.hh

index e5ba7e2..f73c45b 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -32,7 +32,7 @@
 #include "cpu/thread_context.hh"
 #include "sim/system.hh"

-namespace Linux {
+namespace linux {

 class ThreadInfo
 {
@@ -183,6 +183,6 @@
 }
 };

-} // namespace Linux
+} // namespace linux

 #endif // __ARCH_GENERIC_LINUX_THREADINFO_HH__
diff --git a/src/arch/mips/linux/hwrpb.hh b/src/arch/mips/linux/hwrpb.hh
index f7b8bfa..312d086 100644
--- a/src/arch/mips/linux/hwrpb.hh
+++ b/src/arch/mips/linux/hwrpb.hh
@@ -27,7 +27,7 @@

 #include "arch/mips/linux/aligned.hh"

-namespace Linux {
+namespace linux {
 struct pcb_struct
 {
 uint64_ta rpb_ksp;
diff --git a/src/arch/mips/linux/thread_info.hh  
b/src/arch/mips/linux/thread_info.hh

index 3f26ef1..9e37e79 100644
--- a/src/arch/mips/linux/thread_info.hh
+++ b/src/arch/mips/linux/thread_info.hh
@@ -31,7 +31,7 @@

 #include "arch/mips/linux/hwrpb.hh"

-namespace Linux {
+namespace linux {
 struct thread_info
 {
 struct pcb_struct   pcb;
diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc
index aca839e..15a62a7 100644
--- a/src/kern/linux/events.cc
+++ b/src/kern/linux/events.cc
@@ -51,8 +51,7 @@
 #include "sim/core.hh"
 #include "sim/system.hh"

-namespace Linux
-{
+namespace linux {

 void
 DmesgDump::process(ThreadContext *tc)
diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh
index d833ed5..93afdad 100644
--- a/src/kern/linux/events.hh
+++ b/src/kern/linux/events.hh
@@ -53,8 +53,7 @@

 class ThreadContext;

-namespace Linux
-{
+namespace 

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename freebsd loader variables as freebsdLoader

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45423 )



Change subject: arch: Rename freebsd loader variables as freebsdLoader
..

arch: Rename freebsd loader variables as freebsdLoader

Pave the way for a loader namespace.

Change-Id: Ief6f54cc49840fb6c156d56ba3da52dc0a995ac8
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/freebsd/se_workload.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/freebsd/se_workload.cc  
b/src/arch/arm/freebsd/se_workload.cc

index 12f966e..5e52485 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -71,7 +71,7 @@
 }
 };

-FreebsdLoader loader;
+FreebsdLoader freebsdLoader;

 } // anonymous namespace


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45423
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief6f54cc49840fb6c156d56ba3da52dc0a995ac8
Gerrit-Change-Number: 45423
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base,dev,python: Rename Net namespace as network

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45417 )



Change subject: base,dev,python: Rename Net namespace as network
..

base,dev,python: Rename Net namespace as network

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Net became ::network.

Change-Id: I6a77e36c84918174104e507453d53dfe3cb52d35
Signed-off-by: Daniel R. Carvalho 
---
M src/base/inet.cc
M src/base/inet.hh
M src/dev/net/etherswitch.cc
M src/dev/net/etherswitch.hh
M src/dev/net/i8254xGBe.cc
M src/dev/net/ns_gige.cc
M src/dev/net/sinic.cc
M src/python/m5/params.py
M src/python/pybind11/core.cc
9 files changed, 24 insertions(+), 23 deletions(-)



diff --git a/src/base/inet.cc b/src/base/inet.cc
index 7ae36c3..7ac6858 100644
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -50,7 +50,7 @@
 #include "base/logging.hh"
 #include "base/types.hh"

-namespace Net {
+namespace network {

 EthAddr::EthAddr()
 {
@@ -401,5 +401,4 @@
 return split_point;
 }

-
-} // namespace Net
+} // namespace network
diff --git a/src/base/inet.hh b/src/base/inet.hh
index b6f0eb1..c5ebc9e 100644
--- a/src/base/inet.hh
+++ b/src/base/inet.hh
@@ -47,6 +47,7 @@
 #include 
 #include 

+#include "base/compiler.hh"
 #include "base/types.hh"
 #include "dev/net/etherpkt.hh"
 #include "dnet/os.h"
@@ -64,7 +65,8 @@
 #include "dnet/blob.h"
 #include "dnet/rand.h"

-namespace Net {
+GEM5_DEPRECATED_NAMESPACE(Net, network);
+namespace network {

 /*
  * Ethernet Stuff
@@ -828,6 +830,6 @@
  */
 int hsplit(const EthPacketPtr );

-} // namespace Net
+} // namespace network

 #endif // __BASE_INET_HH__
diff --git a/src/dev/net/etherswitch.cc b/src/dev/net/etherswitch.cc
index 13439f8..4bf3c52 100644
--- a/src/dev/net/etherswitch.cc
+++ b/src/dev/net/etherswitch.cc
@@ -133,8 +133,8 @@
 bool
 EtherSwitch::Interface::recvPacket(EthPacketPtr packet)
 {
-Net::EthAddr destMacAddr(packet->data);
-Net::EthAddr srcMacAddr(>data[6]);
+network::EthAddr destMacAddr(packet->data);
+network::EthAddr srcMacAddr(>data[6]);

 learnSenderAddr(srcMacAddr, this);
 Interface *receiver = lookupDestPort(destMacAddr);
@@ -206,7 +206,7 @@
 }

 EtherSwitch::Interface*
-EtherSwitch::Interface::lookupDestPort(Net::EthAddr destMacAddr)
+EtherSwitch::Interface::lookupDestPort(network::EthAddr destMacAddr)
 {
 auto it = parent->forwardingTable.find(uint64_t(destMacAddr));

@@ -230,7 +230,7 @@
 }

 void
-EtherSwitch::Interface::learnSenderAddr(Net::EthAddr srcMacAddr,
+EtherSwitch::Interface::learnSenderAddr(network::EthAddr srcMacAddr,
   Interface *sender)
 {
 // learn the port for the sending MAC address
diff --git a/src/dev/net/etherswitch.hh b/src/dev/net/etherswitch.hh
index 3c6a4c8..7cc2c3d 100644
--- a/src/dev/net/etherswitch.hh
+++ b/src/dev/net/etherswitch.hh
@@ -81,8 +81,8 @@
 void sendDone() {}
 Tick switchingDelay();

-Interface* lookupDestPort(Net::EthAddr destAddr);
-void learnSenderAddr(Net::EthAddr srcMacAddr, Interface *sender);
+Interface* lookupDestPort(network::EthAddr destAddr);
+void learnSenderAddr(network::EthAddr srcMacAddr, Interface  
*sender);


 void serialize(CheckpointOut ) const;
 void unserialize(CheckpointIn );
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 88cd0d5..b3b5122 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -53,7 +53,7 @@
 #include "sim/system.hh"

 using namespace igbreg;
-using namespace Net;
+using namespace network;

 IGbE::IGbE(const Params )
 : EtherDevice(p), etherInt(NULL),
diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc
index a350762..986b043 100644
--- a/src/dev/net/ns_gige.cc
+++ b/src/dev/net/ns_gige.cc
@@ -85,7 +85,7 @@
 "dmaWriteWaiting"
 };

-using namespace Net;
+using namespace network;

 ///
 //
diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index e6ebfd3..ad50539 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -43,7 +43,7 @@
 #include "sim/eventq.hh"
 #include "sim/stats.hh"

-using namespace Net;
+using namespace network;

 namespace sinic {

diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 460a7d0..91a7241 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -934,7 +934,7 @@
 return value

 class EthernetAddr(ParamValue):
-cxx_type = 'Net::EthAddr'
+cxx_type = 'network::EthAddr'
 ex_str = "00:90:00:00:00:01"
 cmd_line_settable = True

@@ -981,13 +981,13 @@

 @classmethod
 def cxx_ini_parse(self, code, src, dest, ret):
-code('%s = Net::EthAddr(%s);' % (dest, src))
+code('%s = network::EthAddr(%s);' % (dest, src))
 code('%s true;' % ret)

 # When initializing an 

[gem5-dev] Change in gem5/gem5[develop]: arch: Rename FreeBSD namespace as free_bsd

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45419 )



Change subject: arch: Rename FreeBSD namespace as free_bsd
..

arch: Rename FreeBSD namespace as free_bsd

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

FreeBSD became free_bsd.

Change-Id: If3fc4b04e60e6e1e790962dc81744ec7f712d8a6
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/generic/freebsd/threadinfo.hh
M src/kern/freebsd/events.cc
M src/kern/freebsd/events.hh
4 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 959581b..d6e9533 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -45,7 +45,7 @@
 #include "mem/physical.hh"
 #include "sim/stat_control.hh"

-using namespace FreeBSD;
+using namespace free_bsd;

 namespace ArmISA
 {
diff --git a/src/arch/generic/freebsd/threadinfo.hh  
b/src/arch/generic/freebsd/threadinfo.hh

index 28184e7..cd04991 100644
--- a/src/arch/generic/freebsd/threadinfo.hh
+++ b/src/arch/generic/freebsd/threadinfo.hh
@@ -36,7 +36,7 @@
 #include "cpu/thread_context.hh"
 #include "sim/system.hh"

-namespace FreeBSD {
+namespace free_bsd {

 class ThreadInfo
 {
@@ -54,6 +54,6 @@
 {}
 };

-} // namespace FreeBSD
+} // namespace free_bsd

 #endif // __ARCH_GENERIC_FREEBSD_THREADINFO_HH__
diff --git a/src/kern/freebsd/events.cc b/src/kern/freebsd/events.cc
index 0a78076..d5bc187 100644
--- a/src/kern/freebsd/events.cc
+++ b/src/kern/freebsd/events.cc
@@ -40,8 +40,7 @@
 #include "kern/system_events.hh"
 #include "sim/system.hh"

-namespace FreeBSD
-{
+namespace free_bsd {

 void
 onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
@@ -60,4 +59,4 @@
 tc->quiesceTick(curTick() + sim_clock::Int::ns * time);
 }

-} // namespace FreeBSD
+} // namespace free_bsd
diff --git a/src/kern/freebsd/events.hh b/src/kern/freebsd/events.hh
index ebf6128..817f8b1 100644
--- a/src/kern/freebsd/events.hh
+++ b/src/kern/freebsd/events.hh
@@ -33,11 +33,12 @@
 #ifndef __KERN_FREEBSD_EVENTS_HH__
 #define __KERN_FREEBSD_EVENTS_HH__

+#include "base/compiler.hh"
 #include "kern/system_events.hh"
 #include "sim/guest_abi.hh"

-namespace FreeBSD
-{
+GEM5_DEPRECATED_NAMESPACE(FreeBSD, free_bsd);
+namespace free_bsd {

 void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t  
time);



--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45419
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If3fc4b04e60e6e1e790962dc81744ec7f712d8a6
Gerrit-Change-Number: 45419
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Rename network variables as net

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45416 )



Change subject: mem-ruby: Rename network variables as net
..

mem-ruby: Rename network variables as net

Pave the way for a network namespace.

Change-Id: Ib109a5e65eb1b88cfae59a77986f01b739071232
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/ruby/system/RubySystem.cc
1 file changed, 10 insertions(+), 10 deletions(-)



diff --git a/src/mem/ruby/system/RubySystem.cc  
b/src/mem/ruby/system/RubySystem.cc

index fcb407f..38f0634 100644
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -106,11 +106,11 @@
 }

 void
-RubySystem::registerMachineID(const MachineID& mach_id, Network* network)
+RubySystem::registerMachineID(const MachineID& mach_id, Network* net)
 {
 int network_id = -1;
 for (int idx = 0; idx < m_networks.size(); ++idx) {
-if (m_networks[idx].get() == network) {
+if (m_networks[idx].get() == net) {
 network_id = idx;
 }
 }
@@ -467,8 +467,8 @@
 RubySystem::resetStats()
 {
 m_start_cycle = curCycle();
-for (auto& network : m_networks) {
-network->resetStats();
+for (auto& net : m_networks) {
+net->resetStats();
 }
 }

@@ -580,8 +580,8 @@
 DPRINTF(RubySystem, "Network functionalRead lookup "
 "(num_maybe_stale=%d, num_busy = %d)\n",
 num_maybe_stale, num_busy);
-for (auto& network : m_networks) {
-if (network->functionalRead(pkt))
+for (auto& net : m_networks) {
+if (net->functionalRead(pkt))
 return true;
 }
 }
@@ -661,8 +661,8 @@
 ctrl->functionalRead(line_address, pkt, bytes);
 ctrl->functionalReadBuffers(pkt, bytes);
 }
-for (auto& network : m_networks) {
-network->functionalRead(pkt, bytes);
+for (auto& net : m_networks) {
+net->functionalRead(pkt, bytes);
 }
 for (auto ctrl : ctrl_others) {
 ctrl->functionalRead(line_address, pkt, bytes);
@@ -720,8 +720,8 @@
 }
 }

-for (auto& network : m_networks) {
-num_functional_writes += network->functionalWrite(pkt);
+for (auto& net : m_networks) {
+num_functional_writes += net->functionalWrite(pkt);
 }
 DPRINTF(RubySystem, "Messages written = %u\n", num_functional_writes);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45416
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib109a5e65eb1b88cfae59a77986f01b739071232
Gerrit-Change-Number: 45416
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Rename units variable as enableUnits

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45414 )



Change subject: base-stats: Rename units variable as enableUnits
..

base-stats: Rename units variable as enableUnits

Pave the way for a units namespace.

Change-Id: Idd8516f0297be7ba4a76b69315c4a4935e57d937
Signed-off-by: Daniel R. Carvalho 
---
M src/base/stats/text.cc
M src/base/stats/text.hh
2 files changed, 15 insertions(+), 15 deletions(-)



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 5718a36..94f21cd 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -226,7 +226,7 @@
 int precision;
 bool descriptions;
 std::string desc;
-bool units;
+bool enableUnits;
 std::string unitStr;
 bool spaces;

@@ -243,7 +243,7 @@
 precision = _precision;
 descriptions = enable_descriptions;
 desc = _desc;
-units = enable_units;
+enableUnits = enable_units;
 unitStr = unit_str;
 spaces = enable_spaces;
 }
@@ -251,7 +251,7 @@
 void
 printUnits(std::ostream ) const
 {
-if (units && !unitStr.empty()) {
+if (enableUnits && !unitStr.empty()) {
 ccprintf(stream, " (%s)", unitStr);
 }
 }
@@ -369,8 +369,8 @@
 std::string base = name + separatorString;

 ScalarPrint print(spaces);
-print.setup(name, flags, precision, descriptions, desc, units, unitStr,
-spaces);
+print.setup(name, flags, precision, descriptions, desc, enableUnits,
+unitStr, spaces);
 print.pdf = _total ? 0.0 : NAN;
 print.cdf = _total ? 0.0 : NAN;

@@ -464,8 +464,8 @@
 DistPrint::init(const Text *text, const Info )
 {
 setup(text->statName(info.name), info.flags, info.precision,
-text->descriptions, info.desc, text->units,  
info.unit->getUnitString(),

-text->spaces);
+text->descriptions, info.desc, text->enableUnits,
+info.unit->getUnitString(), text->spaces);
 separatorString = info.separatorString;
 if (spaces) {
 nameSpaces = 40;
@@ -611,7 +611,7 @@

 ScalarPrint print(spaces);
 print.setup(statName(info.name), info.flags, info.precision,  
descriptions,

-info.desc, units, info.unit->getUnitString(), spaces);
+info.desc, enableUnits, info.unit->getUnitString(), spaces);
 print.value = info.result();
 print.pdf = NAN;
 print.cdf = NAN;
@@ -628,7 +628,7 @@
 size_type size = info.size();
 VectorPrint print(spaces);
 print.setup(statName(info.name), info.flags, info.precision,  
descriptions,

-info.desc, units, info.unit->getUnitString(), spaces);
+info.desc, enableUnits, info.unit->getUnitString(), spaces);
 print.separatorString = info.separatorString;
 print.vec = info.result();
 print.total = info.total();
@@ -674,7 +674,7 @@
 print.flags = info.flags;
 print.separatorString = info.separatorString;
 print.descriptions = descriptions;
-print.units = units;
+print.enableUnits = enableUnits;
 print.precision = info.precision;
 print.forceSubnames = true;

@@ -779,7 +779,7 @@
 SparseHistPrint::init(const Text *text, const Info )
 {
 setup(text->statName(info.name), info.flags, info.precision,
-text->descriptions, info.desc, text->units,
+text->descriptions, info.desc, text->enableUnits,
 info.unit->getUnitString(), text->spaces);
 separatorString = info.separatorString;
 }
@@ -791,8 +791,8 @@
 std::string base = name + separatorString;

 ScalarPrint print(spaces);
-print.setup(base + "samples", flags, precision, descriptions, desc,  
units,

-unitStr, spaces);
+print.setup(base + "samples", flags, precision, descriptions, desc,
+enableUnits, unitStr, spaces);
 print.pdf = NAN;
 print.cdf = NAN;
 print.value = data.samples;
@@ -829,7 +829,7 @@
 if (!connected) {
 text.open(*simout.findOrCreate(filename)->stream());
 text.descriptions = desc;
-text.units = desc; // the units are printed if descs are
+text.enableUnits = desc; // the units are printed if descs are
 text.spaces = spaces;
 connected = true;
 }
diff --git a/src/base/stats/text.hh b/src/base/stats/text.hh
index d5ee7f7..5121a4f 100644
--- a/src/base/stats/text.hh
+++ b/src/base/stats/text.hh
@@ -64,7 +64,7 @@
 bool noOutput(const Info );

   public:
-bool units;
+bool enableUnits;
 bool descriptions;
 bool spaces;


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45414
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd8516f0297be7ba4a76b69315c4a4935e57d937
Gerrit-Change-Number: 45414
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 

[gem5-dev] Change in gem5/gem5[develop]: sim: Rename ProbePoints namespace as probing

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45412 )



Change subject: sim: Rename ProbePoints namespace as probing
..

sim: Rename ProbePoints namespace as probing

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ProbePoints became ::probing.

"probing" was chosen over "probe_points" because the
namespace contains more than solely probe points; it
contains all classes related to the act of probing.

Change-Id: I44567974a521707593739a2bd5933391803e5b51
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/bpred_unit.hh
M src/mem/comm_monitor.cc
M src/mem/comm_monitor.hh
M src/mem/probes/base.hh
M src/mem/probes/mem_footprint.cc
M src/mem/probes/mem_footprint.hh
M src/mem/probes/mem_trace.cc
M src/mem/probes/mem_trace.hh
M src/mem/probes/stack_dist.cc
M src/mem/probes/stack_dist.hh
M src/sim/probe/mem.hh
M src/sim/probe/pmu.hh
M src/sim/probe/probe.hh
18 files changed, 44 insertions(+), 43 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 93995c0..991d883 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -569,7 +569,7 @@
 void
 TLB::regProbePoints()
 {
-ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
+ppRefills.reset(new probing::PMU(getProbeManager(), "Refills"));
 }

 Fault
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 5aa72b5..c1e767b 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -200,7 +200,7 @@
 } stats;

 /** PMU probe for TLB refills */
-ProbePoints::PMUUPtr ppRefills;
+probing::PMUUPtr ppRefills;

 int rangeMRU; //On lookup, only move entries ahead when outside  
rangeMRU


diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index ce82e3c..8f211a0 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -324,11 +324,11 @@

 }

-ProbePoints::PMUUPtr
+probing::PMUUPtr
 BaseCPU::pmuProbePoint(const char *name)
 {
-ProbePoints::PMUUPtr ptr;
-ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
+probing::PMUUPtr ptr;
+ptr.reset(new probing::PMU(getProbeManager(), name));

 return ptr;
 }
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 6d324da..e0055d6 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -482,7 +482,7 @@
  * @param name Name of the probe point.
  * @return A unique_ptr to the new probe point.
  */
-ProbePoints::PMUUPtr pmuProbePoint(const char *name);
+probing::PMUUPtr pmuProbePoint(const char *name);

 /**
  * Instruction commit probe point.
@@ -492,22 +492,22 @@
  * instruction. However, CPU models committing bundles of
  * instructions may call notify once for the entire bundle.
  */
-ProbePoints::PMUUPtr ppRetiredInsts;
-ProbePoints::PMUUPtr ppRetiredInstsPC;
+probing::PMUUPtr ppRetiredInsts;
+probing::PMUUPtr ppRetiredInstsPC;

 /** Retired load instructions */
-ProbePoints::PMUUPtr ppRetiredLoads;
+probing::PMUUPtr ppRetiredLoads;
 /** Retired store instructions */
-ProbePoints::PMUUPtr ppRetiredStores;
+probing::PMUUPtr ppRetiredStores;

 /** Retired branches (any type) */
-ProbePoints::PMUUPtr ppRetiredBranches;
+probing::PMUUPtr ppRetiredBranches;

 /** CPU cycle counter even if any thread Context is suspended*/
-ProbePoints::PMUUPtr ppAllCycles;
+probing::PMUUPtr ppAllCycles;

 /** CPU cycle counter, only counts if any thread contexts is active **/
-ProbePoints::PMUUPtr ppActiveCycles;
+probing::PMUUPtr ppActiveCycles;

 /**
  * ProbePoint that signals transitions of threadContexts sets.
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index be19421..2630fb4 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -90,11 +90,11 @@
 BTBHitRatio.precision(6);
 }

-ProbePoints::PMUUPtr
+probing::PMUUPtr
 BPredUnit::pmuProbePoint(const char *name)
 {
-ProbePoints::PMUUPtr ptr;
-ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
+probing::PMUUPtr ptr;
+ptr.reset(new probing::PMU(getProbeManager(), name));

 return ptr;
 }
diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index 1cdb27c..d4a03ff 100644
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -325,7 +325,7 @@
  * @param name Name of the probe point.
  * @return A unique_ptr to the new probe point.
  */
-ProbePoints::PMUUPtr pmuProbePoint(const char *name);
+probing::PMUUPtr pmuProbePoint(const char *name);


 /**
@@ -333,10 +333,10 @@
  *
  * @note This counter includes speculative branches.
  */
-ProbePoints::PMUUPtr ppBranches;
+probing::PMUUPtr ppBranches;

 /** Miss-predicted branches */
-

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename ReplacementPolicy namespace as replacement_policy

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45405 )



Change subject: mem: Rename ReplacementPolicy namespace as  
replacement_policy

..

mem: Rename ReplacementPolicy namespace as replacement_policy

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

ReplacementPolicy became replacement_policy.

Change-Id: Id46cd9d89e9424fd3c5484e2f9c69ef2b73f135b
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/prefetch/associative_set.hh
M src/mem/cache/prefetch/associative_set_impl.hh
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/replaceable_entry.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.hh
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/sector_tags.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
30 files changed, 72 insertions(+), 71 deletions(-)



diff --git a/src/mem/cache/prefetch/associative_set.hh  
b/src/mem/cache/prefetch/associative_set.hh

index 61fd1f6..d349dc0 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -55,7 +55,7 @@
 /** Pointer to the indexing policy */
 BaseIndexingPolicy* const indexingPolicy;
 /** Pointer to the replacement policy */
-ReplacementPolicy::Base* const replacementPolicy;
+replacement_policy::Base* const replacementPolicy;
 /** Vector containing the entries of the container */
 std::vector entries;

@@ -70,7 +70,7 @@
  * @param init_val initial value of the elements of the set
  */
 AssociativeSet(int assoc, int num_entries, BaseIndexingPolicy  
*idx_policy,
-ReplacementPolicy::Base *rpl_policy, Entry const _val =  
Entry());
+replacement_policy::Base *rpl_policy, Entry const _val =  
Entry());


 /**
  * Find an entry within the set
diff --git a/src/mem/cache/prefetch/associative_set_impl.hh  
b/src/mem/cache/prefetch/associative_set_impl.hh

index 4b16dbb..6118009 100644
--- a/src/mem/cache/prefetch/associative_set_impl.hh
+++ b/src/mem/cache/prefetch/associative_set_impl.hh
@@ -34,7 +34,7 @@

 template
 AssociativeSet::AssociativeSet(int assoc, int num_entries,
-BaseIndexingPolicy *idx_policy, ReplacementPolicy::Base  
*rpl_policy,
+BaseIndexingPolicy *idx_policy, replacement_policy::Base  
*rpl_policy,

 Entry const _value)
   : associativity(assoc), numEntries(num_entries),  
indexingPolicy(idx_policy),

 replacementPolicy(rpl_policy), entries(numEntries, init_value)
diff --git a/src/mem/cache/prefetch/stride.hh  
b/src/mem/cache/prefetch/stride.hh

index 36fc194..b4b1505 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -61,7 +61,7 @@
 #include "params/StridePrefetcherHashedSetAssociative.hh"

 class BaseIndexingPolicy;
-namespace ReplacementPolicy {
+namespace replacement_policy {
 class Base;
 }
 struct StridePrefetcherParams;
@@ -109,14 +109,13 @@
 const int numEntries;

 BaseIndexingPolicy* const indexingPolicy;
-ReplacementPolicy::Base* const replacementPolicy;
+replacement_policy::Base* const replacementPolicy;

 PCTableInfo(int assoc, int num_entries,
 BaseIndexingPolicy* indexing_policy,
-ReplacementPolicy::Base* replacement_policy)
+replacement_policy::Base* repl_policy)
   : assoc(assoc), numEntries(num_entries),
-indexingPolicy(indexing_policy),
-replacementPolicy(replacement_policy)
+indexingPolicy(indexing_policy), replacementPolicy(repl_policy)
 {
 }
 } pcTableInfo;
diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index 

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Rename prefetch variable as isPrefetch

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45409 )



Change subject: gpu-compute: Rename prefetch variable as isPrefetch
..

gpu-compute: Rename prefetch variable as isPrefetch

Pave the way for a prefetch namespace.

Change-Id: I4372abb5603eb6a920f7ff127cde54cb24e31377
Signed-off-by: Daniel R. Carvalho 
---
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
3 files changed, 14 insertions(+), 14 deletions(-)



diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index f0afd827..cf79b05 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -676,7 +676,7 @@
 TranslationState *sender_state =
 safe_cast(pkt->senderState);

-bool update_stats = !sender_state->prefetch;
+bool update_stats = !sender_state->isPrefetch;
 ThreadContext * tmp_tc = sender_state->tc;

 DPRINTF(GPUTLB, "Translation req. for virt. page addr %#x\n",
@@ -891,7 +891,7 @@
 safe_cast(pkt->senderState);

 int req_cnt = tmp_sender_state->reqCnt.back();
-bool update_stats = !tmp_sender_state->prefetch;
+bool update_stats = !tmp_sender_state->isPrefetch;


 if (outcome == TLB_HIT) {
@@ -1102,7 +1102,7 @@
  * This feature could be used to explore security issues around
  * speculative memory accesses.
  */
-if (!sender_state->prefetch && sender_state->tlbEntry)
+if (!sender_state->isPrefetch && sender_state->tlbEntry)
 pagingProtectionChecks(tc, pkt, local_entry, mode);

 int page_size = local_entry->size();
@@ -1124,7 +1124,7 @@
 safe_cast(pkt->senderState);

 ThreadContext *tc = sender_state->tc;
-bool update_stats = !sender_state->prefetch;
+bool update_stats = !sender_state->isPrefetch;

 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
 X86ISA::PageBytes);
@@ -1154,7 +1154,7 @@
 // there is a TLB below -> propagate down the TLB hierarchy
 tlb->memSidePort[0]->sendFunctional(pkt);
 // If no valid translation from a prefetch, then just  
return

-if (sender_state->prefetch && !pkt->req->hasPaddr())
+if (sender_state->isPrefetch && !pkt->req->hasPaddr())
 return;
 } else {
 // Need to access the page table and update the TLB
@@ -1176,7 +1176,7 @@
 pte = p->pTable->lookup(vaddr);
 }

-if (!sender_state->prefetch) {
+if (!sender_state->isPrefetch) {
 // no PageFaults are permitted after
 // the second page table lookup
 assert(pte);
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 1df907b..b678f6b 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -293,7 +293,7 @@
 */
 TlbEntry *tlbEntry;
 // Is this a TLB prefetch request?
-bool prefetch;
+bool isPrefetch;
 // When was the req for this translation issued
 uint64_t issueTime;
 // Remember where this came from
@@ -307,10 +307,10 @@
 Packet::SenderState *saved;

 TranslationState(Mode tlb_mode, ThreadContext *_tc,
- bool _prefetch=false,
+ bool is_prefetch=false,
  Packet::SenderState *_saved=nullptr)
 : tlbMode(tlb_mode), tc(_tc), tlbEntry(nullptr),
-  prefetch(_prefetch), issueTime(0),
+  isPrefetch(is_prefetch), issueTime(0),
   hitLevel(0),saved(_saved) { }
 };

diff --git a/src/gpu-compute/tlb_coalescer.cc  
b/src/gpu-compute/tlb_coalescer.cc

index 08f0f95..ea754c1 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -127,7 +127,7 @@
 // when we can coalesce a packet update the reqCnt
 // that is the number of packets represented by
 // this coalesced packet
-if (!incoming_state->prefetch)
+if (!incoming_state->isPrefetch)
 coalesced_state->reqCnt.back() += incoming_state->reqCnt.back();

 return true;
@@ -170,7 +170,7 @@

 // we are sending the packet back, so pop the reqCnt associated
 // with this level in the TLB hiearchy
-if (!sender_state->prefetch)
+if (!sender_state->isPrefetch)
 sender_state->reqCnt.pop_back();

 /*
@@ -241,7 +241,7 @@
 // push back the port to remember the path back
 sender_state->ports.push_back(this);

-bool update_stats = !sender_state->prefetch;
+bool update_stats = !sender_state->isPrefetch;

 if 

[gem5-dev] Change in gem5/gem5[develop]: base-stats: Create base struct for print structs

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45413 )



Change subject: base-stats: Create base struct for print structs
..

base-stats: Create base struct for print structs

Reduce code duplication.

Change-Id: I4d31b80ef946d9c1d964910e861088cdd2472f7c
Signed-off-by: Daniel R. Carvalho 
---
M src/base/stats/text.cc
1 file changed, 65 insertions(+), 94 deletions(-)



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 26f1622..5718a36 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -219,17 +219,47 @@
 return val.str();
 }

-struct ScalarPrint
+struct BasePrint
+{
+std::string name;
+Flags flags;
+int precision;
+bool descriptions;
+std::string desc;
+bool units;
+std::string unitStr;
+bool spaces;
+
+BasePrint(bool _spaces=false) : spaces(_spaces) {}
+
+void
+setup(std::string _name, Flags _flags, int _precision,
+bool enable_descriptions, std::string _desc,
+bool enable_units, std::string unit_str,
+bool enable_spaces)
+{
+name = _name;
+flags = _flags;
+precision = _precision;
+descriptions = enable_descriptions;
+desc = _desc;
+units = enable_units;
+unitStr = unit_str;
+spaces = enable_spaces;
+}
+
+void
+printUnits(std::ostream ) const
+{
+if (units && !unitStr.empty()) {
+ccprintf(stream, " (%s)", unitStr);
+}
+}
+};
+
+struct ScalarPrint : public BasePrint
 {
 Result value;
-std::string name;
-std::string desc;
-std::string unitStr;
-Flags flags;
-bool descriptions;
-bool spaces;
-bool units;
-int precision;
 Result pdf;
 Result cdf;
 int nameSpaces;
@@ -237,7 +267,9 @@
 int pdfstrSpaces;
 int cdfstrSpaces;

-ScalarPrint(bool spaces) : spaces(spaces) {
+ScalarPrint(bool spaces)
+  : BasePrint(spaces)
+{
 if (spaces) {
 nameSpaces = 40;
 valueSpaces = 12;
@@ -294,33 +326,25 @@
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
 }
-if (units && !unitStr.empty()) {
-ccprintf(stream, " (%s)", unitStr);
-}
+printUnits(stream);
 stream << std::endl;
 }
 }

-struct VectorPrint
+struct VectorPrint : public BasePrint
 {
-std::string name;
 std::string separatorString;
-std::string desc;
-std::string unitStr;
 std::vector subnames;
 std::vector subdescs;
-Flags flags;
-bool units;
-bool descriptions;
-bool spaces;
-int precision;
 VResult vec;
 Result total;
 bool forceSubnames;
 int nameSpaces;

 VectorPrint() = delete;
-VectorPrint(bool spaces) : spaces(spaces) {
+VectorPrint(bool spaces)
+  : BasePrint(spaces)
+{
 if (spaces) {
 nameSpaces = 40;
 } else {
@@ -345,13 +369,8 @@
 std::string base = name + separatorString;

 ScalarPrint print(spaces);
-print.name = name;
-print.desc = desc;
-print.unitStr = unitStr;
-print.precision = precision;
-print.descriptions = descriptions;
-print.units = units;
-print.flags = flags;
+print.setup(name, flags, precision, descriptions, desc, units, unitStr,
+spaces);
 print.pdf = _total ? 0.0 : NAN;
 print.cdf = _total ? 0.0 : NAN;

@@ -391,9 +410,7 @@
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
 }
-if (units && !unitStr.empty()) {
-ccprintf(stream, " (%s)", unitStr);
-}
+printUnits(stream);
 stream << std::endl;
 }
 }
@@ -409,17 +426,9 @@
 }
 }

-struct DistPrint
+struct DistPrint : public BasePrint
 {
-std::string name;
 std::string separatorString;
-std::string desc;
-std::string unitStr;
-Flags flags;
-bool units;
-bool descriptions;
-bool spaces;
-int precision;
 int nameSpaces;

 const DistData 
@@ -454,15 +463,10 @@
 void
 DistPrint::init(const Text *text, const Info )
 {
-name = text->statName(info.name);
+setup(text->statName(info.name), info.flags, info.precision,
+text->descriptions, info.desc, text->units,  
info.unit->getUnitString(),

+text->spaces);
 separatorString = info.separatorString;
-desc = info.desc;
-unitStr = info.unit->getUnitString();
-flags = info.flags;
-precision = info.precision;
-descriptions = text->descriptions;
-units = text->units;
-spaces = text->spaces;
 if (spaces) {
 nameSpaces = 40;
 } else {
@@ -569,9 +573,7 @@
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
 }
-if (units && !unitStr.empty()) {
-ccprintf(stream, " (%s)", 

[gem5-dev] Change in gem5/gem5[develop]: cpu,mem: Rename ContextSwitchTaskId namespace

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45411 )



Change subject: cpu,mem: Rename ContextSwitchTaskId namespace
..

cpu,mem: Rename ContextSwitchTaskId namespace

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ContextSwitchTaskId becomes ::context_switch_task_id.

Change-Id: If3884a5da7afe6144954d556b3b54f659bb7afb5
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/linux/fs_workload.cc
M src/arch/arm/table_walker.cc
M src/cpu/base.cc
M src/dev/arm/gic_v3_its.cc
M src/dev/arm/smmu_v3_proc.cc
M src/dev/dma_device.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/tags/base.cc
M src/mem/request.hh
10 files changed, 19 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index dc70765..e392a86 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -255,9 +255,9 @@
 std::map::iterator itr = taskMap.find(pid);
 if (itr == taskMap.end()) {
 uint32_t map_size = taskMap.size();
-if (map_size > ContextSwitchTaskId::MaxNormalTaskId + 1) {
+if (map_size > context_switch_task_id::MaxNormalTaskId + 1) {
 warn_once("Error out of identifiers for cache occupancy  
stats");

-taskMap[pid] = ContextSwitchTaskId::Unknown;
+taskMap[pid] = context_switch_task_id::Unknown;
 } else {
 taskMap[pid] = map_size;
 }
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 9fa4315..d5cf0a9 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -2174,7 +2174,7 @@
 RequestPtr req = std::make_shared(
 descAddr, numBytes, flags, requestorId);

-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);
 PacketPtr  pkt = new Packet(req, MemCmd::ReadReq);
 pkt->dataStatic(data);
 port->sendFunctional(pkt);
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 1badf0f..ce82e3c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -125,7 +125,7 @@
 : ClockedObject(p), instCnt(0), _cpuId(p.cpu_id),  
_socketId(p.socket_id),

   _instRequestorId(p.system->getRequestorId(this, "inst")),
   _dataRequestorId(p.system->getRequestorId(this, "data")),
-  _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
+  _taskId(context_switch_task_id::Unknown), _pid(invldPid),
   _switchedOut(p.switched_out),  
_cacheLineSize(p.system->cacheLineSize()),

   interrupts(p.interrupts), numThreads(p.numThreads), system(p.system),
   previousCycle(0), previousState(CPU_STATE_SLEEP),
diff --git a/src/dev/arm/gic_v3_its.cc b/src/dev/arm/gic_v3_its.cc
index ee30eee..c30c33a 100644
--- a/src/dev/arm/gic_v3_its.cc
+++ b/src/dev/arm/gic_v3_its.cc
@@ -96,7 +96,7 @@
 RequestPtr req = std::make_shared(
 addr, size, 0, its.requestorId);

-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);

 a.pkt = new Packet(req, MemCmd::ReadReq);
 a.pkt->dataStatic(ptr);
@@ -120,7 +120,7 @@
 RequestPtr req = std::make_shared(
 addr, size, 0, its.requestorId);

-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);

 a.pkt = new Packet(req, MemCmd::WriteReq);
 a.pkt->dataStatic(ptr);
diff --git a/src/dev/arm/smmu_v3_proc.cc b/src/dev/arm/smmu_v3_proc.cc
index cb8aca5..866939b 100644
--- a/src/dev/arm/smmu_v3_proc.cc
+++ b/src/dev/arm/smmu_v3_proc.cc
@@ -81,7 +81,7 @@
 RequestPtr req = std::make_shared(
 addr, size, 0, smmu.requestorId);

-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);

 a.pkt = new Packet(req, MemCmd::ReadReq);
 a.pkt->dataStatic(ptr);
@@ -114,7 +114,7 @@
 RequestPtr req = std::make_shared(
 addr, size, 0, smmu.requestorId);

-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);

 a.pkt = new Packet(req, MemCmd::WriteReq);
 a.pkt->dataStatic(ptr);
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 9aebb7b..57cee49 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -114,7 +114,7 @@
 gen.addr(), gen.size(), flags, id);
 req->setStreamId(sid);
 req->setSubstreamId(ssid);
-req->taskId(ContextSwitchTaskId::DMA);
+req->taskId(context_switch_task_id::DMA);

 PacketPtr pkt = new Packet(req, cmd);

diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index ac2878a..ad1c052 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -201,7 +201,7 @@
 clearPrefetched();
 clearCoherenceBits(AllBits);

-

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Rename Encoder namespace as encoder

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45408 )



Change subject: mem-cache: Rename Encoder namespace as encoder
..

mem-cache: Rename Encoder namespace as encoder

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

compression::Encoder became compression::encoder.

Change-Id: I3ff2693fbbfc366952cf0f03414a00debae27635
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/compressors/encoders/base.hh
M src/mem/cache/compressors/encoders/huffman.cc
M src/mem/cache/compressors/encoders/huffman.hh
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/compressors/frequent_values.hh
5 files changed, 14 insertions(+), 11 deletions(-)



diff --git a/src/mem/cache/compressors/encoders/base.hh  
b/src/mem/cache/compressors/encoders/base.hh

index 8ca1168..a7b7aaf 100644
--- a/src/mem/cache/compressors/encoders/base.hh
+++ b/src/mem/cache/compressors/encoders/base.hh
@@ -31,8 +31,11 @@

 #include 

+#include "base/compiler.hh"
+
 namespace compression {
-namespace Encoder {
+GEM5_DEPRECATED_NAMESPACE(Encoder, encoder);
+namespace encoder {

 struct Code
 {
@@ -73,7 +76,7 @@
 virtual uint64_t decode(const uint64_t code) const = 0;
 };

-} // namespace Encoder
+} // namespace encoder
 } // namespace compression

 #endif //__MEM_CACHE_COMPRESSORS_ENCODERS_BASE_HH__
diff --git a/src/mem/cache/compressors/encoders/huffman.cc  
b/src/mem/cache/compressors/encoders/huffman.cc

index a6b19f7..b005d26 100644
--- a/src/mem/cache/compressors/encoders/huffman.cc
+++ b/src/mem/cache/compressors/encoders/huffman.cc
@@ -33,7 +33,7 @@
 #include "base/logging.hh"

 namespace compression {
-namespace Encoder {
+namespace encoder {

 Huffman::Huffman(uint64_t max_code_length)
   : Base(), maxCodeLength(max_code_length)
@@ -130,5 +130,5 @@
 return it->second;
 }

-} // namespace Encoder
+} // namespace encoder
 } // namespace compression
diff --git a/src/mem/cache/compressors/encoders/huffman.hh  
b/src/mem/cache/compressors/encoders/huffman.hh

index 27b79f0..f1379af 100644
--- a/src/mem/cache/compressors/encoders/huffman.hh
+++ b/src/mem/cache/compressors/encoders/huffman.hh
@@ -39,7 +39,7 @@
 #include "mem/cache/compressors/encoders/base.hh"

 namespace compression {
-namespace Encoder {
+namespace encoder {

 /**
  * This encoder builds a Huffman tree using the frequency of each value to
@@ -174,7 +174,7 @@
 void generateCodes(const Node* node, const Code& current_code);
 };

-} // namespace Encoder
+} // namespace encoder
 } // namespace compression

 #endif //__MEM_CACHE_COMPRESSORS_ENCODERS_HUFFMAN_HH__
diff --git a/src/mem/cache/compressors/frequent_values.cc  
b/src/mem/cache/compressors/frequent_values.cc

index e41be12..4a8f925 100644
--- a/src/mem/cache/compressors/frequent_values.cc
+++ b/src/mem/cache/compressors/frequent_values.cc
@@ -67,7 +67,7 @@
 // Compress every value sequentially. The compressed values are then
 // added to the final compressed data.
 for (const auto& chunk : chunks) {
-Encoder::Code code;
+encoder::Code code;
 int length = 0;
 if (phase == COMPRESSING) {
 VFTEntry* entry = VFT.findEntry(chunk, false);
@@ -141,7 +141,7 @@
 // its corresponding value, in order to make life easier we
 // search for the value and verify that the stored code
 // matches the table's
-GEM5_VAR_USED const Encoder::Code code =
+GEM5_VAR_USED const encoder::Code code =
 indexEncoder.encode(comp_chunk.value);

 // Either the value will be found and the codes match, or  
the
diff --git a/src/mem/cache/compressors/frequent_values.hh  
b/src/mem/cache/compressors/frequent_values.hh

index 2788583..fd4b33f 100644
--- a/src/mem/cache/compressors/frequent_values.hh
+++ b/src/mem/cache/compressors/frequent_values.hh
@@ -80,7 +80,7 @@
 const bool useHuffmanEncoding;

 /** The encoder applied to the VFT indices. */
-Encoder::Huffman indexEncoder;
+encoder::Huffman indexEncoder;

 /** Number of bits in the saturating counters. */
 const int counterBits;
@@ -197,7 +197,7 @@
 struct CompressedValue
 {
 /** The codeword.*/
-Encoder::Code code;
+encoder::Code code;

 /**
  * Original value, stored both for when the codeword marks an
@@ -205,7 +205,7 @@
  */
 uint64_t value;

-CompressedValue(Encoder::Code _code, uint64_t _value)
+CompressedValue(encoder::Code _code, uint64_t _value)
   : code(_code), value(_value)
 {
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45408
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Rename Prefetcher namespace as prefetch

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45410 )



Change subject: mem-cache: Rename Prefetcher namespace as prefetch
..

mem-cache: Rename Prefetcher namespace as prefetch

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Prefetcher became ::prefetcher.

"prefetch" was chosen over "prefetcher" to avoid generating
conflicts with the already existing variables. "prefetcher"
is a name that is expected to be more common in user's code
than "prefetch".

Change-Id: I8f07217f278a0229e05545b7847f2620ed208c66
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/base.hh
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/bop.cc
M src/mem/cache/prefetch/bop.hh
M src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
M src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
M src/mem/cache/prefetch/indirect_memory.cc
M src/mem/cache/prefetch/indirect_memory.hh
M src/mem/cache/prefetch/irregular_stream_buffer.cc
M src/mem/cache/prefetch/irregular_stream_buffer.hh
M src/mem/cache/prefetch/multi.cc
M src/mem/cache/prefetch/multi.hh
M src/mem/cache/prefetch/pif.cc
M src/mem/cache/prefetch/pif.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/sbooe.cc
M src/mem/cache/prefetch/sbooe.hh
M src/mem/cache/prefetch/signature_path.cc
M src/mem/cache/prefetch/signature_path.hh
M src/mem/cache/prefetch/signature_path_v2.cc
M src/mem/cache/prefetch/signature_path_v2.hh
M src/mem/cache/prefetch/slim_ampm.cc
M src/mem/cache/prefetch/slim_ampm.hh
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.cc
M src/mem/cache/prefetch/spatio_temporal_memory_streaming.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
34 files changed, 87 insertions(+), 85 deletions(-)



diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index dbe8eec..ac944cf 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -75,7 +75,7 @@
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"

-namespace Prefetcher {
+namespace prefetch {
 class Base;
 }
 class MSHR;
@@ -347,7 +347,7 @@
 compression::Base* compressor;

 /** Prefetcher */
-Prefetcher::Base *prefetcher;
+prefetch::Base *prefetcher;

 /** To probe when a cache hit occurs */
 ProbePointArg *ppHit;
diff --git a/src/mem/cache/prefetch/Prefetcher.py  
b/src/mem/cache/prefetch/Prefetcher.py

index 0840c60..0098763 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -59,7 +59,7 @@
 class BasePrefetcher(ClockedObject):
 type = 'BasePrefetcher'
 abstract = True
-cxx_class = 'Prefetcher::Base'
+cxx_class = 'prefetch::Base'
 cxx_header = "mem/cache/prefetch/base.hh"
 cxx_exports = [
 PyBindMethod("addEventProbe"),
@@ -111,7 +111,7 @@

 class MultiPrefetcher(BasePrefetcher):
 type = 'MultiPrefetcher'
-cxx_class = 'Prefetcher::Multi'
+cxx_class = 'prefetch::Multi'
 cxx_header = 'mem/cache/prefetch/multi.hh'

 prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
@@ -119,7 +119,7 @@
 class QueuedPrefetcher(BasePrefetcher):
 type = "QueuedPrefetcher"
 abstract = True
-cxx_class = "Prefetcher::Queued"
+cxx_class = "prefetch::Queued"
 cxx_header = "mem/cache/prefetch/queued.hh"
 latency = Param.Int(1, "Latency for generated prefetches")
 queue_size = Param.Int(32, "Maximum number of queued prefetches")
@@ -145,12 +145,12 @@

 class StridePrefetcherHashedSetAssociative(SetAssociative):
 type = 'StridePrefetcherHashedSetAssociative'
-cxx_class = 'Prefetcher::StridePrefetcherHashedSetAssociative'
+cxx_class = 'prefetch::StridePrefetcherHashedSetAssociative'
 cxx_header = "mem/cache/prefetch/stride.hh"

 class StridePrefetcher(QueuedPrefetcher):
 type = 'StridePrefetcher'
-cxx_class = 'Prefetcher::Stride'
+cxx_class = 'prefetch::Stride'
 cxx_header = "mem/cache/prefetch/stride.hh"

 # Do not consult stride prefetcher on instruction accesses
@@ -178,14 +178,14 @@

 class TaggedPrefetcher(QueuedPrefetcher):
 type = 'TaggedPrefetcher'
-cxx_class = 'Prefetcher::Tagged'
+cxx_class = 'prefetch::Tagged'
 cxx_header = "mem/cache/prefetch/tagged.hh"

 degree = Param.Int(2, "Number of prefetches to generate")

 class IndirectMemoryPrefetcher(QueuedPrefetcher):
 type = 'IndirectMemoryPrefetcher'
-cxx_class = 'Prefetcher::IndirectMemory'
+cxx_class = 'prefetch::IndirectMemory'
 cxx_header = "mem/cache/prefetch/indirect_memory.hh"
 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Rename Compressor namespace as compression

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45406 )



Change subject: mem-cache: Rename Compressor namespace as compression
..

mem-cache: Rename Compressor namespace as compression

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

Compressor became compression.

"compression" was chosen over "compressor" to avoid
generating conflicts with the already existing variables,
as well as because the namespace contains more than solely
compressors (e.g., encoders).

Change-Id: I7054845984784b0dffcc4fb90d66c5096a64194d
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/base.hh
M src/mem/cache/compressors/Compressors.py
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/compressors/base_delta.cc
M src/mem/cache/compressors/base_delta.hh
M src/mem/cache/compressors/base_delta_impl.hh
M src/mem/cache/compressors/base_dictionary_compressor.cc
M src/mem/cache/compressors/cpack.cc
M src/mem/cache/compressors/cpack.hh
M src/mem/cache/compressors/dictionary_compressor.hh
M src/mem/cache/compressors/dictionary_compressor_impl.hh
M src/mem/cache/compressors/encoders/base.hh
M src/mem/cache/compressors/encoders/huffman.cc
M src/mem/cache/compressors/encoders/huffman.hh
M src/mem/cache/compressors/fpc.cc
M src/mem/cache/compressors/fpc.hh
M src/mem/cache/compressors/fpcd.cc
M src/mem/cache/compressors/fpcd.hh
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/compressors/frequent_values.hh
M src/mem/cache/compressors/multi.cc
M src/mem/cache/compressors/multi.hh
M src/mem/cache/compressors/perfect.cc
M src/mem/cache/compressors/perfect.hh
M src/mem/cache/compressors/repeated_qwords.cc
M src/mem/cache/compressors/repeated_qwords.hh
M src/mem/cache/compressors/zero.cc
M src/mem/cache/compressors/zero.hh
29 files changed, 74 insertions(+), 71 deletions(-)



diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 3285c97..dbe8eec 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -344,7 +344,7 @@
 BaseTags *tags;

 /** Compression method being used. */
-Compressor::Base* compressor;
+compression::Base* compressor;

 /** Prefetcher */
 Prefetcher::Base *prefetcher;
diff --git a/src/mem/cache/compressors/Compressors.py  
b/src/mem/cache/compressors/Compressors.py

index a05f1de..eb5b406 100644
--- a/src/mem/cache/compressors/Compressors.py
+++ b/src/mem/cache/compressors/Compressors.py
@@ -34,7 +34,7 @@
 class BaseCacheCompressor(SimObject):
 type = 'BaseCacheCompressor'
 abstract = True
-cxx_class = 'Compressor::Base'
+cxx_class = 'compression::Base'
 cxx_header = "mem/cache/compressors/base.hh"

 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
@@ -56,7 +56,7 @@
 class BaseDictionaryCompressor(BaseCacheCompressor):
 type = 'BaseDictionaryCompressor'
 abstract = True
-cxx_class = 'Compressor::BaseDictionaryCompressor'
+cxx_class = 'compression::BaseDictionaryCompressor'
 cxx_header = "mem/cache/compressors/dictionary_compressor.hh"

 dictionary_size = Param.Int(Parent.cache_line_size,
@@ -64,7 +64,7 @@

 class Base64Delta8(BaseDictionaryCompressor):
 type = 'Base64Delta8'
-cxx_class = 'Compressor::Base64Delta8'
+cxx_class = 'compression::Base64Delta8'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 64
@@ -77,7 +77,7 @@

 class Base64Delta16(BaseDictionaryCompressor):
 type = 'Base64Delta16'
-cxx_class = 'Compressor::Base64Delta16'
+cxx_class = 'compression::Base64Delta16'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 64
@@ -90,7 +90,7 @@

 class Base64Delta32(BaseDictionaryCompressor):
 type = 'Base64Delta32'
-cxx_class = 'Compressor::Base64Delta32'
+cxx_class = 'compression::Base64Delta32'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 64
@@ -103,7 +103,7 @@

 class Base32Delta8(BaseDictionaryCompressor):
 type = 'Base32Delta8'
-cxx_class = 'Compressor::Base32Delta8'
+cxx_class = 'compression::Base32Delta8'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 32
@@ -116,7 +116,7 @@

 class Base32Delta16(BaseDictionaryCompressor):
 type = 'Base32Delta16'
-cxx_class = 'Compressor::Base32Delta16'
+cxx_class = 'compression::Base32Delta16'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 32
@@ -129,7 +129,7 @@

 class Base16Delta8(BaseDictionaryCompressor):
 type = 'Base16Delta8'
-cxx_class = 'Compressor::Base16Delta8'
+cxx_class = 'compression::Base16Delta8'
 cxx_header = "mem/cache/compressors/base_delta.hh"

 chunk_size_bits = 16
@@ -142,7 +142,7 @@

 class CPack(BaseDictionaryCompressor):
 type = 'CPack'
-cxx_class = 

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Rename encoder variables as indexEncoder

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45407 )



Change subject: mem-cache: Rename encoder variables as indexEncoder
..

mem-cache: Rename encoder variables as indexEncoder

Pave the way for an encoder namespace.

Change-Id: I5b55ac18a2973e25e53b097cd407861f5f60d646
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/compressors/frequent_values.hh
2 files changed, 9 insertions(+), 9 deletions(-)



diff --git a/src/mem/cache/compressors/frequent_values.cc  
b/src/mem/cache/compressors/frequent_values.cc

index 2615076..e41be12 100644
--- a/src/mem/cache/compressors/frequent_values.cc
+++ b/src/mem/cache/compressors/frequent_values.cc
@@ -42,7 +42,7 @@

 FrequentValues::FrequentValues(const Params )
   : Base(p), useHuffmanEncoding(p.max_code_length != 0),
-encoder(p.max_code_length), counterBits(p.counter_bits),
+indexEncoder(p.max_code_length), counterBits(p.counter_bits),
 codeGenerationTicks(p.code_generation_ticks),
 checkSaturation(p.check_saturation), numVFTEntries(p.vft_entries),
 numSamples(p.num_samples), takenSamples(0), phase(SAMPLING),
@@ -80,14 +80,14 @@

 // If using an index encoder, apply it
 if (useHuffmanEncoding) {
-code = encoder.encode(index);
+code = indexEncoder.encode(index);

 if (index == uncompressed_index) {
 code.length += chunkSizeBits;
 } else if (code.length > 64) {
 // If, for some reason, we could not generate an  
encoding

 // for the value, generate the uncompressed encoding
-code = encoder.encode(uncompressed_index);
+code = indexEncoder.encode(uncompressed_index);
 assert(code.length <= 64);
 code.length += chunkSizeBits;
 }
@@ -142,14 +142,14 @@
 // search for the value and verify that the stored code
 // matches the table's
 GEM5_VAR_USED const Encoder::Code code =
-encoder.encode(comp_chunk.value);
+indexEncoder.encode(comp_chunk.value);

 // Either the value will be found and the codes match, or  
the
 // value will not be found because it is an uncompressed  
entry

 assert(((code.length <= 64) &&
 (code.code == comp_chunk.code.code)) ||
 (comp_chunk.code.code ==
-encoder.encode(uncompressedValue).code));
+indexEncoder.encode(uncompressedValue).code));
 } else {
 // The value at the given VFT entry must match the one  
stored,

 // if it is not the uncompressed value
@@ -236,15 +236,15 @@
 // They are sorted such that the value with highest frequency is
 // the queue's top
 for (const auto& entry : VFT) {
-encoder.sample(entry.value, entry.counter);
+indexEncoder.sample(entry.value, entry.counter);
 }

 // Insert the uncompressed value in the tree assuming it has the
 // highest frequency, since it is in fact a group of all the values
 // not present in the VFT
-encoder.sample(uncompressedValue, ULLONG_MAX);
+indexEncoder.sample(uncompressedValue, ULLONG_MAX);

-encoder.generateCodeMaps();
+indexEncoder.generateCodeMaps();
 }

 // Generate the code map and mark the current phase as code generation
diff --git a/src/mem/cache/compressors/frequent_values.hh  
b/src/mem/cache/compressors/frequent_values.hh

index 1a7530a..2788583 100644
--- a/src/mem/cache/compressors/frequent_values.hh
+++ b/src/mem/cache/compressors/frequent_values.hh
@@ -80,7 +80,7 @@
 const bool useHuffmanEncoding;

 /** The encoder applied to the VFT indices. */
-Encoder::Huffman encoder;
+Encoder::Huffman indexEncoder;

 /** Number of bits in the saturating counters. */
 const int counterBits;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45407
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5b55ac18a2973e25e53b097cd407861f5f60d646
Gerrit-Change-Number: 45407
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename QoS namespace as qos

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45404 )



Change subject: mem: Rename QoS namespace as qos
..

mem: Rename QoS namespace as qos

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::QoS became ::qos.

Fixed some incorrect occurrences of the class name
on debug prints.

Change-Id: I163eae14e1e343384faa22af08570cfb81ae6fb6
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/qos/QoSMemCtrl.py
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qos/QoSPolicy.py
M src/mem/qos/QoSTurnaround.py
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
M src/mem/qos/turnaround_policy_ideal.hh
21 files changed, 75 insertions(+), 73 deletions(-)



diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 607d994..16895bb 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -50,7 +50,7 @@
 #include "sim/system.hh"

 MemCtrl::MemCtrl(const MemCtrlParams ) :
-QoS::MemCtrl(p),
+qos::MemCtrl(p),
 port(name() + ".port", *this), isTimingMode(false),
 retryRdReq(false), retryWrReq(false),
 nextReqEvent([this]{ processNextReqEvent(); }, name()),
@@ -1386,7 +1386,7 @@
 MemCtrl::getPort(const std::string _name, PortID idx)
 {
 if (if_name != "port") {
-return QoS::MemCtrl::getPort(if_name, idx);
+return qos::MemCtrl::getPort(if_name, idx);
 } else {
 return port;
 }
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index dd13e3c..ec2459b 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -233,7 +233,7 @@
  * please cite the paper.
  *
  */
-class MemCtrl : public QoS::MemCtrl
+class MemCtrl : public qos::MemCtrl
 {
   private:

diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index e4826d6..71cb903 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -44,7 +44,7 @@
 class QoSMemCtrl(ClockedObject):
 type = 'QoSMemCtrl'
 cxx_header = "mem/qos/mem_ctrl.hh"
-cxx_class = 'QoS::MemCtrl'
+cxx_class = 'qos::MemCtrl'
 abstract = True

 system = Param.System(Parent.any, "System that the controller belongs  
to.")

diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index fafac64..42a4ea7 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -42,7 +42,7 @@
 class QoSMemSinkCtrl(QoSMemCtrl):
 type = 'QoSMemSinkCtrl'
 cxx_header = "mem/qos/mem_sink.hh"
-cxx_class = "QoS::MemSinkCtrl"
+cxx_class = "qos::MemSinkCtrl"
 port = ResponsePort("Response ports")


diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py
index 6e9e90e..f202413 100644
--- a/src/mem/qos/QoSPolicy.py
+++ b/src/mem/qos/QoSPolicy.py
@@ -41,12 +41,12 @@
 type = 'QoSPolicy'
 abstract = True
 cxx_header = "mem/qos/policy.hh"
-cxx_class = 'QoS::Policy'
+cxx_class = 'qos::Policy'

 class QoSFixedPriorityPolicy(QoSPolicy):
 type = 'QoSFixedPriorityPolicy'
 cxx_header = "mem/qos/policy_fixed_prio.hh"
-cxx_class = 'QoS::FixedPriorityPolicy'
+cxx_class = 'qos::FixedPriorityPolicy'

 cxx_exports = [
 PyBindMethod('initRequestorName'),
@@ -90,7 +90,7 @@
 class QoSPropFairPolicy(QoSPolicy):
 type = 'QoSPropFairPolicy'
 cxx_header = "mem/qos/policy_pf.hh"
-cxx_class = 'QoS::PropFairPolicy'
+cxx_class = 'qos::PropFairPolicy'

 cxx_exports = [
 PyBindMethod('initRequestorName'),
diff --git a/src/mem/qos/QoSTurnaround.py b/src/mem/qos/QoSTurnaround.py
index 3b3991f..4ea9c26 100644
--- a/src/mem/qos/QoSTurnaround.py
+++ b/src/mem/qos/QoSTurnaround.py
@@ -39,10 +39,10 @@
 class QoSTurnaroundPolicy(SimObject):
 type = 'QoSTurnaroundPolicy'
 cxx_header = "mem/qos/turnaround_policy.hh"
-cxx_class = 'QoS::TurnaroundPolicy'
+cxx_class = 'qos::TurnaroundPolicy'
 abstract = True

 class QoSTurnaroundPolicyIdeal(QoSTurnaroundPolicy):
 type = 'QoSTurnaroundPolicyIdeal'
 cxx_header = "mem/qos/turnaround_policy_ideal.hh"
-cxx_class = 'QoS::TurnaroundPolicyIdeal'
+cxx_class = 'qos::TurnaroundPolicyIdeal'
diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index 7f7b802..5860d50 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -42,7 +42,7 @@
 #include "mem/qos/turnaround_policy.hh"
 #include "sim/core.hh"

-namespace QoS {
+namespace qos {

 MemCtrl::MemCtrl(const QoSMemCtrlParams )
   : ClockedObject(p),
@@ -89,7 +89,7 @@
 addRequestor(id);

 

[gem5-dev] Change in gem5/gem5[develop]: misc: Rename SimClock namespace as sim_clock

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45402 )



Change subject: misc: Rename SimClock namespace as sim_clock
..

misc: Rename SimClock namespace as sim_clock

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

SimClock became sim_clock.

Change-Id: I25b8cfc93f283081bc2add9fdef6fec7d7ff3846
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/base/time.cc
M src/cpu/inst_pb_trace.cc
M src/cpu/kvm/timer.hh
M src/cpu/kvm/x86_cpu.cc
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/testers/traffic_gen/trace_gen.cc
M src/cpu/trace/trace_cpu.cc
M src/dev/arm/energy_ctrl.cc
M src/dev/arm/energy_ctrl.hh
M src/dev/arm/generic_timer.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/rv_ctrl.cc
M src/dev/intel_8254_timer.cc
M src/dev/mc146818.cc
M src/dev/mc146818.hh
M src/dev/mips/malta_io.cc
M src/dev/net/etherdump.cc
M src/dev/net/etherswitch.cc
M src/dev/net/ethertap.cc
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/ns_gige.cc
M src/dev/serial/uart8250.cc
M src/gpu-compute/gpu_compute_driver.cc
M src/kern/freebsd/events.cc
M src/kern/linux/events.cc
M src/mem/cache/tags/base.cc
M src/mem/comm_monitor.cc
M src/mem/drampower.cc
M src/mem/dramsim2.cc
M src/mem/dramsim3.cc
M src/mem/mem_interface.cc
M src/mem/probes/mem_trace.cc
M src/mem/qos/mem_ctrl.cc
M src/mem/xbar.cc
M src/sim/clocked_object.hh
M src/sim/core.cc
M src/sim/core.hh
M src/sim/power/thermal_model.cc
M src/sim/pseudo_inst.cc
M src/sim/root.cc
M src/sim/syscall_emul.hh
M src/systemc/core/sc_time.cc
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/utils/vcd.cc
50 files changed, 108 insertions(+), 103 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 02ccaab..c322512 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -41,7 +41,7 @@
 void
 ScxEvsCortexA76::setClkPeriod(Tick clk_period)
 {
-clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
+clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
 }

 template 
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc  
b/src/arch/arm/fastmodel/CortexR52/evs.cc

index f4ce61e..6aed3bd 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -40,7 +40,7 @@
 void
 ScxEvsCortexR52::setClkPeriod(Tick clk_period)
 {
-clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
+clockRateControl->set_mul_div(sim_clock::Int::s, clk_period);
 }

 template 
diff --git a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc  
b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc

index e835304..f86b860 100644
--- a/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
+++ b/src/arch/arm/fastmodel/PL330_DMAC/pl330.cc
@@ -255,7 +255,7 @@
 PL330::start_of_simulation()
 {
 // Set the clock rate using the divider inside the EVS.
-clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod);
+clockRateControl->set_mul_div(sim_clock::Int::s, clockPeriod);
 }

 } // namespace FastModel
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 989d74c..6a52e07 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -500,13 +500,13 @@
 ArmSemihosting::RetErrno
 ArmSemihosting::callClock(ThreadContext *tc)
 {
-return retOK(curTick() / (SimClock::Int::s / 100));
+return retOK(curTick() / (sim_clock::Int::s / 100));
 }

 ArmSemihosting::RetErrno
 ArmSemihosting::callTime(ThreadContext *tc)
 {
-return retOK(timeBase + round(curTick() / SimClock::Float::s));
+return retOK(timeBase + round(curTick() / sim_clock::Float::s));
 }

 ArmSemihosting::RetErrno
@@ -672,7 +672,7 @@
 ArmSemihosting::RetErrno
 ArmSemihosting::callTickFreq(ThreadContext *tc)
 {
-return retOK(semiTick(SimClock::Frequency));
+return retOK(semiTick(sim_clock::Frequency));
 }


diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 6a08935..d195d91 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -414,7 +414,7 @@
 unsigned
 calcTickShift() const
 {
-int msb = findMsbSet(SimClock::Frequency);
+int msb = findMsbSet(sim_clock::Frequency);
 return msb > 31 ? msb - 31 : 0;
 }
 uint64_t
diff --git a/src/base/time.cc b/src/base/time.cc
index 92d69c0..35e1260 100644
--- a/src/base/time.cc
+++ b/src/base/time.cc
@@ -53,17 +53,17 @@
 void
 Time::setTick(Tick ticks)
 {
-uint64_t secs = ticks / SimClock::Frequency;
-ticks -= secs * SimClock::Frequency;
-uint64_t nsecs = static_cast(ticks * SimClock::Float::GHz);
+uint64_t secs = ticks / 

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename qos variables as _qos

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45403 )



Change subject: mem: Rename qos variables as _qos
..

mem: Rename qos variables as _qos

Pave the way for a qos namespace.

Change-Id: I2c225c4c6005846a0253b7df68d874498502d0f5
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/qos/mem_ctrl.cc
1 file changed, 25 insertions(+), 25 deletions(-)



diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index edd2e95..7f7b802 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -81,7 +81,7 @@
 {}

 void
-MemCtrl::logRequest(BusState dir, RequestorID id, uint8_t qos,
+MemCtrl::logRequest(BusState dir, RequestorID id, uint8_t _qos,
 Addr addr, uint64_t entries)
 {
 // If needed, initialize all counters and statistics
@@ -92,31 +92,31 @@
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d] address %d"
 " prio %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-requestors[id], id, addr, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
+requestors[id], id, addr, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos],
 entries);

 if (dir == READ) {
-readQueueSizes[qos] += entries;
+readQueueSizes[_qos] += entries;
 totalReadQueueSize += entries;
 } else if (dir == WRITE) {
-writeQueueSizes[qos] += entries;
+writeQueueSizes[_qos] += entries;
 totalWriteQueueSize += entries;
 }

-packetPriorities[id][qos] += entries;
+packetPriorities[id][_qos] += entries;
 for (auto j = 0; j < entries; ++j) {
 requestTimes[id][addr].push_back(curTick());
 }

 // Record statistics
-stats.avgPriority[id].sample(qos);
+stats.avgPriority[id].sample(_qos);

 // Compute avg priority distance

 for (uint8_t i = 0; i < packetPriorities[id].size(); ++i) {
 uint8_t distance =
-(abs(int(qos) - int(i))) * packetPriorities[id][i];
+(abs(int(_qos) - int(i))) * packetPriorities[id][i];

 if (distance > 0) {
 stats.avgPriorityDistance[id].sample(distance);
@@ -132,13 +132,13 @@
 DPRINTF(QOS,
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d] prio %d "
 "this requestor q packets %d - new queue size %d\n",
-requestors[id], id, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]);
+requestors[id], id, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos]);

 }

 void
-MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t qos,
+MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t _qos,
  Addr addr, uint64_t entries, double delay)
 {
 panic_if(!hasRequestor(id),
@@ -148,23 +148,23 @@
 "QoSMemCtrl::logResponse REQUESTOR %s [id %d] address %d prio"
 " %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-requestors[id], id, addr, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
+requestors[id], id, addr, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos],
 entries);

 if (dir == READ) {
-readQueueSizes[qos] -= entries;
+readQueueSizes[_qos] -= entries;
 totalReadQueueSize -= entries;
 } else if (dir == WRITE) {
-writeQueueSizes[qos] -= entries;
+writeQueueSizes[_qos] -= entries;
 totalWriteQueueSize -= entries;
 }

-panic_if(packetPriorities[id][qos] == 0,
+panic_if(packetPriorities[id][_qos] == 0,
  "QoSMemCtrl::logResponse requestor %s negative packets "
- "for priority %d", requestors[id], qos);
+ "for priority %d", requestors[id], _qos);

-packetPriorities[id][qos] -= entries;
+packetPriorities[id][_qos] -= entries;

 for (auto j = 0; j < entries; ++j) {
 auto it = requestTimes[id].find(addr);
@@ -188,13 +188,13 @@

 if (latency > 0) {
 // Record per-priority latency stats
-if (stats.priorityMaxLatency[qos].value() < latency) {
-stats.priorityMaxLatency[qos] = latency;
+if (stats.priorityMaxLatency[_qos].value() < latency) {
+stats.priorityMaxLatency[_qos] = latency;
 }

-if (stats.priorityMinLatency[qos].value() > latency
-|| stats.priorityMinLatency[qos].value() == 0) {
-stats.priorityMinLatency[qos] = latency;
+if (stats.priorityMinLatency[_qos].value() > latency
+ 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Rename SMBios namespace as smbios

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45397 )



Change subject: arch-x86: Rename SMBios namespace as smbios
..

arch-x86: Rename SMBios namespace as smbios

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

X86ISA::SMBios became X86ISA::smbios.

Change-Id: Ifc90a783356280141e038a6267070fcddcac
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/bios/SMBios.py
M src/arch/x86/bios/smbios.cc
M src/arch/x86/bios/smbios.hh
M src/arch/x86/fs_workload.hh
4 files changed, 25 insertions(+), 25 deletions(-)



diff --git a/src/arch/x86/bios/SMBios.py b/src/arch/x86/bios/SMBios.py
index 7493caa..24d28e3 100644
--- a/src/arch/x86/bios/SMBios.py
+++ b/src/arch/x86/bios/SMBios.py
@@ -38,7 +38,7 @@

 class X86SMBiosSMBiosStructure(SimObject):
 type = 'X86SMBiosSMBiosStructure'
-cxx_class = 'X86ISA::SMBios::SMBiosStructure'
+cxx_class = 'X86ISA::smbios::SMBiosStructure'
 cxx_header = 'arch/x86/bios/smbios.hh'
 abstract = True

@@ -91,7 +91,7 @@

 class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
 type = 'X86SMBiosBiosInformation'
-cxx_class = 'X86ISA::SMBios::BiosInformation'
+cxx_class = 'X86ISA::smbios::BiosInformation'
 cxx_header = 'arch/x86/bios/smbios.hh'

 vendor = Param.String("", "vendor name string")
@@ -114,7 +114,7 @@

 class X86SMBiosSMBiosTable(SimObject):
 type = 'X86SMBiosSMBiosTable'
-cxx_class = 'X86ISA::SMBios::SMBiosTable'
+cxx_class = 'X86ISA::smbios::SMBiosTable'
 cxx_header = 'arch/x86/bios/smbios.hh'

 major_version = Param.UInt8(2, "major version number")
diff --git a/src/arch/x86/bios/smbios.cc b/src/arch/x86/bios/smbios.cc
index e6f7934..bd5210c 100644
--- a/src/arch/x86/bios/smbios.cc
+++ b/src/arch/x86/bios/smbios.cc
@@ -47,14 +47,14 @@
 #include "params/X86SMBiosSMBiosTable.hh"
 #include "sim/byteswap.hh"

-const char X86ISA::SMBios::SMBiosTable::SMBiosHeader::anchorString[]  
= "_SM_";

-const uint8_t X86ISA::SMBios::SMBiosTable::
+const char X86ISA::smbios::SMBiosTable::SMBiosHeader::anchorString[]  
= "_SM_";

+const uint8_t X86ISA::smbios::SMBiosTable::
 SMBiosHeader::formattedArea[] = {0,0,0,0,0};
-const uint8_t X86ISA::SMBios::SMBiosTable::
+const uint8_t X86ISA::smbios::SMBiosTable::
 SMBiosHeader::entryPointLength = 0x1F;
-const uint8_t X86ISA::SMBios::SMBiosTable::
+const uint8_t X86ISA::smbios::SMBiosTable::
 SMBiosHeader::entryPointRevision = 0;
-const char X86ISA::SMBios::SMBiosTable::
+const char X86ISA::smbios::SMBiosTable::
 SMBiosHeader::IntermediateHeader::anchorString[] = "_DMI_";

 template 
@@ -70,7 +70,7 @@
 }

 uint16_t
-X86ISA::SMBios::SMBiosStructure::writeOut(PortProxy& proxy, Addr addr)
+X86ISA::smbios::SMBiosStructure::writeOut(PortProxy& proxy, Addr addr)
 {
 proxy.writeBlob(addr, , 1);

@@ -83,13 +83,13 @@
 return length + getStringLength();
 }

-X86ISA::SMBios::SMBiosStructure::SMBiosStructure(
+X86ISA::smbios::SMBiosStructure::SMBiosStructure(
 const Params , uint8_t _type) :
 SimObject(p), type(_type), handle(0), stringFields(false)
 {}

 void
-X86ISA::SMBios::SMBiosStructure::writeOutStrings(
+X86ISA::smbios::SMBiosStructure::writeOutStrings(
 PortProxy& proxy, Addr addr)
 {
 std::vector::iterator it;
@@ -112,7 +112,7 @@
 }

 int
-X86ISA::SMBios::SMBiosStructure::getStringLength()
+X86ISA::smbios::SMBiosStructure::getStringLength()
 {
 int size = 0;
 std::vector::iterator it;
@@ -125,7 +125,7 @@
 }

 int
-X86ISA::SMBios::SMBiosStructure::addString(const std::string _string)
+X86ISA::smbios::SMBiosStructure::addString(const std::string _string)
 {
 stringFields = true;
 // If a string is empty, treat it as not existing. The index for empty
@@ -137,21 +137,21 @@
 }

 std::string
-X86ISA::SMBios::SMBiosStructure::readString(int n)
+X86ISA::smbios::SMBiosStructure::readString(int n)
 {
 assert(n > 0 && n <= strings.size());
 return strings[n - 1];
 }

 void
-X86ISA::SMBios::SMBiosStructure::setString(
+X86ISA::smbios::SMBiosStructure::setString(
 int n, const std::string _string)
 {
 assert(n > 0 && n <= strings.size());
 strings[n - 1] = new_string;
 }

-X86ISA::SMBios::BiosInformation::BiosInformation(const Params ) :
+X86ISA::smbios::BiosInformation::BiosInformation(const Params ) :
 SMBiosStructure(p, Type),
 startingAddrSegment(p.starting_addr_segment),
 romSize(p.rom_size),
@@ -169,7 +169,7 @@
 }

 uint16_t
-X86ISA::SMBios::BiosInformation::writeOut(PortProxy& proxy, Addr addr)
+X86ISA::smbios::BiosInformation::writeOut(PortProxy& proxy, Addr addr)
 {
 uint8_t size = SMBiosStructure::writeOut(proxy, addr);

@@ -199,7 +199,7 @@
 return size;
 }

-X86ISA::SMBios::SMBiosTable::SMBiosTable(const Params ) :

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Rename X86Macroop namespace as x86_macroop

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45400 )



Change subject: arch-x86: Rename X86Macroop namespace as x86_macroop
..

arch-x86: Rename X86Macroop namespace as x86_macroop

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

X86Macroop became x86_macroop.

Ideally, this should probably be moved to inside the
X86ISA namespace, and renamed accordingly, but a macroop
namespace would probably generate a lot of conflicts.

Change-Id: I06bc0f33a4c1d95492df9397d7d70e5316b1b96b
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/isa/macroop.isa
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index ccd065a..2d7be6a 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -76,8 +76,8 @@

 // Basic instruction class declaration template.
 def template MacroDeclare {{
-namespace X86Macroop
-{
+GEM5_DEPRECATED_NAMESPACE(X86Macroop, x86_macroop);
+namespace x86_macroop {
 /**
  * Static instruction class for "%(mnemonic)s".
  */
@@ -97,7 +97,7 @@

 def template MacroDisassembly {{
 std::string
-X86Macroop::%(class_name)s::generateDisassembly(
+x86_macroop::%(class_name)s::generateDisassembly(
 Addr pc, const Loader::SymbolTable *symtab) const
 {
 std::stringstream out;
@@ -113,7 +113,7 @@

 // Basic instruction class constructor template.
 def template MacroConstructor {{
-X86Macroop::%(class_name)s::%(class_name)s(
+x86_macroop::%(class_name)s::%(class_name)s(
 ExtMachInst machInst, EmulEnv _env)
 : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s,  
_env)

 {
@@ -190,7 +190,7 @@
 self.control_indirect = False

 def getAllocator(self, env):
-return "new X86Macroop::%s(machInst, %s)" % \
+return "new x86_macroop::%s(machInst, %s)" % \
 (self.name, env.getAllocator())
 def getMnemonic(self):
 mnemonic = self.name.lower()

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45400
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I06bc0f33a4c1d95492df9397d7d70e5316b1b96b
Gerrit-Change-Number: 45400
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Rename IntelMP namespace as intelmp

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45398 )



Change subject: arch-x86: Rename IntelMP namespace as intelmp
..

arch-x86: Rename IntelMP namespace as intelmp

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

X86ISA::IntelMP became X86ISA::intelmp.

Change-Id: I800ddba673aa51574c1f4a63ad57721c9d0a0c10
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/bios/IntelMP.py
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/intelmp.hh
M src/arch/x86/fs_workload.hh
4 files changed, 45 insertions(+), 44 deletions(-)



diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index c1de985..0d9a641 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -38,7 +38,7 @@

 class X86IntelMPFloatingPointer(SimObject):
 type = 'X86IntelMPFloatingPointer'
-cxx_class = 'X86ISA::IntelMP::FloatingPointer'
+cxx_class = 'X86ISA::intelmp::FloatingPointer'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 # The minor revision of the spec to support. The major version is  
assumed

@@ -51,7 +51,7 @@

 class X86IntelMPConfigTable(SimObject):
 type = 'X86IntelMPConfigTable'
-cxx_class = 'X86ISA::IntelMP::ConfigTable'
+cxx_class = 'X86ISA::intelmp::ConfigTable'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
@@ -79,19 +79,19 @@

 class X86IntelMPBaseConfigEntry(SimObject):
 type = 'X86IntelMPBaseConfigEntry'
-cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
+cxx_class = 'X86ISA::intelmp::BaseConfigEntry'
 cxx_header = 'arch/x86/bios/intelmp.hh'
 abstract = True

 class X86IntelMPExtConfigEntry(SimObject):
 type = 'X86IntelMPExtConfigEntry'
-cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
+cxx_class = 'X86ISA::intelmp::ExtConfigEntry'
 cxx_header = 'arch/x86/bios/intelmp.hh'
 abstract = True

 class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
 type = 'X86IntelMPProcessor'
-cxx_class = 'X86ISA::IntelMP::Processor'
+cxx_class = 'X86ISA::intelmp::Processor'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 local_apic_id = Param.UInt8(0, 'local APIC id')
@@ -108,7 +108,7 @@

 class X86IntelMPBus(X86IntelMPBaseConfigEntry):
 type = 'X86IntelMPBus'
-cxx_class = 'X86ISA::IntelMP::Bus'
+cxx_class = 'X86ISA::intelmp::Bus'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 bus_id = Param.UInt8(0, 'bus id assigned by the bios')
@@ -121,7 +121,7 @@

 class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
 type = 'X86IntelMPIOAPIC'
-cxx_class = 'X86ISA::IntelMP::IOAPIC'
+cxx_class = 'X86ISA::intelmp::IOAPIC'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 id = Param.UInt8(0, 'id of this APIC')
@@ -152,7 +152,7 @@

 class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
 type = 'X86IntelMPIOIntAssignment'
-cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
+cxx_class = 'X86ISA::intelmp::IOIntAssignment'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of  
interrupt')

@@ -172,7 +172,7 @@

 class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
 type = 'X86IntelMPLocalIntAssignment'
-cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
+cxx_class = 'X86ISA::intelmp::LocalIntAssignment'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of  
interrupt')

@@ -198,7 +198,7 @@

 class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
 type = 'X86IntelMPAddrSpaceMapping'
-cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
+cxx_class = 'X86ISA::intelmp::AddrSpaceMapping'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
@@ -209,7 +209,7 @@

 class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
 type = 'X86IntelMPBusHierarchy'
-cxx_class = 'X86ISA::IntelMP::BusHierarchy'
+cxx_class = 'X86ISA::intelmp::BusHierarchy'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 bus_id = Param.UInt8(0, 'id of the bus being described')
@@ -224,7 +224,7 @@

 class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
 type = 'X86IntelMPCompatAddrSpaceMod'
-cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
+cxx_class = 'X86ISA::intelmp::CompatAddrSpaceMod'
 cxx_header = 'arch/x86/bios/intelmp.hh'

 bus_id = Param.UInt8(0, 'id of the bus being described')
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index 8e6a0b1..3d8bc68 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -62,7 +62,7 @@
 #include "params/X86IntelMPBusHierarchy.hh"
 #include "params/X86IntelMPCompatAddrSpaceMod.hh"

-const char 

[gem5-dev] Change in gem5/gem5[develop]: base: Rename BloomFilter namespace as bloom_filter

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45401 )



Change subject: base: Rename BloomFilter namespace as bloom_filter
..

base: Rename BloomFilter namespace as bloom_filter

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::BloomFilter became ::bloom_filter.

Change-Id: I721ad0f55c77d6c3a2dc2b53fe567b3202783b8b
Signed-off-by: Daniel R. Carvalho 
---
M src/base/filters/BloomFilters.py
M src/base/filters/base.hh
M src/base/filters/block_bloom_filter.cc
M src/base/filters/block_bloom_filter.hh
M src/base/filters/bulk_bloom_filter.cc
M src/base/filters/bulk_bloom_filter.hh
M src/base/filters/h3_bloom_filter.cc
M src/base/filters/h3_bloom_filter.hh
M src/base/filters/multi_bit_sel_bloom_filter.cc
M src/base/filters/multi_bit_sel_bloom_filter.hh
M src/base/filters/multi_bloom_filter.cc
M src/base/filters/multi_bloom_filter.hh
M src/base/filters/perfect_bloom_filter.cc
M src/base/filters/perfect_bloom_filter.hh
14 files changed, 35 insertions(+), 33 deletions(-)



diff --git a/src/base/filters/BloomFilters.py  
b/src/base/filters/BloomFilters.py

index 5ac3a42..4808b19 100644
--- a/src/base/filters/BloomFilters.py
+++ b/src/base/filters/BloomFilters.py
@@ -32,7 +32,7 @@
 type = 'BloomFilterBase'
 abstract = True
 cxx_header = "base/filters/base.hh"
-cxx_class = 'BloomFilter::Base'
+cxx_class = 'bloom_filter::Base'

 size = Param.Int(4096, "Number of entries in the filter")

@@ -45,7 +45,7 @@

 class BloomFilterBlock(BloomFilterBase):
 type = 'BloomFilterBlock'
-cxx_class = 'BloomFilter::Block'
+cxx_class = 'bloom_filter::Block'
 cxx_header = "base/filters/block_bloom_filter.hh"

 masks_lsbs = VectorParam.Unsigned([Self.offset_bits,
@@ -55,7 +55,7 @@

 class BloomFilterMultiBitSel(BloomFilterBase):
 type = 'BloomFilterMultiBitSel'
-cxx_class = 'BloomFilter::MultiBitSel'
+cxx_class = 'bloom_filter::MultiBitSel'
 cxx_header = "base/filters/multi_bit_sel_bloom_filter.hh"

 num_hashes = Param.Int(4, "Number of hashes")
@@ -65,17 +65,17 @@

 class BloomFilterBulk(BloomFilterMultiBitSel):
 type = 'BloomFilterBulk'
-cxx_class = 'BloomFilter::Bulk'
+cxx_class = 'bloom_filter::Bulk'
 cxx_header = "base/filters/bulk_bloom_filter.hh"

 class BloomFilterH3(BloomFilterMultiBitSel):
 type = 'BloomFilterH3'
-cxx_class = 'BloomFilter::H3'
+cxx_class = 'bloom_filter::H3'
 cxx_header = "base/filters/h3_bloom_filter.hh"

 class BloomFilterMulti(BloomFilterBase):
 type = 'BloomFilterMulti'
-cxx_class = 'BloomFilter::Multi'
+cxx_class = 'bloom_filter::Multi'
 cxx_header = "base/filters/multi_bloom_filter.hh"

 # The base filter should not be used, since this filter is the  
combination

@@ -93,7 +93,7 @@

 class BloomFilterPerfect(BloomFilterBase):
 type = 'BloomFilterPerfect'
-cxx_class = 'BloomFilter::Perfect'
+cxx_class = 'bloom_filter::Perfect'
 cxx_header = "base/filters/perfect_bloom_filter.hh"

 # The base filter is not needed. Use a dummy value.
diff --git a/src/base/filters/base.hh b/src/base/filters/base.hh
index 583e035..e3cbb0a 100644
--- a/src/base/filters/base.hh
+++ b/src/base/filters/base.hh
@@ -32,13 +32,15 @@

 #include 

+#include "base/compiler.hh"
 #include "base/intmath.hh"
 #include "base/sat_counter.hh"
 #include "base/types.hh"
 #include "params/BloomFilterBase.hh"
 #include "sim/sim_object.hh"

-namespace BloomFilter {
+GEM5_DEPRECATED_NAMESPACE(BloomFilter, bloom_filter);
+namespace bloom_filter {

 class Base : public SimObject
 {
@@ -146,6 +148,6 @@
 }
 };

-} // namespace BloomFilter
+} // namespace bloom_filter

 #endif // __BASE_FILTERS_BASE_HH__
diff --git a/src/base/filters/block_bloom_filter.cc  
b/src/base/filters/block_bloom_filter.cc

index 100f198..3c29acf 100644
--- a/src/base/filters/block_bloom_filter.cc
+++ b/src/base/filters/block_bloom_filter.cc
@@ -33,7 +33,7 @@
 #include "base/logging.hh"
 #include "params/BloomFilterBlock.hh"

-namespace BloomFilter {
+namespace bloom_filter {

 Block::Block(const BloomFilterBlockParams )
 : Base(p), masksLSBs(p.masks_lsbs),
@@ -89,4 +89,4 @@
 return hashed_addr;
 }

-} // namespace BloomFilter
+} // namespace bloom_filter
diff --git a/src/base/filters/block_bloom_filter.hh  
b/src/base/filters/block_bloom_filter.hh

index 7292914..17c9269 100644
--- a/src/base/filters/block_bloom_filter.hh
+++ b/src/base/filters/block_bloom_filter.hh
@@ -36,7 +36,7 @@

 struct BloomFilterBlockParams;

-namespace BloomFilter {
+namespace bloom_filter {

 /**
  * Simple deletable (with false negatives) bloom filter that extracts
@@ -68,6 +68,6 @@
 std::vector masksSizes;
 };

-} // namespace BloomFilter
+} // namespace bloom_filter

 #endif // __BASE_FILTERS_BLOCK_BLOOM_FILTER_HH__
diff --git 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Rename ConditionTests namespace as condition_tests

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45399 )



Change subject: arch-x86: Rename ConditionTests namespace as condition_tests
..

arch-x86: Rename ConditionTests namespace as condition_tests

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

X86ISA::ConditionTests became X86ISA::condition_tests.

Change-Id: I95c99f9f65995653c48c5562872ebfc52ea7438c
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/insts/microop.cc
M src/arch/x86/insts/microop.hh
M src/arch/x86/isa/microasm.isa
M src/arch/x86/isa/microops/seqop.isa
4 files changed, 42 insertions(+), 41 deletions(-)



diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index 0f81d6a..b9be362 100644
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -48,71 +48,71 @@
 CCFlagBits ccflags = flags;
 switch(condition)
 {
-  case ConditionTests::True:
+  case condition_tests::True:
 return true;
-  case ConditionTests::ECF:
+  case condition_tests::ECF:
 return ccflags.ecf;
-  case ConditionTests::EZF:
+  case condition_tests::EZF:
 return ccflags.ezf;
-  case ConditionTests::SZnZF:
+  case condition_tests::SZnZF:
 return !(!ccflags.ezf && ccflags.zf);
-  case ConditionTests::MSTRZ:
+  case condition_tests::MSTRZ:
 panic("This condition is not implemented!");
-  case ConditionTests::STRZ:
+  case condition_tests::STRZ:
 panic("This condition is not implemented!");
-  case ConditionTests::MSTRC:
+  case condition_tests::MSTRC:
 panic("This condition is not implemented!");
-  case ConditionTests::STRZnEZF:
+  case condition_tests::STRZnEZF:
 return !ccflags.ezf && ccflags.zf;
 //And no interrupts or debug traps are waiting
-  case ConditionTests::OF:
+  case condition_tests::OF:
 return ccflags.of;
-  case ConditionTests::CF:
+  case condition_tests::CF:
 return ccflags.cf;
-  case ConditionTests::ZF:
+  case condition_tests::ZF:
 return ccflags.zf;
-  case ConditionTests::CvZF:
+  case condition_tests::CvZF:
 return ccflags.cf | ccflags.zf;
-  case ConditionTests::SF:
+  case condition_tests::SF:
 return ccflags.sf;
-  case ConditionTests::PF:
+  case condition_tests::PF:
 return ccflags.pf;
-  case ConditionTests::SxOF:
+  case condition_tests::SxOF:
 return ccflags.sf ^ ccflags.of;
-  case ConditionTests::SxOvZF:
+  case condition_tests::SxOvZF:
 return (ccflags.sf ^ ccflags.of) | ccflags.zf;
-  case ConditionTests::False:
+  case condition_tests::False:
 return false;
-  case ConditionTests::NotECF:
+  case condition_tests::NotECF:
 return !ccflags.ecf;
-  case ConditionTests::NotEZF:
+  case condition_tests::NotEZF:
 return !ccflags.ezf;
-  case ConditionTests::NotSZnZF:
+  case condition_tests::NotSZnZF:
 return !ccflags.ezf && ccflags.zf;
-  case ConditionTests::NotMSTRZ:
+  case condition_tests::NotMSTRZ:
 panic("This condition is not implemented!");
-  case ConditionTests::NotSTRZ:
+  case condition_tests::NotSTRZ:
 panic("This condition is not implemented!");
-  case ConditionTests::NotMSTRC:
+  case condition_tests::NotMSTRC:
 panic("This condition is not implemented!");
-  case ConditionTests::STRnZnEZF:
+  case condition_tests::STRnZnEZF:
 return !ccflags.ezf && !ccflags.zf;
 //And no interrupts or debug traps are waiting
-  case ConditionTests::NotOF:
+  case condition_tests::NotOF:
 return !ccflags.of;
-  case ConditionTests::NotCF:
+  case condition_tests::NotCF:
 return !ccflags.cf;
-  case ConditionTests::NotZF:
+  case condition_tests::NotZF:
 return !ccflags.zf;
-  case ConditionTests::NotCvZF:
+  case condition_tests::NotCvZF:
 return !(ccflags.cf | ccflags.zf);
-  case ConditionTests::NotSF:
+  case condition_tests::NotSF:
 return !ccflags.sf;
-  case ConditionTests::NotPF:
+  case condition_tests::NotPF:
 return !ccflags.pf;
-  case ConditionTests::NotSxOF:
+  case condition_tests::NotSxOF:
 return !(ccflags.sf ^ ccflags.of);
-  case ConditionTests::NotSxOvZF:
+  case condition_tests::NotSxOvZF:
 return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
 }
 panic("Unknown condition: %d\n", condition);
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index 13c4bee..3d3230d 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -39,12 +39,13 @@
 #define __ARCH_X86_INSTS_MICROOP_HH__

 #include 

[gem5-dev] Change in gem5/gem5[develop]: dev: Put PS2 classes in the ps2 namespace

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45395 )



Change subject: dev: Put PS2 classes in the ps2 namespace
..

dev: Put PS2 classes in the ps2 namespace

These classes belong in the ps2 namespace. Use this
opportunity to rename PS2Device as ps2::Device, and
PS2TouchKit as ps2::TouchKit.

Unfortunately, since the ps2::Mouse and ps2::Keyboard
namespaces are being deprecated, these names cannot be
used as of now to rename PS2Mouse and PS2Keyboard.

Change-Id: I9a57b87053a6a0acb380a919e09ab427fdb8eca4
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/arm/kmi.hh
M src/dev/ps2/PS2.py
M src/dev/ps2/device.cc
M src/dev/ps2/device.hh
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/touchkit.hh
M src/dev/x86/i8042.hh
11 files changed, 113 insertions(+), 63 deletions(-)



diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh
index 03e9dbd..5a9894b 100644
--- a/src/dev/arm/kmi.hh
+++ b/src/dev/arm/kmi.hh
@@ -52,7 +52,9 @@
 #include "dev/arm/amba_device.hh"
 #include "params/Pl050.hh"

-class PS2Device;
+namespace ps2 {
+class Device;
+} // namespace ps2

 class Pl050 : public AmbaIntDevice
 {
@@ -123,7 +125,7 @@
 InterruptReg getInterrupt() const;

 /** PS2 device connected to this KMI interface */
-PS2Device *ps2Device;
+ps2::Device *ps2Device;

   public:
 Pl050(const Pl050Params );
diff --git a/src/dev/ps2/PS2.py b/src/dev/ps2/PS2.py
index b250859..3c31b6b 100644
--- a/src/dev/ps2/PS2.py
+++ b/src/dev/ps2/PS2.py
@@ -40,20 +40,24 @@
 class PS2Device(SimObject):
 type = 'PS2Device'
 cxx_header = "dev/ps2/device.hh"
+cxx_class = "ps2::Device"
 abstract = True

 class PS2Keyboard(PS2Device):
 type = 'PS2Keyboard'
 cxx_header = "dev/ps2/keyboard.hh"
+cxx_class = "ps2::PS2Keyboard"

 vnc = Param.VncInput(Parent.any, "VNC server providing keyboard input")

 class PS2Mouse(PS2Device):
 type = 'PS2Mouse'
 cxx_header = "dev/ps2/mouse.hh"
+cxx_class = "ps2::PS2Mouse"

 class PS2TouchKit(PS2Device):
 type = 'PS2TouchKit'
 cxx_header = "dev/ps2/touchkit.hh"
+cxx_class = "ps2::TouchKit"

 vnc = Param.VncInput(Parent.any, "VNC server providing mouse input")
diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index b9dfafb..34d5387 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -40,6 +40,8 @@

 #include "dev/ps2/device.hh"

+#include 
+
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "debug/PS2.hh"
@@ -47,14 +49,16 @@
 #include "params/PS2Device.hh"
 #include "sim/serialize.hh"

-PS2Device::PS2Device(const PS2DeviceParams )
+namespace ps2 {
+
+Device::Device(const PS2DeviceParams )
 : SimObject(p)
 {
 inBuffer.reserve(16);
 }

 void
-PS2Device::serialize(CheckpointOut ) const
+Device::serialize(CheckpointOut ) const
 {
 std::vector buffer(outBuffer.size());
 std::copy(outBuffer.begin(), outBuffer.end(), buffer.begin());
@@ -64,7 +68,7 @@
 }

 void
-PS2Device::unserialize(CheckpointIn )
+Device::unserialize(CheckpointIn )
 {
 std::vector buffer;
 arrayParamIn(cp, "outBuffer", buffer);
@@ -75,7 +79,7 @@
 }

 void
-PS2Device::hostRegDataAvailable(const std::function )
+Device::hostRegDataAvailable(const std::function )
 {
 fatal_if(dataAvailableCallback,
  "A data pending callback has already been associated with  
this "

@@ -85,7 +89,7 @@
 }

 uint8_t
-PS2Device::hostRead()
+Device::hostRead()
 {
 uint8_t data = outBuffer.front();
 outBuffer.pop_front();
@@ -93,7 +97,7 @@
 }

 void
-PS2Device::hostWrite(uint8_t c)
+Device::hostWrite(uint8_t c)
 {
 DPRINTF(PS2, "PS2: Host -> device: %#x\n", c);
 inBuffer.push_back(c);
@@ -102,7 +106,7 @@
 }

 void
-PS2Device::send(const uint8_t *data, size_t size)
+Device::send(const uint8_t *data, size_t size)
 {
 assert(data || size == 0);
 while (size) {
@@ -117,7 +121,9 @@
 }

 void
-PS2Device::sendAck()
+Device::sendAck()
 {
-send(ps2::Ack);
+send(Ack);
 }
+
+} // namespace ps2
diff --git a/src/dev/ps2/device.hh b/src/dev/ps2/device.hh
index 9671876..5eecb55 100644
--- a/src/dev/ps2/device.hh
+++ b/src/dev/ps2/device.hh
@@ -41,17 +41,24 @@
 #ifndef __DEV_PS2_DEVICE_HH__
 #define __DEV_PS2_DEVICE_HH__

+#include 
 #include 
+#include 
 #include 

+#include "base/compiler.hh"
 #include "sim/sim_object.hh"

 struct PS2DeviceParams;

-class PS2Device : public SimObject
+namespace ps2 {
+
+GEM5_DEPRECATED_CLASS(PS2Device, Device);
+
+class Device : public SimObject
 {
   public:
-PS2Device(const PS2DeviceParams );
+Device(const PS2DeviceParams );

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;
@@ -142,4 +149,6 @@
 std::function dataAvailableCallback;
 };

+} // namespace ps2
+
 #endif // __DEV_PS2_HOUSE_HH__
diff --git 

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Rename RomLabels namespace as rom_labels

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45396 )



Change subject: arch-x86: Rename RomLabels namespace as rom_labels
..

arch-x86: Rename RomLabels namespace as rom_labels

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

RomLabels became rom_labels.

Change-Id: I972409ab33c595baaf845bf11f2f450ab5938d54
Signed-off-by: Daniel R. Carvalho 
---
M src/arch/x86/faults.cc
M src/arch/x86/isa/microasm.isa
M src/arch/x86/isa/microops/base.isa
M src/arch/x86/isa/rom.isa
4 files changed, 9 insertions(+), 7 deletions(-)



diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 97d7b88..749e743 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -64,7 +64,7 @@
 PCState pcState = tc->pcState();
 Addr pc = pcState.pc();
 DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
-using namespace X86ISAInst::RomLabels;
+using namespace X86ISAInst::rom_labels;
 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
 MicroPC entry;
 if (m5reg.mode == LongMode) {
@@ -292,7 +292,7 @@

 // Update the handy M5 Reg.
 tc->setMiscReg(MISCREG_M5_REG, 0);
-MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
+MicroPC entry = X86ISAInst::rom_labels::extern_label_initIntHalt;
 pc.upc(romMicroPC(entry));
 pc.nupc(romMicroPC(entry) + 1);
 tc->pcState(pc);
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index bac4902..ff110f1 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -216,12 +216,12 @@
 assembler.symbols["label"] = labeler

 def rom_labeler(labelStr):
-return "romMicroPC(RomLabels::extern_label_%s)" % labelStr
+return "romMicroPC(rom_labels::extern_label_%s)" % labelStr

 assembler.symbols["rom_label"] = rom_labeler

 def rom_local_labeler(labelStr):
-return "romMicroPC(RomLabels::label_%s)" % labelStr
+return "romMicroPC(rom_labels::label_%s)" % labelStr

 assembler.symbols["rom_local_label"] = rom_local_labeler

diff --git a/src/arch/x86/isa/microops/base.isa  
b/src/arch/x86/isa/microops/base.isa

index b9e499c..2dea9a3 100644
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -215,7 +215,7 @@
 macroop ? macroop->getExtMachInst() : dummyExtMachInst;
 GEM5_VAR_USED const EmulEnv  =
 macroop ? macroop->getEmulEnv() : dummyEmulEnv;
-using namespace RomLabels;
+using namespace rom_labels;
 return %s;
 }
 '''
diff --git a/src/arch/x86/isa/rom.isa b/src/arch/x86/isa/rom.isa
index 1f41ad1..3f7ad1c 100644
--- a/src/arch/x86/isa/rom.isa
+++ b/src/arch/x86/isa/rom.isa
@@ -31,7 +31,7 @@

 X86ISA::MicrocodeRom::MicrocodeRom()
 {
-using namespace RomLabels;
+using namespace rom_labels;
 genFuncs = new GenFunc[numMicroops];
 %(alloc_generators)s;
 }
@@ -52,7 +52,9 @@


 def getDeclaration(self):
-declareLabels = "namespace RomLabels {\n"
+declareLabels = \
+"GEM5_DEPRECATED_NAMESPACE(RomLabels, rom_labels);\n" \
+"namespace rom_labels {\n"
 for (label, microop) in self.labels.items():
 declareLabels += "const static uint64_t label_%s = %d;\n" \
   % (label, microop.micropc)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45396
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I972409ab33c595baaf845bf11f2f450ab5938d54
Gerrit-Change-Number: 45396
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base,dev: Remove ps2::Keyboard namespace

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45394 )



Change subject: base,dev: Remove ps2::Keyboard namespace
..

base,dev: Remove ps2::Keyboard namespace

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

This namespace didn't bring any benefit on top of
the existing PS2Keyboard class, so it was removed.

Change-Id: I52b66ddd81003735548fc87d30b543853e4c2d32
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/ps2/keyboard.cc
M src/dev/ps2/keyboard.hh
M src/dev/ps2/types.cc
M src/dev/ps2/types.hh
4 files changed, 35 insertions(+), 36 deletions(-)



diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index 86771f6..29ff9ee 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -46,6 +46,8 @@
 #include "dev/ps2/types.hh"
 #include "params/PS2Keyboard.hh"

+const std::vector PS2Keyboard::ID{0xAB, 0x83};
+
 PS2Keyboard::PS2Keyboard(const PS2KeyboardParams )
 : PS2Device(p),
   shiftDown(false),
@@ -78,7 +80,7 @@
   case ps2::ReadID:
 DPRINTF(PS2, "Got keyboard read ID command.\n");
 sendAck();
-send(ps2::Keyboard::ID);
+send(ID);
 return true;
   case ps2::Enable:
 DPRINTF(PS2, "Enabling the keyboard.\n");
@@ -104,7 +106,7 @@
   case ps2::Resend:
 panic("Keyboard resend unimplemented.\n");

-  case ps2::Keyboard::LEDWrite:
+  case LEDWrite:
 if (data.size() == 1) {
 DPRINTF(PS2, "Got LED write command.\n");
 sendAck();
@@ -118,11 +120,11 @@
 sendAck();
 return true;
 }
-  case ps2::Keyboard::DiagnosticEcho:
+  case DiagnosticEcho:
 panic("Keyboard diagnostic echo unimplemented.\n");
-  case ps2::Keyboard::AlternateScanCodes:
+  case AlternateScanCodes:
 panic("Accessing alternate scan codes unimplemented.\n");
-  case ps2::Keyboard::TypematicInfo:
+  case TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");
 sendAck();
@@ -132,20 +134,20 @@
 sendAck();
 return true;
 }
-  case ps2::Keyboard::AllKeysToTypematic:
+  case AllKeysToTypematic:
 panic("Setting all keys to typemantic unimplemented.\n");
-  case ps2::Keyboard::AllKeysToMakeRelease:
+  case AllKeysToMakeRelease:
 panic("Setting all keys to make/release unimplemented.\n");
-  case ps2::Keyboard::AllKeysToMake:
+  case AllKeysToMake:
 panic("Setting all keys to make unimplemented.\n");
-  case ps2::Keyboard::AllKeysToTypematicMakeRelease:
+  case AllKeysToTypematicMakeRelease:
 panic("Setting all keys to "
 "typematic/make/release unimplemented.\n");
-  case ps2::Keyboard::KeyToTypematic:
+  case KeyToTypematic:
 panic("Setting a key to typematic unimplemented.\n");
-  case ps2::Keyboard::KeyToMakeRelease:
+  case KeyToMakeRelease:
 panic("Setting a key to make/release unimplemented.\n");
-  case ps2::Keyboard::KeyToMakeOnly:
+  case KeyToMakeOnly:
 panic("Setting key to make only unimplemented.\n");
   default:
 panic("Unknown keyboard command %#02x.\n", data[0]);
diff --git a/src/dev/ps2/keyboard.hh b/src/dev/ps2/keyboard.hh
index 68514cc..b21 100644
--- a/src/dev/ps2/keyboard.hh
+++ b/src/dev/ps2/keyboard.hh
@@ -41,6 +41,9 @@
 #ifndef __DEV_PS2_KEYBOARD_HH__
 #define __DEV_PS2_KEYBOARD_HH__

+#include 
+#include 
+
 #include "base/vnc/vncinput.hh"
 #include "dev/ps2/device.hh"

@@ -56,6 +59,23 @@
 bool enabled;

   public:
+enum
+{
+LEDWrite = 0xED,
+DiagnosticEcho = 0xEE,
+AlternateScanCodes = 0xF0,
+TypematicInfo = 0xF3,
+AllKeysToTypematic = 0xF7,
+AllKeysToMakeRelease = 0xF8,
+AllKeysToMake = 0xF9,
+AllKeysToTypematicMakeRelease = 0xFA,
+KeyToTypematic = 0xFB,
+KeyToMakeRelease = 0xFC,
+KeyToMakeOnly = 0xFD,
+};
+
+static const std::vector ID;
+
 PS2Keyboard(const PS2KeyboardParams );

 void serialize(CheckpointOut ) const override;
diff --git a/src/dev/ps2/types.cc b/src/dev/ps2/types.cc
index bb2233a..d66189c 100644
--- a/src/dev/ps2/types.cc
+++ b/src/dev/ps2/types.cc
@@ -42,8 +42,7 @@
 #include "base/logging.hh"
 #include "x11keysym/keysym.h"

-const std::vector ps2::Keyboard::ID{0xAB, 0x83};
-
+GEM5_DEPRECATED_NAMESPACE(Ps2, ps2);
 namespace ps2 {

 /** Table to convert simple key symbols (0x00XX) into ps2 bytes. Lower byte
diff --git a/src/dev/ps2/types.hh b/src/dev/ps2/types.hh
index 8c5d3a0..a01c7f3 100644
--- a/src/dev/ps2/types.hh
+++ b/src/dev/ps2/types.hh
@@ -41,7 +41,6 @@
 #include 

 #include 
-#include 

 #include "base/bitunion.hh"
 #include "base/compiler.hh"
@@ -66,27 +65,6 @@

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename sinic::Regs namespace as sinic::registers

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45388 )



Change subject: dev: Rename sinic::Regs namespace as sinic::registers
..

dev: Rename sinic::Regs namespace as sinic::registers

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sinic::Regs became sinic::registers.

"registers" was chosen over "regs" to reduce conflict
resolution (there is already a variable called regs).

Change-Id: I329d40884906bb55d1b1d749610b9f0dee243418
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/net/sinicreg.hh
3 files changed, 83 insertions(+), 76 deletions(-)



diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index 5e27909..cc088ab 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -143,7 +143,7 @@
 void
 Device::prepareRead(ContextID cpu, int index)
 {
-using namespace Regs;
+using namespace registers;
 prepareIO(cpu, index);

 VirtualReg  = virtualRegs[index];
@@ -200,14 +200,14 @@
 daddr -= BARs[0]->addr();

 ContextID cpu = pkt->req->contextId();
-Addr index = daddr >> Regs::VirtualShift;
-Addr raddr = daddr & Regs::VirtualMask;
+Addr index = daddr >> registers::VirtualShift;
+Addr raddr = daddr & registers::VirtualMask;

 if (!regValid(raddr))
 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
   cpu, index, daddr, pkt->getAddr(), pkt->getSize());

-const Regs::Info  = regInfo(raddr);
+const registers::Info  = regInfo(raddr);
 if (!info.read)
 panic("read %s (write only): "
   "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
@@ -238,7 +238,7 @@

 // reading the interrupt status register has the side effect of
 // clearing it
-if (raddr == Regs::IntrStatus)
+if (raddr == registers::IntrStatus)
 devIntrClear();

 return pioDelay;
@@ -253,7 +253,7 @@
 if (!regValid(daddr))
 panic("invalid address: da=%#x", daddr);

-const Regs::Info  = regInfo(daddr);
+const registers::Info  = regInfo(daddr);
 if (!info.read)
 panic("reading %s (write only): cpu=%d da=%#x", info.name, cpu,  
daddr);


@@ -287,14 +287,14 @@
 daddr -= BARs[0]->addr();

 ContextID cpu = pkt->req->contextId();
-Addr index = daddr >> Regs::VirtualShift;
-Addr raddr = daddr & Regs::VirtualMask;
+Addr index = daddr >> registers::VirtualShift;
+Addr raddr = daddr & registers::VirtualMask;

 if (!regValid(raddr))
 panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
 cpu, daddr, pkt->getAddr(), pkt->getSize());

-const Regs::Info  = regInfo(raddr);
+const registers::Info  = regInfo(raddr);
 if (!info.write)
 panic("write %s (read only): "
   "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
@@ -316,34 +316,34 @@
 prepareWrite(cpu, index);

 switch (raddr) {
-  case Regs::Config:
+  case registers::Config:
 changeConfig(pkt->getLE());
 break;

-  case Regs::Command:
+  case registers::Command:
 command(pkt->getLE());
 break;

-  case Regs::IntrStatus:
+  case registers::IntrStatus:
 devIntrClear(regs.IntrStatus &
 pkt->getLE());
 break;

-  case Regs::IntrMask:
+  case registers::IntrMask:
 devIntrChangeMask(pkt->getLE());
 break;

-  case Regs::RxData:
-if (Regs::get_RxDone_Busy(vnic.RxDone))
+  case registers::RxData:
+if (registers::get_RxDone_Busy(vnic.RxDone))
 panic("receive machine busy with another request! rxState=%s",
   RxStateStrings[rxState]);

 vnic.rxUnique = rxUnique++;
-vnic.RxDone = Regs::RxDone_Busy;
+vnic.RxDone = registers::RxDone_Busy;
 vnic.RxData = pkt->getLE();
 rxBusyCount++;

-if (Regs::get_RxData_Vaddr(pkt->getLE())) {
+if (registers::get_RxData_Vaddr(pkt->getLE())) {
 panic("vtophys not implemented in newmem");
 } else {
 DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n",
@@ -364,15 +364,15 @@
 }
 break;

-  case Regs::TxData:
-if (Regs::get_TxDone_Busy(vnic.TxDone))
+  case registers::TxData:
+if (registers::get_TxDone_Busy(vnic.TxDone))
 panic("transmit machine busy with another request! txState=%s",
   TxStateStrings[txState]);

 vnic.txUnique = txUnique++;
-vnic.TxDone = Regs::TxDone_Busy;
+vnic.TxDone = registers::TxDone_Busy;

-if (Regs::get_TxData_Vaddr(pkt->getLE())) {
+if (registers::get_TxData_Vaddr(pkt->getLE())) {
 panic("vtophys won't work here in newmem.\n");
 } else {
 DPRINTF(EthernetPIO, "write TxData vnic %d (txunique 

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename TxdOp namespace as txd_op

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45386 )



Change subject: dev: Rename TxdOp namespace as txd_op
..

dev: Rename TxdOp namespace as txd_op

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

iGbReg::TxdOp became iGbReg::txd_op.

Change-Id: I737205a3d29ffc0d96da72ba9fc6829939970957
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe_defs.hh
2 files changed, 48 insertions(+), 45 deletions(-)



diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 30e38f0..73bea7a 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -1519,7 +1519,7 @@
 DPRINTF(EthernetDesc, "Checking and  processing context  
descriptors\n");


 while (!useTso && unusedCache.size() &&
-   TxdOp::isContext(unusedCache.front())) {
+   txd_op::isContext(unusedCache.front())) {
 DPRINTF(EthernetDesc, "Got context descriptor type...\n");

 desc = unusedCache.front();
@@ -1528,19 +1528,19 @@


 // is this going to be a tcp or udp packet?
-isTcp = TxdOp::tcp(desc) ? true : false;
+isTcp = txd_op::tcp(desc) ? true : false;

 // setup all the TSO variables, they'll be ignored if we don't use
 // tso for this connection
-tsoHeaderLen = TxdOp::hdrlen(desc);
-tsoMss  = TxdOp::mss(desc);
+tsoHeaderLen = txd_op::hdrlen(desc);
+tsoMss  = txd_op::mss(desc);

-if (TxdOp::isType(desc, TxdOp::TXD_CNXT) && TxdOp::tse(desc)) {
+if (txd_op::isType(desc, txd_op::TXD_CNXT) && txd_op::tse(desc)) {
 DPRINTF(EthernetDesc, "TCP offload enabled for packet hdrlen: "
-"%d mss: %d paylen %d\n", TxdOp::hdrlen(desc),
-TxdOp::mss(desc), TxdOp::getLen(desc));
+"%d mss: %d paylen %d\n", txd_op::hdrlen(desc),
+txd_op::mss(desc), txd_op::getLen(desc));
 useTso = true;
-tsoTotalLen = TxdOp::getLen(desc);
+tsoTotalLen = txd_op::getLen(desc);
 tsoLoadedHeader = false;
 tsoDescBytesUsed = 0;
 tsoUsedLen = 0;
@@ -1550,7 +1550,7 @@
 tsoCopyBytes = 0;
 }

-TxdOp::setDd(desc);
+txd_op::setDd(desc);
 unusedCache.pop_front();
 usedCache.push_back(desc);
 }
@@ -1559,13 +1559,13 @@
 return;

 desc = unusedCache.front();
-if (!useTso && TxdOp::isType(desc, TxdOp::TXD_ADVDATA) &&
-TxdOp::tse(desc)) {
+if (!useTso && txd_op::isType(desc, txd_op::TXD_ADVDATA) &&
+txd_op::tse(desc)) {
 DPRINTF(EthernetDesc, "TCP offload(adv) enabled for packet "
 "hdrlen: %d mss: %d paylen %d\n",
-tsoHeaderLen, tsoMss, TxdOp::getTsoLen(desc));
+tsoHeaderLen, tsoMss, txd_op::getTsoLen(desc));
 useTso = true;
-tsoTotalLen = TxdOp::getTsoLen(desc);
+tsoTotalLen = txd_op::getTsoLen(desc);
 tsoLoadedHeader = false;
 tsoDescBytesUsed = 0;
 tsoUsedLen = 0;
@@ -1577,10 +1577,10 @@
 if (useTso && !tsoLoadedHeader) {
 // we need to fetch a header
 DPRINTF(EthernetDesc, "Starting DMA of TSO header\n");
-assert(TxdOp::isData(desc) && TxdOp::getLen(desc) >= tsoHeaderLen);
+assert(txd_op::isData(desc) && txd_op::getLen(desc) >=  
tsoHeaderLen);

 pktWaiting = true;
 assert(tsoHeaderLen <= 256);
-igbe->dmaRead(pciToDma(TxdOp::getBuf(desc)),
+igbe->dmaRead(pciToDma(txd_op::getBuf(desc)),
   tsoHeaderLen, , tsoHeader, 0);
 }
 }
@@ -1594,9 +1594,9 @@
 assert(unusedCache.size());
 TxDesc *desc = unusedCache.front();
 DPRINTF(EthernetDesc, "TSO: len: %d tsoHeaderLen: %d\n",
-TxdOp::getLen(desc), tsoHeaderLen);
+txd_op::getLen(desc), tsoHeaderLen);

-if (TxdOp::getLen(desc) == tsoHeaderLen) {
+if (txd_op::getLen(desc) == tsoHeaderLen) {
 tsoDescBytesUsed = 0;
 tsoLoadedHeader = true;
 unusedCache.pop_front();
@@ -1630,24 +1630,24 @@

 if (tsoPktHasHeader)
 tsoCopyBytes =  std::min((tsoMss + tsoHeaderLen) - p->length,
- TxdOp::getLen(desc) -  
tsoDescBytesUsed);
+ txd_op::getLen(desc) -  
tsoDescBytesUsed);

 else
 tsoCopyBytes =  std::min(tsoMss,
- TxdOp::getLen(desc) -  
tsoDescBytesUsed);
+ txd_op::getLen(desc) -  
tsoDescBytesUsed);

 unsigned pkt_size =
 tsoCopyBytes + (tsoPktHasHeader ? 0 : tsoHeaderLen);

 DPRINTF(EthernetDesc, "TSO: descBytesUsed: %d copyBytes: %d "
 "this descLen: %d\n",

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename Ps2 namespace as ps2

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45390 )



Change subject: dev: Rename Ps2 namespace as ps2
..

dev: Rename Ps2 namespace as ps2

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

Ps2 became ps2.

An instance of a PS2Device which was named as ps2 was
renamed as ps2_device.

Change-Id: I6630a0817ee4aa724ce4e76edac164c28a583d61
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/ps2/device.cc
M src/dev/ps2/keyboard.cc
M src/dev/ps2/mouse.cc
M src/dev/ps2/touchkit.cc
M src/dev/ps2/types.cc
M src/dev/ps2/types.hh
6 files changed, 60 insertions(+), 58 deletions(-)



diff --git a/src/dev/ps2/device.cc b/src/dev/ps2/device.cc
index 47eb026..b9dfafb 100644
--- a/src/dev/ps2/device.cc
+++ b/src/dev/ps2/device.cc
@@ -119,5 +119,5 @@
 void
 PS2Device::sendAck()
 {
-send(Ps2::Ack);
+send(ps2::Ack);
 }
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index d62ec44..86771f6 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -75,36 +75,36 @@
 PS2Keyboard::recv(const std::vector )
 {
 switch (data[0]) {
-  case Ps2::ReadID:
+  case ps2::ReadID:
 DPRINTF(PS2, "Got keyboard read ID command.\n");
 sendAck();
-send(Ps2::Keyboard::ID);
+send(ps2::Keyboard::ID);
 return true;
-  case Ps2::Enable:
+  case ps2::Enable:
 DPRINTF(PS2, "Enabling the keyboard.\n");
 enabled = true;
 sendAck();
 return true;
-  case Ps2::Disable:
+  case ps2::Disable:
 DPRINTF(PS2, "Disabling the keyboard.\n");
 enabled = false;
 sendAck();
 return true;
-  case Ps2::DefaultsAndDisable:
+  case ps2::DefaultsAndDisable:
 DPRINTF(PS2, "Disabling and resetting the keyboard.\n");
 enabled = false;
 sendAck();
 return true;
-  case Ps2::Reset:
+  case ps2::Reset:
 DPRINTF(PS2, "Resetting keyboard.\n");
 enabled = true;
 sendAck();
-send(Ps2::SelfTestPass);
+send(ps2::SelfTestPass);
 return true;
-  case Ps2::Resend:
+  case ps2::Resend:
 panic("Keyboard resend unimplemented.\n");

-  case Ps2::Keyboard::LEDWrite:
+  case ps2::Keyboard::LEDWrite:
 if (data.size() == 1) {
 DPRINTF(PS2, "Got LED write command.\n");
 sendAck();
@@ -118,11 +118,11 @@
 sendAck();
 return true;
 }
-  case Ps2::Keyboard::DiagnosticEcho:
+  case ps2::Keyboard::DiagnosticEcho:
 panic("Keyboard diagnostic echo unimplemented.\n");
-  case Ps2::Keyboard::AlternateScanCodes:
+  case ps2::Keyboard::AlternateScanCodes:
 panic("Accessing alternate scan codes unimplemented.\n");
-  case Ps2::Keyboard::TypematicInfo:
+  case ps2::Keyboard::TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");
 sendAck();
@@ -132,20 +132,20 @@
 sendAck();
 return true;
 }
-  case Ps2::Keyboard::AllKeysToTypematic:
+  case ps2::Keyboard::AllKeysToTypematic:
 panic("Setting all keys to typemantic unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToMakeRelease:
+  case ps2::Keyboard::AllKeysToMakeRelease:
 panic("Setting all keys to make/release unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToMake:
+  case ps2::Keyboard::AllKeysToMake:
 panic("Setting all keys to make unimplemented.\n");
-  case Ps2::Keyboard::AllKeysToTypematicMakeRelease:
+  case ps2::Keyboard::AllKeysToTypematicMakeRelease:
 panic("Setting all keys to "
 "typematic/make/release unimplemented.\n");
-  case Ps2::Keyboard::KeyToTypematic:
+  case ps2::Keyboard::KeyToTypematic:
 panic("Setting a key to typematic unimplemented.\n");
-  case Ps2::Keyboard::KeyToMakeRelease:
+  case ps2::Keyboard::KeyToMakeRelease:
 panic("Setting a key to make/release unimplemented.\n");
-  case Ps2::Keyboard::KeyToMakeOnly:
+  case ps2::Keyboard::KeyToMakeOnly:
 panic("Setting key to make only unimplemented.\n");
   default:
 panic("Unknown keyboard command %#02x.\n", data[0]);
@@ -159,7 +159,7 @@

 // convert the X11 keysym into ps2 codes and update the shift
 // state (shiftDown)
-Ps2::keySymToPs2(key, down, shiftDown, keys);
+ps2::keySymToPs2(key, down, shiftDown, keys);

 // Drop key presses if the keyboard hasn't been enabled by the
 // host. We do that after translating the key code to ensure that
diff --git a/src/dev/ps2/mouse.cc b/src/dev/ps2/mouse.cc
index d8e32f4..108a759 100644
--- a/src/dev/ps2/mouse.cc
+++ b/src/dev/ps2/mouse.cc
@@ -57,45 +57,45 @@
 PS2Mouse::recv(const std::vector )
 {
 switch 

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename Sinic namespace as sinic

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45385 )



Change subject: dev: Rename Sinic namespace as sinic
..

dev: Rename Sinic namespace as sinic

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Sinic became ::sinic.

Change-Id: I0a28089cc9f8f65b33101b4791d67c2f82b85059
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/net/Ethernet.py
M src/dev/net/sinic.cc
M src/dev/net/sinic.hh
M src/dev/net/sinicreg.hh
4 files changed, 9 insertions(+), 7 deletions(-)



diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index 53cc035..dc29ce6 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -229,7 +229,7 @@

 class Sinic(EtherDevBase):
 type = 'Sinic'
-cxx_class = 'Sinic::Device'
+cxx_class = 'sinic::Device'
 cxx_header = "dev/net/sinic.hh"

 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index 9eecfe6..5e27909 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -45,7 +45,7 @@

 using namespace Net;

-namespace Sinic {
+namespace sinic {

 const char *RxStateStrings[] =
 {
@@ -1485,4 +1485,4 @@

 }

-} // namespace Sinic
+} // namespace sinic
diff --git a/src/dev/net/sinic.hh b/src/dev/net/sinic.hh
index 2230a77..f55ebfd 100644
--- a/src/dev/net/sinic.hh
+++ b/src/dev/net/sinic.hh
@@ -29,6 +29,7 @@
 #ifndef __DEV_NET_SINIC_HH__
 #define __DEV_NET_SINIC_HH__

+#include "base/compiler.hh"
 #include "base/inet.hh"
 #include "base/statistics.hh"
 #include "dev/io_device.hh"
@@ -41,7 +42,8 @@
 #include "params/Sinic.hh"
 #include "sim/eventq.hh"

-namespace Sinic {
+GEM5_DEPRECATED_NAMESPACE(Sinic, sinic);
+namespace sinic {

 class Interface;
 class Base : public EtherDevBase
@@ -319,6 +321,6 @@
 virtual void sendDone() { dev->transferDone(); }
 };

-} // namespace Sinic
+} // namespace sinic

 #endif // __DEV_NET_SINIC_HH__
diff --git a/src/dev/net/sinicreg.hh b/src/dev/net/sinicreg.hh
index 97154db..e685b45 100644
--- a/src/dev/net/sinicreg.hh
+++ b/src/dev/net/sinicreg.hh
@@ -52,7 +52,7 @@
 static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
 { return (reg & ~NAME) | ((val << OFFSET) & NAME); }

-namespace Sinic {
+namespace sinic {
 namespace Regs {

 static const int VirtualShift = 8;
@@ -232,6 +232,6 @@
 return true;
 }

-} // namespace Sinic
+} // namespace sinic

 #endif // __DEV_NET_SINICREG_HH__

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45385
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0a28089cc9f8f65b33101b4791d67c2f82b85059
Gerrit-Change-Number: 45385
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Rename SCMI namespace as scmi

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45392 )



Change subject: dev-arm: Rename SCMI namespace as scmi
..

dev-arm: Rename SCMI namespace as scmi

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

SCMI became scmi.

Change-Id: I68f729124079ecce02120577d2b89b25f10bde4a
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/arm/css/Scmi.py
M src/dev/arm/css/scmi_platform.cc
M src/dev/arm/css/scmi_platform.hh
M src/dev/arm/css/scmi_protocols.cc
M src/dev/arm/css/scmi_protocols.hh
5 files changed, 14 insertions(+), 13 deletions(-)



diff --git a/src/dev/arm/css/Scmi.py b/src/dev/arm/css/Scmi.py
index 790806f..b5759cf 100644
--- a/src/dev/arm/css/Scmi.py
+++ b/src/dev/arm/css/Scmi.py
@@ -46,7 +46,7 @@
 """
 type = 'ScmiChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::VirtualChannel"
+cxx_class = "scmi::VirtualChannel"
 shmem_range = Param.AddrRange(
 "Virtual channel's shared memory address range")
 phys_id = Param.Unsigned(4,
@@ -78,7 +78,7 @@
 """
 type = 'ScmiAgentChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::AgentChannel"
+cxx_class = "scmi::AgentChannel"


 class ScmiPlatformChannel(ScmiChannel):
@@ -87,7 +87,7 @@
 """
 type = 'ScmiPlatformChannel'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::PlatformChannel"
+cxx_class = "scmi::PlatformChannel"

 class ScmiCommunication(SimObject):
 """
@@ -98,7 +98,7 @@
 """
 type = 'ScmiCommunication'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::Communication"
+cxx_class = "scmi::Communication"

 agent_channel = Param.ScmiAgentChannel(
 "Agent to Platform channel")
@@ -108,7 +108,7 @@
 class ScmiPlatform(Scp):
 type = 'ScmiPlatform'
 cxx_header = "dev/arm/css/scmi_platform.hh"
-cxx_class = "SCMI::Platform"
+cxx_class = "scmi::Platform"

 comms = VectorParam.ScmiCommunication([],
 "SCMI Communications")
diff --git a/src/dev/arm/css/scmi_platform.cc  
b/src/dev/arm/css/scmi_platform.cc

index 823d225..d9a42da 100644
--- a/src/dev/arm/css/scmi_platform.cc
+++ b/src/dev/arm/css/scmi_platform.cc
@@ -43,7 +43,7 @@
 #include "dev/arm/doorbell.hh"
 #include "mem/packet_access.hh"

-using namespace SCMI;
+using namespace scmi;

 AgentChannel::AgentChannel(const ScmiChannelParams )
   : VirtualChannel(p),
diff --git a/src/dev/arm/css/scmi_platform.hh  
b/src/dev/arm/css/scmi_platform.hh

index 8b23a09..f012213 100644
--- a/src/dev/arm/css/scmi_platform.hh
+++ b/src/dev/arm/css/scmi_platform.hh
@@ -46,8 +46,7 @@

 class Doorbell;

-namespace SCMI
-{
+namespace scmi {

 class Platform;

@@ -326,6 +325,6 @@
 DmaPort dmaPort;
 };

-} // namespace SCMI
+} // namespace scmi

 #endif // __DEV_ARM_CSS_SCMI_PLATFORM_H__
diff --git a/src/dev/arm/css/scmi_protocols.cc  
b/src/dev/arm/css/scmi_protocols.cc

index dcec68e..61b3174 100644
--- a/src/dev/arm/css/scmi_protocols.cc
+++ b/src/dev/arm/css/scmi_protocols.cc
@@ -40,7 +40,7 @@
 #include "debug/SCMI.hh"
 #include "dev/arm/css/scmi_platform.hh"

-using namespace SCMI;
+using namespace scmi;

 const std::string
 Protocol::name() const
diff --git a/src/dev/arm/css/scmi_protocols.hh  
b/src/dev/arm/css/scmi_protocols.hh

index 041dba2..94414e1 100644
--- a/src/dev/arm/css/scmi_protocols.hh
+++ b/src/dev/arm/css/scmi_protocols.hh
@@ -41,8 +41,10 @@
 #include 
 #include 

-namespace SCMI
-{
+#include "base/compiler.hh"
+
+GEM5_DEPRECATED_NAMESPACE(SCMI, scmi);
+namespace scmi {

 class Platform;
 struct Message;
@@ -148,6 +150,6 @@

 };

-}; // namespace SCMI
+}; // namespace scmi

 #endif

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45392
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I68f729124079ecce02120577d2b89b25f10bde4a
Gerrit-Change-Number: 45392
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base,dev: Remove ps2::Mouse namespace

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45393 )



Change subject: base,dev: Remove ps2::Mouse namespace
..

base,dev: Remove ps2::Mouse namespace

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

This namespace didn't bring any benefit on top of
the existing PS2Mouse class, so it was removed.

Change-Id: Ieecad4f6bc2e5e2844f165f317da7e51d7593923
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/ps2/mouse.cc
M src/dev/ps2/mouse.hh
M src/dev/ps2/touchkit.cc
M src/dev/ps2/types.cc
M src/dev/ps2/types.hh
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
7 files changed, 44 insertions(+), 42 deletions(-)



diff --git a/src/dev/ps2/mouse.cc b/src/dev/ps2/mouse.cc
index 108a759..5d71019 100644
--- a/src/dev/ps2/mouse.cc
+++ b/src/dev/ps2/mouse.cc
@@ -47,6 +47,8 @@
 #include "params/PS2Mouse.hh"
 #include "sim/serialize.hh"

+const std::vector PS2Mouse::ID{0x00};
+
 PS2Mouse::PS2Mouse(const PS2MouseParams )
 : PS2Device(p),
   status(0), resolution(4), sampleRate(100)
@@ -60,7 +62,7 @@
   case ps2::ReadID:
 DPRINTF(PS2, "Mouse ID requested.\n");
 sendAck();
-send(ps2::Mouse::ID);
+send(ID);
 return true;
   case ps2::Disable:
 DPRINTF(PS2, "Disabling data reporting.\n");
@@ -82,20 +84,20 @@
 status.enabled = 0;
 sendAck();
 send(ps2::SelfTestPass);
-send(ps2::Mouse::ID);
+send(ID);
 return true;

-  case ps2::Mouse::Scale1to1:
+  case Scale1to1:
 DPRINTF(PS2, "Setting mouse scale to 1:1.\n");
 status.twoToOne = 0;
 sendAck();
 return true;
-  case ps2::Mouse::Scale2to1:
+  case Scale2to1:
 DPRINTF(PS2, "Setting mouse scale to 2:1.\n");
 status.twoToOne = 1;
 sendAck();
 return true;
-  case ps2::Mouse::SetResolution:
+  case SetResolution:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting mouse resolution.\n");
 sendAck();
@@ -106,22 +108,22 @@
 sendAck();
 return true;
 }
-  case ps2::Mouse::GetStatus:
+  case GetStatus:
 DPRINTF(PS2, "Getting mouse status.\n");
 sendAck();
 send((uint8_t *)&(status), 1);
 send(, sizeof(resolution));
 send(, sizeof(sampleRate));
 return true;
-  case ps2::Mouse::ReadData:
+  case ReadData:
 panic("Reading mouse data unimplemented.\n");
-  case ps2::Mouse::ResetWrapMode:
+  case ResetWrapMode:
 panic("Resetting mouse wrap mode unimplemented.\n");
-  case ps2::Mouse::WrapMode:
+  case WrapMode:
 panic("Setting mouse wrap mode unimplemented.\n");
-  case ps2::Mouse::RemoteMode:
+  case RemoteMode:
 panic("Setting mouse remote mode unimplemented.\n");
-  case ps2::Mouse::SampleRate:
+  case SampleRate:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting mouse sample rate.\n");
 sendAck();
diff --git a/src/dev/ps2/mouse.hh b/src/dev/ps2/mouse.hh
index 0a526db..7536cd9 100644
--- a/src/dev/ps2/mouse.hh
+++ b/src/dev/ps2/mouse.hh
@@ -41,6 +41,9 @@
 #ifndef __DEV_PS2_MOUSE_HH__
 #define __DEV_PS2_MOUSE_HH__

+#include 
+#include 
+
 #include "base/bitunion.hh"
 #include "dev/ps2/device.hh"

@@ -62,6 +65,21 @@
 uint8_t sampleRate;

   public:
+enum
+{
+Scale1to1 = 0xE6,
+Scale2to1 = 0xE7,
+SetResolution = 0xE8,
+GetStatus = 0xE9,
+ReadData = 0xEB,
+ResetWrapMode = 0xEC,
+WrapMode = 0xEE,
+RemoteMode = 0xF0,
+SampleRate = 0xF3,
+};
+
+static const std::vector ID;
+
 PS2Mouse(const PS2MouseParams );

 void serialize(CheckpointOut ) const override;
@@ -71,5 +89,7 @@
 bool recv(const std::vector ) override;
 };

+const std::vector PS2Mouse::ID{0x00};
+
 #endif // __DEV_PS2_MOUSE_hH__

diff --git a/src/dev/ps2/touchkit.cc b/src/dev/ps2/touchkit.cc
index f07a2b4..8b564b1 100644
--- a/src/dev/ps2/touchkit.cc
+++ b/src/dev/ps2/touchkit.cc
@@ -87,7 +87,7 @@

   case ps2::ReadID:
 sendAck();
-send(ps2::Mouse::ID);
+send(PS2Mouse::ID);
 return true;

   case ps2::Disable:
@@ -108,17 +108,17 @@
 sendAck();
 return true;

-  case ps2::Mouse::Scale1to1:
-  case ps2::Mouse::Scale2to1:
+  case PS2Mouse::Scale1to1:
+  case PS2Mouse::Scale2to1:
 sendAck();
 return true;

-  case ps2::Mouse::SetResolution:
-  case ps2::Mouse::SampleRate:
+  case PS2Mouse::SetResolution:
+  case PS2Mouse::SampleRate:
 sendAck();
 return data.size() == 2;

-  case ps2::Mouse::GetStatus:
+  case PS2Mouse::GetStatus:
 sendAck();
 send(0);
 send(2); // default 

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename ps2 variables as ps2Device

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45389 )



Change subject: dev: Rename ps2 variables as ps2Device
..

dev: Rename ps2 variables as ps2Device

Pave the way for a ps2 namespace.

Change-Id: I61fa33c57aee3e7c6df02a364420e4f83901f60b
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/arm/kmi.cc
M src/dev/arm/kmi.hh
2 files changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc
index 18fb1f1..4f0541e 100644
--- a/src/dev/arm/kmi.cc
+++ b/src/dev/arm/kmi.cc
@@ -51,9 +51,9 @@
 Pl050::Pl050(const Pl050Params )
 : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
   rawInterrupts(0),
-  ps2(p.ps2)
+  ps2Device(p.ps2)
 {
-ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
+ps2Device->hostRegDataAvailable([this]() { this->updateRxInt(); });
 }

 Tick
@@ -72,13 +72,13 @@
 break;

   case kmiStat:
-status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
+status.rxfull = ps2Device->hostDataAvailable() ? 1 : 0;
 DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
 data = status;
 break;

   case kmiData:
-data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
+data = ps2Device->hostDataAvailable() ? ps2Device->hostRead() : 0;
 updateRxInt();
 DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
 break;
@@ -134,7 +134,7 @@
 DPRINTF(Pl050, "Write Data: %#x\n", data);
 // Clear the TX interrupt before writing new data.
 setTxInt(false);
-ps2->hostWrite((uint8_t)data);
+ps2Device->hostWrite((uint8_t)data);
 // Data is written in 0 time, so raise the TX interrupt again.
 setTxInt(true);
 break;
@@ -167,7 +167,7 @@
 {
 InterruptReg ints = rawInterrupts;

-ints.rx = ps2->hostDataAvailable() ? 1 : 0;
+ints.rx = ps2Device->hostDataAvailable() ? 1 : 0;

 setInterrupts(ints);
 }
diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh
index 2d83c13..03e9dbd 100644
--- a/src/dev/arm/kmi.hh
+++ b/src/dev/arm/kmi.hh
@@ -123,7 +123,7 @@
 InterruptReg getInterrupt() const;

 /** PS2 device connected to this KMI interface */
-PS2Device *ps2;
+PS2Device *ps2Device;

   public:
 Pl050(const Pl050Params );

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45389
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I61fa33c57aee3e7c6df02a364420e4f83901f60b
Gerrit-Change-Number: 45389
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename CopyEngineReg namespace as copy_engine_reg

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45387 )



Change subject: dev: Rename CopyEngineReg namespace as copy_engine_reg
..

dev: Rename CopyEngineReg namespace as copy_engine_reg

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::CopyEngineReg became ::copy_engine_reg.

Change-Id: I8ac5ff272ab6a663a25f245c48827c7ff1b6abc5
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/pci/copy_engine.cc
M src/dev/pci/copy_engine.hh
M src/dev/pci/copy_engine_defs.hh
3 files changed, 8 insertions(+), 7 deletions(-)



diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index c491d66..8780804 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -55,7 +55,7 @@
 #include "sim/stats.hh"
 #include "sim/system.hh"

-using namespace CopyEngineReg;
+using namespace copy_engine_reg;

 CopyEngine::CopyEngine(const Params )
 : PciDevice(p),
diff --git a/src/dev/pci/copy_engine.hh b/src/dev/pci/copy_engine.hh
index 4a5aca6..59f6e39 100644
--- a/src/dev/pci/copy_engine.hh
+++ b/src/dev/pci/copy_engine.hh
@@ -62,9 +62,9 @@
   private:
 DmaPort cePort;
 CopyEngine *ce;
-CopyEngineReg::ChanRegs  cr;
+copy_engine_reg::ChanRegs  cr;
 int channelId;
-CopyEngineReg::DmaDesc *curDmaDesc;
+copy_engine_reg::DmaDesc *curDmaDesc;
 uint8_t *copyBuffer;

 bool busy;
@@ -149,7 +149,7 @@
 } copyEngineStats;

 // device registers
-CopyEngineReg::Regs regs;
+copy_engine_reg::Regs regs;

 // Array of channels each one with regs/dma port/etc
 std::vector chan;
diff --git a/src/dev/pci/copy_engine_defs.hh  
b/src/dev/pci/copy_engine_defs.hh

index 6ac8b48..45fc2bc 100644
--- a/src/dev/pci/copy_engine_defs.hh
+++ b/src/dev/pci/copy_engine_defs.hh
@@ -30,10 +30,11 @@
  * Register and structure descriptions for Intel's I/O AT DMA Engine
  */
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "sim/serialize.hh"

-namespace CopyEngineReg {
-
+GEM5_DEPRECATED_NAMESPACE(CopyEngineReg, copy_engine_reg);
+namespace copy_engine_reg {

 // General Channel independant registers, 128 bytes starting at 0x00
 const uint32_t GEN_CHANCOUNT= 0x00;
@@ -232,6 +233,6 @@

 };

-} // namespace CopyEngineReg
+} // namespace copy_engine_reg



--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45387
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8ac5ff272ab6a663a25f245c48827c7ff1b6abc5
Gerrit-Change-Number: 45387
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev: Rename iGbReg namespace as igbreg

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45391 )



Change subject: dev: Rename iGbReg namespace as igbreg
..

dev: Rename iGbReg namespace as igbreg

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::iGbReg became ::igbreg.

Change-Id: I4b19503c8cda37248667464be0ac4fd9a7bb42d8
Signed-off-by: Daniel R. Carvalho 
---
M src/dev/net/i8254xGBe.cc
M src/dev/net/i8254xGBe.hh
M src/dev/net/i8254xGBe_defs.hh
3 files changed, 17 insertions(+), 17 deletions(-)



diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 73bea7a..c5affcf 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -52,7 +52,7 @@
 #include "sim/stats.hh"
 #include "sim/system.hh"

-using namespace iGbReg;
+using namespace igbreg;
 using namespace Net;

 IGbE::IGbE(const Params )
@@ -1898,7 +1898,7 @@
 {
 DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n",
 completionEnabled);
-igbe->postInterrupt(iGbReg::IT_TXDW);
+igbe->postInterrupt(igbreg::IT_TXDW);
 if (completionEnabled) {
 descEnd = igbe->regs.tdh();
 DPRINTF(EthernetDesc,
@@ -2365,7 +2365,7 @@
 SERIALIZE_SCALAR(eeOpcode);
 SERIALIZE_SCALAR(eeAddr);
 SERIALIZE_SCALAR(lastInterrupt);
-SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+SERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);

 rxFifo.serialize("rxfifo", cp);
 txFifo.serialize("txfifo", cp);
@@ -2416,7 +2416,7 @@
 UNSERIALIZE_SCALAR(eeOpcode);
 UNSERIALIZE_SCALAR(eeAddr);
 UNSERIALIZE_SCALAR(lastInterrupt);
-UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
+UNSERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);

 rxFifo.unserialize("rxfifo", cp);
 txFifo.unserialize("txfifo", cp);
diff --git a/src/dev/net/i8254xGBe.hh b/src/dev/net/i8254xGBe.hh
index 6ae0cb3..2677528 100644
--- a/src/dev/net/i8254xGBe.hh
+++ b/src/dev/net/i8254xGBe.hh
@@ -60,12 +60,12 @@
 IGbEInt *etherInt;

 // device registers
-iGbReg::Regs regs;
+igbreg::Regs regs;

 // eeprom data, status and control bits
 int eeOpBits, eeAddrBits, eeDataBits;
 uint8_t eeOpcode, eeAddr;
-uint16_t flash[iGbReg::EEPROM_SIZE];
+uint16_t flash[igbreg::EEPROM_SIZE];

 // packet fifos
 PacketFifo rxFifo;
@@ -95,7 +95,7 @@
 rxDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting RXT interrupt because RDTR timer expired\n");
-postInterrupt(iGbReg::IT_RXT);
+postInterrupt(igbreg::IT_RXT);
 }

 EventFunctionWrapper rdtrEvent;
@@ -105,7 +105,7 @@
 rxDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting RXT interrupt because RADV timer expired\n");
-postInterrupt(iGbReg::IT_RXT);
+postInterrupt(igbreg::IT_RXT);
 }

 EventFunctionWrapper radvEvent;
@@ -115,7 +115,7 @@
 txDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting TXDW interrupt because TADV timer expired\n");
-postInterrupt(iGbReg::IT_TXDW);
+postInterrupt(igbreg::IT_TXDW);
 }

 EventFunctionWrapper tadvEvent;
@@ -125,7 +125,7 @@
 txDescCache.writeback(0);
 DPRINTF(EthernetIntr,
 "Posting TXDW interrupt because TIDV timer expired\n");
-postInterrupt(iGbReg::IT_TXDW);
+postInterrupt(igbreg::IT_TXDW);
 }
 EventFunctionWrapper tidvEvent;

@@ -145,7 +145,7 @@
  * @param t the type of interrupt we are posting
  * @param now should we ignore the interrupt limiting timer
  */
-void postInterrupt(iGbReg::IntTypes t, bool now = false);
+void postInterrupt(igbreg::IntTypes t, bool now = false);

 /** Check and see if changes to the mask register have caused an  
interrupt

  * to need to be sent or perhaps removed an interrupt cause.
@@ -299,7 +299,7 @@
 };


-class RxDescCache : public DescCache
+class RxDescCache : public DescCache
 {
   protected:
 Addr descBase() const override { return igbe->regs.rdba(); }
@@ -360,7 +360,7 @@

 RxDescCache rxDescCache;

-class TxDescCache  : public DescCache
+class TxDescCache  : public DescCache
 {
   protected:
 Addr descBase() const override { return igbe->regs.tdba(); }
@@ -418,7 +418,7 @@
 unsigned
 descInBlock(unsigned num_desc)
 {
-return num_desc / igbe->cacheBlockSize() /  
sizeof(iGbReg::TxDesc);
+return num_desc / igbe->cacheBlockSize() /  
sizeof(igbreg::TxDesc);

 }

 /** Ask if the packet has been transfered so the state machine can  
give

diff --git a/src/dev/net/i8254xGBe_defs.hh b/src/dev/net/i8254xGBe_defs.hh
index 48610e2..90af3b4 100644
--- a/src/dev/net/i8254xGBe_defs.hh
+++ b/src/dev/net/i8254xGBe_defs.hh
@@ -32,8 +32,8 @@
 #include 

[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Replace M5_HWCAP_SPARC_* constants.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45244 )


Change subject: arch-sparc: Replace M5_HWCAP_SPARC_* constants.
..

arch-sparc: Replace M5_HWCAP_SPARC_* constants.

These were not using correct style and were using an obsolete M5 prefix.

Change-Id: I24273857bee2fcf52f203262b431c23665d5e87f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45244
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/arch/sparc/process.cc
1 file changed, 13 insertions(+), 13 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 791ade6..b2eece7 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -153,26 +153,26 @@
 // maintain double word alignment of the stack pointer.
 uint64_t align = 16;

-enum hardwareCaps
+enum HardwareCaps
 {
-M5_HWCAP_SPARC_FLUSH = 1,
-M5_HWCAP_SPARC_STBAR = 2,
-M5_HWCAP_SPARC_SWAP = 4,
-M5_HWCAP_SPARC_MULDIV = 8,
-M5_HWCAP_SPARC_V9 = 16,
+HwcapSparcFlush = 1,
+HwcapSparcStbar = 2,
+HwcapSparcSwap = 4,
+HwcapSparcMuldiv = 8,
+HwcapSparcV9 = 16,
 // This one should technically only be set
 // if there is a cheetah or cheetah_plus tlb,
 // but we'll use it all the time
-M5_HWCAP_SPARC_ULTRA3 = 32
+HwcapSparcUltra3 = 32
 };

 const int64_t hwcap =
-M5_HWCAP_SPARC_FLUSH |
-M5_HWCAP_SPARC_STBAR |
-M5_HWCAP_SPARC_SWAP |
-M5_HWCAP_SPARC_MULDIV |
-M5_HWCAP_SPARC_V9 |
-M5_HWCAP_SPARC_ULTRA3;
+HwcapSparcFlush |
+HwcapSparcStbar |
+HwcapSparcSwap |
+HwcapSparcMuldiv |
+HwcapSparcV9 |
+HwcapSparcUltra3;

 // Setup the auxilliary vectors. These will already have endian  
conversion.

 // Auxilliary vectors are loaded only for elf formatted executables.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45244
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I24273857bee2fcf52f203262b431c23665d5e87f
Gerrit-Change-Number: 45244
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Fix compilation issues in qos

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45245 )


Change subject: mem: Fix compilation issues in qos
..

mem: Fix compilation issues in qos

Fix circular dependency and related issues.

Change-Id: I48490519fa0a00619a4baede72ebae2868560660
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45245
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
14 files changed, 77 insertions(+), 44 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index ca72a7c..d8cb8bb 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -35,9 +35,12 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "mem_ctrl.hh"
+#include "mem/qos/mem_ctrl.hh"

-#include "turnaround_policy.hh"
+#include "mem/qos/policy.hh"
+#include "mem/qos/q_policy.hh"
+#include "mem/qos/turnaround_policy.hh"
+#include "sim/core.hh"

 namespace QoS {

diff --git a/src/mem/qos/mem_ctrl.hh b/src/mem/qos/mem_ctrl.hh
index 02954d2..dd2fe31 100644
--- a/src/mem/qos/mem_ctrl.hh
+++ b/src/mem/qos/mem_ctrl.hh
@@ -35,22 +35,34 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "debug/QOS.hh"
-#include "mem/qos/policy.hh"
-#include "mem/qos/q_policy.hh"
-#include "params/QoSMemCtrl.hh"
-#include "sim/clocked_object.hh"
-#include "sim/system.hh"
-
-#include 
-#include 
-#include 
-
 #ifndef __MEM_QOS_MEM_CTRL_HH__
 #define __MEM_QOS_MEM_CTRL_HH__

+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "base/logging.hh"
+#include "base/statistics.hh"
+#include "base/trace.hh"
+#include "base/types.hh"
+#include "debug/QOS.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "params/QoSMemCtrl.hh"
+#include "sim/clocked_object.hh"
+#include "sim/cur_tick.hh"
+#include "sim/system.hh"
+
 namespace QoS {

+class Policy;
+class QueuePolicy;
+class TurnaroundPolicy;
+
 /**
  * The QoS::MemCtrl is a base class for Memory objects
  * which support QoS - it provides access to a set of QoS
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index e81788b..73ac2a7 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -33,15 +33,16 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Matteo Andreozzi
  */

+#include "mem/qos/mem_sink.hh"
+
+#include "base/logging.hh"
+#include "base/trace.hh"
 #include "debug/Drain.hh"
 #include "debug/QOS.hh"
-#include "mem_sink.hh"
+#include "mem/qos/q_policy.hh"
 #include "params/QoSMemSinkInterface.hh"
-#include "sim/system.hh"

 namespace QoS {

diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 27eded5..3cbc182 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -33,18 +33,22 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Matteo Andreozzi
  */


 #ifndef __MEM_QOS_MEM_SINK_HH__
 #define __MEM_QOS_MEM_SINK_HH__

+#include 
+#include 
+#include 
+
+#include "base/types.hh"
 #include "mem/abstract_mem.hh"
 #include "mem/qos/mem_ctrl.hh"
 #include "mem/qport.hh"
 #include "params/QoSMemSinkCtrl.hh"
+#include "sim/eventq.hh"

 struct QoSMemSinkInterfaceParams;
 class QoSMemSinkInterface;
diff --git a/src/mem/qos/policy.cc b/src/mem/qos/policy.cc
index c864cf9..5ba40aa 100644
--- a/src/mem/qos/policy.cc
+++ b/src/mem/qos/policy.cc
@@ -33,11 +33,11 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Matteo Andreozzi
  */

-#include "policy.hh"
+#include "mem/qos/policy.hh"
+
+#include "params/QoSPolicy.hh"

 namespace QoS {

diff --git a/src/mem/qos/policy.hh b/src/mem/qos/policy.hh
index d7e3967..d72e2b1 100644
--- a/src/mem/qos/policy.hh
+++ b/src/mem/qos/policy.hh
@@ -33,18 +33,22 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * 

[gem5-dev] Build failed in Jenkins: compiler-checks #72

[jenkins-no-reply--- via gem5-dev]

See 


Changes:

[shingarov] arch-power: Fix precedence of register operands

[shingarov] arch-power: Add fields for DS form instructions

[m] arch-x86: Implement ACPI root tables

[m] arch-x86: Add ACPI support for MADT

[m] configs: Use MADT in x86 full system simulation

[shingarov] arch-power: Refactor load-store instructions

[gabe.black] arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.

[gabe.black] tests: Delete the nmtest "UnitTest".

[gabe.black] tests: Remove the stattest "UnitTest".

[gabe.black] misc: Delete the unittest/genini.py script.

[gabe.black] scons,tests: Delete support for the UnitTest scons class/function.

[gabe.black] arch-x86: Fix x86 build.

[gabe.black] arch-x86: Let individual reg uops specialize their arguments.

[gabe.black] arch-x86: Factor out duplication in the new RegOp base classes.

[gabe.black] arch-x86: Generalize the RegOp operands.

[gabe.black] arch-x86: Use the new op bases for memory microops.

[gabe.black] arch-x86: Remove static code from debug.isa and fix style.

[gabe.black] arch-x86: Use the *Op classes with FP microops.

[gabe.black] arch-x86: Use the newly flexible RegOpT to implement the limm uop.

[gabe.black] arch-x86: Correct style and use uop args in specop.isa.

[gabe.black] arch-x86: Fix style and use uop args in seqop.isa.

[gabe.black] arch-x86: Style fixes and use uop args in the media ops.

[gabe.black] arch-x86: Use regIdx() instead of creating an InstRegIndex 
directly.

[gabe.black] arch-x86: Eliminate the DependenceTags in registers.hh.

[gabe.black] arch-x86: Create a separate type for floating point reg idxs.

[gabe.black] arch-x86: Specialize the remaining operand types for uops.

[gabe.black] arch: Delete a few unused vector register types/constants.

[gabe.black] arch-x86: Make pick, signedPick and merge take indexes directly.

[gabe.black] arch-x86: Use the new multiplication helpers in the mul uops.

[gabe.black] arch-x86: Move the step division helper out of the ISA desc.

[gabe.black] arch-x86: Get rid of the now unused print(Src|Dest)Reg methods.

[gabe.black] base: Add macros to mark things as deprecated.

[gabe.black] base: Mark the unused DPRINTF_UNCONDITIONAL macro as deprecated.

[gabe.black] base,arch,dev,mem: Always compile DPRINTFs, even if they're 
disabled.

[gabe.black] base: Collapse the DTRACE macro in DPRINTF.

[gabe.black] base: Simplify the definition of DTRACE.

[Giacomo Travaglini] arch-arm: Fix SMM* instructions

[gabe.black] base,python: Simplify how we check if a debug flag is enabled.

[gabe.black] base: Move TRACING_ON check into Flag::tracing().

[gabe.black] misc: Collapse all uses of DTRACE(x) to Debug::x.

[gabe.black] base,arch-sparc: Overhaul the small fenv wrapper in base.

[gabe.black] arch-arm: Use src/base/fenv.hh instead of raw fenv.h.

[gabe.black] cpu: Delete an unnecessary return in RegId::flatIndex.

[gabe.black] arch,cpu: Get rid of is*Reg() methods in RegId.

[gabe.black] cpu: Get rid of the unused NumRegClasses constant.

[gabe.black] cpu: Get rid of the redundant PhysRegIndex type.

[gabe.black] scons,misc: Remove the ability to disable some trivial features.

[gabe.black] scons: Pull builder definitions out of SConstruct.

[gabe.black] scons: Simplify finding the python lib with ParseConfig.

[gabe.black] scons: Update comments in SConstruct.

[gabe.black] python: Collapse away the now unused readCommandWithReturn 
function.

[gabe.black] python,scons: Move readCommand and compareVersions into site_scons.

[gabe.black] arch-x86: Clean up x86 integer indexes.

[gabe.black] arch-x86: Create some infrastructure for x86 microop operands.

[gabe.black] arch: Set %(op_idx)s properly when predicated operands are present.

[gabe.black] arch-x86: Build source picking into the operands.

[gabe.black] dev: Overload swap_bytes, don't specialize the template.

[gabe.black] sim: Use type_traits to steer swap_bytes.

[gabe.black] base: Move the macros in compiler.hh to a GEM5_ prefix.

[gabe.black] misc: Replace M5_VAR_USED with GEM5_VAR_USED.

[gabe.black] misc: Replace M5_NODISCARD with GEM5_NO_DISCARD.

[gabe.black] misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.

[gabe.black] misc: Replace M5_ATTR_PACKED with GEM5_PACKED.

[gabe.black] arch-sparc: Replace M5_NO_INLINE with GEM5_NO_INLINE.

[gabe.black] misc: Replace M5_LOCAL and M5_WEAK with GEM5_LOCAL and GEM5_WEAK.

[gabe.black] misc: Replace M5_ALIGNED with GEM5_ALIGNED.

[gabe.black] misc: Replace M5_UNREACHABLE with GEM5_UNREACHABLE.

[gabe.black] base: Replace M5_UNLIKELY with GEM5_UNLIKELY.

[gabe.black] misc: Replace M5_FOR_EACH_IN_PACK with GEM5_FOR_EACH_IN_PACK.

[gabe.black] misc: Replace M5_CLASS_VAR_USED with GEM5_CLASS_VAR_USED.

[gabe.black] sim: Deprecate M5_AT_* constants.

[gabe.black] arch: Stop using deprecated M5_AT_* constants.


--
Started by timer
Running as SYSTEM
Building in workspace 

[gem5-dev] Build failed in Jenkins: nightly #308

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[gabe.black] dev: Overload swap_bytes, don't specialize the template.

[gabe.black] sim: Use type_traits to steer swap_bytes.

[gabe.black] base: Move the macros in compiler.hh to a GEM5_ prefix.

[gabe.black] misc: Replace M5_VAR_USED with GEM5_VAR_USED.

[gabe.black] misc: Replace M5_NODISCARD with GEM5_NO_DISCARD.

[gabe.black] misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.

[gabe.black] misc: Replace M5_ATTR_PACKED with GEM5_PACKED.

[gabe.black] arch-sparc: Replace M5_NO_INLINE with GEM5_NO_INLINE.

[gabe.black] misc: Replace M5_LOCAL and M5_WEAK with GEM5_LOCAL and GEM5_WEAK.

[gabe.black] misc: Replace M5_ALIGNED with GEM5_ALIGNED.

[gabe.black] misc: Replace M5_UNREACHABLE with GEM5_UNREACHABLE.

[gabe.black] base: Replace M5_UNLIKELY with GEM5_UNLIKELY.

[gabe.black] misc: Replace M5_FOR_EACH_IN_PACK with GEM5_FOR_EACH_IN_PACK.

[gabe.black] misc: Replace M5_CLASS_VAR_USED with GEM5_CLASS_VAR_USED.

[gabe.black] sim: Deprecate M5_AT_* constants.

[gabe.black] arch: Stop using deprecated M5_AT_* constants.


--
[...truncated 638.87 KB...]
[ RUN  ] IntmathTest.divCeil
[   OK ] IntmathTest.divCeil (0 ms)
[ RUN  ] IntmathTest.mulUnsignedNarrow
[   OK ] IntmathTest.mulUnsignedNarrow (0 ms)
[ RUN  ] IntmathTest.mulSignedNarrow
[   OK ] IntmathTest.mulSignedNarrow (0 ms)
[ RUN  ] IntmathTest.mulUnsignedMid
[   OK ] IntmathTest.mulUnsignedMid (0 ms)
[ RUN  ] IntmathTest.mulSignedMid
[   OK ] IntmathTest.mulSignedMid (0 ms)
[ RUN  ] IntmathTest.mulUnsignedWide
[   OK ] IntmathTest.mulUnsignedWide (0 ms)
[ RUN  ] IntmathTest.mulSignedWide
[   OK ] IntmathTest.mulSignedWide (0 ms)
[ RUN  ] IntmathTest.roundUp
[   OK ] IntmathTest.roundUp (0 ms)
[ RUN  ] IntmathTest.roundDown
[   OK ] IntmathTest.roundDown (0 ms)
[ RUN  ] IntmathTest.Log2i
[   OK ] IntmathTest.Log2i (0 ms)
[--] 13 tests from IntmathTest (0 ms total)

[--] Global test environment tear-down
[==] 14 tests from 2 test suites ran. (0 ms total)
[  PASSED  ] 13 tests.
[  SKIPPED ] 1 test, listed below:
[  SKIPPED ] IntmathDeathTest.Log2iDeath
 [ CXX] NULL/base/loader/image_file_data.cc -> .fo
 [ CXX] NULL/base/logging.test.cc -> .fo
 [ CXX] NULL/base/logging.cc -> .fo
build/NULL/base/channel_addr.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/channel_addr.test.xml
build/NULL/base/coroutine.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/coroutine.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 2 tests from 1 test suite.
[--] Global test environment set-up.
[--] 2 tests from ChannelAddrRange
[ RUN  ] ChannelAddrRange.DefaultInvalid
[   OK ] ChannelAddrRange.DefaultInvalid (0 ms)
[ RUN  ] ChannelAddrRange.Range
[   OK ] ChannelAddrRange.Range (0 ms)
[--] 2 tests from ChannelAddrRange (0 ms total)

[--] Global test environment tear-down
[==] 2 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 2 tests.
build/NULL/base/fiber.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/fiber.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 1 test suite.
[--] Global test environment set-up.
[--] 8 tests from Coroutine
[ RUN  ] Coroutine.Unstarted
[   OK ] Coroutine.Unstarted (0 ms)
[ RUN  ] Coroutine.Unfinished
[   OK ] Coroutine.Unfinished (0 ms)
[ RUN  ] Coroutine.Passing
[   OK ] Coroutine.Passing (0 ms)
[ RUN  ] Coroutine.Returning
[   OK ] Coroutine.Returning (0 ms)
[ RUN  ] Coroutine.Fibonacci
[   OK ] Coroutine.Fibonacci (0 ms)
[ RUN  ] Coroutine.Cooperative
[   OK ] Coroutine.Cooperative (0 ms)
[ RUN  ] Coroutine.Nested
[   OK ] Coroutine.Nested (0 ms)
[ RUN  ] Coroutine.TwoCallers
[   OK ] Coroutine.TwoCallers (0 ms)
[--] 8 tests from Coroutine (0 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 8 tests.
 [ CXX] NULL/base/hostinfo.cc -> .fo
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 3 tests from 1 test suite.
[--] Global test environment set-up.
[--] 3 tests from Fiber
[ RUN  ] Fiber.Starting
[   OK ] Fiber.Starting (0 ms)
[ RUN  ] Fiber.Switching
[   OK ] Fiber.Switching (0 ms)
[ RUN  ] Fiber.Linked
[   OK ] Fiber.Linked (0 ms)
[--] 3 tests from Fiber (0 ms total)

[--] Global test environment tear-down
[==] 3 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 3 tests.
 [ CXX] NULL/base/match.cc -> .fo
 [LINK]  -> NULL/base/loader/image_file_data.test.fast.unstripped
 [ CXX] NULL/base/pixel.test.cc -> .fo