[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Work around a bug in g++ 6 and 7.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45820 )



Change subject: arch-x86: Work around a bug in g++ 6 and 7.
..

arch-x86: Work around a bug in g++ 6 and 7.

These versions of g++ don't handle parameter pack expansion correctly
when there is a parameter pack defined at the class level and then one
which is defined by the constructor itself. Even though it knows what
the outter parameter pack contains, it still re-assigns it to be empty
and puts all arguments into the later parameter pack.

To work around this problem, we will explicitly put the class level
parameters into a tuple, which we then have to go through extra
acrobatics to explode and pass into base class constructors.

That also means that in all subclasses, the arguments which go into the
tuple need to be wrapped in {}s to group them into constructor arguments
for the tuple.

Change-Id: I3139eebd7042b02f50862d88be5c940583a2a809
---
M src/arch/x86/insts/microldstop.hh
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/insts/microspecop.hh
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/microops/specop.isa
9 files changed, 33 insertions(+), 16 deletions(-)



diff --git a/src/arch/x86/insts/microldstop.hh  
b/src/arch/x86/insts/microldstop.hh

index 067e5bd..8ce458b 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -39,6 +39,8 @@
 #ifndef __ARCH_X86_INSTS_MICROLDSTOP_HH__
 #define __ARCH_X86_INSTS_MICROLDSTOP_HH__

+#include 
+
 #include "arch/x86/insts/microop.hh"
 #include "arch/x86/insts/microop_args.hh"
 #include "arch/x86/ldstflags.hh"
@@ -89,7 +91,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-_data, { _scale, _index, _base, _disp, _segment },
+{ _data, { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -108,7 +110,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-_data, { _scale, _index, _base, _disp, _segment },
+{ _data, { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -126,7 +128,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-{ _scale, _index, _base, _disp, _segment },
+{ { _scale, _index, _base, _disp, _segment } },
 data_size, address_size, mem_flags | _segment.index)
 {}
 };
@@ -148,7 +150,7 @@
 Request::FlagsType mem_flags, OpClass op_class) :
 InstOperands(
 mach_inst, mnem, inst_mnem, set_flags, op_class,
-data_low, data_hi, { _scale, _index, _base, _disp, _segment },
+{ data_low, data_hi, { _scale, _index, _base, _disp, _segment  
} },

 data_size, address_size, mem_flags | _segment.index)
 {}
 };
diff --git a/src/arch/x86/insts/microop_args.hh  
b/src/arch/x86/insts/microop_args.hh

index 3a9cb06..f810a74 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -31,6 +31,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/regs/int.hh"
@@ -338,13 +340,26 @@
 template 
 class InstOperands : public Base, public Operands...
 {
+  private:
+using ArgTuple = std::tuple;
+
+template 
+InstOperands(std::index_sequence, ExtMachInst mach_inst,
+const char *mnem, const char *inst_mnem, uint64_t set_flags,
+OpClass op_class, GEM5_VAR_USED ArgTuple args,
+CTorArgs... ctor_args) :
+Base(mach_inst, mnem, inst_mnem, set_flags, op_class,  
ctor_args...),

+Operands(this, std::get(args))...
+{}
+
   protected:
 template 
 InstOperands(ExtMachInst mach_inst, const char *mnem,
 const char *inst_mnem, uint64_t set_flags, OpClass op_class,
-typename Operands::ArgType... args, CTorArgs... ctor_args) :
-Base(mach_inst, mnem, inst_mnem, set_flags, op_class,  
ctor_args...),

-Operands(this, args)...
+ArgTuple args, CTorArgs... ctor_args) :
+InstOperands(std::make_index_sequence{},
+mach_inst, mnem, inst_mnem, set_flags, op_class,
+std::move(args), ctor_args...)
 {}

 std::string
diff --git a/src/arch/x86/insts/microspecop.hh  
b/src/arch/x86/insts/microspecop.hh

index 3d2c631..ed78024 100644
--- a/src/arch/x86/insts/microspecop.hh
+++

[gem5-dev] Change in gem5/gem5[develop]: base: Initialize some variables in the wide multiply helpers.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45819 )



Change subject: base: Initialize some variables in the wide multiply  
helpers.

..

base: Initialize some variables in the wide multiply helpers.

Not initializing them seems to upset older versions of g++.

Change-Id: Ib3de0460463f2fe514175484c49e1df68dacb4d3
---
M src/base/intmath.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/base/intmath.hh b/src/base/intmath.hh
index 4be4a3b..78d0795 100644
--- a/src/base/intmath.hh
+++ b/src/base/intmath.hh
@@ -228,7 +228,7 @@
 static constexpr std::pair,  
std::make_unsigned_t>

 mulUnsigned(std::make_unsigned_t val_a, std::make_unsigned_t val_b)
 {
-std::make_unsigned_t hi, low;
+std::make_unsigned_t hi{}, low{};
 mulUnsigned(hi, low, val_a, val_b);
 return {hi, low};
 };
@@ -237,7 +237,7 @@
 static constexpr std::pair, std::make_signed_t>
 mulSigned(std::make_signed_t val_a, std::make_signed_t val_b)
 {
-std::make_signed_t hi, low;
+std::make_signed_t hi{}, low{};
 mulSigned(hi, low, val_a, val_b);
 return {hi, low};
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib3de0460463f2fe514175484c49e1df68dacb4d3
Gerrit-Change-Number: 45819
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: weekly #27

2021-05-20 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[gabe.black] base: Eliminate macros in base/inet.hh|cc.

[gabe.black] base: Fix the compiler guard in base/pollevent.hh

[gabe.black] cpu: Make some compiler guards consistent with the other files.

[gabe.black] cpu: Check the KVM API version with a static_assert instead of 
macros.

[gabe.black] base: Avoid an unused expression error in GEM5_DEPRECATED_MACRO.

[gabe.black] base: Deprecate the UNIT_* macros.

[gabe.black] misc: Switch away from the deprecated UNIT_* macros.

[gabe.black] cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

[gabe.black] base: Stop using macros in base/socket.test.cc.

[gabe.black] cpu: Drop the DynInstPtr types from O3CPUImpl.

[gabe.black] cpu: Remove the O3CPU type from the O3CPUImpl.

[gabe.black] cpu: Remove comm types from O3CPUImpl.

[gabe.black] cpu: Remove the MemDepPred template parameter from MemDepUnit.

[gabe.black] cpu: De-templatize the O3 MemDepUnit.

[gabe.black] cpu: De-templatize the O3 ROB.

[Bobby R. Bruce] mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

[gabe.black] arch-riscv: When an inst generates a fault, return it immediately.

[gabe.black] cpu: De-templatize O3's LSQUnit.

[gabe.black] cpu: De-templatize the O3 InstructionQueue.

[gabe.black] cpu: De-templatize the O3 DefaultFetch.

[gabe.black] cpu: De-templatize the O3 DefaultDecode.

[gabe.black] cpu: De-templatize the O3 LSQ.

[gabe.black] cpu: De-templatize the O3 DefaultIEW.

[gabe.black] cpu: De-templatize the O3 DefaultRename.

[gabe.black] cpu: De-templatize the O3 DefaultCommit.

[gabe.black] cpu: De-templatize the O3ThreadContext.

[gabe.black] cpu: Delete the unnecessary BaseO3CPU class.

[gabe.black] cpu: De-templatize the FullO3CPU class.

[gabe.black] cpu: De-templatize the O3ThreadState.

[gabe.black] cpu: Delete the now unused cpu/o3/impl.hh.


--
[...truncated 503.35 KB...]
 [EMBED PY] SPARC/marshal, SPARC/mem/ruby/protocol/L1Cache_Controller.py -> 
SPARC/mem/ruby/protocol/L1Cache_Controller.py.cc
 [ CXX] SPARC/arch/generic/BaseTLB.py.cc -> .o
 [ CXX] SPARC/mem/ruby/protocol/L1Cache_Controller.py.cc -> .o
 [EMBED PY] SPARC/marshal, SPARC/mem/cache/Cache.py -> 
SPARC/mem/cache/Cache.py.cc
 [ CXX] SPARC/mem/cache/Cache.py.cc -> .o
 [EMBED PY] SPARC/marshal, SPARC/mem/ruby/protocol/Directory_Controller.py -> 
SPARC/mem/ruby/protocol/Directory_Controller.py.cc
 [ CXX] SPARC/mem/ruby/protocol/Directory_Controller.py.cc -> .o
 [EMBED PY] SPARC/marshal, arch/sparc/SparcTLB.py -> arch/sparc/SparcTLB.py.cc
 [ CXX] SPARC/arch/sparc/SparcTLB.py.cc -> .o
 [EMBED PY] SPARC/marshal, dev/Device.py -> dev/Device.py.cc
 [ CXX] SPARC/dev/Device.py.cc -> .o
 [EMBED PY] SPARC/marshal, python/m5/ext/pystats/group.py -> 
python/m5/ext/pystats/group.py.cc
 [ CXX] SPARC/python/m5/ext/pystats/group.py.cc -> .o
 [EMBED PY] SPARC/marshal, dev/serial/Uart.py -> dev/serial/Uart.py.cc
 [ CXX] SPARC/dev/serial/Uart.py.cc -> .o
 [EMBED PY] SPARC/marshal, python/m5/internal/params.py -> 
python/m5/internal/params.py.cc
 [ CXX] SPARC/python/m5/internal/params.py.cc -> .o
 [EMBED PY] SPARC/marshal, dev/pci/PciDevice.py -> dev/pci/PciDevice.py.cc
 [ CXX] SPARC/dev/pci/PciDevice.py.cc -> .o
 [EMBED PY] SPARC/marshal, dev/sparc/T1000.py -> dev/sparc/T1000.py.cc
 [ CXX] SPARC/dev/sparc/T1000.py.cc -> .o
 [EMBED PY] SPARC/marshal, python/m5/options.py -> python/m5/options.py.cc
 [ CXX] SPARC/python/m5/options.py.cc -> .o
 [EMBED PY] SPARC/marshal, python/m5/core.py -> python/m5/core.py.cc
 [EMBED PY] SPARC/marshal, sim/power/ThermalModel.py -> 
sim/power/ThermalModel.py.cc
 [ CXX] SPARC/python/m5/core.py.cc -> .o
 [ CXX] SPARC/sim/power/ThermalModel.py.cc -> .o
 [EMBED PY] SPARC/marshal, sim/probe/Probe.py -> sim/probe/Probe.py.cc
 [ CXX] SPARC/sim/probe/Probe.py.cc -> .o
 [EMBED PY] SPARC/marshal, sim/PowerDomain.py -> sim/PowerDomain.py.cc
 [ CXX] SPARC/sim/PowerDomain.py.cc -> .o
 [EMBED PY] SPARC/marshal, cpu/simple/probes/SimPoint.py -> 
cpu/simple/probes/SimPoint.py.cc
 [ CXX] SPARC/cpu/simple/probes/SimPoint.py.cc -> .o
 [EMBED PY] SPARC/marshal, cpu/simple/NonCachingSimpleCPU.py -> 
cpu/simple/NonCachingSimpleCPU.py.cc
 [ CXX] SPARC/cpu/simple/NonCachingSimpleCPU.py.cc -> .o
 [EMBED PY] SPARC/marshal, SPARC/mem/MemDelay.py -> SPARC/mem/MemDelay.py.cc
 [ CXX] SPARC/mem/MemDelay.py.cc -> .o
 [EMBED PY] SPARC/marshal, SPARC/mem/NVMInterface.py -> 
SPARC/mem/NVMInterface.py.cc
 [ CXX] SPARC/mem/NVMInterface.py.cc -> .o
 [EMBED PY] SPARC/marshal, systemc/python/systemc.py -> 
systemc/python/systemc.py.cc
 [ CXX] SPARC/systemc/python/systemc.py.cc -> .o
 [EMBED PY] SPARC/marshal, 
cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py -> 
cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py.cc
 [EMBED PY] SPARC/marshal, SPARC/mem/cache/prefetch/Prefetcher.py ->

[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the now unused cpu/o3/impl.hh.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42119 )


Change subject: cpu: Delete the now unused cpu/o3/impl.hh.
..

cpu: Delete the now unused cpu/o3/impl.hh.

Change-Id: I99b6ec745066c154079c3f44086d2e8721c0ed82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42119
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/cpu/o3/checker.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/fetch.hh
D src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/isa_specific.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/probe/simple_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/thread_context.hh
15 files changed, 1 insertion(+), 57 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/checker.hh b/src/cpu/o3/checker.hh
index 4a2fbbc..da00798 100644
--- a/src/cpu/o3/checker.hh
+++ b/src/cpu/o3/checker.hh
@@ -43,7 +43,6 @@

 #include "cpu/checker/cpu.hh"
 #include "cpu/o3/dyn_inst.hh"
-#include "cpu/o3/impl.hh"

 /**
  * Specific non-templated derived class used for SimObject configuration.
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 2d56272..b345dd1 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -60,7 +60,6 @@
 #include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
 #include "cpu/o3/iew.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/rename.hh"
 #include "cpu/o3/rob.hh"
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 90e59ca..820ff3d 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -46,7 +46,6 @@
 #include "base/statistics.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/timebuf.hh"

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 36d0fa4..e8f8376 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -46,7 +46,6 @@
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
-#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/pred/bpred_unit.hh"
diff --git a/src/cpu/o3/impl.hh b/src/cpu/o3/impl.hh
deleted file mode 100644
index b3b21e9..000
--- a/src/cpu/o3/impl.hh
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_O3_IMPL_HH__
-#define __CPU_O3_IMPL_HH__
-
-/** Implementation specific struct that defines several key types to the
- *  CPU, the stages within the CPU, the time buffers, and the DynInst.
- *  The struct defines the ISA, the CPU policy, the specific DynInst, the
- *  specific O3CPU, and all of the structs from the time buffers to do
- *  communication.
- *  This is one of the key things that must be defined for each hardware
- *  specific CPU implementation.
- */
-struct O3CPUImpl {};
-
-#endif // __CPU_O3_SPARC_IMPL_HH__
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index aab20a9..0d0d0c7 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -53,7 +53,6 @@
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/dep_graph.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
-#include

[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3ThreadState.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42118 )


Change subject: cpu: De-templatize the O3ThreadState.
..

cpu: De-templatize the O3ThreadState.

Change-Id: Ifa6342abe396e131ae8edcb8111453852cdbefd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42118
Tested-by: kokoro 
Reviewed-by: Nathanael Premillieu 
Maintainer: Gabe Black 
---
M src/cpu/o3/SConscript
M src/cpu/o3/commit.cc
M src/cpu/o3/commit.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/thread_context.hh
A src/cpu/o3/thread_state.cc
M src/cpu/o3/thread_state.hh
9 files changed, 93 insertions(+), 67 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 62d01a1..c61c7cf 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -54,6 +54,7 @@
 Source('scoreboard.cc')
 Source('store_set.cc')
 Source('thread_context.cc')
+Source('thread_state.cc')

 DebugFlag('CommitRate')
 DebugFlag('IEW')
diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index 0ef7ccf..64dc73c 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -243,7 +243,7 @@
 }

 void
-DefaultCommit::setThreads(std::vector )
+DefaultCommit::setThreads(std::vector )
 {
 thread = threads;
 }
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 15b73a8..a9d3f32 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -58,8 +58,7 @@

 struct DerivO3CPUParams;

-template 
-struct O3ThreadState;
+class O3ThreadState;

 /**
  * DefaultCommit handles single threaded and SMT commit. Its width is
@@ -86,8 +85,6 @@
 class DefaultCommit
 {
   public:
-typedef O3ThreadState Thread;
-
 /** Overall commit status. Used to determine if the CPU can deschedule
  * itself due to a lack of activity.
  */
@@ -138,7 +135,7 @@
 void regProbePoints();

 /** Sets the list of threads. */
-void setThreads(std::vector );
+void setThreads(std::vector );

 /** Sets the main time buffer pointer, used for backwards  
communication. */

 void setTimeBuffer(TimeBuffer *tb_ptr);
@@ -353,7 +350,7 @@
 FullO3CPU *cpu;

 /** Vector of all of the threads. */
-std::vector thread;
+std::vector thread;

 /** Records that commit has written to the time buffer this cycle.  
Used for
  * the CPU to determine if it can deschedule itself if there is no  
activity.

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 12a4e04..ce83b5b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -303,24 +303,19 @@
 if (FullSystem) {
 // SMT is not supported in FS mode yet.
 assert(numThreads == 1);
-thread[tid] = new O3ThreadState(this, 0, NULL);
+thread[tid] = new O3ThreadState(this, 0, NULL);
 } else {
 if (tid < params.workload.size()) {
 DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
 thread[tid]);
-thread[tid] = new O3ThreadState(this, tid,
+thread[tid] = new O3ThreadState(this, tid,
 params.workload[tid]);
-
-//usedTids[tid] = true;
-//threadMap[tid] = tid;
 } else {
 //Allocate Empty thread so M5 can use later
 //when scheduling threads to CPU
 Process* dummy_proc = NULL;

-thread[tid] = new O3ThreadState(this, tid,
-dummy_proc);
-//usedTids[tid] = false;
+thread[tid] = new O3ThreadState(this, tid, dummy_proc);
 }
 }

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index beb5dff..2d56272 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -599,7 +599,7 @@
 System *system;

 /** Pointers to all of the threads in the CPU. */
-std::vector *> thread;
+std::vector thread;

 /** Threads Scheduled to Enter CPU */
 std::list cpuWaitList;
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 0bbec8c..3e58ab0 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -106,7 +106,7 @@
 BaseCPU *getCpuPtr() { return cpu; }

 /** Pointer to the thread state. */
-O3ThreadState *thread = nullptr;
+O3ThreadState *thread = nullptr;

 /** The kind of fault this instruction has generated. */
 Fault fault = NoFault;
@@ -1014,11 +1014,7 @@
 void setTid(ThreadID tid) { threadNumber = tid; }

 /** Sets the pointer to the thread state. */
-void
-setThreadState(O3ThreadState *state)
-{
-thread = state;
-}
+void setThreadState(O3ThreadState *state) { thread = state; }

 /** Returns the thread context. */
 ThreadContext *tcBase()

[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3ThreadContext.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42115 )


Change subject: cpu: De-templatize the O3ThreadContext.
..

cpu: De-templatize the O3ThreadContext.

Change-Id: I1559760949031bd63bd3a48e62c37448c1f6f5b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42115
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Nathanael Premillieu 
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
D src/cpu/o3/thread_context_impl.hh
5 files changed, 293 insertions(+), 364 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 07e0893..b4c7718 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -334,15 +334,15 @@
 ThreadContext *tc;

 // Setup the TC that will serve as the interface to the  
threads/CPU.

-O3ThreadContext *o3_tc = new O3ThreadContext;
+O3ThreadContext *o3_tc = new O3ThreadContext;

 tc = o3_tc;

 // If we're using a checker, then the TC should be the
 // CheckerThreadContext.
 if (params.checker) {
-tc = new CheckerThreadContext >(
-o3_tc, this->checker);
+tc = new CheckerThreadContext(
+o3_tc, this->checker);
 }

 o3_tc->cpu = this;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index ca5d7be..ff7e0ab 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -76,7 +76,6 @@
 template 
 class Checker;
 class ThreadContext;
-template 
 class O3ThreadContext;

 class Checkpoint;
@@ -106,7 +105,7 @@

 typedef typename std::list::iterator ListIt;

-friend class O3ThreadContext;
+friend class O3ThreadContext;

   public:
 enum Status
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index db07162..c4f5366 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -1,4 +1,17 @@
 /*
+ * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -28,8 +41,277 @@

 #include "cpu/o3/thread_context.hh"

-#include "cpu/o3/impl.hh"
-#include "cpu/o3/thread_context_impl.hh"
+#include "arch/vecregs.hh"
+#include "config/the_isa.hh"
+#include "debug/O3CPU.hh"

-template class O3ThreadContext;
+PortProxy&
+O3ThreadContext::getVirtProxy()
+{
+return thread->getVirtProxy();
+}

+void
+O3ThreadContext::takeOverFrom(ThreadContext *old_context)
+{
+::takeOverFrom(*this, *old_context);
+
+getIsaPtr()->takeOverFrom(this, old_context);
+
+TheISA::Decoder *newDecoder = getDecoderPtr();
+TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
+newDecoder->takeOverFrom(oldDecoder);
+
+thread->funcExeInst = old_context->readFuncExeInst();
+
+thread->noSquashFromTC = false;
+thread->trapPending = false;
+}
+
+void
+O3ThreadContext::activate()
+{
+DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
+threadId());
+
+if (thread->status() == ThreadContext::Active)
+return;
+
+thread->lastActivate = curTick();
+thread->setStatus(ThreadContext::Active);
+
+// status() == Suspended
+cpu->activateContext(thread->threadId());
+}
+
+void
+O3ThreadContext::suspend()
+{
+DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
+threadId());
+
+if (thread->status() == ThreadContext::Suspended)
+return;
+
+if (cpu->isDraining()) {
+DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
+return;
+}
+
+thread->lastActivate = curTick();
+thread->lastSuspend = curTick();
+
+thread->setStatus(ThreadContext::Suspended);
+cpu->suspendContext(thread->threadId());
+}
+
+void
+O3ThreadContext::halt()
+{
+DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
+
+if (thread->status() == ThreadContext::Halting ||
+thread->status() == ThreadContext::Halted)
+return;
+
+// the thread is not going to halt/terminate immediately in this cycle.
+// The thread will be removed after

[gem5-dev] Change in gem5/gem5[develop]: cpu: Delete the unnecessary BaseO3CPU class.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42116 )


Change subject: cpu: Delete the unnecessary BaseO3CPU class.
..

cpu: Delete the unnecessary BaseO3CPU class.

This class has no content, and is not used for anything except as an
extra layer between FullO3CPU and BaseCPU.

Change-Id: Idb6258a655b0fb614e94b0fc0e281696d5081ab0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42116
Tested-by: kokoro 
Reviewed-by: Nathanael Premillieu 
Maintainer: Gabe Black 
---
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
2 files changed, 2 insertions(+), 16 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b4c7718..9f2a630 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -64,14 +64,9 @@

 struct BaseCPUParams;

-BaseO3CPU::BaseO3CPU(const BaseCPUParams )
-: BaseCPU(params)
-{
-}
-
 template 
 FullO3CPU::FullO3CPU(const DerivO3CPUParams )
-: BaseO3CPU(params),
+: BaseCPU(params),
   mmu(params.mmu),
   tickEvent([this]{ tick(); }, "FullO3CPU tick",
 false, Event::CPU_Tick_Pri),
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index ff7e0ab..820a223 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -81,22 +81,13 @@
 class Checkpoint;
 class Process;

-struct BaseCPUParams;
-
-class BaseO3CPU : public BaseCPU
-{
-//Stuff that's pretty ISA independent will go here.
-  public:
-BaseO3CPU(const BaseCPUParams );
-};
-
 /**
  * FullO3CPU class, has each of the stages (fetch through commit)
  * within it, as well as all of the time buffers between stages.  The
  * tick() function for the CPU is defined here.
  */
 template 
-class FullO3CPU : public BaseO3CPU
+class FullO3CPU : public BaseCPU
 {
   public:
 // Typedefs from the Impl here.



17 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idb6258a655b0fb614e94b0fc0e281696d5081ab0
Gerrit-Change-Number: 42116
Gerrit-PatchSet: 20
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nathanael Premillieu 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: When an inst generates a fault, return it immediately.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45520 )


Change subject: arch-riscv: When an inst generates a fault, return it  
immediately.

..

arch-riscv: When an inst generates a fault, return it immediately.

When a fault is generated, it needs to be returned, and nothing else
should be done. There's no point in keeping it around and having to
check over and over if there was a fault and if other parts of the
execute functions should be skipped.

This simplifies the logic a bit which should speed up execution, and
also makes life easier for the compiler since behavior is obvious and
doesn't have to be deduced from possible data values and ifs.

Change-Id: I2004c7d22ac6222e1ef2acb51d49b4eb2e60b144
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45520
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
Reviewed-by: Ayaz Akram 
---
M src/arch/riscv/fp_inst.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
8 files changed, 199 insertions(+), 324 deletions(-)

Approvals:
  Ayaz Akram: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/fp_inst.hh b/src/arch/riscv/fp_inst.hh
index 3a1e2d6..604c016 100644
--- a/src/arch/riscv/fp_inst.hh
+++ b/src/arch/riscv/fp_inst.hh
@@ -34,10 +34,10 @@
 #define  
RM_REQUIRED \
 uint_fast8_t rm =  
ROUND_MODE;   \
 uint_fast8_t frm =  
xc->readMiscReg(MISCREG_FRM);\
-if (rm ==  
7) \
+if (rm ==  
7)\
 rm =  
frm;   \
-if (rm >  
4)  \
-fault = std::make_shared("RM fault",  
machInst);\
+if (rm >  
4) \
+return std::make_shared("RM fault",  
machInst);\
 softfloat_roundingMode =  
rm;\


 #endif // __ARCH_RISCV_FP_INST_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f4bdb7..823698c 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -43,7 +43,7 @@
   CIMM8<5:2> << 6;
 }}, {{
 if (machInst == 0)
-fault = std::make_shared("zero  
instruction",
+return std::make_shared("zero  
instruction",

machInst);
 Rp2 = sp + imm;
 }}, uint64_t);
@@ -53,7 +53,7 @@
 }}, {{
 STATUS status = xc->readMiscReg(MISCREG_STATUS);
 if (status.fs == FPUStatus::OFF)
-fault = std::make_shared("FPU is  
off",

+return std::make_shared("FPU is off",
machInst);

 Fp2_bits = Mem;
@@ -83,7 +83,7 @@
 }}, {{
 STATUS status = xc->readMiscReg(MISCREG_STATUS);
 if (status.fs == FPUStatus::OFF)
-fault = std::make_shared("FPU is  
off",

+return std::make_shared("FPU is off",
machInst);

 Mem = Fp2_bits;
@@ -117,11 +117,12 @@
 }}, {{
 if ((RC1 == 0) != (imm == 0)) {
 if (RC1 == 0) {
-fault = std::make_shared(
+return std::make_shared(
 "source reg x0", machInst);
-} else // imm == 0
-fault = std::make_shared(
+} else { // imm == 0
+return std::make_shared(
 "immediate = 0", machInst);
+}
 }
 Rc1_sd = Rc1_sd + imm;
 }});
@@ -131,7 +132,7 @@
 imm |= ~((uint64_t)0x1F);
 }}, {{
 if (RC1 == 0) {
-fault = std::make_shared(
+return std::make_shared(
 "source reg x0", machInst);
 }
 Rc1_sd = (int32_t)Rc1_sd + imm;
@@ -142,7 +143,7 @@
 imm |= ~((uint64_t)0x1F);
 }}, {{
 if (RC1 == 0) {
-fault = std::make_shared(
+

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

2021-05-20 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45799 )


Change subject: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache
..

mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

This check always equated to False. It should be an 'or' not an 'and'
comparison.

The Clang 11 compiler threw an "overlapping comparisons always evaluate
to false" error for the code generaed from this.

Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45799
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm

index 5c3d5f7..c9fe135 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -358,7 +358,7 @@
   }

   // You have at least half the token in O-like states
-  if (state == State:O && state == State:OM) {
+  if (state == State:O || state == State:OM) {
 assert(cache_entry.Tokens > (max_tokens() / 2));
   }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
Gerrit-Change-Number: 45799
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: De-templatize the O3 ROB.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42106 )


Change subject: cpu: De-templatize the O3 ROB.
..

cpu: De-templatize the O3 ROB.

Change-Id: I257d2a71be5d4254437d84a5bfa59e2e8dc6420a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42106
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/rob.cc
M src/cpu/o3/rob.hh
D src/cpu/o3/rob_impl.hh
6 files changed, 521 insertions(+), 572 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index cb954b8..3c421a4 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -168,7 +168,7 @@
 void setRenameMap(UnifiedRenameMap rm_ptr[O3MaxThreads]);

 /** Sets pointer to the ROB. */
-void setROB(ROB *rob_ptr);
+void setROB(ROB *rob_ptr);

 /** Initializes stage by sending back the number of free entries. */
 void startupStage();
@@ -347,7 +347,7 @@

   public:
 /** ROB interface. */
-ROB *rob;
+ROB *rob;

   private:
 /** Pointer to O3CPU. */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 3e7f97f..8046117 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -324,7 +324,7 @@

 template 
 void
-DefaultCommit::setROB(ROB *rob_ptr)
+DefaultCommit::setROB(ROB *rob_ptr)
 {
 rob = rob_ptr;
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 7b5fac0..2b22002 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -521,7 +521,7 @@
 UnifiedRenameMap commitRenameMap[O3MaxThreads];

 /** The re-order buffer. */
-ROB rob;
+ROB rob;

 /** Active Threads List */
 std::list activeThreads;
diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc
index 6f1af96..52b55ee 100644
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -1,5 +1,17 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,8 +38,497 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "cpu/o3/isa_specific.hh"
-#include "cpu/o3/rob_impl.hh"
+#include "cpu/o3/rob.hh"

-// Force instantiation of InstructionQueue.
-template class ROB;
+#include 
+
+#include "base/logging.hh"
+#include "cpu/o3/dyn_inst.hh"
+#include "cpu/o3/limits.hh"
+#include "debug/Fetch.hh"
+#include "debug/ROB.hh"
+#include "params/DerivO3CPU.hh"
+
+ROB::ROB(FullO3CPU *_cpu, const DerivO3CPUParams )
+: robPolicy(params.smtROBPolicy),
+  cpu(_cpu),
+  numEntries(params.numROBEntries),
+  squashWidth(params.squashWidth),
+  numInstsInROB(0),
+  numThreads(params.numThreads),
+  stats(_cpu)
+{
+//Figure out rob policy
+if (robPolicy == SMTQueuePolicy::Dynamic) {
+//Set Max Entries to Total ROB Capacity
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = numEntries;
+}
+
+} else if (robPolicy == SMTQueuePolicy::Partitioned) {
+DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
+
+//@todo:make work if part_amt doesnt divide evenly.
+int part_amt = numEntries / numThreads;
+
+//Divide ROB up evenly
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = part_amt;
+}
+
+} else if (robPolicy == SMTQueuePolicy::Threshold) {
+DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
+
+int threshold =  params.smtROBThreshold;;
+
+//Divide up by threshold amount
+for (ThreadID tid = 0; tid < numThreads; tid++) {
+maxEntries[tid] = threshold;
+}
+}
+
+for (ThreadID tid = numThreads; tid < O3MaxThreads; tid++) {
+maxEntries[tid] = 0;
+}
+
+resetState();
+}
+
+void
+ROB::resetState()
+{
+for (ThreadID tid = 0; tid  < O3MaxThreads; tid++) {
+threadEntries[tid] = 0;
+squashIt[tid] = instList[tid].end();
+squashedSeqNum[tid] = 0;
+

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove the MemDepPred template parameter from MemDepUnit.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42104 )


Change subject: cpu: Remove the MemDepPred template parameter from  
MemDepUnit.

..

cpu: Remove the MemDepPred template parameter from MemDepUnit.

Hard code this to StoreSet, the only value ever used with this
parameter. If the dependency predictor needs to be updatable, there
should be a well defined interface for it which can be connected at run
time.

Change-Id: Ie30a742eac98220cc39679d26ada5d08099659a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42104
Tested-by: kokoro 
Reviewed-by: Nathanael Premillieu 
Maintainer: Gabe Black 
---
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/mem_dep_unit.cc
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
4 files changed, 63 insertions(+), 67 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 7791cdc..e261d8f 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -292,7 +292,7 @@
 /** The memory dependence unit, which tracks/predicts memory  
dependences

  *  between instructions.
  */
-MemDepUnit memDepUnit[O3MaxThreads];
+MemDepUnit memDepUnit[O3MaxThreads];

 /** The queue to the execute stage.  Issued instructions will be  
written

  *  into it.
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index 21c91d7..963d614 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -28,20 +28,15 @@

 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/mem_dep_unit_impl.hh"
-#include "cpu/o3/store_set.hh"

 #ifdef DEBUG
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_count = 0;
+int MemDepUnit::MemDepEntry::memdep_count = 0;
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_insert = 0;
+int MemDepUnit::MemDepEntry::memdep_insert = 0;
 template <>
-int
-MemDepUnit::MemDepEntry::memdep_erase = 0;
+int MemDepUnit::MemDepEntry::memdep_erase = 0;
 #endif

-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit;
+// Force instantation of memory dependency unit using O3CPUImpl.
+template class MemDepUnit;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index 3874e5f..744d736 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -51,6 +51,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
 #include "cpu/o3/limits.hh"
+#include "cpu/o3/store_set.hh"
 #include "debug/MemDepUnit.hh"

 struct SNHash
@@ -82,7 +83,7 @@
  * utilize.  Thus this class should be most likely be rewritten for other
  * dependence prediction schemes.
  */
-template 
+template 
 class MemDepUnit
 {
   protected:
@@ -259,7 +260,7 @@
  *  this unit what instruction the newly added instruction is dependent
  *  upon.
  */
-MemDepPred depPred;
+StoreSet depPred;

 /** Sequence numbers of outstanding load barriers. */
 std::unordered_set loadBarrierSNs;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh  
b/src/cpu/o3/mem_dep_unit_impl.hh

index ce1aa26..f77fe4f 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -53,15 +53,15 @@
 #include "debug/MemDepUnit.hh"
 #include "params/DerivO3CPU.hh"

-template 
-MemDepUnit::MemDepUnit()
+template 
+MemDepUnit::MemDepUnit()
 : iqPtr(NULL),
   stats(nullptr)
 {
 }

-template 
-MemDepUnit::MemDepUnit(const DerivO3CPUParams )
+template 
+MemDepUnit::MemDepUnit(const DerivO3CPUParams )
 : _name(params.name + ".memdepunit"),
   depPred(params.store_set_clear_period, params.SSITSize,
   params.LFSTSize),
@@ -71,8 +71,8 @@
 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
 }

-template 
-MemDepUnit::~MemDepUnit()
+template 
+MemDepUnit::~MemDepUnit()
 {
 for (ThreadID tid = 0; tid < O3MaxThreads; tid++) {

@@ -96,9 +96,9 @@
 #endif
 }

-template 
+template 
 void
-MemDepUnit::init(
+MemDepUnit::init(
 const DerivO3CPUParams , ThreadID tid, FullO3CPU *cpu)
 {
 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
@@ -113,8 +113,8 @@
 cpu->addStatGroup(stats_group_name.c_str(), );
 }

-template 
-MemDepUnit::
+template 
+MemDepUnit::
 MemDepUnitStats::MemDepUnitStats(Stats::Group *parent)
 : Stats::Group(parent),
   ADD_STAT(insertedLoads, Stats::Units::Count::get(),
@@ -128,9 +128,9 @@
 {
 }

-template 
+template 
 bool
-MemDepUnit::isDrained() const
+MemDepUnit::isDrained() const
 {
 bool drained = instsToReplay.empty()
  && memDepHash.empty()
@@ -141,9 +141,9 @@
 return drained;
 }

-template 
+template 
 void
-MemDepUnit::drainSanityCheck() const
+MemDepUnit::drainSanityCheck() const
 {
 assert(instsToReplay.empty());
 assert(memDepHash.empty());
@@

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove comm types from O3CPUImpl.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42103 )


Change subject: cpu: Remove comm types from O3CPUImpl.
..

cpu: Remove comm types from O3CPUImpl.

This struct is now empty, although we still need to keep it until all
the types within O3 have been de-templated and no longer need a template
argument.

Change-Id: I3889bdbb1b8d638f7b04e5bfb7698e35eb7f2e57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42103
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/cpu/o3/comm.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
17 files changed, 108 insertions(+), 167 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index eb85e5e..c35c2bd 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -51,9 +51,11 @@
 #include "cpu/o3/limits.hh"
 #include "sim/faults.hh"

+namespace O3Comm
+{
+
 /** Struct that defines the information passed from fetch to decode. */
-template
-struct DefaultFetchDefaultDecode
+struct FetchStruct
 {
 int size;

@@ -64,8 +66,7 @@
 };

 /** Struct that defines the information passed from decode to rename. */
-template
-struct DefaultDecodeDefaultRename
+struct DecodeStruct
 {
 int size;

@@ -73,8 +74,7 @@
 };

 /** Struct that defines the information passed from rename to IEW. */
-template
-struct DefaultRenameDefaultIEW
+struct RenameStruct
 {
 int size;

@@ -82,8 +82,7 @@
 };

 /** Struct that defines the information passed from IEW to commit. */
-template
-struct DefaultIEWDefaultCommit
+struct IEWStruct
 {
 int size;

@@ -99,7 +98,6 @@
 bool includeSquashInst[O3MaxThreads];
 };

-template
 struct IssueStruct
 {
 int size;
@@ -108,8 +106,7 @@
 };

 /** Struct that defines all backwards communication. */
-template
-struct TimeBufStruct
+struct TimeStruct
 {
 struct DecodeComm
 {
@@ -225,4 +222,6 @@
 bool iewUnblock[O3MaxThreads];
 };

+} // namespace O3Comm
+
 #endif //__CPU_O3_COMM_HH__
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 4c9a7b5..cb954b8 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -46,6 +46,7 @@
 #include "base/statistics.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/o3/dyn_inst_ptr.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
@@ -86,12 +87,6 @@
 class DefaultCommit
 {
   public:
-// Typedefs from the Impl.
-typedef typename Impl::TimeStruct TimeStruct;
-typedef typename Impl::FetchStruct FetchStruct;
-typedef typename Impl::IEWStruct IEWStruct;
-typedef typename Impl::RenameStruct RenameStruct;
-
 typedef O3ThreadState Thread;

 /** Overall commit status. Used to determine if the CPU can deschedule
@@ -147,15 +142,15 @@
 void setThreads(std::vector );

 /** Sets the main time buffer pointer, used for backwards  
communication. */

-void setTimeBuffer(TimeBuffer *tb_ptr);
+void setTimeBuffer(TimeBuffer *tb_ptr);

-void setFetchQueue(TimeBuffer *fq_ptr);
+void setFetchQueue(TimeBuffer *fq_ptr);

 /** Sets the pointer to the queue coming from rename. */
-void setRenameQueue(TimeBuffer *rq_ptr);
+void setRenameQueue(TimeBuffer *rq_ptr);

 /** Sets the pointer to the queue coming from IEW. */
-void setIEWQueue(TimeBuffer *iq_ptr);
+void setIEWQueue(TimeBuffer *iq_ptr);

 /** Sets the pointer to the IEW stage. */
 void setIEWStage(DefaultIEW *iew_stage);
@@ -326,29 +321,29 @@

   private:
 /** Time buffer interface. */
-TimeBuffer *timeBuffer;
+TimeBuffer *timeBuffer;

 /** Wire to write information heading to previous stages. */
-typename TimeBuffer::wire toIEW;
+typename TimeBuffer::wire toIEW;

 /** Wire to read information from IEW (for ROB). */
-typename TimeBuffer::wire robInfoFromIEW;
+typename TimeBuffer::wire robInfoFromIEW;

-TimeBuffer *fetchQueue;
+TimeBuffer *fetchQueue;

-typename TimeBuffer::wire fromFetch;
+typename TimeBuffer::wire fromFetch;

 /** IEW instruction queue interface. */
-TimeBuffer *iewQueue;
+TimeBuffer *iewQueue;

 /** Wire to read information from IEW queue. */
-typename TimeBuffer::wire fromIEW;
+typename TimeBuffer::wire fromIEW;

 /** Rename instruction queue interface, for ROB. */
-TimeBuffer *renameQueue;
+TimeBuffer *renameQueue;

 /** Wire to read information from rename queue. */
-

[gem5-dev] Change in gem5/gem5[develop]: cpu: Remove the O3CPU type from the O3CPUImpl.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42102 )


Change subject: cpu: Remove the O3CPU type from the O3CPUImpl.
..

cpu: Remove the O3CPU type from the O3CPUImpl.

Change-Id: I4dca10ea3ae1c9bb0f2cb55c7d303f1fd8d25283
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42102
Tested-by: kokoro 
Reviewed-by: Nathanael Premillieu 
Maintainer: Gabe Black 
---
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/mem_dep_unit.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_state.hh
26 files changed, 81 insertions(+), 100 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index bf0b07c..4c9a7b5 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -87,7 +87,6 @@
 {
   public:
 // Typedefs from the Impl.
-typedef typename Impl::O3CPU O3CPU;
 typedef typename Impl::TimeStruct TimeStruct;
 typedef typename Impl::FetchStruct FetchStruct;
 typedef typename Impl::IEWStruct IEWStruct;
@@ -136,7 +135,7 @@

   public:
 /** Construct a DefaultCommit with the given parameters. */
-DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams );
+DefaultCommit(FullO3CPU *_cpu, const DerivO3CPUParams );

 /** Returns the name of the DefaultCommit. */
 std::string name() const;
@@ -357,7 +356,7 @@

   private:
 /** Pointer to O3CPU. */
-O3CPU *cpu;
+FullO3CPU *cpu;

 /** Vector of all of the threads. */
 std::vector thread;
@@ -480,7 +479,7 @@

 struct CommitStats : public Stats::Group
 {
-CommitStats(O3CPU *cpu, DefaultCommit *commit);
+CommitStats(FullO3CPU *cpu, DefaultCommit *commit);
 /** Stat for the total number of squashed instructions discarded by
  * commit.
  */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 06694bf..4442eb9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -79,7 +79,8 @@
 }

 template 
-DefaultCommit::DefaultCommit(O3CPU *_cpu, const DerivO3CPUParams  
)

+DefaultCommit::DefaultCommit(FullO3CPU *_cpu,
+const DerivO3CPUParams )
 : commitPolicy(params.smtCommitPolicy),
   cpu(_cpu),
   iewToCommitDelay(params.iewToCommitDelay),
@@ -150,7 +151,7 @@
 }

 template 
-DefaultCommit::CommitStats::CommitStats(O3CPU *cpu,
+DefaultCommit::CommitStats::CommitStats(FullO3CPU *cpu,
   DefaultCommit *commit)
 : Stats::Group(cpu, "commit"),
   ADD_STAT(commitSquashedInsts, Stats::Units::Count::get(),
@@ -344,7 +345,7 @@

 // Commit must broadcast the number of free entries it has at the
 // start of the simulation, so it starts as active.
-cpu->activateStage(O3CPU::CommitIdx);
+cpu->activateStage(FullO3CPU::CommitIdx);

 cpu->activityThisCycle();
 }
@@ -496,10 +497,10 @@

 if (_nextStatus == Inactive && _status == Active) {
 DPRINTF(Activity, "Deactivating stage.\n");
-cpu->deactivateStage(O3CPU::CommitIdx);
+cpu->deactivateStage(FullO3CPU::CommitIdx);
 } else if (_nextStatus == Active && _status == Inactive) {
 DPRINTF(Activity, "Activating stage.\n");
-cpu->activateStage(O3CPU::CommitIdx);
+cpu->activateStage(FullO3CPU::CommitIdx);
 }

 _status = _nextStatus;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1ed725b..07e0893 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -315,7 +315,7 @@
 DPRINTF(O3CPU, "Workload[%i] process is %#x",
 tid, this->thread[tid]);
 this->thread[tid] = new typename FullO3CPU::Thread(
-(typename Impl::O3CPU *)(this),
+(FullO3CPU *)(this),
 tid, params.workload[tid]);

 //usedTids[tid] = true;
@@ -326,8 +326,7 @@
 Process* dummy_proc = NULL;

 this->thread[tid] = new typename FullO3CPU::Thread(
-(typename Impl::O3CPU *)(this),
-tid, dummy_proc);
+this, tid, dummy_proc);
 //usedTids[tid] = false;
 }
 }
@@ -346,8 +345,7 @@
 o3_tc, this->checker);

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

2021-05-20 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45799 )



Change subject: mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache
..

mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache

This check always equated to False. It should be an 'or' not an 'and'
comparison.

The Clang 11 compiler threw an "overlapping comparisons always evaluate
to false" error for the code generaed from this.

Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
---
M src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm  
b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm

index 5c3d5f7..c9fe135 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
@@ -358,7 +358,7 @@
   }

   // You have at least half the token in O-like states
-  if (state == State:O && state == State:OM) {
+  if (state == State:O || state == State:OM) {
 assert(cache_entry.Tokens > (max_tokens() / 2));
   }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
Gerrit-Change-Number: 45799
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fix struct causing compilation errors in clang-11

2021-05-20 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45800 )



Change subject: arch-riscv: Fix struct causing compilation errors in  
clang-11

..

arch-riscv: Fix struct causing compilation errors in clang-11

Clang 11 threw the following error: `anonymous non-C-compatible type
given name for linkage purposes by typedef declaration; add a tag name
here`.

Clang 11 enforces a restriction on giving non-C-compatible anonymous
structs a typedef name for linking purposes. This change to the C++
standard is discussed here http://wg21.link/p1766r1 and has been
retroactively applied to all C++ standard versions.

Change-Id: I87d84b9a3a842066cd4f61968ceee3fcad267b6f
---
M src/arch/riscv/pmp.hh
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/pmp.hh b/src/arch/riscv/pmp.hh
index 57cb06b..91dd52c 100644
--- a/src/arch/riscv/pmp.hh
+++ b/src/arch/riscv/pmp.hh
@@ -88,7 +88,8 @@
 int numRules;

 /** single pmp entry struct*/
-typedef struct {
+typedef struct PmpEntry
+{
 /** addr range corresponding to a single pmp entry */
 AddrRange pmpAddr = AddrRange(0, 0);
 /** raw addr in pmpaddr register for a pmp entry */

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I87d84b9a3a842066cd4f61968ceee3fcad267b6f
Gerrit-Change-Number: 45800
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove Stage2MMU

2021-05-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45780 )



Change subject: arch-arm: Remove Stage2MMU
..

arch-arm: Remove Stage2MMU

The class was adding some complexity on the python/C++ front:

The Stage2MMU was a child of the ArmTLB and parent of the Stage2TLB
However, it's C++ implementation was solely issuing stage2 table walks
and was not handling the stage2 translation logic in general.

We are removing the class and moving its implemetation structures
within the table walker.

This simplifies the code: the nested Stage2Translation class has
been renamed to Stage2Walk to make its purpose more explicit

The MMU has now a centralized view of all TLBs and Table Walkers in the
system

Change-Id: I8a13a5b793abb7e602e9a05a908e7e0ec3c37247
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmMMU.py
M src/arch/arm/ArmTLB.py
M src/arch/arm/SConscript
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
D src/arch/arm/stage2_mmu.cc
D src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
11 files changed, 318 insertions(+), 395 deletions(-)



diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 06fb964..1c1df39 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -35,8 +35,32 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects.ArmTLB import ArmITB, ArmDTB
+from m5.objects.ArmTLB import ArmITB, ArmDTB, ArmStage2TLB
 from m5.objects.BaseMMU import BaseMMU
+from m5.objects.ClockedObject import ClockedObject
+from m5.params import *
+from m5.proxy import *
+
+# Basic stage 1 translation objects
+class ArmTableWalker(ClockedObject):
+type = 'ArmTableWalker'
+cxx_class = 'ArmISA::TableWalker'
+cxx_header = "arch/arm/table_walker.hh"
+is_stage2 =  Param.Bool(False, "Is this object for stage 2  
translation?")

+num_squash_per_cycle = Param.Unsigned(2,
+"Number of outstanding walks that can be squashed per cycle")
+
+# The port to the memory system. This port is ultimately belonging
+# to the Stage2MMU, and shared by the two table walkers, but we
+# access it through the ITB and DTB walked objects in the CPU for
+# symmetry with the other ISAs.
+port = RequestPort("Port used by the two table walkers")
+
+sys = Param.System(Parent.any, "system object parameter")
+
+# Stage 2 translation objects, only used when virtualisation is being used
+class ArmStage2TableWalker(ArmTableWalker):
+is_stage2 = True

 class ArmMMU(BaseMMU):
 type = 'ArmMMU'
@@ -45,10 +69,27 @@
 itb = ArmITB()
 dtb = ArmDTB()

+stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB")
+stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB")
+
+itb_walker = Param.ArmTableWalker(
+ArmTableWalker(), "HW Table walker")
+dtb_walker = Param.ArmTableWalker(
+ArmTableWalker(), "HW Table walker")
+
+stage2_itb_walker = Param.ArmTableWalker(
+ArmStage2TableWalker(), "HW Table walker")
+stage2_dtb_walker = Param.ArmTableWalker(
+ArmStage2TableWalker(), "HW Table walker")
+
 @classmethod
 def walkerPorts(cls):
-return ["mmu.itb.walker.port", "mmu.dtb.walker.port"]
+return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
+"mmu.stage2_itb_walker.port", "mmu.stage2_dtb_walker.port"]

 def connectWalkerPorts(self, iport, dport):
-self.itb.walker.port = iport
-self.dtb.walker.port = dport
+self.itb_walker.port = iport
+self.dtb_walker.port = dport
+
+self.stage2_itb_walker.port = iport
+self.stage2_dtb_walker.port = dport
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index a821a04..db981d6 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -39,24 +39,6 @@
 from m5.params import *
 from m5.proxy import *
 from m5.objects.BaseTLB import BaseTLB
-from m5.objects.ClockedObject import ClockedObject
-
-# Basic stage 1 translation objects
-class ArmTableWalker(ClockedObject):
-type = 'ArmTableWalker'
-cxx_class = 'ArmISA::TableWalker'
-cxx_header = "arch/arm/table_walker.hh"
-is_stage2 =  Param.Bool(False, "Is this object for stage 2  
translation?")

-num_squash_per_cycle = Param.Unsigned(2,
-"Number of outstanding walks that can be squashed per cycle")
-
-# The port to the memory system. This port is ultimately belonging
-# to the Stage2MMU, and shared by the two table walkers, but we
-# access it through the ITB and DTB walked objects in the CPU for
-# symmetry with the other ISAs.
-port = RequestPort("Port used by the two table walkers")
-
-sys = Param.System(Parent.any, "system object parameter")

 class

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove stage2 TLBI flushes from stage1 flushes

2021-05-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45781 )



Change subject: arch-arm: Remove stage2 TLBI flushes from stage1 flushes
..

arch-arm: Remove stage2 TLBI flushes from stage1 flushes

This is not needed anymore as stage2 flush is now handled by
the MMU. With this patch we are progressively removing any link
between stage1 and stage2 TLBs

Change-Id: I3e9e339a78ac972bc536214152f6c68d6a50cb5c
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/mmu.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
4 files changed, 69 insertions(+), 38 deletions(-)



diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 23fd5a2..ab71b00 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -105,8 +105,27 @@
 void
 flush(const OP _op)
 {
-getITBPtr()->flush(tlbi_op);
-getDTBPtr()->flush(tlbi_op);
+flushStage1(tlbi_op);
+
+if (tlbi_op.stage2Flush()) {
+flushStage2(tlbi_op.makeStage2());
+}
+}
+
+template 
+void
+flushStage1(const OP _op)
+{
+iflush(tlbi_op);
+dflush(tlbi_op);
+}
+
+template 
+void
+flushStage2(const OP _op)
+{
+itbStage2->flush(tlbi_op);
+dtbStage2->flush(tlbi_op);
 }

 template 
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bcc5762..43edddc 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -283,11 +283,6 @@
 }

 stats.flushTlb++;
-
-// If there's a second stage TLB (and we're not it) then flush it as  
well

-if (!isStage2) {
-stage2Tlb->flushAll();
-}
 }

 void
@@ -312,12 +307,6 @@
 }

 stats.flushTlb++;
-
-// If there's a second stage TLB (and we're not it) then flush it as  
well

-// if we're currently in hyp mode
-if (!isStage2 && isHyp) {
-stage2Tlb->flush(tlbi_op.makeStage2());
-}
 }

 void
@@ -341,13 +330,6 @@
 }

 stats.flushTlb++;
-
-// If there's a second stage TLB (and we're not it)
-// and if we're targeting EL1
-// then flush it as well
-if (!isStage2 && tlbi_op.targetEL == EL1) {
-stage2Tlb->flush(tlbi_op.makeStage2());
-}
 }

 void
@@ -372,12 +354,6 @@
 }

 stats.flushTlb++;
-
-// If there's a second stage TLB (and we're not it) then flush it as  
well

-// if we're currently in hyp mode
-if (!isStage2 && tlbi_op.stage2) {
-stage2Tlb->flush(tlbi_op.makeStage2());
-}
 }

 void
@@ -403,11 +379,6 @@
 }

 stats.flushTlb++;
-
-// If there's a second stage TLB (and we're not it) then flush it as  
well

-if (!isStage2 && !hyp) {
-stage2Tlb->flush(tlbi_op.makeStage2());
-}
 }

 void
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index bd784ce..5bcc009 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -48,6 +48,7 @@
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
 el2Enabled = EL2Enabled(tc);
+currentEL = currEL(tc);

 getMMUPtr(tc)->flush(*this);

@@ -108,10 +109,10 @@
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
 el2Enabled = EL2Enabled(tc);

-getMMUPtr(tc)->flush(*this);
+getMMUPtr(tc)->flushStage1(*this);
 CheckerCPU *checker = tc->getCheckerCpuPtr();
 if (checker) {
-getMMUPtr(checker)->flush(*this);
+getMMUPtr(checker)->flushStage1(*this);
 }
 }

@@ -145,11 +146,11 @@
 {
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
-getMMUPtr(tc)->flush(*this);
+getMMUPtr(tc)->flushStage1(*this);

 CheckerCPU *checker = tc->getCheckerCpuPtr();
 if (checker) {
-getMMUPtr(checker)->flush(*this);
+getMMUPtr(checker)->flushStage1(*this);
 }
 }

@@ -158,11 +159,11 @@
 {
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
-getMMUPtr(tc)->flush(*this);
+getMMUPtr(tc)->flushStage1(*this);

 CheckerCPU *checker = tc->getCheckerCpuPtr();
 if (checker) {
-getMMUPtr(checker)->flush(*this);
+getMMUPtr(checker)->flushStage1(*this);
 }
 }

diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index ce72dfb..e1825e3 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -72,6 +72,17 @@
 (*this)(oc);
 }

+/**
+ * Return true if the TLBI op needs to flush stage2
+ * entries, Defaulting to false in the TLBIOp abstract
+ * class
+ */
+virtual bool
+stage2Flush() const
+{
+return false;
+}
+
 bool secureLookup;
 ExceptionLevel targetEL;
 };
@@ -81,11 +92,20 @@
 {
   public:
 TLBIALL(ExceptionLevel _targetEL, bool _secure)
-  : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false)
+  : TLBIOp(_targetEL, _secure),

[gem5-dev] Change in gem5/gem5[develop]: arch: Make MMU::flushAll virtual

2021-05-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45779 )



Change subject: arch: Make MMU::flushAll virtual
..

arch: Make MMU::flushAll virtual

This is enabling ISA specific MMUs to reimplement the flushing
according to their TLB structure

Change-Id: Ic407ab95137b299206cb94926fb69d8898ed33f8
Signed-off-by: Giacomo Travaglini 
---
M src/arch/generic/mmu.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh
index 79e53dc..d7c048c 100644
--- a/src/arch/generic/mmu.hh
+++ b/src/arch/generic/mmu.hh
@@ -61,7 +61,7 @@
 }

   public:
-void
+virtual void
 flushAll()
 {
 dtb->flushAll();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic407ab95137b299206cb94926fb69d8898ed33f8
Gerrit-Change-Number: 45779
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove the TLB::flush overload for TLBI IPA

2021-05-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45782 )



Change subject: arch-arm: Remove the TLB::flush overload for TLBI IPA
..

arch-arm: Remove the TLB::flush overload for TLBI IPA

This will be handled by the MMU

Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
3 files changed, 2 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 43edddc..6c8972b 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -452,15 +452,6 @@
 }

 void
-TLB::flush(const TLBIIPA _op)
-{
-assert(!isStage2);
-
-// Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
-stage2Tlb->flush(tlbi_op.makeStage2());
-}
-
-void
 TLB::drainResume()
 {
 // We might have unserialized something or switched CPUs, so make
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index abe223a..c7144a4 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -66,7 +66,6 @@
 class TLBIMVA;
 class TLBIASID;
 class TLBIMVAA;
-class TLBIIPA;

 class TlbTestInterface
 {
@@ -294,12 +293,6 @@
  */
 void flush(const TLBIMVAA _op);

-/**
- * Invalidate all entries in the stage 2 TLB that match the given ipa
- * and the current VMID
- */
-void flush(const TLBIIPA _op);
-
 Fault trickBoxCheck(const RequestPtr , Mode mode,
 TlbEntry::DomainType domain);

diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index 5bcc009..d918454 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -182,11 +182,11 @@
 void
 TLBIIPA::operator()(ThreadContext* tc)
 {
-getMMUPtr(tc)->flush(*this);
+getMMUPtr(tc)->flushStage2(makeStage2());

 CheckerCPU *checker = tc->getCheckerCpuPtr();
 if (checker) {
-getMMUPtr(checker)->flush(*this);
+getMMUPtr(checker)->flushStage2(makeStage2());
 }
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Gerrit-Change-Number: 45782
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base: Stop using macros in base/socket.test.cc.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45742 )


Change subject: base: Stop using macros in base/socket.test.cc.
..

base: Stop using macros in base/socket.test.cc.

These macros could easily be integer constants instead.

Change-Id: I62711477def1379ba885a7094aa7e00ec17cabeb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45742
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/base/socket.test.cc
1 file changed, 12 insertions(+), 12 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/socket.test.cc b/src/base/socket.test.cc
index 7372911..c08adc2 100644
--- a/src/base/socket.test.cc
+++ b/src/base/socket.test.cc
@@ -31,8 +31,8 @@
 #include "base/gtest/logging.hh"
 #include "base/socket.hh"

-#define TEST_PORT_1 7893
-#define TEST_PORT_2 7894
+static const int TestPort1 = 7893;
+static const int TestPort2 = 7894;

 /*
  * Socket.test tests socket.cc. It should be noted that some features of
@@ -77,7 +77,7 @@
 TEST(SocketTest, ListenToPort)
 {
 MockListenSocket listen_socket;
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1));
+EXPECT_TRUE(listen_socket.listen(TestPort1));
 EXPECT_NE(-1, listen_socket.getfd());
 EXPECT_TRUE(listen_socket.islistening());
 EXPECT_FALSE(listen_socket.allDisabled());
@@ -90,7 +90,7 @@
  * The ListenSocket object should have the same state regardless as to
  * whether reuse is true or false (it is true by default).
  */
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1, false));
+EXPECT_TRUE(listen_socket.listen(TestPort1, false));
 EXPECT_NE(-1, listen_socket.getfd());
 EXPECT_TRUE(listen_socket.islistening());
 EXPECT_FALSE(listen_socket.allDisabled());
@@ -99,13 +99,13 @@
 TEST(SocketTest, RelistenWithSameInstanceSamePort)
 {
 MockListenSocket listen_socket;
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1));
+EXPECT_TRUE(listen_socket.listen(TestPort1));

 /*
  * You cannot listen to another port if you are already listening to  
one.

  */
 gtestLogOutput.str("");
-EXPECT_ANY_THROW(listen_socket.listen(TEST_PORT_1));
+EXPECT_ANY_THROW(listen_socket.listen(TestPort1));
 std::string expected = "panic: Socket already listening!\n";
 std::string actual = gtestLogOutput.str();
 EXPECT_EQ(expected, actual);
@@ -114,13 +114,13 @@
 TEST(SocketTest, RelistenWithSameInstanceDifferentPort)
 {
 MockListenSocket listen_socket;
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1));
+EXPECT_TRUE(listen_socket.listen(TestPort1));

 /*
  * You cannot listen to another port if you are already listening to  
one.

  */
 gtestLogOutput.str("");
-EXPECT_ANY_THROW(listen_socket.listen(TEST_PORT_2));
+EXPECT_ANY_THROW(listen_socket.listen(TestPort2));

 std::string expected = "panic: Socket already listening!\n";
 std::string actual = gtestLogOutput.str();
@@ -130,25 +130,25 @@
 TEST(SocketTest, RelistenWithDifferentInstanceOnDifferentPort)
 {
 MockListenSocket listen_socket;
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1));
+EXPECT_TRUE(listen_socket.listen(TestPort1));

 /*
  * You can listen to another port with a different instance.
  */
 MockListenSocket listen_socket_2;
-EXPECT_TRUE(listen_socket_2.listen(TEST_PORT_2));
+EXPECT_TRUE(listen_socket_2.listen(TestPort2));
 }

 TEST(SocketTest, RelistenWithDifferentInstanceOnSamePort)
 {
 MockListenSocket listen_socket;
-EXPECT_TRUE(listen_socket.listen(TEST_PORT_1));
+EXPECT_TRUE(listen_socket.listen(TestPort1));

 /*
  * You cannot listen to a port that's already being listened to.
  */
 MockListenSocket listen_socket_2;
-EXPECT_FALSE(listen_socket_2.listen(TEST_PORT_1));
+EXPECT_FALSE(listen_socket_2.listen(TestPort1));
 }

 TEST(SocketTest, AcceptError)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62711477def1379ba885a7094aa7e00ec17cabeb
Gerrit-Change-Number: 45742
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

2021-05-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42100 )


Change subject: cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.
..

cpu: Collapse the SimpleCPUPolicy into O3CPUImpl.

Change-Id: I0bc160f28f084c8873c3e19be9a4d7a45f9480a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42100
Reviewed-by: Nathanael Premillieu 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/cpu/o3/commit.hh
M src/cpu/o3/cpu.hh
D src/cpu/o3/cpu_policy.hh
M src/cpu/o3/decode.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/iew.hh
M src/cpu/o3/impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/rename.hh
10 files changed, 44 insertions(+), 111 deletions(-)

Approvals:
  Nathanael Premillieu: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 978619d..6b01359 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -88,12 +88,10 @@
 // Typedefs from the Impl.
 typedef typename Impl::O3CPU O3CPU;
 typedef typename Impl::DynInstPtr DynInstPtr;
-typedef typename Impl::CPUPol CPUPol;
-
-typedef typename CPUPol::TimeStruct TimeStruct;
-typedef typename CPUPol::FetchStruct FetchStruct;
-typedef typename CPUPol::IEWStruct IEWStruct;
-typedef typename CPUPol::RenameStruct RenameStruct;
+typedef typename Impl::TimeStruct TimeStruct;
+typedef typename Impl::FetchStruct FetchStruct;
+typedef typename Impl::IEWStruct IEWStruct;
+typedef typename Impl::RenameStruct RenameStruct;

 typedef O3ThreadState Thread;

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e462322..196f57d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -55,11 +55,11 @@
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/commit.hh"
-#include "cpu/o3/cpu_policy.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/o3/fetch.hh"
 #include "cpu/o3/free_list.hh"
 #include "cpu/o3/iew.hh"
+#include "cpu/o3/impl.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/rename.hh"
 #include "cpu/o3/rob.hh"
@@ -100,7 +100,6 @@
 {
   public:
 // Typedefs from the Impl here.
-typedef typename Impl::CPUPol CPUPolicy;
 typedef typename Impl::DynInstPtr DynInstPtr;
 typedef typename Impl::O3CPU O3CPU;

@@ -558,15 +557,15 @@
 /** Typedefs from the Impl to get the structs that each of the
  *  time buffers should use.
  */
-typedef typename CPUPolicy::TimeStruct TimeStruct;
+typedef typename Impl::TimeStruct TimeStruct;

-typedef typename CPUPolicy::FetchStruct FetchStruct;
+typedef typename Impl::FetchStruct FetchStruct;

-typedef typename CPUPolicy::DecodeStruct DecodeStruct;
+typedef typename Impl::DecodeStruct DecodeStruct;

-typedef typename CPUPolicy::RenameStruct RenameStruct;
+typedef typename Impl::RenameStruct RenameStruct;

-typedef typename CPUPolicy::IEWStruct IEWStruct;
+typedef typename Impl::IEWStruct IEWStruct;

 /** The main time buffer to do backwards communication. */
 TimeBuffer timeBuffer;
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
deleted file mode 100644
index e016548..000
--- a/src/cpu/o3/cpu_policy.hh
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * Copyright (c) 2013 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF