[gem5-dev] Build failed in Jenkins: compiler-checks #111

2021-06-30 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[kyleroarty1716] util: Update GCN Dockerfile for ROCm 4

[odanrc] mem-cache: Creation of dueling classes

[odanrc] mem-cache: Implement a dueling Replacement Policy

[odanrc] mem-cache: Add the DRRIP replacement policy

[odanrc] mem-cache: Change invalidate signature to not const

[shingarov] configs: Fix waiting on remote debugger

[kyleroarty1716] configs: Add mem_banks to Carrizo topology

[kyleroarty1716] arch-x86: Ignore certain syscalls called in ROCm 4

[kyleroarty1716] arch-x86: build with getdents64 if system supports it

[kyleroarty1716] arch-x86,sim: Implement sched_getaffinity

[kyleroarty1716] configs,gpu-compute: Add render driver needed for ROCm 4

[kyleroarty1716] gpu-compute: Ignore GPU kernel names

[kyleroarty1716] dev-hsa,gpu-compute: IOCTL updates for ROCm 4

[kyleroarty1716] gpu-compute: Change certain IOCTL errors to warnings

[kyleroarty1716] gpu-compute: Initialize GPUDriver member variables before use

[Bobby R. Bruce] tests: Update the documentation in compiler-tests.sh

[Bobby R. Bruce] util-docker: Deprecate 18.04-min_dependencies for 20.04-min


--
Started by timer
Running as SYSTEM
Building in workspace 
Selected Git installation does not exist. Using Default
The recommended git tool is: NONE
No credentials specified
 > git rev-parse --resolve-git-dir 
 >  # timeout=10
Fetching changes from the remote Git repository
 > git config remote.origin.url https://gem5.googlesource.com/public/gem5 # 
 > timeout=10
Fetching upstream changes from https://gem5.googlesource.com/public/gem5
 > git --version # timeout=10
 > git --version # 'git version 2.25.1'
 > git fetch --tags --force --progress -- 
 > https://gem5.googlesource.com/public/gem5 
 > +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git rev-parse refs/remotes/origin/develop^{commit} # timeout=10
Checking out Revision 84837422d87d5c805266b286321260c70cd84ad4 
(refs/remotes/origin/develop)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f 84837422d87d5c805266b286321260c70cd84ad4 # timeout=10
Commit message: "util-docker: Deprecate 18.04-min_dependencies for 20.04-min"
 > git rev-list --no-walk 32b4a8cd36dfe441a4487b9ebf99bec05266eb41 # timeout=10
[compiler-checks] $ /bin/sh -xe /tmp/jenkins14634923001354672360.sh
+ ./tests/compiler-tests.sh -j 12
Starting build tests with 'gcc-version-10'...
'gcc-version-10' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'SPARC.opt' with 'gcc-version-10'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-10'...
Done.
  * Building target 'X86.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86.fast' with 'gcc-version-10'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-10'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-10'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-10'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-10'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-10'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-10'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-10'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-10'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-10'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-10'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-10'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'GCN3_X86.opt' with 'gcc-version-9'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target

[gem5-dev] Change in gem5/gem5[develop]: base: Add byte order attribute for object files

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40939 )


Change subject: base: Add byte order attribute for object files
..

base: Add byte order attribute for object files

This adds byte order as an attribute for object files by
introducing new members to the ObjectFile class. This is
populated by the looking at the ELF headers.

Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40939
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Tested-by: kokoro 
---
M src/base/loader/elf_object.cc
M src/base/loader/elf_object.hh
M src/base/loader/object_file.hh
3 files changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index 489a4c0..e7fba63 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -114,6 +114,7 @@

 determineArch();
 determineOpSys();
+determineByteOrder();

 entry = ehdr.e_entry;
 _programHeaderCount = ehdr.e_phnum;
@@ -326,6 +327,15 @@
 }

 void
+ElfObject::determineByteOrder()
+{
+auto edata = ehdr.e_ident[EI_DATA];
+if (edata == ELFDATANONE)
+panic("invalid ELF data encoding");
+byteOrder = (edata == ELFDATA2MSB) ? ByteOrder::big :  
ByteOrder::little;

+}
+
+void
 ElfObject::handleLoadableSegment(GElf_Phdr phdr, int seg_num)
 {
 auto name = std::to_string(seg_num);
diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh
index 797ff1f..7e7b739 100644
--- a/src/base/loader/elf_object.hh
+++ b/src/base/loader/elf_object.hh
@@ -66,6 +66,7 @@

 void determineArch();
 void determineOpSys();
+void determineByteOrder();
 void handleLoadableSegment(GElf_Phdr phdr, int seg_num);

 // These values are provided to a linux process by the kernel, so we
diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index 443dfb9..5e767de 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -38,6 +38,7 @@
 #include "base/loader/symtab.hh"
 #include "base/logging.hh"
 #include "base/types.hh"
+#include "enums/ByteOrder.hh"

 GEM5_DEPRECATED_NAMESPACE(Loader, loader);
 namespace loader
@@ -80,6 +81,7 @@
   protected:
 Arch arch = UnknownArch;
 OpSys opSys = UnknownOpSys;
+ByteOrder byteOrder = ByteOrder::little;

 SymbolTable _symtab;

@@ -106,6 +108,7 @@

 Arch  getArch()  const { return arch; }
 OpSys getOpSys() const { return opSys; }
+ByteOrder getByteOrder() const { return byteOrder; }

 const SymbolTable () const { return _symtab; }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f
Gerrit-Change-Number: 40939
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor argument registers

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40938 )


Change subject: arch-power: Refactor argument registers
..

arch-power: Refactor argument registers

This reintroduces the argument register constants that
were removed in commit 7bb456f02 ("arch-power: Delete
unused register related constants"), adds a definition
for the sixth argument register and switches to these
constants to specify the arguments used by the system
call ABI.

Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40938
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M src/arch/power/regs/int.hh
M src/arch/power/se_workload.cc
2 files changed, 12 insertions(+), 1 deletion(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 2d6a16b..f66be59 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -43,6 +43,12 @@

 // Semantically meaningful register indices
 const int ReturnValueReg = 3;
+const int ArgumentReg0 = 3;
+const int ArgumentReg1 = 4;
+const int ArgumentReg2 = 5;
+const int ArgumentReg3 = 6;
+const int ArgumentReg4 = 7;
+const int ArgumentReg5 = 8;
 const int StackPointerReg = 1;

 enum MiscIntRegNums
diff --git a/src/arch/power/se_workload.cc b/src/arch/power/se_workload.cc
index 31ff243..40179f1 100644
--- a/src/arch/power/se_workload.cc
+++ b/src/arch/power/se_workload.cc
@@ -31,7 +31,12 @@
 {

 const std::vector SEWorkload::SyscallABI::ArgumentRegs = {
-3, 4, 5, 6, 7, 8
+ArgumentReg0,
+ArgumentReg1,
+ArgumentReg2,
+ArgumentReg3,
+ArgumentReg4,
+ArgumentReg5
 };

 } // namespace PowerISA

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5
Gerrit-Change-Number: 40938
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add move condition field instructions

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40936 )


Change subject: arch-power: Add move condition field instructions
..

arch-power: Add move condition field instructions

This adds the following instructions.
  * Move to CR from XER Extended (mcrxrx)
  * Move To One Condition Register Field (mtocrf)
  * Move From One Condition Register Field (mfocrf)

Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40936
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M src/arch/power/isa/decoder.isa
1 file changed, 24 insertions(+), 0 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 4307b25..d752630 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -638,6 +638,14 @@

 567: LoadIndexUpdateOp::lfsux({{ Ft_sf = Mem_sf; }});
 570: IntLogicOp::cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
+
+576: IntOp::mcrxrx({{
+uint8_t res;
+Xer xer = XER;
+res = (xer.ov << 3) | (xer.ov32 << 2) | (xer.ca << 1) |  
xer.ca32;

+CR = insertCRField(CR, BF, res);
+}});
+
 598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
 599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
 631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
@@ -980,6 +988,14 @@
 format IntOp {
 19: decode S {
 0: mfcr({{ Rt = CR; }});
+
+1: mfocrf({{
+int count = popCount(FXM);
+uint64_t mask = 0xf << (4 *  
findMsbSet(FXM));

+if (count == 1) {
+Rt = CR & mask;
+}
+}});
 }

 144: decode S {
@@ -992,6 +1008,14 @@
 }
 CR = (Rs & mask) | (CR & ~mask);
 }});
+
+1: mtocrf({{
+int count = popCount(FXM);
+uint32_t mask = 0xf << (4 *  
findMsbSet(FXM));

+if (count == 1) {
+CR = (Rs & mask) | (CR & ~mask);
+}
+}});
 }

 339: decode SPR {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Gerrit-Change-Number: 40936
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix move condition field instructions

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40935 )


Change subject: arch-power: Fix move condition field instructions
..

arch-power: Fix move condition field instructions

This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
  * Move To Condition Register Fields (mtcrf)
  * Move From Condition Register (mfcr)

Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40935
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
2 files changed, 14 insertions(+), 9 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/bitfields.isa  
b/src/arch/power/isa/bitfields.isa

index 3bfea53..276242e 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -73,6 +73,7 @@

 // FXM field for mtcrf instruction
 def bitfield FXM   <19:12>;
+def bitfield S <20>;

 // Branch fields
 def bitfield BO<25:21>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 6c73b28..4307b25 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -978,17 +978,21 @@

 default: decode XFX_XO {
 format IntOp {
-19: mfcr({{ Rt = CR; }});
+19: decode S {
+0: mfcr({{ Rt = CR; }});
+}

-144: mtcrf({{
-uint32_t mask = 0;
-for (int i = 0; i < 8; ++i) {
-if (((FXM >> i) & 0x1) == 0x1) {
-mask |= 0xf << (4 * i);
+144: decode S {
+0: mtcrf({{
+uint32_t mask = 0;
+for (int i = 0; i < 8; ++i) {
+if (bits(FXM, i)) {
+mask |= 0xf << (4 * i);
+}
 }
-}
-CR = (Rs & mask) | (CR & ~mask);
-}});
+CR = (Rs & mask) | (CR & ~mask);
+}});
+}

 339: decode SPR {
 0x20: mfxer({{ Rt = XER; }});

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Gerrit-Change-Number: 40935
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add time base instructions

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40937 )


Change subject: arch-power: Add time base instructions
..

arch-power: Add time base instructions

This models a pseudo time base using the simulator ticks
and adds the following instructions.
  * Move From Time Base (mftb)
  * Move From Time Base Upper (mftbu)

Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40937
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
2 files changed, 8 insertions(+), 2 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/insts/integer.cc  
b/src/arch/power/insts/integer.cc

index 7795b50..18a72ab 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -46,13 +46,17 @@
 myMnemonic == "mtxer" ||
 myMnemonic == "mtlr"  ||
 myMnemonic == "mtctr" ||
-myMnemonic == "mttar") {
+myMnemonic == "mttar" ||
+myMnemonic == "mttb"  ||
+myMnemonic == "mttbu") {
 printDest = false;
 } else if (myMnemonic == "mfcr"  ||
myMnemonic == "mfxer" ||
myMnemonic == "mflr"  ||
myMnemonic == "mfctr" ||
-   myMnemonic == "mftar") {
+   myMnemonic == "mftar" ||
+   myMnemonic == "mftb"  ||
+   myMnemonic == "mftbu") {
 printSrcs = false;
 }

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d752630..461e2cb 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -1023,6 +1023,8 @@
 0x100: mflr({{ Rt = LR; }});
 0x120: mfctr({{ Rt = CTR; }});
 0x1f9: mftar({{ Rt = TAR; }});
+0x188: mftb({{ Rt = curTick(); }});
+0x1a8: mftbu({{ Rt_uw = curTick() >> 32; }});
 }

 467: decode SPR {

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2
Gerrit-Change-Number: 40937
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add trap instructions

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40934 )


Change subject: arch-power: Add trap instructions
..

arch-power: Add trap instructions

This introduces new classes and new formats for D and X
form instructions, the TO field that is used to encode
the trap conditions and adds the following instructions.
  * Trap Word Immediate (twi)
  * Trap Word (tw)
  * Trap Doubleword Immediate (tdi)
  * Trap Doubleword (td)

Change-Id: I029147ef643c2ee6794426e5e90af4d75f22e92e
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40934
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M src/arch/power/faults.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/types.hh
6 files changed, 225 insertions(+), 0 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index e20ef8e..806f958 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -82,6 +82,16 @@
 }
 };

+
+class TrapFault : public PowerFault
+{
+  public:
+TrapFault()
+: PowerFault("Trap")
+{
+}
+};
+
 } // namespace PowerISA

 #endif // __ARCH_POWER_FAULTS_HH__
diff --git a/src/arch/power/insts/integer.cc  
b/src/arch/power/insts/integer.cc

index 3203507..7795b50 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -820,3 +820,99 @@

 return ss.str();
 }
+
+
+std::string
+IntTrapOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::string ext;
+std::stringstream ss;
+bool printSrcs = true;
+bool printCond = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "tw" &&
+(srcRegIdx(0).index() == 0) && (srcRegIdx(1).index() == 0)) {
+myMnemonic = "trap";
+printSrcs = false;
+} else {
+ext = suffix();
+if (!ext.empty() &&
+(myMnemonic == "tw" || myMnemonic == "td")) {
+myMnemonic += ext;
+} else {
+printCond = true;
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the trap condition
+if (printCond)
+ss << (int) to;
+
+// Print the source registers
+if (printSrcs) {
+if (_numSrcRegs > 0) {
+if (printCond)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+if (_numSrcRegs > 1) {
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+}
+
+return ss.str();
+}
+
+
+std::string
+IntImmTrapOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::string ext;
+std::stringstream ss;
+bool printCond = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+ext = suffix();
+if (!ext.empty()) {
+if (myMnemonic == "twi") {
+myMnemonic = "tw" + ext + "i";
+} else if (myMnemonic == "tdi") {
+myMnemonic = "td" + ext + "i";
+} else {
+printCond = true;
+}
+} else {
+printCond = true;
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the trap condition
+if (printCond)
+ss << (int) to;
+
+// Print the source registers
+if (_numSrcRegs > 0) {
+if (printCond)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+// Print the immediate value
+ss << ", " << si;
+
+return ss.str();
+}
diff --git a/src/arch/power/insts/integer.hh  
b/src/arch/power/insts/integer.hh

index 69bc633..600fdf4 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -713,6 +713,82 @@
 Addr pc, const Loader::SymbolTable *symtab) const override;
 };

+
+/**
+ * Class for integer trap operations.
+ */
+class IntTrapOp : public IntOp
+{
+  protected:
+uint8_t to;
+
+/// Constructor
+IntTrapOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+  : IntOp(mnem, _machInst, __opClass),
+to(machInst.to)
+{
+}
+
+inline bool
+checkTrap(int64_t a, int64_t b) const
+{
+if (((to & 0x10) && (a < b))  ||
+((to & 0x08) && (a > b))  ||
+((to & 0x04) && (a == b)) ||
+((to & 0x02) && ((uint64_t)a < (uint64_t)b)) ||
+((to & 0x01) && ((uint64_t)a > (uint64_t)b))) {
+return true;
+}
+
+return false;
+}
+
+inline std::string
+suffix() const
+{
+std::string str;
+
+switch (to) {
+case

[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding GUPSGen ClockedObject.

2021-06-30 Thread Mahyar Samani (Gerrit) via gem5-dev 
Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47439 )



Change subject: cpu: Adding GUPSGen ClockedObject.
..

cpu: Adding GUPSGen ClockedObject.

This patch adds the code base to implement GUPSGen which is a
ClockedObject that creates read/write requests to the memory
to update elements in an array. The choosing of elements in
the array follow a random distribution. Each element is read
from and return as GUPSGen implements a key-value store program.
Specifications are found in HPCC website from RandomAccess
benchmark. link below.
https://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/

Change-Id: I5c07f230bee317fff2cceec04d15d0218e8ede9a
---
A src/cpu/testers/traffic_gen/GUPSGen.py
M src/cpu/testers/traffic_gen/SConscript
A src/cpu/testers/traffic_gen/gups_gen.cc
A src/cpu/testers/traffic_gen/gups_gen.hh
4 files changed, 761 insertions(+), 0 deletions(-)



diff --git a/src/cpu/testers/traffic_gen/GUPSGen.py  
b/src/cpu/testers/traffic_gen/GUPSGen.py

new file mode 100644
index 000..9a1b7c3
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/GUPSGen.py
@@ -0,0 +1,59 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.proxy import *
+from m5.objects.ClockedObject import ClockedObject
+
+class GUPSGen(ClockedObject):
+"""
+This ClockedObject implements the RandomAccess benchmark specified by  
HPCC

+benchmarks in https://icl.utk.edu/projectsfiles/hpcc/RandomAccess.
+"""
+type = 'GUPSGen'
+cxx_header = "cpu/testers/traffic_gen/gups_gen.hh"
+
+system = Param.System(Parent.any, 'System this generator is a part of')
+
+port = RequestPort('Port that should be connected to other components')
+
+start_addr = Param.Addr(0, 'Start address for allocating update table,'
+' should be a multiple of block_size')
+
+mem_size = Param.MemorySize('Size for allocating update table, based  
on'

+' randomAccess benchmark specification, this'
+' should be equal to half of total system  
memory'

+' ,also should be a power of 2')
+
+update_limit = Param.Int(0, 'The number of updates to issue before the'
+' simulation is over')
+
+request_queue_size = Param.Int(1024, 'Maximum number of parallel'
+' outstanding requests')
+
+init_memory = Param.Bool(False, 'Whether or not to initialize the  
memory,'

+' it does not effect the performance')
diff --git a/src/cpu/testers/traffic_gen/SConscript  
b/src/cpu/testers/traffic_gen/SConscript

index 640d81a..a2670e7 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -43,6 +43,7 @@
 Source('dram_gen.cc')
 Source('dram_rot_gen.cc')
 Source('exit_gen.cc')
+Source('gups_gen.cc')
 Source('hybrid_gen.cc')
 Source('idle_gen.cc')
 Source('linear_gen.cc')
@@ -54,6 +55,9 @@
 DebugFlag('TrafficGen')
 SimObject('BaseTrafficGen.py')

+DebugFlag('GUPSGen')
+SimObject('GUPSGen.py')
+
 if env['USE_PYTHON']:
 Source('pygen.cc', add_tags='python')
 SimObject('PyTrafficGen.py')
diff --git a/src/cpu/testers/traffic_gen/gups_gen.cc  
b/src/cpu/testers/traffic_gen/gups_gen.cc

new file mode 100644
index 000..4a47cf2
--- /dev/null
+++

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Make WeightedLRU inherit from LRU

2021-06-30 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47399 )



Change subject: mem-cache: Make WeightedLRU inherit from LRU
..

mem-cache: Make WeightedLRU inherit from LRU

WeightedLRU adds occupancy information to LRU, so remove the
duplicated code.

Change-Id: Ifec19ea59fb411a5ed7a891e8957b1ab93cdbf05
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
3 files changed, 12 insertions(+), 68 deletions(-)



diff --git a/src/mem/cache/replacement_policies/ReplacementPolicies.py  
b/src/mem/cache/replacement_policies/ReplacementPolicies.py

index 34c8a1e..11de0b2 100644
--- a/src/mem/cache/replacement_policies/ReplacementPolicies.py
+++ b/src/mem/cache/replacement_policies/ReplacementPolicies.py
@@ -120,7 +120,7 @@
 cxx_header = "mem/cache/replacement_policies/tree_plru_rp.hh"
 num_leaves = Param.Int(Parent.assoc, "Number of leaves in each tree")

-class WeightedLRURP(BaseReplacementPolicy):
+class WeightedLRURP(LRURP):
 type = "WeightedLRURP"
 cxx_class = "replacement_policy::WeightedLRU"
 cxx_header = "mem/cache/replacement_policies/weighted_lru_rp.hh"
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.cc  
b/src/mem/cache/replacement_policies/weighted_lru_rp.cc

index 3900014..334a128 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.cc
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.cc
@@ -43,24 +43,15 @@
 {

 WeightedLRU::WeightedLRU(const Params )
-  : Base(p)
+  : LRU(p)
 {
 }

 void
-WeightedLRU::touch(const std::shared_ptr&
-  replacement_data) const
+WeightedLRU::touch(const std::shared_ptr&  
replacement_data,

+int occupancy) const
 {
-std::static_pointer_cast(replacement_data)->
- last_touch_tick =  
curTick();

-}
-
-void
-WeightedLRU::touch(const std::shared_ptr&
-replacement_data, int occupancy) const
-{
-std::static_pointer_cast(replacement_data)->
-  last_touch_tick =  
curTick();

+LRU::touch(replacement_data);
 std::static_pointer_cast(replacement_data)->
   last_occ_ptr = occupancy;
 }
@@ -90,8 +81,8 @@
 } else if (candidate_replacement_data->last_occ_ptr ==
 victim_replacement_data->last_occ_ptr) {
 // Evict the block with a smaller tick.
-Tick time = candidate_replacement_data->last_touch_tick;
-if (time < victim_replacement_data->last_touch_tick) {
+Tick time = candidate_replacement_data->lastTouchTick;
+if (time < victim_replacement_data->lastTouchTick) {
 victim = candidate;
 }
 }
@@ -105,22 +96,4 @@
 return std::shared_ptr(new WeightedLRUReplData);
 }

-void
-WeightedLRU::reset(const std::shared_ptr&
-replacement_data) const
-{
-// Set last touch timestamp
-std::static_pointer_cast(
-replacement_data)->last_touch_tick = curTick();
-}
-
-void
-WeightedLRU::invalidate(
-const std::shared_ptr& replacement_data)
-{
-// Reset last touch timestamp
-std::static_pointer_cast(
-replacement_data)->last_touch_tick = Tick(0);
-}
-
 } // namespace replacement_policy
diff --git a/src/mem/cache/replacement_policies/weighted_lru_rp.hh  
b/src/mem/cache/replacement_policies/weighted_lru_rp.hh

index 82b31d9..2279683 100644
--- a/src/mem/cache/replacement_policies/weighted_lru_rp.hh
+++ b/src/mem/cache/replacement_policies/weighted_lru_rp.hh
@@ -37,7 +37,7 @@
 #include 

 #include "base/types.hh"
-#include "mem/cache/replacement_policies/base.hh"
+#include "mem/cache/replacement_policies/lru_rp.hh"

 struct WeightedLRURPParams;

@@ -45,59 +45,30 @@
 namespace replacement_policy
 {

-class WeightedLRU : public Base
+class WeightedLRU : public LRU
 {
   protected:
 /** Weighted LRU implementation of replacement data. */
-struct WeightedLRUReplData : ReplacementData
+struct WeightedLRUReplData : LRUReplData
 {
 /** pointer for last occupancy */
 int last_occ_ptr;

-/** Tick on which the entry was last touched. */
-Tick last_touch_tick;
-
 /**
  * Default constructor. Invalidate data.
  */
-WeightedLRUReplData() : ReplacementData(),
-last_occ_ptr(0), last_touch_tick(0) {}
+WeightedLRUReplData() : LRUReplData(), last_occ_ptr(0) {}
 };
   public:
 typedef WeightedLRURPParams Params;
 WeightedLRU(const Params );
 ~WeightedLRU() = default;

-/**
- * Invalidate replacement data to set it

[gem5-dev] Change in gem5/gem5[develop]: tests: Update the documentation in compiler-tests.sh

2021-06-30 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47339 )


Change subject: tests: Update the documentation in compiler-tests.sh
..

tests: Update the documentation in compiler-tests.sh

This was out-of-date and has been updated in this commit.

Change-Id: I18519bb2111dae4d2f86806618115153fa8d5372
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47339
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index 41fdfa8..a570e54 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -1,8 +1,8 @@
 #!/bin/bash

 # This script will run all our supported compilers (see the "images" set)
-# against gem5. The "ubuntu-20.04_all-dependencies" and "clang-version-9"
-# images are run against all built targets. The remainder are evaluated
+# against gem5. The images for the latests supported gcc and clang compiler
+# versions are run against all built targets. The remainder are evaluated
 # against a random shuffling of built targets.

 dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18519bb2111dae4d2f86806618115153fa8d5372
Gerrit-Change-Number: 47339
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Deprecate 18.04-min_dependencies for 20.04-min

2021-06-30 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47341 )


Change subject: util-docker: Deprecate 18.04-min_dependencies for 20.04-min
..

util-docker: Deprecate 18.04-min_dependencies for 20.04-min

While we still support Ubuntu 18.04, we will focus testing more-so on
20.04. Therefore, our min-dependency target will now be 20.04 intead of
18.04.

Change-Id: Ib136480e5f9953d216bd5ffc6f0ae3faa1bf2e82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47341
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M util/cloudbuild/cloudbuild_create_images.yaml
R util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile
2 files changed, 8 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/cloudbuild/cloudbuild_create_images.yaml  
b/util/cloudbuild/cloudbuild_create_images.yaml

index b81de98..31876fb 100644
--- a/util/cloudbuild/cloudbuild_create_images.yaml
+++ b/util/cloudbuild/cloudbuild_create_images.yaml
@@ -8,14 +8,14 @@
 - name: 'gcr.io/cloud-builders/docker'
   args: ['build',
 '-t',
-'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
-'util/dockerfiles/ubuntu-18.04_all-dependencies']
+'gcr.io/$PROJECT_ID/ubuntu-20.04_min-dependencies:latest',
+'util/dockerfiles/ubuntu-20.04_min-dependencies']

 - name: 'gcr.io/cloud-builders/docker'
   args: ['build',
 '-t',
-'gcr.io/$PROJECT_ID/ubuntu-18.04_min-dependencies:latest',
-'util/dockerfiles/ubuntu-18.04_min-dependencies']
+'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
+'util/dockerfiles/ubuntu-18.04_all-dependencies']

 - name: 'gcr.io/cloud-builders/docker'
   args: ['build',
@@ -108,8 +108,8 @@
 'util/dockerfiles/gcn-gpu']

 images: ['gcr.io/$PROJECT_ID/ubuntu-20.04_all-dependencies:latest',
+ 'gcr.io/$PROJECT_ID/ubuntu-20.04_min-dependencies:latest',
  'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
- 'gcr.io/$PROJECT_ID/ubuntu-18.04_min-dependencies:latest',
  'gcr.io/$PROJECT_ID/gcc-version-5:latest',
  'gcr.io/$PROJECT_ID/gcc-version-6:latest',
  'gcr.io/$PROJECT_ID/gcc-version-7:latest',
diff --git a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile  
b/util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile

similarity index 85%
rename from util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
rename to util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile
index 53a7d92..68c61ef 100644
--- a/util/dockerfiles/ubuntu-18.04_min-dependencies/Dockerfile
+++ b/util/dockerfiles/ubuntu-20.04_min-dependencies/Dockerfile
@@ -24,12 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-FROM ubuntu:18.04
+FROM ubuntu:20.04

+ENV DEBIAN_FRONTEND=noninteractive
 RUN apt -y update
 RUN apt -y upgrade
-RUN apt -y install build-essential scons zlib1g-dev m4 python3-dev python3  
\

-python3-six
-
-RUN update-alternatives --install /usr/bin/python python /usr/bin/python3  
10

-RUN update-alternatives --install /usr/bin/python python /usr/bin/python2 1
+RUN apt -y install build-essential m4 scons python3-dev python-is-python3

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib136480e5f9953d216bd5ffc6f0ae3faa1bf2e82
Gerrit-Change-Number: 47341
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Change certain IOCTL errors to warnings

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46247 )


Change subject: gpu-compute: Change certain IOCTL errors to warnings
..

gpu-compute: Change certain IOCTL errors to warnings

There are certain IOCTL errors that were triggering with the change to
ROCm 4, however they could be set to warnings without causing any errors
in the program

Change-Id: Ie0052267f3ccfbdbadb90249b6f19e6a1205f57e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46247
Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/gpu-compute/gpu_compute_driver.cc
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 7f8cc16..12e537c 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -417,7 +417,7 @@
 TypedBufferArg args(ioc_buf);
 args.copyIn(virt_proxy);
 if (args->event_type != KFD_IOC_EVENT_SIGNAL) {
-fatal("Signal events are only supported currently\n");
+warn("Signal events are only supported currently\n");
 } else if (eventSlotIndex == SLOTS_PER_PAGE) {
 fatal("Signal event wasn't created; signal limit  
reached\n");

 }
@@ -508,8 +508,8 @@
 "\tamdkfd wait for event %d\n",  
EventData->event_id);

 panic_if(ETable.count(EventData->event_id) == 0,
  "Event ID invalid, cannot set this event\n");
-panic_if(ETable[EventData->event_id].threadWaiting,
- "Multiple threads waiting on the same event\n");
+if (ETable[EventData->event_id].threadWaiting)
+ warn("Multiple threads waiting on the same  
event\n");

 if (ETable[EventData->event_id].setEvent) {
 // If event is already set, the event has already  
happened.
 // Just unset the event and dont put this thread to  
sleep.




3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Branch: develop
Gerrit-Change-Id: Ie0052267f3ccfbdbadb90249b6f19e6a1205f57e
Gerrit-Change-Number: 46247
Gerrit-PatchSet: 8
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs,gpu-compute: Add render driver needed for ROCm 4

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46244 )


Change subject: configs,gpu-compute: Add render driver needed for ROCm 4
..

configs,gpu-compute: Add render driver needed for ROCm 4

ROCm 4 utilizes the render driver located at /dev/dri/renderDXXX. This
patch implements a very simple driver that just returns a file
descriptor when opened, as testing has shown that's all that's needed

Change-Id: I65602346cbf17b2dc80e114046ebf5c9830a1507
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46244
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Maintainer: Jason Lowe-Power 
Maintainer: Matt Sinclair 
---
M configs/example/apu_se.py
M configs/example/hsaTopology.py
M src/gpu-compute/GPU.py
M src/gpu-compute/SConscript
A src/gpu-compute/gpu_render_driver.cc
A src/gpu-compute/gpu_render_driver.hh
6 files changed, 124 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index f779df3..98a1e19 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -436,6 +436,9 @@
   gfxVersion = args.gfx_version,
   dGPUPoolID = 1, m_type = args.m_type)

+renderDriNum = 128
+render_driver = GPURenderDriver(filename = f'dri/renderD{renderDriNum}')
+
 # Creating the GPU kernel launching components: that is the HSA
 # packet processor (HSAPP), GPU command processor (CP), and the
 # dispatcher.
@@ -498,7 +501,8 @@
"HSA_ENABLE_SDMA=0"]

 process = Process(executable = executable, cmd = [args.cmd]
-  + args.options.split(), drivers = [gpu_driver], env =  
env)

+  + args.options.split(),
+  drivers = [gpu_driver, render_driver], env = env)

 for cpu in cpu_list:
 cpu.createThreads()
diff --git a/configs/example/hsaTopology.py b/configs/example/hsaTopology.py
index 78fe1f7..78193e0 100644
--- a/configs/example/hsaTopology.py
+++ b/configs/example/hsaTopology.py
@@ -156,6 +156,9 @@
 file_append((node_dir, 'gpu_id'), 22124)
 file_append((node_dir, 'name'), 'Vega\n')

+# Should be the same as the render driver filename  
(dri/renderD)

+drm_num = 128
+
 # 96 in real Vega
 # Random comment for comparison purposes
 caches = 0
@@ -200,7 +203,7 @@
 'vendor_id 4098\n'  + \
 'device_id 26720\n' + \
 'location_id 1024\n'+ \
-'drm_render_minor 128\n'+ \
+'drm_render_minor %s\n' % drm_num   + \
 'hive_id 0\n'   + \
 'num_sdma_engines 2\n'  + \
 'num_sdma_xgmi_engines 0\n' + \
@@ -329,6 +332,9 @@
 file_append((node_dir, 'gpu_id'), 50156)
 file_append((node_dir, 'name'), 'Fiji\n')

+# Should be the same as the render driver filename  
(dri/renderD)

+drm_num = 128
+
 # Real Fiji shows 96, but building that topology is complex and doesn't
 # appear to be required for anything.
 caches = 0
@@ -373,6 +379,7 @@
 'vendor_id  
4098\n'  + \
 'device_id  
29440\n' + \
 'location_id  
512\n' + \
+'drm_render_minor %s\n' %  
drm_num   + \
 'max_engine_clk_fcompute %s\n' 
\
 % int(toFrequency(options.gpu_clock) /  
1e6) + \
 'local_mem_size  
4294967296\n'   + \

@@ -424,6 +431,9 @@

 mem_banks_cnt = 1

+# Should be the same as the render driver filename  
(dri/renderD)

+drm_num = 128
+
 # populate global node properties
 # NOTE: SIMD count triggers a valid GPU agent creation
 node_prop = 'cpu_cores_count %s\n' %  
options.num_cpus   + \

@@ -446,6 +456,7 @@
 'vendor_id  
4098\n'  + \
 'device_id  
39028\n' + \
 'location_id  
8\n'   + \
+'drm_render_minor %s\n' %  
drm_num   + \
 'max_engine_clk_fcompute %s\n' 
\
 % int(toFrequency(options.gpu_clock) /  
1e6) + \
 'local_mem_size  
0\n'

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa,gpu-compute: IOCTL updates for ROCm 4

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46246 )


Change subject: dev-hsa,gpu-compute: IOCTL updates for ROCm 4
..

dev-hsa,gpu-compute: IOCTL updates for ROCm 4

This change copies over the up-to-date kfd_ioctl.h file from the linux
kernel, and updates the gpu_compute_driver to reflect the changes found
in the new version of the kfd_ioctl.h file

Change-Id: I51e8e7158762f4b7e06c0f84507e5889a17939a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46246
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/hsa/kfd_ioctl.h
M src/gpu-compute/gpu_compute_driver.cc
2 files changed, 310 insertions(+), 275 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/hsa/kfd_ioctl.h b/src/dev/hsa/kfd_ioctl.h
index 504621c..7099851 100644
--- a/src/dev/hsa/kfd_ioctl.h
+++ b/src/dev/hsa/kfd_ioctl.h
@@ -23,13 +23,16 @@
 #ifndef KFD_IOCTL_H_INCLUDED
 #define KFD_IOCTL_H_INCLUDED

+#include 
 #include 
 #include 

-#include 
-
+/*
+ * - 1.1 - initial version
+ * - 1.3 - Add SMI events support
+ */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 2
+#define KFD_IOCTL_MINOR_VERSION 3

 struct kfd_ioctl_get_version_args
 {
@@ -41,6 +44,7 @@
 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0
 #define KFD_IOC_QUEUE_TYPE_SDMA1
 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
+#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI3

 #define KFD_MAX_QUEUE_PERCENTAGE   100
 #define KFD_MAX_QUEUE_PRIORITY 15
@@ -89,6 +93,15 @@
uint64_t cu_mask_ptr;   /* to KFD */
 };

+struct kfd_ioctl_get_queue_wave_state_args
+{
+uint64_t ctl_stack_address; /* to KFD */
+uint32_t ctl_stack_used_size;   /* from KFD */
+uint32_t save_area_used_size;   /* from KFD */
+uint32_t queue_id;  /* to KFD */
+uint32_t pad;
+};
+
 /* For kfd_ioctl_set_memory_policy_args.default_policy and  
alternate_policy */

 #define KFD_IOC_CACHE_POLICY_COHERENT 0
 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
@@ -104,14 +117,6 @@
uint32_t pad;
 };

-struct kfd_ioctl_set_trap_handler_args
-{
-   uint64_t tba_addr;
-   uint64_t tma_addr;
-   uint32_t gpu_id;/* to KFD */
-   uint32_t pad;
-};
-
 /*
  * All counters are monotonic. They are used for profiling of compute jobs.
  * The profiling is done by userspace.
@@ -130,8 +135,6 @@
uint32_t pad;
 };

-#define NUM_OF_SUPPORTED_GPUS 7
-
 struct kfd_process_device_apertures
 {
uint64_t lds_base;  /* from KFD */
@@ -144,10 +147,12 @@
uint32_t pad;
 };

-/* This IOCTL and the limited NUM_OF_SUPPORTED_GPUS is deprecated. Use
- * kfd_ioctl_get_process_apertures_new instead, which supports
- * arbitrary numbers of GPUs.
+/*
+ * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
+ * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
+ * unlimited number of GPUs.
  */
+#define NUM_OF_SUPPORTED_GPUS 7
 struct kfd_ioctl_get_process_apertures_args
 {
struct kfd_process_device_apertures
@@ -217,14 +222,21 @@
 #define KFD_IOC_WAIT_RESULT_TIMEOUT1
 #define KFD_IOC_WAIT_RESULT_FAIL   2

-/*
- * The added 512 is because, currently, 8*(4096/256) signal events are
- * reserved for debugger events, and we want to provide at least 4K signal
- * events for EOP usage.
- * We add 512 to make the allocated size (KFD_SIGNAL_EVENT_LIMIT * 8) be
- * page aligned.
- */
-#define KFD_SIGNAL_EVENT_LIMIT (4096 + 512)
+#define KFD_SIGNAL_EVENT_LIMIT  4096
+
+/* For kfd_event_data.hw_exception_data.reset_type. */
+#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET0
+#define KFD_HW_EXCEPTION_PER_ENGINE_RESET   1
+
+/* For kfd_event_data.hw_exception_data.reset_cause. */
+#define KFD_HW_EXCEPTION_GPU_HANG   0
+#define KFD_HW_EXCEPTION_ECC1
+
+/* For kfd_hsa_memory_exception_data.ErrorType */
+#define KFD_MEM_ERR_NO_RAS  0
+#define KFD_MEM_ERR_SRAM_ECC1
+#define KFD_MEM_ERR_POISON_CONSUMED 2
+#define KFD_MEM_ERR_GPU_HANG3

 struct kfd_ioctl_create_event_args
 {
@@ -267,22 +279,38 @@
 /* memory exception data */
 struct kfd_hsa_memory_exception_data
 {
-   struct kfd_memory_exception_failure failure;
-   uint64_t va;
-   uint32_t gpu_id;
-   uint32_t pad;
+struct kfd_memory_exception_failure failure;
+uint64_t va;
+uint32_t gpu_id;
+uint32_t ErrorType; /* 0 = no RAS error,
+  * 1 = ECC_SRAM,
+  * 2 = Link_SYNFLOOD (poison),
+  * 3 = GPU hang(not attributable to a specific  
cause),

+  * other values reserved
+  */
+};
+
+/* hw exception data */
+struct

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Ignore GPU kernel names

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46245 )


Change subject: gpu-compute: Ignore GPU kernel names
..

gpu-compute: Ignore GPU kernel names

ROCm 4 seems to have updated the akc, and the only real issue that has
occured is that we're no longer able to read kernel names in the same
way as we were in ROCm 1.6. This patch removes the prior method of
reading kernel names and gives all kernels a temporary name

Change-Id: I0040e0cf4cd35d6f56ded6a8acfb10c600bcc77a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46245
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Matt Sinclair 
---
M src/gpu-compute/gpu_command_processor.cc
1 file changed, 1 insertion(+), 5 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_command_processor.cc  
b/src/gpu-compute/gpu_command_processor.cc

index 9bdd0b9..78b3235 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -171,7 +171,6 @@
 DPRINTF(GPUCommandProc, "Machine code starts at addr: %#x\n",
 machine_code_addr);

-Addr kern_name_addr(0);
 std::string kernel_name;

 /**
@@ -184,10 +183,7 @@
  * host memory.  I have no idea what BLIT stands for.
  * */
 if (akc.runtime_loader_kernel_symbol) {
-virt_proxy.readBlob(akc.runtime_loader_kernel_symbol + 0x10,
-(uint8_t*)_name_addr, 0x8);
-
-virt_proxy.readString(kernel_name, kern_name_addr);
+kernel_name = "Some kernel";
 } else {
 kernel_name = "Blit kernel";
 }



3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0040e0cf4cd35d6f56ded6a8acfb10c600bcc77a
Gerrit-Change-Number: 46245
Gerrit-PatchSet: 5
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: build with getdents64 if system supports it

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46242 )


Change subject: arch-x86: build with getdents64 if system supports it
..

arch-x86: build with getdents64 if system supports it

This patch makes it so the getdents64 syscall is built in gem5 if the
underlying host implements the syscall, similar to how the getdents
syscall is implemented.

The implementation for getdents64 already existed

Change-Id: I73b22c8df8df994f3f720e848a7d4f8cd31d318e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46242
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Reviewed-by: Alex Dutu 
Maintainer: Matt Sinclair 
---
M src/arch/x86/linux/syscall_tbl32.cc
M src/arch/x86/linux/syscall_tbl64.cc
2 files changed, 8 insertions(+), 0 deletions(-)

Approvals:
  Alex Dutu: Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass



diff --git a/src/arch/x86/linux/syscall_tbl32.cc  
b/src/arch/x86/linux/syscall_tbl32.cc

index 50d0969..db70151 100644
--- a/src/arch/x86/linux/syscall_tbl32.cc
+++ b/src/arch/x86/linux/syscall_tbl32.cc
@@ -261,7 +261,11 @@
 { 218, "mincore" },
 { 219, "madvise", ignoreFunc },
 { 220, "madvise1" },
+#if defined(SYS_getdents64)
+{ 221, "getdents64", getdents64Func },
+#else
 { 221, "getdents64" },
+#endif
 { 222, "fcntl64" },
 { 223, "unused" },
 { 224, "gettid", gettidFunc },
diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index be82437..94837cd 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -257,7 +257,11 @@
 { 214, "epoll_ctl_old" },
 { 215, "epoll_wait_old" },
 { 216, "remap_file_pages" },
+#if defined(SYS_getdents64)
+{ 217, "getdents64", getdents64Func },
+#else
 { 217, "getdents64" },
+#endif
 { 218, "set_tid_address", setTidAddressFunc },
 { 219, "restart_syscall" },
 { 220, "semtimedop" },



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I73b22c8df8df994f3f720e848a7d4f8cd31d318e
Gerrit-Change-Number: 46242
Gerrit-PatchSet: 5
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86,sim: Implement sched_getaffinity

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46243 )


Change subject: arch-x86,sim: Implement sched_getaffinity
..

arch-x86,sim: Implement sched_getaffinity

sched_getaffinity is different from other syscalls in the raw syscall
return the size of the cpumask being used to represent the CPU bit mask.

Because of this, when a library (libnuma in this case) directly called
sched_getaffinity and got a return value of 0, it errored out, thinking
that there were no CPUs available.

This implementation assumes that all CPUs are available, so it sets
all simulated CPUs in the bitmask

Change-Id: Id95c919986cc98a411877056256604f57a29f0f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46243
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/linux/syscall_tbl64.cc
M src/sim/syscall_emul.hh
2 files changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index 94837cd..7231595 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -244,7 +244,7 @@
 { 201, "time", timeFunc },
 { 202, "futex", futexFunc },
 { 203, "sched_setaffinity", ignoreFunc },
-{ 204, "sched_getaffinity", ignoreFunc },
+{ 204, "sched_getaffinity", schedGetaffinityFunc },
 { 205, "set_thread_area" },
 { 206, "io_setup" },
 { 207, "io_destroy" },
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index cd2d8d1..3c1ad04 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -57,6 +57,7 @@
 /// application on the host machine.

 #if defined(__linux__)
+#include 
 #include 
 #include 

@@ -2603,4 +2604,26 @@
 #endif
 }

+/// Target sched_getaffinity
+template 
+SyscallReturn
+schedGetaffinityFunc(SyscallDesc *desc, ThreadContext *tc,
+ pid_t pid, size_t cpusetsize, VPtr<> cpu_set_mask)
+{
+#if defined(__linux__)
+if (cpusetsize < CPU_ALLOC_SIZE(tc->getSystemPtr()->threads.size()))
+return -EINVAL;
+
+BufferArg maskBuf(cpu_set_mask, cpusetsize);
+maskBuf.copyIn(tc->getVirtProxy());
+for (int i = 0; i < tc->getSystemPtr()->threads.size(); i++) {
+CPU_SET(i, (cpu_set_t *)maskBuf.bufferPtr());
+}
+maskBuf.copyOut(tc->getVirtProxy());
+return CPU_ALLOC_SIZE(tc->getSystemPtr()->threads.size());
+#else
+warnUnsupportedOS("sched_getaffinity");
+return -1;
+#endif
+}
 #endif // __SIM_SYSCALL_EMUL_HH__



3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/46243
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id95c919986cc98a411877056256604f57a29f0f9
Gerrit-Change-Number: 46243
Gerrit-PatchSet: 5
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add mem_banks to Carrizo topology

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46240 )


Change subject: configs: Add mem_banks to Carrizo topology
..

configs: Add mem_banks to Carrizo topology

ROCm 4 iterates through the mem_banks to find an appropriate place to
allocate memory. Previously, Carrizo didn't have any mem_banks, which
resulted in the ROCm 4 runtime erroring out, as it didn't know where to
allocate memory.

The implementation is fairly similar to the implementation used for the
Fiji or Vega configs

Change-Id: I5bb4e89657d44c6cb690fd224ee1bf1d4d6cf2a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46240
Tested-by: kokoro 
Reviewed-by: Matthew Poremba 
Reviewed-by: Matt Sinclair 
Reviewed-by: Bobby R. Bruce 
Maintainer: Matt Sinclair 
---
M configs/example/hsaTopology.py
1 file changed, 15 insertions(+), 2 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Bobby R. Bruce: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/configs/example/hsaTopology.py b/configs/example/hsaTopology.py
index 51585de..78fe1f7 100644
--- a/configs/example/hsaTopology.py
+++ b/configs/example/hsaTopology.py
@@ -36,7 +36,7 @@
 from os.path import join as joinpath
 from os.path import isdir
 from shutil import rmtree, copyfile
-from m5.util.convert import toFrequency
+from m5.util.convert import toFrequency, toMemorySize

 def file_append(path, contents):
 with open(joinpath(*path), 'a') as f:
@@ -422,12 +422,14 @@
 # must have marketing name
 file_append((node_dir, 'name'), 'Carrizo\n')

+mem_banks_cnt = 1
+
 # populate global node properties
 # NOTE: SIMD count triggers a valid GPU agent creation
 node_prop = 'cpu_cores_count %s\n' %  
options.num_cpus   + \
 'simd_count %s\n'  
\
 % (options.num_compute_units *  
options.simds_per_cu)+ \
-'mem_banks_count  
0\n'   + \
+'mem_banks_count %s\n' %  
mem_banks_cnt  + \
 'caches_count  
0\n'  + \
 'io_links_count  
0\n'+ \
 'cpu_core_id_base  
16\n' + \

@@ -453,3 +455,14 @@
 % int(toFrequency(options.CPUClock) / 1e6)

 file_append((node_dir, 'properties'), node_prop)
+
+for i in range(mem_banks_cnt):
+mem_dir = joinpath(node_dir, f'mem_banks/{i}')
+remake_dir(mem_dir)
+
+mem_prop = f'heap_type  
0\n' + \
+   f'size_in_bytes  
{toMemorySize(options.mem_size)}'+ \
+   f'flags  
0\n' + \
+   f'width  
64\n'+ \

+   f'mem_clk_max 1600\n'
+file_append((mem_dir, 'properties'), mem_prop)



2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5bb4e89657d44c6cb690fd224ee1bf1d4d6cf2a5
Gerrit-Change-Number: 46240
Gerrit-PatchSet: 4
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Ignore certain syscalls called in ROCm 4

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46241 )


Change subject: arch-x86: Ignore certain syscalls called in ROCm 4
..

arch-x86: Ignore certain syscalls called in ROCm 4

fdatasync, sigaltstack, and prctl are called by the ROCm 4 stack, but
were unimplemented. Based on testing, we can change these to ignoreFunc
without affecting program correctness.

sched_yield gets changed to ignoreWarnOnceFunc, as it gets called
significantly more in ROCm 4.

Change-Id: I566b1d71d989c54bfc559d5b83790dff73a38b28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46241
Tested-by: kokoro 
Maintainer: Matt Sinclair 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
---
M src/arch/x86/linux/syscall_tbl64.cc
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/linux/syscall_tbl64.cc  
b/src/arch/x86/linux/syscall_tbl64.cc

index 8630265..be82437 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -60,7 +60,7 @@
 {  21, "access", ignoreFunc },
 {  22, "pipe", pipeFunc },
 {  23, "select", selectFunc },
-{  24, "sched_yield", ignoreFunc },
+{  24, "sched_yield", ignoreWarnOnceFunc },
 {  25, "mremap", mremapFunc },
 {  26, "msync" },
 {  27, "mincore" },
@@ -111,7 +111,7 @@
 {  72, "fcntl", fcntlFunc },
 {  73, "flock" },
 {  74, "fsync" },
-{  75, "fdatasync" },
+{  75, "fdatasync", ignoreFunc },
 {  76, "truncate", truncateFunc },
 {  77, "ftruncate", ftruncateFunc },
 #if defined(SYS_getdents)
@@ -171,7 +171,7 @@
 { 128, "rt_sigtimedwait" },
 { 129, "rt_sigqueueinfo" },
 { 130, "rt_sigsuspend" },
-{ 131, "sigaltstack" },
+{ 131, "sigaltstack", ignoreFunc },
 { 132, "utime" },
 { 133, "mknod", mknodFunc },
 { 134, "uselib" },
@@ -197,7 +197,7 @@
 { 154, "modify_ldt" },
 { 155, "pivot_root" },
 { 156, "_sysctl" },
-{ 157, "prctl" },
+{ 157, "prctl", ignoreFunc },
 { 158, "arch_prctl", archPrctlFunc },
 { 159, "adjtimex" },
 { 160, "setrlimit", ignoreFunc },



3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I566b1d71d989c54bfc559d5b83790dff73a38b28
Gerrit-Change-Number: 46241
Gerrit-PatchSet: 5
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Initialize GPUDriver member variables before use

2021-06-30 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46248 )


Change subject: gpu-compute: Initialize GPUDriver member variables before  
use

..

gpu-compute: Initialize GPUDriver member variables before use

A few member variables weren't initialized, but we were assuming that
they were 0 when first read. This explicitly sets those variables to 0.

Change-Id: I2c840d361ed3a7d306e22dc7561a3870f1ef94a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46248
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/gpu-compute/gpu_compute_driver.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 12e537c..02f1de5 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -53,7 +53,8 @@

 GPUComputeDriver::GPUComputeDriver(const Params )
 : EmulatedDriver(p), device(p.device), queueId(0),
-  isdGPU(p.isdGPU), gfxVersion(p.gfxVersion), dGPUPoolID(p.dGPUPoolID)
+  isdGPU(p.isdGPU), gfxVersion(p.gfxVersion), dGPUPoolID(p.dGPUPoolID),
+  eventPage(0), eventSlotIndex(0)
 {
 device->attachDriver(this);
 DPRINTF(GPUDriver, "Constructing KFD: device\n");



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c840d361ed3a7d306e22dc7561a3870f1ef94a1
Gerrit-Change-Number: 46248
Gerrit-PatchSet: 8
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix waiting on remote debugger

2021-06-30 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47360 )


Change subject: configs: Fix waiting on remote debugger
..

configs: Fix waiting on remote debugger

Commit 2c75e58cac ("sim,cpu: Move the remote GDB stub
into the workload.") moved "wait_for_remote_gdb" to the
Workload class. That breaks se.py since it continues to
rely on that being a property of BaseCPU. This ensures
that the property is now set via the current Workload
instance instead.

Also, owing to its boolean nature, the argument should
ideally not expect any additional values. Hence, it is
associated with the "store_true" action.

Change-Id: I4a00b29d283df36ebf833c9125651cd6deb52a4f
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47360
Reviewed-by: Boris Shingarov 
Maintainer: Boris Shingarov 
Tested-by: kokoro 
---
M configs/common/Options.py
M configs/example/se.py
2 files changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/Options.py b/configs/common/Options.py
index 75c60a8..31ac120 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -455,7 +455,7 @@
 "to be used in syscall emulation."
 "Usage: gem5.opt [...] --redirects /dir1=/path/"
 "to/host/dir1 --redirects  
/dir2=/path/to/host/dir2")

-parser.add_argument("--wait-gdb", default=False,
+parser.add_argument("--wait-gdb", default=False, action='store_true',
 help="Wait for remote GDB to connect.")


diff --git a/configs/example/se.py b/configs/example/se.py
index 65acf6a..7b161e1 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -264,8 +264,7 @@
 system.workload = SEWorkload.init_compatible(mp0_path)

 if args.wait_gdb:
-for cpu in system.cpu:
-cpu.wait_for_remote_gdb = True
+system.workload.wait_for_remote_gdb = True

 root = Root(full_system = False, system = system)
 Simulation.run(args, root, system, FutureClass)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a00b29d283df36ebf833c9125651cd6deb52a4f
Gerrit-Change-Number: 47360
Gerrit-PatchSet: 3
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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