[gem5-dev] Change in gem5/gem5[develop]: base: Fix ListenSocket binding logic
Jui-min Lee has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55943 )
Change subject: base: Fix ListenSocket binding logic
..
base: Fix ListenSocket binding logic
The original implementation does not cleanup the socket after it failed
to listen. However, the API doesn't give our user a way to bypass the
bind part and the next try will always break at the bind call.
Furthermore, the next failure will be EINVAL instead of EADDRINUSE so
gem5 will just abort without giving any meaningful message.
In this CL we cleanup the socket if we failed to invoke listen, so the
user can retry with a clean state and even retry on another port.
Test: Try to launch two gem5 that both bind to gdb port (7000) and
repeat it for 100 times.
Change-Id: I7272ea3c3b6ab56e4b904f3a3a45ed389d00dd05
---
M src/base/socket.cc
1 file changed, 49 insertions(+), 21 deletions(-)
diff --git a/src/base/socket.cc b/src/base/socket.cc
index 860249a..7a3a721 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -138,30 +138,38 @@
panic("ListenSocket(listen): setsockopt() SO_REUSEADDR
failed!");
}
-struct sockaddr_in sockaddr;
-sockaddr.sin_family = PF_INET;
-sockaddr.sin_addr.s_addr =
-htobe(bindToLoopback ? INADDR_LOOPBACK : INADDR_ANY);
-sockaddr.sin_port = htons(port);
-// finally clear sin_zero
-std::memset(_zero, 0, sizeof(sockaddr.sin_zero));
-int ret = ::bind(fd, (struct sockaddr *), sizeof (sockaddr));
-if (ret != 0) {
-if (ret == -1 && errno != EADDRINUSE)
-panic("ListenSocket(listen): bind() failed!");
-return false;
-}
+do {
+struct sockaddr_in sockaddr;
+sockaddr.sin_family = PF_INET;
+sockaddr.sin_addr.s_addr =
+htobe(bindToLoopback ? INADDR_LOOPBACK :
INADDR_ANY);
+sockaddr.sin_port = htons(port);
+// finally clear sin_zero
+std::memset(_zero, 0, sizeof(sockaddr.sin_zero));
+int ret = ::bind(fd, (struct sockaddr *), sizeof
(sockaddr));
+if (ret != 0) {
+if (ret == -1 && errno != EADDRINUSE)
+panic("ListenSocket(listen): bind() failed!");
+break;
+}
-if (::listen(fd, 1) == -1) {
-if (errno != EADDRINUSE)
-panic("ListenSocket(listen): listen() failed!");
+if (::listen(fd, 1) == -1) {
+if (errno != EADDRINUSE)
+panic("ListenSocket(listen): listen() failed!");
-return false;
-}
+break;
+}
-listening = true;
-anyListening = true;
-return true;
+listening = true;
+anyListening = true;
+return true;
+} while(false);
+
+// If we reach here, something must have gone wrong while binding
socket.
+// We'll close the socket so our user can retry from a cleaner state.
+close(fd);
+fd = -1;
+return false;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7272ea3c3b6ab56e4b904f3a3a45ed389d00dd05
Gerrit-Change-Number: 55943
Gerrit-PatchSet: 1
Gerrit-Owner: Jui-min Lee
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev: Clean up the IDE disk and controller classes a little.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55583 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev: Clean up the IDE disk and controller classes a
little.
..
dev: Clean up the IDE disk and controller classes a little.
Fix some style issues, and replace some if () panics with panic_ifs.
Change-Id: Ic4fae016520e43d32f435bf3fc0ec37df25ca02a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55583
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
3 files changed, 56 insertions(+), 40 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 7d4ecac..701314f 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -50,10 +50,6 @@
#include "params/IdeController.hh"
#include "sim/byteswap.hh"
-// clang complains about std::set being overloaded with Packet::set if
-// we open up the entire namespace std
-using std::string;
-
namespace gem5
{
@@ -65,7 +61,7 @@
BMIDescTablePtr = 0x4
};
-IdeController::Channel::Channel(string newName) : _name(newName)
+IdeController::Channel::Channel(std::string newName) : _name(newName)
{
bmiRegs.reset();
bmiRegs.status.dmaCap0 = 1;
@@ -287,8 +283,8 @@
newVal.intStatus = 0; // clear the interrupt?
} else {
// Assigning two bitunion fields to each other does not
-// work as intended, so we need to use this temporary
variable
-// to get around the bug.
+// work as intended, so we need to use this temporary
+// variable to get around the bug.
uint8_t tmp = oldVal.intStatus;
newVal.intStatus = tmp;
}
@@ -309,8 +305,9 @@
break;
default:
if (size != sizeof(uint8_t) && size != sizeof(uint16_t) &&
-size != sizeof(uint32_t))
-panic("IDE controller write of invalid write size: %x\n",
size);
+size != sizeof(uint32_t)) {
+panic("IDE controller write of invalid size: %x\n", size);
+}
memcpy((uint8_t *) + offset, data, size);
}
}
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index a7185e4..a5e52b0 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -538,8 +538,9 @@
void
IdeDisk::dmaWriteDone()
{
-DPRINTF(IdeDisk, "doWriteDone: curPrd byte count %d, eot %#x cmd bytes
left:%d\n",
-curPrd.getByteCount(), curPrd.getEOT(), cmdBytesLeft);
+DPRINTF(IdeDisk,
+"doWriteDone: curPrd byte count %d, eot %#x cmd bytes
left:%d\n",
+curPrd.getByteCount(), curPrd.getEOT(), cmdBytesLeft);
// check for the EOT
if (curPrd.getEOT()) {
assert(cmdBytesLeft == 0);
@@ -559,9 +560,9 @@
{
uint32_t bytesRead = image->read(data, sector);
-if (bytesRead != SectorSize)
-panic("Can't read from %s. Only %d of %d read. errno=%d\n",
- name(), bytesRead, SectorSize, errno);
+panic_if(bytesRead != SectorSize,
+"Can't read from %s. Only %d of %d read. errno=%d",
+name(), bytesRead, SectorSize, errno);
}
void
@@ -569,9 +570,9 @@
{
uint32_t bytesWritten = image->write(data, sector);
-if (bytesWritten != SectorSize)
-panic("Can't write to %s. Only %d of %d written. errno=%d\n",
- name(), bytesWritten, SectorSize, errno);
+panic_if(bytesWritten != SectorSize,
+"Can't write to %s. Only %d of %d written. errno=%d",
+name(), bytesWritten, SectorSize, errno);
}
@@ -581,11 +582,11 @@
void
IdeDisk::startDma(const uint32_t )
{
-if (dmaState != Dma_Start)
-panic("Inconsistent DMA state, should be in Dma_Start!\n");
+panic_if(dmaState != Dma_Start,
+"Inconsistent DMA state, should be in Dma_Start!");
-if (devState != Transfer_Data_Dma)
-panic("Inconsistent device state for DMA start!\n");
+panic_if(devState != Transfer_Data_Dma,
+"Inconsistent device state for DMA start!");
// PRD base address is given by bits 31:2
curPrdAddr = pciToDma((Addr)(prdTableBase & ~0x3ULL));
@@ -599,11 +600,11 @@
void
IdeDisk::abortDma()
{
-if (dmaState == Dma_Idle)
-panic("Inconsistent DMA state, should be Start or Transfer!");
+panic_if(dmaState == Dma_Idle,
+"Inconsistent DMA state, should be Start or Transfer!");
-
[gem5-dev] Change in gem5/gem5[develop]: arch-arm,cpu: Add a class for ops for vec reg elements.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49163 )
Change subject: arch-arm,cpu: Add a class for ops for vec reg elements.
..
arch-arm,cpu: Add a class for ops for vec reg elements.
This lets a caller print the name of a register in a friendly way
without having to know how many elements go with each vector register.
Change-Id: I85598c078c604f1bebdba797308102482639c209
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49163
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa.cc
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
3 files changed, 41 insertions(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ed3bea2..5c8c743 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -80,6 +80,8 @@
}
} miscRegClassOps;
+VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg);
+
ISA::ISA(const Params ) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
@@ -87,7 +89,8 @@
_regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
_regClasses.emplace_back(0);
_regClasses.emplace_back(NumVecRegs);
-_regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
+_regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
+vecRegElemClassOps);
_regClasses.emplace_back(NumVecPredRegs);
_regClasses.emplace_back(NUM_CCREGS);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index fc39e42..b667838 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -50,6 +50,14 @@
return csprintf("r%d", id.index());
}
+std::string
+VecElemRegClassOps::regName(const RegId ) const
+{
+RegIndex reg_idx = id.index() / elemsPerVec;
+RegIndex elem_idx = id.index() % elemsPerVec;
+return csprintf("v%d[%d]", reg_idx, elem_idx);
+}
+
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 3c3a656..da6be67 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -79,6 +79,19 @@
std::string regName(const RegId ) const override;
};
+class VecElemRegClassOps : public RegClassOps
+{
+ protected:
+size_t elemsPerVec;
+
+ public:
+explicit VecElemRegClassOps(size_t elems_per_vec) :
+elemsPerVec(elems_per_vec)
+{}
+
+std::string regName(const RegId ) const override;
+};
+
class RegClass
{
private:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49163
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I85598c078c604f1bebdba797308102482639c209
Gerrit-Change-Number: 49163
Gerrit-PatchSet: 37
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: refactored SimpleNetwork routing
Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41858 )
Change subject: mem-ruby: refactored SimpleNetwork routing
..
mem-ruby: refactored SimpleNetwork routing
The routing algorithm is encapsulated in a separate SimObject to allow
user to implement different routing strategies. The default
implementation (WeightBased) maintains the original behavior.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I5c8927f358b8b04b2da55e59679c2f629c7cd2f9
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41858
Reviewed-by: Meatboy 106
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/TypeDefines.hh
M src/mem/ruby/network/Topology.hh
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SConscript
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.hh
M src/mem/ruby/network/simple/SimpleNetwork.py
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
A src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
A src/mem/ruby/network/simple/routing/WeightBased.cc
A src/mem/ruby/network/simple/routing/WeightBased.hh
13 files changed, 417 insertions(+), 105 deletions(-)
Approvals:
Meatboy 106: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/TypeDefines.hh
b/src/mem/ruby/common/TypeDefines.hh
index 8f877be..8cc3e91 100644
--- a/src/mem/ruby/common/TypeDefines.hh
+++ b/src/mem/ruby/common/TypeDefines.hh
@@ -30,6 +30,8 @@
#ifndef __MEM_RUBY_COMMON_TYPEDEFINES_HH__
#define __MEM_RUBY_COMMON_TYPEDEFINES_HH__
+#include
+
namespace gem5
{
@@ -39,6 +41,7 @@
typedef unsigned int LinkID;
typedef unsigned int NodeID;
typedef unsigned int SwitchID;
+typedef std::string PortDirection;
} // namespace ruby
} // namespace gem5
diff --git a/src/mem/ruby/network/Topology.hh
b/src/mem/ruby/network/Topology.hh
index 5ce654f..301811e 100644
--- a/src/mem/ruby/network/Topology.hh
+++ b/src/mem/ruby/network/Topology.hh
@@ -42,7 +42,6 @@
#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
#include
-#include
#include
#include "mem/ruby/common/TypeDefines.hh"
@@ -65,7 +64,6 @@
* represent the source ID, destination ID, and vnet number.
*/
typedef std::vector>> Matrix;
-typedef std::string PortDirection;
struct LinkEntry
{
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 4df3fcf..154e491 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -59,13 +59,6 @@
const int PRIORITY_SWITCH_LIMIT = 128;
-// Operator for helper class
-bool
-operator<(const LinkOrder& l1, const LinkOrder& l2)
-{
-return (l1.m_value < l2.m_value);
-}
-
PerfectSwitch::PerfectSwitch(SwitchID sid, Switch *sw, uint32_t virt_nets)
: Consumer(sw, Switch::PERFECTSWITCH_EV_PRI),
m_switch_id(sid), m_switch(sw)
@@ -101,17 +94,15 @@
void
PerfectSwitch::addOutPort(const std::vector& out,
- const NetDest& routing_table_entry)
+ const NetDest& routing_table_entry,
+ const PortDirection _inport)
{
-// Setup link order
-LinkOrder l;
-l.m_value = 0;
-l.m_link = m_out.size();
-m_link_order.push_back(l);
-
-// Add to routing table
+// Add to routing unit
+m_switch->getRoutingUnit().addOutPort(m_out.size(),
+ out,
+ routing_table_entry,
+ dst_inport);
m_out.push_back(out);
-m_routing_table.push_back(routing_table_entry);
}
PerfectSwitch::~PerfectSwitch()
@@ -167,8 +158,8 @@
Message *net_msg_ptr = NULL;
// temporary vectors to store the routing results
-std::vector output_links;
-std::vector output_link_destinations;
+static thread_local std::vector
output_links;
+
Tick current_time = m_switch->clockEdge();
while (buffer->isReady(current_time)) {
@@ -179,72 +170,16 @@
net_msg_ptr = msg_ptr.get();
DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr));
+
output_links.clear();
-output_link_destinations.clear();
-NetDest msg_dsts = net_msg_ptr->getDestination();
-
-// Unfortunately, the token-protocol sends some
-// zero-destination messages, so this assert isn't valid
-// assert(msg_dsts.count() > 0);
-
-assert(m_link_order.size() == m_routing_table.size());
-assert(m_link_order.size() == m_out.size());
-
-if (m_network_ptr->getAdaptiveRouting()) {
-if (m_network_ptr->isVNetOrdered(vnet)) {
-// Don't adaptively route
-
[gem5-dev] Change in gem5/gem5[develop]: scons: protobuf scanner for EXTRAS
Adrian Herrera has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55903 ) Change subject: scons: protobuf scanner for EXTRAS .. scons: protobuf scanner for EXTRAS This solves the following issue: - An EXTRAS directory "dir" contains a subdirectory "proto" with multiple .proto files. Some .proto files import other .proto files within "proto". - "proto" contains a SConscript file loading the files through the ProtoBuf function. - When SCons runs, it creates "dir/proto" under the $BUILDDIR directory. - The protoc_scanner scans the .proto files under "dir/proto". Each "import a.proto" statement results in an implicit dependency "$BUILDDIR/a.proto", which does not exist, causing a build failure. The correct implicit dependency should be "$BUILDDIR/dir/proto/a.proto". To fix this, we use the Classic scanner from SCons, which also considers the source directory of the .proto file that imports when looking for dependencies. Regex management is also delegated to the Classic scanner. Note: this still allows the use of paths relative to $BUILDDIR in import statements by passing the BUILDDIR as a path_variable. Change-Id: I1ad466813ef44947f3da07371805cb6376e392f0 Signed-off-by: Adrián Herrera Arcila --- M src/SConscript 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/src/SConscript b/src/SConscript index 61585ec..e5b032c 100644 --- a/src/SConscript +++ b/src/SConscript @@ -229,15 +229,11 @@ # no whitespace at the end before or after the ;, and is all on one line. This # should still cover most cases, and a completely accurate scanner would be # MUCH more complex. -protoc_import_re = re.compile(r'^import\s+\"(.*\.proto)\"\;$', re.M) - -def protoc_scanner(node, env, path): -deps = [] -for imp in protoc_import_re.findall(node.get_text_contents()): -deps.append(Dir(env['BUILDDIR']).File(imp)) -return deps - -env.Append(SCANNERS=Scanner(function=protoc_scanner, skeys=['.proto'])) +protoc_scanner = SCons.Scanner.Classic(name='ProtobufScanner', + suffixes=['.proto'], + path_variable='BUILDDIR', + regex=r'^import\s+\"(.*\.proto)\"\;$') +env.Append(SCANNERS=protoc_scanner) def protoc_emitter(target, source, env): root, ext = os.path.splitext(source[0].get_abspath()) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55903 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I1ad466813ef44947f3da07371805cb6376e392f0 Gerrit-Change-Number: 55903 Gerrit-PatchSet: 1 Gerrit-Owner: Adrian Herrera Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: For fun x86 bare metal CLs
Cool! Thanks for the updates. Steve On Mon, Jan 24, 2022 at 6:45 AM Gabe Black via gem5-dev wrote: > BTW, I've started trying to get this test program to run to flush out bugs > in our pre-64bit x86 support. It's been very helpful and usable, and I'm > hoping once I get it working (or at least mostly working :-) we can add it > as a regression. > > https://github.innominds.com/barotto/test386.asm > > Gabe > > On Tue, Jan 18, 2022 at 9:04 PM Gabe Black wrote: > >> It seems slow, and I had to fix a bug in SeaBIOS, but it seems to run :-) >> No video currently, since I haven't written a VGA device yet. >> >> Gabe >> >> On Tue, Jan 18, 2022 at 9:03 PM Gabe Black wrote: >> >>> HimemX 3.34 [Sep 05 2015] (c) 1995, Till Gerken 2001-2006 Tom Ehlert >>> Always on A20 method used >>> Kernel: allocated 45 Diskbuffers = 23940 Bytes in HMA >>> >>> FreeCom version 0.84-pre2 XMS_Swap [Aug 28 2006 00:29:00] >>> >>> Done processing startup files C:\FDCONFIG.SYS and C:\AUTOEXEC.BAT >>> >>> Type HELP to get support on commands and navigation. >>> >>> Welcome to the FreeDOS 1.2 operating system (http://www.freedos.org) >>> >>> C:\>dir >>> Volume in drive C is FREEDOS2016 >>> Volume Serial Number is 104F-0FE7 >>> Directory of C:\ >>> >>> FDOS 02-11-2018 8:05a >>> AUTOEXEC BAT 1,319 02-11-2018 8:14a >>> COMMAND COM66,945 08-28-2006 10:38p >>> FDCONFIG SYS 762 02-11-2018 8:14a >>> KERNEL SYS46,685 05-11-2016 9:42p >>> 4 file(s)115,711 bytes >>> 1 dir(s) 311,771,136 bytes free >>> C:\> >>> >>> On Sun, Jan 9, 2022 at 9:39 PM Gabe Black wrote: >>> Hey folks, I've wanted to try to get a bare metal x86 config going for a long time, since I thought it would be fun to play some old DOS games from my childhood on gem5. To that end, I decided to try to get SeaBIOS, a free implementation of a PC BIOS, to run there. While I haven't gotten that to totally work yet, and I don't want to call for special attention for something I'm just doing for fun, I have found about a dozen general x86 bugs/missing features which I've been fixing up in this CL chain. https://gem5-review.googlesource.com/c/public/gem5/+/55249 PTAL if you're curious about the DOS config, and also to review the actual fixes so that we can get those checked in. Gabe >>> ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: For fun x86 bare metal CLs
BTW, I've started trying to get this test program to run to flush out bugs in our pre-64bit x86 support. It's been very helpful and usable, and I'm hoping once I get it working (or at least mostly working :-) we can add it as a regression. https://github.innominds.com/barotto/test386.asm Gabe On Tue, Jan 18, 2022 at 9:04 PM Gabe Black wrote: > It seems slow, and I had to fix a bug in SeaBIOS, but it seems to run :-) > No video currently, since I haven't written a VGA device yet. > > Gabe > > On Tue, Jan 18, 2022 at 9:03 PM Gabe Black wrote: > >> HimemX 3.34 [Sep 05 2015] (c) 1995, Till Gerken 2001-2006 Tom Ehlert >> Always on A20 method used >> Kernel: allocated 45 Diskbuffers = 23940 Bytes in HMA >> >> FreeCom version 0.84-pre2 XMS_Swap [Aug 28 2006 00:29:00] >> >> Done processing startup files C:\FDCONFIG.SYS and C:\AUTOEXEC.BAT >> >> Type HELP to get support on commands and navigation. >> >> Welcome to the FreeDOS 1.2 operating system (http://www.freedos.org) >> >> C:\>dir >> Volume in drive C is FREEDOS2016 >> Volume Serial Number is 104F-0FE7 >> Directory of C:\ >> >> FDOS 02-11-2018 8:05a >> AUTOEXEC BAT 1,319 02-11-2018 8:14a >> COMMAND COM66,945 08-28-2006 10:38p >> FDCONFIG SYS 762 02-11-2018 8:14a >> KERNEL SYS46,685 05-11-2016 9:42p >> 4 file(s)115,711 bytes >> 1 dir(s) 311,771,136 bytes free >> C:\> >> >> On Sun, Jan 9, 2022 at 9:39 PM Gabe Black wrote: >> >>> Hey folks, I've wanted to try to get a bare metal x86 config going for a >>> long time, since I thought it would be fun to play some old DOS games from >>> my childhood on gem5. To that end, I decided to try to get SeaBIOS, a free >>> implementation of a PC BIOS, to run there. >>> >>> While I haven't gotten that to totally work yet, and I don't want to >>> call for special attention for something I'm just doing for fun, I have >>> found about a dozen general x86 bugs/missing features which I've been >>> fixing up in this CL chain. >>> >>> https://gem5-review.googlesource.com/c/public/gem5/+/55249 >>> >>> PTAL if you're curious about the DOS config, and also to review the >>> actual fixes so that we can get those checked in. >>> >>> Gabe >>> >> ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add some missing checks to STI and CLI.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55892 )
Change subject: arch-x86: Add some missing checks to STI and CLI.
..
arch-x86: Add some missing checks to STI and CLI.
Also make sure those instructions won't truncate the flags register.
Change-Id: Id55a4454480cd20ca462c08b93043254a9962dfe
---
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
2 files changed, 123 insertions(+), 21 deletions(-)
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 40beeb7..6dc9311 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -611,10 +611,12 @@
0x1: STC();
0x2: decode MODE_SUBMODE {
0x3: CLI_VIRT();
+0x4: CLI_REAL();
default: CLI();
}
0x3: decode MODE_SUBMODE {
0x3: STI_VIRT();
+0x4: STI_REAL();
default: STI();
}
0x4: CLD();
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
index 63b37bb..2f2b2ce 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
@@ -35,41 +35,89 @@
microcode = '''
def macroop CLD {
-ruflags t1
+ruflags t1, dataSize=8
limm t2, "~((uint64_t)DFBit)", dataSize=8
-and t1, t1, t2
-wruflags t1, t0
+and t1, t1, t2, dataSize=8
+wruflags t1, t0, dataSize=8
};
def macroop STD {
-ruflags t1
+ruflags t1, dataSize=8
limm t2, "DFBit", dataSize=8
-or t1, t1, t2
-wruflags t1, t0
+or t1, t1, t2, dataSize=8
+wruflags t1, t0, dataSize=8
};
def macroop CLC {
-ruflags t1
-andi t2, t1, "CFBit"
-wruflags t1, t2
+ruflags t1, dataSize=8
+limm t2, "~((uint64_t)CFBit)", dataSize=8
+and t1, t1, t2, dataSize=8
+wruflags t1, t0, dataSize=8
};
def macroop STC {
-ruflags t1
-ori t1, t1, "CFBit"
-wruflags t1, t0
+ruflags t1, dataSize=8
+ori t1, t1, "CFBit", dataSize=8
+wruflags t1, t0, dataSize=8
};
def macroop CMC {
-ruflags t1
-wruflagsi t1, "CFBit"
+ruflags t1, dataSize=8
+wruflagsi t1, "CFBit", dataSize=8
};
def macroop STI {
-rflags t1
+rflags t1, dataSize=8
+
+# Extract the IOPL.
+srli t2, t1, 12, dataSize=8
+andi t2, t1, 0x3, dataSize=8
+
+# Find the CPL.
+rdm5reg t3, dataSize=8
+srli t3, t3, 4, dataSize=8
+andi t3, t3, 0x3, dataSize=8
+
+# if !(CPL > IOPL), jump down to setting IF.
+sub t0, t2, t3, flags=(ECF,), dataSize=8
+br label("setIf"), flags=(nCECF,)
+
+# if (CR4.PVI == 1 && CPL == 3) {
+# } else GP
+
+# Check CR4.PVI
+rdcr t4, cr4, dataSize=8
+andi t0, t4, 0x1, flags=(CEZF,)
+fault "std::make_shared(0)", flags=(CEZF,)
+
+# Check CPL.
+andi t4, t3, 0x3, dataSize=8
+xori t4, t4, 0x3, dataSize=8, flags=(CEZF,)
+fault "std::make_shared(0)", flags=(nCEZF,)
+
+# if (RFLAGS.VIP == 1)
+# EXCEPTION[#GP(0)]
+
+# Check RFLAGS.VIP == 1
+rflag t0, "VIPBit"
+fault "std::make_shared(0)", flags=(nCEZF,)
+
+limm t2, "VIFBit", dataSize=8
+br label("setBitInT2")
+
+setIf:
limm t2, "IFBit", dataSize=8
-or t1, t1, t2
-wrflags t1, t0
+
+setBitInT2:
+or t1, t1, t2, dataSize=8
+wrflags t1, t0, dataSize=8
+};
+
+def macroop STI_REAL {
+rflags t1, dataSize=8
+limm t2, "IFBit", dataSize=8
+or t1, t1, t2, dataSize=8
+wrflags t1, t0, dataSize=8
};
def macroop STI_VIRT {
@@ -77,10 +125,51 @@
};
def macroop CLI {
-rflags t1
-limm t2, "~IFBit", dataSize=8
-and t1, t1, t2
-wrflags t1, t0
+rflags t1, dataSize=8
+
+# Extract the IOPL.
+srli t2, t1, 12, dataSize=8
+andi t2, t1, 0x3, dataSize=8
+
+# Find the CPL.
+rdm5reg t3, dataSize=8
+srli t3, t3, 4, dataSize=8
+andi t3, t3, 0x3, dataSize=8
+
+# if !(CPL > IOPL), jump down to clearing IF.
+sub t0, t2, t3, flags=(ECF,), dataSize=8
+br label("maskIf"), flags=(nCECF,)
+
+# if (CR4.PVI == 1 && CPL == 3) {
+# } else GP
+
+# Check CR4.PVI
+rdcr t4, cr4, dataSize=8
+andi t0, t4, 0x1, flags=(CEZF,)
+fault "std::make_shared(0)", flags=(CEZF,)
+
+# Check CPL.
+andi t4, t3, 0x3, dataSize=8
+xori t4, t4, 0x3, dataSize=8, flags=(CEZF,)
+fault "std::make_shared(0)", flags=(nCEZF,)
+
+# RFLAGS.VIF = 0
+limm t2, "~((uint64_t)VIFBit)", dataSize=8
+br label("maskWithT2")
+
+maskIf:
+limm t2, "~((uint64_t)IFBit)", dataSize=8
+
+maskWithT2:
+and t1, t1, t2, dataSize=8
+wrflags t1, t0, dataSize=8
+};
+
+def macroop
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add some formats for CPL0 only instructions.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55890 )
Change subject: arch-x86: Add some formats for CPL0 only instructions.
..
arch-x86: Add some formats for CPL0 only instructions.
These are essentially the same as the Inst and CondInst formats, except
it adds a CPL check. If the CPL check fails, a new instruction will be
returned which is only a vehicle for delivering a GP fault.
Change-Id: Ie1e7fb6a6c04082437c4d4a25adc3e03be09ac72
---
M src/arch/x86/isa/formats/cond.isa
M src/arch/x86/isa/formats/multi.isa
M src/arch/x86/isa/includes.isa
A src/arch/x86/insts/decode_fault.hh
4 files changed, 128 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/insts/decode_fault.hh
b/src/arch/x86/insts/decode_fault.hh
new file mode 100644
index 000..ba70b3c
--- /dev/null
+++ b/src/arch/x86/insts/decode_fault.hh
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_X86_INSTS_DEBUGFAULT_HH__
+#define __ARCH_X86_INSTS_DEBUGFAULT_HH__
+
+#include "arch/x86/insts/static_inst.hh"
+
+namespace gem5
+{
+
+namespace X86ISA
+{
+
+class DecodeFaultInst : public X86StaticInst
+{
+ private:
+Fault fault;
+
+ public:
+// Constructor.
+DecodeFaultInst(const char *mnem, ExtMachInst _machInst, Fault
_fault) :
+X86StaticInst(mnem, _machInst, No_OpClass), fault(_fault)
+{}
+
+Fault
+execute(ExecContext *tc, Trace::InstRecord *traceData) const override
+{
+return fault;
+}
+};
+
+} // namespace X86ISA
+} // namespace gem5
+
+#endif //__ARCH_X86_INSTS_DEBUGFAULT_HH__
diff --git a/src/arch/x86/isa/formats/cond.isa
b/src/arch/x86/isa/formats/cond.isa
index ec46595..158dff3 100644
--- a/src/arch/x86/isa/formats/cond.isa
+++ b/src/arch/x86/isa/formats/cond.isa
@@ -47,3 +47,33 @@
decode_block = '\tif (%s) {\n%s\n\t} else {\n%s\n}\n' % \
(cond, if_blocks.decode_block, else_blocks.decode_block)
}};
+
+def format Cpl0CondInst(cond, *opTypeSet) {{
+blocks = OutputBlocks()
+
+if_blocks = specializeInst(Name, list(opTypeSet), EmulEnv())
+blocks.append(if_blocks)
+else_blocks = specializeInst('UD2', [], EmulEnv())
+blocks.append(else_blocks)
+
+(header_output, decoder_output,
+ decode_block, exec_output) = blocks.makeList()
+decode_block = '''
+if (%(cond)s) {
+%(if_block)s
+} else {
+%(else_block)s
+}
+''' % {'cond': cond,
+'if_block': if_blocks.decode_block,
+'else_block': else_blocks.decode_block
+}
+decode_block = '''
+if (emi.mode.cpl != 0) {
+return new DecodeFaultInst("%(Name)s", emi,
+std::make_shared(0));
+} else {
+%(decode_block)s
+}
+
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Specialize LLDT for 64 bit and non-64 bit.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55884 )
Change subject: arch-x86: Specialize LLDT for 64 bit and non-64 bit.
..
arch-x86: Specialize LLDT for 64 bit and non-64 bit.
In 64 bit mode the LLDT has a 128 bit descriptor which takes up two
slots. In any other mode, the descriptor is still 64 bits.
Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/segmentation.py
2 files changed, 73 insertions(+), 24 deletions(-)
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 46135fe..d2f763d 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -48,7 +48,10 @@
0x00: decode MODRM_REG {
0x0: sldt_Mw_or_Rv();
0x1: str_Mw_or_Rv();
-0x2: Inst::LLDT(Ew);
+0x2: decode MODE_SUBMODE {
+0x0: Inst::LLDT_64(Ew);
+default: Inst::LLDT(Ew);
+}
0x3: Inst::LTR(Ew);
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
diff --git a/src/arch/x86/isa/insts/system/segmentation.py
b/src/arch/x86/isa/insts/system/segmentation.py
index 814a32c..3915a73 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -211,6 +211,60 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
+def macroop LLDT_64_R
+{
+.serialize_after
+chks reg, t0, InGDTCheck, flags=(EZF,)
+br label("end"), flags=(CEZF,)
+limm t4, 0, dataSize=8
+srli t4, reg, 3, dataSize=2
+ld t1, tsg, [8, t4, t0], dataSize=8
+ld t2, tsg, [8, t4, t0], 8, dataSize=8
+chks reg, t1, LDTCheck
+wrdh t3, t1, t2
+wrdl tsl, t1, reg
+wrbase tsl, t3, dataSize=8
+end:
+fault "NoFault"
+};
+
+def macroop LLDT_64_M
+{
+.serialize_after
+ld t5, seg, sib, disp, dataSize=2
+chks t5, t0, InGDTCheck, flags=(EZF,)
+br label("end"), flags=(CEZF,)
+limm t4, 0, dataSize=8
+srli t4, t5, 3, dataSize=2
+ld t1, tsg, [8, t4, t0], dataSize=8
+ld t2, tsg, [8, t4, t0], 8, dataSize=8
+chks t5, t1, LDTCheck
+wrdh t3, t1, t2
+wrdl tsl, t1, t5
+wrbase tsl, t3, dataSize=8
+end:
+fault "NoFault"
+};
+
+def macroop LLDT_64_P
+{
+.serialize_after
+rdip t7
+ld t5, seg, riprel, disp, dataSize=2
+chks t5, t0, InGDTCheck, flags=(EZF,)
+br label("end"), flags=(CEZF,)
+limm t4, 0, dataSize=8
+srli t4, t5, 3, dataSize=2
+ld t1, tsg, [8, t4, t0], dataSize=8
+ld t2, tsg, [8, t4, t0], 8, dataSize=8
+chks t5, t1, LDTCheck
+wrdh t3, t1, t2
+wrdl tsl, t1, t5
+wrbase tsl, t3, dataSize=8
+end:
+fault "NoFault"
+};
+
def macroop LLDT_R
{
.serialize_after
@@ -218,12 +272,9 @@
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
-ldst t1, tsg, [8, t4, t0], dataSize=8
-ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ld t1, tsg, [8, t4, t0], dataSize=8
chks reg, t1, LDTCheck
-wrdh t3, t1, t2
wrdl tsl, t1, reg
-wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
@@ -236,33 +287,16 @@
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
-ldst t1, tsg, [8, t4, t0], dataSize=8
-ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ld t1, tsg, [8, t4, t0], dataSize=8
chks t5, t1, LDTCheck
-wrdh t3, t1, t2
wrdl tsl, t1, t5
-wrbase tsl, t3, dataSize=8
end:
fault "NoFault"
};
def macroop LLDT_P
{
-.serialize_after
-rdip t7
-ld t5, seg, riprel, disp, dataSize=2
-chks t5, t0, InGDTCheck, flags=(EZF,)
-br label("end"), flags=(CEZF,)
-limm t4, 0, dataSize=8
-srli t4, t5, 3, dataSize=2
-ldst t1, tsg, [8, t4, t0], dataSize=8
-ld t2, tsg, [8, t4, t0], 8, dataSize=8
-chks t5, t1, LDTCheck
-wrdh t3, t1, t2
-wrdl tsl, t1, t5
-wrbase tsl, t3, dataSize=8
-end:
-fault "NoFault"
+panic "LLDT in non-64 bit mode doesn't support RIP addressing."
};
def macroop SWAPGS
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55884
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
Gerrit-Change-Number: 55884
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Specialize LTR for 64 bit mode.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55886 )
Change subject: arch-x86: Specialize LTR for 64 bit mode.
..
arch-x86: Specialize LTR for 64 bit mode.
Like LDT descriptors, the TR descriptors are 128 bits in 64 bit mode,
and only 64 bits in other modes.
Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/segmentation.py
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index d87f1ff..b036e6d 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -52,7 +52,10 @@
0x0: Inst::LLDT_64(Ew);
default: Inst::LLDT(Ew);
}
-0x3: Inst::LTR(Ew);
+0x3: decode MODE_SUBMODE {
+0x0: Inst::LTR_64(Ew);
+default: Inst::LTR(Ew);
+}
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
//0x6: jmpe_Ev(); // IA-64
diff --git a/src/arch/x86/isa/insts/system/segmentation.py
b/src/arch/x86/isa/insts/system/segmentation.py
index 3915a73..448f5c7 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -157,7 +157,7 @@
wrlimit idtr, t1
};
-def macroop LTR_R
+def macroop LTR_64_R
{
.serialize_after
chks reg, t0, TRCheck
@@ -174,7 +174,7 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
-def macroop LTR_M
+def macroop LTR_64_M
{
.serialize_after
ld t5, seg, sib, disp, dataSize=2
@@ -192,7 +192,7 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
-def macroop LTR_P
+def macroop LTR_64_P
{
.serialize_after
rdip t7
@@ -211,6 +211,40 @@
st t1, tsg, [8, t4, t0], dataSize=8
};
+def macroop LTR_R
+{
+.serialize_after
+chks reg, t0, TRCheck
+limm t4, 0, dataSize=8
+srli t4, reg, 3, dataSize=2
+ldst t1, tsg, [8, t4, t0], dataSize=8
+chks reg, t1, TSSCheck
+wrdl tr, t1, reg
+limm t5, (1 << 9)
+or t1, t1, t5
+st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_M
+{
+.serialize_after
+ld t5, seg, sib, disp, dataSize=2
+chks t5, t0, TRCheck
+limm t4, 0, dataSize=8
+srli t4, t5, 3, dataSize=2
+ldst t1, tsg, [8, t4, t0], dataSize=8
+chks t5, t1, TSSCheck
+wrdl tr, t1, t5
+limm t5, (1 << 9)
+or t1, t1, t5
+st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_P
+{
+panic "LTR in non-64 bit mode doesn't support RIP addressing."
+};
+
def macroop LLDT_64_R
{
.serialize_after
--
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Gerrit-Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Gerrit-Change-Number: 55886
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Consider CPL in the decoder logic.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55891 )
Change subject: arch-x86: Consider CPL in the decoder logic.
..
arch-x86: Consider CPL in the decoder logic.
For instructions which simply require CPL0 (vs. requiring CPL is < IOPL,
or something else more complicated), this change either switches their
format so that they check that value before being returned, or adds a
comment marking them as privileged if they aren't yet implemented.
This change also makes the mov to/from CR and DR instructions more
particular, and returns an undefined instruction if the CR or DR index
is invalid.
Change-Id: I367d87a380a47428d458bda2ceecc1b983644704
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M src/arch/x86/isa/decoder/locked_opcodes.isa
3 files changed, 59 insertions(+), 39 deletions(-)
diff --git a/src/arch/x86/isa/decoder/locked_opcodes.isa
b/src/arch/x86/isa/decoder/locked_opcodes.isa
index 4a3a94b..de75479 100644
--- a/src/arch/x86/isa/decoder/locked_opcodes.isa
+++ b/src/arch/x86/isa/decoder/locked_opcodes.isa
@@ -137,8 +137,8 @@
}
'X86ISA::TwoByteOpcode': decode OPCODE_OP_TOP5 {
0x04: decode OPCODE_OP_BOTTOM3 {
-0x0: WarnUnimpl::mov_Rd_CR8D();
-0x2: WarnUnimpl::mov_CR8D_Rd();
+0x0: WarnUnimpl::mov_Rd_CR8D(); // privileged
+0x2: WarnUnimpl::mov_CR8D_Rd(); // privileged
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x3: BTS_LOCKED(Mv,Gv);
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 03fd4e8..40beeb7 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -580,7 +580,7 @@
{{"Tried to execute the repne prefix!"}});
0x3: M5InternalError::error(
{{"Tried to execute the rep/repe prefix!"}});
-0x4: HLT();
+0x4: Cpl0Inst::HLT();
0x5: CMC();
//0x6: group3_Eb();
0x6: decode MODRM_REG {
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index b036e6d..5b0ef57 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -49,12 +49,12 @@
0x0: sldt_Mw_or_Rv();
0x1: str_Mw_or_Rv();
0x2: decode MODE_SUBMODE {
-0x0: Inst::LLDT_64(Ew);
-default: Inst::LLDT(Ew);
+0x0: Cpl0Inst::LLDT_64(Ew);
+default: Cpl0Inst::LLDT(Ew);
}
0x3: decode MODE_SUBMODE {
-0x0: Inst::LTR_64(Ew);
-default: Inst::LTR(Ew);
+0x0: Cpl0Inst::LTR_64(Ew);
+default: Cpl0Inst::LTR(Ew);
}
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
@@ -99,33 +99,33 @@
0x1: xsetbv();
}
default: decode MODE_SUBMODE {
-0x0: Inst::LGDT(M);
+0x0: Cpl0Inst::LGDT(M);
default: decode OPSIZE {
// 16 bit operand sizes are special, but only
// in legacy and compatability modes.
-0x2: Inst::LGDT_16(M);
-default: Inst::LGDT(M);
+0x2: Cpl0Inst::LGDT_16(M);
+default: Cpl0Inst::LGDT(M);
}
}
}
0x3: decode MODRM_MOD {
0x3: decode MODRM_RM {
-0x0: vmrun();
-0x1: vmmcall();
-0x2: vmload();
-0x3: vmsave();
-0x4: stgi();
-0x5: clgi();
+0x0: vmrun(); // privileged
+0x1: vmmcall(); // privileged
+0x2: vmload(); // privileged
+0x3: vmsave(); // privileged
+0x4: stgi(); // privileged
+0x5: clgi(); // privileged
0x6: skinit();
-0x7: invlpga();
+0x7: invlpga(); // privileged
}
default: decode MODE_SUBMODE {
-0x0: Inst::LIDT(M);
+0x0: Cpl0Inst::LIDT(M);
default: decode OPSIZE {
// 16 bit operand sizes are special, but
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Implement segment squashing in IRET.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55888 )
Change subject: arch-x86: Implement segment squashing in IRET.
..
arch-x86: Implement segment squashing in IRET.
In IRET when switching to a new CPL, if installed segments are not
conforming code segments and the new CPL would be less priveleged as the
descriptor's DPL, then those segments need to be set to null selectors.
Change-Id: Ie63f35e9d57cff270a1d7af35173f3e8e51c38e4
---
M
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
1 file changed, 90 insertions(+), 2 deletions(-)
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
index 7184849..bcc1622 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
@@ -223,14 +223,89 @@
andi t0, t7, 0x3, flags=(EZF,)
br label("skipSegmentSquashing"), flags=(CEZF,)
-# The attribute register needs to keep track of more info before this
will
-# work the way it needs to.
#FOR (seg = ES, DS, FS, GS)
#IF ((seg.attr.dpl < cpl && ((seg.attr.type = 'data')
#|| (seg.attr.type = 'non-conforming-code')))
#{
#seg = NULL
#}
+#
+# t1 = temp_RIP (preserved but not used)
+# t2 = Attr - [11:8] = type, [1:0] = dpl
+# t3 = temp_RFLAGS (preserved but not used)
+# t4 = handy m5 reg (preserved but not used)
+# t5 = CPL
+# t6 = 0xc00
+# t7 = temp
+#
+# If the segment is data, bit 11 will be 0, and if it's conforming code
+# then bit 11 will be 1 and 10 will be 0. That means that:
+#
+# (seg.attr.type = 'data') || (seg.attr.type = 'non-conforming-code')
+#
+# is the same as attr[11] == 0 || (attr[11] == 1 && attr[10] == 0)
which is
+# the same as attr[11:10] != 11.
+
+limm t6, 0xc00, dataSize=8
+
+rdattr t2, ds, dataSize=8
+# Check if attr[11:10] is 11.
+xor t7, t2, t6, dataSize=8
+and t0, t7, t6, flags=(EZF,), dataSize=8
+br label("skipDSSquash"), flags=(CEZF,)
+# Check if !(DPL < CPL)
+andi t2, t2, 0x3, dataSize=8
+sub t0, t2, t5, flags=(ECF,), dataSize=8
+br label("skipDSSquash"), flags=(nCECF,)
+
+wrdl ds, t0, t0
+wrsel ds, t0
+
+skipDSSquash:
+
+rdattr t2, es, dataSize=8
+# Check if attr[11:10] is 11.
+xor t7, t2, t6, dataSize=8
+and t0, t7, t6, flags=(EZF,), dataSize=8
+br label("skipESSquash"), flags=(CEZF,)
+# Check if !(DPL < CPL)
+andi t2, t2, 0x3, dataSize=8
+sub t0, t2, t5, flags=(ECF,), dataSize=8
+br label("skipESSquash"), flags=(nCECF,)
+
+wrdl es, t0, t0
+wrsel es, t0
+
+skipESSquash:
+
+rdattr t2, fs, dataSize=8
+# Check if attr[11:10] is 11.
+xor t7, t2, t6, dataSize=8
+and t0, t7, t6, flags=(EZF,), dataSize=8
+br label("skipFSSquash"), flags=(CEZF,)
+# Check if !(DPL < CPL)
+andi t2, t2, 0x3, dataSize=8
+sub t0, t2, t5, flags=(ECF,), dataSize=8
+br label("skipFSSquash"), flags=(nCECF,)
+
+wrdl fs, t0, t0
+wrsel fs, t0
+
+skipFSSquash:
+
+rdattr t2, gs, dataSize=8
+# Check if attr[11:10] is 11.
+xor t7, t2, t6, dataSize=8
+and t0, t7, t6, flags=(EZF,), dataSize=8
+br label("skipSegmentSquashing"), flags=(CEZF,)
+# Check if !(DPL < CPL)
+andi t2, t2, 0x3, dataSize=8
+sub t0, t2, t5, flags=(ECF,), dataSize=8
+br label("skipSegmentSquashing"), flags=(nCECF,)
+
+wrdl gs, t0, t0
+wrsel gs, t0
+
#}
skipSegmentSquashing:
--
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Gerrit-Change-Id: Ie63f35e9d57cff270a1d7af35173f3e8e51c38e4
Gerrit-Change-Number: 55888
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fill out the implementation of LXS instructions.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55883 )
Change subject: arch-x86: Fill out the implementation of LXS instructions.
..
arch-x86: Fill out the implementation of LXS instructions.
These are the LDS, LES, LFS, LGS, and LSS instructions. They had already
been implemented in real mode. This change implements them in protected
mode, and also consolidates the implementation of both using python
string substitution.
Change-Id: I3974e6d1a4d07bcfad63a767820e0e7d7687b18d
---
M src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
3 files changed, 129 insertions(+), 113 deletions(-)
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 104d205..e490189 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -390,12 +390,12 @@
0x4: decode MODE_SUBMODE {
0x0: UD2();
0x3, 0x4: LES_REAL(Gz,Mz);
-default: WarnUnimpl::les_Gz_Mp();
+default: LES(Gz,Mz);
}
0x5: decode MODE_SUBMODE {
0x0: UD2();
0x3, 0x4: LDS_REAL(Gz,Mz);
-default: WarnUnimpl::lds_Gz_Mp();
+default: LDS(Gz,Mz);
}
//0x6: group12_Eb_Ib();
0x6: decode MODRM_REG {
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index b82afb0..46135fe 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -752,16 +752,16 @@
0x1: CMPXCHG(Ev,Gv);
0x2: decode MODE_SUBMODE {
0x3, 0x4: LSS_REAL(Gz,Mz);
-default: WarnUnimpl::lss_Gz_Mp();
+default: LSS(Gz,Mz);
}
0x3: BTR(Ev,Gv);
0x4: decode MODE_SUBMODE {
0x3, 0x4: LFS_REAL(Gz,Mz);
-default: WarnUnimpl::lfs_Gz_Mp();
+default: LFS(Gz,Mz);
}
0x5: decode MODE_SUBMODE {
0x3, 0x4: LGS_REAL(Gz,Mz);
-default: WarnUnimpl::lgs_Gz_Mp();
+default: LGS(Gz,Mz);
}
//The size of the second operand in these instructions
//should really be "b" or "w", but it's set to v in order
diff --git
a/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
b/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
index 1967820..bffa1a4 100644
--- a/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
+++ b/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
@@ -33,121 +33,123 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-microcode = '''
-
-#
-# Real mode versions of the load far pointer instructions.
-#
-
-def macroop LDS_REAL_R_M {
+lxs_template = '''
+def macroop %(full_inst)s {
# Calculate the address of the pointer.
-lea t1, seg, sib, disp, dataSize=asz
+%(addr_calc)s
# Load the selector into a temporary.
ld t2, seg, [1, t0, t1], dsz, dataSize=2
# Load the offset.
-ld reg, seg, [1, t0, t1], 0
-# Install the selector value.
-wrsel ds, t2
-# Make sure there isn't any junk in the upper bits of the base.
-mov t2, t0, t2
-# Compute and set the base.
-slli t2, t2, 4, dataSize=8
-wrbase ds, t2, dataSize=8
+ld t1, seg, [1, t0, t1], 0
+
+# Figure out if this is a null selector.
+andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
+br label("processDescriptor"), flags=(CEZF,)
+
+# Extract the index.
+andi t3, t2, 0xF8, dataSize=8
+
+# Check if this is a local or global descriptor.
+andi t0, t2, 0x4, flags=(EZF,), dataSize=2
+br label("globalDescriptor"), flags=(CEZF,)
+
+# It's local.
+ld t4, tsl, [1, t0, t3], dataSize=8, addressSize=8
+br label("processDescriptor")
+
+# It's global.
+globalDescriptor:
+ld t4, tsg, [1, t0, t3], dataSize=8, addressSize=8
+
+# Install the descriptor.
+processDescriptor:
+chks t2, t4, %(check_type)sdataSize=8
+wrdl %(seg)s, t4, t2
+wrsel %(seg)s, t2
+
+# Install the offset.
+mov reg, reg, t1
};
-
-def macroop LES_REAL_R_M {
-# Calculate the address of the pointer.
-lea t1, seg, sib, disp, dataSize=asz
-
-# Load the selector into a temporary.
-ld t2, seg, [1, t0, t1], dsz, dataSize=2
-# Load the offset.
-ld reg, seg, [1, t0, t1], 0
-# Install the selector value.
-wrsel es, t2
-# Make sure
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Expose the current CPL to the decoder.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55889 )
Change subject: arch-x86: Expose the current CPL to the decoder.
..
arch-x86: Expose the current CPL to the decoder.
This value is already floating around, and there is essentially no
overhead for exposing it to the decoder. With that value, we can handle
instructions which generically need to run at CPL0.
Some instructions have other more complicated permissions checks, like
that the CPL needs to have some relation to the IOPL. Those checks will
have to be implemented by the instructions themselves, since the decoder
can't factor in all possible state values.
Change-Id: Ie93f4f13aae002f69330606c515f369c5706c655
---
M src/arch/x86/decoder.hh
M src/arch/x86/isa/bitfields.isa
M src/arch/x86/types.hh
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 38a5e10..29415ef 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -110,6 +110,8 @@
uint8_t defAddr = 0;
uint8_t stack = 0;
+uint8_t cpl = 0;
+
uint8_t
getNextByte()
{
@@ -256,6 +258,7 @@
Decoder(const X86DecoderParams ) : InstDecoder(p, )
{
emi.reset();
+emi.mode.cpl = cpl;
emi.mode.mode = mode;
emi.mode.submode = submode;
}
@@ -263,8 +266,10 @@
void
setM5Reg(HandyM5Reg m5Reg)
{
+cpl = m5Reg.cpl;
mode = (X86Mode)(uint64_t)m5Reg.mode;
submode = (X86SubMode)(uint64_t)m5Reg.submode;
+emi.mode.cpl = cpl;
emi.mode.mode = mode;
emi.mode.submode = submode;
altOp = m5Reg.altOp;
@@ -298,8 +303,10 @@
Decoder *dec = dynamic_cast(old);
assert(dec);
+cpl = dec->cpl;
mode = dec->mode;
submode = dec->submode;
+emi.mode.cpl = cpl;
emi.mode.mode = mode;
emi.mode.submode = submode;
altOp = dec->altOp;
diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa
index 0404afc..dd81712 100644
--- a/src/arch/x86/isa/bitfields.isa
+++ b/src/arch/x86/isa/bitfields.isa
@@ -83,6 +83,7 @@
def bitfield STACKSIZE stackSize;
def bitfield MODE mode;
+def bitfield CPL mode.cpl;
def bitfield MODE_MODE mode.mode;
def bitfield MODE_SUBMODE mode.submode;
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index a2c2771..f377806 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -187,6 +187,12 @@
Bitfield<2,0> submode;
EndBitUnion(OperatingMode)
+BitUnion8(OperatingModeAndCPL)
+Bitfield<5,4> cpl;
+Bitfield<3> mode;
+Bitfield<2,0> submode;
+EndBitUnion(OperatingModeAndCPL)
+
enum X86Mode
{
LongMode,
@@ -236,7 +242,7 @@
uint8_t dispSize;
//Mode information
-OperatingMode mode;
+OperatingModeAndCPL mode;
};
inline static std::ostream &
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ie93f4f13aae002f69330606c515f369c5706c655
Gerrit-Change-Number: 55889
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Implement protected mode pop into selector reg.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55885 )
Change subject: arch-x86: Implement protected mode pop into selector reg.
..
arch-x86: Implement protected mode pop into selector reg.
These are strongly based on the mov to segment selector instructions.
Change-Id: I0037583b8d8f4a53400c946aaa01d4406073e8fd
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
3 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index e490189..03fd4e8 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -48,7 +48,7 @@
0x7: decode MODE_SUBMODE {
0x0: UD2();
0x3, 0x4: POP_REAL(sEv);
-default: WarnUnimpl::pop_ES();
+default: POP(sEv);
}
default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
@@ -76,7 +76,7 @@
0x7: decode MODE_SUBMODE {
0x0: UD2();
0x3, 0x4: POP_REAL(sSv);
-default: WarnUnimpl::pop_SS();
+default: POP(sSv);
}
default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
@@ -91,7 +91,7 @@
0x7: decode MODE_SUBMODE {
0x0: UD2();
0x3, 0x4: POP_REAL(sDv);
-default: WarnUnimpl::pop_DS();
+default: POP(sDv);
}
default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index d2f763d..d87f1ff 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -673,7 +673,7 @@
0x0: Inst::PUSH(sFv);
0x1: decode MODE_SUBMODE {
0x3, 0x4: Inst::POP_REAL(sFv);
-default: pop_fs();
+default: Inst::POP(sFv);
}
0x2: CPUIDInst::CPUID({{
CpuidResult result;
@@ -703,7 +703,7 @@
0x0: Inst::PUSH(sGv);
0x1: decode MODE_SUBMODE {
0x3, 0x4: Inst::POP_REAL(sGv);
-default: pop_gs();
+default: Inst::POP(sGv);
}
0x2: rsm_smm();
0x3: Inst::BTS(Ev,Gv);
diff --git
a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index e97d17f..34833ca 100644
---
a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++
b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -73,6 +73,33 @@
wrbase sr, t1, dataSize=8
};
+def macroop POP_S {
+# Make the default data size of pops 64 bits in 64 bit mode
+.adjust_env oszIn64Override
+
+ld t1, ss, [1, t0, rsp], addressSize=ssz, dataSize=2
+
+andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
+br label("processDescriptor"), flags=(CEZF,)
+
+andi t2, t1, 0xF8, dataSize=8
+andi t0, t1, 0x4, flags=(EZF,), dataSize=2
+br label("globalDescriptor")
+
+ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
+br label("processDescriptor")
+
+globalDescriptor:
+ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
+
+processDescriptor:
+chks t1, t3, dataSize=8
+wrdl sr, t3, t1
+wrsel sr, t1
+
+addi rsp, rsp, dsz, dataSize=ssz
+};
+
def macroop PUSH_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55885
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0037583b8d8f4a53400c946aaa01d4406073e8fd
Gerrit-Change-Number: 55885
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix a bug in the protected mode IRET.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55887 ) Change subject: arch-x86: Fix a bug in the protected mode IRET. .. arch-x86: Fix a bug in the protected mode IRET. Fix the direction of the comparison which makes sure the new RIP will fit within the new CS limit. Change-Id: I3f3e66c185d0e1fbc430b0ae594d63cdd62b9dfd --- M src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 815f291..7184849 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -156,7 +156,7 @@ # appropriate/other RIP checks. # if temp_RIP > CS.limit throw #GP(0) rdlimit t6, cs, dataSize=8 -sub t0, t1, t6, flags=(ECF,) +sub t0, t6, t1, flags=(ECF,) fault "std::make_shared(0)", flags=(CECF,) #(temp_CPL!=CPL) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55887 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3f3e66c185d0e1fbc430b0ae594d63cdd62b9dfd Gerrit-Change-Number: 55887 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
