from:"Roger Chang \(Gerrit\) via gem5\-dev"

[gem5-dev] [XS] Change in gem5/gem5[develop]: cpu-o3: add decode stall in fetch stage

2023-07-03 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71998?usp=email )



Change subject: cpu-o3: add decode stall in fetch stage
..

cpu-o3: add decode stall in fetch stage

Change-Id: Ibbd532092449bcee5210cde85beeb5e8429fca8c
---
M src/cpu/o3/fetch.cc
1 file changed, 4 insertions(+), 1 deletion(-)



diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 8cd84cb..41841f2 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -1176,11 +1176,13 @@
 auto *dec_ptr = decoder[tid];
 const Addr pc_mask = dec_ptr->pcMask();

+auto fetchStall = false;
+
 // Loop through instruction memory from the cache.
 // Keep issuing while fetchWidth is available and branch is not
 // predicted taken
 while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
-   && !predictedBranch && !quiesce) {
+   && !predictedBranch && !quiesce && !fetchStall) {
 // We need to process more memory if we aren't going to get a
 // StaticInst from the rom, the current macroop, or what's already
 // in the decoder.
@@ -1228,6 +1230,7 @@
 pcOffset = 0;
 }
 } else {
+fetchStall = dec_ptr->isStalled();
 // We need more bytes for this instruction so  
blkOffset and

 // pcOffset will be updated
 break;

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Gerrit-Change-Id: Ibbd532092449bcee5210cde85beeb5e8429fca8c
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Declear vecElemClass for RISC-V vector extensions

2023-07-03 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71999?usp=email )



Change subject: arch-riscv: Declear vecElemClass for RISC-V vector  
extensions

..

arch-riscv: Declear vecElemClass for RISC-V vector extensions

Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/vector.hh
2 files changed, 7 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a4a792e..f60249a 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -244,7 +244,6 @@
 {

 /* Not applicable to RISCV */
-RegClass vecElemClass(VecElemClass, VecElemClassName, 0, debug::IntRegs);
 RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 0,
 debug::IntRegs);
 RegClass matRegClass(MatRegClass, MatRegClassName, 0, debug::MatRegs);
diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh
index d722c2d..05dd702 100644
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -49,6 +49,7 @@
 constexpr unsigned ELEN = 64;
 constexpr unsigned VLEN = 256;
 constexpr unsigned VLENB = VLEN / 8;
+constexpr unsigned NumVecElemPerVecReg = VLEN / ELEN;

 using VecRegContainer = gem5::VecRegContainer;
 using vreg_t = VecRegContainer;
@@ -68,12 +69,18 @@
 // vector index
 const int VecMemInternalReg0 = NumVecStandardRegs;

+static inline VecElemRegClassOps
+vecRegElemClassOps(NumVecElemPerVecReg);
 static inline TypedRegClassOps vecRegClassOps;

 inline constexpr RegClass vecRegClass =
 RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
 ops(vecRegClassOps).
 regType();
+inline constexpr RegClass vecElemClass =
+RegClass(VecElemClass, VecElemClassName, NumVecRegs *  
NumVecElemPerVecReg,

+debug::VecRegs).
+ops(vecRegElemClassOps);

 BitUnion32(VTYPE)
 Bitfield<31> vill;

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Gerrit-Change-Id: I623a753499123d6934eda60ebcfe013c264cf458
Gerrit-Change-Number: 71999
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Pass the DISPLAY environment variable through to SCons.

2023-06-29 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56952?usp=email )


Change subject: scons: Pass the DISPLAY environment variable through to  
SCons.

..

scons: Pass the DISPLAY environment variable through to SCons.

This lets gui programs run correctly within SCons, specifically the
kconfig "guiconfig" helper utility.

Change-Id: Iec51df3db89ac7e7411e6c08fe8201afb69dc63e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56952
Reviewed-by: Matthew Poremba 
Maintainer: Matthew Poremba 
Tested-by: kokoro 
---
M site_scons/gem5_scons/defaults.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index 996cfd4..f800b67 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -67,6 +67,7 @@
 "LINKFLAGS_EXTRA",
 "LANG",
 "LC_CTYPE",
+"DISPLAY",
 ]
 )


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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec51df3db89ac7e7411e6c08fe8201afb69dc63e
Gerrit-Change-Number: 56952
Gerrit-PatchSet: 21
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS

2023-06-13 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email )


Change subject: arch-riscv: Fix unexpected behavior of float operations in  
Mac OS

..

arch-riscv: Fix unexpected behavior of float operations in Mac OS

The uint_fast16_t is the integer at least 16 bits size, it can be
32, 64 bits and more. Usually most of the simulations are in the
x86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,
there is no problem for double precision float operations and it can
pass FloatMM test. However, in the Mac OS, the size of uint_fast16_t
is 16 bits, it will lose the upper bits when converting float
register bits to freg_t and it will generate unexpected results for
FloatMM test.

The change can guarantee that the size of data in freg_t is at least
64 bits and it will not lose any data from floating point to freg_t.

Reference:
https://developer.apple.com/documentation/kernel/uint_fast16_t

https://codebrowser.dev/glibc/glibc/stdlib/stdint.h.html

Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71578
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/regs/float.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 1654bdb..4809372 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -105,7 +105,7 @@
 static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
 static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
 static constexpr freg_t freg(float64_t f) { return f; }
-static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
+static constexpr freg_t freg(uint_fast64_t f) { return {f}; }

 namespace float_reg
 {

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
Gerrit-Change-Number: 71578
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Yu-hsin Wang 
Gerrit-CC: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS

2023-06-13 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email )



Change subject: arch-riscv: Fix unexpected behavior of float operations in  
Mac OS

..

arch-riscv: Fix unexpected behavior of float operations in Mac OS

The uint_fast16_t is the integer at least 16 bits size, it can be
32, 64 bits and more. Usually most of the simulations are in the
x86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,
there is no problem for double precision float operations and it can
pass FloatMM test. However, in the Mac OS, the size of uint_fast16_t
is 16 bits, it will lose the upper bits when converting float
register bits to freg_t and it will generate unexpected results for
FloatMM test.

The change can guarantee that the size of data in freg_t is at least
64 bits and it will not lose any data from floating point to freg_t.

Reference:
https://developer.apple.com/documentation/kernel/uint_fast16_t

https: //codebrowser.dev/glibc/glibc/stdlib/stdint.h.html

Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
---
M src/arch/riscv/regs/float.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 1654bdb..4809372 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -105,7 +105,7 @@
 static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
 static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
 static constexpr freg_t freg(float64_t f) { return f; }
-static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
+static constexpr freg_t freg(uint_fast64_t f) { return {f}; }

 namespace float_reg
 {

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Gerrit-Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor fmax and fmin instructions

2023-06-12 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71479?usp=email )


Change subject: arch-riscv: Refactor fmax and fmin instructions
..

arch-riscv: Refactor fmax and fmin instructions

Currently fmax and fmin instructions convert source float registers such as
Fs1_bits to float64_t(or float32_t and float16_t) many times in the single
instruction. It is not efficient for the future maintenance of these
instructions.

The change adds non-register float_t intermediate variables fs1 and fs2 to
keep converted results so that we don’t need to do it repeatedly. It also
added an intermediate variable fd for specific float type to assume the  
upper

bits of the packed float register are all one.

Change-Id: Ic508d5255db6c4b38ca4df6dd805df440c043fff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71479
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 54 insertions(+), 67 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 2dcd118..a339c11 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1615,93 +1615,80 @@
 }
 0x14: decode ROUND_MODE {
 0x0: fmin_s({{
-bool less = f32_lt_quiet(f32(freg(Fs1_bits)),
-f32(freg(Fs2_bits))) ||
-(f32_eq(f32(freg(Fs1_bits)),
-f32(freg(Fs2_bits))) &&
-bits(f32(freg(Fs1_bits)).v, 31));
+float32_t fs1 = f32(freg(Fs1_bits));
+float32_t fs2 = f32(freg(Fs2_bits));
+float32_t fd;
+bool less = f32_lt_quiet(fs1, fs2) ||
+(f32_eq(fs1, fs2) && bits(fs1.v, 31));

-Fd_bits = less ||
-isNaNF32UI(f32(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF32UI(f32(freg(Fs1_bits)).v) &&
-isNaNF32UI(f32(freg(Fs2_bits)).v))
-Fd_bits = f32(defaultNaNF32UI).v;
+fd = less || isNaNF32UI(fs2.v) ? fs1 : fs2;
+if (isNaNF32UI(fs1.v) && isNaNF32UI(fs2.v))
+fd = f32(defaultNaNF32UI);
+Fd_bits = freg(fd).v;
 }}, FloatCmpOp);
 0x1: fmax_s({{
-bool greater = f32_lt_quiet(f32(freg(Fs2_bits)),
-f32(freg(Fs1_bits))) ||
-(f32_eq(f32(freg(Fs2_bits)),
-f32(freg(Fs1_bits))) &&
-bits(f32(freg(Fs2_bits)).v, 31));
+float32_t fs1 = f32(freg(Fs1_bits));
+float32_t fs2 = f32(freg(Fs2_bits));
+float32_t fd;
+bool greater = f32_lt_quiet(fs2, fs1) ||
+(f32_eq(fs2, fs1) && bits(fs2.v, 31));

-Fd_bits = greater ||
-isNaNF32UI(f32(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF32UI(f32(freg(Fs1_bits)).v) &&
-isNaNF32UI(f32(freg(Fs2_bits)).v))
-Fd_bits = f32(defaultNaNF32UI).v;
+fd = greater || isNaNF32UI(fs2.v) ? fs1: fs2;
+if (isNaNF32UI(fs1.v) && isNaNF32UI(fs2.v))
+fd = f32(defaultNaNF32UI);
+Fd_bits = freg(fd).v;
 }}, FloatCmpOp);
 }
 0x15: decode ROUND_MODE {
 0x0: fmin_d({{
-bool less = f64_lt_quiet(f64(freg(Fs1_bits)),
-f64(freg(Fs2_bits))) ||
-(f64_eq(f64(freg(Fs1_bits)),
-f64(freg(Fs2_bits))) &&
-bits(f64(freg(Fs1_bits)).v, 63));
+float64_t fs1 = f64(freg(Fs1_bits));
+float64_t fs2 = f64(freg(Fs2_bits));
+float64_t fd;
+bool less = f64_lt_quiet(fs1, fs2) ||
+(f64_eq(fs1, fs2) && bits(fs1.v, 63));

-Fd_bits = less ||
-isNaNF64UI(f64(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF64UI(f64(freg(Fs1_bits)).v) &&
-

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor fmax and fmin instructions

2023-06-12 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71479?usp=email )



Change subject: arch-riscv: Refactor fmax and fmin instructions
..

arch-riscv: Refactor fmax and fmin instructions

Currently fmax and fmin instructions convert source float registers such as
Fs1_bits to float64_t(or float32_t and float16_t) many times in the single
instruction. It is not efficient for the future maintenance of these
instructions.

The change adds non-register float_t intermediate variables fs1 and fs2 to
keep converted results so that we don’t need to do it repeatedly. It also
added an intermediate variable fd for specific float type to assume the  
upper

bits of the packed float register are all one.

Change-Id: Ic508d5255db6c4b38ca4df6dd805df440c043fff
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 54 insertions(+), 67 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 2dcd118..a339c11 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1615,93 +1615,80 @@
 }
 0x14: decode ROUND_MODE {
 0x0: fmin_s({{
-bool less = f32_lt_quiet(f32(freg(Fs1_bits)),
-f32(freg(Fs2_bits))) ||
-(f32_eq(f32(freg(Fs1_bits)),
-f32(freg(Fs2_bits))) &&
-bits(f32(freg(Fs1_bits)).v, 31));
+float32_t fs1 = f32(freg(Fs1_bits));
+float32_t fs2 = f32(freg(Fs2_bits));
+float32_t fd;
+bool less = f32_lt_quiet(fs1, fs2) ||
+(f32_eq(fs1, fs2) && bits(fs1.v, 31));

-Fd_bits = less ||
-isNaNF32UI(f32(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF32UI(f32(freg(Fs1_bits)).v) &&
-isNaNF32UI(f32(freg(Fs2_bits)).v))
-Fd_bits = f32(defaultNaNF32UI).v;
+fd = less || isNaNF32UI(fs2.v) ? fs1 : fs2;
+if (isNaNF32UI(fs1.v) && isNaNF32UI(fs2.v))
+fd = f32(defaultNaNF32UI);
+Fd_bits = freg(fd).v;
 }}, FloatCmpOp);
 0x1: fmax_s({{
-bool greater = f32_lt_quiet(f32(freg(Fs2_bits)),
-f32(freg(Fs1_bits))) ||
-(f32_eq(f32(freg(Fs2_bits)),
-f32(freg(Fs1_bits))) &&
-bits(f32(freg(Fs2_bits)).v, 31));
+float32_t fs1 = f32(freg(Fs1_bits));
+float32_t fs2 = f32(freg(Fs2_bits));
+float32_t fd;
+bool greater = f32_lt_quiet(fs2, fs1) ||
+(f32_eq(fs2, fs1) && bits(fs2.v, 31));

-Fd_bits = greater ||
-isNaNF32UI(f32(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF32UI(f32(freg(Fs1_bits)).v) &&
-isNaNF32UI(f32(freg(Fs2_bits)).v))
-Fd_bits = f32(defaultNaNF32UI).v;
+fd = greater || isNaNF32UI(fs2.v) ? fs1: fs2;
+if (isNaNF32UI(fs1.v) && isNaNF32UI(fs2.v))
+fd = f32(defaultNaNF32UI);
+Fd_bits = freg(fd).v;
 }}, FloatCmpOp);
 }
 0x15: decode ROUND_MODE {
 0x0: fmin_d({{
-bool less = f64_lt_quiet(f64(freg(Fs1_bits)),
-f64(freg(Fs2_bits))) ||
-(f64_eq(f64(freg(Fs1_bits)),
-f64(freg(Fs2_bits))) &&
-bits(f64(freg(Fs1_bits)).v, 63));
+float64_t fs1 = f64(freg(Fs1_bits));
+float64_t fs2 = f64(freg(Fs2_bits));
+float64_t fd;
+bool less = f64_lt_quiet(fs1, fs2) ||
+(f64_eq(fs1, fs2) && bits(fs1.v, 63));

-Fd_bits = less ||
-isNaNF64UI(f64(freg(Fs2_bits)).v) ?
-freg(Fs1_bits).v : freg(Fs2_bits).v;
-if (isNaNF64UI(f64(freg(Fs1_bits)).v) &&
-isNaNF64UI(f64(freg(Fs2_bits)).v))
-Fd_bits = f64(defaultNaNF64UI).v;
+fd = less || isNaNF64UI(fs2.v) ? fs1 : fs2;
+if (isNaNF64UI(fs1.v) &&

[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Add extra parent dir to CPPPATH if --no-duplicate-sources

2023-06-12 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71478?usp=email )



Change subject: scons: Add extra parent dir to CPPPATH if  
--no-duplicate-sources

..

scons: Add extra parent dir to CPPPATH if --no-duplicate-sources

In the previous version of gem5, the source files of extra directories will
copy to build directory for compilation. It will not be a problem if the
extra directories include *.h(*.hh) from the other extra directories.

After the patch applied from the change
(https://gem5-review.googlesource.com/c/public/gem5/+/68758). The source  
files

of extra directories will not copy to the build directory unless the user
compiles gem5 with "--duplicate-sources". It will cause the compilation  
error

if the code includes a header file from other repositories.

For example, assume we want to compile gem5 with "foo/bar1" and "foo/bar2"
repositories and they are gem5-independent. There are some header files in
"foo/bar1/a.h" "foo/bar1/b.h" and "foo/bar2/d.h". If the code
"foo/bar1/sample.c" tries to include the file "foo/bar2/d.h". They usually
include the file by declare "#include bar2/d.h" in foo/bar1/sample.c. It
can work if --duplicate-sources is specified in gem5 build because they will
copy to /bar1 and /bar2 respectively, and -I
is specified by default whether duplicate_sources or not. It will raise the
compilation error if the user does not specify it.

The change is aimed to let the situation work without duplicate-sources
specified by adding parent extra directory, and adding them before the extra
directories. If the --duplicate-sources specified, it will not add parent  
extra

directories to avoid repeat include paths.

Change-Id: I461e1dcb8266d785f1f38eeff77f9d515d47c03d
---
M src/SConscript
1 file changed, 8 insertions(+), 0 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d26bf49..f0af67c 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -536,6 +536,14 @@
 # the corresponding build directory to pick up generated include
 # files.
 env.Append(CPPPATH=Dir('.'))
+parent_dir_set = set()
+
+for extra_dir in extras_dir_list:
+parent_dir_set.add(str(Dir(extra_dir).Dir('..').abspath))
+
+if not GetOption('duplicate_sources'):
+for parent_dir in parent_dir_set:
+env.Append(CPPPATH=Dir(parent_dir))

 for extra_dir in extras_dir_list:
 env.Append(CPPPATH=Dir(extra_dir))

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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix grpc protobuf actions

2023-06-07 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71318?usp=email )


Change subject: scons: Fix grpc protobuf actions
..

scons: Fix grpc protobuf actions

The change will fix the proto import issue and build issue with
--no-duplicate-sources options, more details please reference:
https://gem5-review.googlesource.com/c/public/gem5/+/64491.

Change-Id: I259413f7739f89598dcd42c3f2e1e865cec3de43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71318
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/SConscript
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/SConscript b/src/SConscript
index 13f08d2..d26bf49 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -280,9 +280,9 @@
 root, ext = os.path.splitext(source[0].get_abspath())
 return [root + '.grpc.pb.cc', root + '.grpc.pb.h'], source

-protoc_grpc_action=MakeAction('${PROTOC} --grpc_out ${BUILDDIR} '
-'--plugin=protoc-gen-grpc=${PROTOC_GRPC} --proto_path ${BUILDDIR} '
-'${SOURCE.get_abspath()}',
+protoc_grpc_action=MakeAction('${PROTOC} --grpc_out ${TARGET.dir.abspath} '
+'--plugin=protoc-gen-grpc=${PROTOC_GRPC} '
+'--proto_path ${SOURCE.dir.abspath} ${SOURCE.abspath}',
 Transform("PROTOC"))

 env.Append(BUILDERS={'GrpcProtoBufCC' : Builder(

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Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix grpc protobuf actions

2023-06-05 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71318?usp=email )



Change subject: scons: Fix grpc protobuf actions
..

scons: Fix grpc protobuf actions

The change will fix the proto import issue and build issue with
--no-duplicate-sources options, more details please reference:
https://gem5-review.googlesource.com/c/public/gem5/+/64491.

Change-Id: I259413f7739f89598dcd42c3f2e1e865cec3de43
---
M src/SConscript
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 13f08d2..efc1477 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -280,9 +280,9 @@
 root, ext = os.path.splitext(source[0].get_abspath())
 return [root + '.grpc.pb.cc', root + '.grpc.pb.h'], source

-protoc_grpc_action=MakeAction('${PROTOC} --grpc_out ${BUILDDIR} '
-'--plugin=protoc-gen-grpc=${PROTOC_GRPC} --proto_path ${BUILDDIR} '
-'${SOURCE.get_abspath()}',
+protoc_grpc_action=MakeAction('${PROTOC} --grpc_out ${TARGET.dir.abspath} '
+'--plugin=protoc-gen-grpc=${PROTOC_GRPC} --proto_path  
${SOURCE.dir.abspath} '

+'${SOURCE.abspath}',
 Transform("PROTOC"))

 env.Append(BUILDERS={'GrpcProtoBufCC' : Builder(

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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Add U74VecFU to U74CPU

2023-06-04 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71238?usp=email )


Change subject: stdlib: Add U74VecFU to U74CPU
..

stdlib: Add U74VecFU to U74CPU

This change is to elimilate the warning message from U74CPU.

Change-Id: I7a5d0cd0b2955e54ed14fc1ac6f7127bd7f0604b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71238
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

index 48291bf..4b8d2c1 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
@@ -75,6 +75,10 @@
 pass


+class U74VecFU(MinorDefaultVecFU):
+pass
+
+
 class U74FUPool(MinorFUPool):
 funcUnits = [
 U74IntFU(),
@@ -86,6 +90,7 @@
 U74MemReadFU(),
 U74MemWriteFU(),
 U74MiscFU(),
+U74VecFU(),
 ]



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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I7a5d0cd0b2955e54ed14fc1ac6f7127bd7f0604b
Gerrit-Change-Number: 71238
Gerrit-PatchSet: 3
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext

2023-06-04 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67295?usp=email )


Change subject: arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext
..

arch-riscv,cpu-minor: Add MinorDefaultVecFU for risc-v v-ext

Change-Id: Id5c5ae5fa1901154cadeb0a4958703f3f15d491f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67295
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/minor/BaseMinorCPU.py
1 file changed, 28 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py
index bd27b92..c20a310 100644
--- a/src/cpu/minor/BaseMinorCPU.py
+++ b/src/cpu/minor/BaseMinorCPU.py
@@ -250,6 +250,33 @@
 opLat = 1


+class MinorDefaultVecFU(MinorFU):
+opClasses = minorMakeOpClassSet(
+[
+"VectorUnitStrideLoad",
+"VectorUnitStrideStore",
+"VectorUnitStrideMaskLoad",
+"VectorUnitStrideMaskStore",
+"VectorStridedLoad",
+"VectorStridedStore",
+"VectorIndexedLoad",
+"VectorIndexedStore",
+"VectorUnitStrideFaultOnlyFirstLoad",
+"VectorWholeRegisterLoad",
+"VectorWholeRegisterStore",
+"VectorIntegerArith",
+"VectorFloatArith",
+"VectorFloatConvert",
+"VectorIntegerReduce",
+"VectorFloatReduce",
+"VectorMisc",
+"VectorIntegerExtension",
+"VectorConfig",
+]
+)
+opLat = 1
+
+
 class MinorDefaultFUPool(MinorFUPool):
 funcUnits = [
 MinorDefaultIntFU(),
@@ -260,6 +287,7 @@
 MinorDefaultPredFU(),
 MinorDefaultMemFU(),
 MinorDefaultMiscFU(),
+MinorDefaultVecFU(),
 ]



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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
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Gerrit-Change-Id: Id5c5ae5fa1901154cadeb0a4958703f3f15d491f
Gerrit-Change-Number: 67295
Gerrit-PatchSet: 5
Gerrit-Owner: 轩胡 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Add U74VecFU to elimilate warning from minor cpu

2023-06-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71238?usp=email )



Change subject: stdlib: Add U74VecFU to elimilate warning from minor cpu
..

stdlib: Add U74VecFU to elimilate warning from minor cpu

Change-Id: I7a5d0cd0b2955e54ed14fc1ac6f7127bd7f0604b
---
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py  
b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

index 48291bf..4b8d2c1 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
@@ -75,6 +75,10 @@
 pass


+class U74VecFU(MinorDefaultVecFU):
+pass
+
+
 class U74FUPool(MinorFUPool):
 funcUnits = [
 U74IntFU(),
@@ -86,6 +90,7 @@
 U74MemReadFU(),
 U74MemWriteFU(),
 U74MiscFU(),
+U74VecFU(),
 ]



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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

2023-06-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71198?usp=email )


Change subject: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp  
c.fsdsp

..

arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

The change adds the missing FPU checking for these instructions.

Change-Id: I7f2ef89786af0d528f2029f1097cfeac6c7d65f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71198
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c7eefbc..2dcd118 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -307,6 +307,11 @@
  CIMM1 << 5 |
  CIMM5<2:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is off",
+   machInst);
+
 Fc1_bits = Mem;
 }}, {{
 EA = rvZext(sp + offset);
@@ -330,6 +335,11 @@
  CIMM1 << 5 |
  CIMM5<1:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is  
off",
+
machInst);

+
 freg_t fd;
 fd = freg(f32(Mem_uw));
 Fd_bits = fd.v;
@@ -387,6 +397,11 @@
 offset = CIMM6<5:3> << 3 |
  CIMM6<2:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is off",
+   machInst);
+
 Mem_ud = Fc2_bits;
 }}, {{
 EA = rvZext(sp + offset);
@@ -404,6 +419,11 @@
 offset = CIMM6<5:2> << 2 |
  CIMM6<1:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is  
off",
+
machInst);

+
 Mem_uw = unboxF32(boxF32(Fs2_bits));
 }}, {{
 EA = (uint32_t)(sp_uw + offset);

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Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

2023-06-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71198?usp=email )



Change subject: arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp  
c.fsdsp

..

arch-riscv: Check FPU status for c.flwsp c.fldsp c.fswsp c.fsdsp

Most of float point operations check the FPU status beforehead.
The change adds the missing FPU checking for these instructions.

Change-Id: I7f2ef89786af0d528f2029f1097cfeac6c7d65f2
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 20 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c7eefbc..2dcd118 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -307,6 +307,11 @@
  CIMM1 << 5 |
  CIMM5<2:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is off",
+   machInst);
+
 Fc1_bits = Mem;
 }}, {{
 EA = rvZext(sp + offset);
@@ -330,6 +335,11 @@
  CIMM1 << 5 |
  CIMM5<1:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is  
off",
+
machInst);

+
 freg_t fd;
 fd = freg(f32(Mem_uw));
 Fd_bits = fd.v;
@@ -387,6 +397,11 @@
 offset = CIMM6<5:3> << 3 |
  CIMM6<2:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is off",
+   machInst);
+
 Mem_ud = Fc2_bits;
 }}, {{
 EA = rvZext(sp + offset);
@@ -404,6 +419,11 @@
 offset = CIMM6<5:2> << 2 |
  CIMM6<1:0> << 6;
 }}, {{
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is  
off",
+
machInst);

+
 Mem_uw = unboxF32(boxF32(Fs2_bits));
 }}, {{
 EA = (uint32_t)(sp_uw + offset);

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add BS format isa

2023-05-23 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70598?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Add BS format isa
..

arch-riscv: Add BS format isa

This format is helper for aes32dsi, aes32dsmi, aes32esi, aes32esmi,
sm4ed, sm4ks disassembly

Change-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70598
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bs.cc
A src/arch/riscv/insts/bs.hh
M src/arch/riscv/isa/decoder.isa
A src/arch/riscv/isa/formats/bs.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 172 insertions(+), 12 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 80592a3..704152c 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -28,6 +28,7 @@
 Import('*')

 Source('amo.cc', tags='riscv isa')
+Source('bs.cc', tags='riscv isa')
 Source('compressed.cc', tags='riscv isa')
 Source('mem.cc', tags='riscv isa')
 Source('standard.cc', tags='riscv isa')
diff --git a/src/arch/riscv/insts/bs.cc b/src/arch/riscv/insts/bs.cc
new file mode 100644
index 000..7a9e6e7
--- /dev/null
+++ b/src/arch/riscv/insts/bs.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/insts/bs.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+
+namespace gem5
+{
+
+namespace RiscvISA
+{
+
+std::string
+BSOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+registerName(srcRegIdx(0)) << ", " << registerName(srcRegIdx(1)) <<
+", " << (uint32_t)bs;
+return ss.str();
+}
+
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/bs.hh b/src/arch/riscv/insts/bs.hh
new file mode 100644
index 000..d4db5c9
--- /dev/null
+++ b/src/arch/riscv/insts/bs.hh
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Simplify the rev8 and brev8 instructions

2023-05-23 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70599?usp=email )


Change subject: arch-riscv: Simplify the rev8 and brev8 instructions
..

arch-riscv: Simplify the rev8 and brev8 instructions

These mnemonic of instructions should not have 'rv32_' prefix

Change-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70599
Reviewed-by: Yu-hsin Wang 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 18 insertions(+), 38 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 45e2946..ae2f0a4 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -667,44 +667,24 @@
 | (Rs1 << ((xlen - imm) & (xlen - 1;
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0xd: decode RS2 {
-0x18: decode BIT25 {
-0x0: rv32_rev8({{
-uint32_t result = 0;
-result |=
-((Rs1_uw & 0xffUL) << 24)
-| (((Rs1_uw >> 24) & 0xffUL));
-result |=
-(((Rs1_uw >> 8) & 0xffUL) << 16)
-| (((Rs1_uw >> 16) & 0xffUL) << 8);
-Rd = rvSext(result);
-}},
-imm_type = uint64_t, imm_code = {{ imm =  
SHAMT5; }});

-0x1: rev8({{
-uint64_t result = 0;
-result |=
-((Rs1 & 0xffULL) << 56)
-| (((Rs1 >> 56) & 0xffULL));
-result |=
-(((Rs1 >> 8) & 0xffULL) << 48)
-| (((Rs1 >> 48) & 0xffULL) << 8);
-result |=
-(((Rs1 >> 16) & 0xffULL) << 40)
-| (((Rs1 >> 40) & 0xffULL) << 16);
-result |=
-(((Rs1 >> 24) & 0xffULL) << 32)
-| (((Rs1 >> 32) & 0xffULL) << 24);
-Rd = result;
-}},
-imm_type = uint64_t, imm_code = {{ imm =  
SHAMT6; }});

-}
-0x07: decode RVTYPE {
-0x0: rv32_brev8({{
-Rd_sw = _rvk_emu_brev8_32(Rs1_sw);
-}}, imm_code = {{ imm = SHAMT5; }});
-0x1: brev8({{
-Rd = _rvk_emu_brev8_64(Rs1);
-}}, imm_code = {{ imm = SHAMT6; }});
-}
+0x18: ROp::rev8({{
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_grev_32(Rs1_sd, 0x18);
+} else {
+Rd_sd = _rvk_emu_grev_64(Rs1_sd, 0x38);
+}
+}});
+0x07: ROp::brev8({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_brev8_32(Rs1_sd);
+} else {
+Rd_sd = _rvk_emu_brev8_64(Rs1_sd);
+}
+}});
 }
 }
 0x6: ori({{

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957
Gerrit-Change-Number: 70599
Gerrit-PatchSet: 4
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
___

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8

2023-05-23 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70600?usp=email )


Change subject: arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8
..

arch-riscv: Merge rv32 and rv64 version of xperm4 and xperm8

Remove unessential postfix like '_32' and '_64' from mnemonic

Change-Id: I83d47eeccd04fe61ac8ee0addd7221abbdcefbd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70600
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 12 insertions(+), 14 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index ae2f0a4..c7eefbc 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1124,14 +1124,13 @@
 0x10: sh1add({{
 Rd = rvSext((Rs1 << 1) + Rs2);
 }});
-0x14: decode RVTYPE {
-0x0: xperm4_32({{
-Rd_sw = _rvk_emu_xperm4_32(Rs1_sw, Rs2_sw);
-}});
-0x1: xperm4_64({{
+0x14: xperm4({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_xperm4_32(Rs1_sd, Rs2_sd);
+} else {
 Rd_sd = _rvk_emu_xperm4_64(Rs1_sd, Rs2_sd);
-}});
-}
+}
+}});
 }
 0x3: decode FUNCT7 {
 0x0: sltu({{
@@ -1181,14 +1180,13 @@
 0x10: sh2add({{
 Rd = rvSext((Rs1 << 2) + Rs2);
 }});
-0x14: decode RVTYPE {
-0x0: xperm8_32({{
-Rd_sw = _rvk_emu_xperm8_32(Rs1_sw, Rs2_sw);
-}});
-0x1: xperm8_64({{
+0x14: xperm8({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_xperm8_32(Rs1_sd, Rs2_sd);
+} else {
 Rd_sd = _rvk_emu_xperm8_64(Rs1_sd, Rs2_sd);
-}});
-}
+}
+}});
 0x20: xnor({{
 Rd = rvSext(~(Rs1 ^ Rs2));
 }});

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Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

2023-05-22 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70597?usp=email )


Change subject: arch-riscv: Simplify amd merge RV32/RV64 the RVM  
instructions

..

arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

The change move the details implementation to utility.hh and merge
the RV32 and RV64 versions into one.

Change-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70597
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
Maintainer: Bobby Bruce 
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/utility.hh
2 files changed, 149 insertions(+), 183 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 3acd80e..47519ee 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1084,34 +1084,13 @@
 0x0: sll({{
 Rd = rvSext(Rs1 << rvSelect(Rs2<4:0>, Rs2<5:0>));
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulh({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_sw) >> 32;
-}}, IntMultOp);
-0x1: mulh({{
-bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
-
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
-uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd)  

32;

-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs2_lo*Rs1_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 :  
0)

-: res;
-}}, IntMultOp);
-}
+0x1: mulh({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulh_32(Rs1_sd, Rs2_sd);
+} else {
+Rd_sd = mulh_64(Rs1_sd, Rs2_sd);
+}
+}}, IntMultOp);
 0x5: clmul({{
 uint64_t result = 0;
 for (int i = 0; i < rvSelect(32, 64); i++) {
@@ -1144,32 +1123,13 @@
 0x0: slt({{
 Rd = (rvSext(Rs1_sd) < rvSext(Rs2_sd)) ? 1 : 0;
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulhsu({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_uw) >> 32;
-}}, IntMultOp);
-0x1: mulhsu({{
-bool negate = Rs1_sd < 0;
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)Rs2;
-uint64_t Rs2_hi = Rs2 >> 32;
-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs1_lo*Rs2_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 :  
0) : res;

-}}, IntMultOp);
-}
+0x1: mulhsu({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulhsu_32(Rs1_sd, Rs2);
+} else {
+Rd_sd = mulhsu_64(Rs1_sd, Rs2);
+}
+}}, IntMultOp);

[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Update riscv/fs_linux.py script

2023-05-21 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70177?usp=email )


Change subject: configs: Update riscv/fs_linux.py script
..

configs: Update riscv/fs_linux.py script

This change fixes a couple of small issues with
the configs/example/riscv/fs_linux.py script to ensure
that it works with the latest version of gem5.

Change-Id: I9753ca4c8dd0b87d05681b167cf51e3c097e9152
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70177
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Alex Richardson 
Tested-by: kokoro 
Reviewed-by: Roger Chang 
---
M configs/example/riscv/fs_linux.py
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Alex Richardson: Looks good to me, but someone else must approve
  Roger Chang: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/riscv/fs_linux.py  
b/configs/example/riscv/fs_linux.py

index aec126a..949c7e2 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -187,6 +187,7 @@
 # RTCCLK (Set to 100MHz for faster simulation)
 system.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
 system.platform.clint.int_pin = system.platform.rtc.int_pin
+system.platform.pci_host.pio = system.iobus.mem_side_ports

 # VirtIOMMIO
 if args.disk_image:
@@ -236,8 +237,6 @@
 clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain
 )

-system.workload.object_file = args.kernel
-
 # NOTE: Not yet tested
 if args.script is not None:
 system.readfile = args.script

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Gerrit-PatchSet: 2
Gerrit-Owner: Ayaz Akram 
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Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: merge rv32 and rv64 version of xperm4 and xperm8

2023-05-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70600?usp=email )



Change subject: arch-riscv: merge rv32 and rv64 version of xperm4 and xperm8
..

arch-riscv: merge rv32 and rv64 version of xperm4 and xperm8

Change-Id: I83d47eeccd04fe61ac8ee0addd7221abbdcefbd1
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 12 insertions(+), 14 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 1f78b32..acd2122 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1120,14 +1120,13 @@
 0x10: sh1add({{
 Rd = rvSext((Rs1 << 1) + Rs2);
 }});
-0x14: decode RVTYPE {
-0x0: xperm4_32({{
-Rd_sw = _rvk_emu_xperm4_32(Rs1_sw, Rs2_sw);
-}});
-0x1: xperm4_64({{
+0x14: xperm4({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_xperm4_32(Rs1_sd, Rs2_sd);
+} else {
 Rd_sd = _rvk_emu_xperm4_64(Rs1_sd, Rs2_sd);
-}});
-}
+}
+}});
 }
 0x3: decode FUNCT7 {
 0x0: sltu({{
@@ -1177,14 +1176,13 @@
 0x10: sh2add({{
 Rd = rvSext((Rs1 << 2) + Rs2);
 }});
-0x14: decode RVTYPE {
-0x0: xperm8_32({{
-Rd_sw = _rvk_emu_xperm8_32(Rs1_sw, Rs2_sw);
-}});
-0x1: xperm8_64({{
+0x14: xperm8({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_xperm8_32(Rs1_sd, Rs2_sd);
+} else {
 Rd_sd = _rvk_emu_xperm8_64(Rs1_sd, Rs2_sd);
-}});
-}
+}
+}});
 0x20: xnor({{
 Rd = rvSext(~(Rs1 ^ Rs2));
 }});

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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

2023-05-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70597?usp=email )



Change subject: arch-riscv: Simplify amd merge RV32/RV64 the RVM  
instructions

..

arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

The change move the details implementation to utility.hh and merge
the RV32 and RV64 versions into one.

Change-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/utility.hh
2 files changed, 149 insertions(+), 183 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index f22efb0..c9c815f 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1084,34 +1084,13 @@
 0x0: sll({{
 Rd = rvSext(Rs1 << rvSelect(Rs2<4:0>, Rs2<5:0>));
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulh({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_sw) >> 32;
-}}, IntMultOp);
-0x1: mulh({{
-bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
-
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
-uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd)  

32;

-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs2_lo*Rs1_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 :  
0)

-: res;
-}}, IntMultOp);
-}
+0x1: mulh({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulh_32(Rs1_sd, Rs2_sd);
+} else {
+Rd_sd = mulh_64(Rs1_sd, Rs2_sd);
+}
+}}, IntMultOp);
 0x5: clmul({{
 uint64_t result = 0;
 for (int i = 0; i < rvSelect(32, 64); i++) {
@@ -1144,32 +1123,13 @@
 0x0: slt({{
 Rd = (rvSext(Rs1_sd) < rvSext(Rs2_sd)) ? 1 : 0;
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulhsu({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_uw) >> 32;
-}}, IntMultOp);
-0x1: mulhsu({{
-bool negate = Rs1_sd < 0;
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)Rs2;
-uint64_t Rs2_hi = Rs2 >> 32;
-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs1_lo*Rs2_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 :  
0) : res;

-}}, IntMultOp);
-}
+0x1: mulhsu({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulhsu_32(Rs1_sd, Rs2);
+} else {
+Rd_sd = mulhsu_64(Rs1_sd, Rs2);
+}
+}}, IntMultOp);
 0x5: clmulr({{
 uint64_t result = 0;
 uint64_t xlen = rvSelect(32, 64);
@@ -1197,27 +1157,13 @@
 0x0: sltu({{
 Rd = (rvZext(Rs1) < rvZext(Rs2)) ? 1 : 0;

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: simply the rev8 and brev8 instruction

2023-05-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70599?usp=email )



Change subject: arch-riscv: simply the rev8 and brev8 instruction
..

arch-riscv: simply the rev8 and brev8 instruction

Change-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 14 insertions(+), 38 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 9c0cf45..1f78b32 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -667,44 +667,20 @@
 | (Rs1 << ((xlen - imm) & (xlen - 1;
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0xd: decode RS2 {
-0x18: decode BIT25 {
-0x0: rv32_rev8({{
-uint32_t result = 0;
-result |=
-((Rs1_uw & 0xffUL) << 24)
-| (((Rs1_uw >> 24) & 0xffUL));
-result |=
-(((Rs1_uw >> 8) & 0xffUL) << 16)
-| (((Rs1_uw >> 16) & 0xffUL) << 8);
-Rd = rvSext(result);
-}},
-imm_type = uint64_t, imm_code = {{ imm =  
SHAMT5; }});

-0x1: rev8({{
-uint64_t result = 0;
-result |=
-((Rs1 & 0xffULL) << 56)
-| (((Rs1 >> 56) & 0xffULL));
-result |=
-(((Rs1 >> 8) & 0xffULL) << 48)
-| (((Rs1 >> 48) & 0xffULL) << 8);
-result |=
-(((Rs1 >> 16) & 0xffULL) << 40)
-| (((Rs1 >> 40) & 0xffULL) << 16);
-result |=
-(((Rs1 >> 24) & 0xffULL) << 32)
-| (((Rs1 >> 32) & 0xffULL) << 24);
-Rd = result;
-}},
-imm_type = uint64_t, imm_code = {{ imm =  
SHAMT6; }});

-}
-0x07: decode RVTYPE {
-0x0: rv32_brev8({{
-Rd_sw = _rvk_emu_brev8_32(Rs1_sw);
-}}, imm_code = {{ imm = SHAMT5; }});
-0x1: brev8({{
-Rd = _rvk_emu_brev8_64(Rs1);
-}}, imm_code = {{ imm = SHAMT6; }});
-}
+0x18: ROp::rev8({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_grev_32(Rs1_sd, 0x18);
+} else {
+Rd_sd = _rvk_emu_grev_64(Rs1_sd, 0x38);
+}
+}});
+0x07: ROp::brev8({{
+if (machInst.rv_type == RV32) {
+Rd_sd = _rvk_emu_brev8_32(Rs1_sd);
+} else {
+Rd_sd = _rvk_emu_brev8_64(Rs1_sd);
+}
+}});
 }
 }
 0x6: ori({{

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Gerrit-Change-Id: Ic072ba8b84e5a51be060e5d7ca16dd913c318957
Gerrit-Change-Number: 70599
Gerrit-PatchSet: 1
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add BS format isa

2023-05-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70598?usp=email )



Change subject: arch-riscv: Add BS format isa
..

arch-riscv: Add BS format isa

This format is helper for aes32dsi, aes32dsmi, aes32esi, aes32esmi,
sm4ed, sm4ks disassembly

Change-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bs.cc
A src/arch/riscv/insts/bs.hh
M src/arch/riscv/isa/decoder.isa
A src/arch/riscv/isa/formats/bs.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 173 insertions(+), 12 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 80592a3..704152c 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -28,6 +28,7 @@
 Import('*')

 Source('amo.cc', tags='riscv isa')
+Source('bs.cc', tags='riscv isa')
 Source('compressed.cc', tags='riscv isa')
 Source('mem.cc', tags='riscv isa')
 Source('standard.cc', tags='riscv isa')
diff --git a/src/arch/riscv/insts/bs.cc b/src/arch/riscv/insts/bs.cc
new file mode 100644
index 000..7a9e6e7
--- /dev/null
+++ b/src/arch/riscv/insts/bs.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/insts/bs.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+
+namespace gem5
+{
+
+namespace RiscvISA
+{
+
+std::string
+BSOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+registerName(srcRegIdx(0)) << ", " << registerName(srcRegIdx(1)) <<
+", " << (uint32_t)bs;
+return ss.str();
+}
+
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/bs.hh b/src/arch/riscv/insts/bs.hh
new file mode 100644
index 000..7a063fb
--- /dev/null
+++ b/src/arch/riscv/insts/bs.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

2023-05-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email )


Change subject: arch-riscv: Add missing zbkb instructions
..

arch-riscv: Add missing zbkb instructions

Add the following instructions:
pack
packh
packw

Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70537
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 13 insertions(+), 7 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 6f66c98..755be3d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1282,11 +1282,13 @@
 }
 }}, IntDivOp);
 }
-0x4: decode RVTYPE {
-0x0: rv32_zext_h({{
-Rd = Rs1_uh;
-}});
-}
+0x4: pack({{
+int xlen = rvSelect(32, 64);
+Rd = rvSext(
+(bits(Rs2, xlen/2-1, 0) << (xlen / 2)) | \
+bits(Rs1, xlen/2-1, 0)
+);
+}});
 0x5: min({{
 Rd_sd = std::min(rvSext(Rs1_sd), rvSext(Rs2_sd));
 }});
@@ -1402,6 +1404,10 @@
 }
 }}, IntDivOp);
 }
+0x4: packh({{
+// It doesn't need to sign ext as MSB is always 0
+Rd = (Rs2_ub << 8) | Rs1_ub;
+}});
 0x5: maxu({{
 Rd = rvSext(std::max(rvZext(Rs1), rvZext(Rs2)));
 }});
@@ -1459,8 +1465,8 @@
 Rd_sd = Rs1_sw/Rs2_sw;
 }
 }}, IntDivOp);
-0x4: zext_h({{
-Rd = Rs1_uh;
+0x4: packw({{
+Rd_sd = sext<32>((Rs2_uh << 16) | Rs1_uh);
 }});
 0x10: sh2add_uw({{
 Rd = (((uint64_t)Rs1_uw) << 2) + Rs2;

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df
Gerrit-Change-Number: 70537
Gerrit-PatchSet: 2
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Yu-hsin Wang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Treat RVC HINT as nops rather than trap

2023-05-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70357?usp=email )


Change subject: arch-riscv: Treat RVC HINT as nops rather than trap
..

arch-riscv: Treat RVC HINT as nops rather than trap

The RVC HINT can be implemented as no-op to ignore them. See the
section 18.7 of RISC-V spec Volume I for more details

Change-Id: I88a62fd5722ac542ecfef5fcb80fef2ce04f010f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70357
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 10 insertions(+), 27 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 69b3055..d89a0c9 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -152,11 +152,9 @@
 }}, {{
 if ((RC1 == 0) != (imm == 0)) {
 if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-} else { // imm == 0
-return std::make_shared(
-"immediate = 0", machInst);
+// imm != 0 is HINT
+} else {
+// imm == 0 is HINT
 }
 }
 Rc1_sd = rvSext(Rc1_sd + imm);
@@ -179,10 +177,7 @@
 0x2: CIOp::c_li({{
 imm = sext<6>(CIMM5 | (CIMM1 << 5));
 }}, {{
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-}
+// RC1 == 0 is HINT
 Rc1_sd = imm;
 }});
 0x3: decode RC1 {
@@ -202,10 +197,7 @@
 default: CIOp::c_lui({{
 imm = sext<6>(CIMM5 | (CIMM1 << 5)) << 12;
 }}, {{
-if (RC1 == 0 || RC1 == 2) {
-return std::make_shared(
-"source reg x0", machInst);
-}
+// RC1 == 0 is HINT
 if (imm == 0) {
 return std::make_shared(
 "immediate = 0", machInst);
@@ -223,8 +215,7 @@
 "shmat[5] != 0", machInst);
 }
 if (imm == 0) {
-return std::make_shared(
-"immediate = 0", machInst);
+// C.SRLI64, HINT for RV32/RV64
 }
 // The MSB can never be 1, hence no need to sign ext.
 Rp1 = rvZext(Rp1) >> imm;
@@ -237,8 +228,7 @@
 "shmat[5] != 0", machInst);
 }
 if (imm == 0) {
-return std::make_shared(
-"immediate = 0", machInst);
+// C.SRAI64, HINT for RV32/RV64
 }
 Rp1_sd = rvSext(Rp1_sd) >> imm;
 }}, uint64_t);
@@ -306,13 +296,9 @@
 "shmat[5] != 0", machInst);
 }
 if (imm == 0) {
-return std::make_shared(
-"immediate = 0", machInst);
+// C.SLLI64, HINT for RV32/RV64
 }
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-}
+// RC1 == 0 is HINT
 Rc1 = rvSext(Rc1 << imm);
 }}, uint64_t);
 format CompressedLoad {
@@ -375,10 +361,7 @@
 NPC = rvZext(Rc1);
 }}, IsIndirectControl, IsUncondControl);
 default: CROp::c_mv({{
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-}
+// RC1 == 0 is HINT
 Rc1 = rvSext(Rc2);
 }});
 }

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Gerrit-Change-Number: 70357
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l fc...

2023-05-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70377?usp=email )


Change subject: arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu,  
fcvt_d_l fcvt_d_lu

..

arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l
fcvt_d_lu

These instructions use type casting methods to convert integer to
float, so the fflags couldn't trace the event of these. It should
use the function xx_to_f64 to convert from integer to float

Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 12 insertions(+), 4 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 755be3d..69b3055 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -2069,22 +2069,30 @@
 0x69: decode CONV_SGN {
 0x0: fcvt_d_w({{
 RM_REQUIRED;
-Fd = (double)Rs1_sw;
+freg_t fd;
+fd = freg(i32_to_f64(Rs1_sw));
+Fd_bits = fd.v;
 }}, FloatCvtOp);
 0x1: fcvt_d_wu({{
 RM_REQUIRED;
-Fd = (double)Rs1_uw;
+freg_t fd;
+fd = freg(ui32_to_f64(Rs1_uw));
+Fd_bits = fd.v;
 }}, FloatCvtOp);
 0x2: decode RVTYPE {
 0x1: fcvt_d_l({{
 RM_REQUIRED;
-Fd = (double)Rs1_sd;
+freg_t fd;
+fd = freg(i64_to_f64(Rs1_sd));
+Fd_bits = fd.v;
 }}, FloatCvtOp);
 }
 0x3: decode RVTYPE {
 0x1: fcvt_d_lu({{
 RM_REQUIRED;
-Fd = (double)Rs1;
+freg_t fd;
+fd = freg(ui64_to_f64(Rs1));
+Fd_bits = fd.v;
 }}, FloatCvtOp);
 }
 }

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Gerrit-MessageType: merged
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Gerrit-Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Gerrit-Change-Number: 70377
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Yu-hsin Wang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

2023-05-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70358?usp=email )


Change subject: arch-riscv: Refactor RVC decode flow when funct4==0b1001  
and op==C2

..

arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

the compressed instruction 0x901e (c.add zero, t2) should be decoded as
"c_add zero, t2" not c_ebreak

Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70358
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 11 insertions(+), 17 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d89a0c9..f22efb0 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -365,27 +365,21 @@
 Rc1 = rvSext(Rc2);
 }});
 }
-0x1: decode RC1 {
-0x0: SystemOp::c_ebreak({{
-if (RC2 != 0) {
-return std::make_shared(
-"source reg x1", machInst);
-}
-return  
std::make_shared(xc->pcState());

-}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
-default: decode RC2 {
-0x0: Jump::c_jalr({{
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-}
+0x1: decode RC2 {
+0x0: decode RC1 {
+0x0: SystemOp::c_ebreak({{
+return std::make_shared(
+xc->pcState());
+}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
+default: Jump::c_jalr({{
 ra = rvSext(NPC);
 NPC = rvZext(Rc1);
 }}, IsIndirectControl, IsUncondControl, IsCall);
-default: CompressedROp::c_add({{
-Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
-}});
 }
+default: CompressedROp::c_add({{
+// RC1 == 0 is HINT
+Rc1_sd = rvSext(Rc1_sd + Rc2_sd);
+}});
 }
 }
 format CompressedStore {

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Gerrit-Change-Number: 70358
Gerrit-PatchSet: 7
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
Gerrit-CC: Yu-hsin Wang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add missing zbkb instructions

2023-05-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70537?usp=email )



Change subject: arch-riscv: Add missing zbkb instructions
..

arch-riscv: Add missing zbkb instructions

Add the following instructions:
pack
packh
packw

Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 13 insertions(+), 7 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 6f66c98..755be3d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1282,11 +1282,13 @@
 }
 }}, IntDivOp);
 }
-0x4: decode RVTYPE {
-0x0: rv32_zext_h({{
-Rd = Rs1_uh;
-}});
-}
+0x4: pack({{
+int xlen = rvSelect(32, 64);
+Rd = rvSext(
+(bits(Rs2, xlen/2-1, 0) << (xlen / 2)) | \
+bits(Rs1, xlen/2-1, 0)
+);
+}});
 0x5: min({{
 Rd_sd = std::min(rvSext(Rs1_sd), rvSext(Rs2_sd));
 }});
@@ -1402,6 +1404,10 @@
 }
 }}, IntDivOp);
 }
+0x4: packh({{
+// It doesn't need to sign ext as MSB is always 0
+Rd = (Rs2_ub << 8) | Rs1_ub;
+}});
 0x5: maxu({{
 Rd = rvSext(std::max(rvZext(Rs1), rvZext(Rs2)));
 }});
@@ -1459,8 +1465,8 @@
 Rd_sd = Rs1_sw/Rs2_sw;
 }
 }}, IntDivOp);
-0x4: zext_h({{
-Rd = Rs1_uh;
+0x4: packw({{
+Rd_sd = sext<32>((Rs2_uh << 16) | Rs1_uh);
 }});
 0x10: sh2add_uw({{
 Rd = (((uint64_t)Rs1_uw) << 2) + Rs2;

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Gerrit-PatchSet: 1
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add RV32 only Zk instruction extensions

2023-05-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69937?usp=email )


Change subject: arch-riscv: Add RV32 only Zk instruction extensions
..

arch-riscv: Add RV32 only Zk instruction extensions

The following instructions is add:
Zbkb extension:
zip
unzip

Zknd extension:
aes32dsi
aes32dsmi

Zkne extension:
aes32esi
aes32esmi

Zknh extension:
sha512sig0h
sha512sig0l
sha512sig1h
sha512sig1l
sha512sum0r
sha512sum1r

Change-Id: Id29007704128154d9fb8305155f92c2e08ffa435
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69937
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Hoa Nguyen 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/rvk.hh
2 files changed, 114 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Hoa Nguyen: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index cb2b199..6f66c98 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -524,6 +524,11 @@
 }
 Rd = rvSext(Rs1 << imm);
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

+0x01: decode RVTYPE {
+0x0: zip({{
+Rd_sw = _rvk_emu_zip_32(Rs1_sw);
+}}, imm_code = {{ imm = SHAMT5; }});
+}
 0x02: decode FS2 {
 0x0: sha256sum0({{
 Rd_sw = _rvk_emu_sha256sum0(Rs1_sw);
@@ -643,6 +648,11 @@
 }
 Rd = rvSext(rvZext(Rs1) >> imm);
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

+0x1: decode RVTYPE {
+0x0: unzip({{
+Rd_sw = _rvk_emu_unzip_32(Rs1_sw);
+}}, imm_code = {{ imm = SHAMT5; }});
+}
 0x5: orc_b({{
 uint64_t result = 0;
 result |= (Rs1<7:0> ? UINT64_C(0xff) : 0x0);
@@ -991,6 +1001,68 @@
 Rd = rvSext(Rs1_sd * Rs2_sd);
 }}, IntMultOp);
 }
+0x08: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sum0r({{
+Rd_sw = _rvk_emu_sha512sum0r(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x09: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sum1r({{
+Rd_sw = _rvk_emu_sha512sum1r(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x0a: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sig0l({{
+Rd_sw = _rvk_emu_sha512sig0l(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x0b: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sig1l({{
+Rd_sw = _rvk_emu_sha512sig1l(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x0e: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sig0h({{
+Rd_sw = _rvk_emu_sha512sig0h(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x0f: decode BS {
+0x1: decode RVTYPE {
+0x0: sha512sig1h({{
+Rd_sw = _rvk_emu_sha512sig1h(Rs1_sw,  
Rs2_sw);

+}});
+}
+}
+0x11: decode RVTYPE {
+0x0: aes32esi({{
+Rd_sw = _rvk_emu_aes32esi(Rs1_sw, Rs2_sw,  
(uint8_t)BS);

+}});
+}
+0x13: decode RVTYPE {
+0x0: aes32esmi({{
+Rd_sw = _rvk_emu_aes32esmi(Rs1_sw, Rs2_sw,  
(uint8_t)BS);

+}});
+}
+0x15: decode RVTYPE {
+0x0: aes32dsi({{
+Rd_sw = _rvk_emu_aes32dsi(Rs1_sw, Rs2_sw,  
(uint8_t)BS);

+}});
+}
+

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: seperate RV32 and RV64 Zk extensions

2023-05-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66191?usp=email )


Change subject: arch-riscv: seperate RV32 and RV64 Zk extensions
..

arch-riscv: seperate RV32 and RV64 Zk extensions

1. If the instruction is RV64 only, such as zknd(aes64ds, aes64dsm,
   aes64im, aes64ks1i, and aes64ks2), zkne(aes64es, aes64esm,
   aes64ks1i, aes64ks2), Zknh(sha512sig0, sha512sig1, sha512sum0,
   sha512sum1). The decoder should check rv_type before returning
   the instruction.

2. For the Zbkx(xperm8 and xperm4), I seperate them with RV32 and
   RV64 respectively, since the xperm function has individual
   implement for handling different size of integer.

3. Add the brev8(zbkb) instruction

Change-Id: Id0b7ab2772fd1b21c1ee41075df44a5b6dbe5b47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66191
Reviewed-by: Hoa Nguyen 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 82 insertions(+), 42 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Hoa Nguyen: Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 58958bb..cb2b199 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -537,18 +537,26 @@
 0x3: sha256sig1({{
 Rd_sw = _rvk_emu_sha256sig1(Rs1_sw);
 }});
-0x4: sha512sum0({{
-Rd_sd = _rvk_emu_sha512sum0(Rs1_sd);
-}});
-0x5: sha512sum1({{
-Rd_sd = _rvk_emu_sha512sum1(Rs1_sd);
-}});
-0x6: sha512sig0({{
-Rd_sd = _rvk_emu_sha512sig0(Rs1_sd);
-}});
-0x7: sha512sig1({{
-Rd_sd = _rvk_emu_sha512sig1(Rs1_sd);
-}});
+0x4: decode RVTYPE {
+0x1: sha512sum0({{
+Rd_sd = _rvk_emu_sha512sum0(Rs1_sd);
+}});
+}
+0x5: decode RVTYPE {
+0x1: sha512sum1({{
+Rd_sd = _rvk_emu_sha512sum1(Rs1_sd);
+}});
+}
+0x6: decode RVTYPE {
+0x1: sha512sig0({{
+Rd_sd = _rvk_emu_sha512sig0(Rs1_sd);
+}});
+}
+0x7: decode RVTYPE {
+0x1: sha512sig1({{
+Rd_sd = _rvk_emu_sha512sig1(Rs1_sd);
+}});
+}
 0x8: sm3p0({{
 Rd_sw = _rvk_emu_sm3p0(Rs1_sw);
 }});
@@ -565,12 +573,16 @@
 Rd = rvSext(Rs1 | (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x06: decode BIT24 {
-0x0: aes64im({{
-Rd_sd = _rvk_emu_aes64im(Rs1_sd);
-}});
-0x1: aes64ks1i({{
-Rd_sd = _rvk_emu_aes64ks1i(Rs1_sd, imm);
-}}, imm_type = int32_t, imm_code={{ imm = RNUM;  
}});

+0x0: decode RVTYPE {
+0x1: aes64im({{
+Rd_sd = _rvk_emu_aes64im(Rs1_sd);
+}});
+}
+0x1: decode RVTYPE {
+0x1: aes64ks1i({{
+Rd_sd = _rvk_emu_aes64ks1i(Rs1_sd, imm);
+}}, imm_type = int32_t, imm_code={{ imm =  
RNUM; }});

+}
 }
 0x09: bclri({{
 if (rvSelect((bool)SHAMT6BIT5, false)) {
@@ -698,6 +710,14 @@
 }},
 imm_type = uint64_t, imm_code = {{ imm =  
SHAMT6; }});

 }
+0x07: decode RVTYPE {
+0x0: rv32_brev8({{
+Rd_sw = _rvk_emu_brev8_32(Rs1_sw);
+}}, imm_code = {{ imm = SHAMT5; }});
+0x1: brev8({{
+Rd = _rvk_emu_brev8_64(Rs1);
+}}, imm_code = {{ imm = SHAMT6; }});
+}

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Remove Riscv32CPU instance

2023-04-27 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66871?usp=email )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Remove Riscv32CPU instance
..

arch-riscv: Remove Riscv32CPU instance

To use riscv 32 bits CPU, we can simply speficy by RiscvXXXCPU
   parameters like
   RiscvAtomicSimpleCPU(isa=RiscvISA(riscv_type="RV32"...))

Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66871
Reviewed-by: Jui-min Lee 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/RiscvCPU.py
1 file changed, 0 insertions(+), 29 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jui-min Lee: Looks good to me, but someone else must approve
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved




diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py
index 678c329..1c77045 100644
--- a/src/arch/riscv/RiscvCPU.py
+++ b/src/arch/riscv/RiscvCPU.py
@@ -23,8 +23,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-import functools
-
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
 from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
 from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
@@ -43,13 +41,6 @@
 ArchISA = RiscvISA


-class Riscv32CPU:
-ArchDecoder = RiscvDecoder
-ArchMMU = RiscvMMU
-ArchInterrupts = RiscvInterrupts
-ArchISA = functools.partial(RiscvISA, riscv_type="RV32")
-
-
 class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
 mmu = RiscvMMU()

@@ -68,23 +59,3 @@

 class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
 mmu = RiscvMMU()
-
-
-class Riscv32AtomicSimpleCPU(BaseAtomicSimpleCPU, Riscv32CPU):
-mmu = RiscvMMU()
-
-
-class Riscv32NonCachingSimpleCPU(BaseNonCachingSimpleCPU, Riscv32CPU):
-mmu = RiscvMMU()
-
-
-class Riscv32TimingSimpleCPU(BaseTimingSimpleCPU, Riscv32CPU):
-mmu = RiscvMMU()
-
-
-class Riscv32O3CPU(BaseO3CPU, Riscv32CPU):
-mmu = RiscvMMU()
-
-
-class Riscv32MinorCPU(BaseMinorCPU, Riscv32CPU):
-mmu = RiscvMMU()

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5
Gerrit-Change-Number: 66871
Gerrit-PatchSet: 11
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-CC: Jason Lowe-Power 
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[gem5-dev] [L] Change in gem5/gem5[develop]: tests: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

2023-04-27 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70097?usp=email )


Change subject: tests: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction  
tests"

..

tests: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

This reverts https://gem5-review.googlesource.com/c/public/gem5/+/65533

This is early version support RV32 instruction tests. We should directly
set isa feature of RiscvCPU to run RV32 instruction not just choose
Riscv32CPU

Change-Id: I51b744e9d827adfabc2a7c222ab3801d454601d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70097
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
---
M tests/gem5/asmtest/tests.py
M tests/gem5/configs/simple_binary_run.py
2 files changed, 160 insertions(+), 211 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index 0ddffb2..b2a5992 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -34,159 +34,156 @@
 # The following lists the RISCV binaries. Those commented out presently  
result

 # in a test failure. This is outlined in the following Jira issue:
 # https://gem5.atlassian.net/browse/GEM5-496
-binary_configs = (
-("rv{}samt-ps-sysclone_d", (64,)),
-("rv{}samt-ps-sysfutex1_d", (64,)),
+binaries = (
+"rv64samt-ps-sysclone_d",
+"rv64samt-ps-sysfutex1_d",
 #'rv64samt-ps-sysfutex2_d',
-("rv{}samt-ps-sysfutex3_d", (64,)),
+"rv64samt-ps-sysfutex3_d",
 #'rv64samt-ps-sysfutex_d',
-("rv{}ua-ps-amoadd_d", (64,)),
-("rv{}ua-ps-amoadd_w", (32, 64)),
-("rv{}ua-ps-amoand_d", (64,)),
-("rv{}ua-ps-amoand_w", (32, 64)),
-("rv{}ua-ps-amomax_d", (64,)),
-("rv{}ua-ps-amomax_w", (32, 64)),
-("rv{}ua-ps-amomaxu_d", (64,)),
-("rv{}ua-ps-amomaxu_w", (32, 64)),
-("rv{}ua-ps-amomin_d", (64,)),
-("rv{}ua-ps-amomin_w", (32, 64)),
-("rv{}ua-ps-amominu_d", (64,)),
-("rv{}ua-ps-amominu_w", (32, 64)),
-("rv{}ua-ps-amoor_d", (64,)),
-("rv{}ua-ps-amoor_w", (32, 64)),
-("rv{}ua-ps-amoswap_d", (64,)),
-("rv{}ua-ps-amoswap_w", (32, 64)),
-("rv{}ua-ps-amoxor_d", (64,)),
-("rv{}ua-ps-amoxor_w", (32, 64)),
-("rv{}ua-ps-lrsc", (32, 64)),
-("rv{}uamt-ps-amoadd_d", (64,)),
-("rv{}uamt-ps-amoand_d", (64,)),
-("rv{}uamt-ps-amomax_d", (64,)),
-("rv{}uamt-ps-amomaxu_d", (64,)),
-("rv{}uamt-ps-amomin_d", (64,)),
-("rv{}uamt-ps-amominu_d", (64,)),
-("rv{}uamt-ps-amoor_d", (64,)),
-("rv{}uamt-ps-amoswap_d", (64,)),
-("rv{}uamt-ps-amoxor_d", (64,)),
-("rv{}uamt-ps-lrsc_d", (64,)),
-("rv{}uamt-ps-amoadd_w", (32,)),
-("rv{}uamt-ps-amoand_w", (32,)),
-("rv{}uamt-ps-amomax_w", (32,)),
-("rv{}uamt-ps-amomaxu_w", (32,)),
-("rv{}uamt-ps-amomin_w", (32,)),
-("rv{}uamt-ps-amominu_w", (32,)),
-("rv{}uamt-ps-amoor_w", (32,)),
-("rv{}uamt-ps-amoswap_w", (32,)),
-("rv{}uamt-ps-amoxor_w", (32,)),
-("rv{}uamt-ps-lrsc_w", (32,)),
-("rv{}ud-ps-fadd", (32, 64)),
-("rv{}ud-ps-fclass", (32, 64)),
-("rv{}ud-ps-fcmp", (32, 64)),
-("rv{}ud-ps-fcvt", (32, 64)),
-("rv{}ud-ps-fcvt_w", (32, 64)),
-("rv{}ud-ps-fdiv", (32, 64)),
-("rv{}ud-ps-fmadd", (32, 64)),
-("rv{}ud-ps-fmin", (32, 64)),
-("rv{}ud-ps-ldst", (32, 64)),
-("rv{}ud-ps-move", (64,)),
-("rv{}ud-ps-recoding", (32, 64)),
-("rv{}ud-ps-structural", (64,)),
-("rv{}uf-ps-fadd", (32, 64)),
-("rv{}uf-ps-fclass", (32, 64)),
-("rv{}uf-ps-fcmp", (32, 64)),
-("rv{}uf-ps-fcvt", (32, 64)),
-("rv{}uf-ps-fcvt_w", (32, 64)),
-("rv{}uf-ps-fdiv", (32, 64)),
-("rv{}uf-ps-fmadd", (32, 64)),
-("rv{}uf-ps-fmin", (32, 64)),
-("rv{}uf-ps-ldst", (32, 64)),
-("rv{}uf-ps-move", (32, 64)),
-("rv{}uf-ps-recoding", (32, 64)),
-("rv{}ui-ps-add", (32, 64)),
-("rv{}ui-ps-addi", (32, 64)),
-("rv{}ui-ps-addiw", (64,)),
-("rv{}ui-ps-addw", (64,)),
-("rv{}ui-ps-and", (32, 64)),
-("rv{}ui-ps-andi", (32, 64)),
-("rv{}ui-ps-auipc", (32, 64)),
-("rv{}ui-ps-beq", (32, 64)),
-("rv{}ui-ps-bge", (32, 64)),
-("rv{}ui-ps-bgeu", (32, 64)),
-("rv{}ui-ps-blt", (32, 64)),
-("rv{}ui-ps-bltu", (32, 64)),
-("rv{}ui-ps-bne", (32, 64)),
-("rv{}ui-ps-fence_i", (32, 64)),
-("rv{}ui-ps-jal", (32, 64)),
-("rv{}ui-ps-jalr", (32, 64)),
-("rv{}ui-ps-lb", (32, 64)),
-("rv{}ui-ps-lbu", (32, 64)),
-("rv{}ui-ps-ld", (64,)),
-("rv{}ui-ps-lh", (32, 64)),
-("rv{}ui-ps-lhu", (32, 64)),
-("rv{}ui-ps-lui", (32, 64)),
-("rv{}ui-ps-lw", (32, 64)),
-("rv{}ui-ps-lwu", (64,)),
-("rv{}ui-ps-or", (32, 64)),
-("rv{}ui-ps-ori", (32, 64)),
-("rv{}ui-ps-sb", (32, 64)),
-("rv{}ui-ps-sd", (64,)),
-("rv{}ui-ps-sh", (32, 64)),
-

[gem5-dev] [L] Change in gem5/gem5[develop]: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

2023-04-26 Thread Roger Chang (Gerrit) via gem5-dev


Attention is currently required from: Bobby Bruce, Yu-hsin Wang.

Hello kokoro, Bobby Bruce, Yu-hsin Wang,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70097?usp=email

to review the following change.


Change subject: Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"
..

Revert "arch-riscv: add RV32 ADFIMU_Zfh instruction tests"

This reverts commit 083566d0c82d2610b246b0b5ad903766e336ac31.

Reason for revert: Remove the additional RV32 tests

This is early version support RV32 instruction tests. To enable run RV32  
instruction. We select Riscv32AtomicSimpleCPU, Riscv32TimingSimpleCPU and  
so on to run RV32 instruction. We should directly set isa feature of  
RiscvCPU to run RV32 instruction


Change-Id: I51b744e9d827adfabc2a7c222ab3801d454601d1
---
M tests/gem5/asmtest/tests.py
M tests/gem5/configs/simple_binary_run.py
2 files changed, 160 insertions(+), 211 deletions(-)



diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index 0ddffb2..b2a5992 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -34,159 +34,156 @@
 # The following lists the RISCV binaries. Those commented out presently  
result

 # in a test failure. This is outlined in the following Jira issue:
 # https://gem5.atlassian.net/browse/GEM5-496
-binary_configs = (
-("rv{}samt-ps-sysclone_d", (64,)),
-("rv{}samt-ps-sysfutex1_d", (64,)),
+binaries = (
+"rv64samt-ps-sysclone_d",
+"rv64samt-ps-sysfutex1_d",
 #'rv64samt-ps-sysfutex2_d',
-("rv{}samt-ps-sysfutex3_d", (64,)),
+"rv64samt-ps-sysfutex3_d",
 #'rv64samt-ps-sysfutex_d',
-("rv{}ua-ps-amoadd_d", (64,)),
-("rv{}ua-ps-amoadd_w", (32, 64)),
-("rv{}ua-ps-amoand_d", (64,)),
-("rv{}ua-ps-amoand_w", (32, 64)),
-("rv{}ua-ps-amomax_d", (64,)),
-("rv{}ua-ps-amomax_w", (32, 64)),
-("rv{}ua-ps-amomaxu_d", (64,)),
-("rv{}ua-ps-amomaxu_w", (32, 64)),
-("rv{}ua-ps-amomin_d", (64,)),
-("rv{}ua-ps-amomin_w", (32, 64)),
-("rv{}ua-ps-amominu_d", (64,)),
-("rv{}ua-ps-amominu_w", (32, 64)),
-("rv{}ua-ps-amoor_d", (64,)),
-("rv{}ua-ps-amoor_w", (32, 64)),
-("rv{}ua-ps-amoswap_d", (64,)),
-("rv{}ua-ps-amoswap_w", (32, 64)),
-("rv{}ua-ps-amoxor_d", (64,)),
-("rv{}ua-ps-amoxor_w", (32, 64)),
-("rv{}ua-ps-lrsc", (32, 64)),
-("rv{}uamt-ps-amoadd_d", (64,)),
-("rv{}uamt-ps-amoand_d", (64,)),
-("rv{}uamt-ps-amomax_d", (64,)),
-("rv{}uamt-ps-amomaxu_d", (64,)),
-("rv{}uamt-ps-amomin_d", (64,)),
-("rv{}uamt-ps-amominu_d", (64,)),
-("rv{}uamt-ps-amoor_d", (64,)),
-("rv{}uamt-ps-amoswap_d", (64,)),
-("rv{}uamt-ps-amoxor_d", (64,)),
-("rv{}uamt-ps-lrsc_d", (64,)),
-("rv{}uamt-ps-amoadd_w", (32,)),
-("rv{}uamt-ps-amoand_w", (32,)),
-("rv{}uamt-ps-amomax_w", (32,)),
-("rv{}uamt-ps-amomaxu_w", (32,)),
-("rv{}uamt-ps-amomin_w", (32,)),
-("rv{}uamt-ps-amominu_w", (32,)),
-("rv{}uamt-ps-amoor_w", (32,)),
-("rv{}uamt-ps-amoswap_w", (32,)),
-("rv{}uamt-ps-amoxor_w", (32,)),
-("rv{}uamt-ps-lrsc_w", (32,)),
-("rv{}ud-ps-fadd", (32, 64)),
-("rv{}ud-ps-fclass", (32, 64)),
-("rv{}ud-ps-fcmp", (32, 64)),
-("rv{}ud-ps-fcvt", (32, 64)),
-("rv{}ud-ps-fcvt_w", (32, 64)),
-("rv{}ud-ps-fdiv", (32, 64)),
-("rv{}ud-ps-fmadd", (32, 64)),
-("rv{}ud-ps-fmin", (32, 64)),
-("rv{}ud-ps-ldst", (32, 64)),
-("rv{}ud-ps-move", (64,)),
-("rv{}ud-ps-recoding", (32, 64)),
-("rv{}ud-ps-structural", (64,)),
-("rv{}uf-ps-fadd", (32, 64)),
-("rv{}uf-ps-fclass", (32, 64)),
-("rv{}uf-ps-fcmp", (32, 64)),
-("rv{}uf-ps-fcvt", (32, 64)),
-("rv{}uf-ps-fcvt_w", (32, 64)),
-("rv{}uf-ps-fdiv", (32, 64)),
-("rv{}uf-ps-fmadd", (32, 64)),
-("rv{}uf-ps-fmin", (32, 64)),
-("rv{}uf-ps-ldst", (32, 64)),
-("rv{}uf-ps-move", (32, 64)),
-("rv{}uf-ps-recoding", (32, 64)),
-("rv{}ui-ps-add", (32, 64)),
-("rv{}ui-ps-addi", (32, 64)),
-("rv{}ui-ps-addiw", (64,)),
-("rv{}ui-ps-addw", (64,)),
-("rv{}ui-ps-and", (32, 64)),
-("rv{}ui-ps-andi", (32, 64)),
-("rv{}ui-ps-auipc", (32, 64)),
-("rv{}ui-ps-beq", (32, 64)),
-("rv{}ui-ps-bge", (32, 64)),
-("rv{}ui-ps-bgeu", (32, 64)),
-("rv{}ui-ps-blt", (32, 64)),
-("rv{}ui-ps-bltu", (32, 64)),
-("rv{}ui-ps-bne", (32, 64)),
-("rv{}ui-ps-fence_i", (32, 64)),
-("rv{}ui-ps-jal", (32, 64)),
-("rv{}ui-ps-jalr", (32, 64)),
-("rv{}ui-ps-lb", (32, 64)),
-("rv{}ui-ps-lbu", (32, 64)),
-("rv{}ui-ps-ld", (64,)),
-("rv{}ui-ps-lh", (32, 64)),
-("rv{}ui-ps-lhu", (32, 64)),
-("rv{}ui-ps-lui", (32, 64)),
-("rv{}ui-ps-lw", (32, 64)),
-("rv{}ui-ps-lwu", (64,)),
-("rv{}ui-ps-or", (32, 64)),
-("rv{}ui-ps-ori", (32, 64)),
-("rv{}ui-ps-sb", (32, 64)),
-("rv{}ui-ps-sd", (64,)),
-

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: refactor bitfields of insts

2023-04-25 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68417?usp=email )


Change subject: arch-riscv: refactor bitfields of insts
..

arch-riscv: refactor bitfields of insts

+ move bitfields of ExtMachInst defined in bitfields.hh
  to types.hh

Change-Id: Ic25e2fd1a887f87231268a4449d8755593919a0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68417
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Hoa Nguyen 
Reviewed-by: Roger Chang 
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/insts/amo.cc
D src/arch/riscv/insts/bitfields.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/types.hh
M util/m5/src/abi/riscv/m5op.S
10 files changed, 151 insertions(+), 55 deletions(-)

Approvals:
  Roger Chang: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Hoa Nguyen: Looks good to me, approved




diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index b816c17..7faa310 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -42,6 +42,7 @@
 {
 aligned = true;
 mid = false;
+machInst = 0;
 emi = 0;
 }

@@ -58,20 +59,20 @@

 bool aligned = pc.instAddr() % sizeof(machInst) == 0;
 if (aligned) {
-emi = inst;
-if (compressed(emi))
-emi = bits(emi, mid_bit, 0);
+emi.instBits = inst;
+if (compressed(inst))
+emi.instBits = bits(inst, mid_bit, 0);
 outOfBytes = !compressed(emi);
 instDone = true;
 } else {
 if (mid) {
-assert(bits(emi, max_bit, mid_bit + 1) == 0);
-replaceBits(emi, max_bit, mid_bit + 1, inst);
+assert(bits(emi.instBits, max_bit, mid_bit + 1) == 0);
+replaceBits(emi.instBits, max_bit, mid_bit + 1, inst);
 mid = false;
 outOfBytes = false;
 instDone = true;
 } else {
-emi = bits(inst, max_bit, mid_bit + 1);
+emi.instBits = bits(inst, max_bit, mid_bit + 1);
 mid = !compressed(emi);
 outOfBytes = true;
 instDone = compressed(emi);
@@ -83,7 +84,7 @@
 Decoder::decode(ExtMachInst mach_inst, Addr addr)
 {
 DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
-mach_inst, addr);
+mach_inst.instBits, addr);

 StaticInstPtr  = instMap[mach_inst];
 if (!si)
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index d845c91..052586e 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -32,7 +32,6 @@
 #include 
 #include 

-#include "arch/riscv/insts/bitfields.hh"
 #include "arch/riscv/utility.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
@@ -49,7 +48,7 @@
 Addr pc, const loader::SymbolTable *symtab) const
 {
 std::stringstream ss;
-ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
+ss << csprintf("0x%08x", machInst.instBits) << ' ' << mnemonic;
 return ss.str();
 }

@@ -66,14 +65,14 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", ("
+<< registerName(intRegClass[machInst.rs1]) << ')';
 return ss.str();
 }

@@ -94,15 +93,15 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", "
-<< registerName(intRegClass[RS2]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", "
+<< registerName(intRegClass[machInst.rs2]) << ", ("
+<< registerName(intRegClass[machInst.rs1]) << ')';
 return ss.str();
 }

@@ -124,15 +123,15 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", "
-<< registerName(intRegClass[RS2]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", "
+<< registerName(intRegClass[machInst.rs2]) << ", ("
+<<

[gem5-dev] [S] Change in gem5/gem5[develop]: arch: Add vector function unit and OpClass enums

2023-04-25 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67293?usp=email )


Change subject: arch: Add vector function unit and OpClass enums
..

arch: Add vector function unit and OpClass enums

These enums are needed for risc-v vector extension

Change-Id: Ia61682c43c89ac2043fb9d1d5c349dfd646fb88d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67293
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Hoa Nguyen 
Reviewed-by: Roger Chang 
---
M src/cpu/FuncUnit.py
M src/cpu/op_class.hh
2 files changed, 43 insertions(+), 0 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Roger Chang: Looks good to me, approved




diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 4a2733a..a1050de 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -98,6 +98,25 @@
 "FloatMemWrite",
 "IprAccess",
 "InstPrefetch",
+"VectorUnitStrideLoad",
+"VectorUnitStrideStore",
+"VectorUnitStrideMaskLoad",
+"VectorUnitStrideMaskStore",
+"VectorStridedLoad",
+"VectorStridedStore",
+"VectorIndexedLoad",
+"VectorIndexedStore",
+"VectorUnitStrideFaultOnlyFirstLoad",
+"VectorWholeRegisterLoad",
+"VectorWholeRegisterStore",
+"VectorIntegerArith",
+"VectorFloatArith",
+"VectorFloatConvert",
+"VectorIntegerReduce",
+"VectorFloatReduce",
+"VectorMisc",
+"VectorIntegerExtension",
+"VectorConfig",
 ]


diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 4de018f..94d2794 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -108,6 +108,30 @@
 static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
 static const OpClass IprAccessOp = enums::IprAccess;
 static const OpClass InstPrefetchOp = enums::InstPrefetch;
+static const OpClass VectorUnitStrideLoadOp = enums::VectorUnitStrideLoad;
+static const OpClass VectorUnitStrideStoreOp =  
enums::VectorUnitStrideStore;

+static const OpClass VectorUnitStrideMaskLoadOp
+ = enums::VectorUnitStrideMaskLoad;
+static const OpClass VectorUnitStrideMaskStoreOp
+ = enums::VectorUnitStrideMaskStore;
+static const OpClass VectorStridedLoadOp = enums::VectorStridedLoad;
+static const OpClass VectorStridedStoreOp = enums::VectorStridedStore;
+static const OpClass VectorIndexedLoadOp = enums::VectorIndexedLoad;
+static const OpClass VectorIndexedStoreOp = enums::VectorIndexedStore;
+static const OpClass VectorUnitStrideFaultOnlyFirstLoadOp
+ = enums::VectorUnitStrideFaultOnlyFirstLoad;
+static const OpClass VectorWholeRegisterLoadOp
+ = enums::VectorWholeRegisterLoad;
+static const OpClass VectorWholeRegisterStoreOp
+ = enums::VectorWholeRegisterStore;
+static const OpClass VectorIntegerArithOp = enums::VectorIntegerArith;
+static const OpClass VectorFloatArithOp = enums::VectorFloatArith;
+static const OpClass VectorFloatConvertOp = enums::VectorFloatConvert;
+static const OpClass VectorIntegerReduceOp = enums::VectorIntegerReduce;
+static const OpClass VectorFloatReduceOp = enums::VectorFloatReduce;
+static const OpClass VectorMiscOp = enums::VectorMisc;
+static const OpClass VectorIntegerExtensionOp =  
enums::VectorIntegerExtension;

+static const OpClass VectorConfigOp = enums::VectorConfig;
 static const OpClass Num_OpClasses = enums::Num_OpClass;

 } // namespace gem5

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia61682c43c89ac2043fb9d1d5c349dfd646fb88d
Gerrit-Change-Number: 67293
Gerrit-PatchSet: 8
Gerrit-Owner: 轩胡 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Giacomo Travaglini 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of bootloader into debug symbol table...

2023-04-12 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email )


Change subject: arch-riscv: Insert symbol table of bootloader into debug  
symbol table in bare metal workload

..

arch-riscv: Insert symbol table of bootloader into debug symbol table
in bare metal workload

Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69697
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/bare_metal/fs_workload.cc
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/bare_metal/fs_workload.cc  
b/src/arch/riscv/bare_metal/fs_workload.cc

index 4f7adb3..574c944 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -47,6 +47,8 @@
 fatal_if(!bootloader, "Could not load bootloader file %s.",  
p.bootloader);

 _resetVect = bootloader->entryPoint();
 bootloaderSymtab = bootloader->symtab();
+
+loader::debugSymbolTable.insert(bootloaderSymtab);
 }

 BareMetal::~BareMetal()

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
Gerrit-Change-Number: 69697
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of into debug symbol table

2023-04-12 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email )



Change subject: arch-riscv: Insert symbol table of into debug symbol table
..

arch-riscv: Insert symbol table of into debug symbol table

Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
---
M src/arch/riscv/bare_metal/fs_workload.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/bare_metal/fs_workload.cc  
b/src/arch/riscv/bare_metal/fs_workload.cc

index 4f7adb3..574c944 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -47,6 +47,8 @@
 fatal_if(!bootloader, "Could not load bootloader file %s.",  
p.bootloader);

 _resetVect = bootloader->entryPoint();
 bootloaderSymtab = bootloader->symtab();
+
+loader::debugSymbolTable.insert(bootloaderSymtab);
 }

 BareMetal::~BareMetal()

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor the shouldCheckPMP function

2023-04-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69497?usp=email )


Change subject: arch-riscv: Refactor the shouldCheckPMP function
..

arch-riscv: Refactor the shouldCheckPMP function

The shouldCheckPMP can be simply with pmode != PRV_M since the
privilege mode of memory is modified by TLB and Walker. The
numRules check can done in shouldPMPCheck

Change-Id: I842687674fed7bc4d88a9ba6b4c4d52c3459068f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69497
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/pmp.cc
M src/arch/riscv/pmp.hh
2 files changed, 11 insertions(+), 28 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved




diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 6275104..8fa1ca3 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -59,7 +59,7 @@
   Addr vaddr)
 {
 // First determine if pmp table should be consulted
-if (!shouldCheckPMP(pmode, mode, tc))
+if (!shouldCheckPMP(pmode, tc))
 return NoFault;

 if (req->hasVaddr()) {
@@ -71,9 +71,6 @@
 req->getPaddr());
 }

-if (numRules == 0)
-return NoFault;
-
 // match_index will be used to identify the pmp entry
 // which matched for the given address
 int match_index = -1;
@@ -273,26 +270,14 @@
 }

 bool
-PMP::shouldCheckPMP(RiscvISA::PrivilegeMode pmode,
-BaseMMU::Mode mode, ThreadContext *tc)
+PMP::shouldCheckPMP(RiscvISA::PrivilegeMode pmode, ThreadContext *tc)
 {
-// instruction fetch in S and U mode
-bool cond1 = (mode == BaseMMU::Execute &&
-(pmode != RiscvISA::PrivilegeMode::PRV_M));
-
-// data access in S and U mode when MPRV in mstatus is clear
-RiscvISA::STATUS status =
-tc->readMiscRegNoEffect(RiscvISA::MISCREG_STATUS);
-bool cond2 = (mode != BaseMMU::Execute &&
- (pmode != RiscvISA::PrivilegeMode::PRV_M)
- && (!status.mprv));
-
-// data access in any mode when MPRV bit in mstatus is set
-// and the MPP field in mstatus is S or U
-bool cond3 = (mode != BaseMMU::Execute && (status.mprv)
-&& (status.mpp != RiscvISA::PrivilegeMode::PRV_M));
-
-return (cond1 || cond2 || cond3 || hasLockEntry);
+// The privilege mode of memory read and write
+// is modified by TLB. It can just simply check if
+// the numRule is not zero, then return true if
+// privilege mode is not M or has any lock entry
+return numRules != 0 && (
+pmode != RiscvISA::PrivilegeMode::PRV_M || hasLockEntry);
 }

 AddrRange
diff --git a/src/arch/riscv/pmp.hh b/src/arch/riscv/pmp.hh
index 24cb4ad..ff8c4fc 100644
--- a/src/arch/riscv/pmp.hh
+++ b/src/arch/riscv/pmp.hh
@@ -118,7 +118,7 @@
  * is allowed based on the pmp rules.
  * @param req memory request.
  * @param mode mode of request (read, write, execute).
- * @param pmode current privilege mode of execution (U, S, M).
+ * @param pmode current privilege mode of memory (U, S, M).
  * @param tc thread context.
  * @param vaddr optional parameter to pass vaddr of original
  * request for which a page table walk is consulted by pmp unit
@@ -159,13 +159,11 @@
  * This function is called during a memory
  * access to determine if the pmp table
  * should be consulted for this access.
- * @param pmode current privilege mode of execution (U, S, M).
- * @param mode mode of request (read, write, execute).
+ * @param pmode current privilege mode of memory (U, S, M).
  * @param tc thread context.
  * @return true or false.
  */
-bool shouldCheckPMP(RiscvISA::PrivilegeMode pmode,
-BaseMMU::Mode mode, ThreadContext *tc);
+bool shouldCheckPMP(RiscvISA::PrivilegeMode pmode, ThreadContext *tc);

 /**
  * createAddrfault creates an address fault

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Gerrit-Change-Number: 69497
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the address check of pmp

2023-04-11 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69577?usp=email )


Change subject: arch-riscv: Fix the address check of pmp
..

arch-riscv: Fix the address check of pmp

Fix the AddrRange of pmp region. the contains of AddrRange(start, end)
will be valid if the address y is in start <= y < end. It should not
minus 1 in end parameter.

Change-Id: I1a0eb51f2d5881b8aa90d310884922b16f2019fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69577
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/pmp.cc
1 file changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved




diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 49dc7ba..6275104 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -83,9 +83,9 @@
 for (int i = 0; i < pmpTable.size(); i++) {
 AddrRange pmp_range = pmpTable[i].pmpAddr;
 if (pmp_range.contains(req->getPaddr()) &&
-pmp_range.contains(req->getPaddr() + req->getSize())) {
+pmp_range.contains(req->getPaddr() + req->getSize() - 1)) {
 // according to specs address is only matched,
-// when (addr) and (addr + request_size) are both
+// when (addr) and (addr + request_size - 1) are both
 // within the pmp range
 match_index = i;
 }
@@ -197,11 +197,11 @@
 break;
   case PMP_TOR:
 // top of range mode
-this_range = AddrRange(prevAddr << 2, (this_addr << 2) - 1);
+this_range = AddrRange(prevAddr << 2, (this_addr << 2));
 break;
   case PMP_NA4:
 // naturally aligned four byte region
-this_range = AddrRange(this_addr << 2, (this_addr + 4) - 1);
+this_range = AddrRange(this_addr << 2, ((this_addr << 2) + 4));
 break;
   case PMP_NAPOT:
 // naturally aligned power of two region, >= 8 bytes
@@ -246,7 +246,7 @@
 }

 DPRINTF(PMP, "Update pmp addr %#x for pmp entry %u \n",
-  this_addr, pmp_index);
+  (this_addr << 2), pmp_index);

 if (pmpTable[pmp_index].pmpCfg & PMP_LOCK) {
 DPRINTF(PMP, "Update pmp entry %u failed because the lock bit  
set\n",

@@ -303,7 +303,7 @@
 return this_range;
 } else {
 uint64_t t1 = ctz64(~pmpaddr);
-uint64_t range = (std::pow(2,t1+3))-1;
+uint64_t range = (1ULL << (t1+3));

 // pmpaddr reg encodes bits 55-2 of a
 // 56 bit physical address for RV64

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Gerrit-Change-Number: 69577
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the address check of pmp

2023-04-09 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69577?usp=email )



Change subject: arch-riscv: Fix the address check of pmp
..

arch-riscv: Fix the address check of pmp

Fix the AddrRange of pmp region. the contains of AddrRange(start, end)
will be valid if the address y is in start <= y < end. It should not
minus 1 in end parameter.

Change-Id: I1a0eb51f2d5881b8aa90d310884922b16f2019fb
---
M src/arch/riscv/pmp.cc
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 49dc7ba..636ea89 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -83,9 +83,9 @@
 for (int i = 0; i < pmpTable.size(); i++) {
 AddrRange pmp_range = pmpTable[i].pmpAddr;
 if (pmp_range.contains(req->getPaddr()) &&
-pmp_range.contains(req->getPaddr() + req->getSize())) {
+pmp_range.contains(req->getPaddr() + req->getSize() - 1)) {
 // according to specs address is only matched,
-// when (addr) and (addr + request_size) are both
+// when (addr) and (addr + request_size - 1) are both
 // within the pmp range
 match_index = i;
 }
@@ -197,11 +197,11 @@
 break;
   case PMP_TOR:
 // top of range mode
-this_range = AddrRange(prevAddr << 2, (this_addr << 2) - 1);
+this_range = AddrRange(prevAddr << 2, (this_addr << 2));
 break;
   case PMP_NA4:
 // naturally aligned four byte region
-this_range = AddrRange(this_addr << 2, (this_addr + 4) - 1);
+this_range = AddrRange(this_addr << 2, (this_addr + 4));
 break;
   case PMP_NAPOT:
 // naturally aligned power of two region, >= 8 bytes
@@ -303,7 +303,7 @@
 return this_range;
 } else {
 uint64_t t1 = ctz64(~pmpaddr);
-uint64_t range = (std::pow(2,t1+3))-1;
+uint64_t range = (std::pow(2,t1+3));

 // pmpaddr reg encodes bits 55-2 of a
 // 56 bit physical address for RV64

--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of pmp

2023-04-07 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69497?usp=email )



Change subject: arch-riscv: Fix the behavior of pmp
..

arch-riscv: Fix the behavior of pmp

1. Refactor the shouldCheckPMP function
2. Fix the AddrRange of pmp region. the contains of
   AddrRange(start, end) will be valid if the address y is in
   start <= y < end. It should not minus 1 in end parameter

Change-Id: I842687674fed7bc4d88a9ba6b4c4d52c3459068f
---
M src/arch/riscv/pmp.cc
1 file changed, 12 insertions(+), 26 deletions(-)



diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 49dc7ba..eaac8b6 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -71,9 +71,6 @@
 req->getPaddr());
 }

-if (numRules == 0)
-return NoFault;
-
 // match_index will be used to identify the pmp entry
 // which matched for the given address
 int match_index = -1;
@@ -83,9 +80,9 @@
 for (int i = 0; i < pmpTable.size(); i++) {
 AddrRange pmp_range = pmpTable[i].pmpAddr;
 if (pmp_range.contains(req->getPaddr()) &&
-pmp_range.contains(req->getPaddr() + req->getSize())) {
+pmp_range.contains(req->getPaddr() + req->getSize() - 1)) {
 // according to specs address is only matched,
-// when (addr) and (addr + request_size) are both
+// when (addr) and (addr + request_size - 1) are both
 // within the pmp range
 match_index = i;
 }
@@ -197,11 +194,11 @@
 break;
   case PMP_TOR:
 // top of range mode
-this_range = AddrRange(prevAddr << 2, (this_addr << 2) - 1);
+this_range = AddrRange(prevAddr << 2, (this_addr << 2));
 break;
   case PMP_NA4:
 // naturally aligned four byte region
-this_range = AddrRange(this_addr << 2, (this_addr + 4) - 1);
+this_range = AddrRange(this_addr << 2, (this_addr + 4));
 break;
   case PMP_NAPOT:
 // naturally aligned power of two region, >= 8 bytes
@@ -246,7 +243,7 @@
 }

 DPRINTF(PMP, "Update pmp addr %#x for pmp entry %u \n",
-  this_addr, pmp_index);
+  (this_addr << 2), pmp_index);

 if (pmpTable[pmp_index].pmpCfg & PMP_LOCK) {
 DPRINTF(PMP, "Update pmp entry %u failed because the lock bit  
set\n",

@@ -276,23 +273,12 @@
 PMP::shouldCheckPMP(RiscvISA::PrivilegeMode pmode,
 BaseMMU::Mode mode, ThreadContext *tc)
 {
-// instruction fetch in S and U mode
-bool cond1 = (mode == BaseMMU::Execute &&
-(pmode != RiscvISA::PrivilegeMode::PRV_M));
-
-// data access in S and U mode when MPRV in mstatus is clear
-RiscvISA::STATUS status =
-tc->readMiscRegNoEffect(RiscvISA::MISCREG_STATUS);
-bool cond2 = (mode != BaseMMU::Execute &&
- (pmode != RiscvISA::PrivilegeMode::PRV_M)
- && (!status.mprv));
-
-// data access in any mode when MPRV bit in mstatus is set
-// and the MPP field in mstatus is S or U
-bool cond3 = (mode != BaseMMU::Execute && (status.mprv)
-&& (status.mpp != RiscvISA::PrivilegeMode::PRV_M));
-
-return (cond1 || cond2 || cond3 || hasLockEntry);
+// The privilege mode of memory read and write access
+// is modified by TLB, it can just simply check if
+// the privilege mode is M or the numRules is zero
+// or has lock entry
+return (pmode != RiscvISA::PrivilegeMode::PRV_M ||
+numRules == 0 || hasLockEntry);
 }

 AddrRange
@@ -303,7 +289,7 @@
 return this_range;
 } else {
 uint64_t t1 = ctz64(~pmpaddr);
-uint64_t range = (std::pow(2,t1+3))-1;
+uint64_t range = (std::pow(2,t1+3));

 // pmpaddr reg encodes bits 55-2 of a
 // 56 bit physical address for RV64

--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add pmp index checking

2023-03-21 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69117?usp=email )


Change subject: arch-riscv: Add pmp index checking
..

arch-riscv: Add pmp index checking

Check the index is within the bounds of PMP table before updating the
address and config

Change-Id: Ie938b3c2a61eca9527192c0452d1db9522f07af9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69117
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Ayaz Akram 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/pmp.cc
1 file changed, 16 insertions(+), 2 deletions(-)

Approvals:
  Ayaz Akram: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 940af47..49dc7ba 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -152,6 +152,13 @@
 bool
 PMP::pmpUpdateCfg(uint32_t pmp_index, uint8_t this_cfg)
 {
+if (pmp_index >= pmpEntries) {
+DPRINTF(PMP, "Can't update pmp entry config %u"
+" because the index exceed the size of pmp entries %u",
+pmp_index, pmpEntries);
+return false;
+}
+
 DPRINTF(PMP, "Update pmp config with %u for pmp entry: %u \n",
 (unsigned)this_cfg, pmp_index);
 if (pmpTable[pmp_index].pmpCfg & PMP_LOCK) {
@@ -231,6 +238,13 @@
 bool
 PMP::pmpUpdateAddr(uint32_t pmp_index, Addr this_addr)
 {
+if (pmp_index >= pmpEntries) {
+DPRINTF(PMP, "Can't update pmp entry address %u"
+" because the index exceed the size of pmp entries %u",
+pmp_index, pmpEntries);
+return false;
+}
+
 DPRINTF(PMP, "Update pmp addr %#x for pmp entry %u \n",
   this_addr, pmp_index);

@@ -241,8 +255,8 @@
 } else if (pmp_index < pmpTable.size() - 1 &&
((pmpTable[pmp_index+1].pmpCfg & PMP_LOCK) != 0) &&
pmpGetAField(pmpTable[pmp_index+1].pmpCfg) == PMP_TOR) {
-DPRINTF(PMP, "Update pmp entry %u failed because the entry %u lock  
bit set"

-"and A field is TOR\n",
+DPRINTF(PMP, "Update pmp entry %u failed because the entry %u lock  
bit"

+" set and A field is TOR\n",
 pmp_index, pmp_index+1);
 return false;
 }

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Gerrit-Change-Number: 69117
Gerrit-PatchSet: 2
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
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Gerrit-CC: Hoa Nguyen 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Add pmp index checking

2023-03-20 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69117?usp=email )



Change subject: arch-riscv: Add pmp index checking
..

arch-riscv: Add pmp index checking

Check the index is within the bounds of PMP table before updating the
address and config

Change-Id: Ie938b3c2a61eca9527192c0452d1db9522f07af9
---
M src/arch/riscv/pmp.cc
1 file changed, 16 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 940af47..49dc7ba 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -152,6 +152,13 @@
 bool
 PMP::pmpUpdateCfg(uint32_t pmp_index, uint8_t this_cfg)
 {
+if (pmp_index >= pmpEntries) {
+DPRINTF(PMP, "Can't update pmp entry config %u"
+" because the index exceed the size of pmp entries %u",
+pmp_index, pmpEntries);
+return false;
+}
+
 DPRINTF(PMP, "Update pmp config with %u for pmp entry: %u \n",
 (unsigned)this_cfg, pmp_index);
 if (pmpTable[pmp_index].pmpCfg & PMP_LOCK) {
@@ -231,6 +238,13 @@
 bool
 PMP::pmpUpdateAddr(uint32_t pmp_index, Addr this_addr)
 {
+if (pmp_index >= pmpEntries) {
+DPRINTF(PMP, "Can't update pmp entry address %u"
+" because the index exceed the size of pmp entries %u",
+pmp_index, pmpEntries);
+return false;
+}
+
 DPRINTF(PMP, "Update pmp addr %#x for pmp entry %u \n",
   this_addr, pmp_index);

@@ -241,8 +255,8 @@
 } else if (pmp_index < pmpTable.size() - 1 &&
((pmpTable[pmp_index+1].pmpCfg & PMP_LOCK) != 0) &&
pmpGetAField(pmpTable[pmp_index+1].pmpCfg) == PMP_TOR) {
-DPRINTF(PMP, "Update pmp entry %u failed because the entry %u lock  
bit set"

-"and A field is TOR\n",
+DPRINTF(PMP, "Update pmp entry %u failed because the entry %u lock  
bit"

+" set and A field is TOR\n",
 pmp_index, pmp_index+1);
 return false;
 }

--
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Remove CLINT parameter of HiFiveBase

2023-03-16 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69017?usp=email )



Change subject: arch-riscv,dev: Remove CLINT parameter of HiFiveBase
..

arch-riscv,dev: Remove CLINT parameter of HiFiveBase

Remove the clint parameter because HiFiveBase platform don't need
to use CLINT component

Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4
---
M src/dev/riscv/HiFive.py
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
3 files changed, 8 insertions(+), 13 deletions(-)



diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 5bd6363..e58fcff 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -72,13 +72,6 @@
 board series. It contains the CLINT and PLIC
 interrupt controllers, Uart and Disk.

-Driving CLINT:
-CLINT has an interrupt pin which increments
-mtime. It can be connected to any interrupt
-source pin which acts as the RTCCLK pin. An
-abstract RTC wrapper called RiscvRTC can be
-used.
-
 Driving PLIC:
 PLIC handles external interrupts. Interrupt
 PioDevices should inherit from PlicIntDevice
@@ -94,9 +87,6 @@
 cxx_header = "dev/riscv/hifive.hh"
 cxx_class = "gem5::HiFiveBase"

-# CLINT
-clint = Param.Clint(NULL, "CLINT")
-
 # PLIC
 plic = Param.PlicBase(NULL, "PLIC")

@@ -159,6 +149,13 @@
 setup for a RISC-V HiFive platform. See
 configs/example/riscv/fs_linux.py for example.

+Driving CLINT:
+CLINT has an interrupt pin which increments
+mtime. It can be connected to any interrupt
+source pin which acts as the RTCCLK pin. An
+abstract RTC wrapper called RiscvRTC can be
+used.
+
 Uart:
 The HiFive platform also has an uart_int_id.
 This is because Uart8250 uses postConsoleInt
diff --git a/src/dev/riscv/hifive.cc b/src/dev/riscv/hifive.cc
index 0487eab..ca44a79 100644
--- a/src/dev/riscv/hifive.cc
+++ b/src/dev/riscv/hifive.cc
@@ -50,10 +50,9 @@

 HiFiveBase::HiFiveBase(const Params ) :
 Platform(params),
-clint(params.clint), plic(params.plic),
+plic(params.plic),
 uartIntID(params.uart_int_id)
 {
-fatal_if(clint == nullptr, "CLINT should not be NULL");
 fatal_if(plic == nullptr, "PLIC should not be NULL");
 }

diff --git a/src/dev/riscv/hifive.hh b/src/dev/riscv/hifive.hh
index 99d7ae6..2b17715 100644
--- a/src/dev/riscv/hifive.hh
+++ b/src/dev/riscv/hifive.hh
@@ -52,7 +52,6 @@
 class HiFiveBase : public Platform
 {
   public:
-Clint *clint;
 PlicBase *plic;
 int uartIntID;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iea4c8c54354b8230f1352d0ae31a6a6a3a479ff4
Gerrit-Change-Number: 69017
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add new misa bit union

2023-03-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68917?usp=email )


Change subject: arch-riscv: Add new misa bit union
..

arch-riscv: Add new misa bit union

The new misa bit union type can help get and set misa CSR more
clearily

Change-Id: Id48b140968a0e8021b09782815aa612b409ac75b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68917
Reviewed-by: Bobby Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Hoa Nguyen 
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/misc.hh
2 files changed, 59 insertions(+), 15 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  Hoa Nguyen: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 7964de5..d744fe36 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -287,21 +287,33 @@
 miscRegFile[MISCREG_VENDORID] = 0;
 miscRegFile[MISCREG_ARCHID] = 0;
 miscRegFile[MISCREG_IMPID] = 0;
+
+MISA misa = 0;
+STATUS status = 0;
+
+// default config arch isa string is rv64(32)imafdc
+misa.rvi = misa.rvm = misa.rva = misa.rvf = misa.rvd = misa.rvc = 1;
+// default privlege modes if MSU
+misa.rvs = misa.rvu = 1;
+
+// mark FS is initial
+status.fs = INITIAL;
+
 // rv_type dependent init.
 switch (rv_type) {
 case RV32:
-miscRegFile[MISCREG_ISA] = (1ULL << MXL_OFFSETS[RV32]) |  
0x14112D;

-miscRegFile[MISCREG_STATUS] = (1ULL << FS_OFFSET);
-break;
+  misa.rv32_mxl = 1;
+  break;
 case RV64:
-miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSETS[RV64]) |  
0x14112D;

-miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) |
-  (2ULL << SXL_OFFSET) |
-  (1ULL << FS_OFFSET);
-break;
+  misa.rv64_mxl = 2;
+  status.uxl = status.sxl = 2;
+  break;
 default:
-panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+  panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
 }
+
+miscRegFile[MISCREG_ISA] = misa;
+miscRegFile[MISCREG_STATUS] = status;
 miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
 miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
 // don't set it to zero; software may try to determine the supported
@@ -425,10 +437,10 @@
   case MISCREG_SEPC:
   case MISCREG_MEPC:
 {
-auto misa = readMiscRegNoEffect(MISCREG_ISA);
+MISA misa = readMiscRegNoEffect(MISCREG_ISA);
 auto val = readMiscRegNoEffect(idx);
 // if compressed instructions are disabled, epc[1] is set to 0
-if ((misa & ISA_EXT_C_MASK) == 0)
+if (misa.rvc == 0)
 return mbits(val, 63, 2);
 // epc[0] is always 0
 else
@@ -617,15 +629,16 @@
 break;
   case MISCREG_ISA:
 {
-auto cur_val = readMiscRegNoEffect(idx);
+MISA cur_misa = (MISA)readMiscRegNoEffect(MISCREG_ISA);
+MISA new_misa = (MISA)val;
 // only allow to disable compressed instructions
 // if the following instruction is 4-byte aligned
-if ((val & ISA_EXT_C_MASK) == 0 &&
+if (new_misa.rvc == 0 &&
 bits(tc->pcState().as().npc(),
 2, 0) != 0) {
-val |= cur_val & ISA_EXT_C_MASK;
+new_misa.rvc = new_misa.rvc | cur_misa.rvc;
 }
-setMiscRegNoEffect(idx, val);
+setMiscRegNoEffect(idx, new_misa);
 }
 break;
   case MISCREG_STATUS:
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 8cb4ca0..5ea3536 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -754,6 +754,37 @@

 /**
  * These fields are specified in the RISC-V Instruction Set Manual, Volume  
II,
+ * v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org. The  
register

+ * is used to control instruction extensions.
+ */
+BitUnion64(MISA)
+Bitfield<63, 62> rv64_mxl;
+Bitfield<31, 30> rv32_mxl;
+Bitfield<23> rvx;
+Bitfield<21> rvv;
+Bitfield<20> rvu;
+Bitfield<19> rvt;
+Bitfield<18> rvs;
+Bitfield<16> rvq;
+Bitfield<15> rvp;
+Bitfield<13> rvn;
+Bitfield<12> rvm;
+Bitfield<11> rvl;
+Bitfield<10> rvk;
+Bitfield<9> rvj;
+Bitfield<8> rvi;
+Bitfield<7> rvh;
+Bitfield<6> rvg;
+Bitfield<5> rvf;
+Bitfield<4> rve;
+Bitfield<3> rvd;
+Bitfield<2> rvc;
+Bitfield<1> rvb;
+Bitfield<0> rva;
+EndBitUnion(MISA)
+
+/**
+ * These fields are specified in the RISC-V Instruction

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Add new misa bit union

2023-03-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68917?usp=email )



Change subject: arch-riscv: Add new misa bit union
..

arch-riscv: Add new misa bit union

The new misa bit union type can help get and set misa CSR more
clearily

Change-Id: Id48b140968a0e8021b09782815aa612b409ac75b
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/misc.hh
2 files changed, 60 insertions(+), 16 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 7964de5..18e1d7e 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -287,21 +287,33 @@
 miscRegFile[MISCREG_VENDORID] = 0;
 miscRegFile[MISCREG_ARCHID] = 0;
 miscRegFile[MISCREG_IMPID] = 0;
+
+MISA misa = 0;
+STATUS status = 0;
+
 // rv_type dependent init.
-switch (rv_type) {
+// default config arch isa string is rv64(32)imafdc
+misa.rvi = misa.rvm = misa.rva = misa.rvf = misa.rvd = misa.rvc = 1;
+// default privlege modes if MSU
+misa.rvs = misa.rvu = 1;
+
+// mark FS is initial
+status.fs = INITIAL;
+
+switch(rv_type) {
 case RV32:
-miscRegFile[MISCREG_ISA] = (1ULL << MXL_OFFSETS[RV32]) |  
0x14112D;

-miscRegFile[MISCREG_STATUS] = (1ULL << FS_OFFSET);
-break;
+  misa.rv32_mxl = 1;
+  break;
 case RV64:
-miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSETS[RV64]) |  
0x14112D;

-miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) |
-  (2ULL << SXL_OFFSET) |
-  (1ULL << FS_OFFSET);
-break;
+  misa.rv64_mxl = 2;
+  status.uxl = status.sxl = 2;
+  break;
 default:
-panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+  panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
 }
+
+miscRegFile[MISCREG_ISA] = misa;
+miscRegFile[MISCREG_STATUS] = status;
 miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
 miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
 // don't set it to zero; software may try to determine the supported
@@ -425,10 +437,10 @@
   case MISCREG_SEPC:
   case MISCREG_MEPC:
 {
-auto misa = readMiscRegNoEffect(MISCREG_ISA);
+MISA misa = readMiscRegNoEffect(MISCREG_ISA);
 auto val = readMiscRegNoEffect(idx);
 // if compressed instructions are disabled, epc[1] is set to 0
-if ((misa & ISA_EXT_C_MASK) == 0)
+if (misa.rvc == 0)
 return mbits(val, 63, 2);
 // epc[0] is always 0
 else
@@ -617,15 +629,16 @@
 break;
   case MISCREG_ISA:
 {
-auto cur_val = readMiscRegNoEffect(idx);
+MISA cur_misa = (MISA)readMiscRegNoEffect(MISCREG_ISA);
+MISA new_misa = (MISA)val;
 // only allow to disable compressed instructions
 // if the following instruction is 4-byte aligned
-if ((val & ISA_EXT_C_MASK) == 0 &&
+if (new_misa.rvc == 0 &&
 bits(tc->pcState().as().npc(),
 2, 0) != 0) {
-val |= cur_val & ISA_EXT_C_MASK;
+new_misa.rvc = new_misa.rvc | cur_misa.rvc;
 }
-setMiscRegNoEffect(idx, val);
+setMiscRegNoEffect(idx, new_misa);
 }
 break;
   case MISCREG_STATUS:
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 8cb4ca0..d12b40d 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -754,6 +754,37 @@

 /**
  * These fields are specified in the RISC-V Instruction Set Manual, Volume  
II,
+ * v1.10, v1.11 and v.12 in Figure 3.1, accessible at www.riscv.org. The  
register

+ * is used to control instruction extensions.
+ */
+BitUnion64(MISA)
+Bitfield<63, 62> rv64_mxl;
+Bitfield<31, 30> rv32_mxl;
+Bitfield<23> rvx;
+Bitfield<21> rvv;
+Bitfield<20> rvu;
+Bitfield<19> rvt;
+Bitfield<18> rvs;
+Bitfield<16> rvq;
+Bitfield<15> rvp;
+Bitfield<13> rvn;
+Bitfield<12> rvm;
+Bitfield<11> rvl;
+Bitfield<10> rvk;
+Bitfield<9> rvj;
+Bitfield<8> rvi;
+Bitfield<7> rvh;
+Bitfield<6> rvg;
+Bitfield<5> rvf;
+Bitfield<4> rve;
+Bitfield<3> rvd;
+Bitfield<2> rvc;
+Bitfield<1> rvb;
+Bitfield<0> rva;
+EndBitUnion(MISA)
+
+/**
+ * These fields are specified in the RISC-V Instruction Set Manual, Volume  
II,
  * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the  
MIP

  * and MIE registers have the same fields, so accesses to either should use
  * this bit union.

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Support PMP lock feature

2023-03-06 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68057?usp=email )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Support PMP lock feature
..

arch-riscv: Support PMP lock feature

The lock feature will let M mode do memory permission check before
R/W/X data. If the lock bit of pmpicfg set, then the pmpicfg and
pmpaddri will ignore the update value later until CPU reset, and
pmpaddri-1 will ignore if the TOR A field is set.

The following is add in CL:
1. Add condition to run PMP check when any lock bit of pmp tables
   is set
2. Add PMP_LOCK bit check when try to update pmpaddr and pmpcfg
3. If there is no PMP entry matches and priviledge mode is M,
   no fault generated
4. If the address matches PMP entry, return no fault if priviledge
mode is M and lock bit is not set

For more details about PMP, please see RISC-V Spec Volumn II,
Priviledge Archtecture, Ver 1.12, Section 3.7 Physical Memory
Protection

Change-Id: I3e7c5824d6c05f2ea928ee9ec7714f7271e4c58c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68057
Reviewed-by: Ayaz Akram 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
Maintainer: Bobby Bruce 
---
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/pmp.cc
M src/arch/riscv/pmp.hh
4 files changed, 93 insertions(+), 29 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  Ayaz Akram: Looks good to me, but someone else must approve
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 3469c71..940f710 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -33,6 +33,8 @@

 #include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/isa.hh"
+#include "arch/riscv/mmu.hh"
+#include "arch/riscv/pmp.hh"
 #include "arch/riscv/regs/misc.hh"
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
@@ -180,6 +182,14 @@
 tc->getIsaPtr()->newPCState(workload->getEntry(;
 panic_if(!new_pc, "Failed create new PCState from ISA pointer");
 tc->pcState(*new_pc);
+
+// Reset PMP Cfg
+auto* mmu = dynamic_cast(tc->getMMUPtr());
+if (mmu == nullptr) {
+warn("MMU is not Riscv MMU instance, we can't reset PMP");
+return;
+}
+mmu->getPMP()->pmpReset();
 }

 void
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 3809c61..d778957 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -2,6 +2,7 @@
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
  * Copyright (c) 2020 Barkhausen Institut
+ * Copyright (c) 2022 Google LLC
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -544,6 +545,8 @@
 // qemu seems to update the tables when
 // pmp addr regs are written (with the assumption
 // that cfg regs are already written)
+RegVal res = 0;
+RegVal old_val = readMiscRegNoEffect(idx);

 for (int i=0; i < regSize; i++) {

@@ -554,10 +557,15 @@
 // Form pmp_index using the index i and
 // PMPCFG register number
 uint32_t pmp_index = i+(4*(idx-MISCREG_PMPCFG0));
-mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
+bool result =  
mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);

+if (result) {
+res |= ((RegVal)cfg_val << (8*i));
+} else {
+res |= (old_val & (0xFF << (8*i)));
+}
 }

-setMiscRegNoEffect(idx, val);
+setMiscRegNoEffect(idx, res);
 }
 break;
   case MISCREG_PMPADDR00 ... MISCREG_PMPADDR15:
@@ -568,9 +576,9 @@
 auto mmu = dynamic_cast
   (tc->getMMUPtr());
 uint32_t pmp_index = idx-MISCREG_PMPADDR00;
-mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
-
-setMiscRegNoEffect(idx, val);
+if (mmu->getPMP()->pmpUpdateAddr(pmp_index, val)) {
+setMiscRegNoEffect(idx, val);
+}
 }
 break;

diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 77ef98f..940af47 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 The Regents of the University of California
+ * Copyright (c) 2023 Google LLC
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,7 +28,6 @@
  */

 #include "arch/riscv/pmp.hh"
-
 #include "arch/generic/tlb.hh"
 #include

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform

2023-03-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email )


 (

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv,dev: Add HiFive Base Platform
..

arch-riscv,dev: Add HiFive Base Platform

This is basic abstract platform and all of RISC-V system should
use platform inherit from HiFiveBase, HiFiveBase declared the common
way to handle interrupt.

Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68199
Maintainer: Jason Lowe-Power 
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
---
M src/dev/riscv/HiFive.py
M src/dev/riscv/SConscript
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
4 files changed, 107 insertions(+), 79 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 4669686..5bd6363 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -1,5 +1,6 @@
 # Copyright (c) 2021 Huawei International
 # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -63,24 +64,14 @@
 _dma_coherent = True


-class HiFive(Platform):
-"""HiFive Platform
+class HiFiveBase(Platform):
+"""HiFive Base Abstract Platform

 Implementation:
 This is the base class for SiFive's HiFive
 board series. It contains the CLINT and PLIC
 interrupt controllers, Uart and Disk.

-Implementation details are based on SiFive
-FU540-C000. https://sifive.cdn.prismic.io/
-sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2
-1_FU540-C000-v1p3.pdf
-
-Setup:
-The following sections outline the required
-setup for a RISC-V HiFive platform. See
-configs/example/riscv/fs_linux.py for example.
-
 Driving CLINT:
 CLINT has an interrupt pin which increments
 mtime. It can be connected to any interrupt
@@ -88,7 +79,7 @@
 abstract RTC wrapper called RiscvRTC can be
 used.

-Attaching PLIC devices:
+Driving PLIC:
 PLIC handles external interrupts. Interrupt
 PioDevices should inherit from PlicIntDevice
 (PCI and DMA not yet implemented). It contains
@@ -96,63 +87,30 @@
 to call platform->postPciInt(id).

 All PLIC interrupt devices should be returned
-by _off_chip_devices(). Calling attachPlic sets
-up the PLIC interrupt source count.
-
-Uart:
-The HiFive platform also has an uart_int_id.
-This is because Uart8250 uses postConsoleInt
-instead of postPciInt. In the future if a Uart
-that inherits PlicIntDevice is implemented,
-this can be removed.
-
-Disk:
-See fs_linux.py for setup example.
-
-PMAChecker:
-The PMAChecker will be attached to the MMU of
-each CPU (which allows them to differ). See
-fs_linux.py for setup example.
+by _off_chip_devices().
 """

-type = "HiFive"
+type = "HiFiveBase"
 cxx_header = "dev/riscv/hifive.hh"
-cxx_class = "gem5::HiFive"
+cxx_class = "gem5::HiFiveBase"

 # CLINT
-clint = Param.Clint(Clint(pio_addr=0x200), "CLINT")
+clint = Param.Clint(NULL, "CLINT")

 # PLIC
-plic = Param.Plic(Plic(pio_addr=0xC00), "PLIC")
+plic = Param.PlicBase(NULL, "PLIC")

-# PCI
-pci_host = GenericRiscvPciHost(
-conf_base=0x3000,
-conf_size="256MB",
-conf_device_bits=12,
-pci_pio_base=0x2F00,
-pci_mem_base=0x4000,
-)
-
-# Uart
-uart = RiscvUart8250(pio_addr=0x1000)
 # Int source ID to redirect console interrupts to
 # Set to 0 if using a pci interrupt for Uart instead
-uart_int_id = Param.Int(0xA, "PLIC Uart interrupt ID")
-terminal = Terminal()
+uart_int_id = Param.Int(0, "PLIC Uart interrupt ID")

 def _on_chip_devices(self):
 """Returns a list of on-chip peripherals"""
-return [self.clint, self.plic]
+return []

 def _off_chip_devices(self):
 """Returns a list of off-chip peripherals"""
-devices = [self.uart]
-if hasattr(self, "disk"):
-devices.append(self.disk)
-if hasattr(self, "rng"):
-devices.append(self.rng)
-return devices
+return []

 def _on_chip_ranges(self):
 """Returns a list of on-chip peripherals
@@ -172,17 +130,6 @@
 for dev in self._off_chip_devices()
 ]

-def attachPlic(self):
-"""Count number of PLIC interrupt sources"""
-plic_srcs = [
-

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...

2023-03-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email )


 (

7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-riscv,dev: Add PLIC abstract class to support  
multiple PLIC implementation

..

arch-riscv,dev: Add PLIC abstract class to support multiple PLIC
implementation

We should create PLIC abstract and have common interface to let
HiFive platform send and clear interrupt to variable type of PLIC

Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68197
Maintainer: Jason Lowe-Power 
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
---
M src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
4 files changed, 41 insertions(+), 7 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 33b6940..b4486b9 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2021 Huawei International
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -39,7 +40,22 @@
 from m5.util.fdthelper import *


-class Plic(BasicPioDevice):
+class PlicBase(BasicPioDevice):
+"""
+This is abstract class of PLIC and
+define interface to handle received
+interrupt singal from device
+"""
+
+type = "PlicBase"
+cxx_header = "dev/riscv/plic.hh"
+cxx_class = "gem5::PlicBase"
+abstract = True
+
+pio_size = Param.Addr("PIO Size")
+
+
+class Plic(PlicBase):
 """
 This implementation of PLIC is based on
 the SiFive U54MC datasheet:
@@ -51,7 +67,7 @@
 type = "Plic"
 cxx_header = "dev/riscv/plic.hh"
 cxx_class = "gem5::Plic"
-pio_size = Param.Addr(0x400, "PIO Size")
+pio_size = 0x400
 n_src = Param.Int("Number of interrupt sources")
 n_contexts = Param.Int(
 "Number of interrupt contexts. Usually the number "
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index af0b96b..6e3376b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -2,6 +2,7 @@

 # Copyright (c) 2021 Huawei International
 # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,7 +35,7 @@
 SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa')
 SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa')
 SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa')
-SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa')
+SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa')
 SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa')
 SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'],
 tags='riscv isa')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 371af9e..fd42920 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -45,6 +45,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -53,7 +54,7 @@
 using namespace RiscvISA;

 Plic::Plic(const Params ) :
-BasicPioDevice(params, params.pio_size),
+PlicBase(params),
 system(params.system),
 nSrc(params.n_src),
 nContext(params.n_contexts),
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index d077e73..00128ee 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Huawei International
+ * Copyright (c) 2023 Google LLC
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,6 +48,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -94,7 +96,21 @@
   std::vector maxPriority;
 };

-class Plic : public BasicPioDevice
+class PlicBase : public BasicPioDevice
+{
+  public:
+typedef PlicBaseParams Params;
+PlicBase(const Params ) :
+  BasicPioDevice(params, params.pio_size)
+{}
+
+// Interrupt interface to send signal to PLIC
+virtual void post(int src_id) = 0;
+// Interrupt interface to clear signal to PLIC
+virtual void clear(int src_id) = 0;
+};
+
+class Plic : public PlicBase
 {
   // Params
   protected:
@@ -125,8 +141,8 @@
 /**
  * Interrupt interface
  */
-void post(int src_id);
-void clear(int src_id);
+void post(int src_id) override;
+void clear(int src_id)

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Fix behavior issues of PLIC

2023-02-23 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68198?usp=email )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv,dev: Fix behavior issues of PLIC
..

arch-riscv,dev: Fix behavior issues of PLIC

1. Fix reserved size between enable memory map and threshold memory
map. The number of enablePadding should be the number of context in
PLIC
2. writePriority to memory should update

Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68198
Reviewed-by: Ayaz Akram 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
Maintainer: Jason Lowe-Power 
---
M src/dev/riscv/plic.cc
1 file changed, 22 insertions(+), 1 deletion(-)

Approvals:
  Ayaz Akram: Looks good to me, but someone else must approve
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved




diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index b8f765a..371af9e 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -203,7 +203,7 @@
 - plic->nSrc32 * 4;
 reserved.emplace_back("reserved1", reserve1_size);
 const size_t reserve2_size = thresholdStart - enableStart
-- plic->nSrc32 * plic->nContext * enablePadding;
+- plic->nContext * enablePadding;
 reserved.emplace_back("reserved2", reserve2_size);
 const size_t reserve3_size = plic->pioSize - thresholdStart
 - plic->nContext * thresholdPadding;
@@ -333,6 +333,8 @@
 Plic::writeThreshold(Register32& reg, const uint32_t& data,
 const int context_id)
 {
+reg.update(data);
+
 DPRINTF(Plic,
 "Threshold updated - context: %d, val: %d\n",
 context_id, reg.get());

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
Gerrit-Change-Number: 68198
Gerrit-PatchSet: 6
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-CC: Hoa Nguyen 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform

2023-02-20 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email )



Change subject: arch-riscv,dev: Add HiFive Base Platform
..

arch-riscv,dev: Add HiFive Base Platform

This is basic abstract platform and all of RISC-V system should
use platform inherit from HiFiveBase, HiFiveBase declared the common
way to handle interrupt.

Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637
---
M src/dev/riscv/HiFive.py
M src/dev/riscv/SConscript
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
4 files changed, 118 insertions(+), 75 deletions(-)



diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 4669686..ae5c232 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -1,5 +1,6 @@
 # Copyright (c) 2021 Huawei International
 # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -63,24 +64,14 @@
 _dma_coherent = True


-class HiFive(Platform):
-"""HiFive Platform
+class HiFiveBase(Platform):
+"""HiFive Base Abstract Platform

 Implementation:
 This is the base class for SiFive's HiFive
 board series. It contains the CLINT and PLIC
 interrupt controllers, Uart and Disk.

-Implementation details are based on SiFive
-FU540-C000. https://sifive.cdn.prismic.io/
-sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2
-1_FU540-C000-v1p3.pdf
-
-Setup:
-The following sections outline the required
-setup for a RISC-V HiFive platform. See
-configs/example/riscv/fs_linux.py for example.
-
 Driving CLINT:
 CLINT has an interrupt pin which increments
 mtime. It can be connected to any interrupt
@@ -99,60 +90,29 @@
 by _off_chip_devices(). Calling attachPlic sets
 up the PLIC interrupt source count.

-Uart:
-The HiFive platform also has an uart_int_id.
-This is because Uart8250 uses postConsoleInt
-instead of postPciInt. In the future if a Uart
-that inherits PlicIntDevice is implemented,
-this can be removed.
-
-Disk:
-See fs_linux.py for setup example.
-
-PMAChecker:
-The PMAChecker will be attached to the MMU of
-each CPU (which allows them to differ). See
-fs_linux.py for setup example.
 """

-type = "HiFive"
+type = "HiFiveBase"
 cxx_header = "dev/riscv/hifive.hh"
-cxx_class = "gem5::HiFive"
+cxx_class = "gem5::HiFiveBase"

 # CLINT
-clint = Param.Clint(Clint(pio_addr=0x200), "CLINT")
+clint = Param.Clint(NULL, "CLINT")

 # PLIC
-plic = Param.Plic(Plic(pio_addr=0xC00), "PLIC")
+plic = Param.PlicBase(NULL, "PLIC")

-# PCI
-pci_host = GenericRiscvPciHost(
-conf_base=0x3000,
-conf_size="256MB",
-conf_device_bits=12,
-pci_pio_base=0x2F00,
-pci_mem_base=0x4000,
-)
-
-# Uart
-uart = RiscvUart8250(pio_addr=0x1000)
 # Int source ID to redirect console interrupts to
 # Set to 0 if using a pci interrupt for Uart instead
-uart_int_id = Param.Int(0xA, "PLIC Uart interrupt ID")
-terminal = Terminal()
+uart_int_id = Param.Int(0, "PLIC Uart interrupt ID")

 def _on_chip_devices(self):
 """Returns a list of on-chip peripherals"""
-return [self.clint, self.plic]
+return []

 def _off_chip_devices(self):
 """Returns a list of off-chip peripherals"""
-devices = [self.uart]
-if hasattr(self, "disk"):
-devices.append(self.disk)
-if hasattr(self, "rng"):
-devices.append(self.rng)
-return devices
+return []

 def _on_chip_ranges(self):
 """Returns a list of on-chip peripherals
@@ -172,17 +132,6 @@
 for dev in self._off_chip_devices()
 ]

-def attachPlic(self):
-"""Count number of PLIC interrupt sources"""
-plic_srcs = [
-self.uart_int_id,
-self.pci_host.int_base + self.pci_host.int_count,
-]
-for device in self._off_chip_devices():
-if hasattr(device, "interrupt_id"):
-plic_srcs.append(device.interrupt_id)
-self.plic.n_src = max(plic_srcs) + 1
-
 def attachOnChipIO(self, bus):
 """Attach on-chip IO devices, needs modification
 to support DMA
@@ -197,6 +146,83 @@
 for device in self._off_chip_devices():
 device.pio = bus.mem_side_ports

+
+class HiFive(HiFiveBase):
+"""HiFive Platform
+
+Implementation:
+Implementation details are based on SiFive
+FU540-C000. https://sifive.cdn.prismic.io/
+sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2
+1_FU540-C000-v1p3.pdf
+
+Setup:
+The following

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Fix reserved size between enable memory map and thres...

2023-02-20 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68198?usp=email )



Change subject: arch-riscv,dev: Fix reserved size between enable memory map  
and threshold memory map

..

arch-riscv,dev: Fix reserved size between enable memory map and
threshold memory map

The number of enablePadding is depending on number of context in
PLIC

Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
---
M src/dev/riscv/plic.cc
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index edf0e06..d221946 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -204,7 +204,7 @@
 - plic->nSrc32 * 4;
 reserved.emplace_back("reserved1", reserve1_size);
 const size_t reserve2_size = thresholdStart - enableStart
-- plic->nSrc32 * plic->nContext * enablePadding;
+- plic->nContext * enablePadding;
 reserved.emplace_back("reserved2", reserve2_size);
 const size_t reserve3_size = plic->pioSize - thresholdStart
 - plic->nContext * thresholdPadding;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4b7e5ecd183863e140c4f3382a75057902d446d
Gerrit-Change-Number: 68198
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...

2023-02-20 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email )



Change subject: arch-riscv,dev: Add PLIC abstract class to support multiple  
PLIC implementation

..

arch-riscv,dev: Add PLIC abstract class to support multiple PLIC
implementation

We should create PLIC abstract and have common interface to let
HiFive platform send and clear interrupt to variable PLIC

Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
---
M src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
4 files changed, 53 insertions(+), 7 deletions(-)



diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 33b6940..3233e0d 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2021 Huawei International
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -39,7 +40,21 @@
 from m5.util.fdthelper import *


-class Plic(BasicPioDevice):
+class PlicBase(BasicPioDevice):
+  """
+  This is abstract class of PLIC and
+  define interface to handle received
+  interrupt singal from device
+  """
+  type = "PlicBase"
+  cxx_header = "dev/riscv/plic.hh"
+  cxx_class = "gem5::PlicBase"
+  abstract = True
+
+  pio_size = Param.Addr("PIO Size")
+
+
+class Plic(PlicBase):
 """
 This implementation of PLIC is based on
 the SiFive U54MC datasheet:
@@ -51,7 +66,7 @@
 type = "Plic"
 cxx_header = "dev/riscv/plic.hh"
 cxx_class = "gem5::Plic"
-pio_size = Param.Addr(0x400, "PIO Size")
+pio_size = 0x400
 n_src = Param.Int("Number of interrupt sources")
 n_contexts = Param.Int(
 "Number of interrupt contexts. Usually the number "
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index af0b96b..6e3376b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -2,6 +2,7 @@

 # Copyright (c) 2021 Huawei International
 # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,7 +35,7 @@
 SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa')
 SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa')
 SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa')
-SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa')
+SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa')
 SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa')
 SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'],
 tags='riscv isa')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index b8f765a..edf0e06 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -45,6 +45,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -53,7 +54,7 @@
 using namespace RiscvISA;

 Plic::Plic(const Params ) :
-BasicPioDevice(params, params.pio_size),
+PlicBase(params),
 system(params.system),
 nSrc(params.n_src),
 nContext(params.n_contexts),
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index d077e73..0b30813 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Huawei International
+ * Copyright (c) 2023 Google LLC
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,6 +48,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -94,7 +96,21 @@
   std::vector maxPriority;
 };

-class Plic : public BasicPioDevice
+class PlicBase : public BasicPioDevice
+{
+  public:
+typedef PlicBaseParams Params;
+PlicBase(const Params ) :
+  BasicPioDevice(params, params.pio_size)
+{}
+
+/** Interrupt interface to send signal to PLIC */
+virtual void post(int src_id) = 0;
+/** Interrupt interface to clear signal to PLIC */
+virtual void clear(int src_id) = 0;
+};
+
+class Plic : public PlicBase
 {
   // Params
   protected:
@@ -125,8 +141,8 @@
 /**
  * Interrupt interface
  */
-void post(int src_id);
-void clear(int src_id);
+void post(int src_id) override;
+void clear(int src_id) override;

 /**
  * SimObject functions

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Gerrit-Change-Number: 68197
Gerrit-PatchSet: 1
Gerrit-Owner:

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Support PMP lock feature

2023-02-17 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68057?usp=email )



Change subject: arch-riscv: Support PMP lock feature
..

arch-riscv: Support PMP lock feature

The lock feature will let M mode do memory permission check before
R/W/X data. If the lock bit of pmpicfg set, then the pmpicfg and
pmpaddri will ignore the update value later until CPU reset, and
pmpaddri-1 will ignore if the TOR A field is set.

The following is add in CL:
1. Add condition to run PMP check when any lock bit of pmp tables
   is set
2. Add PMP_LOCK bit check when try to update pmpaddr and pmpcfg
3. If there is no PMP entry matches and priviledge mode is M,
   no fault generated
4. If the address matches PMP entry, return no fault if priviledge
mode is M and lock bit is not set

For more details about PMP, please see RISC-V Spec Volumn II,
Priviledge Archtecture, Ver 1.12, Section 3.7 Physical Memory
Protection

Change-Id: I3e7c5824d6c05f2ea928ee9ec7714f7271e4c58c
---
M src/arch/riscv/PMP.py
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/pmp.cc
M src/arch/riscv/pmp.hh
5 files changed, 131 insertions(+), 29 deletions(-)



diff --git a/src/arch/riscv/PMP.py b/src/arch/riscv/PMP.py
index a3844c9..c395688 100644
--- a/src/arch/riscv/PMP.py
+++ b/src/arch/riscv/PMP.py
@@ -32,6 +32,6 @@
 class PMP(SimObject):
 type = "PMP"
 cxx_header = "arch/riscv/pmp.hh"
-cxx_class = "gem5::PMP"
+cxx_class = "gem5::RiscvISA::PMP"

 pmp_entries = Param.Int(16, "Maximum PMP Entries Supported")
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 3469c71..8c6c0c0 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -33,6 +33,8 @@

 #include "arch/riscv/insts/static_inst.hh"
 #include "arch/riscv/isa.hh"
+#include "arch/riscv/mmu.hh"
+#include "arch/riscv/pmp.hh"
 #include "arch/riscv/regs/misc.hh"
 #include "arch/riscv/utility.hh"
 #include "cpu/base.hh"
@@ -180,6 +182,15 @@
 tc->getIsaPtr()->newPCState(workload->getEntry(;
 panic_if(!new_pc, "Failed create new PCState from ISA pointer");
 tc->pcState(*new_pc);
+
+// Reset PMP Cfg
+auto* mmu = dynamic_cast(tc->getMMUPtr());
+if (mmu == NULL) {
+warn("MMU is not Riscv MMU instance, we can't reset PMP");
+return;
+}
+auto* pmp = dynamic_cast(mmu->getPMP());
+pmp->pmpReset();
 }

 void
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 3809c61..03c6418 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -544,6 +544,8 @@
 // qemu seems to update the tables when
 // pmp addr regs are written (with the assumption
 // that cfg regs are already written)
+RegVal res = 0;
+RegVal old_val = readMiscRegNoEffect(idx);

 for (int i=0; i < regSize; i++) {

@@ -554,10 +556,15 @@
 // Form pmp_index using the index i and
 // PMPCFG register number
 uint32_t pmp_index = i+(4*(idx-MISCREG_PMPCFG0));
-mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
+bool result =  
mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);

+if (result) {
+res |= ((RegVal)cfg_val << (8*i));
+} else {
+res |= (old_val & (0xFF << (8*i)));
+}
 }

-setMiscRegNoEffect(idx, val);
+setMiscRegNoEffect(idx, res);
 }
 break;
   case MISCREG_PMPADDR00 ... MISCREG_PMPADDR15:
@@ -568,9 +575,9 @@
 auto mmu = dynamic_cast
   (tc->getMMUPtr());
 uint32_t pmp_index = idx-MISCREG_PMPADDR00;
-mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
-
-setMiscRegNoEffect(idx, val);
+if(mmu->getPMP()->pmpUpdateAddr(pmp_index, val)){
+setMiscRegNoEffect(idx, val);
+}
 }
 break;

diff --git a/src/arch/riscv/pmp.cc b/src/arch/riscv/pmp.cc
index 77ef98f..b728347 100644
--- a/src/arch/riscv/pmp.cc
+++ b/src/arch/riscv/pmp.cc
@@ -44,10 +44,13 @@
 namespace gem5
 {

+using namespace RiscvISA;
+
 PMP::PMP(const Params ) :
 SimObject(params),
 pmpEntries(params.pmp_entries),
-numRules(0)
+numRules(0),
+hasLockEntry(false)
 {
 pmpTable.resize(pmpEntries);
 }
@@ -70,10 +73,7 @@
 req->getPaddr());
 }

-// An access should be successful if there are
-// no rules defined yet or we are in M mode (based
-// on specs v1.10)
-if (numRules == 0 || (pmode == RiscvISA::PrivilegeMode::PRV_M))
+if (numRules == 0)
 return NoFault;

 // match_index will be used to identify the pmp entry
@@ -94,20 +94,19

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

2023-02-15 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email )


 (

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Fix incorrect trap value of instruction fault
..

arch-riscv: Fix incorrect trap value of instruction fault

As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.

Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67677
Reviewed-by: Yu-hsin Wang 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/faults.hh
1 file changed, 18 insertions(+), 1 deletion(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index e664767..f687fd6 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -173,7 +173,7 @@
 : RiscvFault(n, FaultType::OTHERS, INST_ILLEGAL), _inst(inst)
 {}

-RegVal trap_value() const override { return _inst; }
+RegVal trap_value() const override { return bits(_inst, 31, 0); }
 };

 class UnknownInstFault : public InstFault

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Gerrit-Change-Number: 67677
Gerrit-PatchSet: 6
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of write to status CSR

2023-02-14 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67897?usp=email )


Change subject: arch-riscv: Fix the behavior of write to status CSR
..

arch-riscv: Fix the behavior of write to status CSR

According to RISC V spec Volumn I, Section 11.1, the CSR will be
written only if RS1 != 0 or imm != 0. However, after the change
of CL(https://gem5-review.googlesource.com/c/public/gem5/+/67717),
it will cause IllegalInstFault to write status CSR if we don't
change the data.

Example of Instruction Fault for mstatus

```
addi a5, zero, 8
csrc mstatus, a5
```

It will cause instruction fault if mstatus value is 0 due to
"newdata_all == olddata_all". We can just simply check if
the data value is changed out of mask.

Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67897
Reviewed-by: Yu-hsin Wang 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 34 insertions(+), 3 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

index afcfd7a..2dfe73a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -111,7 +111,7 @@
strcmp(mnemonic, "csrrc") == 0 ||
strcmp(mnemonic, "csrrsi") == 0 ||
strcmp(mnemonic, "csrrci") == 0 ){
-  if (RS1 == 0) {
+  if (RS1 == 0 || uimm == 0) {
 write = false;
   }
 }
diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 1bd431a..c94a0bc 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
 %(op_decl)s;
 %(op_rd)s;

-RegVal data = 0, olddata = 0;
+RegVal data = 0, olddata = 0, nonmaskdata = 0;
 auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
 if (pm < lowestAllowedMode) {
@@ -397,6 +397,7 @@

 %(code)s;

+nonmaskdata = data & ~maskVal;
 data &= maskVal;
 if (write) {
 if (bits(csr, 11, 10) == 0x3) {
@@ -419,7 +420,7 @@
   case CSR_SIP: case CSR_SIE:
   case CSR_UIP: case CSR_UIE:
   case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS:
-if (newdata_all != olddata_all) {
+if (nonmaskdata == 0) {
 xc->setMiscReg(midx, newdata_all);
 } else {
 return std::make_shared(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Gerrit-Change-Number: 67897
Gerrit-PatchSet: 2
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-CC: chengyong zhong 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the behavior of write to status CSR

2023-02-13 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67897?usp=email )



Change subject: arch-riscv: Fix the behavior of write to status CSR
..

arch-riscv: Fix the behavior of write to status CSR

According to RISC V spec Volumn I, Section 11.1, the CSR will be
written only if RS1 != 0 or imm != 0. However, after the change
of CL(https://gem5-review.googlesource.com/c/public/gem5/+/67717),
it will cause IllegalInstFault to write status CSR if we don't
change the data.

Example of Instruction Fault for mstatus

```
addi a5, zero, 8
csrc mstatus, a5
```

It will cause instruction fault if mstatus value is 0 due to
"newdata_all == olddata_all". We can just simply check if
the data value is changed out of mask.

Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 30 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

index afcfd7a..2dfe73a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -111,7 +111,7 @@
strcmp(mnemonic, "csrrc") == 0 ||
strcmp(mnemonic, "csrrsi") == 0 ||
strcmp(mnemonic, "csrrci") == 0 ){
-  if (RS1 == 0) {
+  if (RS1 == 0 || uimm == 0) {
 write = false;
   }
 }
diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 1bd431a..c94a0bc 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
 %(op_decl)s;
 %(op_rd)s;

-RegVal data = 0, olddata = 0;
+RegVal data = 0, olddata = 0, nonmaskdata = 0;
 auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
 if (pm < lowestAllowedMode) {
@@ -397,6 +397,7 @@

 %(code)s;

+nonmaskdata = data & ~maskVal;
 data &= maskVal;
 if (write) {
 if (bits(csr, 11, 10) == 0x3) {
@@ -419,7 +420,7 @@
   case CSR_SIP: case CSR_SIE:
   case CSR_UIP: case CSR_UIE:
   case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS:
-if (newdata_all != olddata_all) {
+if (nonmaskdata == 0) {
 xc->setMiscReg(midx, newdata_all);
 } else {
 return std::make_shared(

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Gerrit-Change-Number: 67897
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

2023-02-07 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email )



Change subject: arch-riscv: Fix incorrect trap value of instruction fault
..

arch-riscv: Fix incorrect trap value of instruction fault

As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.

Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
---
M src/arch/riscv/faults.hh
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index e664767..f687fd6 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -173,7 +173,7 @@
 : RiscvFault(n, FaultType::OTHERS, INST_ILLEGAL), _inst(inst)
 {}

-RegVal trap_value() const override { return _inst; }
+RegVal trap_value() const override { return bits(_inst, 31, 0); }
 };

 class UnknownInstFault : public InstFault

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Gerrit-Change-Number: 67677
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,sim-se: Support RV32 register ABI call

2023-02-01 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65532?usp=email )


 (

20 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv,sim-se: Support RV32 register ABI call
..

arch-riscv,sim-se: Support RV32 register ABI call

1. Add RegABI32, SyscallABI32
2. Support parse function arguments to host and save result to registers
3. Add write to ThreadPointerReg in archClone
4. Support RV32 M5Op syscall

Change-Id: Ie327b517f41b5d633d2741b6abb5be955281c838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65532
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Yu-hsin Wang 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.hh
M src/arch/riscv/reg_abi.cc
M src/arch/riscv/reg_abi.hh
M src/arch/riscv/se_workload.hh
7 files changed, 86 insertions(+), 10 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/formats/m5ops.isa  
b/src/arch/riscv/isa/formats/m5ops.isa

index edc965a..034a0dd 100644
--- a/src/arch/riscv/isa/formats/m5ops.isa
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -38,8 +38,12 @@
 def format M5Op() {{
 iop = InstObjParams(name, Name, 'PseudoOp', '''
 uint64_t result;
-pseudo_inst::pseudoInst(xc->tcBase(), M5FUNC,  
result);

-a0 = result''',
+if (machInst.rv_type == RV32) {
+pseudo_inst::pseudoInst(xc->tcBase(), M5FUNC,  
result);

+} else {
+pseudo_inst::pseudoInst(xc->tcBase(), M5FUNC,  
result);

+}
+a0 = rvSext(result)''',
 ['IsNonSpeculative', 'IsSerializeAfter'])
 header_output = BasicDeclare.subst(iop)
 decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index b072183..de8bccc 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -371,8 +371,10 @@
   uint64_t stack, uint64_t tls)
 {
 ctc->getIsaPtr()->copyRegsFrom(ptc);
+if (flags & TGT_CLONE_SETTLS)
+ctc->setReg(RiscvISA::ThreadPointerReg, sext<32>(tls));
 if (stack)
-ctc->setReg(RiscvISA::StackPointerReg, stack);
+ctc->setReg(RiscvISA::StackPointerReg, sext<32>(stack));
 }
 };

diff --git a/src/arch/riscv/linux/se_workload.cc  
b/src/arch/riscv/linux/se_workload.cc

index dac2807..952fe71 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -123,7 +123,7 @@
 return 0;
 }

-SyscallDescTable EmuLinux::syscallDescs64 = {
+SyscallDescTable EmuLinux::syscallDescs64 = {
 { 0,"io_setup" },
 { 1,"io_destroy" },
 { 2,"io_submit" },
@@ -462,7 +462,7 @@
 { 2011, "getmainvars" }
 };

-SyscallDescTable EmuLinux::syscallDescs32 = {
+SyscallDescTable EmuLinux::syscallDescs32 = {
 { 0,"io_setup" },
 { 1,"io_destroy" },
 { 2,"io_submit" },
diff --git a/src/arch/riscv/linux/se_workload.hh  
b/src/arch/riscv/linux/se_workload.hh

index 41a3d41..4ec818b 100644
--- a/src/arch/riscv/linux/se_workload.hh
+++ b/src/arch/riscv/linux/se_workload.hh
@@ -47,10 +47,10 @@
   protected:

 /// 64 bit syscall descriptors, indexed by call number.
-static SyscallDescTable syscallDescs64;
+static SyscallDescTable syscallDescs64;

 /// 32 bit syscall descriptors, indexed by call number.
-static SyscallDescTable syscallDescs32;
+static SyscallDescTable syscallDescs32;

   public:
 using Params = RiscvEmuLinuxParams;
diff --git a/src/arch/riscv/reg_abi.cc b/src/arch/riscv/reg_abi.cc
index b9827f7..3d48056 100644
--- a/src/arch/riscv/reg_abi.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -39,5 +39,11 @@
 int_reg::A4, int_reg::A5, int_reg::A6
 };

+const std::vector RegABI32::ArgumentRegs = {
+int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
+int_reg::A4, int_reg::A5, int_reg::A6
+};
+
+
 } // namespace RiscvISA
 } // namespace gem5
diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh
index 3419c31..4c96532 100644
--- a/src/arch/riscv/reg_abi.hh
+++ b/src/arch/riscv/reg_abi.hh
@@ -44,7 +44,36 @@
 static const std::vector ArgumentRegs;
 };

+struct RegABI32 : public GenericSyscallABI32
+{
+static const std::vector ArgumentRegs;
+};
+
 } // namespace RiscvISA
+
+namespace guest_abi
+{
+
+// This method will be used if the size of argument type of function is
+// greater than 4 for Riscv 32.
+template 
+struct Argument &&
+std::is_integral_v &&
+ABI::template IsWideV>>
+{

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct interrupt order

2023-01-10 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67211?usp=email )


 (

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: Correct interrupt order
..

arch-riscv: Correct interrupt order

In Section 3.1.14 of Volume II Riscv Spec., the interrupt order
should be MEI, MSI, MTI, SEI, SSI, STI and so on.

issues:
https://gem5.atlassian.net/browse/GEM5-889

Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211
Maintainer: Jason Lowe-Power 
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Reviewed-by: Jui-min Lee 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/interrupts.hh
1 file changed, 24 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jui-min Lee: Looks good to me, but someone else must approve
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved





diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f10c5f3..a1ee396 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,9 +125,9 @@
 return std::make_shared();
 std::bitset mask = globalMask();
 const std::vector interrupt_order {
-INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
-INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
-INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE,
+INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER,
+INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER
 };
 for (const int  : interrupt_order)
 if (checkInterrupt(id) && mask[id])

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Gerrit-Change-Number: 67211
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Peter Yuen 
Gerrit-Reviewer: Roger Chang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU

2023-01-10 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )


Change subject: arch-riscv: Check RISCV process run in matched CPU
..

arch-riscv: Check RISCV process run in matched CPU

1. Remove set RV32 flag in RiscvProcess32
2. Check if binary run appropriate CPU

Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67251
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/process.cc
1 file changed, 24 insertions(+), 5 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..cd00f5d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
 Process::initState();

 argsInit(PageBytes);
-for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+for (ContextID ctx: contextIds) {
+auto *tc = system->threads[ctx];
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits  
mode");

+}
 }

 void
@@ -114,9 +118,8 @@
 for (ContextID ctx: contextIds) {
 auto *tc = system->threads[ctx];
 tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-PCState pc = tc->pcState().as();
-pc.rvType(RV32);
-tc->pcState(pc);
+auto *isa = dynamic_cast(tc->getIsaPtr());
+fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits  
mode");

 }
 }


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Gerrit-Change-Number: 67251
Gerrit-PatchSet: 4
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Check RISCV process run in matched CPU

2023-01-09 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )



Change subject: arch-riscv: Check RISCV process run in matched CPU
..

arch-riscv: Check RISCV process run in matched CPU

The process should run correct CPU configuration instead of setting
RISCV flags by process

Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
---
M src/arch/riscv/process.cc
1 file changed, 20 insertions(+), 5 deletions(-)



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..e76933e 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
 Process::initState();

 argsInit(PageBytes);
-for (ContextID ctx: contextIds)
-system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+for (ContextID ctx: contextIds) {
+auto *tc = system->threads[ctx];
+tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+auto isa = dynamic_cast(tc->getIsaPtr());
+panic_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits  
mode");

+}
 }

 void
@@ -114,9 +118,8 @@
 for (ContextID ctx: contextIds) {
 auto *tc = system->threads[ctx];
 tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-PCState pc = tc->pcState().as();
-pc.rvType(RV32);
-tc->pcState(pc);
+auto isa = dynamic_cast(tc->getIsaPtr());
+panic_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits  
mode");

 }
 }


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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: add RV32 ADFIMU_Zfh instruction tests

2022-12-30 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65533?usp=email )


 (

35 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-riscv: add RV32 ADFIMU_Zfh instruction tests
..

arch-riscv: add RV32 ADFIMU_Zfh instruction tests

1. Add rv32 binary files into asmtests
2. Support Riscv CPU with 32 bits register to  simple_binary_run.py

Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65533
Reviewed-by: Yu-hsin Wang 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
Maintainer: Bobby Bruce 
---
M tests/gem5/asmtest/tests.py
M tests/gem5/configs/simple_binary_run.py
2 files changed, 228 insertions(+), 160 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, but someone else must approve
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index b2a5992..0ddffb2 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -34,156 +34,159 @@
 # The following lists the RISCV binaries. Those commented out presently  
result

 # in a test failure. This is outlined in the following Jira issue:
 # https://gem5.atlassian.net/browse/GEM5-496
-binaries = (
-"rv64samt-ps-sysclone_d",
-"rv64samt-ps-sysfutex1_d",
+binary_configs = (
+("rv{}samt-ps-sysclone_d", (64,)),
+("rv{}samt-ps-sysfutex1_d", (64,)),
 #'rv64samt-ps-sysfutex2_d',
-"rv64samt-ps-sysfutex3_d",
+("rv{}samt-ps-sysfutex3_d", (64,)),
 #'rv64samt-ps-sysfutex_d',
-"rv64ua-ps-amoadd_d",
-"rv64ua-ps-amoadd_w",
-"rv64ua-ps-amoand_d",
-"rv64ua-ps-amoand_w",
-"rv64ua-ps-amomax_d",
-"rv64ua-ps-amomax_w",
-"rv64ua-ps-amomaxu_d",
-"rv64ua-ps-amomaxu_w",
-"rv64ua-ps-amomin_d",
-"rv64ua-ps-amomin_w",
-"rv64ua-ps-amominu_d",
-"rv64ua-ps-amominu_w",
-"rv64ua-ps-amoor_d",
-"rv64ua-ps-amoor_w",
-"rv64ua-ps-amoswap_d",
-"rv64ua-ps-amoswap_w",
-"rv64ua-ps-amoxor_d",
-"rv64ua-ps-amoxor_w",
-"rv64ua-ps-lrsc",
-"rv64uamt-ps-amoadd_d",
-"rv64uamt-ps-amoand_d",
-"rv64uamt-ps-amomax_d",
-"rv64uamt-ps-amomaxu_d",
-"rv64uamt-ps-amomin_d",
-"rv64uamt-ps-amominu_d",
-"rv64uamt-ps-amoor_d",
-"rv64uamt-ps-amoswap_d",
-"rv64uamt-ps-amoxor_d",
-"rv64uamt-ps-lrsc_d",
-"rv64ud-ps-fadd",
-"rv64ud-ps-fclass",
-"rv64ud-ps-fcmp",
-"rv64ud-ps-fcvt",
-"rv64ud-ps-fcvt_w",
-"rv64ud-ps-fdiv",
-"rv64ud-ps-fmadd",
-"rv64ud-ps-fmin",
-"rv64ud-ps-ldst",
-"rv64ud-ps-move",
-"rv64ud-ps-recoding",
-"rv64ud-ps-structural",
-"rv64uf-ps-fadd",
-"rv64uf-ps-fclass",
-"rv64uf-ps-fcmp",
-"rv64uf-ps-fcvt",
-"rv64uf-ps-fcvt_w",
-"rv64uf-ps-fdiv",
-"rv64uf-ps-fmadd",
-"rv64uf-ps-fmin",
-"rv64uf-ps-ldst",
-"rv64uf-ps-move",
-"rv64uf-ps-recoding",
-"rv64ui-ps-add",
-"rv64ui-ps-addi",
-"rv64ui-ps-addiw",
-"rv64ui-ps-addw",
-"rv64ui-ps-and",
-"rv64ui-ps-andi",
-"rv64ui-ps-auipc",
-"rv64ui-ps-beq",
-"rv64ui-ps-bge",
-"rv64ui-ps-bgeu",
-"rv64ui-ps-blt",
-"rv64ui-ps-bltu",
-"rv64ui-ps-bne",
-"rv64ui-ps-fence_i",
-"rv64ui-ps-jal",
-"rv64ui-ps-jalr",
-"rv64ui-ps-lb",
-"rv64ui-ps-lbu",
-"rv64ui-ps-ld",
-"rv64ui-ps-lh",
-"rv64ui-ps-lhu",
-"rv64ui-ps-lui",
-"rv64ui-ps-lw",
-"rv64ui-ps-lwu",
-"rv64ui-ps-or",
-"rv64ui-ps-ori",
-"rv64ui-ps-sb",
-"rv64ui-ps-sd",
-"rv64ui-ps-sh",
-"rv64ui-ps-simple",
-"rv64ui-ps-sll",
-"rv64ui-ps-slli",
-"rv64ui-ps-slliw",
-"rv64ui-ps-sllw",
-"rv64ui-ps-slt",
-"rv64ui-ps-slti",
-"rv64ui-ps-sltiu",
-"rv64ui-ps-sltu",
-"rv64ui-ps-sra",
-"rv64ui-ps-srai",
-"rv64ui-ps-sraiw",
-"rv64ui-ps-sraw",
-"rv64ui-ps-srl",
-"rv64ui-ps-srli",
-"rv64ui-ps-srliw",
-"rv64ui-ps-srlw",
-"rv64ui-ps-sub",
-"rv64ui-ps-subw",
-"rv64ui-ps-sw",
-"rv64ui-ps-xor",
-"rv64ui-ps-xori",
-"rv64um-ps-div",
-"rv64um-ps-divu",
-"rv64um-ps-divuw",
-"rv64um-ps-divw",
-"rv64um-ps-mul",
-"rv64um-ps-mulh",
-"rv64um-ps-mulhsu",
-"rv64um-ps-mulhu",
-"rv64um-ps-mulw",
-"rv64um-ps-rem",
-"rv64um-ps-remu",
-"rv64um-ps-remuw",
-"rv64um-ps-remw",
-"rv64uzfh-ps-fadd",
-"rv64uzfh-ps-fclass",
-"rv64uzfh-ps-fcmp",
-"rv64uzfh-ps-fcvt",
-"rv64uzfh-ps-fcvt_w",
-"rv64uzfh-ps-fdiv",
-"rv64uzfh-ps-fmadd",
-"rv64uzfh-ps-fmin",
-"rv64uzfh-ps-ldst",
-"rv64uzfh-ps-move",
-"rv64uzfh-ps-recoding",
+("rv{}ua-ps-amoadd_d", (64,)),
+("rv{}ua-ps-amoadd_w", (32, 64)),
+("rv{}ua-ps-amoand_d", (64,)),
+

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...

2022-12-23 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email )


Change subject: arch-riscv: Correct the IllegalInstFault messege of  
instruction c.addi4spn

..

arch-riscv: Correct the IllegalInstFault messege of instruction
c.addi4spn

In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
https://gem5-review.git.corp.google.com/c/public/gem5/+/66732, and here is  
the additional patch to the CL.


Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66931
Reviewed-by: Yu-hsin Wang 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 20 insertions(+), 1 deletion(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c070392..53d4a4d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,7 +48,7 @@
   CIMM8<5:2> << 6;
 }}, {{
 if (imm == 0)
-return std::make_shared("zero  
instruction",

+return std::make_shared("immediate = 0",
machInst);
 Rp2 = rvSext(sp + imm);
 }}, uint64_t);

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Gerrit-Change-Number: 66931
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jui-min Lee 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Correct the IllegalInstFault messege of instruction c.add...

2022-12-22 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email )



Change subject: arch-riscv: Correct the IllegalInstFault messege of  
instruction c.addi4spn

..

arch-riscv: Correct the IllegalInstFault messege of instruction
c.addi4spn

In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
[CL](https://gem5-review.git.corp.google.com/c/public/gem5/+/66732), and  
here is the additional patch to the CL.


Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 15 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c070392..53d4a4d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,7 +48,7 @@
   CIMM8<5:2> << 6;
 }}, {{
 if (imm == 0)
-return std::make_shared("zero  
instruction",

+return std::make_shared("immediate = 0",
machInst);
 Rp2 = rvSext(sp + imm);
 }}, uint64_t);

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Refactor compressed instructions

2022-12-22 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66732?usp=email )


Change subject: arch-riscv: Refactor compressed instructions
..

arch-riscv: Refactor compressed instructions

1. C.JAL should use CJOp format to generate code
2. Use sext function to handle MSB for immediate
3. Add IsCall flags to c.jal, c.jalr
4. Use JumpConstructor to CJOp format

Change-Id: Id01c0d7cc1a3e17776890268879c568fc9996bc5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66732
Reviewed-by: Yu-hsin Wang 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/compressed.isa
2 files changed, 90 insertions(+), 94 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 458327e..c070392 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -47,7 +47,7 @@
   CIMM8<7:6> << 4 |
   CIMM8<5:2> << 6;
 }}, {{
-if (machInst == 0)
+if (imm == 0)
 return std::make_shared("zero  
instruction",

machInst);
 Rp2 = rvSext(sp + imm);
@@ -147,91 +147,71 @@
 }
 }
 0x1: decode COPCODE {
-format CIOp {
-0x0: c_addi({{
-imm = CIMM5;
-if (CIMM1 > 0)
-imm |= ~((uint64_t)0x1F);
-}}, {{
-if ((RC1 == 0) != (imm == 0)) {
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-} else { // imm == 0
-return std::make_shared(
-"immediate = 0", machInst);
-}
+0x0: CIOp::c_addi({{
+imm = sext<6>(CIMM5 | (CIMM1 << 5));
+}}, {{
+if ((RC1 == 0) != (imm == 0)) {
+if (RC1 == 0) {
+return std::make_shared(
+"source reg x0", machInst);
+} else { // imm == 0
+return std::make_shared(
+"immediate = 0", machInst);
 }
-Rc1_sd = rvSext(Rc1_sd + imm);
-}});
-0x1: decode RVTYPE {
-0x0: c_jal({{
-imm = sext<12>((CJUMPIMM3TO1 << 1) |
-   (CJUMPIMM4TO4 << 4) |
-   (CJUMPIMM5TO5 << 5) |
-   (CJUMPIMM6TO6 << 6) |
-   (CJUMPIMM7TO7 << 7) |
-   (CJUMPIMM9TO8 << 8) |
-   (CJUMPIMM10TO10 << 10) |
-   (CJUMPIMMSIGN << 11));
-}}, {{
-ra_sw = NPC_uw;
-NPC_uw = PC_uw + imm;
-}});
-0x1: c_addiw({{
-imm = CIMM5;
-if (CIMM1 > 0)
-imm |= ~((uint64_t)0x1F);
-}}, {{
-if (RC1 == 0) {
-return std::make_shared(
-"source reg x0", machInst);
-}
-Rc1_sw = (int32_t)(Rc1_sw + imm);
-}});
 }
-0x2: c_li({{
-imm = CIMM5;
-if (CIMM1 > 0)
-imm |= ~((uint64_t)0x1F);
+Rc1_sd = rvSext(Rc1_sd + imm);
+}});
+0x1: decode RVTYPE {
+0x0: CJOp::c_jal({{
+ra_sw = NPC_uw;
+NPC_uw = PC_uw + imm;
+}}, IsDirectControl, IsUncondControl, IsCall);
+0x1: CIOp::c_addiw({{
+imm = sext<6>(CIMM5 | (CIMM1 << 5));
 }}, {{
 if (RC1 == 0) {
 return std::make_shared(
 "source reg x0", machInst);
 }
+Rc1_sw = (int32_t)(Rc1_sw + imm);
+}});
+}
+0x2: CIOp::c_li({{
+imm = sext<6>(CIMM5 | (CIMM1 << 5));
+}}, {{
+if (RC1 == 0) {
+return std::make_shared(
+"source reg x0", machInst);
+}
+Rc1_sd = imm;
+}});
+0x3: decode RC1 {
+0x2: CIOp::c_addi16sp({{
+imm = sext<10>((CIMM5<4:4> << 4) |
+   (CIMM5<0:0> << 5) |
+   (CIMM5<3:3> << 6) |
+   (CIMM5<2:1> << 7) |
+   (CIMM1 <<

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor template JumpConstructor

2022-12-22 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66811?usp=email )


Change subject: arch-riscv: Refactor template JumpConstructor
..

arch-riscv: Refactor template JumpConstructor

Add COPCODE == 4 condition to ensure the available instruction is either  
c_jr or c_jalr and the flag IsReturn should set for instruction c_jalr if  
RC1 == t0


Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66811
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 23 insertions(+), 3 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 6be281f..bb500f5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -250,9 +250,14 @@
 %(constructor)s;
 %(imm_code)s;
 if (QUADRANT != 0x3) {
-// Handle "c_jr" instruction, set "IsReturn" flag if RC1 is 1  
or 5

-if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
-flags[IsReturn] = true;
+if (COPCODE == 4) {
+// Handle "c_jr" instruction, set "IsReturn" flag if RC1  
is 1 or 5

+if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
+flags[IsReturn] = true;
+// Handle "c_jalr" instruction, set IsReturn if RC1 != ra
+if (CFUNCT1 == 1 && RC1 == 5)
+flags[IsReturn] = true;
+}
 } else {
 bool rd_link = (RD == 1 || RD == 5);
 bool rs1_link = (RS1 == 1 || RS1 == 5);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Gerrit-Change-Number: 66811
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Earl Ou 
Gerrit-CC: Jui-min Lee 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Refactor template JumpConstructor

2022-12-18 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66811?usp=email )



Change subject: arch-riscv: Refactor template JumpConstructor
..

arch-riscv: Refactor template JumpConstructor

Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 17 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 6be281f..bb500f5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -250,9 +250,14 @@
 %(constructor)s;
 %(imm_code)s;
 if (QUADRANT != 0x3) {
-// Handle "c_jr" instruction, set "IsReturn" flag if RC1 is 1  
or 5

-if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
-flags[IsReturn] = true;
+if (COPCODE == 4) {
+// Handle "c_jr" instruction, set "IsReturn" flag if RC1  
is 1 or 5

+if (CFUNCT1 == 0 && (RC1 == 1 || RC1 == 5))
+flags[IsReturn] = true;
+// Handle "c_jalr" instruction, set IsReturn if RC1 != ra
+if (CFUNCT1 == 1 && RC1 == 5)
+flags[IsReturn] = true;
+}
 } else {
 bool rd_link = (RD == 1 || RD == 5);
 bool rs1_link = (RS1 == 1 || RS1 == 5);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Gerrit-Change-Number: 66811
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

2022-12-13 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66211?usp=email )


Change subject: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32  
/ rv64

..

arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

The following instructions will be supported for both rv32 and rv64

Zba extensions:
SLLI.UW
SH1ADD
SH2ADD
SH3ADD
ADD.UW
SH1ADD.UW
SH2ADD.UW
SH3ADD.UW

Zbb extensions:
CLZ
CTZ
CPOP
SEXT.B
SEXT.H
ORC.B
RORI
REV8
CLZW
CTZW
CPOPW
RORIW
ROL
MIN
XNOR
MINU
ROR
MAX
ORN
MAXU
ANDN
ROLW
ZEXT.H
RORW

Zbc extensions:
CLMUL
CLMULR
CLMULH

Zbs extensions:
BSETI
BCLRI
BINVI
BEXTI
BSET
BCLR
BINV
BEXT

Change-Id: I3f489a3a1bab8799e2d95218740e495313b9961d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66211
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
2 files changed, 240 insertions(+), 147 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/bitfields.isa  
b/src/arch/riscv/isa/bitfields.isa

index 863982c..4f58416 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -129,6 +129,7 @@

 // Cryptography instructions
 def bitfield BIT24 <24>;
+def bitfield BIT25 <25>;
 def bitfield RNUM   <23:20>;
 def bitfield KFUNCT5<29:25>;
 def bitfield BS <31:30>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8857940..458327e 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -577,8 +577,12 @@
 }});
 }
 0x05: bseti({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 | (UINT64_C(1) << index);
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 | (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x06: decode BIT24 {
 0x0: aes64im({{
@@ -589,24 +593,32 @@
 }}, imm_type = int32_t, imm_code={{ imm = RNUM;  
}});

 }
 0x09: bclri({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 & (~(UINT64_C(1) << index));
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 & (~(UINT64_C(1) << index)));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x0d: binvi({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 ^ (UINT64_C(1) << index);
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 ^ (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 }
 format ROp {
 0x0c: decode RS2 {
 0x00: clz({{
-Rd = clz64(Rs1);
+Rd = (machInst.rv_type == RV32) ? clz32(Rs1) :  
clz64(Rs1);

 }});
 0x01: ctz({{
-Rd = ctz64(Rs1);
+Rd = (machInst.rv_type == RV32) ? ctz32(Rs1) :  
ctz64(Rs1);

 }});
 0x02: cpop({{
-Rd = popCount(Rs1);
+Rd = (machInst.rv_type == RV32) ?  
popCount(Rs1<31:0>) : popCount(Rs1);

 }});
 0x04: sext_b({{
 Rd = sext<8>(Rs1_ub);
@@ -649,7 +661,7 @@
 result |= (Rs1<47:40> ? UINT64_C(0xff) : 0x0) <<  
40;
 result |= (Rs1<55:48> ? UINT64_C(0xff) : 0x0) <<  
48;
 result |= (Rs1<63:56> ? UINT64_C(0xff) : 0x0) <<  
56;

-Rd = result;
+Rd = rvSext(result);

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, tests: Refactor SimpleProcessor and SimpleCore

2022-12-08 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66592?usp=email )



Change subject: stdlib, tests: Refactor SimpleProcessor and SimpleCore
..

stdlib, tests: Refactor SimpleProcessor and SimpleCore

1. Add riscv_bits parameters to cpu_simobject_factory
2. Use Riscv32CPU if user set riscv_bits = 32

Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
---
M src/python/gem5/components/processors/simple_core.py
M src/python/gem5/components/processors/simple_processor.py
2 files changed, 27 insertions(+), 5 deletions(-)



diff --git a/src/python/gem5/components/processors/simple_core.py  
b/src/python/gem5/components/processors/simple_core.py

index 15e15dc..6391eda 100644
--- a/src/python/gem5/components/processors/simple_core.py
+++ b/src/python/gem5/components/processors/simple_core.py
@@ -42,7 +42,8 @@
 """

 def __init__(
-self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
+self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None,
+riscv_bits: int = 64,
 ):

 # If the ISA is not specified, we infer it via the  
`get_runtime_isa`

@@ -55,7 +56,8 @@

 super().__init__(
 core=SimpleCore.cpu_simobject_factory(
-isa=isa, cpu_type=cpu_type, core_id=core_id
+isa=isa, cpu_type=cpu_type, core_id=core_id,
+riscv_bits=riscv_bits,
 ),
 isa=isa,
 )
@@ -66,7 +68,9 @@
 return self._cpu_type

 @classmethod
-def cpu_simobject_factory(cls, cpu_type: CPUTypes, isa: ISA, core_id:  
int):

+def cpu_simobject_factory(
+cls, cpu_type: CPUTypes, isa: ISA, core_id: int, riscv_bits: int =  
64

+):
 """
 A factory used to return the SimObject core object given the cpu  
type,

 and ISA target. An exception will be thrown if there is an
@@ -130,6 +134,10 @@
 f"{_isa_string_map[isa]}V8"
 f"{_cpu_types_string_map[cpu_type]}"
 )
+elif riscv_bits == 32:
+cpu_class_str = (
+f"{_isa_string_map[isa]}32"  
f"{_cpu_types_string_map[cpu_type]}"

+)
 else:
 cpu_class_str = (
 f"{_isa_string_map[isa]}"  
f"{_cpu_types_string_map[cpu_type]}"
diff --git a/src/python/gem5/components/processors/simple_processor.py  
b/src/python/gem5/components/processors/simple_processor.py

index 510e37d..0cafed1 100644
--- a/src/python/gem5/components/processors/simple_processor.py
+++ b/src/python/gem5/components/processors/simple_processor.py
@@ -42,7 +42,8 @@
 """

 def __init__(
-self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] = None
+self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] =  
None,

+riscv_bits: int = 64,
 ) -> None:
 """
 :param cpu_type: The CPU type for each type in the processor.
@@ -64,7 +65,8 @@
 )
 super().__init__(
 cores=[
-SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)
+SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa,
+   riscv_bits=riscv_bits)
 for i in range(num_cores)
 ]
 )

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
Gerrit-Change-Number: 66592
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Add basic features toward rv32 support

2022-12-02 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63091?usp=email )


Change subject: arch-riscv: Add basic features toward rv32 support
..

arch-riscv: Add basic features toward rv32 support

Various changes to support rv32:
1. Add riscv_bits field into RiscvISA to switch rv_type
2. Add rv_type field into ExtMachInst
3. Split various constants into rv32/rv64 version
4. Fix mcause/mstatus/misa setting per rv_type
5. Split RiscvCPU into rv32/rv64
6. Fix how reset/branch create new pc so rv_type is preserved
7. Tag gdb-xml only for rv64

TODO:
Add rv32 gdb-xml
Add rv32 implementation into decoder

Currently there're three places where we store the rv_type information
(1) ISA (2) PCState (3) ExtMachInst. In theory, the ISA should be the
source of truth, and propagates information into PCState, then Inst.

However, there is an API on RiscvProcess that let users modify the
rv_type in PCState, so there's a chance to get inconsistent rv_type. We
should either modify the structure so such kind of usage is well
supported, or just prohibit people from setting a different rv_type.

Change-Id: If5685ae60f8d18f4f2e18137e235989e63156404
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63091
Reviewed-by: Yu-hsin Wang 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/RiscvCPU.py
M src/arch/riscv/RiscvISA.py
M src/arch/riscv/SConscript
M src/arch/riscv/decoder.cc
M src/arch/riscv/faults.cc
M src/arch/riscv/gdb-xml/SConscript
R src/arch/riscv/gdb-xml/riscv-64bit.xml
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/pcstate.hh
M src/arch/riscv/process.cc
M src/arch/riscv/regs/misc.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/riscv/types.hh
21 files changed, 301 insertions(+), 121 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Yu-hsin Wang: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py
index 1c77045..678c329 100644
--- a/src/arch/riscv/RiscvCPU.py
+++ b/src/arch/riscv/RiscvCPU.py
@@ -23,6 +23,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+import functools
+
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
 from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
 from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
@@ -41,6 +43,13 @@
 ArchISA = RiscvISA


+class Riscv32CPU:
+ArchDecoder = RiscvDecoder
+ArchMMU = RiscvMMU
+ArchInterrupts = RiscvInterrupts
+ArchISA = functools.partial(RiscvISA, riscv_type="RV32")
+
+
 class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
 mmu = RiscvMMU()

@@ -59,3 +68,23 @@

 class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
 mmu = RiscvMMU()
+
+
+class Riscv32AtomicSimpleCPU(BaseAtomicSimpleCPU, Riscv32CPU):
+mmu = RiscvMMU()
+
+
+class Riscv32NonCachingSimpleCPU(BaseNonCachingSimpleCPU, Riscv32CPU):
+mmu = RiscvMMU()
+
+
+class Riscv32TimingSimpleCPU(BaseTimingSimpleCPU, Riscv32CPU):
+mmu = RiscvMMU()
+
+
+class Riscv32O3CPU(BaseO3CPU, Riscv32CPU):
+mmu = RiscvMMU()
+
+
+class Riscv32MinorCPU(BaseMinorCPU, Riscv32CPU):
+mmu = RiscvMMU()
diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index ee98a5b..e2381fd 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -38,10 +38,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from m5.params import Enum
 from m5.params import Param
 from m5.objects.BaseISA import BaseISA


+class RiscvType(Enum):
+vals = ["RV32", "RV64"]
+
+
 class RiscvISA(BaseISA):
 type = "RiscvISA"
 cxx_class = "gem5::RiscvISA::ISA"
@@ -50,3 +55,4 @@
 check_alignment = Param.Bool(
 False, "whether to check memory access alignment"
 )
+riscv_type = Param.RiscvType("RV64", "RV32 or RV64")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index dd4e9ae..924bba5 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -70,7 +70,8 @@
 tags='riscv isa')
 SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'],
 tags='riscv isa')
-SimObject('RiscvISA.py', sim_objects=['RiscvISA'], tags='riscv isa')
+SimObject('RiscvISA.py', sim_objects=['RiscvISA'],
+enums=['RiscvType'], tags='riscv isa')
 SimObject('RiscvMMU.py', sim_objects=['RiscvMMU'], tags='riscv isa')

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

2022-11-30 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66211?usp=email )



Change subject: arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32  
/ rv64

..

arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64

The following instructions will be supported for both rv32 and rv64

Zba extensions:
SLLI.UW
SH1ADD
SH2ADD
SH3ADD
ADD.UW
SH1ADD.UW
SH2ADD.UW
SH3ADD.UW

Zbb extensions:
CLZ
CTZ
CPOP
SEXT.B
SEXT.H
ORC.B
RORI
REV8
CLZW
CTZW
CPOPW
RORIW
ROL
MIN
XNOR
MINU
ROR
MAX
ORN
MAXU
ANDN
ROLW
ZEXT.H
RORW

Zbc extensions:
CLMUL
CLMULR
CLMULH

Zbs extensions:
BSETI
BCLRI
BINVI
BEXTI
BSET
BCLR
BINV
BEXT

Change-Id: I3f489a3a1bab8799e2d95218740e495313b9961d
---
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
2 files changed, 254 insertions(+), 147 deletions(-)



diff --git a/src/arch/riscv/isa/bitfields.isa  
b/src/arch/riscv/isa/bitfields.isa

index 863982c..4f58416 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -129,6 +129,7 @@

 // Cryptography instructions
 def bitfield BIT24 <24>;
+def bitfield BIT25 <25>;
 def bitfield RNUM   <23:20>;
 def bitfield KFUNCT5<29:25>;
 def bitfield BS <31:30>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a0d86bc..284a2e8 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -577,8 +577,12 @@
 }});
 }
 0x05: bseti({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 | (UINT64_C(1) << index);
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 | (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x06: decode BIT24 {
 0x0: aes64im({{
@@ -589,24 +593,50 @@
 }}, imm_type = int32_t, imm_code={{ imm = RNUM;  
}});

 }
 0x09: bclri({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 & (~(UINT64_C(1) << index));
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 & (~(UINT64_C(1) << index)));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x0d: binvi({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 ^ (UINT64_C(1) << index);
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 ^ (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 }
 format ROp {
 0x0c: decode RS2 {
 0x00: clz({{
-Rd = clz64(Rs1);
+uint64_t result = 0;
+if (machInst.rv_type == RV32) {
+result = clz32(Rs1);
+} else {
+result = clz64(Rs1);
+}
+Rd = result;
 }});
 0x01: ctz({{
-Rd = ctz64(Rs1);
+uint64_t result = 0;
+if (machInst.rv_type == RV32) {
+result = ctz32(Rs1);
+} else {
+result = ctz64(Rs1);
+}
+Rd = result;
 }});
 0x02: cpop({{
-Rd = popCount(Rs1);
+uint64_t result = 0;
+if (machInst.rv_type == RV32) {
+result = popCount(Rs1<31:0>);
+} else {
+result = popCount(Rs1);
+}
+Rd = result;

[gem5-dev] [L] Change in gem5/gem5[develop]: Add another instructions

2022-11-29 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66191?usp=email )



Change subject: Add another instructions
..

Add another instructions

Change-Id: Id0b7ab2772fd1b21c1ee41075df44a5b6dbe5b47
---
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
2 files changed, 270 insertions(+), 193 deletions(-)



diff --git a/src/arch/riscv/isa/bitfields.isa  
b/src/arch/riscv/isa/bitfields.isa

index 863982c..4f58416 100644
--- a/src/arch/riscv/isa/bitfields.isa
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -129,6 +129,7 @@

 // Cryptography instructions
 def bitfield BIT24 <24>;
+def bitfield BIT25 <25>;
 def bitfield RNUM   <23:20>;
 def bitfield KFUNCT5<29:25>;
 def bitfield BS <31:30>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a0d86bc..9105a71 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -557,18 +557,26 @@
 0x3: sha256sig1({{
 Rd_sw = _rvk_emu_sha256sig1(Rs1_sw);
 }});
-0x4: sha512sum0({{
-Rd_sd = _rvk_emu_sha512sum0(Rs1_sd);
-}});
-0x5: sha512sum1({{
-Rd_sd = _rvk_emu_sha512sum1(Rs1_sd);
-}});
-0x6: sha512sig0({{
-Rd_sd = _rvk_emu_sha512sig0(Rs1_sd);
-}});
-0x7: sha512sig1({{
-Rd_sd = _rvk_emu_sha512sig1(Rs1_sd);
-}});
+0x4: decode RVTYPE {
+0x1: sha512sum0({{
+Rd_sd = _rvk_emu_sha512sum0(Rs1_sd);
+}});
+}
+0x5: decode RVTYPE {
+0x1: sha512sum1({{
+Rd_sd = _rvk_emu_sha512sum1(Rs1_sd);
+}});
+}
+0x6: decode RVTYPE {
+0x1: sha512sig0({{
+Rd_sd = _rvk_emu_sha512sig0(Rs1_sd);
+}});
+}
+0x7: decode RVTYPE {
+0x1: sha512sig1({{
+Rd_sd = _rvk_emu_sha512sig1(Rs1_sd);
+}});
+}
 0x8: sm3p0({{
 Rd_sw = _rvk_emu_sm3p0(Rs1_sw);
 }});
@@ -577,36 +585,68 @@
 }});
 }
 0x05: bseti({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 | (UINT64_C(1) << index);
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 | (UINT64_C(1) << index));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

-0x06: decode BIT24 {
-0x0: aes64im({{
-Rd_sd = _rvk_emu_aes64im(Rs1_sd);
-}});
-0x1: aes64ks1i({{
-Rd_sd = _rvk_emu_aes64ks1i(Rs1_sd, imm);
-}}, imm_type = int32_t, imm_code={{ imm = RNUM;  
}});

+0x06: decode RVTYPE {
+0x1: decode BIT24 {
+0x0: aes64im({{
+Rd_sd = _rvk_emu_aes64im(Rs1_sd);
+}});
+0x1: aes64ks1i({{
+Rd_sd = _rvk_emu_aes64ks1i(Rs1_sd, imm);
+}}, imm_type = int32_t, imm_code={{ imm =  
RNUM; }});

+}
 }
 0x09: bclri({{
-uint64_t index = imm & (64 - 1);
-Rd = Rs1 & (~(UINT64_C(1) << index));
+if (rvSelect((bool)SHAMT6BIT5, false)) {
+return std::make_shared(
+"shmat[5] != 0", machInst);
+}
+uint64_t index = imm & rvSelect(32 - 1, 64 - 1);
+Rd = rvSext(Rs1 & (~(UINT64_C(1) << index)));
 }}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;  
}});

 0x0d: binvi({{
-uint64_t index = imm &

[gem5-dev] [L] Change in gem5/gem5[develop]: Implement rv32 zicsr extension

2022-11-17 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65733?usp=email )



Change subject: Implement rv32 zicsr extension
..

Implement rv32 zicsr extension

1. Add misc register mstatush, cycleh, timeh, instreth,
   hpmcounter03...hpmcounter31, pmpcfg1, pmpcfg3
2. Implement handling RV32 only registers
3. Implement methods of set time CSR
4. add cycleh, timeh to gdb-xml

Change-Id: I5c55c18a0da91977d6e23da24ea3cbcba9f0509b
---
M src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
M src/arch/riscv/isa.cc
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/regs/misc.hh
M src/dev/riscv/clint.cc
5 files changed, 495 insertions(+), 205 deletions(-)



diff --git a/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml  
b/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml

index 8d56ad5..fee676e 100644
--- a/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
+++ b/src/arch/riscv/gdb-xml/riscv-32bit-csr.xml
@@ -56,6 +56,8 @@
   
   
   
+  
+

[gem5-dev] [L] Change in gem5/gem5[develop]: RV32 tests

2022-11-15 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65533?usp=email )



Change subject: RV32 tests
..

RV32 tests

Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
---
M tests/gem5/asmtest/tests.py
A tests/gem5/configs/riscv_binary_run.py
2 files changed, 232 insertions(+), 143 deletions(-)



diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index b2a5992..9f3e065 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -26,153 +26,31 @@

 from testlib import *

-if config.bin_path:
-resource_path = config.bin_path
-else:
-resource_path = joinpath(absdirpath(__file__), "..", "resources")
+import glob
+import os

 # The following lists the RISCV binaries. Those commented out presently  
result

 # in a test failure. This is outlined in the following Jira issue:
 # https://gem5.atlassian.net/browse/GEM5-496
-binaries = (
-"rv64samt-ps-sysclone_d",
-"rv64samt-ps-sysfutex1_d",
-#'rv64samt-ps-sysfutex2_d',
-"rv64samt-ps-sysfutex3_d",
-#'rv64samt-ps-sysfutex_d',
-"rv64ua-ps-amoadd_d",
-"rv64ua-ps-amoadd_w",
-"rv64ua-ps-amoand_d",
-"rv64ua-ps-amoand_w",
-"rv64ua-ps-amomax_d",
-"rv64ua-ps-amomax_w",
-"rv64ua-ps-amomaxu_d",
-"rv64ua-ps-amomaxu_w",
-"rv64ua-ps-amomin_d",
-"rv64ua-ps-amomin_w",
-"rv64ua-ps-amominu_d",
-"rv64ua-ps-amominu_w",
-"rv64ua-ps-amoor_d",
-"rv64ua-ps-amoor_w",
-"rv64ua-ps-amoswap_d",
-"rv64ua-ps-amoswap_w",
-"rv64ua-ps-amoxor_d",
-"rv64ua-ps-amoxor_w",
-"rv64ua-ps-lrsc",
-"rv64uamt-ps-amoadd_d",
-"rv64uamt-ps-amoand_d",
-"rv64uamt-ps-amomax_d",
-"rv64uamt-ps-amomaxu_d",
-"rv64uamt-ps-amomin_d",
-"rv64uamt-ps-amominu_d",
-"rv64uamt-ps-amoor_d",
-"rv64uamt-ps-amoswap_d",
-"rv64uamt-ps-amoxor_d",
-"rv64uamt-ps-lrsc_d",
-"rv64ud-ps-fadd",
-"rv64ud-ps-fclass",
-"rv64ud-ps-fcmp",
-"rv64ud-ps-fcvt",
-"rv64ud-ps-fcvt_w",
-"rv64ud-ps-fdiv",
-"rv64ud-ps-fmadd",
-"rv64ud-ps-fmin",
-"rv64ud-ps-ldst",
-"rv64ud-ps-move",
-"rv64ud-ps-recoding",
-"rv64ud-ps-structural",
-"rv64uf-ps-fadd",
-"rv64uf-ps-fclass",
-"rv64uf-ps-fcmp",
-"rv64uf-ps-fcvt",
-"rv64uf-ps-fcvt_w",
-"rv64uf-ps-fdiv",
-"rv64uf-ps-fmadd",
-"rv64uf-ps-fmin",
-"rv64uf-ps-ldst",
-"rv64uf-ps-move",
-"rv64uf-ps-recoding",
-"rv64ui-ps-add",
-"rv64ui-ps-addi",
-"rv64ui-ps-addiw",
-"rv64ui-ps-addw",
-"rv64ui-ps-and",
-"rv64ui-ps-andi",
-"rv64ui-ps-auipc",
-"rv64ui-ps-beq",
-"rv64ui-ps-bge",
-"rv64ui-ps-bgeu",
-"rv64ui-ps-blt",
-"rv64ui-ps-bltu",
-"rv64ui-ps-bne",
-"rv64ui-ps-fence_i",
-"rv64ui-ps-jal",
-"rv64ui-ps-jalr",
-"rv64ui-ps-lb",
-"rv64ui-ps-lbu",
-"rv64ui-ps-ld",
-"rv64ui-ps-lh",
-"rv64ui-ps-lhu",
-"rv64ui-ps-lui",
-"rv64ui-ps-lw",
-"rv64ui-ps-lwu",
-"rv64ui-ps-or",
-"rv64ui-ps-ori",
-"rv64ui-ps-sb",
-"rv64ui-ps-sd",
-"rv64ui-ps-sh",
-"rv64ui-ps-simple",
-"rv64ui-ps-sll",
-"rv64ui-ps-slli",
-"rv64ui-ps-slliw",
-"rv64ui-ps-sllw",
-"rv64ui-ps-slt",
-"rv64ui-ps-slti",
-"rv64ui-ps-sltiu",
-"rv64ui-ps-sltu",
-"rv64ui-ps-sra",
-"rv64ui-ps-srai",
-"rv64ui-ps-sraiw",
-"rv64ui-ps-sraw",
-"rv64ui-ps-srl",
-"rv64ui-ps-srli",
-"rv64ui-ps-srliw",
-"rv64ui-ps-srlw",
-"rv64ui-ps-sub",
-"rv64ui-ps-subw",
-"rv64ui-ps-sw",
-"rv64ui-ps-xor",
-"rv64ui-ps-xori",
-"rv64um-ps-div",
-"rv64um-ps-divu",
-"rv64um-ps-divuw",
-"rv64um-ps-divw",
-"rv64um-ps-mul",
-"rv64um-ps-mulh",
-"rv64um-ps-mulhsu",
-"rv64um-ps-mulhu",
-"rv64um-ps-mulw",
-"rv64um-ps-rem",
-"rv64um-ps-remu",
-"rv64um-ps-remuw",
-"rv64um-ps-remw",
-"rv64uzfh-ps-fadd",
-"rv64uzfh-ps-fclass",
-"rv64uzfh-ps-fcmp",
-"rv64uzfh-ps-fcvt",
-"rv64uzfh-ps-fcvt_w",
-"rv64uzfh-ps-fdiv",
-"rv64uzfh-ps-fmadd",
-"rv64uzfh-ps-fmin",
-"rv64uzfh-ps-ldst",
-"rv64uzfh-ps-move",
-"rv64uzfh-ps-recoding",
-)
+riscv_tests = '/opt/riscv/target/share/riscv-tests'
+binaries64_path = glob.glob(os.path.join(riscv_tests, 'isa/rv64*-ps*'))
+binaries64_path = sorted(list(filter(
+lambda path: not path.endswith('.dump'),
+binaries64_path,
+)))
+
+binaries32_path = glob.glob(os.path.join(riscv_tests, 'isa/rv32*-ps*'))
+binaries32_path = sorted(list(filter(
+lambda path: not path.endswith('.dump'),
+binaries32_path,
+)))

 cpu_types = ("atomic", "timing", "minor", "o3")

 for cpu_type in cpu_types:
-for binary in binaries:
+for path in binaries64_path:
+binary = os.path.basename(path)
+bindir = os.path.dirname(path)
 gem5_verify_config(
 name=f"asm-riscv-{binary}-{cpu_type}",

[gem5-dev] [M] Change in gem5/gem5[develop]: Add rv32 Syscall ABI

2022-11-15 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65532?usp=email )



Change subject: Add rv32 Syscall ABI
..

Add rv32 Syscall ABI

1. Change default value of arch to Unknown
2. Add RegABI32, SyscallABI32
3. Implement function arguments and results assignment with registers
4. Add write to ThreadPointerReg in archClone

Change-Id: Ie327b517f41b5d633d2741b6abb5be955281c838
---
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.hh
M src/arch/riscv/reg_abi.cc
M src/arch/riscv/reg_abi.hh
M src/arch/riscv/se_workload.hh
6 files changed, 67 insertions(+), 7 deletions(-)



diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index b072183..fc651cb 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -371,6 +371,8 @@
   uint64_t stack, uint64_t tls)
 {
 ctc->getIsaPtr()->copyRegsFrom(ptc);
+if (flags & TGT_CLONE_SETTLS)
+ctc->setReg(RiscvISA::ThreadPointerReg, sext<32>(tls));
 if (stack)
 ctc->setReg(RiscvISA::StackPointerReg, stack);
 }
diff --git a/src/arch/riscv/linux/se_workload.cc  
b/src/arch/riscv/linux/se_workload.cc

index dac2807..952fe71 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -123,7 +123,7 @@
 return 0;
 }

-SyscallDescTable EmuLinux::syscallDescs64 = {
+SyscallDescTable EmuLinux::syscallDescs64 = {
 { 0,"io_setup" },
 { 1,"io_destroy" },
 { 2,"io_submit" },
@@ -462,7 +462,7 @@
 { 2011, "getmainvars" }
 };

-SyscallDescTable EmuLinux::syscallDescs32 = {
+SyscallDescTable EmuLinux::syscallDescs32 = {
 { 0,"io_setup" },
 { 1,"io_destroy" },
 { 2,"io_submit" },
diff --git a/src/arch/riscv/linux/se_workload.hh  
b/src/arch/riscv/linux/se_workload.hh

index 41a3d41..4ec818b 100644
--- a/src/arch/riscv/linux/se_workload.hh
+++ b/src/arch/riscv/linux/se_workload.hh
@@ -47,10 +47,10 @@
   protected:

 /// 64 bit syscall descriptors, indexed by call number.
-static SyscallDescTable syscallDescs64;
+static SyscallDescTable syscallDescs64;

 /// 32 bit syscall descriptors, indexed by call number.
-static SyscallDescTable syscallDescs32;
+static SyscallDescTable syscallDescs32;

   public:
 using Params = RiscvEmuLinuxParams;
diff --git a/src/arch/riscv/reg_abi.cc b/src/arch/riscv/reg_abi.cc
index b9827f7..3d48056 100644
--- a/src/arch/riscv/reg_abi.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -39,5 +39,11 @@
 int_reg::A4, int_reg::A5, int_reg::A6
 };

+const std::vector RegABI32::ArgumentRegs = {
+int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
+int_reg::A4, int_reg::A5, int_reg::A6
+};
+
+
 } // namespace RiscvISA
 } // namespace gem5
diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh
index 3419c31..ee94698 100644
--- a/src/arch/riscv/reg_abi.hh
+++ b/src/arch/riscv/reg_abi.hh
@@ -44,6 +44,11 @@
 static const std::vector ArgumentRegs;
 };

+struct RegABI32 : public GenericSyscallABI32
+{
+static const std::vector ArgumentRegs;
+};
+
 } // namespace RiscvISA
 } // namespace gem5

diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index 6f7c2ed..a8a0248 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -58,10 +58,11 @@
 params().remote_gdb_port, system);
 }

-loader::Arch getArch() const override { return loader::Riscv64; }
+loader::Arch getArch() const override { return loader::UnknownArch; }

 //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
-using SyscallABI = RegABI64;
+using SyscallABI64 = RegABI64;
+using SyscallABI32 = RegABI32;
 };

 } // namespace RiscvISA
@@ -70,8 +71,40 @@
 namespace guest_abi
 {

+template 
+struct Argument &&
+std::is_integral_v &&
+ABI::template IsWideV>>
+{
+static Arg
+get(ThreadContext *tc, typename ABI::State )
+{
+panic_if(state >= ABI::ArgumentRegs.size(),
+"Ran out of syscall argument registers.");
+return bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
+}
+};
+
 template <>
-struct Result
+struct Result
+{
+static void
+store(ThreadContext *tc, const SyscallReturn )
+{
+if (ret.successful()) {
+// no error
+tc->setReg(RiscvISA::ReturnValueReg, ret.returnValue());
+} else {
+// got an error, return details
+tc->setReg(RiscvISA::ReturnValueReg, ret.encodedValue());
+}
+}
+};
+
+template <>
+struct Result
 {
 static void
 store(ThreadContext *tc, const SyscallReturn )

--
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim-se: change sizeof output pid buffer to 4

2022-11-10 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65531?usp=email )



Change subject: sim-se: change sizeof output pid buffer to 4
..

sim-se: change sizeof output pid buffer to 4

The sizeof pid should be 4 and should not overwrite the other fields

Change-Id: Ic9b25701e2b9968e29c14afe4c04bf64f705136a
---
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
2 files changed, 19 insertions(+), 8 deletions(-)



diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index c212d24..e98ec1b 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -94,8 +94,8 @@
 exitFutexWake(ThreadContext *tc, VPtr<> addr, uint64_t tgid)
 {
 // Clear value at address pointed to by thread's childClearTID field.
-BufferArg ctidBuf(addr, sizeof(long));
-long *ctid = (long *)ctidBuf.bufferPtr();
+BufferArg ctidBuf(addr, sizeof(int));
+int *ctid = (int *)ctidBuf.bufferPtr();
 *ctid = 0;
 ctidBuf.copyOut(SETranslatingPortProxy(tc));

diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index b4550dd..efd490d 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1668,9 +1668,9 @@
 owner->revokeThreadContext(ctc->contextId());

 if (flags & OS::TGT_CLONE_PARENT_SETTID) {
-BufferArg ptidBuf(ptidPtr, sizeof(long));
-long *ptid = (long *)ptidBuf.bufferPtr();
-*ptid = cp->pid();
+BufferArg ptidBuf(ptidPtr, sizeof(int));
+int *ptid = (int *)ptidBuf.bufferPtr();
+*ptid = (int)cp->pid();
 ptidBuf.copyOut(SETranslatingPortProxy(tc));
 }

@@ -1692,9 +1692,9 @@
 }

 if (flags & OS::TGT_CLONE_CHILD_SETTID) {
-BufferArg ctidBuf(ctidPtr, sizeof(long));
-long *ctid = (long *)ctidBuf.bufferPtr();
-*ctid = cp->pid();
+BufferArg ctidBuf(ctidPtr, sizeof(int));
+int *ctid = (int *)ctidBuf.bufferPtr();
+*ctid = (int)cp->pid();
 ctidBuf.copyOut(SETranslatingPortProxy(ctc));
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic9b25701e2b9968e29c14afe4c04bf64f705136a
Gerrit-Change-Number: 65531
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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