Re: Addressing Scheme with 64 vs 63 bits

2008-10-23 Thread Shmuel Metz (Seymour J.)
In [EMAIL PROTECTED], on 10/21/2008
   at 05:30 PM, Scott Ford [EMAIL PROTECTED] said:

Starting writing Assembler on a 360/20,, man 704 days...

I won't try to justify the 704, but one (IBMAP) of the assemblers on,
e.g., the 709, 7090, had a facility (QUAL) that HLA still doesn't have.
And the convert instructions were cool.
 
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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Edward Jaffe

Robert A. Rosenberg wrote:
There was also the secondary use of the high bit to signal AM24 vs 
AM31 in addresses used for branching to/from subroutines. This 
required replacing BALR with BASR and BR with BSM to do the AM Mode 
Switch.


And, the low-order bit of the address now indicates switching to 64-bit 
mode using pointer-defined linkage. This has caused a number of software 
issues for code that tried to process those pointers using other 
instructions without first clearing bit 63.


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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Anne Lynn Wheeler
The following message is a courtesy copy of an article
that has been posted to bit.listserv.ibm-main as well.


[EMAIL PROTECTED] (Robert A. Rosenberg) writes:
 There was also the secondary use of the high bit to signal AM24 vs
 AM31 in addresses used for branching to/from subroutines. This
 required replacing BALR with BASR and BR with BSM to do the AM Mode
 Switch.

360/370 24bit psw had ILC/CC and program mask in adjacent byte; BAL/BALR
not only saved the 24bit instruction address but also the next byte of
the PSW (cc, and program mask).

on return, not only could the calling/return address be restored, but
SPM instruction would also be used to restore the program mask ... aka
from principle of ops SPM programming notes:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dz9zr003/7.5.113?DT=20040504121320

  1. Bits 34-39 of the general register may have been loaded from the PSW
by execution of BRANCH AND LINK in the 24-bit addressing mode or by
execution of INSERT PROGRAM MASK in either the 24-bit or 31-bit
addressing mode.

  2. SET PROGRAM MASK permits setting of the condition code and the mask
bits in either the problem state or the supervisor state.

  3. The program should take into consideration that the setting of the
program mask can have a significant effect on subsequent execution of
the program. Not only do the four mask bits control whether the
corresponding interruptions occur, but the exponent-underflow and
significance masks also determine the result which is obtained.

... snip ..

BAS/BASR were introduced on 360/67 as part of supporting 32bit virtual
addressing mode.

retrenching to 370 ... not only was 360/67 32bit virtual addressing
dropped ... but also the channel controller for multiprocessor support
... standard 360/67 multiprocessor not only allowed all processors to
address all real storage but also all channels.

standard 360 (and later 370) multiprocessor support only allowed two
processors to address all of the (same) real storage ... but each
processor was limited to only addressing their own, dedicated channels.

some of the 360/67 control registers were also used to sense the
switches on the channel controller (which governed the multiprocessor
configuration settings ... not only for channels but also for real
storage) ... these control register definitions were later taken over
for access registers

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Patrick O'Keefe
On Mon, 20 Oct 2008 22:00:00 -0500, Paul Gilmartin 
[EMAIL PROTECTED] wrote:

...
I thought 31-bit was for compatibility with existing exploitation
of the sign bit; ...

Nope, it was the use of a X'80' in the high-order byte of a fullword to
terminate a variable-length parameter list (of fullwords).

Nope?  Where do you perceive us to be in disagreement?
...

There's a slight semantic difference.  Sign vs. flag.  Two different
uses of the same high order bit, neither of which is compatable with 
a 32 bit address.

Pat O'Keefe

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread J R
Right, but I think it's fairly clear that they 
were both talking about the same thing.  
 
 
 Date: Tue, 21 Oct 2008 14:16:43 -0500
 From: [EMAIL PROTECTED]
 Subject: Re: Addressing Scheme with 64 vs 63 bits
 To: IBM-MAIN@BAMA.UA.EDU
 
 On Mon, 20 Oct 2008 22:00:00 -0500, Paul Gilmartin 
 [EMAIL PROTECTED] wrote:
 
 ...
 I thought 31-bit was for compatibility with existing exploitation
 of the sign bit; ...
 
 Nope, it was the use of a X'80' in the high-order byte of a fullword to
 terminate a variable-length parameter list (of fullwords).
 
 Nope? Where do you perceive us to be in disagreement?
 ...
 
 There's a slight semantic difference. Sign vs. flag. Two different
 uses of the same high order bit, neither of which is compatable with 
 a 32 bit address.
 
 Pat O'Keefe
 
 
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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Paul Gilmartin
On Tue, 21 Oct 2008 15:38:56 -0400, J R wrote:

Right, but I think it's fairly clear that they 
were both talking about the same thing.  
 
... and I chose the term simply because I can never
remember which systems number bits left-to-right, and
which right to left, or start with 0, or start with 1.
And I think the IBM 704 didn't even number the sign
bit -- it was simply S, and didn't (sometimes)
participate in shift instructions.

 Date: Tue, 21 Oct 2008 14:16:43 -0500
 From: [EMAIL PROTECTED]
 
 Nope? Where do you perceive us to be in disagreement?
 ...
 
 There's a slight semantic difference. Sign vs. flag. Two different
 uses of the same high order bit, neither of which is compatable with 
 a 32 bit address.

-- gil

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Scott Ford
Gil -- same here...but I don't get hung up on semantics..I translate
flag/sign when speaking in assembler-ese...


Regards,
Scott Ford
Senior Systems Engineer

 
[p] 678.266.3399 x304[m] 609-346-0399  identityforge.com



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-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Paul Gilmartin
Sent: Tuesday, October 21, 2008 4:25 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Addressing Scheme with 64 vs 63 bits

On Tue, 21 Oct 2008 15:38:56 -0400, J R wrote:

Right, but I think it's fairly clear that they 
were both talking about the same thing.  
 
... and I chose the term simply because I can never
remember which systems number bits left-to-right, and
which right to left, or start with 0, or start with 1.
And I think the IBM 704 didn't even number the sign
bit -- it was simply S, and didn't (sometimes)
participate in shift instructions.

 Date: Tue, 21 Oct 2008 14:16:43 -0500
 From: [EMAIL PROTECTED]
 
 Nope? Where do you perceive us to be in disagreement?
 ...
 
 There's a slight semantic difference. Sign vs. flag. Two different
 uses of the same high order bit, neither of which is compatable with 
 a 32 bit address.

-- gil

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Gerhard Postpischil

Paul Gilmartin wrote:

... and I chose the term simply because I can never
remember which systems number bits left-to-right, and
which right to left, or start with 0, or start with 1.
And I think the IBM 704 didn't even number the sign
bit -- it was simply S, and didn't (sometimes)
participate in shift instructions.


It's simple, the bits on the 360, et seq. are numbered in the 
same direction as on the 704, etc.


And I really missed the instruction to shift only the sign bit 
from the AC to the MQ.




Gerhard Postpischil
Bradford, VT

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-21 Thread Scott Ford
Yeah Gerhard and Gil,

Starting writing Assembler on a 360/20,, man 704 days...

Scott Ford
Senior Systems Engineer

 
[p] 678.266.3399 x304[m] 609-346-0399  identityforge.com



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-Original Message-
From: IBM Mainframe Discussion List [mailto:[EMAIL PROTECTED] On Behalf
Of Gerhard Postpischil
Sent: Tuesday, October 21, 2008 5:16 PM
To: IBM-MAIN@BAMA.UA.EDU
Subject: Re: Addressing Scheme with 64 vs 63 bits

Paul Gilmartin wrote:
 ... and I chose the term simply because I can never
 remember which systems number bits left-to-right, and
 which right to left, or start with 0, or start with 1.
 And I think the IBM 704 didn't even number the sign
 bit -- it was simply S, and didn't (sometimes)
 participate in shift instructions.

It's simple, the bits on the 360, et seq. are numbered in the 
same direction as on the 704, etc.

And I really missed the instruction to shift only the sign bit 
from the AC to the MQ.



Gerhard Postpischil
Bradford, VT

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Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread Mohammad Khan
And why was it expected to be 63 bit ? Was there an expectation that one 
bit will be used to distinguish a 63 bit address from 31 / 24 bit addresses ?

Mohammad


On Sun, 19 Oct 2008 23:33:22 -0700, Edward Jaffe 
[EMAIL PROTECTED] wrote:

It's analogous to why IBM implemented 64-bit addressing instead of the
expected 63-bit. Both systems will address more data than all of the
DASD in the world. But, the competitors would have convinced these
idiots that 64-bit was superior to 63-bit. (Just a bit better.  ;-) )


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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread Edward Jaffe

Mohammad Khan wrote:
And why was it expected to be 63 bit ? Was there an expectation that one 
bit will be used to distinguish a 63 bit address from 31 / 24 bit addresses ?
  


During the early discussions, many people expected ESAME to implement 
63-bit addressing for reasons similar to why XA/370, ESA/370, and 
ESA/390 implemented 31-bit and not 32-bit addressing.


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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread Paul Gilmartin
On Mon, 20 Oct 2008 09:57:12 -0700, Edward Jaffe wrote:

Mohammad Khan wrote:
 And why was it expected to be 63 bit ? Was there an expectation that one
 bit will be used to distinguish a 63 bit address from 31 / 24 bit addresses ?

No, because there was no prior convention of using a doubleword
to contain a 31-bit address.

During the early discussions, many people expected ESAME to implement
63-bit addressing for reasons similar to why XA/370, ESA/370, and
ESA/390 implemented 31-bit and not 32-bit addressing.

I thought 31-bit was for compatibility with existing exploitation
of the sign bit; but there was no legacy convention of using
the sign bit of shorter addresses stored in a doubleword to
preserve compatibility with.

-- gil

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread W. Kevin Kelley
On Mon, 20 Oct 2008 15:00:48 -0500, Paul Gilmartin 
[EMAIL PROTECTED] wrote:

I thought 31-bit was for compatibility with existing exploitation
of the sign bit; but there was no legacy convention of using
the sign bit of shorter addresses stored in a doubleword to
preserve compatibility with.


Nope, it was the use of a X'80' in the high-order byte of a fullword to 
terminate a variable-length parameter list (of fullwords).

And, FWIW, the S360/67 did implement (as an option) 32-bit addressing... 
Really caused problems when some customers had to get off of TSS and try to 
stuff things in 31-bit.

W. Kevin Kelley  IBM POK Lab -- z/OS Core Technical Development

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread J R
 Nope, it was the use of a X'80' in the high-order byte of a fullword to  
 terminate a variable-length parameter list (of fullwords).
 
Isn't that the existing exploitation of the sign bit 
that Gil is alluding to?  
 
 Date: Mon, 20 Oct 2008 20:31:08 -0500
 From: [EMAIL PROTECTED]
 Subject: Re: Addressing Scheme with 64 vs 63 bits
 To: IBM-MAIN@BAMA.UA.EDU
 
 On Mon, 20 Oct 2008 15:00:48 -0500, Paul Gilmartin 
 [EMAIL PROTECTED] wrote:
 
 I thought 31-bit was for compatibility with existing exploitation
 of the sign bit; but there was no legacy convention of using
 the sign bit of shorter addresses stored in a doubleword to
 preserve compatibility with.
 
 
 Nope, it was the use of a X'80' in the high-order byte of a fullword to 
 terminate a variable-length parameter list (of fullwords).
 
 And, FWIW, the S360/67 did implement (as an option) 32-bit addressing... 
 Really caused problems when some customers had to get off of TSS and try to 
 stuff things in 31-bit.
 
 W. Kevin Kelley IBM POK Lab -- z/OS Core Technical Development
 
 
 
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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread Paul Gilmartin
On Mon, 20 Oct 2008 20:31:08 -0500, W. Kevin Kelley wrote:

On Mon, 20 Oct 2008 15:00:48 -0500, Paul Gilmartin
[EMAIL PROTECTED] wrote:

I thought 31-bit was for compatibility with existing exploitation
of the sign bit; ...

Nope, it was the use of a X'80' in the high-order byte of a fullword to
terminate a variable-length parameter list (of fullwords).

Nope?  Where do you perceive us to be in disagreement?

Of course, with the transition from 370 to XA, the bit could
no longer be set with MVI; OI was required.  This almost
certainly provoked an interminable thread on ASSEMBLER-LIST
concerning the performance impact.  I'd hardly be surprised,
though, if OI on XA ran faster than MVI on 370.

-- gil

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Re: Addressing Scheme with 64 vs 63 bits

2008-10-20 Thread Robert A. Rosenberg
At 22:00 -0500 on 10/20/2008, Paul Gilmartin wrote about Re: 
Addressing Scheme with 64 vs 63 bits:



On Mon, 20 Oct 2008 20:31:08 -0500, W. Kevin Kelley wrote:


On Mon, 20 Oct 2008 15:00:48 -0500, Paul Gilmartin
[EMAIL PROTECTED] wrote:


I thought 31-bit was for compatibility with existing exploitation
of the sign bit; ...


Nope, it was the use of a X'80' in the high-order byte of a fullword to
terminate a variable-length parameter list (of fullwords).


Nope?  Where do you perceive us to be in disagreement?

Of course, with the transition from 370 to XA, the bit could
no longer be set with MVI; OI was required.  This almost
certainly provoked an interminable thread on ASSEMBLER-LIST
concerning the performance impact.  I'd hardly be surprised,
though, if OI on XA ran faster than MVI on 370.

-- gil


There was also the secondary use of the high bit to signal AM24 vs 
AM31 in addresses used for branching to/from subroutines. This 
required replacing BALR with BASR and BR with BSM to do the AM Mode 
Switch.


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