[Intel-gfx] [PATCH v2 07/12] drm/i915: Read out display FIFO size on VLV/CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.
v2: Add display_mmio_offset to DSPARB
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++-
drivers/gpu/drm/i915/intel_pm.c | 55 +
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b35aaf3..3b48f4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4026,7 +4026,7 @@ enum skl_disp_power_wells {
#define DPINVGTT_STATUS_MASK 0xff
#define DPINVGTT_STATUS_MASK_CHV 0xfff
-#define DSPARB 0x70030
+#define DSPARB (dev_priv-info.display_mmio_offset + 0x70030)
#define DSPARB_CSTART_MASK (0x7f 7)
#define DSPARB_CSTART_SHIFT 7
#define DSPARB_BSTART_MASK (0x7f)
@@ -4034,6 +4034,9 @@ enum skl_disp_power_wells {
#define DSPARB_BEND_SHIFT9 /* on 855 */
#define DSPARB_AEND_SHIFT0
+#define DSPARB2(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv
*/
+#define DSPARB3(VLV_DISPLAY_BASE + 0x7006c) /* chv */
+
/* pnv/gen4/g4x/vlv/chv */
#define DSPFW1 (dev_priv-info.display_mmio_offset + 0x70034)
#define DSPFW_SR_SHIFT 23
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f8f6cee..27ce40c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -280,6 +280,61 @@ void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv, bool enable)
*/
static const int pessimal_latency_ns = 5000;
+#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
+ dsparb) (lo_shift)) 0xff) | dsparb2) (hi_shift)) 0x1)
8))
+
+static int vlv_get_fifo_size(struct drm_device *dev,
+ enum pipe pipe, int plane)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ int sprite0_start, sprite1_start, size;
+
+ switch (pipe) {
+ uint32_t dsparb, dsparb2, dsparb3;
+ case PIPE_A:
+ dsparb = I915_READ(DSPARB);
+ dsparb2 = I915_READ(DSPARB2);
+ sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
+ sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
+ break;
+ case PIPE_B:
+ dsparb = I915_READ(DSPARB);
+ dsparb2 = I915_READ(DSPARB2);
+ sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
+ sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
+ break;
+ case PIPE_C:
+ dsparb2 = I915_READ(DSPARB2);
+ dsparb3 = I915_READ(DSPARB3);
+ sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
+ sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
+ break;
+ default:
+ return 0;
+ }
+
+ switch (plane) {
+ case 0:
+ size = sprite0_start;
+ break;
+ case 1:
+ size = sprite1_start - sprite0_start;
+ break;
+ case 2:
+ size = 512 - 1 - sprite1_start;
+ break;
+ default:
+ return 0;
+ }
+
+ DRM_DEBUG_KMS(Pipe %c %s %c FIFO size: %d\n,
+ pipe_name(pipe), plane == 0 ? primary : sprite,
+ plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane -
1),
+ size);
+
+ return size;
+}
+
static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
{
struct drm_i915_private *dev_priv = dev-dev_private;
--
2.0.5
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[Intel-gfx] [PATCH 04/12] drm/i915: Hide VLV DDL precision handling
From: Ville Syrjälä ville.syrj...@linux.intel.com
Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++---
drivers/gpu/drm/i915/intel_pm.c | 74 +++--
2 files changed, 28 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 230320b..b35aaf3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4167,15 +4167,11 @@ enum skl_disp_power_wells {
/* drain latency register values*/
#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 *
(pipe))
-#define DDL_CURSOR_PRECISION_HIGH (131)
-#define DDL_CURSOR_PRECISION_LOW (031)
#define DDL_CURSOR_SHIFT 24
-#define DDL_SPRITE_PRECISION_HIGH(sprite) (1(15+8*(sprite)))
-#define DDL_SPRITE_PRECISION_LOW(sprite) (0(15+8*(sprite)))
#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
-#define DDL_PLANE_PRECISION_HIGH (17)
-#define DDL_PLANE_PRECISION_LOW(07)
#define DDL_PLANE_SHIFT0
+#define DDL_PRECISION_HIGH (17)
+#define DDL_PRECISION_LOW (07)
#define DRAIN_LATENCY_MASK 0x7f
/* FIFO watermark sizes etc */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d6c6c1b..c4c2317 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,35 +711,35 @@ static bool g4x_compute_srwm(struct drm_device *dev,
display, cursor);
}
-static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
- int pixel_size,
- int *prec_mult,
- int *drain_latency)
+static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
+int pixel_size)
{
struct drm_device *dev = crtc-dev;
- int entries;
+ int entries, prec_mult, drain_latency;
int clock = to_intel_crtc(crtc)-config-base.adjusted_mode.crtc_clock;
+ const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
if (WARN(clock == 0, Pixel clock is zero!\n))
- return false;
+ return 0;
if (WARN(pixel_size == 0, Pixel size is zero!\n))
- return false;
+ return 0;
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
- *prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
- *drain_latency = (64 * (*prec_mult) * 4) / entries;
+ prec_mult = high_precision;
+ drain_latency = 64 * prec_mult * 4 / entries;
- if (*drain_latency DRAIN_LATENCY_MASK) {
- *prec_mult /= 2;
- *drain_latency = (64 * (*prec_mult) * 4) / entries;
+ if (drain_latency DRAIN_LATENCY_MASK) {
+ prec_mult /= 2;
+ drain_latency = 64 * prec_mult * 4 / entries;
}
- if (*drain_latency DRAIN_LATENCY_MASK)
- *drain_latency = DRAIN_LATENCY_MASK;
+ if (drain_latency DRAIN_LATENCY_MASK)
+ drain_latency = DRAIN_LATENCY_MASK;
- return true;
+ return drain_latency | (prec_mult == high_precision ?
+ DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
}
/*
@@ -756,14 +756,12 @@ static void vlv_update_drain_latency(struct drm_crtc
*crtc)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pixel_size;
- int drain_latency;
enum pipe pipe = intel_crtc-pipe;
- int plane_prec, prec_mult, plane_dl;
- const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+ int plane_dl;
- plane_dl = I915_READ(VLV_DDL(pipe)) ~(DDL_PLANE_PRECISION_HIGH |
- DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
- (DRAIN_LATENCY_MASK DDL_CURSOR_SHIFT));
+ plane_dl = I915_READ(VLV_DDL(pipe))
+ ~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK)
DDL_CURSOR_SHIFT) |
+ ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK)
DDL_PLANE_SHIFT));
if (!intel_crtc_active(crtc)) {
I915_WRITE(VLV_DDL(pipe), plane_dl);
@@ -772,12 +770,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
/* Primary plane Drain Latency */
pixel_size = crtc-primary-fb-bits_per_pixel / 8; /* BPP */
- if (vlv_compute_drain_latency(crtc, pixel_size, prec_mult,
drain_latency)) {
- plane_prec = (prec_mult == high_precision) ?
- DDL_PLANE_PRECISION_HIGH :
- DDL_PLANE_PRECISION_LOW;
-
[Intel-gfx] [PATCH 03/12] drm/i915: Simplify VLV drain latency computation
From: Ville Syrjälä ville.syrj...@linux.intel.com
The current drain lantency computation relies on hardcoded limits to
determine when the to use the low vs. high precision multiplier.
Rewrite the code to use a more straightforward approach.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f0281a..d6c6c1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -727,12 +727,15 @@ static bool vlv_compute_drain_latency(struct drm_crtc
*crtc,
return false;
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
- if (IS_CHERRYVIEW(dev))
- *prec_mult = (entries 32) ? 16 : 8;
- else
- *prec_mult = (entries 128) ? 64 : 32;
+
+ *prec_mult = IS_CHERRYVIEW(dev) ? 16 : 64;
*drain_latency = (64 * (*prec_mult) * 4) / entries;
+ if (*drain_latency DRAIN_LATENCY_MASK) {
+ *prec_mult /= 2;
+ *drain_latency = (64 * (*prec_mult) * 4) / entries;
+ }
+
if (*drain_latency DRAIN_LATENCY_MASK)
*drain_latency = DRAIN_LATENCY_MASK;
--
2.0.5
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[Intel-gfx] [PATCH 12/12] drm/i915: Disable DDR DVFS on CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com
DDR DVFS introduces massive memory latencies which can't be handled by
the PND deadline stuff. Instead the watermarks will need to be
programmed to compensate for the latency and the deadlines will need to
be programmed to tight fixed values. That means DDR DVFS can only be
enabled if the display FIFOs are large enough, and that pretty much
means we have to manually repartition them to suit the needs of the
moment.
That's a lot of change, so in the meantime let's just disable DDR DVFS
to get the display(s) to be stable.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 34 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a20f58..744d162 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -630,6 +630,11 @@ enum skl_disp_power_wells {
#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+#define PUNIT_REG_DDR_SETUP2 0x139
+#define FORCE_DDR_FREQ_REQ_ACK (1 8)
+#define FORCE_DDR_LOW_FREQ (1 1)
+#define FORCE_DDR_HIGH_FREQ (1 0)
+
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1dd82ec..fc03e24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -235,6 +235,28 @@ static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop,
return NULL;
}
+static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
+{
+ u32 val;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
+ if (enable)
+ val = ~FORCE_DDR_HIGH_FREQ;
+ else
+ val |= FORCE_DDR_HIGH_FREQ;
+ val = ~FORCE_DDR_LOW_FREQ;
+ val |= FORCE_DDR_FREQ_REQ_ACK;
+ vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
+
+ if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2)
+ FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
+ DRM_ERROR(timed out waiting for Punit DDR DVFS request\n);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+}
+
static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
{
u32 val;
@@ -282,6 +304,7 @@ void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv, bool enable)
enable ? enabled : disabled);
}
+
/*
* Latency for FIFO fetches is dependent on several factors:
* - memory configuration (speed, channels)
@@ -992,6 +1015,17 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
wm.sr.plane, wm.sr.cursor);
+ /*
+* FIXME DDR DVFS introduces massive memory latencies which
+* are not known to system agent so any deadline specified
+* by the display may not be respected. To support DDR DVFS
+* the watermark code needs to be rewritten to essentially
+* bypass deadline mechanism and rely solely on the
+* watermarks. For now disable DDR DVFS.
+*/
+ if (IS_CHERRYVIEW(dev_priv))
+ chv_set_memory_dvfs(dev_priv, false);
+
if (!cxsr_enabled)
intel_set_memory_cxsr(dev_priv, false);
--
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[Intel-gfx] [PATCH v2 06/12] drm/i915: Pass plane to vlv_compute_drain_latency()
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that we have drm_planes for the cursor and primary we can move the
pixel_size handling into vlv_compute_drain_latency() and just pass the
appropriate plane to it.
v2: Check plane-state-fb instead of plane-fb
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org (v1)
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 42 -
1 file changed, 16 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5515d10..f8f6cee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -727,16 +727,26 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
}
static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
-int pixel_size)
+struct drm_plane *plane)
{
struct drm_device *dev = crtc-dev;
- int entries, prec_mult, drain_latency;
- int clock = to_intel_crtc(crtc)-config-base.adjusted_mode.crtc_clock;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int entries, prec_mult, drain_latency, pixel_size;
+ int clock = intel_crtc-config-base.adjusted_mode.crtc_clock;
const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
+ /*
+* FIXME the plane might have an fb
+* but be invisible (eg. due to clipping)
+*/
+ if (!intel_crtc-active || !plane-state-fb)
+ return 0;
+
if (WARN(clock == 0, Pixel clock is zero!\n))
return 0;
+ pixel_size = drm_format_plane_cpp(plane-state-fb-pixel_format, 0);
+
if (WARN(pixel_size == 0, Pixel size is zero!\n))
return 0;
@@ -770,31 +780,11 @@ static void vlv_update_drain_latency(struct drm_crtc
*crtc)
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pixel_size;
enum pipe pipe = intel_crtc-pipe;
struct vlv_wm_values wm = dev_priv-wm.vlv;
- wm.ddl[pipe].primary = 0;
- wm.ddl[pipe].cursor = 0;
-
- if (!intel_crtc_active(crtc)) {
- vlv_write_wm_values(intel_crtc, wm);
- return;
- }
-
- /* Primary plane Drain Latency */
- pixel_size = crtc-primary-fb-bits_per_pixel / 8; /* BPP */
- wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
-
- /* Cursor Drain Latency
-* BPP is always 4 for cursor
-*/
- pixel_size = 4;
-
- /* Program cursor DL only if it is enabled */
- if (intel_crtc-cursor_base)
- wm.ddl[pipe].cursor =
- vlv_compute_drain_latency(crtc, pixel_size);
+ wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc-primary);
+ wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc-cursor);
vlv_write_wm_values(intel_crtc, wm);
}
@@ -961,7 +951,7 @@ static void valleyview_update_sprite_wm(struct drm_plane
*plane,
if (enabled)
wm.ddl[pipe].sprite[sprite] =
- vlv_compute_drain_latency(crtc, pixel_size);
+ vlv_compute_drain_latency(crtc, plane);
else
wm.ddl[pipe].sprite[sprite] = 0;
--
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[Intel-gfx] [PATCH v3 11/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
v2: Put the thing into a separate function to avoid churn later
v3: Don't break VLV
Reviewed-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 18 ++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 145f0d4..5a20f58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -552,6 +552,9 @@
#define DSPFREQSTAT_MASK (0x3 DSPFREQSTAT_SHIFT)
#define DSPFREQGUAR_SHIFT14
#define DSPFREQGUAR_MASK (0x3 DSPFREQGUAR_SHIFT)
+#define DSP_MAXFIFO_PM5_STATUS (1 22) /* chv */
+#define DSP_AUTO_CDCLK_GATE_DISABLE (1 7) /* chv */
+#define DSP_MAXFIFO_PM5_ENABLE (1 6) /* chv */
#define _DP_SSC(val, pipe) ((val) (2 * (pipe)))
#define DP_SSC_MASK(pipe)_DP_SSC(0x3, (pipe))
#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 497847c..1dd82ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -235,6 +235,22 @@ static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop,
return NULL;
}
+static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
+{
+ u32 val;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+ if (enable)
+ val |= DSP_MAXFIFO_PM5_ENABLE;
+ else
+ val = ~DSP_MAXFIFO_PM5_ENABLE;
+ vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+}
+
void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
{
struct drm_device *dev = dev_priv-dev;
@@ -242,6 +258,8 @@ void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv, bool enable)
if (IS_VALLEYVIEW(dev)) {
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+ if (IS_CHERRYVIEW(dev))
+ chv_set_memory_pm5(dev_priv, enable);
} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
} else if (IS_PINEVIEW(dev)) {
--
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[Intel-gfx] [PATCH v2 09/12] drm/i915: Rewrite VLV/CHV watermark code
From: Ville Syrjälä ville.syrj...@linux.intel.com
Assuming the PND deadline mechanism works reasonably we should do
memory requests as early as possible so that PND has schedule the
requests more intelligently. Currently we're still calculating
the watermarks as if VLV/CHV are identical to g4x, which isn't
the case.
The current code also seems to calculate insufficient watermarks
and hence we're seeing some underruns, especially on high resolution
displays.
To fix it just rip out the current code and replace is with something
that tries to utilize PND as efficiently as possible.
We now calculate the WM watermark to trigger when the FIFO still has
256us worth of data. 256us is the maximum deadline value supoorted by
PND, so issuing memory requests earlier would mean we probably couldn't
utilize the full FIFO as PND would attempt to return the data at
least in at least 256us. We also clamp the watermark to at least 8
cachelines as that's the magic watermark that enabling trickle feed
would also impose. I'm assuming it matches some burst size.
In theory we could just enable trickle feed and ignore the WM values,
except trickle feed doesn't work with max fifo mode anyway, so we'd
still need to calculate the SR watermarks. It seems cleaner to just
disable trickle feed and calculate all watermarks the same way. Also
trickle feed wouldn't account for the 256us max deadline value, thoguh
that may be a moot point in non-max fifo mode sicne the FIFOs are fairly
small.
On VLV max fifo mode can be used with either primary or sprite planes.
So the code now also checks all the planes (apart from the cursor)
when calculating the SR plane watermark.
We don't have to worry about the WM1 watermarks since we're using the
PND deadline scheme which means the hardware ignores WM1 values.
v2: Use plane-state-fb instead of plane-fb
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 11 ++
drivers/gpu/drm/i915/i915_reg.h | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 330 +---
3 files changed, 188 insertions(+), 157 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5de69a0..b191b12 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1516,6 +1516,17 @@ struct ilk_wm_values {
struct vlv_wm_values {
struct {
+ uint16_t primary;
+ uint16_t sprite[2];
+ uint8_t cursor;
+ } pipe[3];
+
+ struct {
+ uint16_t plane;
+ uint8_t cursor;
+ } sr;
+
+ struct {
uint8_t cursor;
uint8_t sprite[2];
uint8_t primary;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8178610..9f98384 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4127,7 +4127,7 @@ enum skl_disp_power_wells {
/* vlv/chv high order bits */
#define DSPHOWM(VLV_DISPLAY_BASE + 0x70064)
#define DSPFW_SR_HI_SHIFT24
-#define DSPFW_SR_HI_MASK (124)
+#define DSPFW_SR_HI_MASK (324) /* 2 bits for chv, 1 for vlv */
#define DSPFW_SPRITEF_HI_SHIFT 23
#define DSPFW_SPRITEF_HI_MASK(123)
#define DSPFW_SPRITEE_HI_SHIFT 22
@@ -4148,7 +4148,7 @@ enum skl_disp_power_wells {
#define DSPFW_PLANEA_HI_MASK (10)
#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068)
#define DSPFW_SR_WM1_HI_SHIFT24
-#define DSPFW_SR_WM1_HI_MASK (124)
+#define DSPFW_SR_WM1_HI_MASK (324) /* 2 bits for chv, 1 for vlv */
#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
#define DSPFW_SPRITEF_WM1_HI_MASK(123)
#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bdb0f5d..497847c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -778,6 +778,55 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
(wm-ddl[pipe].sprite[0] DDL_SPRITE_SHIFT(0)) |
(wm-ddl[pipe].primary DDL_PLANE_SHIFT));
+ I915_WRITE(DSPFW1,
+ ((wm-sr.plane DSPFW_SR_SHIFT) DSPFW_SR_MASK) |
+ ((wm-pipe[PIPE_B].cursor DSPFW_CURSORB_SHIFT)
DSPFW_CURSORB_MASK) |
+ ((wm-pipe[PIPE_B].primary DSPFW_PLANEB_SHIFT)
DSPFW_PLANEB_MASK_VLV) |
+ ((wm-pipe[PIPE_A].primary DSPFW_PLANEA_SHIFT)
DSPFW_PLANEA_MASK_VLV));
+ I915_WRITE(DSPFW2,
+ ((wm-pipe[PIPE_A].sprite[1] DSPFW_SPRITEB_SHIFT)
DSPFW_SPRITEB_MASK_VLV) |
+ ((wm-pipe[PIPE_A].cursor DSPFW_CURSORA_SHIFT)
DSPFW_CURSORA_MASK) |
+ ((wm-pipe[PIPE_A].sprite[0] DSPFW_SPRITEA_SHIFT)
DSPFW_SPRITEA_MASK_VLV));
+ I915_WRITE(DSPFW3,
+ ((wm-sr.cursor
Re: [Intel-gfx] [PATCH 32/53] drm/i915: Update mi_set_context() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Updated mi_set_context() to take a request structure instead of a ring and
context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c |9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 475d1fd..9e66fac 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -472,10 +472,9 @@ i915_gem_context_get(struct drm_i915_file_private
*file_priv, u32 id)
}
static inline int
-mi_set_context(struct intel_engine_cs *ring,
- struct intel_context *new_context,
- u32 hw_flags)
+mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
+ struct intel_engine_cs *ring = req-ring;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
@@ -527,7 +526,7 @@ mi_set_context(struct intel_engine_cs *ring,
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
- intel_ring_emit(ring,
i915_gem_obj_ggtt_offset(new_context-legacy_hw_ctx.rcs_state) |
+ intel_ring_emit(ring,
i915_gem_obj_ggtt_offset(req-ctx-legacy_hw_ctx.rcs_state) |
flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
@@ -628,7 +627,7 @@ static int do_switch(struct drm_i915_gem_request *req)
if (!to-legacy_hw_ctx.initialized || i915_gem_context_is_default(to))
hw_flags |= MI_RESTORE_INHIBIT;
- ret = mi_set_context(req-ring, to, hw_flags);
+ ret = mi_set_context(req, hw_flags);
if (ret)
goto unpin_out;
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 33/53] drm/i915: Update a bunch of execbuffer heplers to take request structures
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Updated *_ring_invalidate_all_caches(), i915_reset_gen7_sol_offsets() and
i915_emit_box() to take request structures instead of ring or ringbuf/context
pairs.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 +++-
drivers/gpu/drm/i915/intel_lrc.c |9 -
drivers/gpu/drm/i915/intel_ringbuffer.c|3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.h|2 +-
4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index dc13751..a79c893 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -857,7 +857,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return intel_ring_invalidate_all_caches(req-ring);
+ return intel_ring_invalidate_all_caches(req);
}
static bool
@@ -1002,8 +1002,9 @@ i915_gem_execbuffer_retire_commands(struct
i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_device *dev,
- struct intel_engine_cs *ring)
+ struct drm_i915_gem_request *req)
{
+ struct intel_engine_cs *ring = req-ring;
struct drm_i915_private *dev_priv = dev-dev_private;
int ret, i;
@@ -1028,10 +1029,11 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
}
static int
-i915_emit_box(struct intel_engine_cs *ring,
+i915_emit_box(struct drm_i915_gem_request *req,
struct drm_clip_rect *box,
int DR1, int DR4)
{
+ struct intel_engine_cs *ring = req-ring;
int ret;
if (box-y2 = box-y1 || box-x2 = box-x1 ||
@@ -1247,7 +1249,7 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
}
if (args-flags I915_EXEC_GEN7_SOL_RESET) {
- ret = i915_reset_gen7_sol_offsets(params-dev, ring);
+ ret = i915_reset_gen7_sol_offsets(params-dev, params-request);
if (ret)
goto error;
}
@@ -1258,7 +1260,7 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
if (cliprects) {
for (i = 0; i args-num_cliprects; i++) {
- ret = i915_emit_box(ring, cliprects[i],
+ ret = i915_emit_box(params-request, cliprects[i],
args-DR1, args-DR4);
if (ret)
goto error;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 479365e..fab9269 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -558,10 +558,9 @@ static int execlists_context_queue(struct intel_engine_cs
*ring,
return 0;
}
-static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
- struct intel_context *ctx)
+static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = ringbuf-ring;
+ struct intel_engine_cs *ring = req-ring;
uint32_t flush_domains;
int ret;
@@ -569,7 +568,7 @@ static int logical_ring_invalidate_all_caches(struct
intel_ringbuffer *ringbuf,
if (ring-gpu_caches_dirty)
flush_domains = I915_GEM_GPU_DOMAINS;
- ret = ring-emit_flush(ringbuf, ctx,
+ ret = ring-emit_flush(req-ringbuf, req-ctx,
I915_GEM_GPU_DOMAINS, flush_domains);
if (ret)
return ret;
@@ -605,7 +604,7 @@ static int execlists_move_to_gpu(struct
drm_i915_gem_request *req,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return logical_ring_invalidate_all_caches(req-ringbuf, req-ctx);
+ return logical_ring_invalidate_all_caches(req);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 508d7d8..efa44db 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2864,8 +2864,9 @@ intel_ring_flush_all_caches(struct intel_engine_cs *ring)
}
int
-intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
+intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
{
+ struct intel_engine_cs *ring = req-ring;
uint32_t flush_domains;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 25d5ede..b817725 100644
---
[Intel-gfx] [PATCH v4 10/12] drm/i915: Program PFI credits for VLV
From: Vidya Srinivas vidya.srini...@intel.com
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid intermittent hangs while accessing memory even from
different Gfx units (not just display).
If cdclk/czclk =1, PFI credits could be set as any number. To get better
performance, larger PFI credit can be assigned to PND. Otherwise if
cdclk/czclk1, the default PFI credit of 8 should be set.
v2:
- Change log to lower log level instead of DRM_ERROR
- Change function name to valleyview_program_pfi_credits
- Move program PFI credits to modeset_init instead of intel_set_mode
- Change magic numbers to logical constants
[vsyrjala v3:
- only program in response to cdclk update
- program the credits also when cdclkczclk
- add CHV bits
v4:
- Change CHV cdclkczclk credits to 12 (Vijay)]
Signed-off-by: Vidya Srinivas vidya.srini...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8
drivers/gpu/drm/i915/intel_display.c | 38
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f98384..145f0d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2061,6 +2061,14 @@ enum skl_disp_power_wells {
#define CDCLK_FREQ_SHIFT 4
#define CDCLK_FREQ_MASK (0x1f CDCLK_FREQ_SHIFT)
#define CZCLK_FREQ_MASK 0xf
+
+#define GCI_CONTROL(VLV_DISPLAY_BASE + 0x650C)
+#define PFI_CREDIT_63(9 28) /* chv only */
+#define PFI_CREDIT_31(8 28) /* chv only */
+#define PFI_CREDIT(x)(((x) - 8) 28) /* 8-15 */
+#define PFI_CREDIT_RESEND(1 27)
+#define VGA_FAST_MODE_DISABLE(1 14)
+
#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
/*
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3fe9598..29ee72d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4987,6 +4987,42 @@ static void valleyview_modeset_global_pipes(struct
drm_device *dev,
*prepare_pipes |= (1 intel_crtc-pipe);
}
+static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
+{
+ unsigned int credits, default_credits;
+
+ if (IS_CHERRYVIEW(dev_priv))
+ default_credits = PFI_CREDIT(12);
+ else
+ default_credits = PFI_CREDIT(8);
+
+ if (DIV_ROUND_CLOSEST(dev_priv-vlv_cdclk_freq, 1000) =
dev_priv-rps.cz_freq) {
+ /* CHV suggested value is 31 or 63 */
+ if (IS_CHERRYVIEW(dev_priv))
+ credits = PFI_CREDIT_31;
+ else
+ credits = PFI_CREDIT(15);
+ } else {
+ credits = default_credits;
+ }
+
+ /*
+* WA - write default credits before re-programming
+* FIXME: should we also set the resend bit here?
+*/
+ I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+ default_credits);
+
+ I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
+ credits | PFI_CREDIT_RESEND);
+
+ /*
+* FIXME is this guaranteed to clear
+* immediately or should we poll for it?
+*/
+ WARN_ON(I915_READ(GCI_CONTROL) PFI_CREDIT_RESEND);
+}
+
static void valleyview_modeset_global_resources(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -5010,6 +5046,8 @@ static void valleyview_modeset_global_resources(struct
drm_device *dev)
else
valleyview_set_cdclk(dev, req_cdclk);
+ vlv_program_pfi_credits(dev_priv);
+
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
}
--
2.0.5
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[Intel-gfx] [PATCH v2 02/12] drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
From: Ville Syrjälä ville.syrj...@linux.intel.com
Kill the silly DRAIN_LATENCY_PRECISION_* defines and just use the raw
number instead.
v2: Move the sprite 32/16 - 16/8 preision multiplier
change to another patch (Jesse)
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8a0205..230320b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4166,10 +4166,6 @@ enum skl_disp_power_wells {
#define DSPFW_PLANEA_WM1_HI_MASK (10)
/* drain latency register values*/
-#define DRAIN_LATENCY_PRECISION_8 8
-#define DRAIN_LATENCY_PRECISION_16 16
-#define DRAIN_LATENCY_PRECISION_32 32
-#define DRAIN_LATENCY_PRECISION_64 64
#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 *
(pipe))
#define DDL_CURSOR_PRECISION_HIGH (131)
#define DDL_CURSOR_PRECISION_LOW (031)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index efbcfef..0f0281a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -728,11 +728,9 @@ static bool vlv_compute_drain_latency(struct drm_crtc
*crtc,
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
if (IS_CHERRYVIEW(dev))
- *prec_mult = (entries 32) ? DRAIN_LATENCY_PRECISION_16 :
- DRAIN_LATENCY_PRECISION_8;
+ *prec_mult = (entries 32) ? 16 : 8;
else
- *prec_mult = (entries 128) ? DRAIN_LATENCY_PRECISION_64 :
- DRAIN_LATENCY_PRECISION_32;
+ *prec_mult = (entries 128) ? 64 : 32;
*drain_latency = (64 * (*prec_mult) * 4) / entries;
if (*drain_latency DRAIN_LATENCY_MASK)
@@ -758,8 +756,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
int drain_latency;
enum pipe pipe = intel_crtc-pipe;
int plane_prec, prec_mult, plane_dl;
- const int high_precision = IS_CHERRYVIEW(dev) ?
- DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
+ const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
plane_dl = I915_READ(VLV_DDL(pipe)) ~(DDL_PLANE_PRECISION_HIGH |
DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
@@ -957,8 +954,7 @@ static void valleyview_update_sprite_wm(struct drm_plane
*plane,
int plane_prec;
int sprite_dl;
int prec_mult;
- const int high_precision = IS_CHERRYVIEW(dev) ?
- DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
+ const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
sprite_dl = I915_READ(VLV_DDL(pipe))
~(DDL_SPRITE_PRECISION_HIGH(sprite) |
(DRAIN_LATENCY_MASK DDL_SPRITE_SHIFT(sprite)));
--
2.0.5
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[Intel-gfx] [PATCH 05/12] drm/i915: Reorganize VLV DDL setup
From: Ville Syrjälä ville.syrj...@linux.intel.com
Introduce struct vlv_wm_values to house VLV watermark/drain latency
values. We start by using it when computing the drain latency values.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 9
drivers/gpu/drm/i915/intel_pm.c | 46 +++--
2 files changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26ffe8b..5de69a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1514,6 +1514,14 @@ struct ilk_wm_values {
enum intel_ddb_partitioning partitioning;
};
+struct vlv_wm_values {
+ struct {
+ uint8_t cursor;
+ uint8_t sprite[2];
+ uint8_t primary;
+ } ddl[3];
+};
+
struct skl_ddb_entry {
uint16_t start, end;/* in number of blocks, 'end' is exclusive */
};
@@ -1870,6 +1878,7 @@ struct drm_i915_private {
union {
struct ilk_wm_values hw;
struct skl_wm_values skl_hw;
+ struct vlv_wm_values vlv;
};
} wm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c4c2317..5515d10 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,6 +711,21 @@ static bool g4x_compute_srwm(struct drm_device *dev,
display, cursor);
}
+static void vlv_write_wm_values(struct intel_crtc *crtc,
+ const struct vlv_wm_values *wm)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc-base.dev);
+ enum pipe pipe = crtc-pipe;
+
+ I915_WRITE(VLV_DDL(pipe),
+ (wm-ddl[pipe].cursor DDL_CURSOR_SHIFT) |
+ (wm-ddl[pipe].sprite[1] DDL_SPRITE_SHIFT(1)) |
+ (wm-ddl[pipe].sprite[0] DDL_SPRITE_SHIFT(0)) |
+ (wm-ddl[pipe].primary DDL_PLANE_SHIFT));
+
+ dev_priv-wm.vlv = *wm;
+}
+
static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
int pixel_size)
{
@@ -757,20 +772,19 @@ static void vlv_update_drain_latency(struct drm_crtc
*crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pixel_size;
enum pipe pipe = intel_crtc-pipe;
- int plane_dl;
+ struct vlv_wm_values wm = dev_priv-wm.vlv;
- plane_dl = I915_READ(VLV_DDL(pipe))
- ~(((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK)
DDL_CURSOR_SHIFT) |
- ((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK)
DDL_PLANE_SHIFT));
+ wm.ddl[pipe].primary = 0;
+ wm.ddl[pipe].cursor = 0;
if (!intel_crtc_active(crtc)) {
- I915_WRITE(VLV_DDL(pipe), plane_dl);
+ vlv_write_wm_values(intel_crtc, wm);
return;
}
/* Primary plane Drain Latency */
pixel_size = crtc-primary-fb-bits_per_pixel / 8; /* BPP */
- plane_dl = vlv_compute_drain_latency(crtc, pixel_size)
DDL_PLANE_SHIFT;
+ wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, pixel_size);
/* Cursor Drain Latency
* BPP is always 4 for cursor
@@ -779,9 +793,10 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
/* Program cursor DL only if it is enabled */
if (intel_crtc-cursor_base)
- plane_dl |= vlv_compute_drain_latency(crtc, pixel_size)
DDL_CURSOR_SHIFT;
+ wm.ddl[pipe].cursor =
+ vlv_compute_drain_latency(crtc, pixel_size);
- I915_WRITE(VLV_DDL(pipe), plane_dl);
+ vlv_write_wm_values(intel_crtc, wm);
}
#define single_plane_enabled(mask) is_power_of_2(mask)
@@ -939,17 +954,18 @@ static void valleyview_update_sprite_wm(struct drm_plane
*plane,
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
- int pipe = to_intel_plane(plane)-pipe;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum pipe pipe = intel_crtc-pipe;
int sprite = to_intel_plane(plane)-plane;
- int sprite_dl;
-
- sprite_dl = I915_READ(VLV_DDL(pipe))
- ~((DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK)
DDL_SPRITE_SHIFT(sprite));
+ struct vlv_wm_values wm = dev_priv-wm.vlv;
if (enabled)
- sprite_dl |= vlv_compute_drain_latency(crtc, pixel_size)
DDL_SPRITE_SHIFT(sprite);
+ wm.ddl[pipe].sprite[sprite] =
+ vlv_compute_drain_latency(crtc, pixel_size);
+ else
+ wm.ddl[pipe].sprite[sprite] = 0;
- I915_WRITE(VLV_DDL(pipe), sprite_dl);
+ vlv_write_wm_values(intel_crtc, wm);
}
static void g4x_update_wm(struct drm_crtc *crtc)
--
2.0.5
Re: [Intel-gfx] [PATCH 28/53] drm/i915: Update queue_flip() to do explicit request management
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Updated the display page flip code to do explicit request creation and
submission rather than relying on the OLR and just hoping that the request
actually gets submitted at some random point.
The sequence is now to create a request, queue the work to the ring, assign the
known request to the flip queue work item then actually submit the work and post
the request.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/intel_display.c| 43 ---
drivers/gpu/drm/i915/intel_ringbuffer.c |2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h |1 -
4 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9cc343..34fd338 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -560,7 +560,7 @@ struct drm_i915_display_funcs {
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
- struct intel_engine_cs *ring,
+ struct drm_i915_gem_request *req,
uint32_t flags);
void (*update_primary_plane)(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..c32bc0c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9251,9 +9251,10 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
-struct intel_engine_cs *ring,
+struct drm_i915_gem_request *req,
uint32_t flags)
{
+ struct intel_engine_cs *ring = req-ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -9278,7 +9279,6 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, 0); /* aux display base address, unused */
intel_mark_page_flip_active(intel_crtc);
- __intel_ring_advance(ring);
return 0;
}
@@ -9286,9 +9286,10 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
-struct intel_engine_cs *ring,
+struct drm_i915_gem_request *req,
uint32_t flags)
{
+ struct intel_engine_cs *ring = req-ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -9310,7 +9311,6 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, MI_NOOP);
intel_mark_page_flip_active(intel_crtc);
- __intel_ring_advance(ring);
return 0;
}
@@ -9318,9 +9318,10 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
-struct intel_engine_cs *ring,
+struct drm_i915_gem_request *req,
uint32_t flags)
{
+ struct intel_engine_cs *ring = req-ring;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -9349,7 +9350,6 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, pf | pipesrc);
intel_mark_page_flip_active(intel_crtc);
- __intel_ring_advance(ring);
return 0;
}
@@ -9357,9 +9357,10 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
-struct intel_engine_cs *ring,
+struct drm_i915_gem_request *req,
uint32_t flags)
{
+ struct intel_engine_cs *ring = req-ring;
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -9385,7 +9386,6 @@ static int
Re: [Intel-gfx] [PATCH 31/53] drm/i915: Update l3_remap to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Converted i915_gem_l3_remap() to take a request structure instead of a ring.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_gem.c |5 +++--
drivers/gpu/drm/i915/i915_gem_context.c |2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9fef4c..3955bef 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2825,7 +2825,7 @@ int __must_check i915_gem_object_finish_gpu(struct
drm_i915_gem_object *obj);
int __must_check i915_gem_init(struct drm_device *dev);
int i915_gem_init_rings(struct drm_device *dev);
int __must_check i915_gem_init_hw(struct drm_device *dev);
-int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
+int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
void i915_gem_init_swizzling(struct drm_device *dev);
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
int __must_check i915_gpu_idle(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0ae9be2..043933b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4644,8 +4644,9 @@ err:
return ret;
}
-int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
+int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
{
+ struct intel_engine_cs *ring = req-ring;
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
@@ -4864,7 +4865,7 @@ i915_gem_init_hw(struct drm_device *dev)
if (ring-id == RCS) {
for (i = 0; i NUM_L3_SLICES(dev); i++)
- i915_gem_l3_remap(ring, i);
+ i915_gem_l3_remap(req, i);
}
ret = i915_ppgtt_init_ring(req);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index e4d75be..475d1fd 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -636,7 +636,7 @@ static int do_switch(struct drm_i915_gem_request *req)
if (!(to-remap_slice (1i)))
continue;
- ret = i915_gem_l3_remap(req-ring, i);
+ ret = i915_gem_l3_remap(req, i);
/* If it failed, try again next round */
if (ret)
DRM_DEBUG_DRIVER(L3 remapping failed\n);
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 30/53] drm/i915: Update [vma|object]_move_to_active() to take request structures
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use request structures, it is
possible to update the lower level move_to_active() functions to be request
based as well.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_gem.c | 17 -
drivers/gpu/drm/i915/i915_gem_context.c |2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c |2 +-
drivers/gpu/drm/i915/intel_lrc.c |2 +-
6 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9206328..e9fef4c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2747,7 +2747,7 @@ int __must_check i915_mutex_lock_interruptible(struct
drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *to_req);
void i915_vma_move_to_active(struct i915_vma *vma,
-struct intel_engine_cs *ring);
+struct drm_i915_gem_request *req);
int i915_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 24fb7b9..0ae9be2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2265,17 +2265,16 @@ i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
static void
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
- struct intel_engine_cs *ring)
+ struct drm_i915_gem_request *req)
{
- struct drm_i915_gem_request *req;
- struct intel_engine_cs *old_ring;
+ struct intel_engine_cs *new_ring, *old_ring;
- BUG_ON(ring == NULL);
+ BUG_ON(req == NULL);
- req = intel_ring_get_request(ring);
+ new_ring = i915_gem_request_get_ring(req);
old_ring = i915_gem_request_get_ring(obj-last_read_req);
- if (old_ring != ring obj-last_write_req) {
+ if (old_ring != new_ring obj-last_write_req) {
/* Keep the request relative to the current ring */
i915_gem_request_assign(obj-last_write_req, req);
}
@@ -2286,16 +2285,16 @@ i915_gem_object_move_to_active(struct
drm_i915_gem_object *obj,
obj-active = 1;
}
- list_move_tail(obj-ring_list, ring-active_list);
+ list_move_tail(obj-ring_list, new_ring-active_list);
i915_gem_request_assign(obj-last_read_req, req);
}
void i915_vma_move_to_active(struct i915_vma *vma,
-struct intel_engine_cs *ring)
+struct drm_i915_gem_request *req)
{
list_move_tail(vma-mm_list, vma-vm-active_list);
- return i915_gem_object_move_to_active(vma-obj, ring);
+ return i915_gem_object_move_to_active(vma-obj, req);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 938cd26..e4d75be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -652,7 +652,7 @@ static int do_switch(struct drm_i915_gem_request *req)
*/
if (from != NULL) {
from-legacy_hw_ctx.rcs_state-base.read_domains =
I915_GEM_DOMAIN_INSTRUCTION;
-
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from-legacy_hw_ctx.rcs_state),
req-ring);
+
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from-legacy_hw_ctx.rcs_state),
req);
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
* whole damn pipeline, we don't need to explicitly mark the
* object dirty. The only exception is that the context must be
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 15e33a9..dc13751 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -966,7 +966,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
obj-base.pending_read_domains |=
obj-base.read_domains;
obj-base.read_domains = obj-base.pending_read_domains;
- i915_vma_move_to_active(vma, ring);
+ i915_vma_move_to_active(vma, req);
if (obj-base.write_domain) {
obj-dirty = 1;
i915_gem_request_assign(obj-last_write_req, req);
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index
[Intel-gfx] [PATCH v2 01/12] drm/i915: Reduce CHV DDL multiplier to 16/8
From: Ville Syrjälä ville.syrj...@linux.intel.com
Apparently we must yet halve the DDL drain latency from what we're
using currently. This little nugget is not in any spec, but came
down through the grapevine.
This makes the displays a bit more stable. Not quite fully stable but at
least they don't fall over immediately on driver load.
v2: Update high_precision in valleyview_update_sprite_wm() too (Jesse)
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ee1964..d8a0205 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4166,6 +4166,7 @@ enum skl_disp_power_wells {
#define DSPFW_PLANEA_WM1_HI_MASK (10)
/* drain latency register values*/
+#define DRAIN_LATENCY_PRECISION_8 8
#define DRAIN_LATENCY_PRECISION_16 16
#define DRAIN_LATENCY_PRECISION_32 32
#define DRAIN_LATENCY_PRECISION_64 64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c64810..efbcfef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -728,8 +728,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
if (IS_CHERRYVIEW(dev))
- *prec_mult = (entries 128) ? DRAIN_LATENCY_PRECISION_32 :
- DRAIN_LATENCY_PRECISION_16;
+ *prec_mult = (entries 32) ? DRAIN_LATENCY_PRECISION_16 :
+ DRAIN_LATENCY_PRECISION_8;
else
*prec_mult = (entries 128) ? DRAIN_LATENCY_PRECISION_64 :
DRAIN_LATENCY_PRECISION_32;
@@ -759,7 +759,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
enum pipe pipe = intel_crtc-pipe;
int plane_prec, prec_mult, plane_dl;
const int high_precision = IS_CHERRYVIEW(dev) ?
- DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
+ DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
plane_dl = I915_READ(VLV_DDL(pipe)) ~(DDL_PLANE_PRECISION_HIGH |
DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
@@ -958,7 +958,7 @@ static void valleyview_update_sprite_wm(struct drm_plane
*plane,
int sprite_dl;
int prec_mult;
const int high_precision = IS_CHERRYVIEW(dev) ?
- DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
+ DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64;
sprite_dl = I915_READ(VLV_DDL(pipe))
~(DDL_SPRITE_PRECISION_HIGH(sprite) |
(DRAIN_LATENCY_MASK DDL_SPRITE_SHIFT(sprite)));
--
2.0.5
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[Intel-gfx] [PATCH v2 00/12] drm/i915: Redo VLV/CHV watermark code (v2)
From: Ville Syrjälä ville.syrj...@linux.intel.com Here's an updated version of the series to redo the VLV/CHV watermark code. The most important thing is that this makes the display stable on BSW with the fancy new memory PM features enabled by the firmware. Changes since v1: * Drop the two plane maxfifo mode patch (Vijay) * Move one the misplaced hunk to the right patch (Jesse) * Use the right amount of PFI credits for the cdclkczclk case (Vijay) * Drop the extra drain latency multipler frobbing as it no longer seems to be necessary to get a stable picture with multiple 4k displays. Not really sure if this was due to a BIOS update or what. * Use plane-state-fb instead of plane-fb in the wm/ddl calculations. * Don't break VLV maxfifo enable/disable. Noticed this one myself while going through the patches I'm still missing a review on drm/i915: Rewrite VLV/CHV watermark code and drm/i915: Disable DDR DVFS on CHV The rest have r-bs now. I kept Jesses r-b on drm/i915: Pass plane to vlv_compute_drain_latency() even though v2 is a slightly different that v1 due to the plane-state changes. Vidya Srinivas (1): drm/i915: Program PFI credits for VLV Ville Syrjälä (11): drm/i915: Reduce CHV DDL multiplier to 16/8 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines drm/i915: Simplify VLV drain latency computation drm/i915: Hide VLV DDL precision handling drm/i915: Reorganize VLV DDL setup drm/i915: Pass plane to vlv_compute_drain_latency() drm/i915: Read out display FIFO size on VLV/CHV drm/i915: Make sure PND deadline mode is enabled on VLV/CHV drm/i915: Rewrite VLV/CHV watermark code drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV drm/i915: Disable DDR DVFS on CHV drivers/gpu/drm/i915/i915_drv.h | 20 ++ drivers/gpu/drm/i915/i915_reg.h | 39 ++- drivers/gpu/drm/i915/intel_display.c | 38 +++ drivers/gpu/drm/i915/intel_pm.c | 577 +-- 4 files changed, 432 insertions(+), 242 deletions(-) -- 2.0.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
From: Ville Syrjälä ville.syrj...@linux.intel.com
Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.
The hardware has two modes of operation wrt. watermarks:
1) PND deadline mode:
- memory request deadline is calculated from actual FIFO level * DDL
- WM1 watermark values are unused (AFAIK)
- WM watermark level defines when to start fetching data from memory
(assuming trickle feed is not used)
2) backup mode
- deadline is based on FIFO status, DDL is unused
- FIFO split into three regions with WM and WM1 watermarks, each
part specifying a different FIFO status
We want to use the PND deadline mode, so let's make sure the chicken
bit is in the correct position on init.
Also take the opportunity to refactor the shared code between VLV and
CHV to a shared function.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 19 +--
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b48f4b..8178610 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4177,6 +4177,9 @@ enum skl_disp_power_wells {
#define DDL_PRECISION_LOW (07)
#define DRAIN_LATENCY_MASK 0x7f
+#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400)
+#define CBR_PND_DEADLINE_DISABLE (131)
+
/* FIFO watermark sizes etc */
#define G4X_FIFO_LINE_SIZE 64
#define I915_FIFO_LINE_SIZE64
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27ce40c..bdb0f5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
gen6_check_mch_setup(dev);
}
+static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+
+ /*
+* Disable trickle feed and enable pnd deadline calculation
+*/
+ I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+ I915_WRITE(CBR1_VLV, 0);
+}
+
static void valleyview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+ vlv_init_display_clock_gating(dev_priv);
/* WaDisableEarlyCull:vlv */
I915_WRITE(_3D_CHICKEN3,
@@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct
drm_device *dev)
I915_WRITE(GEN7_UCGCTL4,
I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
- I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
-
/*
* BSpec says this must be set, even though
* WaDisable4x2SubspanOptimization isn't listed for VLV.
@@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct
drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
-
- I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+ vlv_init_display_clock_gating(dev_priv);
/* WaVSRefCountFullforceMissDisable:chv */
/* WaDSRefCountFullforceMissDisable:chv */
--
2.0.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Preventing zero GPU virtual address allocation
On Thu, Mar 05, 2015 at 04:27:59PM +0100, Daniel Vetter wrote: I recommended exposing the PIN_BIAS since that will work without full ppgtt too. And yeah for full ppgtt we could just use svm where userspace controls the address, but since that's still a bit out we might need a quick interim solution? Letting userspace control the address of bo used in a batch is about 2 patches each of ~100 lines. And it could be used will full-ppgtt before svm if mesa wants to take complete control of its layout. I think it is one of those useful tools that is likely to find uses far beyond the initial justification. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request
On 05/03/2015 15:46, John Harrison wrote:
On 05/03/2015 15:27, Tomas Elf wrote:
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The alloc_request() function does not actually return the newly
allocated
request. Instead, it must be pulled from
ring-outstanding_lazy_request. This
patch fixes this so that code can create a request and start using it
knowing
exactly which request it actually owns.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|3 ++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c |3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 13 +
drivers/gpu/drm/i915/intel_lrc.h |3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c| 14 ++
drivers/gpu/drm/i915/intel_ringbuffer.h|3 ++-
6 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 87a4a2e..90223f208 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1909,7 +1909,8 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or
execlists) away */
struct {
int (*alloc_request)(struct intel_engine_cs *ring,
- struct intel_context *ctx);
+ struct intel_context *ctx,
+ struct drm_i915_gem_request **req_out);
int (*do_execbuf)(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 61471e9..37dcc6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1353,6 +1353,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
void *data,
struct i915_address_space *vm;
struct i915_execbuffer_params params_master; /* XXX: will be
removed later */
struct i915_execbuffer_params *params = params_master;
+struct drm_i915_gem_request *request;
Please initialize request to NULL. If you accidentally dereference it
before it is allocated (seeing as the allocation is several pages down
from here) you get a null pointer exception, which is a clear
indication that you did something stupid. Otherwise it's not clear
what will happen (sure, page fault, but null pointer exception is a
better failure indication).
That should generate a 'use before assignment' compiler warning.
That assumes that the developer in question isn't too busy hacking to
check for warnings (in all honesty that developer probably would've been
me ;)). Sure, you should always check for warnings but if we can save
this developer some time by giving them a clear run-time indication
aside from the compile-time warning then that would not be a bad thing.
I've been there myself a few times and I know times in the past where
this would've saved me the time it takes to rebuild and redeploy the
kernel once.
Thanks,
Tomas
Thanks,
Tomas
const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
u32 dispatch_flags;
int ret;
@@ -1531,7 +1532,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
void *data,
params-batch_obj_vm_offset =
i915_gem_obj_offset(batch_obj, vm);
/* Allocate a request for this batch buffer nice and early. */
-ret = dev_priv-gt.alloc_request(ring, ctx);
+ret = dev_priv-gt.alloc_request(ring, ctx, request);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index 8628abf..c3c783f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -857,13 +857,17 @@ void intel_lr_context_unpin(struct
intel_engine_cs *ring,
}
int intel_logical_ring_alloc_request(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+ struct intel_context *ctx,
+ struct drm_i915_gem_request **req_out)
{
struct drm_i915_gem_request *request;
struct drm_i915_private *dev_private = ring-dev-dev_private;
int ret;
-if (ring-outstanding_lazy_request)
+if (!req_out)
+return -EINVAL;
+
+if ((*req_out = ring-outstanding_lazy_request) != NULL)
return 0;
request = kzalloc(sizeof(*request), GFP_KERNEL);
@@ -898,7 +902,7 @@ int intel_logical_ring_alloc_request(struct
intel_engine_cs *ring,
i915_gem_context_reference(request-ctx);
request-ringbuf = ctx-engine[ring-id].ringbuf;
-ring-outstanding_lazy_request = request;
+*req_out = ring-outstanding_lazy_request = request;
return 0;
}
@@ -1051,6 +1055,7 @@ static int logical_ring_prepare(struct
intel_ringbuffer *ringbuf,
int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
Re: [Intel-gfx] [PATCH 29/53] drm/i915: Update add_request() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Now that all callers of i915_add_request() have a request pointer to hand, it is
possible to update the add request function to take a request pointer rather
than pulling it out of the OLR.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 10 +-
drivers/gpu/drm/i915/i915_gem.c| 24
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_lrc.c |2 +-
drivers/gpu/drm/i915/intel_overlay.c |4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c|3 ++-
7 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34fd338..9206328 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2830,14 +2830,14 @@ void i915_gem_init_swizzling(struct drm_device *dev);
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
int __must_check i915_gpu_idle(struct drm_device *dev);
int __must_check i915_gem_suspend(struct drm_device *dev);
-int __i915_add_request(struct intel_engine_cs *ring,
+int __i915_add_request(struct drm_i915_gem_request *req,
struct drm_file *file,
struct drm_i915_gem_object *batch_obj,
bool flush_caches);
-#define i915_add_request(ring) \
- __i915_add_request(ring, NULL, NULL, true)
-#define i915_add_request_no_flush(ring) \
- __i915_add_request(ring, NULL, NULL, false)
+#define i915_add_request(req) \
+ __i915_add_request(req, NULL, NULL, true)
+#define i915_add_request_no_flush(req) \
+ __i915_add_request(req, NULL, NULL, false)
int __i915_wait_request(struct drm_i915_gem_request *req,
unsigned reset_counter,
bool interruptible,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0c7e1bd..24fb7b9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1162,7 +1162,7 @@ i915_gem_check_olr(struct drm_i915_gem_request *req)
ret = 0;
if (req == req-ring-outstanding_lazy_request)
- ret = i915_add_request(req-ring);
+ ret = i915_add_request(req);
return ret;
}
@@ -2407,25 +2407,25 @@ i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
return 0;
}
-int __i915_add_request(struct intel_engine_cs *ring,
+int __i915_add_request(struct drm_i915_gem_request *request,
struct drm_file *file,
struct drm_i915_gem_object *obj,
bool flush_caches)
{
- struct drm_i915_private *dev_priv = ring-dev-dev_private;
- struct drm_i915_gem_request *request;
+ struct intel_engine_cs *ring;
+ struct drm_i915_private *dev_priv;
struct intel_ringbuffer *ringbuf;
u32 request_start;
int ret;
- request = ring-outstanding_lazy_request;
if (WARN_ON(request == NULL))
return -ENOMEM;
- if (i915.enable_execlists) {
- ringbuf = request-ctx-engine[ring-id].ringbuf;
- } else
- ringbuf = ring-buffer;
+ ring = request-ring;
+ dev_priv = ring-dev-dev_private;
+ ringbuf = request-ringbuf;
+
+ WARN_ON(request != ring-outstanding_lazy_request);
request_start = intel_ring_get_tail(ringbuf);
/*
@@ -3118,7 +3118,7 @@ int i915_gpu_idle(struct drm_device *dev)
return ret;
}
- ret = i915_add_request_no_flush(req-ring);
+ ret = i915_add_request_no_flush(req);
if (ret) {
i915_gem_request_unreference(req);
return ret;
@@ -3966,7 +3966,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (ret)
return ret;
- ret = i915_add_request_no_flush(req-ring);
+ ret = i915_add_request_no_flush(req);
if (ret)
return ret;
}
@@ -4884,7 +4884,7 @@ i915_gem_init_hw(struct drm_device *dev)
return ret;
}
- ret = i915_add_request_no_flush(ring);
+ ret = i915_add_request_no_flush(req);
if (ret) {
DRM_ERROR(Add request ring #%d failed: %d\n, i, ret);
i915_gem_request_unreference(req);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1e2fc80..15e33a9 100644
---
[Intel-gfx] [PATCH i-g-t] igt.cocci: Replace igt_assert() with igt_assert_CMP() where possible
The integer comparison macros give us better error output by including
the actual values that failed the comparison.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
lib/igt.cocci | 32
tests/drv_hangman.c | 26 +-
tests/drv_suspend.c | 2 +-
tests/eviction_common.c | 10 ++--
tests/gem_close_race.c| 2 +-
tests/gem_cs_prefetch.c | 2 +-
tests/gem_cs_tlb.c| 3 +-
tests/gem_ctx_basic.c | 4 +-
tests/gem_evict_alignment.c | 2 +-
tests/gem_exec_bad_domains.c | 2 +-
tests/gem_exec_blt.c | 4 +-
tests/gem_exec_faulting_reloc.c | 2 +-
tests/gem_exec_nop.c | 2 +-
tests/gem_fence_thrash.c | 4 +-
tests/gem_flink.c | 20
tests/gem_flink_race.c| 8 +--
tests/gem_gtt_hog.c | 2 +-
tests/gem_linear_blits.c | 2 +-
tests/gem_persistent_relocs.c | 2 +-
tests/gem_reloc_vs_gpu.c | 2 +-
tests/gem_reset_stats.c | 100 +++---
tests/gem_ringfill.c | 2 +-
tests/gem_seqno_wrap.c| 18 +++
tests/gem_set_tiling_vs_blt.c | 6 +--
tests/gem_storedw_batches_loop.c | 2 +-
tests/gem_stress.c| 4 +-
tests/gem_threaded_access_tiled.c | 2 +-
tests/gem_tiled_fence_blits.c | 2 +-
tests/gem_userptr_blits.c | 67 -
tests/gem_workarounds.c | 4 +-
tests/gen3_mixed_blits.c | 4 +-
tests/gen3_render_linear_blits.c | 2 +-
tests/gen3_render_mixed_blits.c | 2 +-
tests/gen3_render_tiledx_blits.c | 2 +-
tests/gen3_render_tiledy_blits.c | 2 +-
tests/gen7_forcewake_mt.c | 4 +-
tests/kms_cursor_crc.c| 6 +--
tests/kms_flip.c | 8 +--
tests/kms_flip_event_leak.c | 10 ++--
tests/kms_flip_tiling.c | 2 +-
tests/kms_mmio_vs_cs_flip.c | 20
tests/kms_psr_sink_crc.c | 20
tests/kms_render.c| 4 +-
tests/kms_setmode.c | 4 +-
tests/kms_universal_plane.c | 6 +--
tests/pm_lpsp.c | 4 +-
tests/pm_rc6_residency.c | 6 +--
tests/pm_rpm.c| 56 ++---
tests/pm_rps.c| 4 +-
tests/prime_nv_api.c | 8 +--
tests/prime_nv_pcopy.c| 8 +--
tests/prime_self_import.c | 12 ++---
tests/testdisplay.c | 6 +--
53 files changed, 288 insertions(+), 252 deletions(-)
diff --git a/lib/igt.cocci b/lib/igt.cocci
index 41a8beb..7dc398d 100644
--- a/lib/igt.cocci
+++ b/lib/igt.cocci
@@ -141,3 +141,35 @@ a = drm_open_any();
- return ...;
- }
)
+
+// Use comparison macros instead of raw igt_assert when possible
+@@
+typedef uint32_t;
+uint32_t E1, E2;
+int E3, E4;
+@@
+(
+- igt_assert(E1 == E2);
++ igt_assert_eq_u32(E1, E2);
+|
+- igt_assert(E1 != E2);
++ igt_assert_neq_u32(E1, E2);
+|
+- igt_assert(E1 = E2);
++ igt_assert_lte_u32(E1, E2);
+|
+- igt_assert(E1 E2);
++ igt_assert_lt_u32(E1, E2);
+|
+- igt_assert(E3 == E4);
++ igt_assert_eq(E3, E4);
+|
+- igt_assert(E3 != E4);
++ igt_assert_neq(E3, E4);
+|
+- igt_assert(E3 = E4);
++ igt_assert_lte(E3, E4);
+|
+- igt_assert(E3 E4);
++ igt_assert_lt(E3, E4);
+)
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index a882822..d93bef3 100644
--- a/tests/drv_hangman.c
+++ b/tests/drv_hangman.c
@@ -79,14 +79,15 @@ static void test_sysfs_error_exists(void)
{
char tmp[1024];
- igt_assert(read_sysfs(tmp, sizeof(tmp), error) 0);
+ igt_assert_lt(0, read_sysfs(tmp, sizeof(tmp), error));
}
static void test_debugfs_error_state_exists(void)
{
int fd;
- igt_assert((fd = igt_debugfs_open(i915_error_state, O_RDONLY)) = 0);
+ igt_assert_lte(0,
+ (fd = igt_debugfs_open(i915_error_state, O_RDONLY)));
close (fd);
}
@@ -95,7 +96,7 @@ static void test_debugfs_ring_stop_exists(void)
{
int fd;
- igt_assert((fd = igt_debugfs_open(i915_ring_stop, O_RDONLY)) = 0);
+ igt_assert_lte(0, (fd = igt_debugfs_open(i915_ring_stop, O_RDONLY)));
close(fd);
}
@@ -105,10 +106,10 @@ static void read_dfs(const char *fname, char *d, int
maxlen)
int fd;
int l;
- igt_assert((fd = igt_debugfs_open(fname, O_RDONLY)) = 0);
+ igt_assert_lte(0, (fd = igt_debugfs_open(fname, O_RDONLY)));
- igt_assert((l = read(fd, d, maxlen-1)) 0);
- igt_assert(l maxlen);
+ igt_assert_lt(0, (l = read(fd, d, maxlen - 1)));
+ igt_assert_lt(l, maxlen);
d[l] = 0;
close(fd);
@@ -210,7 +211,8 @@ static void clear_error_state(void)
int fd;
const char *b = 1;
- igt_assert((fd = igt_debugfs_open(i915_error_state, O_WRONLY)) = 0);
+
[Intel-gfx] [PATCH 2/2] drm/i915: Don't assume primary cursor are always on for wm calculation (v2)
Current ILK-style watermark code assumes the primary plane and cursor
plane are always enabled. This assumption, along with the combination
of two independent commits that got merged at the same time, results in
a NULL dereference. The offending commits are:
commit fd2d61341bf39d1054256c07d6eddd624ebc4241
Author: Matt Roper matthew.d.ro...@intel.com
Date: Fri Feb 27 10:12:01 2015 -0800
drm/i915: Use plane-state-fb in watermark code (v2)
and
commit 0fda65680e92545caea5be7805a7f0a617fb6c20
Author: Tvrtko Ursulin tvrtko.ursu...@intel.com
Date: Fri Feb 27 15:12:35 2015 +
drm/i915/skl: Update watermarks for Y tiling
The first commit causes us to use the FB from plane-state-fb rather
than the legacy plane-fb, which is updated a bit later in the process.
The second commit includes a change that now triggers watermark
reprogramming on primary plane enable/disable where we didn't have one
before (which wasn't really correct, but we had been getting lucky
because we always calculated as if the primary plane was on).
Together, these two commits cause the watermark calculation to
(properly) see plane-state-fb = NULL when we're in the process of
disabling the primary plane. However the existing watermark code
assumes there's always a primary fb and tries to dereference it to find
out pixel format / bpp information.
The fix is to make ILK-style watermark calculation actually check the
true status of primary cursor planes and adjust our watermark logic
accordingly.
v2: Update unchecked uses of state-fb for other platforms (pnv, skl,
etc.). Note that this is just a temporary fix. Ultimately the
useful information is going to be computed at check time and stored
right in the state structures so that we don't have to figure this
all out while we're supposed to be programming the watermarks.
(caught by Tvrtko)
Cc: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reported-by: Michael Leuchtenburg mich...@slashhome.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89388
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 116 +---
1 file changed, 85 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2e8414..09e210c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -553,12 +553,17 @@ static void pineview_update_wm(struct drm_crtc
*unused_crtc)
crtc = single_enabled_crtc(dev);
if (crtc) {
const struct drm_display_mode *adjusted_mode;
- int pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+ int pixel_size;
int clock;
adjusted_mode =
to_intel_crtc(crtc)-config-base.adjusted_mode;
clock = adjusted_mode-crtc_clock;
+ if (crtc-primary-state-fb)
+ pixel_size = crtc-primary-state-fb-bits_per_pixel /
8;
+ else
+ pixel_size = 4;
+
/* Display SR */
wm = intel_calculate_wm(clock, pineview_display_wm,
pineview_display_wm.fifo_size,
@@ -629,7 +634,11 @@ static bool g4x_compute_wm0(struct drm_device *dev,
clock = adjusted_mode-crtc_clock;
htotal = adjusted_mode-crtc_htotal;
hdisplay = to_intel_crtc(crtc)-config-pipe_src_w;
- pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+
+ if (crtc-primary-state-fb)
+ pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+ else
+ pixel_size = 4;
/* Use the small buffer method to calculate plane watermark */
entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
@@ -716,7 +725,11 @@ static bool g4x_compute_srwm(struct drm_device *dev,
clock = adjusted_mode-crtc_clock;
htotal = adjusted_mode-crtc_htotal;
hdisplay = to_intel_crtc(crtc)-config-pipe_src_w;
- pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+
+ if (crtc-primary-state-fb)
+ pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+ else
+ pixel_size = 4;
line_time_us = max(htotal * 1000 / clock, 1);
line_count = (latency_ns / line_time_us + 1000) / 1000;
@@ -799,7 +812,10 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc)
}
/* Primary plane Drain Latency */
- pixel_size = crtc-primary-state-fb-bits_per_pixel / 8; /* BPP
*/
+ if (crtc-primary-state-fb)
+ pixel_size = crtc-primary-state-fb-bits_per_pixel / 8;
+ else
+ pixel_size = 4;
if (vlv_compute_drain_latency(crtc, pixel_size, prec_mult,
drain_latency)) {
plane_prec = (prec_mult == high_precision) ?
[Intel-gfx] [PATCH 01/12] intel: Remove unused define IS_MOBILE()
Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- intel/intel_chipset.h | 10 -- 1 file changed, 10 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index e22a867..9a8df6a 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -181,16 +181,6 @@ #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D -#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ -(devid) == PCI_CHIP_I915_GM || \ -(devid) == PCI_CHIP_I945_GM || \ -(devid) == PCI_CHIP_I945_GME || \ -(devid) == PCI_CHIP_I965_GM || \ -(devid) == PCI_CHIP_I965_GME || \ -(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT2) - #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ (devid) == PCI_CHIP_Q45_G || \ (devid) == PCI_CHIP_G45_G || \ -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/12] intel: Make drm_intel_decode use a drm_intel_device
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_decode.c | 31 ---
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 7d5cbe5..9ada2fa 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -35,6 +35,7 @@
#include libdrm.h
#include xf86drm.h
+#include intel_device.h
#include intel_chipset.h
#include intel_bufmgr.h
@@ -43,6 +44,9 @@ struct drm_intel_decode {
/** stdio file where the output should land. Defaults to stdout. */
FILE *out;
+ /** Description of the GPU */
+ struct drm_intel_device *dev;
+
/** PCI device ID. */
uint32_t devid;
@@ -3826,27 +3830,15 @@ drm_intel_decode_context_alloc(uint32_t devid)
if (!ctx)
return NULL;
+ ctx-dev = drm_intel_device_new_from_devid(devid);
+ if (!ctx-dev) {
+ free(ctx);
+ return NULL;
+ }
+
ctx-devid = devid;
ctx-out = stdout;
-
- if (IS_GEN9(devid))
- ctx-gen = 9;
- else if (IS_GEN8(devid))
- ctx-gen = 8;
- else if (IS_GEN7(devid))
- ctx-gen = 7;
- else if (IS_GEN6(devid))
- ctx-gen = 6;
- else if (IS_GEN5(devid))
- ctx-gen = 5;
- else if (IS_GEN4(devid))
- ctx-gen = 4;
- else if (IS_9XX(devid))
- ctx-gen = 3;
- else {
- assert(IS_GEN2(devid));
- ctx-gen = 2;
- }
+ ctx-gen = ctx-dev-gen;
return ctx;
}
@@ -3854,6 +3846,7 @@ drm_intel_decode_context_alloc(uint32_t devid)
drm_public void
drm_intel_decode_context_free(struct drm_intel_decode *ctx)
{
+ drm_intel_device_free(ctx-dev);
free(ctx);
}
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 14/53] drm/i915: Update pin_to_display_plane() to do explicit request management
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Added explicit creation creation and submission of the request structure to the
display object pinning code. This removes any reliance on the OLR keeping track
of the request and the unknown randomness that can ensue with other work
becoming part of the same request.
v2: Added semaphore enabled check to prevent allocating a pointless request
structure in the case where the sync just calls wait_rendering().
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4c29177..5897d54 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3943,9 +3943,24 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
int ret;
if (pipelined != i915_gem_request_get_ring(obj-last_read_req)) {
- ret = i915_gem_object_sync(obj, pipelined);
- if (ret)
- return ret;
+ if (!pipelined || !i915_semaphore_is_enabled(obj-base.dev)) {
+ ret = i915_gem_object_wait_rendering(obj, false);
... Also, the ret value here is never checked and returned. It's
overwritten a few lines further down.
Thanks,
Tomas
+ } else {
+ struct drm_i915_private *dev_priv =
pipelined-dev-dev_private;
+ struct drm_i915_gem_request *req;
+
+ ret = dev_priv-gt.alloc_request(pipelined,
pipelined-default_context, req);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_sync(obj, req-ring);
+ if (ret)
+ return ret;
+
+ ret = i915_add_request_no_flush(req-ring);
+ if (ret)
+ return ret;
+ }
}
/* Mark the pin_display early so that we account for the
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[Intel-gfx] [PATCH 10/12] intel: Make test_decode fail gracefully the decode context is NULL
If, for some reason, we couldn't create the decode context, exit,
instead of segfaulting.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/test_decode.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/intel/test_decode.c b/intel/test_decode.c
index 93f47ef..1ffd829 100644
--- a/intel/test_decode.c
+++ b/intel/test_decode.c
@@ -182,6 +182,11 @@ main(int argc, char **argv)
devid = infer_devid(argv[1]);
ctx = drm_intel_decode_context_alloc(devid);
+ if (!ctx) {
+ fprintf(stderr, Couldn't create decode context for 0x%04x\n,
+ devid);
+ exit(1);
+ }
if (argc == 3) {
if (strcmp(argv[2], -dump) == 0)
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 14/53] drm/i915: Update pin_to_display_plane() to do explicit request management
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Added explicit creation creation and submission of the request structure to the
Nitpick: creation creation
display object pinning code. This removes any reliance on the OLR keeping track
of the request and the unknown randomness that can ensue with other work
becoming part of the same request.
v2: Added semaphore enabled check to prevent allocating a pointless request
structure in the case where the sync just calls wait_rendering().
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4c29177..5897d54 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3943,9 +3943,24 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
int ret;
if (pipelined != i915_gem_request_get_ring(obj-last_read_req)) {
- ret = i915_gem_object_sync(obj, pipelined);
- if (ret)
- return ret;
+ if (!pipelined || !i915_semaphore_is_enabled(obj-base.dev)) {
+ ret = i915_gem_object_wait_rendering(obj, false);
+ } else {
The call to i915_gem_object_wait_rendering() was taken from the
implementation of i915_gem_object_sync() below. Ripping out code from
the function you're calling just to do it in advance is not very nice.
Just imagine a scenario where the i915_gem_object_sync() implementation
were to change but the code outside the function would not. We need to
figure out a better way of doing this. In fact, allocating and managing
a request that never gets to be used inside the i915_gem_object_sync()
function could be a better way to go since it poses less potential
future problem even though it's more wasteful. But there are probably
better ways of doing this.
Thanks,
Tomas
+ struct drm_i915_private *dev_priv =
pipelined-dev-dev_private;
+ struct drm_i915_gem_request *req;
+
+ ret = dev_priv-gt.alloc_request(pipelined,
pipelined-default_context, req);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_sync(obj, req-ring);
+ if (ret)
+ return ret;
+
+ ret = i915_add_request_no_flush(req-ring);
+ if (ret)
+ return ret;
+ }
}
/* Mark the pin_display early so that we account for the
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Re: [Intel-gfx] [PATCH 15/53] drm/i915: Update i915_gem_object_sync() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the i915_gem_object_sync()
code path.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|2 +-
drivers/gpu/drm/i915/i915_gem.c|7 ---
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
drivers/gpu/drm/i915/intel_lrc.c |2 +-
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 375d4f9..bfd7b47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2744,7 +2744,7 @@ static inline void i915_gem_object_unpin_pages(struct
drm_i915_gem_object *obj)
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
-struct intel_engine_cs *to);
+struct drm_i915_gem_request *to_req);
void i915_vma_move_to_active(struct i915_vma *vma,
struct intel_engine_cs *ring);
int i915_gem_dumb_create(struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5897d54..c5b9bc7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2956,7 +2956,7 @@ out:
* i915_gem_object_sync - sync an object to a ring.
*
* @obj: object which may be in use on another ring.
- * @to: ring we wish to use the object on. May be NULL.
+ * @to_req: request we wish to use the object for. May be NULL.
*
* This code is meant to abstract object synchronization with the GPU.
* Calling with NULL implies synchronizing the object with the CPU
@@ -2966,8 +2966,9 @@ out:
*/
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
-struct intel_engine_cs *to)
+struct drm_i915_gem_request *to_req)
{
+ struct intel_engine_cs *to = to_req ? to_req-ring : NULL;
struct intel_engine_cs *from;
u32 seqno;
int ret, idx;
@@ -3953,7 +3954,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (ret)
return ret;
- ret = i915_gem_object_sync(obj, req-ring);
+ ret = i915_gem_object_sync(obj, req);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 76f6dcf..2cd0579 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -838,7 +838,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request
*req,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
- ret = i915_gem_object_sync(obj, req-ring);
+ ret = i915_gem_object_sync(obj, req);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b42346..0d88e9c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -589,7 +589,7 @@ static int execlists_move_to_gpu(struct
drm_i915_gem_request *req,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
- ret = i915_gem_object_sync(obj, req-ring);
+ ret = i915_gem_object_sync(obj, req);
if (ret)
return ret;
This seems to be just fine but if the requests of any of the existing
i915_gem_object_sync() call sites were to be null they would cause local
null pointer exceptions in the calling functions even though
i915_gem_object_sync() itself supports an incoming null request. There
does not seem to be any call sites in the driver that actually passes or
supports passing null requests into i915_gem_object_sync(). Does the
driver do that anywhere today or how does that fit in?
Aside from that open question:
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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[Intel-gfx] [PATCH] checkpatch: Add spell checking of email subject line
Only commit log and patch additions are checked for
typos and spelling errors currently. Add a check
of the email subject line too.
Suggested-by: Jani Nikula jani.nik...@linux.intel.com
Signed-off-by: Joe Perches j...@perches.com
---
scripts/checkpatch.pl | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 421bbb4..c061a63 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2303,7 +2303,8 @@ sub process {
}
# Check for various typo / spelling mistakes
- if (defined($misspellings) ($in_commit_log || $line =~
/^\+/)) {
+ if (defined($misspellings)
+ ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) {
while ($rawline =~
/(?:^|[^a-z@])($misspellings)(?:$|[^a-z@])/gi) {
my $typo = $1;
my $typo_fix = $spelling_fix{lc($typo)};
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[Intel-gfx] [PATCH 02/12] intel: Introduce an drm_intel_device object
The intention here is to:
- have a single object that represents a device
- reuse the kernel i915_pciids.h file so we only one place to update
and copy the file over.
- hide the various information about an intel device in that object
instead of having endless #define in intel_chipset.h. That can be
basic info like which gen are we talking about or, hopefully soon,
detailed information about the device (number of
slices/sub-slices/eus/...)
We'll start slowy by making this API an internal detail at the moment.
Maybe it can grow into something better.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/Makefile.sources | 3 +
intel/i915_pciids.h| 289 +++
intel/intel_device.c | 300 +
intel/intel_device.h | 99
4 files changed, 691 insertions(+)
create mode 100644 intel/i915_pciids.h
create mode 100644 intel/intel_device.c
create mode 100644 intel/intel_device.h
diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 7b2272c..0077a17 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -1,9 +1,12 @@
LIBDRM_INTEL_FILES := \
+ i915_pciids.h \
intel_bufmgr.c \
intel_bufmgr_priv.h \
intel_bufmgr_fake.c \
intel_bufmgr_gem.c \
intel_decode.c \
+ intel_device.c \
+ intel_device.h \
intel_chipset.h \
mm.c \
mm.h
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
new file mode 100644
index 000..f2e47fd
--- /dev/null
+++ b/intel/i915_pciids.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2013 Intel Corporation
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * Software), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _I915_PCIIDS_H
+#define _I915_PCIIDS_H
+
+/*
+ * A pci_device_id struct {
+ * __u32 vendor, device;
+ * __u32 subvendor, subdevice;
+ * __u32 class, class_mask;
+ * kernel_ulong_t driver_data;
+ * };
+ * Don't use C99 here because class is reserved and we want to
+ * give userspace flexibility.
+ */
+#define INTEL_VGA_DEVICE(id, info) { \
+ 0x8086, id, \
+ ~0, ~0, \
+ 0x03, 0xff, \
+ (unsigned long) info }
+
+#define INTEL_QUANTA_VGA_DEVICE(info) {\
+ 0x8086, 0x16a, \
+ 0x152d, 0x8990, \
+ 0x03, 0xff, \
+ (unsigned long) info }
+
+#define INTEL_I830_IDS(info) \
+ INTEL_VGA_DEVICE(0x3577, info)
+
+#define INTEL_I845G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2562, info)
+
+#define INTEL_I85X_IDS(info) \
+ INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
+ INTEL_VGA_DEVICE(0x358e, info)
+
+#define INTEL_I865G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
+
+#define INTEL_I915G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
+ INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
+
+#define INTEL_I915GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
+
+#define INTEL_I945G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
+
+#define INTEL_I945GM_IDS(info) \
+ INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
+ INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
+
+#define INTEL_I965G_IDS(info) \
+ INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
+ INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
+ INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */\
+ INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
+
+#define
[Intel-gfx] [PATCH 11/12] intel: Make test_decode not depend on intel_chipset.h
We were pulling a few PCI ids, we can just hardcode them, it doesn't
change much.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/test_decode.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/intel/test_decode.c b/intel/test_decode.c
index 1ffd829..b9897b3 100644
--- a/intel/test_decode.c
+++ b/intel/test_decode.c
@@ -36,7 +36,6 @@
#include libdrm.h
#include intel_bufmgr.h
-#include intel_chipset.h
#define HW_OFFSET 0x1230
@@ -147,9 +146,9 @@ infer_devid(const char *batch_filename)
{ 945, 0x2772},
{ gen4, 0x2a02 },
{ gm45, 0x2a42 },
- { gen5, PCI_CHIP_ILD_G },
- { gen6, PCI_CHIP_SANDYBRIDGE_GT2 },
- { gen7, PCI_CHIP_IVYBRIDGE_GT2 },
+ { gen5, 0x0042 },
+ { gen6, 0x0112 },
+ { gen7, 0x0162 },
{ gen8, 0x1616 },
{ NULL, 0 },
};
--
1.8.3.1
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[Intel-gfx] [PATCH 07/12] intel: Kill the IS_GEN4() macro
Turns out nobody was using it, nor the underlying defines. Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- intel/intel_chipset.h | 15 --- 1 file changed, 15 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index a8a2b0e..241d700 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -181,13 +181,6 @@ #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D -#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ -(devid) == PCI_CHIP_Q45_G || \ -(devid) == PCI_CHIP_G45_G || \ -(devid) == PCI_CHIP_G41_G) -#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) -#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) - #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) @@ -214,14 +207,6 @@ #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) -#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ -(devid) == PCI_CHIP_I965_Q || \ -(devid) == PCI_CHIP_I965_G_1 || \ -(devid) == PCI_CHIP_I965_GM || \ -(devid) == PCI_CHIP_I965_GME || \ -(devid) == PCI_CHIP_I946_GZ || \ -IS_G4X(devid)) - #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/12] intel: Use '||' for the boolean or
While the bitwise operator should do the right thing here, it's probably better to use the logical or here, at least to not cause a 'wtf' when reading the code. At the same time, get rid of unnecessary '()'. Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- intel/intel_bufmgr_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 72a6ab1..8570a30 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3494,8 +3494,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) /* Kernel does not supports HAS_LLC query, fallback to GPU * generation detection and assume that we have LLC on GEN6/7 */ - bufmgr_gem-has_llc = (IS_GEN6(bufmgr_gem-pci_device) | - IS_GEN7(bufmgr_gem-pci_device)); + bufmgr_gem-has_llc = IS_GEN6(bufmgr_gem-pci_device) || + IS_GEN7(bufmgr_gem-pci_device); } else bufmgr_gem-has_llc = *gp.value; -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/12] intel: Use drm_intel_device in the gem buffer manager
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_bufmgr_gem.c | 58 +++-
1 file changed, 8 insertions(+), 50 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 33d8fbc..72a6ab1 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -60,6 +60,7 @@
#include libdrm_lists.h
#include intel_bufmgr.h
#include intel_bufmgr_priv.h
+#include intel_device.h
#include intel_chipset.h
#include intel_aub.h
#include string.h
@@ -120,6 +121,7 @@ typedef struct _drm_intel_bufmgr_gem {
uint64_t gtt_size;
int available_fences;
+ struct drm_intel_device *dev;
int pci_device;
int gen;
unsigned int has_bsd : 1;
@@ -1763,6 +1765,7 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
}
}
+ drm_intel_device_free(bufmgr_gem-dev);
free(bufmgr);
}
@@ -3071,37 +3074,6 @@ drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr
*bufmgr, int limit)
drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
}
-/**
- * Get the PCI ID for the device. This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- */
-static int
-get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
-{
- char *devid_override;
- int devid = 0;
- int ret;
- drm_i915_getparam_t gp;
-
- if (geteuid() == getuid()) {
- devid_override = getenv(INTEL_DEVID_OVERRIDE);
- if (devid_override) {
- bufmgr_gem-no_exec = true;
- return strtod(devid_override, NULL);
- }
- }
-
- memclear(gp);
- gp.param = I915_PARAM_CHIPSET_ID;
- gp.value = devid;
- ret = drmIoctl(bufmgr_gem-fd, DRM_IOCTL_I915_GETPARAM, gp);
- if (ret) {
- fprintf(stderr, get chip id failed: %d [%d]\n, ret, errno);
- fprintf(stderr, param: %d, val: %d\n, gp.param, *gp.value);
- }
- return devid;
-}
-
drm_public int
drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
{
@@ -3469,30 +3441,16 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
(int)bufmgr_gem-gtt_size / 1024);
}
- bufmgr_gem-pci_device = get_pci_device_id(bufmgr_gem);
-
- if (IS_GEN2(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 2;
- else if (IS_GEN3(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 3;
- else if (IS_GEN4(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 4;
- else if (IS_GEN5(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 5;
- else if (IS_GEN6(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 6;
- else if (IS_GEN7(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 7;
- else if (IS_GEN8(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 8;
- else if (IS_GEN9(bufmgr_gem-pci_device))
- bufmgr_gem-gen = 9;
- else {
+ bufmgr_gem-dev = drm_intel_device_new(fd);
+ if (bufmgr_gem-dev == NULL) {
free(bufmgr_gem);
bufmgr_gem = NULL;
goto exit;
}
+ bufmgr_gem-pci_device = drm_intel_device_get_devid(bufmgr_gem-dev);
+ bufmgr_gem-gen = bufmgr_gem-dev-gen;
+
if (IS_GEN3(bufmgr_gem-pci_device)
bufmgr_gem-gtt_size 256*1024*1024) {
/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
--
1.8.3.1
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[Intel-gfx] [PATCH 12/12] intel: Remove intel_chipset.h
Finally, we can remove this file now that everything is using drm_intel_device. Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- intel/Makefile.sources | 1 - intel/intel_bufmgr_gem.c | 1 - intel/intel_chipset.h| 184 --- intel/intel_decode.c | 1 - 4 files changed, 187 deletions(-) delete mode 100644 intel/intel_chipset.h diff --git a/intel/Makefile.sources b/intel/Makefile.sources index 2f8398b..b58ca4f 100644 --- a/intel/Makefile.sources +++ b/intel/Makefile.sources @@ -8,7 +8,6 @@ LIBDRM_INTEL_FILES := \ intel_device.c \ intel_device.h \ intel_device_priv.h \ - intel_chipset.h \ mm.c \ mm.h diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 011fa5b..d0119fc 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -61,7 +61,6 @@ #include intel_bufmgr.h #include intel_bufmgr_priv.h #include intel_device_priv.h -#include intel_chipset.h #include intel_aub.h #include string.h diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h deleted file mode 100644 index 134c877..000 --- a/intel/intel_chipset.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * Software), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _INTEL_CHIPSET_H -#define _INTEL_CHIPSET_H - -#define PCI_CHIP_I810 0x7121 -#define PCI_CHIP_I810_DC1000x7123 -#define PCI_CHIP_I810_E0x7125 -#define PCI_CHIP_I815 0x1132 - -#define PCI_CHIP_I830_M0x3577 -#define PCI_CHIP_845_G 0x2562 -#define PCI_CHIP_I855_GM 0x3582 -#define PCI_CHIP_I865_G0x2572 - -#define PCI_CHIP_I915_G0x2582 -#define PCI_CHIP_E7221_G 0x258A -#define PCI_CHIP_I915_GM 0x2592 -#define PCI_CHIP_I945_G0x2772 -#define PCI_CHIP_I945_GM 0x27A2 -#define PCI_CHIP_I945_GME 0x27AE - -#define PCI_CHIP_Q35_G 0x29B2 -#define PCI_CHIP_G33_G 0x29C2 -#define PCI_CHIP_Q33_G 0x29D2 - -#define PCI_CHIP_IGD_GM0xA011 -#define PCI_CHIP_IGD_G 0xA001 - -#define IS_IGDGM(devid)((devid) == PCI_CHIP_IGD_GM) -#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) -#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) - -#define PCI_CHIP_I965_G0x29A2 -#define PCI_CHIP_I965_Q0x2992 -#define PCI_CHIP_I965_G_1 0x2982 -#define PCI_CHIP_I946_GZ 0x2972 -#define PCI_CHIP_I965_GM 0x2A02 -#define PCI_CHIP_I965_GME 0x2A12 - -#define PCI_CHIP_GM45_GM 0x2A42 - -#define PCI_CHIP_IGD_E_G 0x2E02 -#define PCI_CHIP_Q45_G 0x2E12 -#define PCI_CHIP_G45_G 0x2E22 -#define PCI_CHIP_G41_G 0x2E32 - -#define PCI_CHIP_ILD_G 0x0042 -#define PCI_CHIP_ILM_G 0x0046 - -#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ -#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 -#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 -#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ -#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 -#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS0x0126 -#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ - -#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ -#define PCI_CHIP_IVYBRIDGE_GT2 0x0162 -#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ -#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 -#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ -#define PCI_CHIP_IVYBRIDGE_S_GT2
[Intel-gfx] [PATCH 08/12] intel: Remove direct usage of IS_915()
One more step towards getting rid of intel_chipset.h. The slightly tricky bit here is that I don't want to leave defines like IS_CHIP() or IS_GEN4() is a file that can potentially become a public header. intel_device_priv.h was introduced then. Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- intel/Makefile.sources| 1 + intel/intel_bufmgr_gem.c | 6 +++--- intel/intel_device_priv.h | 35 +++ 3 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 intel/intel_device_priv.h diff --git a/intel/Makefile.sources b/intel/Makefile.sources index 0077a17..2f8398b 100644 --- a/intel/Makefile.sources +++ b/intel/Makefile.sources @@ -7,6 +7,7 @@ LIBDRM_INTEL_FILES := \ intel_decode.c \ intel_device.c \ intel_device.h \ + intel_device_priv.h \ intel_chipset.h \ mm.c \ mm.h diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 8570a30..58543a2 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -60,7 +60,7 @@ #include libdrm_lists.h #include intel_bufmgr.h #include intel_bufmgr_priv.h -#include intel_device.h +#include intel_device_priv.h #include intel_chipset.h #include intel_aub.h #include string.h @@ -338,7 +338,7 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, return ALIGN(pitch, 64); if (*tiling_mode == I915_TILING_X - || (IS_915(bufmgr_gem-pci_device) + || (IS_CHIP(bufmgr_gem-dev, I915) *tiling_mode == I915_TILING_Y)) tile_width = 512; else @@ -843,7 +843,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, if ((bufmgr_gem-gen == 2) tiling != I915_TILING_NONE) height_alignment = 16; else if (tiling == I915_TILING_X - || (IS_915(bufmgr_gem-pci_device) + || (IS_CHIP(bufmgr_gem-dev, I915) tiling == I915_TILING_Y)) height_alignment = 8; else if (tiling == I915_TILING_Y) diff --git a/intel/intel_device_priv.h b/intel/intel_device_priv.h new file mode 100644 index 000..87dc1dc --- /dev/null +++ b/intel/intel_device_priv.h @@ -0,0 +1,35 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef __INTEL_DEVICE_PRIV_H__ +#define __INTEL_DEVICE_PRIV_H__ + +#include intel_device.h + +/* + * Shorthand defines. These are not namespaced and shouldn't be in a public + * header, hence a _priv.h one for internal use. + */ +#define IS_CHIP(dev, id) ((dev)-chip == DRM_INTEL_CHIP_ ## id) + +#endif /* __INTEL_DEVICE_PRIV_H__ */ -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/12] intel: Kill the IS_9XX() macro
IS_9XX() has grown to mean gen = 3. It was only used in a single test:
(IS_9XX !IS_GEN3)
Which has then be replaced with gen = 4.
The code in that area was idented a bit weirdly, so do a pass on that as
well.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_chipset.h | 9 -
intel/intel_decode.c | 13 +
2 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 9a8df6a..a8a2b0e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -354,13 +354,4 @@
#define IS_GEN9(devid) IS_SKYLAKE(devid)
-#define IS_9XX(dev)(IS_GEN3(dev) || \
-IS_GEN4(dev) || \
-IS_GEN5(dev) || \
-IS_GEN6(dev) || \
-IS_GEN7(dev) || \
-IS_GEN8(dev) || \
-IS_GEN9(dev))
-
-
#endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 9ada2fa..2fd2cc5 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3949,15 +3949,12 @@ drm_intel_decode(struct drm_intel_decode *ctx)
index += decode_2d(ctx);
break;
case 0x3:
- if (IS_9XX(devid) !IS_GEN3(devid)) {
- index +=
- decode_3d_965(ctx);
- } else if (IS_GEN3(devid)) {
+ if (ctx-dev-gen = 4)
+ index += decode_3d_965(ctx);
+ else if (IS_GEN3(devid))
index += decode_3d(ctx);
- } else {
- index +=
- decode_3d_i830(ctx);
- }
+ else
+ index += decode_3d_i830(ctx);
break;
default:
instr_out(ctx, index, UNKNOWN\n);
--
1.8.3.1
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[Intel-gfx] [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
A couple of things I wanted to do for the longest time: - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the file when updating - Start a new object, struct drm_intel_device where we could put common code across several userspace projects. For instance it could be where we put the number of threads logic we need to use in several 3d/gpgpu states/instructions (that's a bit fiddly starting with CHV: we can't use static tables anymore and need a runtime query to the kernel) I tested it a bit so it can't be totally wrong: - I ran with this series on a couple of machines with no noticeable problem - I check that the INTEL_DEVID_OVERRIDE env variable was still working (to dump AUB files) - make check, which exercises changes in the decoder path, still passes -- Damien Damien Lespiau (12): intel: Remove unused define IS_MOBILE() intel: Introduce an drm_intel_device object intel: Use drm_intel_device in the gem buffer manager intel: Make drm_intel_decode use a drm_intel_device intel: Use '||' for the boolean or intel: Kill the IS_9XX() macro intel: Kill the IS_GEN4() macro intel: Remove direct usage of IS_915() intel: Provide IS_GENX() macros taking a drm_intel_device as argument intel: Make test_decode fail gracefully the decode context is NULL intel: Make test_decode not depend on intel_chipset.h intel: Remove intel_chipset.h intel/Makefile.sources| 5 +- intel/i915_pciids.h | 289 +++ intel/intel_bufmgr_gem.c | 70 ++--- intel/intel_chipset.h | 376 -- intel/intel_decode.c | 82 +- intel/intel_device.c | 300 intel/intel_device.h | 99 intel/intel_device_priv.h | 43 ++ intel/test_decode.c | 12 +- 9 files changed, 791 insertions(+), 485 deletions(-) create mode 100644 intel/i915_pciids.h delete mode 100644 intel/intel_chipset.h create mode 100644 intel/intel_device.c create mode 100644 intel/intel_device.h create mode 100644 intel/intel_device_priv.h -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/53] drm/i915: Wrap request allocation with a function pointer
On Thu, Mar 05, 2015 at 03:01:21PM +, Tomas Elf wrote:
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
In order to explicitly manage requests from creation to submission, it is
necessary to be able to explicitly create them in the first place. This patch
adds an indirection wrapper to the request creation function so that it can
be
called from generic code without having to worry about execlist vs legacy
mode.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c |2 ++
drivers/gpu/drm/i915/intel_lrc.c|6 +++---
drivers/gpu/drm/i915/intel_lrc.h|2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c |6 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h |2 ++
6 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index b350910..87a4a2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1908,6 +1908,8 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
struct {
+int (*alloc_request)(struct intel_engine_cs *ring,
+ struct intel_context *ctx);
int (*do_execbuf)(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas);
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 7a0dc7c..cf959e3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4860,11 +4860,13 @@ int i915_gem_init(struct drm_device *dev)
}
if (!i915.enable_execlists) {
+dev_priv-gt.alloc_request = intel_ring_alloc_request;
dev_priv-gt.do_execbuf = i915_gem_ringbuffer_submission;
dev_priv-gt.init_rings = i915_gem_init_rings;
dev_priv-gt.cleanup_ring = intel_cleanup_ring_buffer;
dev_priv-gt.stop_ring = intel_stop_ring_buffer;
} else {
+dev_priv-gt.alloc_request = intel_logical_ring_alloc_request;
dev_priv-gt.do_execbuf = intel_execlists_submission;
dev_priv-gt.init_rings = intel_logical_rings_init;
dev_priv-gt.cleanup_ring = intel_logical_ring_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index dc474b4..8628abf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -856,8 +856,8 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring,
}
}
-static int logical_ring_alloc_request(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+int intel_logical_ring_alloc_request(struct intel_engine_cs *ring,
+ struct intel_context *ctx)
{
struct drm_i915_gem_request *request;
struct drm_i915_private *dev_private = ring-dev-dev_private;
@@ -1066,7 +1066,7 @@ int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf,
return ret;
/* Preallocate the olr before touching the ring */
-ret = logical_ring_alloc_request(ring, ctx);
+ret = intel_logical_ring_alloc_request(ring, ctx);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h
b/drivers/gpu/drm/i915/intel_lrc.h
index 3a6abce..3cc38bd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,6 +36,8 @@
#define RING_CONTEXT_STATUS_PTR(ring) ((ring)-mmio_base+0x3a0)
/* Logical Rings */
+int __must_check intel_logical_ring_alloc_request(struct intel_engine_cs
*ring,
+ struct intel_context *ctx);
void intel_logical_ring_stop(struct intel_engine_cs *ring);
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
int intel_logical_rings_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7fd89e5..635707a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2163,8 +2163,8 @@ int intel_ring_idle(struct intel_engine_cs *ring)
return i915_wait_request(req);
}
-static int
-intel_ring_alloc_request(struct intel_engine_cs *ring)
+int
+intel_ring_alloc_request(struct intel_engine_cs *ring, struct intel_context
*ctx)
{
int ret;
struct drm_i915_gem_request *request;
@@ -2229,7 +2229,7 @@ int intel_ring_begin(struct intel_engine_cs *ring,
return ret;
/* Preallocate the olr before touching the ring */
-ret = intel_ring_alloc_request(ring);
+ret = intel_ring_alloc_request(ring,
Re: [Intel-gfx] [PATCH 16/53] drm/i915: Update i915_gpu_idle() to manage its own request
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Added explicit request creation and submission to the GPU idle code path.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c5b9bc7..51f719c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3114,11 +3114,27 @@ int i915_gpu_idle(struct drm_device *dev)
/* Flush everything onto the inactive list. */
for_each_ring(ring, dev_priv, i) {
if (!i915.enable_execlists) {
- ret = i915_switch_context(ring, ring-default_context);
+ struct drm_i915_gem_request *req;
+
+ ret = dev_priv-gt.alloc_request(ring,
ring-default_context, req);
if (ret)
return ret;
+
+ ret = i915_switch_context(req-ring,
ring-default_context);
+ if (ret) {
+ i915_gem_request_unreference(req);
+ return ret;
+ }
+
+ ret = i915_add_request_no_flush(req-ring);
+ if (ret) {
+ i915_gem_request_unreference(req);
+ return ret;
+ }
}
+ WARN_ON(ring-outstanding_lazy_request);
+
ret = intel_ring_idle(ring);
if (ret)
return ret;
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 17/53] drm/i915: Split i915_ppgtt_init_hw() in half - generic and per ring
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The i915_gem_init_hw() function calls a bunch of smaller initialisation
functions. Multiple of which have generic sections and per ring sections. This
means multiple passes are done over the rings. Each pass writes data to the ring
which floats around in that ring's OLR until some random point in the future
when an add_request() is done by some random other piece of code.
This patch breaks i915_ppgtt_init_hw() in two with the per ring initialisation
now being done in i915_ppgtt_init_ring(). The ring looping is now done at the
top level in i915_gem_init_hw().
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 25 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 25 -
drivers/gpu/drm/i915/i915_gem_gtt.h |1 +
3 files changed, 32 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 51f719c..9bc60d7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4844,19 +4844,32 @@ i915_gem_init_hw(struct drm_device *dev)
*/
init_unused_rings(dev);
+ ret = i915_ppgtt_init_hw(dev);
+ if (ret) {
+ DRM_ERROR(PPGTT enable HW failed %d\n, ret);
+ return ret;
+ }
+
+ /* Need to do basic initialisation of all rings first: */
Nitpick: No need for trailing colon in comment
for_each_ring(ring, dev_priv, i) {
ret = ring-init_hw(ring);
if (ret)
return ret;
}
- for (i = 0; i NUM_L3_SLICES(dev); i++)
- i915_gem_l3_remap(dev_priv-ring[RCS], i);
+ /* Now it is safe to go back round and do everything else: */
Nitpick: No need for trailing colon in comment
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
+ for_each_ring(ring, dev_priv, i) {
+ if (ring-id == RCS) {
+ for (i = 0; i NUM_L3_SLICES(dev); i++)
+ i915_gem_l3_remap(ring, i);
+ }
- ret = i915_ppgtt_init_hw(dev);
- if (ret ret != -EIO) {
- DRM_ERROR(PPGTT enable failed %d\n, ret);
- i915_gem_cleanup_ringbuffer(dev);
+ ret = i915_ppgtt_init_ring(ring);
+ if (ret ret != -EIO) {
+ DRM_ERROR(PPGTT enable ring #%d failed %d\n, i, ret);
+ i915_gem_cleanup_ringbuffer(dev);
+ return ret;
+ }
}
ret = i915_gem_context_enable(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e54b2a0..428d2f6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1206,11 +1206,6 @@ int i915_ppgtt_init(struct drm_device *dev, struct
i915_hw_ppgtt *ppgtt)
int i915_ppgtt_init_hw(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev-dev_private;
- struct intel_engine_cs *ring;
- struct i915_hw_ppgtt *ppgtt = dev_priv-mm.aliasing_ppgtt;
- int i, ret = 0;
-
/* In the case of execlists, PPGTT is enabled by the context descriptor
* and the PDPs are contained within the context itself. We don't
* need to do anything here. */
@@ -1229,16 +1224,20 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
else
MISSING_CASE(INTEL_INFO(dev)-gen);
- if (ppgtt) {
- for_each_ring(ring, dev_priv, i) {
- ret = ppgtt-switch_mm(ppgtt, ring);
- if (ret != 0)
- return ret;
- }
- }
+ return 0;
+}
- return ret;
+int i915_ppgtt_init_ring(struct intel_engine_cs *ring)
+{
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ struct i915_hw_ppgtt *ppgtt = dev_priv-mm.aliasing_ppgtt;
+
+ if (!ppgtt)
+ return 0;
+
+ return ppgtt-switch_mm(ppgtt, ring);
}
+
struct i915_hw_ppgtt *
i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8f76990..5a6cef9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -300,6 +300,7 @@ void i915_global_gtt_cleanup(struct drm_device *dev);
int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
int i915_ppgtt_init_hw(struct drm_device *dev);
+int i915_ppgtt_init_ring(struct intel_engine_cs *ring);
void i915_ppgtt_release(struct kref *kref);
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
struct drm_i915_file_private *fpriv);
Re: [Intel-gfx] [PATCH 09/12] drm/i915: Rewrite VLV/CHV watermark code
On Tue, Feb 10, 2015 at 03:28:26PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Assuming the PND deadline mechanism works reasonably we should do memory requests as early as possible so that PND has schedule the requests more intelligently. Currently we're still calculating the watermarks as if VLV/CHV are identical to g4x, which isn't the case. The current code also seems to calculate insufficient watermarks and hence we're seeing some underruns, especially on high resolution displays. To fix it just rip out the current code and replace is with something that tries to utilize PND as efficiently as possible. We now calculate the WM watermark to trigger when the FIFO still has 256us worth of data. 256us is the maximum deadline value supoorted by PND, so issuing memory requests earlier would mean we probably couldn't utilize the full FIFO as PND would attempt to return the data at least in at least 256us. We also clamp the watermark to at least 8 cachelines as that's the magic watermark that enabling trickle feed would also impose. I'm assuming it matches some burst size. In theory we could just enable trickle feed and ignore the WM values, except trickle feed doesn't work with max fifo mode anyway, so we'd still need to calculate the SR watermarks. It seems cleaner to just disable trickle feed and calculate all watermarks the same way. Also trickle feed wouldn't account for the 256us max deadline value, thoguh that may be a moot point in non-max fifo mode sicne the FIFOs are fairly small. On VLV max fifo mode can be used with either primary or sprite planes. So the code now also checks all the planes (apart from the cursor) when calculating the SR plane watermark. We don't have to worry about the WM1 watermarks since we're using the PND deadline scheme which means the hardware ignores WM1 values. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com This patch still lacks review. Any takers? -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Disable DDR DVFS on CHV
On Tue, Mar 03, 2015 at 01:27:17PM +0530, Arun R Murthy wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
DDR DVFS introduces massive memory latencies which can't be handled by the
PND deadline stuff. Instead the watermarks will need to be programmed to
compensate for the latency and the deadlines will need to be programmed to
tight fixed values. That means DDR DVFS can only be enabled if the display
FIFOs are large enough, and that pretty much means we have to manually
repartition them to suit the needs of the moment.
That's a lot of change, so in the meantime let's just disable DDR DVFS to
get the display(s) to be stable.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 34 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h index 581813e..f67be5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -630,6 +630,11 @@ enum skl_disp_power_wells {
#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT8
+#define PUNIT_REG_DDR_SETUP2 0x139
+#define FORCE_DDR_FREQ_REQ_ACK (1 8)
+#define FORCE_DDR_LOW_FREQ (1 1)
+#define FORCE_DDR_HIGH_FREQ (1 0)
+
#define PUNIT_GPU_STATUS_REG 0xdb
#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
#define PUNIT_GPU_STATUS_MAX_FREQ_MASK0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c index f603dac..f43d77c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -235,6 +235,28 @@ static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop,
return NULL;
}
+static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool
+enable) {
+ u32 val;
+
+ mutex_lock(dev_priv-rps.hw_lock);
+
+ val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
+ if (enable)
+ val = ~FORCE_DDR_HIGH_FREQ;
+ else
+ val |= FORCE_DDR_HIGH_FREQ;
+ val = ~FORCE_DDR_LOW_FREQ;
+ val |= FORCE_DDR_FREQ_REQ_ACK;
+ vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
+
+ if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2)
+ FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
+ DRM_ERROR(timed out waiting for Punit DDR DVFS request\n);
+
+ mutex_unlock(dev_priv-rps.hw_lock);
+}
+
static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool
enable) {
u32 val;
@@ -281,6 +303,7 @@ void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv, bool enable)
enable ? enabled : disabled); }
+
/*
* Latency for FIFO fetches is dependent on several factors:
* - memory configuration (speed, channels)
@@ -1000,6 +1023,17 @@ static void valleyview_update_wm(struct drm_crtc
*crtc)
wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
wm.sr.plane, wm.sr.cursor);
+ /*
+* FIXME DDR DVFS introduces massive memory latencies which
+* are not known to system agent so any deadline specified
+* by the display may not be respected. To support DDR DVFS
+* the watermark code needs to be rewritten to essentially
+* bypass deadline mechanism and rely solely on the
+* watermarks. For now disable DDR DVFS.
+*/
+ if (IS_CHERRYVIEW(dev_priv))
+ chv_set_memory_dvfs(dev_priv, false);
DDR DVFS should be enabled only when we are in single plane,|
single pipe mode, i.e ideally in maxfifo mode.
As stated it's going to take a bit of work to get the code into proper
shape especially as we want to change the FIFO partitioning to maximize
the chances of getting DVFS working. Relying on maxfifo alone won't work
since we can't force the hardware to use it, it'll make that decision on
its own.
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 20/53] drm/i915: Update ppgtt_init_ring() context_enable() to take requests
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The final step in removing the OLR from i915_gem_init_hw() is to pass the newly
allocated request structure in to each step rather than passing a ring
structure. This patch updates both i915_ppgtt_init_ring() and
i915_gem_context_enable() to take request pointers.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_gem.c |4 ++--
drivers/gpu/drm/i915/i915_gem_context.c |7 ---
drivers/gpu/drm/i915/i915_gem_gtt.c |6 +++---
drivers/gpu/drm/i915/i915_gem_gtt.h |2 +-
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea0da6b..618a841 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2990,7 +2990,7 @@ int __must_check i915_gem_context_init(struct drm_device
*dev);
void i915_gem_context_fini(struct drm_device *dev);
void i915_gem_context_reset(struct drm_device *dev);
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
-int i915_gem_context_enable(struct intel_engine_cs *ring);
+int i915_gem_context_enable(struct drm_i915_gem_request *req);
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
int i915_switch_context(struct intel_engine_cs *ring,
struct intel_context *to);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index efed49a..379bf44 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4877,7 +4877,7 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_l3_remap(ring, i);
}
- ret = i915_ppgtt_init_ring(ring);
+ ret = i915_ppgtt_init_ring(req);
if (ret ret != -EIO) {
DRM_ERROR(PPGTT enable ring #%d failed %d\n, i, ret);
i915_gem_request_unreference(req);
@@ -4885,7 +4885,7 @@ i915_gem_init_hw(struct drm_device *dev)
return ret;
}
- ret = i915_gem_context_enable(ring);
+ ret = i915_gem_context_enable(req);
if (ret ret != -EIO) {
DRM_ERROR(Context enable ring #%d failed %d\n, i,
ret);
i915_gem_request_unreference(req);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index dd83d61..04d2a20 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -403,17 +403,18 @@ void i915_gem_context_fini(struct drm_device *dev)
i915_gem_context_unreference(dctx);
}
-int i915_gem_context_enable(struct intel_engine_cs *ring)
+int i915_gem_context_enable(struct drm_i915_gem_request *req)
{
+ struct intel_engine_cs *ring = req-ring;
int ret;
if (i915.enable_execlists) {
if (ring-init_context == NULL)
return 0;
- ret = ring-init_context(ring, ring-default_context);
+ ret = ring-init_context(req-ring, ring-default_context);
} else
- ret = i915_switch_context(ring, ring-default_context);
+ ret = i915_switch_context(req-ring, ring-default_context);
You don't have to make any more changes to this function aside from
setting up the ring variable at the top. ring = req-ring and if you
don't change these lines the will by default use ring like they always did.
if (ret) {
DRM_ERROR(ring init context: %d\n, ret);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 428d2f6..cd00080 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1227,15 +1227,15 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
return 0;
}
-int i915_ppgtt_init_ring(struct intel_engine_cs *ring)
+int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
{
- struct drm_i915_private *dev_priv = ring-dev-dev_private;
+ struct drm_i915_private *dev_priv = req-ring-dev-dev_private;
struct i915_hw_ppgtt *ppgtt = dev_priv-mm.aliasing_ppgtt;
if (!ppgtt)
return 0;
- return ppgtt-switch_mm(ppgtt, ring);
+ return ppgtt-switch_mm(ppgtt, req-ring);
}
If you want to uphold a pattern that you've already established you
could just make a single change in the function above by setting up ring
= req-ring and then make no more changes to the function body. In this
case it's one new line vs. two changes of existing code so it's doesn't
make that much of a difference but it is nice to stick to patterns.
Also, you wouldn't have to make a 4-level indirection
(req-ring-dev-dev_private),
Re: [Intel-gfx] [PATCH 21/53] drm/i915: Set context in request from creation even in legacy mode
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
In execlist mode, the context object pointer is written in to the request
structure (and reference counted) at the point of request creation. In legacy
mode, this only happens inside i915_add_request().
This patch updates the legacy code path to match the execlist version. This
allows all the intermediate code between request creation and request submission
to get at the context object given only a request structure. Thus negating the
need to pass context pointers here, there and everywhere.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c |9 +
drivers/gpu/drm/i915/intel_ringbuffer.c |2 ++
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 379bf44..64288e3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2470,14 +2470,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
WARN_ON(request-batch_obj obj);
request-batch_obj = obj;
- if (!i915.enable_execlists) {
- /* Hold a reference to the current context so that we can
inspect
-* it later in case a hangcheck error event fires.
-*/
- request-ctx = ring-last_context;
- if (request-ctx)
- i915_gem_context_reference(request-ctx);
- }
+ WARN_ON(request-ctx != ring-last_context);
__i915_add_request is gen agnostic but ring-last_context is only used
in legacy mode. Maybe you want to check for !i915.enable_execlists just
like in the block you removed above?
request-emitted_jiffies = jiffies;
list_add_tail(request-list, ring-request_list);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1a9f884..05a7e33 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2186,6 +2186,8 @@ intel_ring_alloc_request(struct intel_engine_cs *ring,
request-ring = ring;
request-ringbuf = ring-buffer;
request-uniq = dev_private-request_uniq++;
+ request-ctx = ctx;
+ i915_gem_context_reference(request-ctx);
ret = i915_gem_get_seqno(ring-dev, request-seqno);
if (ret) {
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Re: [Intel-gfx] [PATCH 22/53] drm/i915: Update i915_switch_context() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Now that the request is guaranteed to specify the context, it is possible to
update the context switch code to use requests rather than ring and context
pairs. This patch updates i915_switch_context() accordingly.
Also removed the warning that the request's context must match the last context
switch's context. As the context switch now gets the context object from the
request structure, there is no longer any scope for the two to become out of
step.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|3 +--
drivers/gpu/drm/i915/i915_gem.c|4 +---
drivers/gpu/drm/i915/i915_gem_context.c| 19 +--
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
4 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 618a841..e9cc343 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2992,8 +2992,7 @@ void i915_gem_context_reset(struct drm_device *dev);
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
int i915_gem_context_enable(struct drm_i915_gem_request *req);
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
-int i915_switch_context(struct intel_engine_cs *ring,
- struct intel_context *to);
+int i915_switch_context(struct drm_i915_gem_request *req);
struct intel_context *
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
void i915_gem_context_free(struct kref *ctx_ref);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 64288e3..0c7e1bd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2470,8 +2470,6 @@ int __i915_add_request(struct intel_engine_cs *ring,
WARN_ON(request-batch_obj obj);
request-batch_obj = obj;
- WARN_ON(request-ctx != ring-last_context);
-
request-emitted_jiffies = jiffies;
list_add_tail(request-list, ring-request_list);
request-file_priv = NULL;
@@ -3114,7 +3112,7 @@ int i915_gpu_idle(struct drm_device *dev)
if (ret)
return ret;
- ret = i915_switch_context(req-ring,
ring-default_context);
+ ret = i915_switch_context(req);
if (ret) {
i915_gem_request_unreference(req);
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 04d2a20..b326f8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ int i915_gem_context_enable(struct drm_i915_gem_request
*req)
ret = ring-init_context(req-ring, ring-default_context);
} else
- ret = i915_switch_context(req-ring, ring-default_context);
+ ret = i915_switch_context(req);
if (ret) {
DRM_ERROR(ring init context: %d\n, ret);
@@ -693,8 +693,7 @@ unpin_out:
/**
* i915_switch_context() - perform a GPU context switch.
- * @ring: ring for which we'll execute the context switch
- * @to: the context to switch to
+ * @req: request for which we'll execute the context switch
*
* The context life cycle is simple. The context refcount is incremented and
* decremented by 1 and create and destroy. If the context is in use by the
GPU,
@@ -705,25 +704,25 @@ unpin_out:
* switched by writing to the ELSP and requests keep a reference to their
* context.
*/
-int i915_switch_context(struct intel_engine_cs *ring,
- struct intel_context *to)
+int i915_switch_context(struct drm_i915_gem_request *req)
{
+ struct intel_engine_cs *ring = req-ring;
struct drm_i915_private *dev_priv = ring-dev-dev_private;
WARN_ON(i915.enable_execlists);
WARN_ON(!mutex_is_locked(dev_priv-dev-struct_mutex));
- if (to-legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context
*/
- if (to != ring-last_context) {
- i915_gem_context_reference(to);
+ if (req-ctx-legacy_hw_ctx.rcs_state == NULL) { /* We have the fake
context */
+ if (req-ctx != ring-last_context) {
+ i915_gem_context_reference(req-ctx);
if (ring-last_context)
i915_gem_context_unreference(ring-last_context);
- ring-last_context = to;
+ ring-last_context = req-ctx;
}
return 0;
}
- return do_switch(ring, to);
+ return do_switch(req-ring, req-ctx);
}
static bool contexts_enabled(struct
Re: [Intel-gfx] [PATCH 1/8] drm/i915/skl: Added new macros
On Thu, Mar 05, 2015 at 02:12:07PM +0530, Akash Goel wrote: On Thu, 2015-02-26 at 12:50 +, Chris Wilson wrote: On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.g...@intel.com wrote: +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv-dev) ? \ + INTERVAL_1_33_US(us) : \ + INTERVAL_1_28_US(us)) Just use IS_GEN9(dev_priv) Fine, will use 'dev_priv', actually missed the definition of '__I915__' macro. Is implicit use of 'dev_priv' fine ?. Actually saw several such instances in i915_reg.h file, that's why used like this. I am trying to wean i915 away from using the implicit arg as it is making our code larger by the extra pointer dancing it forces upon us. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/8] drm/i915/skl: Added new macros
On Thu, 2015-02-26 at 12:50 +, Chris Wilson wrote: On Thu, Feb 26, 2015 at 06:19:37PM +0530, akash.g...@intel.com wrote: +#define GT_INTERVAL_FROM_US(us) (IS_GEN9(dev_priv-dev) ? \ + INTERVAL_1_33_US(us) : \ + INTERVAL_1_28_US(us)) Just use IS_GEN9(dev_priv) Fine, will use 'dev_priv', actually missed the definition of '__I915__' macro. Is implicit use of 'dev_priv' fine ?. Actually saw several such instances in i915_reg.h file, that's why used like this. Best regards Akash -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The alloc_request() function does not actually return the newly allocated
request. Instead, it must be pulled from ring-outstanding_lazy_request. This
patch fixes this so that code can create a request and start using it knowing
exactly which request it actually owns.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|3 ++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c |3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 13 +
drivers/gpu/drm/i915/intel_lrc.h |3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c| 14 ++
drivers/gpu/drm/i915/intel_ringbuffer.h|3 ++-
6 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 87a4a2e..90223f208 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1909,7 +1909,8 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists)
away */
struct {
int (*alloc_request)(struct intel_engine_cs *ring,
-struct intel_context *ctx);
+struct intel_context *ctx,
+struct drm_i915_gem_request **req_out);
int (*do_execbuf)(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 61471e9..37dcc6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1353,6 +1353,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct i915_address_space *vm;
struct i915_execbuffer_params params_master; /* XXX: will be removed
later */
struct i915_execbuffer_params *params = params_master;
+ struct drm_i915_gem_request *request;
Please initialize request to NULL. If you accidentally dereference it
before it is allocated (seeing as the allocation is several pages down
from here) you get a null pointer exception, which is a clear indication
that you did something stupid. Otherwise it's not clear what will happen
(sure, page fault, but null pointer exception is a better failure
indication).
Thanks,
Tomas
const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
u32 dispatch_flags;
int ret;
@@ -1531,7 +1532,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params-batch_obj_vm_offset = i915_gem_obj_offset(batch_obj,
vm);
/* Allocate a request for this batch buffer nice and early. */
- ret = dev_priv-gt.alloc_request(ring, ctx);
+ ret = dev_priv-gt.alloc_request(ring, ctx, request);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8628abf..c3c783f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -857,13 +857,17 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring,
}
int intel_logical_ring_alloc_request(struct intel_engine_cs *ring,
-struct intel_context *ctx)
+struct intel_context *ctx,
+struct drm_i915_gem_request **req_out)
{
struct drm_i915_gem_request *request;
struct drm_i915_private *dev_private = ring-dev-dev_private;
int ret;
- if (ring-outstanding_lazy_request)
+ if (!req_out)
+ return -EINVAL;
+
+ if ((*req_out = ring-outstanding_lazy_request) != NULL)
return 0;
request = kzalloc(sizeof(*request), GFP_KERNEL);
@@ -898,7 +902,7 @@ int intel_logical_ring_alloc_request(struct intel_engine_cs
*ring,
i915_gem_context_reference(request-ctx);
request-ringbuf = ctx-engine[ring-id].ringbuf;
- ring-outstanding_lazy_request = request;
+ *req_out = ring-outstanding_lazy_request = request;
return 0;
}
@@ -1051,6 +1055,7 @@ static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf,
int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
struct intel_context *ctx, int num_dwords)
{
+ struct drm_i915_gem_request *req;
struct intel_engine_cs *ring = ringbuf-ring;
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1066,7 +1071,7 @@ int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf,
return ret;
/* Preallocate the olr before touching the ring */
- ret =
Re: [Intel-gfx] [PATCH 08/53] drm/i915: Update alloc_request to return the allocated request
On 05/03/2015 15:27, Tomas Elf wrote:
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The alloc_request() function does not actually return the newly
allocated
request. Instead, it must be pulled from
ring-outstanding_lazy_request. This
patch fixes this so that code can create a request and start using it
knowing
exactly which request it actually owns.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|3 ++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c |3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 13 +
drivers/gpu/drm/i915/intel_lrc.h |3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c| 14 ++
drivers/gpu/drm/i915/intel_ringbuffer.h|3 ++-
6 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index 87a4a2e..90223f208 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1909,7 +1909,8 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or
execlists) away */
struct {
int (*alloc_request)(struct intel_engine_cs *ring,
- struct intel_context *ctx);
+ struct intel_context *ctx,
+ struct drm_i915_gem_request **req_out);
int (*do_execbuf)(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 61471e9..37dcc6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1353,6 +1353,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
void *data,
struct i915_address_space *vm;
struct i915_execbuffer_params params_master; /* XXX: will be
removed later */
struct i915_execbuffer_params *params = params_master;
+struct drm_i915_gem_request *request;
Please initialize request to NULL. If you accidentally dereference it
before it is allocated (seeing as the allocation is several pages down
from here) you get a null pointer exception, which is a clear
indication that you did something stupid. Otherwise it's not clear
what will happen (sure, page fault, but null pointer exception is a
better failure indication).
That should generate a 'use before assignment' compiler warning.
Thanks,
Tomas
const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
u32 dispatch_flags;
int ret;
@@ -1531,7 +1532,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
void *data,
params-batch_obj_vm_offset =
i915_gem_obj_offset(batch_obj, vm);
/* Allocate a request for this batch buffer nice and early. */
-ret = dev_priv-gt.alloc_request(ring, ctx);
+ret = dev_priv-gt.alloc_request(ring, ctx, request);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index 8628abf..c3c783f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -857,13 +857,17 @@ void intel_lr_context_unpin(struct
intel_engine_cs *ring,
}
int intel_logical_ring_alloc_request(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+ struct intel_context *ctx,
+ struct drm_i915_gem_request **req_out)
{
struct drm_i915_gem_request *request;
struct drm_i915_private *dev_private = ring-dev-dev_private;
int ret;
-if (ring-outstanding_lazy_request)
+if (!req_out)
+return -EINVAL;
+
+if ((*req_out = ring-outstanding_lazy_request) != NULL)
return 0;
request = kzalloc(sizeof(*request), GFP_KERNEL);
@@ -898,7 +902,7 @@ int intel_logical_ring_alloc_request(struct
intel_engine_cs *ring,
i915_gem_context_reference(request-ctx);
request-ringbuf = ctx-engine[ring-id].ringbuf;
-ring-outstanding_lazy_request = request;
+*req_out = ring-outstanding_lazy_request = request;
return 0;
}
@@ -1051,6 +1055,7 @@ static int logical_ring_prepare(struct
intel_ringbuffer *ringbuf,
int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
struct intel_context *ctx, int num_dwords)
{
+struct drm_i915_gem_request *req;
struct intel_engine_cs *ring = ringbuf-ring;
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -1066,7 +1071,7 @@ int intel_logical_ring_begin(struct
intel_ringbuffer *ringbuf,
return ret;
/* Preallocate the olr before touching the ring */
-ret = intel_logical_ring_alloc_request(ring, ctx);
+ret = intel_logical_ring_alloc_request(ring, ctx, req);
if (ret)
Re: [Intel-gfx] [PATCH 12/53] drm/i915: Update execbuffer_move_to_active() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the
execbuffer_move_to_active() code path.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c |6 +++---
drivers/gpu/drm/i915/intel_lrc.c |2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 678b190..68d6dec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2643,7 +2643,7 @@ int i915_gem_set_domain_ioctl(struct drm_device *dev,
void *data,
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
- struct intel_engine_cs *ring);
+ struct drm_i915_gem_request *req);
int i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params);
int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index da1e232..f7c19bc 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -950,9 +950,9 @@ i915_gem_validate_context(struct drm_device *dev, struct
drm_file *file,
void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
- struct intel_engine_cs *ring)
+ struct drm_i915_gem_request *req)
{
- struct drm_i915_gem_request *req = intel_ring_get_request(ring);
+ struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
struct i915_vma *vma;
list_for_each_entry(vma, vmas, exec_list) {
@@ -1279,7 +1279,7 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
trace_i915_gem_ring_dispatch(params-request, params-dispatch_flags);
- i915_gem_execbuffer_move_to_active(vmas, ring);
+ i915_gem_execbuffer_move_to_active(vmas, params-request);
ret = i915_gem_execbuffer_retire_commands(params);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index efe970f..bc3809e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -712,7 +712,7 @@ int intel_execlists_submission(struct
i915_execbuffer_params *params,
trace_i915_gem_ring_dispatch(params-request, params-dispatch_flags);
- i915_gem_execbuffer_move_to_active(vmas, ring);
+ i915_gem_execbuffer_move_to_active(vmas, params-request);
return i915_gem_execbuffer_retire_commands(params);
}
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/53] drm/i915: Moved the for_each_ring loop outside of i915_gem_context_enable()
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The start of day context initialisation code in i915_gem_context_enable() loops
over each ring and calls the legacy switch context or the execlist init context
code as appropriate.
This patch moves the ring looping out of that function in to the top level
caller i915_gem_init_hw(). This means the a single pass can be made over all
rings doing the PPGTT, L3 remap and context initialisation of each ring
altogether.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_gem.c | 18 ++---
drivers/gpu/drm/i915/i915_gem_context.c | 32 +++
3 files changed, 23 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bfd7b47..653c82d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2989,7 +2989,7 @@ int __must_check i915_gem_context_init(struct drm_device
*dev);
void i915_gem_context_fini(struct drm_device *dev);
void i915_gem_context_reset(struct drm_device *dev);
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
-int i915_gem_context_enable(struct drm_i915_private *dev_priv);
+int i915_gem_context_enable(struct intel_engine_cs *ring);
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
int i915_switch_context(struct intel_engine_cs *ring,
struct intel_context *to);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9bc60d7..5850991 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4844,6 +4844,8 @@ i915_gem_init_hw(struct drm_device *dev)
*/
init_unused_rings(dev);
+ BUG_ON(!dev_priv-ring[RCS].default_context);
+
ret = i915_ppgtt_init_hw(dev);
if (ret) {
DRM_ERROR(PPGTT enable HW failed %d\n, ret);
@@ -4859,6 +4861,8 @@ i915_gem_init_hw(struct drm_device *dev)
/* Now it is safe to go back round and do everything else: */
for_each_ring(ring, dev_priv, i) {
+ WARN_ON(!ring-default_context);
+
if (ring-id == RCS) {
for (i = 0; i NUM_L3_SLICES(dev); i++)
i915_gem_l3_remap(ring, i);
@@ -4870,17 +4874,17 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_cleanup_ringbuffer(dev);
return ret;
}
- }
- ret = i915_gem_context_enable(dev_priv);
- if (ret ret != -EIO) {
- DRM_ERROR(Context enable failed %d\n, ret);
- i915_gem_cleanup_ringbuffer(dev);
+ ret = i915_gem_context_enable(ring);
+ if (ret ret != -EIO) {
+ DRM_ERROR(Context enable ring #%d failed %d\n, i,
ret);
+ i915_gem_cleanup_ringbuffer(dev);
- return ret;
+ return ret;
+ }
}
- return ret;
+ return 0;
}
int i915_gem_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8603bf4..dd83d61 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -403,32 +403,22 @@ void i915_gem_context_fini(struct drm_device *dev)
i915_gem_context_unreference(dctx);
}
-int i915_gem_context_enable(struct drm_i915_private *dev_priv)
+int i915_gem_context_enable(struct intel_engine_cs *ring)
{
- struct intel_engine_cs *ring;
- int ret, i;
-
- BUG_ON(!dev_priv-ring[RCS].default_context);
+ int ret;
if (i915.enable_execlists) {
- for_each_ring(ring, dev_priv, i) {
- if (ring-init_context) {
- ret = ring-init_context(ring,
- ring-default_context);
- if (ret) {
- DRM_ERROR(ring init context: %d\n,
- ret);
- return ret;
- }
- }
- }
+ if (ring-init_context == NULL)
+ return 0;
+ ret = ring-init_context(ring, ring-default_context);
} else
- for_each_ring(ring, dev_priv, i) {
- ret = i915_switch_context(ring, ring-default_context);
- if (ret)
- return ret;
- }
+ ret = i915_switch_context(ring, ring-default_context);
+
+ if (ret) {
+ DRM_ERROR(ring init context: %d\n, ret);
+
Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement
On Thu, 2015-03-05 at 14:06 +, Chris Wilson wrote: Probably unrelated. Look in dmesg dmesg is pretty muddy right now as I still have drm.debug=6 set. and /sys/class/drm/card0/error http://brian.interlinx.bc.ca/intel.debug.gz as it is currently. Or is it more useful if it's collected right after the Chrome UI hang? Cheers, b. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 19/53] drm/i915: Add explicit request management to i915_gem_init_hw()
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Now that a single per ring loop is being done for all the different
intialisation steps in i915_gem_init_hw(), it is possible to add proper request
management as well. The last remaining issue is that the context enable call
eventually ends up within *_render_state_init() and this does it's own private
_i915_add_request() call.
This patch adds explicit request creation and submission to the top level loop
and removes the add_request() from deep within the sub-functions. Note that the
old add_request() call was being passed a batch object. This is now explicitly
written to the request object instead. A warning has also been added to
i915_add_request() to ensure that there is never an attempt to add two batch
objects to a single request - e.g. because render_state_init() was called during
execbuffer processing.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |3 ++-
drivers/gpu/drm/i915/i915_gem.c | 18 ++
drivers/gpu/drm/i915/i915_gem_render_state.c |3 ++-
drivers/gpu/drm/i915/intel_lrc.c |8 +++-
4 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 653c82d..ea0da6b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2158,7 +2158,8 @@ struct drm_i915_gem_request {
struct intel_context *ctx;
struct intel_ringbuffer *ringbuf;
- /** Batch buffer related to this request if any */
+ /** Batch buffer related to this request if any (used for
+ error state dump only) */
struct drm_i915_gem_object *batch_obj;
/** Time at which this request was emitted, in jiffies. */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5850991..efed49a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2467,6 +2467,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
* inactive_list and lose its active reference. Hence we do not need
* to explicitly hold another reference here.
*/
+ WARN_ON(request-batch_obj obj);
request-batch_obj = obj;
if (!i915.enable_execlists) {
@@ -4861,8 +4862,16 @@ i915_gem_init_hw(struct drm_device *dev)
/* Now it is safe to go back round and do everything else: */
for_each_ring(ring, dev_priv, i) {
+ struct drm_i915_gem_request *req;
+
WARN_ON(!ring-default_context);
+ ret = dev_priv-gt.alloc_request(ring, ring-default_context,
req);
+ if (ret) {
+ i915_gem_cleanup_ringbuffer(dev);
+ return ret;
+ }
+
if (ring-id == RCS) {
for (i = 0; i NUM_L3_SLICES(dev); i++)
i915_gem_l3_remap(ring, i);
@@ -4871,6 +4880,7 @@ i915_gem_init_hw(struct drm_device *dev)
ret = i915_ppgtt_init_ring(ring);
if (ret ret != -EIO) {
DRM_ERROR(PPGTT enable ring #%d failed %d\n, i, ret);
+ i915_gem_request_unreference(req);
i915_gem_cleanup_ringbuffer(dev);
return ret;
}
@@ -4878,8 +4888,16 @@ i915_gem_init_hw(struct drm_device *dev)
ret = i915_gem_context_enable(ring);
if (ret ret != -EIO) {
DRM_ERROR(Context enable ring #%d failed %d\n, i,
ret);
+ i915_gem_request_unreference(req);
i915_gem_cleanup_ringbuffer(dev);
+ return ret;
+ }
+ ret = i915_add_request_no_flush(ring);
+ if (ret) {
+ DRM_ERROR(Add request ring #%d failed: %d\n, i, ret);
+ i915_gem_request_unreference(req);
+ i915_gem_cleanup_ringbuffer(dev);
return ret;
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index aba39c3..989476e 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -173,7 +173,8 @@ int i915_gem_render_state_init(struct intel_engine_cs *ring)
i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
- ret = __i915_add_request(ring, NULL, so.obj, true);
+ WARN_ON(ring-outstanding_lazy_request-batch_obj);
+ ring-outstanding_lazy_request-batch_obj = so.obj;
/* __i915_add_request moves object to inactive if it fails */
out:
i915_gem_render_state_fini(so);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
Re: [Intel-gfx] Preventing zero GPU virtual address allocation
On Thu, Mar 05, 2015 at 01:01:21PM +, Chris Wilson wrote: On Thu, Mar 05, 2015 at 01:52:51PM +0100, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 02:56:52AM +, Song, Ruiling wrote: Hi Daniel, OpenCL language support NULL pointer, using zero as the NULL pointer is the obvious way. That is zero will be treated as invalid address. Then it requires drm won't allocate zero to drm buffer. And David in CC list has help us make a patch, please see attached. The logic is only for ppgtt, and he said zero offset is used under ggtt. My question is what is offset zero used under ggtt? Will it make sure zero is not allocatable to drm buffer object? The code in i915_gem_execbuf.c already supports an optional bias to avoid putting a buffer into the first few kb. See __EXEC_OBJECT_NEEDS_BIAS. I suggest you expose this to userspace, which also address your issue that you didn't add an abi revision flag. A better API would be to allow userspace to request a buffer to place at a specific point in the VM and fail if that is not possible aka soft-pinning. Then OCL could assign a bo to offset 0 and detect writes to the NULL address if it so desired. With full-ppgtt, userspace can be sure of being able to evict any location in its VM and so also allows graceful detection of scenarios under which it cannot provide the NULL address safety feature (and opt not to run, or just bury its head in the sand). I recommended exposing the PIN_BIAS since that will work without full ppgtt too. And yeah for full ppgtt we could just use svm where userspace controls the address, but since that's still a bit out we might need a quick interim solution? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/53] drm/i915: Update the dispatch tracepoint to use params-request
On 19/02/2015 17:17, john.c.harri...@intel.com wrote: From: John Harrison john.c.harri...@intel.com Updated a couple of trace points to use the now cached request pointer rather than extracting it from the ring. For: VIZ-5115 Signed-off-by: John Harrison john.c.harri...@intel.com --- drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +- drivers/gpu/drm/i915/intel_lrc.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 10462f6..883cabd 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1277,7 +1277,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, return ret; } - trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), params-dispatch_flags); + trace_i915_gem_ring_dispatch(params-request, params-dispatch_flags); i915_gem_execbuffer_move_to_active(vmas, ring); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c3c783f..c42af08 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -712,7 +712,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params, if (ret) return ret; - trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), params-dispatch_flags); + trace_i915_gem_ring_dispatch(params-request, params-dispatch_flags); i915_gem_execbuffer_move_to_active(vmas, ring); Reviewed-by: Tomas Elf tomas@intel.com Thanks, Tomas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
As per the recommendation from PHY team, limit the max vco supported in CHV
to 6.48 GHz
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
* them would make no difference.
*/
.dot = { .min = 25000 * 5, .max = 54 * 5},
- .vco = { .min = 486, .max = 670 },
+ .vco = { .min = 486, .max = 648 },
I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.
Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco6.48
GHz.
I any case this seems OK, so
Acked-by: Ville Syrjälä ville.syrj...@linux.intel.com
This one doesn't apply any more ... still needed?
-Daniel
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 22, .max = 175 22 },
--
1.7.9.5
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--
Ville Syrjälä
Intel OTC
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
On Thu, Mar 05, 2015 at 04:52:56PM +0100, Daniel Vetter wrote:
On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
As per the recommendation from PHY team, limit the max vco supported in
CHV to 6.48 GHz
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
* them would make no difference.
*/
.dot = { .min = 25000 * 5, .max = 54 * 5},
- .vco = { .min = 486, .max = 670 },
+ .vco = { .min = 486, .max = 648 },
I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.
Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco6.48
GHz.
I any case this seems OK, so
Acked-by: Ville Syrjälä ville.syrj...@linux.intel.com
This one doesn't apply any more ... still needed?
Supposedly, yes.
--
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Intel OTC
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[Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
v4 : Fix feedfwd gain (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Signed-off-by: Ville Syrjala ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 14 ++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD(0 8)
#define DPIO_CHV_SECOND_MOD (1 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..c5a8725 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config-dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config-dpll.m2 22;
bestp1 = pipe_config-dpll.p1;
bestp2 = pipe_config-dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6164,12 +6166,16 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
1 DPIO_CHV_N_DIV_SHIFT);
/* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac)
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
/* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val = ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
+ dpio_val |= (2 DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ if (bestm2_frac)
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
On 3/3/2015 9:08 PM, Ville Syrjälä wrote:
On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote:
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches based on review by
Ville
v3: Addressed rest of the review comments. Clear out the old bits before
we modify those bits as part of RMW
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW9_CH0 0x8024
#define _CHV_PLL_DW9_CH1 0x81A4
#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 1)
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse 0 :
fine */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 15904a8..a6b5786 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2 DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
Missing
dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
here.
So I think to avoid such mistakes it's best to rewrite this too as:
val = read(PLL_DW9)
val = ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
val |= 0x5 DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT)
if (!bestm2_frac)
val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
write(PLL_DW9, val);
I will send v4 with this change and add your signed-off-by tag.
Thanks,
Vijay
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val = ~DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val = ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
/* Loop filter */
--
1.7.9.5
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[Intel-gfx] [PATCH 56/56] drm/i915: Update a bunch of LRC functions to take requests
From: John Harrison john.c.harri...@intel.com
A bunch of the low level LRC functions were passing around ringbuf and
ctx pairs. In a few cases, they took the r/c pair and a request as
well. This is all quite messy and unnecesary.
Updated those functions to just take the request structure.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 61 --
1 file changed, 26 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1fa36de..ce5c19a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -494,25 +494,20 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
((u32)ring-next_context_status_buffer 0x07) 8);
}
-static int execlists_context_queue(struct intel_engine_cs *ring,
- struct intel_context *to,
- u32 tail,
- struct drm_i915_gem_request *request)
+static int execlists_context_queue(struct drm_i915_gem_request *request)
{
+ struct intel_engine_cs *ring = request-ring;
struct drm_i915_gem_request *cursor;
struct drm_i915_private *dev_priv = ring-dev-dev_private;
unsigned long flags;
int num_elements = 0;
- if (to != ring-default_context)
- intel_lr_context_pin(ring, to);
-
- WARN_ON(!request);
- WARN_ON(to != request-ctx);
+ if (request-ctx != ring-default_context)
+ intel_lr_context_pin(ring, request-ctx);
i915_gem_request_reference(request);
- request-tail = tail;
+ request-tail = request-ringbuf-tail;
intel_runtime_pm_get(dev_priv);
@@ -529,7 +524,7 @@ static int execlists_context_queue(struct intel_engine_cs
*ring,
struct drm_i915_gem_request,
execlist_link);
- if (to == tail_req-ctx) {
+ if (request-ctx == tail_req-ctx) {
WARN(tail_req-elsp_submitted != 0,
More than 2 already-submitted reqs queued\n);
list_del(tail_req-execlist_link);
@@ -636,7 +631,7 @@ static int logical_ring_wait_request(struct
intel_ringbuffer *ringbuf,
/*
* intel_logical_ring_advance_and_submit() - advance the tail and submit the
workload
- * @ringbuf: Logical Ringbuffer to advance.
+ * @request: Request to advance the logical ringbuffer of.
*
* The tail is updated in our logical ringbuffer struct, not in the actual
context. What
* really happens during submission is that the context and current tail will
be placed
@@ -644,32 +639,29 @@ static int logical_ring_wait_request(struct
intel_ringbuffer *ringbuf,
* point, the tail *inside* the context is updated and the ELSP written to.
*/
static void
-intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
- struct intel_context *ctx,
- struct drm_i915_gem_request *request)
+intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
- struct intel_engine_cs *ring = ringbuf-ring;
+ struct intel_engine_cs *ring = request-ring;
- intel_logical_ring_advance(ringbuf);
+ intel_logical_ring_advance(request-ringbuf);
if (intel_ring_stopped(ring))
return;
- execlists_context_queue(ring, ctx, ringbuf-tail, request);
+ execlists_context_queue(request);
}
-static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
- struct intel_context *ctx,
+static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
int bytes)
{
- struct intel_engine_cs *ring = ringbuf-ring;
+ struct intel_engine_cs *ring = req-ring;
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_gem_request *local_req;
unsigned long end;
int ret;
- ret = logical_ring_wait_request(ringbuf, bytes);
+ ret = logical_ring_wait_request(req-ringbuf, bytes);
if (ret != -ENOSPC)
return ret;
@@ -686,10 +678,10 @@ static int logical_ring_wait_for_space(struct
intel_ringbuffer *ringbuf,
* Thus the request cannot be submitted via i915_add_request() and
* can not be waiting on by i915_gem_wait_request().
*/
- ret = dev_priv-gt.alloc_request(ring, ctx, local_req);
+ ret = dev_priv-gt.alloc_request(ring, req-ctx, local_req);
if (ret)
return ret;
- intel_logical_ring_advance_and_submit(ringbuf, ctx, local_req);
+ intel_logical_ring_advance_and_submit(local_req);
/* With GEM the hangcheck timer
[Intel-gfx] [PATCH 54/56] drm/i915: Rename 'do_execbuf' to 'execbuf_submit'
From: John Harrison john.c.harri...@intel.com
The submission portion of the execbuffer code path was abstracted into a
function pointer indirection as part of the legacy vs execlist work. The two
implementation functions are called 'i915_gem_ringbuffer_submission' and
'intel_execlists_submission' but the pointer was called 'do_execbuf'. There is
already a 'i915_gem_do_execbuffer' function (which is what calls the pointer
indirection). The name of the pointer is therefore considered to be backwards
and should be changed.
This patch renames it to 'execbuf_submit' which is hopefully a bit clearer.
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|6 +++---
drivers/gpu/drm/i915/i915_gem.c|4 ++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c |2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c9e569..4e9a350 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1793,9 +1793,9 @@ struct drm_i915_private {
int (*alloc_request)(struct intel_engine_cs *ring,
struct intel_context *ctx,
struct drm_i915_gem_request **req_out);
- int (*do_execbuf)(struct i915_execbuffer_params *params,
- struct drm_i915_gem_execbuffer2 *args,
- struct list_head *vmas);
+ int (*execbuf_submit)(struct i915_execbuffer_params *params,
+ struct drm_i915_gem_execbuffer2 *args,
+ struct list_head *vmas);
int (*init_rings)(struct drm_device *dev);
void (*cleanup_ring)(struct intel_engine_cs *ring);
void (*stop_ring)(struct intel_engine_cs *ring);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ecff3f7..27abc9d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4928,13 +4928,13 @@ int i915_gem_init(struct drm_device *dev)
if (!i915.enable_execlists) {
dev_priv-gt.alloc_request = intel_ring_alloc_request;
- dev_priv-gt.do_execbuf = i915_gem_ringbuffer_submission;
+ dev_priv-gt.execbuf_submit = i915_gem_ringbuffer_submission;
dev_priv-gt.init_rings = i915_gem_init_rings;
dev_priv-gt.cleanup_ring = intel_cleanup_ring_buffer;
dev_priv-gt.stop_ring = intel_stop_ring_buffer;
} else {
dev_priv-gt.alloc_request = intel_logical_ring_alloc_request;
- dev_priv-gt.do_execbuf = intel_execlists_submission;
+ dev_priv-gt.execbuf_submit = intel_execlists_submission;
dev_priv-gt.init_rings = intel_logical_rings_init;
dev_priv-gt.cleanup_ring = intel_logical_ring_cleanup;
dev_priv-gt.stop_ring = intel_logical_ring_stop;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index dfad66a..d969eb5 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1558,7 +1558,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params-batch_obj = batch_obj;
params-ctx = ctx;
- ret = dev_priv-gt.do_execbuf(params, args, eb-vmas);
+ ret = dev_priv-gt.execbuf_submit(params, args, eb-vmas);
err:
/*
--
1.7.9.5
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[Intel-gfx] [PATCH 55/56] drm/i915: Remove 'faked' request from LRC submission
From: John Harrison john.c.harri...@intel.com
The LRC submission code requires a request for tracking purposes. It does not
actually require that request to 'complete' it simply uses it for keeping hold
of reference counts on contexts and such like.
In the case where the ring buffer is completely full, the LRC code looks for a
pending request that would free up sufficient space upon completion and waits
for it. If no such request can be found it resorts to simply polling the free
space count until it is big enough. This situation should only occur when the
entire buffer is filled with the request currently being generated. I.e., the
user is trying to submit a single piece of work that is large than the ring
buffer itself (which should be impossible because very large batch buffers don't
consume any more ring buffer space). Before starting to poll, a submit call is
made to make sure that the currently queued up work in the buffer will actually
be submtted and thus the poll will eventually succeed.
The problem here is that the 'official' request cannot be used as that could
lead to multiple LRC submissions being tagged to a single request structure.
Instead, the code fakes up a private request structure and uses that.
This patch moves the faked request allocation higher up in the call stack to the
wait code itself (rather than being at the very lowest submission level). Thus
it is now obvious where the faked request is coming from and why it is
necessary. The patch also replaces it with a call to the official request
allocation code rather than attempting to duplicate that code. This becomes
especially important in the future when the request allocation changes to
accommodate a conversion to struct fence.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 45 ++
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 65eea51..1fa36de 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -507,23 +507,11 @@ static int execlists_context_queue(struct intel_engine_cs
*ring,
if (to != ring-default_context)
intel_lr_context_pin(ring, to);
- if (!request) {
- /*
-* If there isn't a request associated with this submission,
-* create one as a temporary holder.
-*/
- request = kzalloc(sizeof(*request), GFP_KERNEL);
- if (request == NULL)
- return -ENOMEM;
- request-ring = ring;
- request-ctx = to;
- kref_init(request-ref);
- request-uniq = dev_priv-request_uniq++;
- i915_gem_context_reference(request-ctx);
- } else {
- i915_gem_request_reference(request);
- WARN_ON(to != request-ctx);
- }
+ WARN_ON(!request);
+ WARN_ON(to != request-ctx);
+
+ i915_gem_request_reference(request);
+
request-tail = tail;
intel_runtime_pm_get(dev_priv);
@@ -677,6 +665,7 @@ static int logical_ring_wait_for_space(struct
intel_ringbuffer *ringbuf,
struct intel_engine_cs *ring = ringbuf-ring;
struct drm_device *dev = ring-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_i915_gem_request *local_req;
unsigned long end;
int ret;
@@ -684,8 +673,23 @@ static int logical_ring_wait_for_space(struct
intel_ringbuffer *ringbuf,
if (ret != -ENOSPC)
return ret;
- /* Force the context submission in case we have been skipping it */
- intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
+ /*
+* Force the context submission in case we have been skipping it.
+* This requires creating a place holder request so that the LRC
+* submission can be tracked. Note that if this point has been
+* reached then it is the current submission that is blocking the
+* driver and the only course of action is to do a partial send and
+* wait for it to complete.
+* Note also that because there is no space left in the ring, it is
+* not possible to write the request submission prologue (which does
+* things like update seqno values and trigger completion interrupts).
+* Thus the request cannot be submitted via i915_add_request() and
+* can not be waiting on by i915_gem_wait_request().
+*/
+ ret = dev_priv-gt.alloc_request(ring, ctx, local_req);
+ if (ret)
+ return ret;
+ intel_logical_ring_advance_and_submit(ringbuf, ctx, local_req);
/* With GEM the hangcheck timer should kick us out of the loop,
* leaving it early runs the risk of corrupting GEM state (due
@@ -717,6 +721,9 @@ static int
[Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches (Ville)
v3: Clear out the old bits before we modify those bits as RMW (Ville)
v4: Reset coarse threshold when M2 fraction is enabled (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
Signed-off-by: Ville Syrjala ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW9_CH0 0x8024
#define _CHV_PLL_DW9_CH1 0x81A4
#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 1)
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse 0 :
fine */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c5a8725..6c5a5a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6177,6 +6177,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val = ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
+ DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+ dpio_val |= (0x5 DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ if (!bestm2_frac)
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
loopfilter = 5 DPIO_CHV_PROP_COEFF_SHIFT |
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
On 3/3/2015 9:06 PM, Ville Syrjälä wrote:
On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote:
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 24 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD (0 8)
#define DPIO_CHV_SECOND_MOD (1 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config-dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config-dpll.m2 22;
bestp1 = pipe_config-dpll.p1;
bestp2 = pipe_config-dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val = ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+ dpio_val |= (2 DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val = ~DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
You're not writing the feedfwd gain here. The register docs list it as
'Feedforwad gain for fractional mode/SSC mode PLL'. The SSC part there
makes me think these bits might mean something even if the fractional
divider is not used.
At least I don't see any harm in setting it even if the fractional
divider is not used. So with that in mind I'd probably write this as
something like:
val = read(PLL_DW3)
val = ~(FRAC_DIV_EN | FEEDFWD_GAIN_MASK)
val |= 2 FEEDFWD_GAIN_SHIFT;
if (bestm2_trac)
val |= FRAC_DIV_EN;
write(PLL_DW3, val);
This should also make it less likely we will accidentally update
only one of the branches in the future when both need changing.
Makes sense. I will send v4 with this change and add your signed-off-by tag.
Thanks,
Vijay
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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[Intel-gfx] [PATCH 01/53] drm/i915: Remove ironlake rc6 support
From: John Harrison john.c.harri...@intel.com
Apparently, this has never worked reliably and is currently disabled. Also, the
gains are not particularly impressive. Thus rather than try to keep unused code
from decaying and having to update it for other driver changes, it was decided
to simply remove it.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 ---
drivers/gpu/drm/i915/i915_drv.h |3 -
drivers/gpu/drm/i915/intel_display.c |2 -
drivers/gpu/drm/i915/intel_drv.h |1 -
drivers/gpu/drm/i915/intel_pm.c | 155 --
5 files changed, 173 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 68a1e6e..18e4900 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1846,18 +1846,6 @@ static int i915_context_status(struct seq_file *m, void
*unused)
if (ret)
return ret;
- if (dev_priv-ips.pwrctx) {
- seq_puts(m, power context );
- describe_obj(m, dev_priv-ips.pwrctx);
- seq_putc(m, '\n');
- }
-
- if (dev_priv-ips.renderctx) {
- seq_puts(m, render context );
- describe_obj(m, dev_priv-ips.renderctx);
- seq_putc(m, '\n');
- }
-
list_for_each_entry(ctx, dev_priv-context_list, link) {
if (!i915.enable_execlists
ctx-legacy_hw_ctx.rcs_state == NULL)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 798fa88..05f106d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1053,9 +1053,6 @@ struct intel_ilk_power_mgmt {
int c_m;
int r_t;
-
- struct drm_i915_gem_object *pwrctx;
- struct drm_i915_gem_object *renderctx;
};
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5c35098..51f7ed4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13904,8 +13904,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_fbc_disable(dev);
- ironlake_teardown_rc6(dev);
-
mutex_unlock(dev-struct_mutex);
/* flush any delayed tasks or pending work */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f4305be..b793558 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1229,7 +1229,6 @@ void intel_enable_gt_powersave(struct drm_device *dev);
void intel_disable_gt_powersave(struct drm_device *dev);
void intel_suspend_gt_powersave(struct drm_device *dev);
void intel_reset_gt_powersave(struct drm_device *dev);
-void ironlake_teardown_rc6(struct drm_device *dev);
void gen6_update_ring_freq(struct drm_device *dev);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
void gen6_rps_boost(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 542cf68..0762572 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3539,41 +3539,6 @@ void intel_update_sprite_watermarks(struct drm_plane
*plane,
pixel_size, enabled, scaled);
}
-static struct drm_i915_gem_object *
-intel_alloc_context_page(struct drm_device *dev)
-{
- struct drm_i915_gem_object *ctx;
- int ret;
-
- WARN_ON(!mutex_is_locked(dev-struct_mutex));
-
- ctx = i915_gem_alloc_object(dev, 4096);
- if (!ctx) {
- DRM_DEBUG(failed to alloc power context, RC6 disabled\n);
- return NULL;
- }
-
- ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
- if (ret) {
- DRM_ERROR(failed to pin power context: %d\n, ret);
- goto err_unref;
- }
-
- ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
- if (ret) {
- DRM_ERROR(failed to set-domain on power context: %d\n, ret);
- goto err_unpin;
- }
-
- return ctx;
-
-err_unpin:
- i915_gem_object_ggtt_unpin(ctx);
-err_unref:
- drm_gem_object_unreference(ctx-base);
- return NULL;
-}
-
/**
* Lock protecting IPS related data structures
*/
@@ -4990,124 +4955,6 @@ static void valleyview_enable_rps(struct drm_device
*dev)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
-void ironlake_teardown_rc6(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev-dev_private;
-
- if (dev_priv-ips.renderctx) {
- i915_gem_object_ggtt_unpin(dev_priv-ips.renderctx);
- drm_gem_object_unreference(dev_priv-ips.renderctx-base);
- dev_priv-ips.renderctx = NULL;
- }
-
- if (dev_priv-ips.pwrctx) {
-
Re: [Intel-gfx] [PATCH 03/53] drm/i915: Cache ringbuf pointer in request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
In execlist mode, the ringbuf is a function of the ring and context whereas in
legacy mode, it is derived from the ring alone. Thus the calculation required to
determine the ringbuf pointer from the ring (and context) also needs to test
execlist mode or not. This is messy.
Further, the request structure holds a pointer to both the ring and the context
for which it was created. Thus, given a request, it is possible to derive the
ringbuf in either legacy or execlist mode. Hence it is necessary to pass just
the request in to all the low level functions rather than some combination of
request, ring, context and ringbuf. However, rather than recalculating it each
time, it is much simpler to just cache the ringbuf pointer in the request
structure itself.
Caching the pointer means the calculation is done one at request creation time
and all further code and simply read it directly from the request structure.
Caching the pointer means the calculation is done one at request
creation time and all further code and simply read it directly from the
request structure
Nitpick: Broken sentence, you might want to fix that. Aside from that,
no major problems with this patch.
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |3 ++-
drivers/gpu/drm/i915/i915_gem.c | 14 +-
drivers/gpu/drm/i915/intel_lrc.c|6 --
drivers/gpu/drm/i915/intel_ringbuffer.c |1 +
4 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2dedd43..ba09137 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2144,8 +2144,9 @@ struct drm_i915_gem_request {
/** Position in the ringbuffer of the end of the whole request */
u32 tail;
- /** Context related to this request */
+ /** Context and ring buffer related to this request */
struct intel_context *ctx;
+ struct intel_ringbuffer *ringbuf;
/** Batch buffer related to this request if any */
struct drm_i915_gem_object *batch_obj;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61134ab..7a0dc7c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2763,7 +2763,6 @@ i915_gem_retire_requests_ring(struct intel_engine_cs
*ring)
while (!list_empty(ring-request_list)) {
struct drm_i915_gem_request *request;
- struct intel_ringbuffer *ringbuf;
request = list_first_entry(ring-request_list,
struct drm_i915_gem_request,
@@ -2774,23 +2773,12 @@ i915_gem_retire_requests_ring(struct intel_engine_cs
*ring)
trace_i915_gem_request_retire(request);
- /* This is one of the few common intersection points
-* between legacy ringbuffer submission and execlists:
-* we need to tell them apart in order to find the correct
-* ringbuffer to which the request belongs to.
-*/
- if (i915.enable_execlists) {
- struct intel_context *ctx = request-ctx;
- ringbuf = ctx-engine[ring-id].ringbuf;
- } else
- ringbuf = ring-buffer;
-
/* We know the GPU must have read the request to have
* sent us the seqno + interrupt, so use the position
* of tail of the request to update the last known position
* of the GPU head.
*/
- ringbuf-last_retired_head = request-postfix;
+ request-ringbuf-last_retired_head = request-postfix;
i915_gem_free_request(request);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 637cbb7..f14b517 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -888,12 +888,14 @@ static int logical_ring_alloc_request(struct
intel_engine_cs *ring,
return ret;
}
- /* Hold a reference to the context this request belongs to
+ /*
+* Hold a reference to the context this request belongs to
* (we will need it when the time comes to emit/retire the
-* request).
+* request). Likewise, the ringbuff is useful to keep track of.
*/
request-ctx = ctx;
i915_gem_context_reference(request-ctx);
+ request-ringbuf = ctx-engine[ring-id].ringbuf;
ring-outstanding_lazy_request = request;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ca7de3d..7fd89e5 100644
---
Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement
On Tue, 2015-03-03 at 13:49 +, Chris Wilson wrote: It's an OR. The bug I am thinking about has a w/a in the ddx and a real fix in the kernel. Either one should do, and I think will resolve your issue. Yeah, upgrading to that newer Intel driver did seem to do the trick. I wonder if it's making https://code.google.com/p/chromium/issues/detail?id=463243 worse though since that problem seems to have gotten worse with the new driver. It didn't even really occur to me that that problem was related to my GPU driver but I've since put the same version of Chrome on my laptop with an nVidia Quadro and I have not see the same problem there (yet). Cheers, b. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
v2: Split the original changes into multiple smaller patches based on
review by Ville
v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.
v4: TDC target cnt is 10 bits and not 8 bits (Ville)
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..14b560b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6c5a5a9..3eb0946 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc-pipe;
int dpll_reg = DPLL(crtc-pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config-dpll.n;
bestm2_frac = pipe_config-dpll.m2 0x3f;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config-dpll.m2 22;
bestp1 = pipe_config-dpll.p1;
bestp2 = pipe_config-dpll.p2;
+ vco = pipe_config-dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6187,18 +6189,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 DPIO_CHV_PROP_COEFF_SHIFT |
- 2 DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco = 620) {
+ loopfilter |= (0x5 DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco = 648) {
+ loopfilter |= (0x4 DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val = ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+ dpio_val |= (tribuf_calcntr DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fix simple_return.cocci warnings
drivers/gpu/drm/i915/intel_ringbuffer.c:435:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Fengguang Wu fengguang...@intel.com --- intel_ringbuffer.c |6 +- 1 file changed, 1 insertion(+), 5 deletions(-) --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -432,11 +432,7 @@ gen8_render_ring_flush(struct intel_engi return ret; } - ret = gen8_emit_pipe_control(ring, flags, scratch_addr); - if (ret) - return ret; - - return 0; + return gen8_emit_pipe_control(ring, flags, scratch_addr); } static void ring_write_tail(struct intel_engine_cs *ring, ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915: Pass in plane state when (un)pinning frame buffers
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Plane state carries the rotation information which is needed for determining
the appropriate GGTT view type.
This just adds the parameter with the actual usage coming in future patches.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 18 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d1c6ef3..81072c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2247,6 +2247,7 @@ intel_fb_align_height(struct drm_device *dev, unsigned
int height,
int
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state,
struct intel_engine_cs *pipelined)
{
struct drm_device *dev = fb-dev;
@@ -2334,8 +2335,11 @@ err_interruptible:
return ret;
}
-static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
+static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state)
{
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+
WARN_ON(!mutex_is_locked(obj-base.dev-struct_mutex));
i915_gem_object_unpin_fence(obj);
@@ -9225,7 +9229,7 @@ static void intel_unpin_work_fn(struct work_struct
*__work)
enum pipe pipe = to_intel_crtc(work-crtc)-pipe;
mutex_lock(dev-struct_mutex);
- intel_unpin_fb_obj(intel_fb_obj(work-old_fb));
+ intel_unpin_fb_obj(work-old_fb, work-crtc-primary-state);
drm_gem_object_unreference(work-pending_flip_obj-base);
drm_framebuffer_unreference(work-old_fb);
@@ -9933,7 +9937,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
ring = dev_priv-ring[RCS];
}
- ret = intel_pin_and_fence_fb_obj(crtc-primary, fb, ring);
+ ret = intel_pin_and_fence_fb_obj(crtc-primary, fb,
+crtc-primary-state, ring);
if (ret)
goto cleanup_pending;
@@ -9973,7 +9978,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
return 0;
cleanup_unpin:
- intel_unpin_fb_obj(obj);
+ intel_unpin_fb_obj(fb, crtc-primary-state);
cleanup_pending:
atomic_dec(intel_crtc-unpin_work_count);
crtc-primary-fb = old_fb;
@@ -11928,7 +11933,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
if (ret)
DRM_DEBUG_KMS(failed to attach phys object\n);
} else {
- ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
+ ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
}
if (ret == 0)
@@ -11960,7 +11965,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
if (plane-type != DRM_PLANE_TYPE_CURSOR ||
!INTEL_INFO(dev)-cursor_needs_physical) {
mutex_lock(dev-struct_mutex);
- intel_unpin_fb_obj(obj);
+ intel_unpin_fb_obj(fb, old_state);
mutex_unlock(dev-struct_mutex);
}
}
@@ -13850,6 +13855,7 @@ void intel_modeset_gem_init(struct drm_device *dev)
if (intel_pin_and_fence_fb_obj(c-primary,
c-primary-fb,
+ c-primary-state,
NULL)) {
DRM_ERROR(failed to pin boot fb on pipe %d\n,
to_intel_crtc(c)-pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1677ea1..9b96d48 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -958,6 +958,7 @@ void intel_release_load_detect_pipe(struct drm_connector
*connector,
struct intel_load_detect_pipe *old);
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state,
struct intel_engine_cs *pipelined);
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 234a699..d8204ae 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -126,7 +126,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
}
/* Flush everything out, we'll be doing GTT only from now on */
- ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL);
+ ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL, NULL);
if (ret) {
[Intel-gfx] [PATCH v3 0/7] Skylake 90/270 display rotation
From: Tvrtko Ursulin tvrtko.ursu...@intel.com Display engine on Skylake can scan out specially prepared frame buffers rotated by 90 or 270 degrees. This adds partial support for this and will need some patches from Sonika to complete the feature. Going by looking pretty comment by Daniel Vetter (on IRC) I think this is now ready for detailed review. v2: * Individual review comments. * Main patch split into four smaller ones. v3: * Dropped the DRM core patch since it has been merged. * Refactored tile height helper a bit. * Moved rotated GGTT view code into i915_gem_gtt.c Tvrtko Ursulin (7): drm/i915/skl: Extract tile height code into a helper function drm/i915: Use GGTT view when (un)pinning objects to planes drm/i915: Pass in plane state when (un)pinning frame buffers drm/i915: Helper function to determine GGTT view from plane state drm/i915/skl: Support secondary (rotated) frame buffer mapping drm/i915/skl: Query display address through a wrapper drm/i915/skl: Take 90/270 rotation into account in watermark calculations drivers/gpu/drm/i915/i915_drv.h | 40 - drivers/gpu/drm/i915/i915_gem.c | 31 --- drivers/gpu/drm/i915/i915_gem_gtt.c | 116 - drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++ drivers/gpu/drm/i915/intel_display.c | 160 +++ drivers/gpu/drm/i915/intel_drv.h | 25 +- drivers/gpu/drm/i915/intel_fbdev.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 3 +- drivers/gpu/drm/i915/intel_pm.c | 18 +++- drivers/gpu/drm/i915/intel_sprite.c | 10 +-- 10 files changed, 353 insertions(+), 64 deletions(-) -- 2.3.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/skl: Extract tile height code into a helper function
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It will be used in a later patch and also convert all height parameters
from int to unsigned int.
v2: Rebased for fb modifiers.
v3: Fixed v2 rebase.
v4:
* Height should be unsigned int.
* Make it take pixel_format for consistency and simplicity.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com (v1)
---
drivers/gpu/drm/i915/intel_display.c | 43 +---
drivers/gpu/drm/i915/intel_drv.h | 7 +++---
2 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8e9e18c..bf389fc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2189,13 +2189,12 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
-int
-intel_fb_align_height(struct drm_device *dev, int height,
- uint32_t pixel_format,
- uint64_t fb_format_modifier)
+static unsigned int
+intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
+ uint64_t fb_format_modifier)
{
- int tile_height;
- uint32_t bits_per_pixel;
+ unsigned int tile_height;
+ uint32_t pixel_bytes;
switch (fb_format_modifier) {
case DRM_FORMAT_MOD_NONE:
@@ -2208,20 +2207,20 @@ intel_fb_align_height(struct drm_device *dev, int
height,
tile_height = 32;
break;
case I915_FORMAT_MOD_Yf_TILED:
- bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
- switch (bits_per_pixel) {
+ pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
+ switch (pixel_bytes) {
default:
- case 8:
+ case 1:
tile_height = 64;
break;
- case 16:
- case 32:
+ case 2:
+ case 4:
tile_height = 32;
break;
- case 64:
+ case 8:
tile_height = 16;
break;
- case 128:
+ case 16:
WARN_ONCE(1,
128-bit pixels are not supported for
display!);
tile_height = 16;
@@ -2234,7 +2233,15 @@ intel_fb_align_height(struct drm_device *dev, int height,
break;
}
- return ALIGN(height, tile_height);
+ return tile_height;
+}
+
+unsigned int
+intel_fb_align_height(struct drm_device *dev, unsigned int height,
+ uint32_t pixel_format, uint64_t fb_format_modifier)
+{
+ return ALIGN(height, intel_tile_height(dev, pixel_format,
+ fb_format_modifier));
}
int
@@ -6720,7 +6727,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
u32 val, base, offset;
int pipe = crtc-pipe, plane = crtc-plane;
int fourcc, pixel_format;
- int aligned_height;
+ unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
@@ -7758,7 +7765,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
u32 val, base, offset, stride_mult, tiling;
int pipe = crtc-pipe;
int fourcc, pixel_format;
- int aligned_height;
+ unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
@@ -7866,7 +7873,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
u32 val, base, offset;
int pipe = crtc-pipe;
int fourcc, pixel_format;
- int aligned_height;
+ unsigned int aligned_height;
struct drm_framebuffer *fb;
struct intel_framebuffer *intel_fb;
@@ -12791,7 +12798,7 @@ static int intel_framebuffer_init(struct drm_device
*dev,
struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_i915_gem_object *obj)
{
- int aligned_height;
+ unsigned int aligned_height;
int ret;
u32 pitch_limit, stride_alignment;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6633674..1677ea1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -900,9 +900,10 @@ void intel_frontbuffer_flip(struct drm_device *dev,
intel_frontbuffer_flush(dev, frontbuffer_bits);
}
-int intel_fb_align_height(struct drm_device *dev, int height,
- uint32_t pixel_format,
- uint64_t fb_format_modifier);
+unsigned int intel_fb_align_height(struct drm_device *dev,
+ unsigned int height,
+ uint32_t pixel_format,
+
[Intel-gfx] [PATCH 6/7] drm/i915/skl: Query display address through a wrapper
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND. (Chris Wilson)
v4:
* Extracted 90/270 rotation check into a helper function. (Michel Thierry)
For: VIZ-4545
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 24 ++--
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu/drm/i915/intel_sprite.c | 5 -
5 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b04b07d..e12b6f3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2879,6 +2879,13 @@ i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
}
static inline unsigned long
+i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view)
+{
+ return i915_gem_obj_offset_view(obj, i915_obj_to_ggtt(obj), view);
+}
+
+static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ecedda5..ba99bfe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5181,8 +5181,8 @@ unsigned long i915_gem_obj_offset_view(struct
drm_i915_gem_object *o,
return vma-node.start;
}
- WARN(1, %s vma for this object not found.\n,
-i915_is_ggtt(vm) ? global : ppgtt);
+ WARN(1, %s vma for this object not found. (view=%u)\n,
+i915_is_ggtt(vm) ? global : ppgtt, view);
return -1;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9867f55..c7ead35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2258,8 +2258,7 @@ int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
if (!plane_state)
return 0;
- if (!(plane_state-rotation
- (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
+ if (!intel_rotation_90_or_270(plane_state-rotation))
return 0;
*view = rotated_view;
@@ -2864,6 +2863,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
uint64_t fb_modifier,
}
}
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj)
+{
+ enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
+
+ if (intel_rotation_90_or_270(intel_plane-base.state-rotation))
+ view = I915_GGTT_VIEW_ROTATED;
+
+ return i915_gem_obj_ggtt_offset_view(obj, view);
+}
+
static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y)
@@ -2874,6 +2884,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_i915_gem_object *obj;
int pipe = intel_crtc-pipe;
u32 plane_ctl, stride_div;
+ unsigned long surf_addr;
if (!intel_crtc-primary_enabled) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2940,11 +2951,12 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb-modifier[0],
fb-pixel_format);
+ surf_addr = intel_plane_obj_offset(to_intel_plane(crtc-primary), obj);
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
DRM_DEBUG_KMS(Writing base %08lX %d,%d,%d,%d pitch=%d\n,
- i915_gem_obj_ggtt_offset(obj),
+ surf_addr,
x, y, fb-width, fb-height,
fb-pitches[0]);
@@ -2954,7 +2966,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
(intel_crtc-config-pipe_src_h - 1) 16 |
(intel_crtc-config-pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), fb-pitches[0] / stride_div);
- I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
+ I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -9987,8 +,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work-gtt_offset =
- i915_gem_obj_ggtt_offset(obj) + intel_crtc-dspaddr_offset;
+
[Intel-gfx] [PATCH 5/7] drm/i915/skl: Support secondary (rotated) frame buffer mapping
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
90/270 rotated scanout needs a rotated GTT view of the framebuffer.
This is put in a separate VMA with a dedicated ggtt view and wired such that
it is created when a framebuffer is pinned to a 90/270 rotated plane.
Rotation is only possible with Yb/Yf buffers and error is propagated to
user space in case of a mismatch.
Special rotated page view is constructed at the VMA creation time by
borrowing the DMA addresses from obj-pages.
v2:
* Do not bother with pages for rotated sg list, just populate the DMA
addresses. (Daniel Vetter)
* Checkpatch cleanup.
v3:
* Rebased on top of new plane handling (create rotated mapping when
setting the rotation property).
* Unpin rotated VMA on unpinning from display plane.
* Simplify rotation check using bitwise AND. (Chris Wilson)
v4:
* Fix unpinning of optional rotated mapping so it is really considered
to be optional.
v5:
* Rebased for fb modifier changes.
* Rebased for atomic commit.
* Only pin needed view for display. (Ville Syrjälä, Daniel Vetter)
v6:
* Rebased after preparatory work has been extracted out. (Daniel Vetter)
v7:
* Slightly simplified tiling geometry calculation.
* Moved rotated GGTT view implementation into i915_gem_gtt.c (Daniel Vetter)
For: VIZ-4726
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com (v4)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 116 ++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 12
drivers/gpu/drm/i915/intel_display.c | 29 -
drivers/gpu/drm/i915/intel_drv.h | 4 ++
4 files changed, 157 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 74df3d1..084aac1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2372,14 +2372,121 @@ i915_gem_obj_lookup_or_create_vma_view(struct
drm_i915_gem_object *obj,
return vma;
}
+static
+void rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
+ struct sg_table *st)
+{
+ unsigned int column, row;
+ unsigned int src_idx;
+ struct scatterlist *sg = st-sgl;
+
+ st-nents = 0;
+
+ for (column = 0; column width; column++) {
+ src_idx = width * (height - 1) + column;
+ for (row = 0; row height; row++) {
+ st-nents++;
+ /* We don't need the pages, but need to initialize
+* the entries so the sg list can be happily traversed.
+* The only thing we need are DMA addresses.
+*/
+ sg_set_page(sg, NULL, PAGE_SIZE, 0);
+ sg_dma_address(sg) = in[src_idx];
+ sg_dma_len(sg) = PAGE_SIZE;
+ sg = sg_next(sg);
+ src_idx -= width;
+ }
+ }
+}
+
+static
+struct sg_table *intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
+ struct drm_i915_gem_object *obj)
+{
+ struct drm_device *dev = obj-base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct i915_address_space *ggtt = dev_priv-gtt.base;
+ struct intel_rotation_info *rot_info = ggtt_view-rotation_info;
+ unsigned long size, pages, rot_pages;
+ struct sg_page_iter sg_iter;
+ unsigned long i;
+ dma_addr_t *page_addr_list;
+ struct sg_table *st;
+ unsigned int tile_pitch, tile_height;
+ unsigned int width_pages, height_pages;
+ int ret = ENOMEM;
+
+ pages = i915_gem_obj_size(obj, ggtt) / PAGE_SIZE;
+
+ /* Calculate tiling geometry. */
+ tile_height = intel_tile_height(dev, rot_info-pixel_format,
+ rot_info-fb_modifier);
+ tile_pitch = PAGE_SIZE / tile_height;
+ width_pages = DIV_ROUND_UP(rot_info-pitch, tile_pitch);
+ height_pages = DIV_ROUND_UP(rot_info-height, tile_height);
+ rot_pages = width_pages * height_pages;
+ size = rot_pages * PAGE_SIZE;
+
+ /* Allocate a temporary list of source pages for random access. */
+ page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t));
+ if (!page_addr_list)
+ return ERR_PTR(ret);
+
+ /* Allocate target SG list. */
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ goto err_st_alloc;
+
+ ret = sg_alloc_table(st, rot_pages, GFP_KERNEL);
+ if (ret)
+ goto err_sg_alloc;
+
+ /* Populate source page list from the object. */
+ i = 0;
+ for_each_sg_page(obj-pages-sgl, sg_iter, obj-pages-nents, 0) {
+ page_addr_list[i] = sg_page_iter_dma_address(sg_iter);
+ i++;
+ }
+
+ /* Rotate the pages. */
+
[Intel-gfx] [PATCH 7/7] drm/i915/skl: Take 90/270 rotation into account in watermark calculations
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
v2: Pass in rotation info to sprite plane updates as well.
v3: Use helper to determine 90/270 rotation. (Michel Thierry)
v4: Rebased for fb modifiers and atomic changes.
For: VIZ-4546
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Reviewed-by: Michel Thierry michel.thie...@intel.com (v3)
---
drivers/gpu/drm/i915/intel_display.c | 27 +++
drivers/gpu/drm/i915/intel_drv.h | 4
drivers/gpu/drm/i915/intel_pm.c | 18 +-
drivers/gpu/drm/i915/intel_sprite.c | 5 +
4 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c7ead35..6425f31 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11942,6 +11942,28 @@ static void intel_shared_dpll_init(struct drm_device
*dev)
}
/**
+ * intel_wm_need_update - Check whether watermarks need updating
+ * @plane: drm plane
+ * @state: new plane state
+ *
+ * Check current plane state versus the new one to determine whether
+ * watermarks need to be recalculated.
+ *
+ * Returns true or false.
+ */
+bool intel_wm_need_update(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ /* Update watermarks on tiling changes. */
+ if (!plane-state-fb || !state-fb ||
+ plane-state-fb-modifier[0] != state-fb-modifier[0] ||
+ plane-state-rotation != state-rotation)
+ return true;
+
+ return false;
+}
+
+/**
* intel_prepare_plane_fb - Prepare fb for usage on plane
* @plane: drm plane to prepare for
* @fb: framebuffer to prepare for presentation
@@ -12087,10 +12109,7 @@ intel_check_primary_plane(struct drm_plane *plane,
intel_crtc-atomic.update_fbc = true;
- /* Update watermarks on tiling changes. */
- if (!plane-state-fb || !state-base.fb ||
- plane-state-fb-modifier[0] !=
- state-base.fb-modifier[0])
+ if (intel_wm_need_update(plane, state-base))
intel_crtc-atomic.update_wm = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d57b9b7..d03d3bd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -501,6 +501,7 @@ struct intel_plane_wm_parameters {
bool enabled;
bool scaled;
u64 tiling;
+ unsigned int rotation;
};
struct intel_plane {
@@ -993,6 +994,9 @@ intel_rotation_90_or_270(unsigned int rotation)
return rotation (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
}
+bool intel_wm_need_update(struct drm_plane *plane,
+ struct drm_plane_state *state);
+
/* shared dpll functions */
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e710b43..49e7d4e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2712,6 +2712,7 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
*/
if (fb)
p-plane[0].tiling = fb-modifier[0];
+ p-plane[0].rotation = crtc-primary-state-rotation;
p-cursor.enabled = true;
p-cursor.bytes_per_pixel = 4;
@@ -2761,7 +2762,21 @@ static bool skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (p_params-tiling == I915_FORMAT_MOD_Y_TILED ||
p_params-tiling == I915_FORMAT_MOD_Yf_TILED) {
- uint32_t y_tile_minimum = plane_blocks_per_line * 4;
+ uint32_t min_scanlines = 4;
+ uint32_t y_tile_minimum;
+ if (intel_rotation_90_or_270(p_params-rotation)) {
+ switch (p_params-bytes_per_pixel) {
+ case 1:
+ min_scanlines = 16;
+ break;
+ case 2:
+ min_scanlines = 8;
+ break;
+ case 8:
+ WARN(1, Unsupported pixel depth for rotation);
+ };
+ }
+ y_tile_minimum = plane_blocks_per_line * min_scanlines;
selected_result = max(method2, y_tile_minimum);
} else {
if ((ddb_allocation / plane_blocks_per_line) = 1)
@@ -3221,6 +3236,7 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
*/
if (fb)
intel_plane-wm.tiling = fb-modifier[0];
+ intel_plane-wm.rotation = plane-state-rotation;
skl_update_wm(crtc);
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
[Intel-gfx] [PATCH 2/7] drm/i915: Use GGTT view when (un)pinning objects to planes
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
To support frame buffer rotation we need to be able to pass on the information
on what kind of GGTT view is required for display.
This patch just adds the parameter and makes all the callers default to the
normal view.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 33 +
drivers/gpu/drm/i915/i915_gem.c | 27 +--
drivers/gpu/drm/i915/intel_display.c | 7 ---
drivers/gpu/drm/i915/intel_overlay.c | 3 ++-
4 files changed, 52 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b384b72..b04b07d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2761,8 +2761,10 @@ i915_gem_object_set_to_cpu_domain(struct
drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
-struct intel_engine_cs *pipelined);
-void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
+struct intel_engine_cs *pipelined,
+const struct i915_ggtt_view *view);
+void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view
*view);
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align);
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
@@ -2831,7 +2833,13 @@ i915_gem_obj_lookup_or_create_vma(struct
drm_i915_gem_object *obj,
i915_ggtt_view_normal);
}
-struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
+struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view);
+static inline
+struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
+{
+ return i915_gem_obj_to_ggtt_view(obj, I915_GGTT_VIEW_NORMAL);
+}
static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
struct i915_vma *vma;
list_for_each_entry(vma, obj-vma_list, vma_link)
@@ -2885,13 +2893,30 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
alignment, flags | PIN_GLOBAL);
}
+static inline int __must_check
+i915_gem_obj_ggtt_pin_view(struct drm_i915_gem_object *obj,
+ uint32_t alignment,
+ unsigned flags,
+ const struct i915_ggtt_view *ggtt_view)
+{
+ return i915_gem_object_pin_view(obj, i915_obj_to_ggtt(obj),
+ alignment, flags | PIN_GLOBAL,
+ ggtt_view);
+}
+
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}
-void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
+void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
+enum i915_ggtt_view_type view);
+static inline void
+i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
+{
+ i915_gem_object_ggtt_unpin_view(obj, I915_GGTT_VIEW_NORMAL);
+}
/* i915_gem_context.c */
int __must_check i915_gem_context_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3831cc0..ecedda5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3951,7 +3951,8 @@ static bool is_pin_display(struct drm_i915_gem_object
*obj)
int
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
-struct intel_engine_cs *pipelined)
+struct intel_engine_cs *pipelined,
+const struct i915_ggtt_view *view)
{
u32 old_read_domains, old_write_domain;
bool was_pin_display;
@@ -3987,7 +3988,9 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
* (e.g. libkms for the bootup splash), we have to ensure that we
* always use map_and_fenceable for all scanout buffers.
*/
- ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
+ ret = i915_gem_obj_ggtt_pin_view(obj, alignment,
+view-type == I915_GGTT_VIEW_NORMAL ?
+PIN_MAPPABLE : 0, view);
if (ret)
goto err_unpin_display;
@@ -4015,9 +4018,11 @@ err_unpin_display:
}
void
-i915_gem_object_unpin_from_display_plane(struct
[Intel-gfx] [PATCH 4/7] drm/i915: Helper function to determine GGTT view from plane state
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
For now only default implementation defaulting to normal view.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 81072c4..8157999 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2244,6 +2244,16 @@ intel_fb_align_height(struct drm_device *dev, unsigned
int height,
fb_format_modifier));
}
+static
+int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
+ struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state)
+{
+ *view = i915_ggtt_view_normal;
+
+ return 0;
+}
+
int
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
@@ -2253,6 +2263,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_device *dev = fb-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_ggtt_view view;
u32 alignment;
int ret;
@@ -2289,6 +2300,10 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
return -EINVAL;
}
+ ret = intel_fill_fb_ggtt_view(view, fb, plane_state);
+ if (ret 0)
+ return ret;
+
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
* we should always have valid PTE following the scanout preventing
@@ -2308,7 +2323,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
dev_priv-mm.interruptible = false;
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
- i915_ggtt_view_normal);
+ view);
if (ret)
goto err_interruptible;
@@ -2328,7 +2343,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
return 0;
err_unpin:
- i915_gem_object_unpin_from_display_plane(obj, i915_ggtt_view_normal);
+ i915_gem_object_unpin_from_display_plane(obj, view);
err_interruptible:
dev_priv-mm.interruptible = true;
intel_runtime_pm_put(dev_priv);
@@ -2339,11 +2354,16 @@ static void intel_unpin_fb_obj(struct drm_framebuffer
*fb,
const struct drm_plane_state *plane_state)
{
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_ggtt_view view;
+ int ret;
WARN_ON(!mutex_is_locked(obj-base.dev-struct_mutex));
+ ret = intel_fill_fb_ggtt_view(view, fb, plane_state);
+ WARN_ONCE(ret 0, Couldn't get view from plane state!);
+
i915_gem_object_unpin_fence(obj);
- i915_gem_object_unpin_from_display_plane(obj, i915_ggtt_view_normal);
+ i915_gem_object_unpin_from_display_plane(obj, view);
}
/* Computes the linear offset to the base tile and adjusts x, y. bytes per
pixel
--
2.3.0
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH 1/3] drm/i915/skl: Allow universal planes to position
Signed-off-by: Sonika Jindal sonika.jin...@intel.com --- drivers/gpu/drm/i915/intel_display.c |7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 437a679..e1b0c4d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12183,16 +12183,21 @@ intel_check_primary_plane(struct drm_plane *plane, struct drm_rect *dest = state-dst; struct drm_rect *src = state-src; const struct drm_rect *clip = state-clip; + bool can_position = false; int ret; crtc = crtc ? crtc : plane-crtc; intel_crtc = to_intel_crtc(crtc); + if (INTEL_INFO(dev)-gen = 9) + can_position = true; + ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, - false, true, state-visible); + can_position, true, + state-visible); if (ret) return ret; -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915/skl: Updated the gen6_init_rps_frequencies function
On Thu, 2015-03-05 at 12:14 +0200, Ville Syrjälä wrote:
On Thu, Feb 26, 2015 at 06:19:39PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL the frequency is specified in units of 16.66 MHZ, barring the
RP_STATE_CAP(0x5998) register, which still reports frequency in units
of 50 MHZ. So an extra conversion is required in gen6_init_rps_frequencies
function for SKL, to store the frequency values as per the actual hardware
unit.
Signed-off-by: Akash Goel akash.g...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index 1b36d0e..9dcfca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4032,6 +4032,13 @@ static void gen6_init_rps_frequencies(struct
drm_device *dev)
dev_priv-rps.rp0_freq = (rp_state_cap 0) 0xff;
dev_priv-rps.rp1_freq = (rp_state_cap 8) 0xff;
dev_priv-rps.min_freq = (rp_state_cap 16) 0xff;
+ if (IS_SKYLAKE(dev)) {
+ /* Store the frequency values in 16.66 MHZ units, which is
+ the natural hardware unit for SKL */
+ dev_priv-rps.rp0_freq /= GEN9_FREQ_SCALER;
+ dev_priv-rps.rp1_freq /= GEN9_FREQ_SCALER;
+ dev_priv-rps.min_freq /= GEN9_FREQ_SCALER;
+ }
Shouldn't these be multiplied instead of divided?
So sorry for this blooper, thanks for spotting it.
Did it correctly in debugfs but faltered here.
/* hw_max = RP0 until we check for overclocking */
dev_priv-rps.max_freq = dev_priv-rps.rp0_freq;
--
1.9.2
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Re: [Intel-gfx] [PATCH 4/8] drm/i915/skl: Updated the gen6_set_rps function
On Thu, Feb 26, 2015 at 06:19:40PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.
Signed-off-by: Akash Goel akash.g...@intel.com
A bit hard to see since the GEN9_FREQUENCY() define was added in another
patch, but checking that against the spec tells me the shift is correct.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dcfca6..339a034 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3798,7 +3798,10 @@ static void gen6_set_rps(struct drm_device *dev, u8
val)
if (val != dev_priv-rps.cur_freq) {
gen6_set_rps_thresholds(dev_priv, val);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_GEN9(dev))
+ I915_WRITE(GEN6_RPNSWREQ,
+GEN9_FREQUENCY(val));
+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
I915_WRITE(GEN6_RPNSWREQ,
HSW_FREQUENCY(val));
else
--
1.9.2
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--
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Intel OTC
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Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement
On Thu, Mar 05, 2015 at 09:04:54AM -0500, Brian J. Murrell wrote: On Tue, 2015-03-03 at 13:49 +, Chris Wilson wrote: It's an OR. The bug I am thinking about has a w/a in the ddx and a real fix in the kernel. Either one should do, and I think will resolve your issue. Yeah, upgrading to that newer Intel driver did seem to do the trick. I wonder if it's making https://code.google.com/p/chromium/issues/detail?id=463243 worse though since that problem seems to have gotten worse with the new driver. Probably unrelated. Look in dmesg and /sys/class/drm/card0/error for information we need to begin diagnosing the problem. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/53] drm/i915: Remove ironlake rc6 support
On Thu, Mar 05, 2015 at 02:03:03PM +, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Apparently, this has never worked reliably and is currently disabled. Also,
the
gains are not particularly impressive. Thus rather than try to keep unused
code
from decaying and having to update it for other driver changes, it was decided
to simply remove it.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 ---
drivers/gpu/drm/i915/i915_drv.h |3 -
drivers/gpu/drm/i915/intel_display.c |2 -
drivers/gpu/drm/i915/intel_drv.h |1 -
drivers/gpu/drm/i915/intel_pm.c | 155
--
5 files changed, 173 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 68a1e6e..18e4900 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1846,18 +1846,6 @@ static int i915_context_status(struct seq_file *m,
void *unused)
if (ret)
return ret;
- if (dev_priv-ips.pwrctx) {
- seq_puts(m, power context );
- describe_obj(m, dev_priv-ips.pwrctx);
- seq_putc(m, '\n');
- }
-
- if (dev_priv-ips.renderctx) {
- seq_puts(m, render context );
- describe_obj(m, dev_priv-ips.renderctx);
- seq_putc(m, '\n');
- }
-
list_for_each_entry(ctx, dev_priv-context_list, link) {
if (!i915.enable_execlists
ctx-legacy_hw_ctx.rcs_state == NULL)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 798fa88..05f106d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1053,9 +1053,6 @@ struct intel_ilk_power_mgmt {
int c_m;
int r_t;
-
- struct drm_i915_gem_object *pwrctx;
- struct drm_i915_gem_object *renderctx;
};
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5c35098..51f7ed4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13904,8 +13904,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
intel_fbc_disable(dev);
- ironlake_teardown_rc6(dev);
-
mutex_unlock(dev-struct_mutex);
/* flush any delayed tasks or pending work */
diff --git a/drivers/gpu/drm/i915/intel_drv.h
b/drivers/gpu/drm/i915/intel_drv.h
index f4305be..b793558 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1229,7 +1229,6 @@ void intel_enable_gt_powersave(struct drm_device *dev);
void intel_disable_gt_powersave(struct drm_device *dev);
void intel_suspend_gt_powersave(struct drm_device *dev);
void intel_reset_gt_powersave(struct drm_device *dev);
-void ironlake_teardown_rc6(struct drm_device *dev);
void gen6_update_ring_freq(struct drm_device *dev);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
void gen6_rps_boost(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 542cf68..0762572 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3539,41 +3539,6 @@ void intel_update_sprite_watermarks(struct drm_plane
*plane,
pixel_size, enabled, scaled);
}
-static struct drm_i915_gem_object *
-intel_alloc_context_page(struct drm_device *dev)
-{
- struct drm_i915_gem_object *ctx;
- int ret;
-
- WARN_ON(!mutex_is_locked(dev-struct_mutex));
-
- ctx = i915_gem_alloc_object(dev, 4096);
- if (!ctx) {
- DRM_DEBUG(failed to alloc power context, RC6 disabled\n);
- return NULL;
- }
-
- ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
- if (ret) {
- DRM_ERROR(failed to pin power context: %d\n, ret);
- goto err_unref;
- }
-
- ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
- if (ret) {
- DRM_ERROR(failed to set-domain on power context: %d\n, ret);
- goto err_unpin;
- }
-
- return ctx;
-
-err_unpin:
- i915_gem_object_ggtt_unpin(ctx);
-err_unref:
- drm_gem_object_unreference(ctx-base);
- return NULL;
-}
-
/**
* Lock protecting IPS related data structures
*/
@@ -4990,124 +4955,6 @@ static void valleyview_enable_rps(struct drm_device
*dev)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
-void ironlake_teardown_rc6(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = dev-dev_private;
-
- if (dev_priv-ips.renderctx) {
- i915_gem_object_ggtt_unpin(dev_priv-ips.renderctx);
-
Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Support for 90/270 rotation
On Thu, Mar 05, 2015 at 03:08:17PM +0200, Ville Syrjälä wrote: On Thu, Mar 05, 2015 at 01:56:53PM +0100, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 02:51:28PM +0530, Sonika Jindal wrote: @@ -1519,16 +1550,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) goto out; } - if (!dev-mode_config.rotation_property) - dev-mode_config.rotation_property = - drm_mode_create_rotation_property(dev, - BIT(DRM_ROTATE_0) | - BIT(DRM_ROTATE_180)); - - if (dev-mode_config.rotation_property) - drm_object_attach_property(intel_plane-base.base, -dev-mode_config.rotation_property, -state-base.rotation); + intel_create_rotation_property(dev, intel_plane); I think back from the original rotation work we've had the leftover task to move this into common code so that we do create the property just once without this check. I think this should be done now. Someone should also make it so we can again have different supported rotation bits on different planes. I'll have need for it on CHV I think. plane-atomic_check just needs to reject them. Tbh I'm not sold on the value of trying to tell userspace which rotation works and which doesnt - generic userspace won't learn about y-tiling requirements either so this feels a bit pointless tbh. And rejecting stuff in atomic_check is what it's for. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/53] drm/i915: Remove ironlake rc6 support
On 05/03/2015 15:22, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 02:03:03PM +, john.c.harri...@intel.com wrote: From: John Harrison john.c.harri...@intel.com Apparently, this has never worked reliably and is currently disabled. Also, the gains are not particularly impressive. Thus rather than try to keep unused code from decaying and having to update it for other driver changes, it was decided to simply remove it. For: VIZ-5115 Signed-off-by: John Harrison john.c.harri...@intel.com Queued for -next, thanks for the patch. -Daniel Can you hold off merging any of the other patches in the series for the moment. Tomas Elf is currently posting review comments, some with R-B some with change requests. Some of the re-work either for his comments or for yours causes changes which ripple through a number of the patches in the series. So I would like to repost the whole set once all the comments have been addressed. Otherwise, it all just gets far too messy as to which patches have or haven't been updated, what needs re-merging, which version is which, etc. Thanks, John. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/51] drm/i915: Add return code check to i915_gem_execbuffer_retire_commands()
On Thu, Mar 05, 2015 at 03:06:42PM +, John Harrison wrote: On 05/03/2015 14:44, Daniel Vetter wrote: Imo reserving a bit of ring space for each add_request should be solid. Userspace uses the exact same reservation logic for adding end-of-batch workarounds. The only thing needed to make this solid is to WARN if add_request ends up using more ring space than what we've reserved (not just when it actually runs out, that obviously doesn't happen often enough for testing). The problem is that there could be multiple requests being processed in parallel. This is especially true with the scheduler. Userland could submit a whole stream of batches that all get queued up in the scheduler. Only later do they get submitted to the hardware. The request must be allocated up front because there is no other means of tracking them. But reserving space at that point won't work because you either end up reserving massive amounts of space if the reserve is cumulative, or not enough if only one slot is reserved. At least with execlist we don't have that problem really since writing the ringbuffer is done synchronously and directly. For the legacy scheduler I expect that we won't do any of the ringbuf writes directly and instead that's all done by the scheduler asynchronously. So this should just be an issue while we are converting to the scheduler or on platforms that will never have one. And imo the request ringbuf reservation is the solution with the simplest impact on the design. Everything else just readds olr through the backdoor, which is kinda what we wanted to avoid from an accounting pov. Because then you have again some random request outstanding which scoops up everything it encounters. Not quite. The difference is that with something like an outstanding failed request rather than a lazy one, there is still the segregation of work. The failed request will be posted and added to the request list in its entirety before a new request is allocated and used for the new work. Well history lesson, but that's exactly how olr started out. Then the hydra grew heads to no end. That's why I don't want to go down this road again, since I've been on that trip the past 3 years ;-) And since your motivation for olr light is exactly the one I provided 3 years ago to get my patch in I think history repeating is likely. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix simple_return.cocci warnings
On Thu, Mar 05, 2015 at 10:03:08PM +0800, kbuild test robot wrote: drivers/gpu/drm/i915/intel_ringbuffer.c:435:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Fengguang Wu fengguang...@intel.com Queued for -next, thanks for the patch. -Daniel --- intel_ringbuffer.c |6 +- 1 file changed, 1 insertion(+), 5 deletions(-) --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -432,11 +432,7 @@ gen8_render_ring_flush(struct intel_engi return ret; } - ret = gen8_emit_pipe_control(ring, flags, scratch_addr); - if (ret) - return ret; - - return 0; + return gen8_emit_pipe_control(ring, flags, scratch_addr); } static void ring_write_tail(struct intel_engine_cs *ring, -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/53] drm/i915: Add request to execbuf params and add explicit cleanup
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Rather than just having a local request variable in the execbuff code, the
request pointer is now stored in the execbuff params structure. Also added
explicit cleanup of the request (plus wiping the OLR to match) in the error
case. This means that the execbuff code is no longer dependent upon the OLR
keeping track of the request so as to not leak it when things do go wrong. Note
that in the success case, the i915_add_request() at the end of the submission
function will tidy up the request and clear the OLR.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 +++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90223f208..678b190 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1653,6 +1653,7 @@ struct i915_execbuffer_params {
struct intel_engine_cs *ring;
struct drm_i915_gem_object *batch_obj;
struct intel_context*ctx;
+ struct drm_i915_gem_request *request;
};
struct drm_i915_private {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 37dcc6f..10462f6 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1353,7 +1353,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct i915_address_space *vm;
struct i915_execbuffer_params params_master; /* XXX: will be removed
later */
struct i915_execbuffer_params *params = params_master;
- struct drm_i915_gem_request *request;
const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
u32 dispatch_flags;
int ret;
@@ -1532,7 +1531,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
params-batch_obj_vm_offset = i915_gem_obj_offset(batch_obj,
vm);
/* Allocate a request for this batch buffer nice and early. */
- ret = dev_priv-gt.alloc_request(ring, ctx, request);
+ ret = dev_priv-gt.alloc_request(ring, ctx, params-request);
if (ret)
goto err;
@@ -1565,6 +1564,16 @@ err:
i915_gem_context_unreference(ctx);
eb_destroy(eb);
+ /*
+* If the request was created but not successfully submitted then it
+* must be freed again. If it was submitted then it is being tracked
+* on the active request list and no clean up is required here.
+*/
+ if (ret params-request) {
+ i915_gem_request_unreference(params-request);
+ ring-outstanding_lazy_request = NULL;
+ }
+
mutex_unlock(dev-struct_mutex);
pre_mutex_err:
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 11/53] drm/i915: Update move_to_gpu() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the move_to_gpu() code paths.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 10 --
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 883cabd..da1e232 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -828,7 +828,7 @@ err:
}
static int
-i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,
+i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
struct list_head *vmas)
{
struct i915_vma *vma;
@@ -838,7 +838,7 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
- ret = i915_gem_object_sync(obj, ring);
+ ret = i915_gem_object_sync(obj, req-ring);
if (ret)
return ret;
@@ -849,7 +849,7 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring,
}
if (flush_chipset)
- i915_gem_chipset_flush(ring-dev);
+ i915_gem_chipset_flush(req-ring-dev);
if (flush_domains I915_GEM_DOMAIN_GTT)
wmb();
@@ -857,7 +857,7 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs
*ring,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return intel_ring_invalidate_all_caches(ring);
+ return intel_ring_invalidate_all_caches(req-ring);
}
static bool
@@ -1186,7 +1186,7 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
}
}
- ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);
+ ret = i915_gem_execbuffer_move_to_gpu(params-request, vmas);
if (ret)
goto error;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c42af08..efe970f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -578,11 +578,9 @@ static int logical_ring_invalidate_all_caches(struct
intel_ringbuffer *ringbuf,
return 0;
}
-static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
-struct intel_context *ctx,
+static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
struct list_head *vmas)
{
- struct intel_engine_cs *ring = ringbuf-ring;
struct i915_vma *vma;
uint32_t flush_domains = 0;
bool flush_chipset = false;
@@ -591,7 +589,7 @@ static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma-obj;
- ret = i915_gem_object_sync(obj, ring);
+ ret = i915_gem_object_sync(obj, req-ring);
if (ret)
return ret;
@@ -607,7 +605,7 @@ static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf,
/* Unconditionally invalidate gpu caches and ensure that we do flush
* any residual writes from the previous batch.
*/
- return logical_ring_invalidate_all_caches(ringbuf, ctx);
+ return logical_ring_invalidate_all_caches(req-ringbuf, req-ctx);
}
/**
@@ -686,7 +684,7 @@ int intel_execlists_submission(struct
i915_execbuffer_params *params,
return -EINVAL;
}
- ret = execlists_move_to_gpu(ringbuf, params-ctx, vmas);
+ ret = execlists_move_to_gpu(params-request, vmas);
if (ret)
return ret;
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Support for 90/270 rotation
On Thu, Mar 05, 2015 at 04:29:30PM +0100, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 03:08:17PM +0200, Ville Syrjälä wrote: On Thu, Mar 05, 2015 at 01:56:53PM +0100, Daniel Vetter wrote: On Thu, Mar 05, 2015 at 02:51:28PM +0530, Sonika Jindal wrote: @@ -1519,16 +1550,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) goto out; } - if (!dev-mode_config.rotation_property) - dev-mode_config.rotation_property = - drm_mode_create_rotation_property(dev, - BIT(DRM_ROTATE_0) | - BIT(DRM_ROTATE_180)); - - if (dev-mode_config.rotation_property) - drm_object_attach_property(intel_plane-base.base, - dev-mode_config.rotation_property, - state-base.rotation); + intel_create_rotation_property(dev, intel_plane); I think back from the original rotation work we've had the leftover task to move this into common code so that we do create the property just once without this check. I think this should be done now. Someone should also make it so we can again have different supported rotation bits on different planes. I'll have need for it on CHV I think. plane-atomic_check just needs to reject them. Tbh I'm not sold on the value of trying to tell userspace which rotation works and which doesnt - generic userspace won't learn about y-tiling requirements either so this feels a bit pointless tbh. And rejecting stuff in atomic_check is what it's for. By that logic we shouldn't expose pixel formats or any other useful infromation either then. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads.
From: Deepak S deepa...@linux.intel.com
In normal cases, RC6 promotion timer is 1700us/500us. This will
result in more time spent in C1 state. For more residency in
C6 in case of media workloads, this is changed to 250us.
Not doing this for 3D workloads as too many C6-C0
transition delays can result in performance impact.
v2: Extend GPU busy idle detection framework for rc6 Promotion
timer changes (Chris)
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 10 +-
drivers/gpu/drm/i915/intel_display.c | 3 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 27 +++
4 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3831cc0..85f8aa6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2428,7 +2428,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
struct drm_i915_gem_request *request;
struct intel_ringbuffer *ringbuf;
u32 request_start;
- int ret;
+ int ret, was_empty;
request = ring-outstanding_lazy_request;
if (WARN_ON(request == NULL))
@@ -2495,6 +2495,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
}
request-emitted_jiffies = jiffies;
+ was_empty = list_empty(ring-request_list);
list_add_tail(request-list, ring-request_list);
request-file_priv = NULL;
@@ -2519,6 +2520,10 @@ int __i915_add_request(struct intel_engine_cs *ring,
queue_delayed_work(dev_priv-wq,
dev_priv-mm.retire_work,
round_jiffies_up_relative(HZ));
+
+ if ((ring-id == VCS) was_empty)
+ vlv_media_promotion_timer_busy(dev_priv);
+
intel_mark_busy(dev_priv-dev);
return 0;
@@ -2802,6 +2807,9 @@ i915_gem_retire_requests_ring(struct intel_engine_cs
*ring)
}
WARN_ON(i915_verify_lists(ring-dev));
+
+ if (ring-id == VCS list_empty(ring-request_list))
+ vlv_media_promotion_timer_idle(dev_priv);
}
bool
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 597c10b..5d121b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9172,8 +9172,9 @@ void intel_mark_idle(struct drm_device *dev)
intel_decrease_pllclock(crtc);
}
- if (INTEL_INFO(dev)-gen = 6)
+ if (INTEL_INFO(dev)-gen = 6) {
gen6_rps_idle(dev-dev_private);
+ }
out:
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2a6ec4b..f1a90b8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1233,6 +1233,8 @@ void ironlake_teardown_rc6(struct drm_device *dev);
void gen6_update_ring_freq(struct drm_device *dev);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
void gen6_rps_boost(struct drm_i915_private *dev_priv);
+void vlv_media_promotion_timer_idle(struct drm_i915_private *dev_priv);
+void vlv_media_promotion_timer_busy(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_device *dev);
void skl_wm_get_hw_state(struct drm_device *dev);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e710b43..d23b60a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3961,6 +3961,33 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)
mutex_unlock(dev_priv-rps.hw_lock);
}
+void vlv_media_promotion_timer_idle(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+
+ if (!IS_VALLEYVIEW(dev))
+ return;
+
+ if (IS_CHERRYVIEW(dev_priv-dev)) {
+ /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
+ } else {
+ /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
+ }
+}
+
+void vlv_media_promotion_timer_busy(struct drm_i915_private *dev_priv)
+{
+ struct drm_device *dev = dev_priv-dev;
+
+ if (!IS_VALLEYVIEW(dev))
+ return;
+
+ /* TO threshold set to 250 us ( 0xC3 * 1.28 us) */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0xC3);
+}
+
void intel_set_rps(struct drm_device *dev, u8 val)
{
if (IS_VALLEYVIEW(dev))
--
1.9.1
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[Intel-gfx] [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
Time to switch over all the IS_GENX() macros to the new device object.
Nothing more than a mechanical search replace here.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_bufmgr_gem.c | 7 +-
intel/intel_chipset.h | 158 --
intel/intel_decode.c | 41 ++--
intel/intel_device_priv.h | 8 +++
4 files changed, 31 insertions(+), 183 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 58543a2..011fa5b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3451,8 +3451,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem-pci_device = drm_intel_device_get_devid(bufmgr_gem-dev);
bufmgr_gem-gen = bufmgr_gem-dev-gen;
- if (IS_GEN3(bufmgr_gem-pci_device)
- bufmgr_gem-gtt_size 256*1024*1024) {
+ if (IS_GEN3(bufmgr_gem-dev) bufmgr_gem-gtt_size 256*1024*1024) {
/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
* be used for tiled blits. To simplify the accounting, just
* substract the unmappable part (fixed to 256MB on all known
@@ -3494,8 +3493,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
/* Kernel does not supports HAS_LLC query, fallback to GPU
* generation detection and assume that we have LLC on GEN6/7
*/
- bufmgr_gem-has_llc = IS_GEN6(bufmgr_gem-pci_device) ||
- IS_GEN7(bufmgr_gem-pci_device);
+ bufmgr_gem-has_llc = IS_GEN6(bufmgr_gem-dev) ||
+ IS_GEN7(bufmgr_gem-dev);
} else
bufmgr_gem-has_llc = *gp.value;
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 241d700..134c877 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,162 +181,4 @@
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
-#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
-
-#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
-(devid) == PCI_CHIP_E7221_G || \
-(devid) == PCI_CHIP_I915_GM)
-
-#define IS_945GM(devid)((devid) == PCI_CHIP_I945_GM || \
-(devid) == PCI_CHIP_I945_GME)
-
-#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
-(devid) == PCI_CHIP_I945_GM || \
-(devid) == PCI_CHIP_I945_GME || \
-IS_G33(devid))
-
-#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
-(devid) == PCI_CHIP_Q33_G || \
-(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
-(devid) == PCI_CHIP_845_G || \
-(devid) == PCI_CHIP_I855_GM || \
-(devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
-
-#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
-(devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
-(devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
-(devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
-(devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
-IS_HASWELL(devid) || \
-IS_VALLEYVIEW(devid))
-
-#define IS_IVYBRIDGE(devid)((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
-(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
-(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
-(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
-(devid) == PCI_CHIP_IVYBRIDGE_S || \
-(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-
-#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
-(devid) == PCI_CHIP_VALLEYVIEW_1 || \
-(devid) == PCI_CHIP_VALLEYVIEW_2 || \
-(devid) == PCI_CHIP_VALLEYVIEW_3)
-
-#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
-(devid) == PCI_CHIP_HASWELL_M_GT1 || \
-(devid) == PCI_CHIP_HASWELL_S_GT1 || \
-
Re: [Intel-gfx] [PATCH 23/53] drm/i915: Update do_switch() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Updated do_switch() to take a request pointer instead of a ring/context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b326f8d..eedb994 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -556,9 +556,10 @@ mi_set_context(struct intel_engine_cs *ring,
return ret;
}
-static int do_switch(struct intel_engine_cs *ring,
-struct intel_context *to)
+static int do_switch(struct drm_i915_gem_request *req)
{
+ struct intel_context *to = req-ctx;
+ struct intel_engine_cs *ring = req-ring;
struct drm_i915_private *dev_priv = ring-dev-dev_private;
struct intel_context *from = ring-last_context;
u32 hw_flags = 0;
@@ -591,7 +592,7 @@ static int do_switch(struct intel_engine_cs *ring,
if (to-ppgtt) {
trace_switch_mm(ring, to);
- ret = to-ppgtt-switch_mm(to-ppgtt, ring);
+ ret = to-ppgtt-switch_mm(to-ppgtt, req-ring);
No need for this change, ring = req-ring has already been set up. Just
leave the code as it was.
if (ret)
goto unpin_out;
}
@@ -627,7 +628,7 @@ static int do_switch(struct intel_engine_cs *ring,
if (!to-legacy_hw_ctx.initialized || i915_gem_context_is_default(to))
hw_flags |= MI_RESTORE_INHIBIT;
- ret = mi_set_context(ring, to, hw_flags);
+ ret = mi_set_context(req-ring, to, hw_flags);
No need for this change, ring = req-ring has already been set up. Just
leave the code as it was.
if (ret)
goto unpin_out;
@@ -635,7 +636,7 @@ static int do_switch(struct intel_engine_cs *ring,
if (!(to-remap_slice (1i)))
continue;
- ret = i915_gem_l3_remap(ring, i);
+ ret = i915_gem_l3_remap(req-ring, i);
No need for this change, ring = req-ring has already been set up. Just
leave the code as it was.
/* If it failed, try again next round */
if (ret)
DRM_DEBUG_DRIVER(L3 remapping failed\n);
@@ -651,7 +652,7 @@ static int do_switch(struct intel_engine_cs *ring,
*/
if (from != NULL) {
from-legacy_hw_ctx.rcs_state-base.read_domains =
I915_GEM_DOMAIN_INSTRUCTION;
-
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from-legacy_hw_ctx.rcs_state),
ring);
+
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from-legacy_hw_ctx.rcs_state),
req-ring);
No need for this change, ring = req-ring has already been set up. Just
leave the code as it was.
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
* whole damn pipeline, we don't need to explicitly mark the
* object dirty. The only exception is that the context must be
@@ -677,7 +678,7 @@ done:
if (uninitialized) {
if (ring-init_context) {
- ret = ring-init_context(ring, to);
+ ret = ring-init_context(req-ring, to);
No need for this change, ring = req-ring has already been set up. Just
leave the code as it was.
if (ret)
DRM_ERROR(ring init context: %d\n, ret);
}
@@ -722,7 +723,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
return 0;
}
- return do_switch(req-ring, req-ctx);
+ return do_switch(req);
}
static bool contexts_enabled(struct drm_device *dev)
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 24/53] drm/i915: Update deferred context creation to do explicit request management
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
In execlist mode, context initialisation is deferred until first use of the
given context. This is because execlist mode has many more contexts than legacy
mode and many are never actually used. Previously, the initialisation commands
were written to the ring and tagged with some random request structure via the
OLR. This seemed to be causing a null pointer deference bug under certain
circumstances (BZ:40112).
This patch adds explicit request creation and submission to the deferred
initialisation code path. Thus removing any reliance on or randomness caused by
the OLR.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dff7829..4bcb70e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1849,6 +1849,7 @@ static void lrc_setup_hardware_status_page(struct
intel_engine_cs *ring,
int intel_lr_context_deferred_create(struct intel_context *ctx,
struct intel_engine_cs *ring)
{
+ struct drm_i915_private *dev_priv = ring-dev-dev_private;
const bool is_global_default_ctx = (ctx == ring-default_context);
struct drm_device *dev = ring-dev;
struct drm_i915_gem_object *ctx_obj;
@@ -1929,13 +1930,27 @@ int intel_lr_context_deferred_create(struct
intel_context *ctx,
lrc_setup_hardware_status_page(ring, ctx_obj);
else if (ring-id == RCS !ctx-rcs_initialized) {
if (ring-init_context) {
- ret = ring-init_context(ring, ctx);
+ struct drm_i915_gem_request *req;
+
+ ret = dev_priv-gt.alloc_request(ring, ctx, req);
+ if (ret)
+ return ret;
+
+ ret = ring-init_context(req-ring, ctx);
if (ret) {
DRM_ERROR(ring init context: %d\n, ret);
+ i915_gem_request_unreference(req);
ctx-engine[ring-id].ringbuf = NULL;
ctx-engine[ring-id].state = NULL;
goto error;
}
+
+ ret = i915_add_request_no_flush(req-ring);
+ if (ret) {
+ DRM_ERROR(ring init context: %d\n, ret);
+ i915_gem_request_unreference(req);
+ goto error;
+ }
}
ctx-rcs_initialized = true;
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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[Intel-gfx] [PATCH] drm/i915: Update intel_dp_hpd_pulse() to check link status for non-MST operation
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
correctly handled afterwards.
This patch also corrects the problem of SST mode only being handled in the
case of a short (0.5ms - 1.0ms) HPD pulse. For compliance testing purposes
both short and long pulses are used by the different tests, thus both cases
need to be addressed for SST.
This patch replaces [PATCH 10/10] drm/i915: Fix intel_dp_hot_plug() in the
previous compliance testing patch sequence. Review feedback on that patch
indicated that updating intel_dp_hot_plug() was not the correct place for
the test handler.
For the SST case, the main stream is disabled for long HPD pulses as this
generally indicates either a connect/disconnect event or link failure. For
a number of case in compliance testing, the source is required to disable
the main link upon detection of a long HPD.
V2:
- N/A
V3:
- Place the SST mode link status check into the mst_fail case
- Remove obsolete comment regarding SST mode operation
- Removed an erroneous line of code that snuck in during rebasing
V4:
- Added a disable of the main stream (DP transport) for the long pulse case
for SST to support compliance testing
Signed-off-by: Todd PRevite tprev...@gmail.com
---
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 080cc23..2460d14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4618,16 +4618,6 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
goto mst_fail;
}
-
- if (!intel_dp-is_mst) {
- /*
-* we'll check the link status via the normal hot plug
path later -
-* but for short hpds we should check it now
-*/
- drm_modeset_lock(dev-mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
- drm_modeset_unlock(dev-mode_config.connection_mutex);
- }
}
ret = IRQ_HANDLED;
@@ -4639,6 +4629,21 @@ mst_fail:
DRM_DEBUG_KMS(MST device may have disappeared %d vs %d\n,
intel_dp-is_mst, intel_dp-mst_mgr.mst_state);
intel_dp-is_mst = false;
drm_dp_mst_topology_mgr_set_mst(intel_dp-mst_mgr,
intel_dp-is_mst);
+ } else {
+ /* SST mode - handle short/long pulses here */
+ drm_modeset_lock(dev-mode_config.connection_mutex, NULL);
+ /* Clear compliance testing flags/data here to prevent
+* false detection in userspace */
+ intel_dp-compliance_test_data = 0;
+ intel_dp-compliance_testing_active = 0;
+ /* For a long pulse in SST mode, disable the main link */
+ if (long_hpd) {
+ I915_WRITE(DP_TP_CTL(intel_dig_port-port),
+ ~DP_TP_CTL_ENABLE);
+ }
+ intel_dp_check_link_status(intel_dp);
+ drm_modeset_unlock(dev-mode_config.connection_mutex);
+ ret = IRQ_HANDLED;
}
put_power:
intel_display_power_put(dev_priv, power_domain);
--
1.9.1
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Re: [Intel-gfx] [PATCH 25/53] drm/i915: Update init_context() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use requests, it is possible to
update init_context() to take a request pointer instead of a ring/context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c |4 ++--
drivers/gpu/drm/i915/intel_lrc.c|9 -
drivers/gpu/drm/i915/intel_ringbuffer.c |7 +++
drivers/gpu/drm/i915/intel_ringbuffer.h |3 +--
4 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index eedb994..938cd26 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -412,7 +412,7 @@ int i915_gem_context_enable(struct drm_i915_gem_request
*req)
if (ring-init_context == NULL)
return 0;
- ret = ring-init_context(req-ring, ring-default_context);
+ ret = ring-init_context(req);
} else
ret = i915_switch_context(req);
@@ -678,7 +678,7 @@ done:
if (uninitialized) {
if (ring-init_context) {
- ret = ring-init_context(req-ring, to);
+ ret = ring-init_context(req);
if (ret)
DRM_ERROR(ring init context: %d\n, ret);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4bcb70e..cbec056 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1376,16 +1376,15 @@ out:
return ret;
}
-static int gen8_init_rcs_context(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
{
int ret;
- ret = intel_logical_ring_workarounds_emit(ring, ctx);
+ ret = intel_logical_ring_workarounds_emit(req-ring, req-ctx);
if (ret)
return ret;
- return intel_lr_context_render_state_init(ring, ctx);
+ return intel_lr_context_render_state_init(req-ring, req-ctx);
}
/**
@@ -1936,7 +1935,7 @@ int intel_lr_context_deferred_create(struct intel_context
*ctx,
if (ret)
return ret;
- ret = ring-init_context(req-ring, ctx);
+ ret = ring-init_context(req);
if (ret) {
DRM_ERROR(ring init context: %d\n, ret);
i915_gem_request_unreference(req);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 05a7e33..26964a2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -775,16 +775,15 @@ static int intel_ring_workarounds_emit(struct
intel_engine_cs *ring,
return 0;
}
-static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
{
int ret;
- ret = intel_ring_workarounds_emit(ring, ctx);
+ ret = intel_ring_workarounds_emit(req-ring, req-ctx);
if (ret != 0)
return ret;
- ret = i915_gem_render_state_init(ring);
+ ret = i915_gem_render_state_init(req-ring);
if (ret)
DRM_ERROR(init render state: %d\n, ret);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 4f8a14a..c32f5a1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -143,8 +143,7 @@ struct intel_engine_cs {
int (*init_hw)(struct intel_engine_cs *ring);
- int (*init_context)(struct intel_engine_cs *ring,
- struct intel_context *ctx);
+ int (*init_context)(struct drm_i915_gem_request *req);
void(*write_tail)(struct intel_engine_cs *ring,
u32 value);
Reviewed-by: Tomas Elf tomas@intel.com
Thanks,
Tomas
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Re: [Intel-gfx] [PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
On 03/05/2015 08:20 AM, Damien Lespiau wrote:
Time to switch over all the IS_GENX() macros to the new device object.
Nothing more than a mechanical search replace here.
Hmm... why not just do the comparisons directly? The macros seem
superfluous.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
intel/intel_bufmgr_gem.c | 7 +-
intel/intel_chipset.h | 158
--
intel/intel_decode.c | 41 ++--
intel/intel_device_priv.h | 8 +++
4 files changed, 31 insertions(+), 183 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 58543a2..011fa5b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3451,8 +3451,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem-pci_device = drm_intel_device_get_devid(bufmgr_gem-dev);
bufmgr_gem-gen = bufmgr_gem-dev-gen;
- if (IS_GEN3(bufmgr_gem-pci_device)
- bufmgr_gem-gtt_size 256*1024*1024) {
+ if (IS_GEN3(bufmgr_gem-dev) bufmgr_gem-gtt_size 256*1024*1024) {
/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
* be used for tiled blits. To simplify the accounting, just
* substract the unmappable part (fixed to 256MB on all known
@@ -3494,8 +3493,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
/* Kernel does not supports HAS_LLC query, fallback to GPU
* generation detection and assume that we have LLC on GEN6/7
*/
- bufmgr_gem-has_llc = IS_GEN6(bufmgr_gem-pci_device) ||
- IS_GEN7(bufmgr_gem-pci_device);
+ bufmgr_gem-has_llc = IS_GEN6(bufmgr_gem-dev) ||
+ IS_GEN7(bufmgr_gem-dev);
} else
bufmgr_gem-has_llc = *gp.value;
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 241d700..134c877 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,162 +181,4 @@
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-#define IS_ILD(devid)((devid) == PCI_CHIP_ILD_G)
-#define IS_ILM(devid)((devid) == PCI_CHIP_ILM_G)
-
-#define IS_915(devid)((devid) == PCI_CHIP_I915_G || \
- (devid) == PCI_CHIP_E7221_G || \
- (devid) == PCI_CHIP_I915_GM)
-
-#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME)
-
-#define IS_945(devid)((devid) == PCI_CHIP_I945_G || \
- (devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME || \
- IS_G33(devid))
-
-#define IS_G33(devid)((devid) == PCI_CHIP_G33_G || \
- (devid) == PCI_CHIP_Q33_G || \
- (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
- (devid) == PCI_CHIP_845_G || \
- (devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
-
-#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 ||
\
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid) || \
- IS_VALLEYVIEW(devid))
-
-#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_S || \
- (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-
-#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
- (devid) == PCI_CHIP_VALLEYVIEW_1 || \
- (devid) == PCI_CHIP_VALLEYVIEW_2 || \
- (devid) == PCI_CHIP_VALLEYVIEW_3)
-
-#define IS_HSW_GT1(devid)((devid) ==
Re: [Intel-gfx] [PATCH 26/53] drm/i915: Update render_state_init() to take a request structure
On 19/02/2015 17:17, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Updated the two render_state_init() functions to take a request pointer instead
of a ring. This removes their reliance on the OLR.
v2: Rebased to newer tree.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_gem_render_state.c | 18 +-
drivers/gpu/drm/i915/i915_gem_render_state.h |2 +-
drivers/gpu/drm/i915/intel_lrc.c | 22 ++
drivers/gpu/drm/i915/intel_ringbuffer.c |2 +-
4 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c
b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 989476e..85cc746 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -152,29 +152,29 @@ int i915_gem_render_state_prepare(struct intel_engine_cs
*ring,
return 0;
}
-int i915_gem_render_state_init(struct intel_engine_cs *ring)
+int i915_gem_render_state_init(struct drm_i915_gem_request *req)
{
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(ring, so);
+ ret = i915_gem_render_state_prepare(req-ring, so);
if (ret)
return ret;
if (so.rodata == NULL)
return 0;
- ret = ring-dispatch_execbuffer(ring,
- so.ggtt_offset,
- so.rodata-batch_items * 4,
- I915_DISPATCH_SECURE);
+ ret = req-ring-dispatch_execbuffer(req-ring,
+so.ggtt_offset,
+so.rodata-batch_items * 4,
+I915_DISPATCH_SECURE);
if (ret)
goto out;
- i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
+ i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req-ring);
- WARN_ON(ring-outstanding_lazy_request-batch_obj);
- ring-outstanding_lazy_request-batch_obj = so.obj;
+ WARN_ON(req-batch_obj);
+ req-batch_obj = so.obj;
/* __i915_add_request moves object to inactive if it fails */
out:
i915_gem_render_state_fini(so);
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h
b/drivers/gpu/drm/i915/i915_gem_render_state.h
index c44961e..7aa7372 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.h
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -39,7 +39,7 @@ struct render_state {
int gen;
};
-int i915_gem_render_state_init(struct intel_engine_cs *ring);
+int i915_gem_render_state_init(struct drm_i915_gem_request *req);
void i915_gem_render_state_fini(struct render_state *so);
int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
struct render_state *so);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cbec056..f0bb98a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1345,31 +1345,29 @@ static int gen8_emit_request(struct intel_ringbuffer
*ringbuf,
return 0;
}
-static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
- struct intel_context *ctx)
+static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ringbuf = ctx-engine[ring-id].ringbuf;
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(ring, so);
+ ret = i915_gem_render_state_prepare(req-ring, so);
if (ret)
return ret;
if (so.rodata == NULL)
return 0;
- ret = ring-emit_bb_start(ringbuf,
- ctx,
- so.ggtt_offset,
- I915_DISPATCH_SECURE);
+ ret = req-ring-emit_bb_start(req-ringbuf,
+ req-ctx,
+ so.ggtt_offset,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
- i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
+ i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req-ring);
- WARN_ON(ring-outstanding_lazy_request-batch_obj);
- ring-outstanding_lazy_request-batch_obj = so.obj;
+ WARN_ON(req-batch_obj);
+ req-batch_obj = so.obj;
/* __i915_add_request moves object to inactive if it fails */
out:
i915_gem_render_state_fini(so);
@@ -1384,7 +1382,7 @@ static int gen8_init_rcs_context(struct
drm_i915_gem_request *req)
if (ret)
return ret;
- return intel_lr_context_render_state_init(req-ring, req-ctx);
+ return intel_lr_context_render_state_init(req);
}
/**
diff
Re: [Intel-gfx] [PATCH libdrm 00/12] Introduce drm_intel_device and use i915_pciid.h
Based on light reading, patches 1, 5, 6, 7, 8, 10, and 11 are Reviewed-by: Ian Romanick ian.d.roman...@intel.com I sent a comment on patch 9. I'll try to look at the others in the next few days... assuming nobody beats me to it. I'm also going to send some similar Mesa patches that I'll CC you on. On 03/05/2015 08:20 AM, Damien Lespiau wrote: A couple of things I wanted to do for the longest time: - Have (intel's) libdrm use the kernel i915_pciids.h so we can just copy the file when updating - Start a new object, struct drm_intel_device where we could put common code across several userspace projects. For instance it could be where we put the number of threads logic we need to use in several 3d/gpgpu states/instructions (that's a bit fiddly starting with CHV: we can't use static tables anymore and need a runtime query to the kernel) I tested it a bit so it can't be totally wrong: - I ran with this series on a couple of machines with no noticeable problem - I check that the INTEL_DEVID_OVERRIDE env variable was still working (to dump AUB files) - make check, which exercises changes in the decoder path, still passes ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
