Re: [PATCH 0/3] drm/i915: intel_color_check() cleanup
On Thu, 23 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Eliminate the crtc_state->state footgun from intel_color_check(), > and hide some mundane C8 plane details inside it. On the series, Reviewed-by: Jani Nikula > > Ville Syrjälä (3): > drm/i915: Plumb the entire atomic state into intel_color_check() > drm/i915: Hide the intel_crtc_needs_color_update() inside > intel_color_check() > drm/i915: Bury c8_planes_changed() in intel_color_check() > > drivers/gpu/drm/i915/display/intel_color.c | 125 --- > drivers/gpu/drm/i915/display/intel_color.h | 4 +- > drivers/gpu/drm/i915/display/intel_display.c | 26 +--- > 3 files changed, 85 insertions(+), 70 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
On Thu, 23 May 2024, Jani Nikula wrote: > On Thu, 23 May 2024, Ville Syrjälä wrote: >> On Thu, May 23, 2024 at 03:59:44PM +0300, Jani Nikula wrote: >>> Avoid the implicit dev_priv local variable use, and pass dev_priv >>> explicitly to the PIPEGCMAX register macro. >>> >>> Signed-off-by: Jani Nikula >>> --- >>> drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- >>> drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- >>> 2 files changed, 10 insertions(+), 9 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c >>> b/drivers/gpu/drm/i915/display/intel_color.c >>> index a83f41ee6834..da56d24eb933 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_color.c >>> +++ b/drivers/gpu/drm/i915/display/intel_color.c >>> @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc >>> *crtc, >>> i965_lut_10p6_udw([i])); >>> } >>> >>> - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); >>> - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); >>> - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); >>> + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); >>> + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), >>> + lut[i].green); >> >> nit: the newline breaks the pattern in a somewhat ugly way > > It's all cocci's doing... sometimes it's smart, sometimes less so. Pushed to din, with this small wart fixed while applying. > >> Series is >> Reviewed-by: Ville Syrjälä > > Thanks! > > >> >>> + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); >>> } >>> >>> static void i965_load_luts(const struct intel_crtc_state *crtc_state) >>> @@ -3239,9 +3240,9 @@ static struct drm_property_blob >>> *i965_read_lut_10p6(struct intel_crtc *crtc) >>> i965_lut_10p6_pack([i], ldw, udw); >>> } >>> >>> - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(pipe, 0))); >>> - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(pipe, 1))); >>> - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(pipe, 2))); >>> + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(dev_priv, pipe, 0))); >>> + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(dev_priv, pipe, 1))); >>> + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >>> PIPEGCMAX(dev_priv, pipe, 2))); >>> >>> return blob; >>> } >>> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h >>> b/drivers/gpu/drm/i915/display/intel_color_regs.h >>> index 61c18b4a7fa5..8eb643cfead7 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h >>> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h >>> @@ -37,9 +37,9 @@ >>> (i) * 4) >>> >>> /* i965/g4x/vlv/chv */ >>> -#define _PIPEAGCMAX 0x70010 >>> -#define _PIPEBGCMAX 0x71010 >>> -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + >>> (i) * 4) /* u1.16 */ >>> +#define _PIPEAGCMAX 0x70010 >>> +#define _PIPEBGCMAX 0x71010 >>> +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, >>> _PIPEAGCMAX + (i) * 4) /* u1.16 */ >>> >>> /* ilk+ palette */ >>> #define _LGC_PALETTE_A 0x4a000 >>> -- >>> 2.39.2 -- Jani Nikula, Intel
Re: [PATCH 05/10] drm/i915/display: add platform descriptors
On Thu, 23 May 2024, Rodrigo Vivi wrote:
> On Wed, May 22, 2024 at 08:33:42PM +0300, Jani Nikula wrote:
>> We'll need to start identifying the platforms independently in display
>> code in order to break free from the i915 and xe IS_()
>> macros. This is fairly straightforward, as we already identify most
>> platforms by PCI ID in display probe anyway.
>>
>> As the first step, add platform descriptors with pointers to display
>> info. We'll have more platforms than display info, so minimize
>> duplication:
>>
>> - Add separate skl/kbl/cfl/cml descriptors while they share the display
>> info.
>>
>> - Add separate jsl/ehl descriptors while they share the display info.
>>
>> Identify ADL-P (and derivatives) and DG2 descriptors by their names even
>> though their display info is Xe LPD or HPD.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> .../drm/i915/display/intel_display_device.c | 558 ++
>> 1 file changed, 326 insertions(+), 232 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
>> b/drivers/gpu/drm/i915/display/intel_display_device.c
>> index 56b27546d1b3..d1e03437abb3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
>> @@ -20,6 +20,10 @@
>> __diag_push();
>> __diag_ignore_all("-Woverride-init", "Allow field initialization overrides
>> for display info");
>>
>> +struct platform_desc {
>> +const struct intel_display_device_info *info;
>> +};
>
> I had to jump to the latest patch to understand why this single item
> in a new struct... later it makes sense...
Yeah...
>> -#define GEN3_DISPLAY \
>> +#define GEN3_DISPLAY \
>
> I had noticed a trend in all of your recent series, to replace the long tab
> or space before '\' with a single space. But then here you change the single
> space to multiple spaces. Intentional?
Accidental.
Emacs wants to indent and align \'s in a specific way, in a nice column
towards the right. Usually I follow that when adding new stuff manually.
Here, that happened on a line I didn't mean to change.
In the PCI ID patches I intentionally used a single space because I
scripted the whole thing, and I couldn't be bothered to figure out how
to align the \'s any other way! :)
>> static const struct {
>> u32 devid;
>> -const struct intel_display_device_info *info;
>> +const struct platform_desc *desc;
>> } intel_display_ids[] = {
>> -INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, _d_display),
>> -INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, _m_display),
>> -INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, _ehl_display),
>> -INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, _ehl_display),
>> -INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, _display),
>> -INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, _s_display),
Re: [PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values()
> -intel_dp->link.max_lane_count = lane_count >> 1;
>> -} else {
>> +new_lane_count = crtc_state->lane_count;
>> +new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
>> +if (new_link_rate < 0) {
>> +new_lane_count = reduce_lane_count(intel_dp,
>> crtc_state->lane_count);
>> +new_link_rate = intel_dp_max_common_rate(intel_dp);
>> +}
>> +
>> +if (new_lane_count < 0) {
>> drm_err(>drm, "Link Training Unsuccessful\n");
>> return -1;
>> }
>>
>> +if (intel_dp_is_edp(intel_dp) &&
>> +!intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
>> new_lane_count)) {
>> +drm_dbg_kms(>drm,
>> +"Retrying Link training for eDP with same
>> parameters\n");
>> +return 0;
>> +}
>> +
>> +drm_dbg_kms(>drm, "Reducing link parameters from %dx%d to
>> %dx%d\n",
>> + crtc_state->lane_count, crtc_state->port_clock,
>> +new_lane_count, new_link_rate);
>> +
>> +intel_dp->link.max_rate = new_link_rate;
>> +intel_dp->link.max_lane_count = new_lane_count;
>> +
>> return 0;
>> }
>>
>> @@ -1178,9 +1200,7 @@ static void
>> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>> lt_dbg(intel_dp, DP_PHY_DPRX,
>> "Link Training failed with HOBL active, not enabling it
>> from now on\n");
>> intel_dp->hobl_failed = true;
>> -} else if (intel_dp_get_link_train_fallback_values(intel_dp,
>> -
>> crtc_state->port_clock,
>> -
>> crtc_state->lane_count)) {
>> +} else if (intel_dp_get_link_train_fallback_values(intel_dp,
>> crtc_state)) {
>> return;
>> }
>>
>> --
>> 2.43.3
--
Jani Nikula, Intel
[PATCH 2/3] drm/xe: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index c9f067b8f54d..f4366cb958be 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
--
2.39.2
[PATCH 3/3] drm/amdgpu: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/Makefile | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1f6b56ec99f6..9508d0b5708e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd
-subdir-ccflags-y := -Wextra
-subdir-ccflags-y += -Wunused
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-format-attribute
-# Need this to avoid recursive variable evaluation issues
-cond-flags := $(call cc-option, -Wunused-but-set-variable) \
- $(call cc-option, -Wunused-const-variable) \
- $(call cc-option, -Wstringop-truncation) \
- $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(cond-flags)
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-sign-compare
-subdir-ccflags-y += -Wno-missing-field-initializers
+# Locally disable W=1 warnings enabled in drm subsystem Makefile
subdir-ccflags-y += -Wno-override-init
subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
--
2.39.2
[PATCH 1/3] drm/i915: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7cad944b825c..a70d95a8fd7a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
--
2.39.2
[PATCH 0/3] amd, i915, xe: drop redundant warnings from driver makefiles
I'm sending these together, as they're related, and almost identical, but I expect them to be merged individually to each driver. BR, Jani. Jani Nikula (3): drm/i915: drop redundant W=1 warnings from Makefile drm/xe: drop redundant W=1 warnings from Makefile drm/amdgpu: drop redundant W=1 warnings from Makefile drivers/gpu/drm/amd/amdgpu/Makefile | 18 +- drivers/gpu/drm/i915/Makefile | 25 + drivers/gpu/drm/xe/Makefile | 25 + 3 files changed, 3 insertions(+), 65 deletions(-) -- 2.39.2
Re: [PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
On Thu, 23 May 2024, Ville Syrjälä wrote: > On Thu, May 23, 2024 at 03:59:44PM +0300, Jani Nikula wrote: >> Avoid the implicit dev_priv local variable use, and pass dev_priv >> explicitly to the PIPEGCMAX register macro. >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- >> drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- >> 2 files changed, 10 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c >> b/drivers/gpu/drm/i915/display/intel_color.c >> index a83f41ee6834..da56d24eb933 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color.c >> +++ b/drivers/gpu/drm/i915/display/intel_color.c >> @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc >> *crtc, >>i965_lut_10p6_udw([i])); >> } >> >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), >> + lut[i].green); > > nit: the newline breaks the pattern in a somewhat ugly way It's all cocci's doing... sometimes it's smart, sometimes less so. > Series is > Reviewed-by: Ville Syrjälä Thanks! > >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); >> } >> >> static void i965_load_luts(const struct intel_crtc_state *crtc_state) >> @@ -3239,9 +3240,9 @@ static struct drm_property_blob >> *i965_read_lut_10p6(struct intel_crtc *crtc) >> i965_lut_10p6_pack([i], ldw, udw); >> } >> >> -lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 0))); >> -lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 1))); >> -lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 2))); >> +lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 0))); >> +lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 1))); >> +lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 2))); >> >> return blob; >> } >> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h >> b/drivers/gpu/drm/i915/display/intel_color_regs.h >> index 61c18b4a7fa5..8eb643cfead7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h >> @@ -37,9 +37,9 @@ >>(i) * 4) >> >> /* i965/g4x/vlv/chv */ >> -#define _PIPEAGCMAX 0x70010 >> -#define _PIPEBGCMAX 0x71010 >> -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + >> (i) * 4) /* u1.16 */ >> +#define _PIPEAGCMAX0x70010 >> +#define _PIPEBGCMAX0x71010 >> +#define PIPEGCMAX(dev_priv, pipe, i)_MMIO_PIPE2(dev_priv, pipe, >> _PIPEAGCMAX + (i) * 4) /* u1.16 */ >> >> /* ilk+ palette */ >> #define _LGC_PALETTE_A 0x4a000 >> -- >> 2.39.2 -- Jani Nikula, Intel
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Mon, 13 May 2024, Alex Deucher wrote: > On Mon, May 13, 2024 at 8:20 AM Jani Nikula wrote: >> >> On Fri, 10 May 2024, Alex Deucher wrote: >> > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: >> > Series is: >> > Acked-by: Alex Deucher >> >> Thanks, do you want to pick these up via your tree? And do you expect a >> proper R-b before merging? > > Feel free to take them via drm-misc if you'd prefer to land the whole > set together, otherwise, I can pick up the radeon/amdgpu patches. Thanks, merged everything to drm-misc-next. BR, Jani. -- Jani Nikula, Intel
[PATCH 14/16] drm/i915: pass dev_priv explicitly to PRIMSIZE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1cefcdd4f26a..82cb393a0a22 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -476,7 +476,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 7f291b34f10a..8d45c879e74a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -94,8 +94,8 @@ #define PRIM_POS_X_MASK REG_GENMASK(15, 0) #define PRIM_POS_X(x)REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) -#define _PRIMSIZE_A0x60a0c -#define PRIMSIZE(plane)_MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define _PRIMSIZE_A0x60a0c +#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) -- 2.39.2
[PATCH 06/16] drm/i915: pass dev_priv explicitly to DSPPOS
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 34760ecd5d34..b23135ed1a38 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -437,7 +437,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 049114620d93..13a49550c456 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -53,7 +53,7 @@ #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPPOS(dev_priv, plane)_MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 02c5dafc0c93..00dd2b647c83 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -168,7 +168,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); - MMIO_D(DSPPOS(PIPE_A)); + MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); @@ -177,7 +177,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); - MMIO_D(DSPPOS(PIPE_B)); + MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); @@ -186,7 +186,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); - MMIO_D(DSPPOS(PIPE_C)); + MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); -- 2.39.2
[PATCH 05/16] drm/i915: pass dev_priv explicitly to DSPSTRIDE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSTRIDE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ba76c952a656..34760ecd5d34 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -423,7 +423,7 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane),
plane_state->view.color_plane[0].mapping_stride);
if (DISPLAY_VER(dev_priv) < 4) {
@@ -1055,7 +1055,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
- val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane));
fb->pitches[0] = val & 0xffc0;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index e222c0333d19..049114620d93 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -50,7 +50,7 @@
#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
#define _DSPASTRIDE0x70188
-#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
+#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
#define _DSPAPOS 0x7018C /* pre-g4x */
#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAPOS)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 3b6529a6501b..7072d14d86cf 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1316,7 +1316,7 @@ static int gen8_decode_mi_display_flip(struct
parser_exec_state *s,
if (info->plane == PLANE_A) {
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
- info->stride_reg = DSPSTRIDE(info->pipe);
+ info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
} else if (info->plane == PLANE_B) {
info->ctrl_reg = SPRCTL(info->pipe);
@@ -1382,7 +1382,7 @@ static int skl_decode_mi_display_flip(struct
parser_exec_state *s,
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
- info->stride_reg = DSPSTRIDE(info->pipe);
+ info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 48e3b6d8ed98..cf1cff3d1c4f 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -155,7 +155,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu,
int pipe,
{
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
- u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
+ u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) &
stride_mask;
u32 stride = stride_reg;
if (GRAPHICS_VER(dev_priv) >= 9) {
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 944765fe22e7..02c5dafc0c93 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -167,7 +167,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
MMIO_D(DSPADDR(dev_priv, PIPE_A));
- MMIO_D(DSPSTRIDE(PIPE_A));
+ MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
MMIO_D(DSPSURF(PIPE_A));
@@ -176,7 +176,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
[PATCH 13/16] drm/i915: pass dev_priv explicitly to PRIMPOS
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 2026323d88ac..1cefcdd4f26a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -474,7 +474,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, int crtc_w = drm_rect_width(_state->uapi.dst); int crtc_h = drm_rect_height(_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index f67c5a2bb6b9..7f291b34f10a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -87,8 +87,8 @@ #define DSPGAMC(dev_priv, plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -#define _PRIMPOS_A 0x60a08 -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define _PRIMPOS_A 0x60a08 +#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y)REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define PRIM_POS_X_MASK REG_GENMASK(15, 0) -- 2.39.2
[PATCH 15/16] drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PRIMCNSTALPHA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 ++-
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 82cb393a0a22..5c8778865156 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -478,7 +478,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane),
PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w -
1));
- intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv,
+ PRIMCNSTALPHA(dev_priv, i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 8d45c879e74a..a2ba55fa2b30 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -101,8 +101,8 @@
#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
#define PRIM_WIDTH(w)REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
-#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
+#define _PRIMCNSTALPHA_A 0x60a10
+#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane,
_PRIMCNSTALPHA_A)
#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
#define PRIM_CONST_ALPHA_MASKREG_GENMASK(7, 0)
#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK,
(alpha))
--
2.39.2
[PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEGCMAX register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a83f41ee6834..da56d24eb933 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, i965_lut_10p6_udw([i])); } - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), + lut[i].green); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); } static void i965_load_luts(const struct intel_crtc_state *crtc_state) @@ -3239,9 +3240,9 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) i965_lut_10p6_pack([i], ldw, udw); } - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0))); + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1))); + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2))); return blob; } diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 61c18b4a7fa5..8eb643cfead7 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -37,9 +37,9 @@ (i) * 4) /* i965/g4x/vlv/chv */ -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 -- 2.39.2
[PATCH 07/16] drm/i915: pass dev_priv explicitly to DSPSIZE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b23135ed1a38..42175cb74d5d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, */ intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 13a49550c456..5a1f45eceed4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -60,7 +60,7 @@ #define DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, (x)) #define _DSPASIZE 0x70190 /* pre-g4x */ -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00dd2b647c83..e047928c3ea0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); - MMIO_D(DSPSIZE(PIPE_A)); + MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); @@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); - MMIO_D(DSPSIZE(PIPE_B)); + MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); @@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); - MMIO_D(DSPSIZE(PIPE_C)); + MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); -- 2.39.2
[PATCH 10/16] drm/i915: pass dev_priv explicitly to DSPOFFSET
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPOFFSET register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 36225c2aa1c8..2026323d88ac 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -482,7 +482,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
@@ -1033,7 +1033,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->format = drm_format_info(fourcc);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+ offset = intel_de_read(dev_priv,
+ DSPOFFSET(dev_priv, i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index baa3d348c77e..0930a76ccf3c 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -78,7 +78,7 @@
#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
#define _DSPAOFFSET0x701A4 /* hsw+ */
-#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
+#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
#define _DSPASURFLIVE 0x701AC /* g4x+ */
#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index a8be80bde2e7..50dfe1f81b99 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -171,7 +171,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_A));
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(dev_priv, PIPE_A));
- MMIO_D(DSPOFFSET(PIPE_A));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
MMIO_D(DSPSURFLIVE(PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
@@ -180,7 +180,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_B));
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(dev_priv, PIPE_B));
- MMIO_D(DSPOFFSET(PIPE_B));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
MMIO_D(DSPSURFLIVE(PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
@@ -189,7 +189,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_C));
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(dev_priv, PIPE_C));
- MMIO_D(DSPOFFSET(PIPE_C));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
MMIO_D(DSPSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
--
2.39.2
[PATCH 08/16] drm/i915: pass dev_priv explicitly to DSPSURF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 12 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 8
drivers/gpu/drm/i915/intel_clock_gating.c | 6 --
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
8 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 42175cb74d5d..7adaf8cbd945 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
@@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0);
else
intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
}
@@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
}
@@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
+ base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
@@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
else
offset = intel_de_read(dev_priv,
DSPLINOFF(dev_priv, i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
+ base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
@@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc
*crtc,
return false;
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
+ intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base);
else
intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 5a1f45eceed4..2771f2a7645b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -67,7 +67,7 @@
#define DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK,
(w))
#define _DSPASURF 0x7019C /* i965+ */
-#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURF)
+#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURF)
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* i965+ */
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index f46e01cad053..e9189a864f69 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
-
[PATCH 12/16] drm/i915: pass dev_priv explicitly to DSPGAMC
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPGAMC register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 22a550c8b41a..f67c5a2bb6b9 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -84,7 +84,7 @@ #define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPGAMC(dev_priv, plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 -- 2.39.2
[PATCH 11/16] drm/i915: pass dev_priv explicitly to DSPSURFLIVE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURFLIVE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 4 ++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 0930a76ccf3c..22a550c8b41a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -81,7 +81,7 @@
#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
#define _DSPASURFLIVE 0x701AC /* g4x+ */
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
+#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
#define _DSPAGAMC 0x701E0 /* pre-g4x */
#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane,
_DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index abcb8f0825e0..840fea160aa6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
write_vreg(vgpu, offset, p_data, bytes);
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu,
offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
@@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu,
write_vreg(vgpu, offset, p_data, bytes);
if (plane == PLANE_PRIMARY) {
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) =
vgpu_vreg(vgpu, offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
} else {
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 50dfe1f81b99..b4d5592b18df 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(dev_priv, PIPE_A));
MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
- MMIO_D(DSPSURFLIVE(PIPE_A));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
MMIO_D(DSPADDR(dev_priv, PIPE_B));
@@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(dev_priv, PIPE_B));
MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
- MMIO_D(DSPSURFLIVE(PIPE_B));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
MMIO_D(DSPADDR(dev_priv, PIPE_C));
@@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(dev_priv, PIPE_C));
MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
- MMIO_D(DSPSURFLIVE(PIPE_C));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
MMIO_D(SPRLINOFF(PIPE_A));
--
2.39.2
[PATCH 09/16] drm/i915: pass dev_priv explicitly to DSPTILEOFF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPTILEOFF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 7adaf8cbd945..36225c2aa1c8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -487,7 +487,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
linear_offset);
- intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
}
@@ -1038,7 +1038,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
- DSPTILEOFF(i9xx_plane));
+ DSPTILEOFF(dev_priv,
i9xx_plane));
else
offset = intel_de_read(dev_priv,
DSPLINOFF(dev_priv, i9xx_plane));
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 2771f2a7645b..baa3d348c77e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -71,7 +71,7 @@
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* i965+ */
-#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPATILEOFF)
+#define DSPTILEOFF(dev_priv, plane)_MMIO_PIPE2(dev_priv, plane,
_DSPATILEOFF)
#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6c3a0f160bea..0afde865a7de 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -274,7 +274,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
plane->height += 1; /* raw height is one minus the real value */
- val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
+ val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
_PRI_PLANE_X_OFF_SHIFT;
plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
--
2.39.2
[PATCH 04/16] drm/i915: pass dev_priv explicitly to DSPLINOFF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPLINOFF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 79280fe2662d..ba76c952a656 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -485,7 +485,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
@@ -1041,7 +1041,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
DSPTILEOFF(i9xx_plane));
else
offset = intel_de_read(dev_priv,
- DSPLINOFF(i9xx_plane));
+ DSPLINOFF(dev_priv, i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index a68d7b228187..e222c0333d19 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -47,7 +47,7 @@
#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
#define _DSPALINOFF0x70184 /* i965+ */
-#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
+#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
#define _DSPASTRIDE0x70188
#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
--
2.39.2
[PATCH 03/16] drm/i915: pass dev_priv explicitly to DSPADDR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPADDR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 8
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ceb0a969357f..79280fe2662d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -502,7 +502,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
}
@@ -544,7 +544,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
}
static void
@@ -1045,7 +1045,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
- base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
}
plane_config->base = base;
@@ -1096,7 +1096,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc
*crtc,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
else
- intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
+ intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index d483569e4147..a68d7b228187 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -44,7 +44,7 @@
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184 /* pre-i965 */
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
+#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
#define _DSPALINOFF0x70184 /* i965+ */
#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 680d7fc39503..f46e01cad053 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -327,8 +327,8 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPADDR(dev_priv,
i9xx_plane)));
}
static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 909823d7ed1b..944765fe22e7 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -166,7 +166,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70098));
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
- MMIO_D(DSPADDR(PIPE_A));
+ MMIO_D(DSPADDR(dev_priv, PIPE_A));
MMIO_D(DSPSTRIDE(PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
@@ -175,7 +175,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
- MMIO_D(DSPADDR(PIPE_B));
+ MMIO_D(DSPADDR(dev_priv, PIPE_B));
MMIO_D(DSPSTRIDE(PIPE_B));
MMIO_D(DSPPOS(PIPE_B));
MMIO_D(DSPSIZE(PIPE_B));
@@ -184,7 +184,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PI
[PATCH 02/16] drm/i915: pass dev_priv explicitly to DSPCNTR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPCNTR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 10 +-
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/display.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 2 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 3 ++-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
10 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 4636523d7948..ceb0a969357f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -496,7 +496,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
@@ -539,7 +539,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
*/
dspcntr = i9xx_plane_ctl_crtc(crtc_state);
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
@@ -561,7 +561,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
if (async_flip)
dspcntr |= DISP_ASYNC_FLIP;
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
@@ -685,7 +685,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane
*plane,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
ret = val & DISP_ENABLE;
@@ -1012,7 +1012,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->dev = dev;
- val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
if (DISPLAY_VER(dev_priv) >= 4) {
if (val & DISP_TILED) {
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 926da106f1a2..d483569e4147 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -12,7 +12,7 @@
#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR_VLV)
#define _DSPACNTR 0x70180
-#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPACNTR)
+#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPACNTR)
#define DISP_ENABLE REG_BIT(31)
#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 82b155708422..a83f41ee6834 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1038,7 +1038,7 @@ static void i9xx_get_config(struct intel_crtc_state
*crtc_state)
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 tmp;
- tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
if (tmp & DISP_PIPE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1e8e2fd52cf6..58a4060f90b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8233,11 +8233,11 @@ void i830_disable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
pipe_name(pipe));
drm_WARN_ON(_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) &
DISP_ENABLE);
drm_WARN_ON(_priv->drm
[PATCH 01/16] drm/i915: pass dev_priv explicitly to DSPADDR_VLV
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1f05f9184cb2..4636523d7948 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -577,7 +577,7 @@ vlv_primary_async_flip(struct intel_plane *plane, u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d74a74d1f29a..926da106f1a2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -- 2.39.2
[PATCH 00/16] drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
Pass dev_priv explicitly in i9xx_plane_regs.h/intel_color_regs.h. The main changes are scripted, with some manual indentation cleanups on top. BR, Jani. Jani Nikula (16): drm/i915: pass dev_priv explicitly to DSPADDR_VLV drm/i915: pass dev_priv explicitly to DSPCNTR drm/i915: pass dev_priv explicitly to DSPADDR drm/i915: pass dev_priv explicitly to DSPLINOFF drm/i915: pass dev_priv explicitly to DSPSTRIDE drm/i915: pass dev_priv explicitly to DSPPOS drm/i915: pass dev_priv explicitly to DSPSIZE drm/i915: pass dev_priv explicitly to DSPSURF drm/i915: pass dev_priv explicitly to DSPTILEOFF drm/i915: pass dev_priv explicitly to DSPOFFSET drm/i915: pass dev_priv explicitly to DSPSURFLIVE drm/i915: pass dev_priv explicitly to DSPGAMC drm/i915: pass dev_priv explicitly to PRIMPOS drm/i915: pass dev_priv explicitly to PRIMSIZE drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA drm/i915: pass dev_priv explicitly to PIPEGCMAX drivers/gpu/drm/i915/display/i9xx_plane.c | 60 ++- .../gpu/drm/i915/display/i9xx_plane_regs.h| 36 +-- drivers/gpu/drm/i915/display/intel_color.c| 15 ++--- .../gpu/drm/i915/display/intel_color_regs.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-- drivers/gpu/drm/i915/gvt/cmd_parser.c | 12 ++-- drivers/gpu/drm/i915/gvt/display.c| 4 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 8 +-- drivers/gpu/drm/i915/gvt/handlers.c | 14 ++--- drivers/gpu/drm/i915/intel_clock_gating.c | 9 ++- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 48 +++ 12 files changed, 116 insertions(+), 110 deletions(-) -- 2.39.2
Re: XE tests on Tiger Lake
On Wed, 22 May 2024, Sebastian Andrzej Siewior wrote: > Hi, > > I've been testing v6.9 with the XE driver on a > | 00:02.0 VGA compatible controller: Intel Corporation TigerLake-LP GT2 > [Iris Xe Graphics] (rev 01) > (8086:9a49) 11th Gen Intel(R) Core(TM) i7-1165G7 platform. Thanks for testing! I suggest filing an issue at [1], attaching dmesg from boot with drm.debug=14 module parameter set. Cc: xe driver maintainers. BR, Jani. [1] https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/ -- Jani Nikula, Intel
Re: [PATCH] drm/i915: Fix audio component initialization
t; drm_i915_private *i915) > > intel_display_driver_enable_user_access(i915); > > + intel_audio_register(i915); > + It's a bit silly that intel_display_driver_register() now calls both intel_audio_init() and intel_audio_register(). We should probably move the init earlier. The register part shouldn't really be doing any hardware initialization stuff, just expose the software interfaces to the world. Regardless, Reviewed-by: Jani Nikula > intel_display_debugfs_register(i915); > > /* -- Jani Nikula, Intel
Re: [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Instead of that huge _PICK() let's use PICK_EVEN_2RANGES() > for the SEL_FETCH_PLANE registers. A bit more tedious to have > to define 8 raw register offsets for everything, but perhaps > a bit easier to understand since we use a standard mechanism > now instead of hand rolling the arithmetic. > > Also bloat-o-meter says: > add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326) > Function old new delta > icl_plane_update_arm 510 446 -64 > icl_plane_disable_sel_fetch_arm.isra 158 54-104 > icl_plane_update_noarm 18981740-158 > Total: Before=2574502, After=2574176, chg -0.01% > > Signed-off-by: Ville Syrjälä I just don't understand the old one. Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 > .../i915/display/skl_universal_plane_regs.h | 68 +++ > 2 files changed, 68 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index f0bd0a726d7a..289c371c98d1 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -251,51 +251,6 @@ > #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 > #define PIPE_SRCSZ_ERLY_TPT(pipe)_MMIO_PIPE((pipe), > _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) > > -#define _SEL_FETCH_PLANE_BASE_1_A0x70890 > -#define _SEL_FETCH_PLANE_BASE_2_A0x708B0 > -#define _SEL_FETCH_PLANE_BASE_3_A0x708D0 > -#define _SEL_FETCH_PLANE_BASE_4_A0x708F0 > -#define _SEL_FETCH_PLANE_BASE_5_A0x70920 > -#define _SEL_FETCH_PLANE_BASE_6_A0x70940 > -#define _SEL_FETCH_PLANE_BASE_7_A0x70960 > -#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 > -#define _SEL_FETCH_PLANE_BASE_1_B0x71890 > - > -#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ > - _SEL_FETCH_PLANE_BASE_1_A, \ > - _SEL_FETCH_PLANE_BASE_2_A, \ > - _SEL_FETCH_PLANE_BASE_3_A, \ > - _SEL_FETCH_PLANE_BASE_4_A, \ > - _SEL_FETCH_PLANE_BASE_5_A, \ > - _SEL_FETCH_PLANE_BASE_6_A, \ > - _SEL_FETCH_PLANE_BASE_7_A, \ > - _SEL_FETCH_PLANE_BASE_CUR_A) > -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, > _SEL_FETCH_PLANE_BASE_1_B) > -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ > - _SEL_FETCH_PLANE_BASE_1_A + \ > - _SEL_FETCH_PLANE_BASE_A(plane)) > - > -#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > -#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > -_SEL_FETCH_PLANE_CTL_1_A - \ > -_SEL_FETCH_PLANE_BASE_1_A) > -#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) > - > -#define _SEL_FETCH_PLANE_POS_1_A 0x70894 > -#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > -_SEL_FETCH_PLANE_POS_1_A - \ > -_SEL_FETCH_PLANE_BASE_1_A) > - > -#define _SEL_FETCH_PLANE_SIZE_1_A0x70898 > -#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > - _SEL_FETCH_PLANE_SIZE_1_A - \ > - _SEL_FETCH_PLANE_BASE_1_A) > - > -#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > -#define SEL_FETCH_PLANE_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > - _SEL_FETCH_PLANE_OFFSET_1_A - > \ > - _SEL_FETCH_PLANE_BASE_1_A) > - > #define _ALPM_CTL_A 0x60950 > #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, > _ALPM_CTL_A) > #define ALPM_CTL_ALPM_ENABLEREG_BIT(31) > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index cb3bdd71b6b2..a6528e0d719e 100644 > --- a/drivers/gpu/drm/i915/displ
Re: [PATCH 00/10] drm/i915: identify all platforms in display probe
On Wed, 22 May 2024, Gustavo Sousa wrote: > Quoting Jani Nikula (2024-05-22 14:33:37-03:00) >>Add independent platform probe in display, in preparation for breaking >>free from i915 and xe code. >> >>Up next would be adding separate IS_() style macros to >>display. Not included here, because I couldn't come up with nice names >>yet. IS_DISPLAY_() is a bit verbose. > > Drive-by comment: At least for recent hardware, we can use > display-specific release names, e.g. IS_XE2LPD() for LNL's display, > since theoretically that display IP could be reused in a different > platform. I think we should prefer the IP version checks over adding names like xe2lpd which IMO are hard to remember and associate with platforms or IP versions. And we'll still need the platform checks for a plethora of old platforms. BR, Jani. -- Jani Nikula, Intel
[PATCH 09/10] drm/i915/display: add support for subplatforms
Add support for subplatforms. This is similar to what the xe driver is
doing. The subplatform is an enum and it's exclusive, i.e. only one
subplatform can match, and it completely identifies the platform and
subplatform. This is different from i915 core, and is notable in the
handling of ULT/ULX and RPL/RPL-U.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 204 ++
.../drm/i915/display/intel_display_device.h | 26 +++
2 files changed, 230 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 7c5cead1fe15..59b8ca174ef8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -20,9 +20,16 @@
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for
display info");
+struct subplatform_desc {
+ enum intel_display_subplatform subplatform;
+ const char *name;
+ const u16 *pciidlist;
+};
+
struct platform_desc {
enum intel_display_platform platform;
const char *name;
+ const struct subplatform_desc *subplatforms;
const struct intel_display_device_info *info; /* NULL for GMD ID */
};
@@ -30,6 +37,8 @@ struct platform_desc {
.platform = (INTEL_DISPLAY_##_platform), \
.name = #_platform
+#define ID(id) (id)
+
static const struct intel_display_device_info no_display = {};
#define PIPE_A_OFFSET 0x7
@@ -460,8 +469,26 @@ static const struct platform_desc vlv_desc = {
},
};
+static const u16 hsw_ult_ids[] = {
+ INTEL_HSW_ULT_GT1_IDS(ID),
+ INTEL_HSW_ULT_GT2_IDS(ID),
+ INTEL_HSW_ULT_GT3_IDS(ID),
+ 0
+};
+
+static const u16 hsw_ulx_ids[] = {
+ INTEL_HSW_ULX_GT1_IDS(ID),
+ INTEL_HSW_ULX_GT2_IDS(ID),
+ 0
+};
+
static const struct platform_desc hsw_desc = {
PLATFORM(HASWELL),
+ .subplatforms = (const struct subplatform_desc[]) {
+ { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids },
+ { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids },
+ {},
+ },
.info = &(const struct intel_display_device_info) {
.has_ddi = 1,
.has_dp_mst = 1,
@@ -483,8 +510,29 @@ static const struct platform_desc hsw_desc = {
},
};
+static const u16 bdw_ult_ids[] = {
+ INTEL_BDW_ULT_GT1_IDS(ID),
+ INTEL_BDW_ULT_GT2_IDS(ID),
+ INTEL_BDW_ULT_GT3_IDS(ID),
+ INTEL_BDW_ULT_RSVD_IDS(ID),
+ 0
+};
+
+static const u16 bdw_ulx_ids[] = {
+ INTEL_BDW_ULX_GT1_IDS(ID),
+ INTEL_BDW_ULX_GT2_IDS(ID),
+ INTEL_BDW_ULX_GT3_IDS(ID),
+ INTEL_BDW_ULX_RSVD_IDS(ID),
+ 0
+};
+
static const struct platform_desc bdw_desc = {
PLATFORM(BROADWELL),
+ .subplatforms = (const struct subplatform_desc[]) {
+ { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids },
+ { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids },
+ {},
+ },
.info = &(const struct intel_display_device_info) {
.has_ddi = 1,
.has_dp_mst = 1,
@@ -549,23 +597,89 @@ static const struct intel_display_device_info skl_display
= {
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
};
+static const u16 skl_ult_ids[] = {
+ INTEL_SKL_ULT_GT1_IDS(ID),
+ INTEL_SKL_ULT_GT2_IDS(ID),
+ INTEL_SKL_ULT_GT3_IDS(ID),
+ 0
+};
+
+static const u16 skl_ulx_ids[] = {
+ INTEL_SKL_ULX_GT1_IDS(ID),
+ INTEL_SKL_ULX_GT2_IDS(ID),
+ 0
+};
+
static const struct platform_desc skl_desc = {
PLATFORM(SKYLAKE),
+ .subplatforms = (const struct subplatform_desc[]) {
+ { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids },
+ { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids },
+ {},
+ },
.info = _display,
};
+static const u16 kbl_ult_ids[] = {
+ INTEL_KBL_ULT_GT1_IDS(ID),
+ INTEL_KBL_ULT_GT2_IDS(ID),
+ INTEL_KBL_ULT_GT3_IDS(ID),
+ 0
+};
+
+static const u16 kbl_ulx_ids[] = {
+ INTEL_KBL_ULX_GT1_IDS(ID),
+ INTEL_KBL_ULX_GT2_IDS(ID),
+ INTEL_AML_KBL_GT2_IDS(ID),
+ 0
+};
+
static const struct platform_desc kbl_desc = {
PLATFORM(KABYLAKE),
+ .subplatforms = (const struct subplatform_desc[]) {
+ { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids },
+ { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids },
+ {},
+ },
.info = _display,
};
+static const u16 cfl_ult_ids[] = {
+ INTEL_CFL_U_GT2_IDS(ID),
+ INTEL_CFL_U_GT3_IDS(ID),
+ INTEL_WHL_U_GT1_IDS(ID),
+ INTEL_WHL_U_GT2_IDS(ID),
+ INTEL_WHL_U_GT3_IDS(ID),
+ 0
+};
+
+static const u16 cfl_
[PATCH 10/10] drm/i915/display: add probe message
Add an info message about which display device was probed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 59b8ca174ef8..5b6dfb5032e7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1305,6 +1305,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; + drm_info(>drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n", +desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", +pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, +DISPLAY_RUNTIME_INFO(i915)->ip.rel); + return; no_display: -- 2.39.2
[PATCH 08/10] drm/i915/display: identify platforms with enum and name
Add enum intel_display_platform and add that and name to all platform
descriptors.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 48 +++
.../drm/i915/display/intel_display_device.h | 58 +++
2 files changed, 106 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 416853ed50df..7c5cead1fe15 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -21,9 +21,15 @@ __diag_push();
__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for
display info");
struct platform_desc {
+ enum intel_display_platform platform;
+ const char *name;
const struct intel_display_device_info *info; /* NULL for GMD ID */
};
+#define PLATFORM(_platform) \
+ .platform = (INTEL_DISPLAY_##_platform), \
+ .name = #_platform
+
static const struct intel_display_device_info no_display = {};
#define PIPE_A_OFFSET 0x7
@@ -205,6 +211,7 @@ static const struct intel_display_device_info no_display =
{};
.__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
static const struct platform_desc i830_desc = {
+ PLATFORM(I830),
.info = &(const struct intel_display_device_info) {
I830_DISPLAY,
@@ -213,6 +220,7 @@ static const struct platform_desc i830_desc = {
};
static const struct platform_desc i845_desc = {
+ PLATFORM(I845G),
.info = &(const struct intel_display_device_info) {
I845_DISPLAY,
@@ -221,6 +229,7 @@ static const struct platform_desc i845_desc = {
};
static const struct platform_desc i85x_desc = {
+ PLATFORM(I85X),
.info = &(const struct intel_display_device_info) {
I830_DISPLAY,
@@ -230,6 +239,7 @@ static const struct platform_desc i85x_desc = {
};
static const struct platform_desc i865g_desc = {
+ PLATFORM(I865G),
.info = &(const struct intel_display_device_info) {
I845_DISPLAY,
@@ -251,6 +261,7 @@ static const struct platform_desc i865g_desc = {
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
static const struct platform_desc i915g_desc = {
+ PLATFORM(I915G),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I845_COLORS,
@@ -260,6 +271,7 @@ static const struct platform_desc i915g_desc = {
};
static const struct platform_desc i915gm_desc = {
+ PLATFORM(I915GM),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I9XX_COLORS,
@@ -272,6 +284,7 @@ static const struct platform_desc i915gm_desc = {
};
static const struct platform_desc i945g_desc = {
+ PLATFORM(I945G),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I845_COLORS,
@@ -282,6 +295,7 @@ static const struct platform_desc i945g_desc = {
};
static const struct platform_desc i945gm_desc = {
+ PLATFORM(I915GM),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I9XX_COLORS,
@@ -295,6 +309,7 @@ static const struct platform_desc i945gm_desc = {
};
static const struct platform_desc g33_desc = {
+ PLATFORM(G33),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I845_COLORS,
@@ -303,6 +318,7 @@ static const struct platform_desc g33_desc = {
};
static const struct platform_desc pnv_desc = {
+ PLATFORM(PINEVIEW),
.info = &(const struct intel_display_device_info) {
GEN3_DISPLAY,
I9XX_COLORS,
@@ -323,6 +339,7 @@ static const struct platform_desc pnv_desc = {
BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
static const struct platform_desc i965g_desc = {
+ PLATFORM(I965G),
.info = &(const struct intel_display_device_info) {
GEN4_DISPLAY,
.has_overlay = 1,
@@ -332,6 +349,7 @@ static const struct platform_desc i965g_desc = {
};
static const struct platform_desc i965gm_desc = {
+ PLATFORM(I965GM),
.info = &(const struct intel_display_device_info) {
GEN4_DISPLAY,
.has_overlay = 1,
@@ -343,6 +361,7 @@ static const struct platform_desc i965gm_desc = {
};
static const struct platform_desc g45_desc = {
+ PLATFORM(G45),
.info = &(const struct intel_display_device_info) {
GEN4_DISPLAY,
@@ -351,6 +370,7 @@ static const struct platform_desc g45_desc = {
};
static const struct platform_desc gm45_desc = {
+ PLATFORM(GM45),
.info = &(const struct intel_display_device_info) {
GEN4_DISPLAY,
[PATCH 07/10] drm/i915/display: change display probe to identify GMD ID based platforms
We'll need to identify all platforms, including the ones that have
display defined by GMD ID. Add MTL and LNL. Their display info will
still be probed via GMD ID.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 44 +++
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index d1e03437abb3..416853ed50df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -21,7 +21,7 @@ __diag_push();
__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for
display info");
struct platform_desc {
- const struct intel_display_device_info *info;
+ const struct intel_display_device_info *info; /* NULL for GMD ID */
};
static const struct intel_display_device_info no_display = {};
@@ -871,6 +871,17 @@ static const struct intel_display_device_info
xe2_hpd_display = {
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
};
+/*
+ * Do not initialize the .info member of the platform desc for GMD ID based
+ * platforms. Their display will be probed automatically based on the IP
version
+ * reported by the hardware.
+ */
+static const struct platform_desc mtl_desc = {
+};
+
+static const struct platform_desc lnl_desc = {
+};
+
__diag_pop();
/*
@@ -937,12 +948,8 @@ static const struct {
INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, _p_desc),
INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, _p_desc),
INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, _desc),
-
- /*
-* Do not add any GMD_ID-based platforms to this list. They will
-* be probed automatically based on the IP version reported by
-* the hardware.
-*/
+ INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, _desc),
+ INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, _desc),
};
static const struct {
@@ -995,20 +1002,15 @@ probe_gmdid_display(struct drm_i915_private *i915,
struct intel_display_ip_ver *
return NULL;
}
-static const struct intel_display_device_info *
-probe_display(struct drm_i915_private *i915)
+static const struct platform_desc *find_platform_desc(struct pci_dev *pdev)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
int i;
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
if (intel_display_ids[i].devid == pdev->device)
- return intel_display_ids[i].desc->info;
+ return intel_display_ids[i].desc;
}
- drm_dbg(>drm, "No display ID found for device ID %04x; disabling
display.\n",
- pdev->device);
-
return NULL;
}
@@ -1017,6 +1019,7 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
const struct intel_display_device_info *info;
struct intel_display_ip_ver ip_ver = {};
+ const struct platform_desc *desc;
/* Add drm device backpointer as early as possible. */
i915->display.drm = >drm;
@@ -1028,12 +1031,17 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
goto no_display;
}
- if (HAS_GMD_ID(i915))
- info = probe_gmdid_display(i915, _ver);
- else
- info = probe_display(i915);
+ desc = find_platform_desc(pdev);
+ if (!desc) {
+ drm_dbg_kms(>drm, "Unknown device ID %04x; disabling
display.\n",
+ pdev->device);
+ goto no_display;
+ }
+ info = desc->info;
if (!info)
+ info = probe_gmdid_display(i915, _ver);
+if (!info)
goto no_display;
DISPLAY_INFO(i915) = info;
--
2.39.2
[PATCH 06/10] drm/i915: add LNL PCI IDs
Although not supported by i915 core, the display code needs to know the LNL PCI IDs. Long term, xe and i915 should probably share the file defining PCI IDs. Signed-off-by: Jani Nikula --- include/drm/i915_pciids.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 3e39d644ebaa..7ae7ee11ef38 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -783,4 +783,10 @@ MACRO__(0x7DD1, ## __VA_ARGS__), \ MACRO__(0x7DD5, ## __VA_ARGS__) +/* LNL */ +#define INTEL_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + #endif /* _I915_PCIIDS_H */ -- 2.39.2
[PATCH 05/10] drm/i915/display: add platform descriptors
We'll need to start identifying the platforms independently in display
code in order to break free from the i915 and xe IS_()
macros. This is fairly straightforward, as we already identify most
platforms by PCI ID in display probe anyway.
As the first step, add platform descriptors with pointers to display
info. We'll have more platforms than display info, so minimize
duplication:
- Add separate skl/kbl/cfl/cml descriptors while they share the display
info.
- Add separate jsl/ehl descriptors while they share the display info.
Identify ADL-P (and derivatives) and DG2 descriptors by their names even
though their display info is Xe LPD or HPD.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 558 ++
1 file changed, 326 insertions(+), 232 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 56b27546d1b3..d1e03437abb3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -20,6 +20,10 @@
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for
display info");
+struct platform_desc {
+ const struct intel_display_device_info *info;
+};
+
static const struct intel_display_device_info no_display = {};
#define PIPE_A_OFFSET 0x7
@@ -200,33 +204,41 @@ static const struct intel_display_device_info no_display
= {};
.__runtime_defaults.pipe_mask = BIT(PIPE_A), \
.__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
-static const struct intel_display_device_info i830_display = {
- I830_DISPLAY,
+static const struct platform_desc i830_desc = {
+ .info = &(const struct intel_display_device_info) {
+ I830_DISPLAY,
- .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
BIT(PORT_C), /* DVO A/B/C */
+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
BIT(PORT_C), /* DVO A/B/C */
+ },
};
-static const struct intel_display_device_info i845_display = {
- I845_DISPLAY,
+static const struct platform_desc i845_desc = {
+ .info = &(const struct intel_display_device_info) {
+ I845_DISPLAY,
- .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
+ .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
DVO B/C */
+ },
};
-static const struct intel_display_device_info i85x_display = {
- I830_DISPLAY,
+static const struct platform_desc i85x_desc = {
+ .info = &(const struct intel_display_device_info) {
+ I830_DISPLAY,
- .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
DVO B/C */
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+ },
};
-static const struct intel_display_device_info i865g_display = {
- I845_DISPLAY,
+static const struct platform_desc i865g_desc = {
+ .info = &(const struct intel_display_device_info) {
+ I845_DISPLAY,
- .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+ .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
DVO B/C */
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+ },
};
-#define GEN3_DISPLAY \
+#define GEN3_DISPLAY \
.has_gmch = 1, \
.has_overlay = 1, \
I9XX_PIPE_OFFSETS, \
@@ -238,52 +250,64 @@ static const struct intel_display_device_info
i865g_display = {
BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
-static const struct intel_display_device_info i915g_display = {
- GEN3_DISPLAY,
- I845_COLORS,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
+static const struct platform_desc i915g_desc = {
+ .info = &(const struct intel_display_device_info) {
+ GEN3_DISPLAY,
+ I845_COLORS,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ },
};
-static const struct intel_display_device_info i915gm_display = {
- GEN3_DISPLAY,
- I9XX_COLORS,
- .cursor_needs_physical = 1,
- .overlay_needs_physical = 1,
- .supports_tv = 1,
+static const struct platform_desc i915gm_desc = {
+ .info = &(const struct intel_display_device_info) {
+ GEN3_DISPLAY,
+ I9XX_COLORS,
+ .cursor_needs_physical = 1,
+ .overlay_needs_physical = 1,
+ .supports_tv = 1,
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
+
[PATCH 04/10] drm/i915/display: change GMD ID display ip ver propagation at probe
Add a name to the display ip version structure, and pass that around
instead of a triplet of u16's.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 40 ---
.../drm/i915/display/intel_display_device.h | 2 +-
2 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index f548a7b0ec23..56b27546d1b3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -862,22 +862,14 @@ static const struct {
};
static const struct intel_display_device_info *
-probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16
*step)
+probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver
*ip_ver)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct intel_display_ip_ver gmd_id;
void __iomem *addr;
u32 val;
int i;
- /* The caller expects to ver, rel and step to be initialized
-* here, and there's no good way to check when there was a
-* failure and no_display was returned. So initialize all these
-* values here zero, to be sure.
-*/
- *ver = 0;
- *rel = 0;
- *step = 0;
-
addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY),
sizeof(u32));
if (!addr) {
drm_err(>drm, "Cannot map MMIO BAR to read display
GMD_ID\n");
@@ -892,17 +884,20 @@ probe_gmdid_display(struct drm_i915_private *i915, u16
*ver, u16 *rel, u16 *step
return NULL;
}
- *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
- *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
- *step = REG_FIELD_GET(GMD_ID_STEP, val);
+ gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+ gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+ gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
- for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
- if (*ver == gmdid_display_map[i].ver &&
- *rel == gmdid_display_map[i].rel)
+ for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
+ if (gmd_id.ver == gmdid_display_map[i].ver &&
+ gmd_id.rel == gmdid_display_map[i].rel) {
+ *ip_ver = gmd_id;
return gmdid_display_map[i].display;
+ }
+ }
drm_err(>drm, "Unrecognized display IP version %d.%02d; disabling
display.\n",
- *ver, *rel);
+ gmd_id.ver, gmd_id.rel);
return NULL;
}
@@ -927,7 +922,7 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
const struct intel_display_device_info *info;
- u16 ver, rel, step;
+ struct intel_display_ip_ver ip_ver = {};
/* Add drm device backpointer as early as possible. */
i915->display.drm = >drm;
@@ -940,7 +935,7 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
}
if (HAS_GMD_ID(i915))
- info = probe_gmdid_display(i915, , , );
+ info = probe_gmdid_display(i915, _ver);
else
info = probe_display(i915);
@@ -953,11 +948,8 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
_INFO(i915)->__runtime_defaults,
sizeof(*DISPLAY_RUNTIME_INFO(i915)));
- if (HAS_GMD_ID(i915)) {
- DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
- DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
- DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
- }
+ if (ip_ver.ver || ip_ver.rel || ip_ver.step)
+ DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver;
return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 17ddf82f0b6e..fd2d03bfe8a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -111,7 +111,7 @@ struct drm_printer;
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
struct intel_display_runtime_info {
- struct {
+ struct intel_display_ip_ver {
u16 ver;
u16 rel;
u16 step;
--
2.39.2
[PATCH 03/10] drm/i915/display: check platforms without display one level higher
The main change here is that the check for platforms without display is
now also done for GMD ID based platforms. However, without matches, the
end result is the same.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_device.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 03181bb79d21..f548a7b0ec23 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -912,11 +912,6 @@ probe_display(struct drm_i915_private *i915)
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
int i;
- if (has_no_display(pdev)) {
- drm_dbg_kms(>drm, "Device doesn't have display\n");
- return NULL;
- }
-
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
if (intel_display_ids[i].devid == pdev->device)
return intel_display_ids[i].info;
@@ -930,6 +925,7 @@ probe_display(struct drm_i915_private *i915)
void intel_display_device_probe(struct drm_i915_private *i915)
{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
const struct intel_display_device_info *info;
u16 ver, rel, step;
@@ -938,6 +934,11 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
intel_display_params_copy(>display.params);
+ if (has_no_display(pdev)) {
+ drm_dbg_kms(>drm, "Device doesn't have display\n");
+ goto no_display;
+ }
+
if (HAS_GMD_ID(i915))
info = probe_gmdid_display(i915, , , );
else
--
2.39.2
[PATCH 02/10] drm/i915/display: change probe for no display case
Return NULL for errors, and handle the no display case in one
location. This will make subsequent changes easier.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c| 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 9edadc7270f6..03181bb79d21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -881,7 +881,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16
*ver, u16 *rel, u16 *step
addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY),
sizeof(u32));
if (!addr) {
drm_err(>drm, "Cannot map MMIO BAR to read display
GMD_ID\n");
- return _display;
+ return NULL;
}
val = ioread32(addr);
@@ -889,7 +889,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16
*ver, u16 *rel, u16 *step
if (val == 0) {
drm_dbg_kms(>drm, "Device doesn't have display\n");
- return _display;
+ return NULL;
}
*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
@@ -903,7 +903,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16
*ver, u16 *rel, u16 *step
drm_err(>drm, "Unrecognized display IP version %d.%02d; disabling
display.\n",
*ver, *rel);
- return _display;
+ return NULL;
}
static const struct intel_display_device_info *
@@ -914,7 +914,7 @@ probe_display(struct drm_i915_private *i915)
if (has_no_display(pdev)) {
drm_dbg_kms(>drm, "Device doesn't have display\n");
- return _display;
+ return NULL;
}
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
@@ -925,7 +925,7 @@ probe_display(struct drm_i915_private *i915)
drm_dbg(>drm, "No display ID found for device ID %04x; disabling
display.\n",
pdev->device);
- return _display;
+ return NULL;
}
void intel_display_device_probe(struct drm_i915_private *i915)
@@ -943,6 +943,9 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
else
info = probe_display(i915);
+ if (!info)
+ goto no_display;
+
DISPLAY_INFO(i915) = info;
memcpy(DISPLAY_RUNTIME_INFO(i915),
@@ -954,6 +957,11 @@ void intel_display_device_probe(struct drm_i915_private
*i915)
DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
}
+
+ return;
+
+no_display:
+ DISPLAY_INFO(i915) = _display;
}
void intel_display_device_remove(struct drm_i915_private *i915)
--
2.39.2
[PATCH 01/10] drm/i915/display: move params copy at probe earlier
Copy the parameters earlier to make subsequent changes easier. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index cf093bc0cb28..9edadc7270f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -936,6 +936,8 @@ void intel_display_device_probe(struct drm_i915_private *i915) /* Add drm device backpointer as early as possible. */ i915->display.drm = >drm; + intel_display_params_copy(>display.params); + if (HAS_GMD_ID(i915)) info = probe_gmdid_display(i915, , , ); else @@ -952,8 +954,6 @@ void intel_display_device_probe(struct drm_i915_private *i915) DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; DISPLAY_RUNTIME_INFO(i915)->ip.step = step; } - - intel_display_params_copy(>display.params); } void intel_display_device_remove(struct drm_i915_private *i915) -- 2.39.2
[PATCH 00/10] drm/i915: identify all platforms in display probe
Add independent platform probe in display, in preparation for breaking free from i915 and xe code. Up next would be adding separate IS_() style macros to display. Not included here, because I couldn't come up with nice names yet. IS_DISPLAY_() is a bit verbose. BR, Jani. Jani Nikula (10): drm/i915/display: move params copy at probe earlier drm/i915/display: change probe for no display case drm/i915/display: check platforms without display one level higher drm/i915/display: change GMD ID display ip ver propagation at probe drm/i915/display: add platform descriptors drm/i915: add LNL PCI IDs drm/i915/display: change display probe to identify GMD ID based platforms drm/i915/display: identify platforms with enum and name drm/i915/display: add support for subplatforms drm/i915/display: add probe message .../drm/i915/display/intel_display_device.c | 920 -- .../drm/i915/display/intel_display_device.h | 86 +- include/drm/i915_pciids.h | 6 + 3 files changed, 731 insertions(+), 281 deletions(-) -- 2.39.2
Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
On Mon, 20 May 2024, Jani Nikula wrote: > On Wed, 15 May 2024, Jani Nikula wrote: >> The PCI ID macros in xe_pciids.h allow passing in the macro to operate >> on each PCI ID, making it more flexible. Convert i915_pciids.h to the >> same pattern. >> >> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and >> unconditionally uses INTEL_QUANTA_VGA_DEVICE(). >> >> Cc: Bjorn Helgaas >> Cc: linux-...@vger.kernel.org > > Bjorn, since I asked for acks on the last ones, I probably should here > too. :) > > I'm hoping to stop mucking with the macros after this. Okay, well, I pushed this to drm-intel-next, since this doesn't really change x86 functionally, and you weren't all that interested the last time. Hope it's fine. :) BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 2/2] drm/i915/display: Add compare config for MTL+ platforms
const struct intel_cx0pll_state *b)
> +{
Maybe this for starters?
if (a->use_c10 != b->use_c10)
return false;
> + if (a->use_c10 && b->use_c10)
> + return mtl_compare_hw_state_c10(>c10,
> + >c10);
> + else
> + return mtl_compare_hw_state_c20(>c20,
> + >c20);
> +}
> +
> int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
>const struct intel_cx0pll_state *pll_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 3e03af3e006c..180821df1834 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -39,6 +39,8 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private
> *dev_priv,
> const struct intel_c10pll_state *hw_state);
> void intel_cx0pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> +bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
> +const struct intel_cx0pll_state *b);
> void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> const struct intel_c20pll_state *hw_state);
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cce1420fb541..17b43b2ae0e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -66,6 +66,7 @@
> #include "intel_crtc.h"
> #include "intel_crtc_state_dump.h"
> #include "intel_cursor_regs.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> @@ -5002,6 +5003,30 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool
> fastset,
> intel_dpll_dump_hw_state(i915, p, b);
> }
>
> +static void
> +pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> + const struct intel_crtc *crtc,
> + const char *name,
> + const struct intel_cx0pll_state *a,
> + const struct intel_cx0pll_state *b)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid
> -Werror=format-zero-length */
Instead of working around something and adding comments like that, maybe
actually use it for something useful?
Something like, idk, "%s", a->c10 ? "c10" : "c20"
> +
> + if (a->use_c10) {
> + drm_printf(p, "expected:\n");
> + intel_c10pll_dump_hw_state(i915, >c10);
> + drm_printf(p, "found:\n");
> + intel_c10pll_dump_hw_state(i915, >c10);
> + } else {
> + drm_printf(p, "expected:\n");
> + intel_c20pll_dump_hw_state(i915, >c20);
> + drm_printf(p, "found:\n");
> + intel_c20pll_dump_hw_state(i915, >c20);
> + }
> + drm_printf(p, "found:\n");
> + intel_c10pll_dump_hw_state(i915, >c10);
> + } else {
> + drm_printf(p, "expected:\n");
> + intel_c20pll_dump_hw_state(i915, >c20);
> + drm_printf(p, "found:\n");
> + intel_c20pll_dump_hw_state(i915, >c20);
> + }
I think I'd add a intel_cx0pll_dump_hw_state() to avoid looking into the
details like this at high level code. This becomes cleaner too.
> +}
> +
> bool
> intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> @@ -5105,6 +5130,16 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
> + if (!intel_cx0pll_compare_hw_state(_config->name, \
> +_config->name)) { \
> + pipe_config_cx0pll_mismatch(, fastset, crtc,
> __stringify(name), \
> + _config->name, \
> + _config->name); \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_CHECK_TIMINGS(name) do { \
> PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
> PIPE_CONF_CHECK_I(name.crtc_htotal); \
> @@ -5337,6 +5372,10 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
> PIPE_CONF_CHECK_PLL(dpll_hw_state);
>
> + /* FIXME convert MTL+ platforms over to dpll_mgr */
> + if (DISPLAY_VER(dev_priv) >= 14)
> + PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
> +
> PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> PIPE_CONF_CHECK_X(dsi_pll.div);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f09e513ce05b..36baed75b89a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -264,6 +264,7 @@ struct intel_cx0pll_state {
> struct intel_c20pll_state c20;
> };
> bool ssc_enabled;
> + bool use_c10;
> };
>
> struct intel_dpll_hw_state {
--
Jani Nikula, Intel
Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()
On Tue, 21 May 2024, Ville Syrjälä wrote: > On Tue, May 21, 2024 at 12:51:03PM +0300, Jani Nikula wrote: >> On Mon, 20 May 2024, Ville Syrjälä wrote: >> > On Mon, May 20, 2024 at 01:47:34PM +0300, Jani Nikula wrote: >> >> On Fri, 17 May 2024, Ville Syrjala wrote: >> >> > From: Ville Syrjälä >> >> > >> >> > Extract a helper to check whether the source+sink combo >> >> > supports DSC. That basic check is needed both during mode >> >> > validation and compute config. We'll also need to add extra >> >> > checks to both places, so having a single place for it is nicer. >> >> > >> >> > Signed-off-by: Ville Syrjälä >> >> > --- >> >> > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++-- >> >> > 1 file changed, 14 insertions(+), 2 deletions(-) >> >> > >> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >> >> > b/drivers/gpu/drm/i915/display/intel_dp.c >> >> > index 1e88449fe5f2..7bf283b4df7f 100644 >> >> > --- a/drivers/gpu/drm/i915/display/intel_dp.c >> >> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> >> > @@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp >> >> > *intel_dp, >> >> >connector->force_bigjoiner_enable; >> >> > } >> >> > >> >> > +static bool intel_dp_has_dsc(struct intel_connector *connector) >> >> >> >> Why not const? >> > >> > We've generally not consted these things. And then whenver add >> > one const somewhere it usually ends up getting in the way later, >> > not because we need mutability but simply because we want to >> > call something that doesn't have the const. >> > >> > I suppose if we do want to start consting things more we should >> > just do some kind of bigger pass over the whole codebase so that >> > that there's less chance of pain later. >> > >> > We're also not using container_of_const() for these right now, >> > so the const can vanish semi-accidentally when casting things. >> > >> > I suppose this thing might be low level enough that the const >> > could be kept. I'll have another think about it. >> >> It's just that this series drops a bunch of const because of this, which >> feels like the opposite of what you usually do. :) > > I suppose. > > My current rule of thumb is: > - atomic object states and fbs should be const if possible > - everything else is not > > I wouldn't mind making more things const, but I suspect > there are several sizeable rabbit holes that need to be > dug out beforehand. Fair enough. Like I said, the series is R-b. J. -- Jani Nikula, Intel
Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()
On Mon, 20 May 2024, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 01:47:34PM +0300, Jani Nikula wrote:
>> On Fri, 17 May 2024, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Extract a helper to check whether the source+sink combo
>> > supports DSC. That basic check is needed both during mode
>> > validation and compute config. We'll also need to add extra
>> > checks to both places, so having a single place for it is nicer.
>> >
>> > Signed-off-by: Ville Syrjälä
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
>> > 1 file changed, 14 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 1e88449fe5f2..7bf283b4df7f 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp
>> > *intel_dp,
>> > connector->force_bigjoiner_enable;
>> > }
>> >
>> > +static bool intel_dp_has_dsc(struct intel_connector *connector)
>>
>> Why not const?
>
> We've generally not consted these things. And then whenver add
> one const somewhere it usually ends up getting in the way later,
> not because we need mutability but simply because we want to
> call something that doesn't have the const.
>
> I suppose if we do want to start consting things more we should
> just do some kind of bigger pass over the whole codebase so that
> that there's less chance of pain later.
>
> We're also not using container_of_const() for these right now,
> so the const can vanish semi-accidentally when casting things.
>
> I suppose this thing might be low level enough that the const
> could be kept. I'll have another think about it.
It's just that this series drops a bunch of const because of this, which
feels like the opposite of what you usually do. :)
BR,
Jani.
>
>>
>> > +{
>> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> > +
>> > + if (!HAS_DSC(i915))
>> > + return false;
>> > +
>> > + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
>> > + return false;
>> > +
>> > + return true;
>> > +}
>> > +
>> > static enum drm_mode_status
>> > intel_dp_mode_valid(struct drm_connector *_connector,
>> >struct drm_display_mode *mode)
>> > @@ -1274,8 +1287,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>> > mode_rate = intel_dp_link_required(target_clock,
>> >
>> > intel_dp_mode_min_output_bpp(connector, mode));
>> >
>> > - if (HAS_DSC(dev_priv) &&
>> > - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
>> > + if (intel_dp_has_dsc(connector)) {
>> >enum intel_output_format sink_format, output_format;
>> >int pipe_bpp;
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
Re: [PATCH v2] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+
On Mon, 20 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2. > Bump our limit to match. > > v2: Bump for ADL-S as well (Jani) > > Cc: Jani Nikula > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 0faf2afa1c09..9ac670a40bc1 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct > intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > int max_tmds_clock, vbt_max_tmds_clock; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_S(dev_priv)) > + max_tmds_clock = 60; > + else if (DISPLAY_VER(dev_priv) >= 10) > max_tmds_clock = 594000; > else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) > max_tmds_clock = 30; -- Jani Nikula, Intel
Re: [PATCH 1/3] drm/i915/display: Add missing include to intel_vga.c
On Mon, 20 May 2024, Michal Wajdeczko wrote: > This compilation unit uses udelay() function without including > it's header file. Fix that to break dependency on other code. > > Signed-off-by: Michal Wajdeczko > Cc: Jani Nikula Probably won't be an issue to merge this via xe. Acked-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_vga.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vga.c > b/drivers/gpu/drm/i915/display/intel_vga.c > index 4b98833bfa8c..0b5916c15307 100644 > --- a/drivers/gpu/drm/i915/display/intel_vga.c > +++ b/drivers/gpu/drm/i915/display/intel_vga.c > @@ -3,6 +3,7 @@ > * Copyright © 2019 Intel Corporation > */ > > +#include > #include > > #include -- Jani Nikula, Intel
Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
On Mon, 20 May 2024, Ville Syrjälä wrote: > On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote: >> On Thu, 16 May 2024, Ville Syrjala wrote: >> I also think it's kind of unnecessary when they're only >> passed on as parameters. Or is there some corner case where it matters? > > I think cargo-culting is probably the best argument for protecting > each and every macro argument. If used universally then I think > it'll be a bit more likely that newly added macros, where it > might matter more, will inherit it as well. That's a good point. BR, Jani. -- Jani Nikula, Intel
Re: Is it possible to distinguish between HDMI and DVI in i915?
On Mon, 20 May 2024, Arkadiusz Drabczyk wrote: > My Asus Z97-A motherboard has DVI and HDMI connectors but i915 shows > 2x HDMI ports (and the 3rd one for DP but a separate DP1 is also > shown). Would it be possible to distinguish between DVI and HDMI in > the driver code for example by reading some undocumented VBT registers > or testing port characteristics or something? Please file a bug as described at [1], attach dmesg with drm.debug=14 and VBT as described in the link, and we'll be able to tell you more. Thanks, Jani. [1] https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html -- Jani Nikula, Intel
Re: [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits
On Thu, 16 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make a more thorough split between universal planes vs. cursors
> by defining the contents of the cursor WM/DDB registers separately.
>
> Signed-off-by: Ville Syrjälä
I like this better than exposing the reg val functions.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++
> .../gpu/drm/i915/display/intel_cursor_regs.h | 9 +
> .../drm/i915/display/skl_universal_plane.c| 4 +--
> .../drm/i915/display/skl_universal_plane.h| 3 --
> 4 files changed, 39 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 7983cbaf83f7..cea0cfed569d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -24,7 +24,6 @@
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
> #include "intel_vblank.h"
> -#include "skl_universal_plane.h"
> #include "skl_watermark.h"
>
> #include "gem/i915_gem_object.h"
> @@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
> intel_plane *plane,
> }
> }
>
> +static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return CUR_BUF_END(entry->end - 1) |
> + CUR_BUF_START(entry->start);
> +}
> +
> +static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
> +{
> + u32 val = 0;
> +
> + if (level->enable)
> + val |= CUR_WM_EN;
> + if (level->ignore_lines)
> + val |= CUR_WM_IGNORE_LINES;
> + val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
> + val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
> +
> + return val;
> +}
> +
> static void skl_write_cursor_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane
> *plane,
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> intel_de_write_fw(i915, CUR_WM(pipe, level),
> -
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> +
> skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
> + skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = _wm->planes[plane_id];
>
> intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> - skl_plane_wm_reg_val(>sagv.wm0));
> + skl_cursor_wm_reg_val(>sagv.wm0));
> intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> - skl_plane_wm_reg_val(>sagv.trans_wm));
> + skl_cursor_wm_reg_val(>sagv.trans_wm));
> }
>
> intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> - skl_plane_ddb_reg_val(ddb));
> + skl_cursor_ddb_reg_val(ddb));
> }
>
> /* TODO: split into noarm+arm pair */
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index ab02d497fba6..307a850d54b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -78,6 +78,10 @@
> #define _CUR_WM_A_0 0x70140
> #define _CUR_WM_B_0 0x71140
> #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) +
> (level) * 4)
> +#define CUR_WM_EN REG_BIT(31)
> +#define CUR_WM_IGNORE_LINESREG_BIT(30)
> +#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
>
> #define _CUR_WM_SAGV_A 0x70158
> #define _CUR_WM_SAGV_B 0x71158
> @@ -94,6 +98,11 @@
> #define _CUR_BUF_CFG_A 0x7017c
> #define _CUR_BUF_CFG_B 0x7117c
> #define CUR_BUF_CFG(pipe)_MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
> _CUR_BUF_CFG_B)
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define CUR_BUF_END_MASK REG_
Re: [PATCH 13/13] drm/i915: Document which platforms use which sprite registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Note which sprite registers are valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++ > 1 file changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > index c27adbaf0f00..73021e3ced6d 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > @@ -6,6 +6,7 @@ > > #include "intel_display_reg_defs.h" > > +/* g4x/ilk/snb video sprite */ > #define _DVSACNTR0x72180 > #define _DVSBCNTR0x73180 > #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) > @@ -111,6 +112,7 @@ > #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ > #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, > _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ > > +/* ivb/hsw/bdw sprite */ > #define _SPRA_CTL0x70280 > #define _SPRB_CTL0x71280 > #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) > @@ -140,8 +142,8 @@ > #define SPRITE_TILED REG_BIT(10) > #define SPRITE_DEST_KEYREG_BIT(2) > > -#define _SPRA_LINOFF 0x70284 > -#define _SPRB_LINOFF 0x71284 > +#define _SPRA_LINOFF 0x70284 /* ivb */ > +#define _SPRB_LINOFF 0x71284 /* ivb */ > #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) > > #define _SPRA_STRIDE 0x70288 > @@ -181,24 +183,24 @@ > #define _SPRB_KEYMAX 0x712a0 > #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) > > -#define _SPRA_TILEOFF0x702a4 > -#define _SPRB_TILEOFF0x712a4 > +#define _SPRA_TILEOFF0x702a4 /* ivb */ > +#define _SPRB_TILEOFF0x712a4 /* ivb */ > #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) > #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) > #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) > #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) > > -#define _SPRA_OFFSET 0x702a4 > -#define _SPRB_OFFSET 0x712a4 > +#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */ > +#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */ > #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) > > #define _SPRA_SURFLIVE 0x702ac > #define _SPRB_SURFLIVE 0x712ac > #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) > > -#define _SPRA_SCALE 0x70304 > -#define _SPRB_SCALE 0x71304 > +#define _SPRA_SCALE 0x70304 /* ivb */ > +#define _SPRB_SCALE 0x71304 /* ivb */ > #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) > #define SPRITE_SCALE_ENABLEREG_BIT(31) > #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) > @@ -224,6 +226,7 @@ > #define _SPRB_GAMC17 0x7144c > #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + > (i) * 4) /* 3 x u2.10 */ > > +/* vlv/chv sprite */ > #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ > _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) > #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ -- Jani Nikula, Intel
Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
On Mon, 20 May 2024, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Group the sprite plane register definitions such that everything >> to do wiht the same register is in one place. *with >> >> Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani Nikula > >> --- >> .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++ >> 1 file changed, 134 insertions(+), 97 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> b/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> index bb67705652b2..c27adbaf0f00 100644 >> --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h >> @@ -7,6 +7,8 @@ >> #include "intel_display_reg_defs.h" >> >> #define _DVSACNTR 0x72180 >> +#define _DVSBCNTR 0x73180 >> +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) >> #define DVS_ENABLEREG_BIT(31) >> #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) >> #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) >> @@ -28,31 +30,67 @@ >> #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) >> #define DVS_TILED REG_BIT(10) >> #define DVS_DEST_KEY REG_BIT(2) >> + >> #define _DVSALINOFF 0x72184 >> +#define _DVSBLINOFF 0x73184 >> +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) >> + >> #define _DVSASTRIDE 0x72188 >> +#define _DVSBSTRIDE 0x73188 >> +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) >> + >> #define _DVSAPOS0x7218c >> +#define _DVSBPOS0x7318c >> +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) >> #define DVS_POS_Y_MASKREG_GENMASK(31, 16) >> #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, >> (y)) >> #define DVS_POS_X_MASKREG_GENMASK(15, 0) >> #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, >> (x)) >> + >> #define _DVSASIZE 0x72190 >> +#define _DVSBSIZE 0x73190 >> +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) >> #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) >> #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, >> (h)) >> #define DVS_WIDTH_MASKREG_GENMASK(15, 0) >> #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, >> (w)) >> + >> #define _DVSAKEYVAL 0x72194 >> +#define _DVSBKEYVAL 0x73194 >> +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) >> + >> #define _DVSAKEYMSK 0x72198 >> +#define _DVSBKEYMSK 0x73198 >> +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) >> + >> #define _DVSASURF 0x7219c >> +#define _DVSBSURF 0x7319c >> +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) >> #define DVS_ADDR_MASK REG_GENMASK(31, 12) >> + >> #define _DVSAKEYMAXVAL 0x721a0 >> +#define _DVSBKEYMAXVAL 0x731a0 >> +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) >> + >> #define _DVSATILEOFF0x721a4 >> +#define _DVSBTILEOFF0x731a4 >> +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) >> #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) >> #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) >> #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) >> #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) >> + >> #define _DVSASURFLIVE 0x721ac >> +#define _DVSBSURFLIVE 0x731ac >> +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) >> + >> #define _DVSAGAMC_G4X 0x721e0 /* g4x */ >> +#define _DVSBGAMC_G4X 0x731e0 /* g4x */ >> +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, >> _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ >> + >> #define _DVSASCALE 0x72204 >> +#define _DVSBSCALE 0x73204 >> +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) >> #define DVS_SCALE_ENABLE REG_BIT(31) >> #define DVS_FILTER_MASK REG_GENMASK(30, 29) >> #define DVS_FILTER_MEDIUM REG_FIEL
Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the sprite plane register definitions such that everything > to do wiht the same register is in one place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++ > 1 file changed, 134 insertions(+), 97 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > index bb67705652b2..c27adbaf0f00 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h > @@ -7,6 +7,8 @@ > #include "intel_display_reg_defs.h" > > #define _DVSACNTR0x72180 > +#define _DVSBCNTR0x73180 > +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) > #define DVS_ENABLE REG_BIT(31) > #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) > #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) > @@ -28,31 +30,67 @@ > #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) > #define DVS_TILED REG_BIT(10) > #define DVS_DEST_KEY REG_BIT(2) > + > #define _DVSALINOFF 0x72184 > +#define _DVSBLINOFF 0x73184 > +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) > + > #define _DVSASTRIDE 0x72188 > +#define _DVSBSTRIDE 0x73188 > +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) > + > #define _DVSAPOS 0x7218c > +#define _DVSBPOS 0x7318c > +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) > #define DVS_POS_Y_MASK REG_GENMASK(31, 16) > #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, > (y)) > #define DVS_POS_X_MASK REG_GENMASK(15, 0) > #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, > (x)) > + > #define _DVSASIZE0x72190 > +#define _DVSBSIZE0x73190 > +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) > #define DVS_HEIGHT_MASKREG_GENMASK(31, 16) > #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, > (h)) > #define DVS_WIDTH_MASK REG_GENMASK(15, 0) > #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, > (w)) > + > #define _DVSAKEYVAL 0x72194 > +#define _DVSBKEYVAL 0x73194 > +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) > + > #define _DVSAKEYMSK 0x72198 > +#define _DVSBKEYMSK 0x73198 > +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) > + > #define _DVSASURF0x7219c > +#define _DVSBSURF0x7319c > +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) > #define DVS_ADDR_MASK REG_GENMASK(31, 12) > + > #define _DVSAKEYMAXVAL 0x721a0 > +#define _DVSBKEYMAXVAL 0x731a0 > +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) > + > #define _DVSATILEOFF 0x721a4 > +#define _DVSBTILEOFF 0x731a4 > +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) > #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DVS_OFFSET_Y(y)REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) > #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DVS_OFFSET_X(x)REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) > + > #define _DVSASURFLIVE0x721ac > +#define _DVSBSURFLIVE0x731ac > +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) > + > #define _DVSAGAMC_G4X0x721e0 /* g4x */ > +#define _DVSBGAMC_G4X0x731e0 /* g4x */ > +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) > + (5 - (i)) * 4) /* 6 x u0.8 */ > + > #define _DVSASCALE 0x72204 > +#define _DVSBSCALE 0x73204 > +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) > #define DVS_SCALE_ENABLE REG_BIT(31) > #define DVS_FILTER_MASKREG_GENMASK(30, 29) > #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) > @@ -64,42 +102,18 @@ > #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) > #define DVS_SRC_HEIGHT_MASKREG_GENMASK(10, 0) > #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) > + > #define _DVSAGAMC_ILK0x72300 /* ilk/snb */ > -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ > - >
Re: [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Add some notes indicatign which plane registers/bits are *indicating > valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula because I'm not going to chase through all the specs for these. ;) > --- > .../gpu/drm/i915/display/i9xx_plane_regs.h| 22 +-- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > index 929b26faf31e..d74a74d1f29a 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -37,53 +37,53 @@ > #define DISP_LINE_DOUBLE REG_BIT(20) > #define DISP_STEREO_POLARITY_SECONDREG_BIT(18) > #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ > -#define DISP_ROTATE_180REG_BIT(15) > +#define DISP_ROTATE_180REG_BIT(15) /* i965+ */ > #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ > -#define DISP_TILED REG_BIT(10) > +#define DISP_TILED REG_BIT(10) /* i965+ */ > #define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > #define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > > -#define _DSPAADDR0x70184 > +#define _DSPAADDR0x70184 /* pre-i965 */ > #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPAADDR) > > -#define _DSPALINOFF 0x70184 > +#define _DSPALINOFF 0x70184 /* i965+ */ > #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPALINOFF) > > #define _DSPASTRIDE 0x70188 > #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASTRIDE) > > -#define _DSPAPOS 0x7018C /* reserved */ > +#define _DSPAPOS 0x7018C /* pre-g4x */ > #define DSPPOS(plane)_MMIO_PIPE2(dev_priv, > plane, _DSPAPOS) > #define DISP_POS_Y_MASKREG_GENMASK(31, 16) > #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > #define DISP_POS_X_MASKREG_GENMASK(15, 0) > #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, > (x)) > > -#define _DSPASIZE0x70190 > +#define _DSPASIZE0x70190 /* pre-g4x */ > #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASIZE) > #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > #define DISP_WIDTH_MASKREG_GENMASK(15, 0) > #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, > (w)) > > -#define _DSPASURF0x7019C /* 965+ only */ > +#define _DSPASURF0x7019C /* i965+ */ > #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASURF) > #define DISP_ADDR_MASK REG_GENMASK(31, 12) > > -#define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPATILEOFF 0x701A4 /* i965+ */ > #define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, > _DSPATILEOFF) > #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) > #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) > > -#define _DSPAOFFSET 0x701A4 /* HSW */ > +#define _DSPAOFFSET 0x701A4 /* hsw+ */ > #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAOFFSET) > > -#define _DSPASURFLIVE0x701AC > +#define _DSPASURFLIVE0x701AC /* g4x+ */ > #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASURFLIVE) > > -#define _DSPAGAMC 0x701E0 > +#define _DSPAGAMC0x701E0 /* pre-g4x */ > #define DSPGAMC(plane, i)_MMIO_PIPE2(dev_priv, plane, > _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ > > /* CHV pipe B primary plane */ -- Jani Nikula, Intel
Re: [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the pre-skl primary plane register definitions > sensible, and toss in a few comments to indicate which > platforms have what. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/i9xx_plane_regs.h| 46 --- > 1 file changed, 29 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > index 0bf2cd42bce7..929b26faf31e 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -9,7 +9,10 @@ > #include "intel_display_reg_defs.h" > > #define _DSPAADDR_VLV0x7017C /* vlv/chv */ > +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAADDR_VLV) > + > #define _DSPACNTR0x70180 > +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPACNTR) > #define DISP_ENABLEREG_BIT(31) > #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) > #define DISP_FORMAT_MASK REG_GENMASK(29, 26) > @@ -39,60 +42,69 @@ > #define DISP_TILED REG_BIT(10) > #define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > #define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > + > #define _DSPAADDR0x70184 > +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPAADDR) > + > +#define _DSPALINOFF 0x70184 > +#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPALINOFF) > + > #define _DSPASTRIDE 0x70188 > +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASTRIDE) > + > #define _DSPAPOS 0x7018C /* reserved */ > +#define DSPPOS(plane)_MMIO_PIPE2(dev_priv, > plane, _DSPAPOS) > #define DISP_POS_Y_MASKREG_GENMASK(31, 16) > #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > #define DISP_POS_X_MASKREG_GENMASK(15, 0) > #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, > (x)) > + > #define _DSPASIZE0x70190 > +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASIZE) > #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) > #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) > #define DISP_WIDTH_MASKREG_GENMASK(15, 0) > #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, > (w)) > + > #define _DSPASURF0x7019C /* 965+ only */ > +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, > plane, _DSPASURF) > #define DISP_ADDR_MASK REG_GENMASK(31, 12) > + > #define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, > _DSPATILEOFF) > #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) > #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) > #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) > #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) > + > #define _DSPAOFFSET 0x701A4 /* HSW */ > +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPAOFFSET) > + > #define _DSPASURFLIVE0x701AC > +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, > _DSPASURFLIVE) > + > #define _DSPAGAMC0x701E0 > - > -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) > -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) > -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) > -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) > -#define DSPPOS(plane)_MMIO_PIPE2(dev_priv, plane, _DSPAPOS) > -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) > -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) > -#define DSPTILEOFF(plane)_MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) > -#define DSPLINOFF(plane) DSPADDR(plane) > -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) > -#define DSPSURFLIVE(plane) _MMIO_PIPE2(d
Re: [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > PIPEGCMAX was left behind when all other gamma registers moved > into intel_color_regs.h. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color_regs.h | 5 + > drivers/gpu/drm/i915/i915_reg.h | 4 > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h > b/drivers/gpu/drm/i915/display/intel_color_regs.h > index bb99ea533842..61c18b4a7fa5 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h > @@ -36,6 +36,11 @@ > _CHV_PALETTE_C, > _CHV_PALETTE_C) + \ > (i) * 4) > > +/* i965/g4x/vlv/chv */ > +#define _PIPEAGCMAX 0x70010 > +#define _PIPEBGCMAX 0x71010 > +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) > * 4) /* u1.16 */ > + > /* ilk+ palette */ > #define _LGC_PALETTE_A 0x4a000 > #define _LGC_PALETTE_B 0x4a800 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 52b029cd3981..f5e8833cc37e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1882,10 +1882,6 @@ > #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) > #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) > > -#define _PIPEAGCMAX 0x70010 > -#define _PIPEBGCMAX 0x71010 > -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) > * 4) /* u1.16 */ > - > #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ > #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, > _PIPE_ARB_CTL_A) > #define PIPE_ARB_USE_PROG_SLOTSREG_BIT(13) -- Jani Nikula, Intel
Re: [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Relocate all pre-skl primary plane register definitions > into their own declutter i915_reg.h. > > Cc: Zhenyu Wang > Cc: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + > .../gpu/drm/i915/display/i9xx_plane_regs.h| 98 +++ > .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + > drivers/gpu/drm/i915/display/intel_color.c| 2 +- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_fbc.c | 1 + > drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + > drivers/gpu/drm/i915/gvt/display.c| 1 + > drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + > drivers/gpu/drm/i915/gvt/handlers.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 87 +--- > drivers/gpu/drm/i915/intel_clock_gating.c | 1 + > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + > 13 files changed, 110 insertions(+), 87 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c > b/drivers/gpu/drm/i915/display/i9xx_plane.c > index ea4d8ba55ad8..1f05f9184cb2 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -10,6 +10,7 @@ > > #include "i915_reg.h" > #include "i9xx_plane.h" > +#include "i9xx_plane_regs.h" > #include "intel_atomic.h" > #include "intel_atomic_plane.h" > #include "intel_de.h" > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > new file mode 100644 > index ..0bf2cd42bce7 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h > @@ -0,0 +1,98 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __I9XX_PLANE_REGS_H__ > +#define __I9XX_PLANE_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +#define _DSPAADDR_VLV0x7017C /* vlv/chv */ > +#define _DSPACNTR0x70180 > +#define DISP_ENABLEREG_BIT(31) > +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) > +#define DISP_FORMAT_MASK REG_GENMASK(29, 26) > +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) > +#define DISP_FORMAT_BGRA555 > REG_FIELD_PREP(DISP_FORMAT_MASK, 3) > +#define DISP_FORMAT_BGRX555 > REG_FIELD_PREP(DISP_FORMAT_MASK, 4) > +#define DISP_FORMAT_BGRX565 > REG_FIELD_PREP(DISP_FORMAT_MASK, 5) > +#define DISP_FORMAT_BGRX888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 6) > +#define DISP_FORMAT_BGRA888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 7) > +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) > +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) > +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) > +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) > +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) > +#define DISP_FORMAT_RGBX888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 14) > +#define DISP_FORMAT_RGBA888 > REG_FIELD_PREP(DISP_FORMAT_MASK, 15) > +#define DISP_STEREO_ENABLE REG_BIT(25) > +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ > +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) > +#define DISP_PIPE_SEL(pipe) > REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) > +#define DISP_SRC_KEY_ENABLEREG_BIT(22) > +#define DISP_LINE_DOUBLE REG_BIT(20) > +#define DISP_STEREO_POLARITY_SECONDREG_BIT(18) > +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ > +#define DISP_ROTATE_180REG_BIT(15) > +#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ > +#define DISP_TILED REG_BIT(10) > +#define DISP_ASYNC_FLIPREG_BIT(9) /* g4x+ */ > +#define DISP_MIRRORREG_BIT(8) /* CHV pipe B */ > +#define _DSPAADDR0x70184 > +#define _DSPASTRIDE 0x70188 > +#define _DSPAPOS 0x7018C /* reserved */ > +#define DISP_POS_Y_MASKREG_GENMASK(31, 16) > +#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, > (y)) > +#define DISP_POS_
Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
On Wed, 15 May 2024, Jani Nikula wrote:
> The PCI ID macros in xe_pciids.h allow passing in the macro to operate
> on each PCI ID, making it more flexible. Convert i915_pciids.h to the
> same pattern.
>
> INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
> unconditionally uses INTEL_QUANTA_VGA_DEVICE().
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
Bjorn, since I asked for acks on the last ones, I probably should here
too. :)
I'm hoping to stop mucking with the macros after this.
BR,
Jani.
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
>
> ---
>
> Tip: It's probably easiest to apply and use 'git show --color-words' for
> review.
>
> This transformation is completely scripted:
>
> | #!/bin/bash
> |
> | FILE=include/drm/i915_pciids.h
> |
> | sed -i 's/[\t ]*\\/ \\/' $FILE
> |
> | sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
> |
> | sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
> |
> | sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ##
> __VA_ARGS__)/' $FILE
> |
> | # Special case: IVB Q transcode
> | sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
> |
> | # Change all users
> | for file in $(git grep -l "#include "); do
> | for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed
> 's/#define //'); do
> | sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
> | done
> | done
> ---
> arch/x86/kernel/early-quirks.c| 80 +-
> .../drm/i915/display/intel_display_device.c | 86 +-
> drivers/gpu/drm/i915/i915_pci.c | 150 +-
> drivers/gpu/drm/i915/intel_device_info.c | 88 +-
> include/drm/i915_pciids.h | 1348 -
> 5 files changed, 876 insertions(+), 876 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index fd74d7f26f01..1c137771c5d2 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops
> __initconst = {
>
> /* Intel integrated GPUs for which we need to reserve "stolen memory" */
> static const struct pci_device_id intel_early_ids[] __initconst = {
> - INTEL_I830_IDS(_early_ops),
> - INTEL_I845G_IDS(_early_ops),
> - INTEL_I85X_IDS(_early_ops),
> - INTEL_I865G_IDS(_early_ops),
> - INTEL_I915G_IDS(_early_ops),
> - INTEL_I915GM_IDS(_early_ops),
> - INTEL_I945G_IDS(_early_ops),
> - INTEL_I945GM_IDS(_early_ops),
> - INTEL_VLV_IDS(_early_ops),
> - INTEL_PNV_IDS(_early_ops),
> - INTEL_I965G_IDS(_early_ops),
> - INTEL_G33_IDS(_early_ops),
> - INTEL_I965GM_IDS(_early_ops),
> - INTEL_GM45_IDS(_early_ops),
> - INTEL_G45_IDS(_early_ops),
> - INTEL_ILK_IDS(_early_ops),
> - INTEL_SNB_IDS(_early_ops),
> - INTEL_IVB_IDS(_early_ops),
> - INTEL_HSW_IDS(_early_ops),
> - INTEL_BDW_IDS(_early_ops),
> - INTEL_CHV_IDS(_early_ops),
> - INTEL_SKL_IDS(_early_ops),
> - INTEL_BXT_IDS(_early_ops),
> - INTEL_KBL_IDS(_early_ops),
> - INTEL_CFL_IDS(_early_ops),
> - INTEL_WHL_IDS(_early_ops),
> - INTEL_CML_IDS(_early_ops),
> - INTEL_GLK_IDS(_early_ops),
> - INTEL_CNL_IDS(_early_ops),
> - INTEL_ICL_IDS(_early_ops),
> - INTEL_EHL_IDS(_early_ops),
> - INTEL_JSL_IDS(_early_ops),
> - INTEL_TGL_IDS(_early_ops),
> - INTEL_RKL_IDS(_early_ops),
> - INTEL_ADLS_IDS(_early_ops),
> - INTEL_ADLP_IDS(_early_ops),
> - INTEL_ADLN_IDS(_early_ops),
> - INTEL_RPLS_IDS(_early_ops),
> - INTEL_RPLU_IDS(_early_ops),
> - INTEL_RPLP_IDS(_early_ops),
> + INTEL_I830_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I845G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I85X_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I865G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I915G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I945G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_VLV_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_PNV_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I965G_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_G33_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_GM45_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_G45_IDS(INTEL_VGA_DEVICE, _early_ops),
> + INTEL_ILK_IDS(INTEL_VGA_DEVICE, _early_ops),
>
Re: [PATCH v5 6/6] drm/i915/alpm: Add debugfs for LOBF
On Mon, 20 May 2024, Animesh Manna wrote:
> For validation purpose add debugfs for LOBF.
>
> v1: Initial version.
> v2: Add aux-wake/less info along with lobf status. [Jouni]
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> .../drm/i915/display/intel_display_debugfs.c | 2 +
> 3 files changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 8f4da817ef55..843ffb5fcb7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -360,3 +360,52 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
> {
> lnl_alpm_configure(intel_dp, crtc_state);
> }
> +
> +static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
> +{
> + struct intel_connector *connector = m->private;
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct drm_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + enum transcoder cpu_transcoder;
> + u32 alpm_ctl;
> + int ret;
> +
> + ret =
> drm_modeset_lock_single_interruptible(_priv->drm.mode_config.connection_mutex);
> + if (ret)
> + return ret;
> +
> + crtc = connector->base.state->crtc;
> + if (connector->base.status != connector_status_connected || !crtc) {
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + crtc_state = to_intel_crtc_state(crtc->state);
> + cpu_transcoder = crtc_state->cpu_transcoder;
> + alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));
> + seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl &
> ALPM_CTL_LOBF_ENABLE));
> + seq_printf(m, "Aux-wake alpm status: %s\n",
> +str_enabled_disabled(!(alpm_ctl &
> ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
> + seq_printf(m, "Aux-less alpm status: %s\n",
> +str_enabled_disabled(alpm_ctl &
> ALPM_CTL_ALPM_AUX_LESS_ENABLE));
> +out:
> + drm_modeset_unlock(_priv->drm.mode_config.connection_mutex);
> +
> + return ret;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
> +
> +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
This file is about alpm, and might add more alpm related debugfs files
later. There's no need to encode lobf in the name here.
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct dentry *root = connector->base.debugfs_entry;
> +
> + if (DISPLAY_VER(i915) < 20 ||
> + connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
> + return;
> +
> + debugfs_create_file("i915_edp_lobf_info", 0444, root,
Why does the filename need to include edp? The connector debugfs files
for psr don't include that either.
> + connector, _edp_lobf_info_fops);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index fd9be8aa876c..0dab2068164a 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -11,6 +11,7 @@
> struct intel_dp;
> struct intel_crtc_state;
> struct drm_connector_state;
> +struct intel_connector;
>
> void intel_alpm_get_capability(struct intel_dp *intel_dp);
> bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> @@ -20,4 +21,5 @@ void intel_alpm_compute_lobf_config(struct intel_dp
> *intel_dp,
> struct drm_connector_state *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 35f9f86ef70f..86d9900c40af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -13,6 +13,7 @@
> #include "i915_debugfs.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_alpm.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_crtc_state_dump.h"
> @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector
> *connector)
> intel_drrs_connector_debugfs_add(connector);
> intel_pps_connector_debugfs_add(connector);
> intel_psr_connector_debugfs_add(connector);
> + intel_alpm_lobf_debugfs_add(connector);
All the others are intel_foo_connector_debugfs_add(). So should this.
>
> if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> connector_type == DRM_MODE_CONNECTOR_HDMIA ||
--
Jani Nikula, Intel
Re: [PATCH v5 4/6] drm/i915/alpm: Add compute config for lobf
struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0ad6134ba94e..d77a9f22b5c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1410,6 +1410,9 @@ struct intel_crtc_state {
>
> /* for loading single buffered registers during vblank */
> struct drm_vblank_work vblank_work;
> +
> + /* LOBF flag */
> + bool has_lobf;
> };
>
> enum intel_pipe_crc_source {
> @@ -1845,6 +1848,8 @@ struct intel_dp {
> u8 silence_period_sym_clocks;
> u8 lfps_half_cycle_num_of_syms;
> } alpm_parameters;
> +
> + u8 alpm_dpcd;
> };
>
> enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c0a3b6d50681..61ee66ad8bd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -48,6 +48,7 @@
> #include "i915_drv.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_alpm.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_backlight.h"
> @@ -3000,6 +3001,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> intel_vrr_compute_config(pipe_config, conn_state);
> intel_dp_compute_as_sdp(intel_dp, pipe_config);
> intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> + intel_alpm_compute_lobf_config(intel_dp, pipe_config, conn_state);
> intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
> conn_state);
> @@ -6616,6 +6618,8 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
>
> intel_pps_init_late(intel_dp);
>
> + intel_alpm_get_capability(intel_dp);
> +
> return true;
>
> out_vdd_off:
--
Jani Nikula, Intel
Re: [PATCH 0/7] drm/i915: DSC stuff
On Fri, 17 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Respect the VBT's edp_disable_dsc bit, and do a bunch > of refactoring around checking for DSC support. > > Also threw in a bonus cleanup to intel_dp_has_audio() > that caught my eye. The dropping of const here and there sticks out a bit, but with that explained or fixed, the series is Reviewed-by: Jani Nikula > > Ville Syrjälä (7): > drm/i915: Drop redundant dsc_decompression_aux check > drm/i915: Extract intel_dp_has_dsc() > drm/i915: Handle MST in intel_dp_has_dsc() > drm/i915: Use intel_dp_has_dsc() during .compute_config() > drm/i915: Reuse intel_dp_supports_dsc() for MST > drm/i915: Utilize edp_disable_dsc from VBT > drm/i915: Remove bogus MST check in intel_dp_has_audio() > > drivers/gpu/drm/i915/display/intel_bios.c | 4 ++ > .../drm/i915/display/intel_display_types.h| 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 42 +-- > drivers/gpu/drm/i915/display/intel_dp.h | 4 ++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--- > 5 files changed, 44 insertions(+), 30 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 7/7] drm/i915: Remove bogus MST check in intel_dp_has_audio()
On Fri, 17 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No idea what this MST checks is doing in intel_dp_has_audio().
> Looks completely pointless, so get rid of it.
2e775f2d41ef ("drm/i915/display: update intel_dp_has_audio to support MST")
6297ee90f682 ("drm/i915/display: configure SDP split for DP-MST")
The division of changes here is not ideal, but I presume the goal was to
not do functional changes compared to intel_dp_mst_has_audio(). Which
may or may not be a good reason...
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index af298d5017d9..4a486bb6d48c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2806,7 +2806,6 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
> }
>
> static bool intel_dp_has_audio(struct intel_encoder *encoder,
> -struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> @@ -2815,8 +2814,7 @@ static bool intel_dp_has_audio(struct intel_encoder
> *encoder,
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
>
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> - !intel_dp_port_has_audio(i915, encoder->port))
> + if (!intel_dp_port_has_audio(i915, encoder->port))
> return false;
>
> if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
> @@ -2875,7 +2873,7 @@ intel_dp_audio_compute_config(struct intel_encoder
> *encoder,
> struct drm_connector_state *conn_state)
> {
> pipe_config->has_audio =
> - intel_dp_has_audio(encoder, pipe_config, conn_state) &&
> + intel_dp_has_audio(encoder, conn_state) &&
> intel_audio_compute_config(encoder, pipe_config, conn_state);
>
> pipe_config->sdp_split_enable = pipe_config->has_audio &&
--
Jani Nikula, Intel
Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()
On Fri, 17 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract a helper to check whether the source+sink combo
> supports DSC. That basic check is needed both during mode
> validation and compute config. We'll also need to add extra
> checks to both places, so having a single place for it is nicer.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1e88449fe5f2..7bf283b4df7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1220,6 +1220,19 @@ bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> connector->force_bigjoiner_enable;
> }
>
> +static bool intel_dp_has_dsc(struct intel_connector *connector)
Why not const?
> +{
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +
> + if (!HAS_DSC(i915))
> + return false;
> +
> + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
> + return false;
> +
> + return true;
> +}
> +
> static enum drm_mode_status
> intel_dp_mode_valid(struct drm_connector *_connector,
> struct drm_display_mode *mode)
> @@ -1274,8 +1287,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> mode_rate = intel_dp_link_required(target_clock,
>
> intel_dp_mode_min_output_bpp(connector, mode));
>
> - if (HAS_DSC(dev_priv) &&
> - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
> + if (intel_dp_has_dsc(connector)) {
> enum intel_output_format sink_format, output_format;
> int pipe_bpp;
--
Jani Nikula, Intel
Re: [PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. *max There's also ADL-S with display 12 and 6 Gbps support? BR, Jani. > Bump our limit to match. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 0faf2afa1c09..bd0ba4edcd1d 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct > intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > int max_tmds_clock, vbt_max_tmds_clock; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(dev_priv) >= 13) > + max_tmds_clock = 60; > + else if (DISPLAY_VER(dev_priv) >= 10) > max_tmds_clock = 594000; > else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) > max_tmds_clock = 30; -- Jani Nikula, Intel
Re: [PATCH 1/5] drm/i915: Rename all bigjoiner to joiner
On Mon, 20 May 2024, Stanislav Lisovskiy wrote:
> Lets unify both bigjoiner and ultrajoiner under simple "joiner" name,
> because in future we might have multiple configurations, involving
> multiple bigjoiners, ultrajoiner, however it is possible to use
> same api for handling both.
If you're doing a big rename, might as well do the master/slave ->
primary/secondary rename too.
BR,
Jani.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
> .../drm/i915/display/intel_crtc_state_dump.c | 8 +-
> drivers/gpu/drm/i915/display/intel_cursor.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 204 +-
> drivers/gpu/drm/i915/display/intel_display.h | 8 +-
> .../drm/i915/display/intel_display_debugfs.c | 10 +-
> .../drm/i915/display/intel_display_types.h| 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 60 +++---
> drivers/gpu/drm/i915/display/intel_dp.h | 8 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +-
> drivers/gpu/drm/i915/display/intel_drrs.c | 6 +-
> .../drm/i915/display/intel_modeset_setup.c| 38 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
> drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c| 4 +-
> 19 files changed, 207 insertions(+), 207 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 27224ecdc94c..7a0b2f3a672e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -335,7 +335,7 @@ void intel_plane_copy_uapi_to_hw_state(struct
> intel_plane_state *plane_state,
> intel_plane_clear_hw_state(plane_state);
>
> /*
> - * For the bigjoiner slave uapi.crtc will point at
> + * For the joiner slave uapi.crtc will point at
>* the master crtc. So we explicitly assign the right
>* slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
>* the plane is logically enabled on the uapi level.
> @@ -720,7 +720,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
> + if (new_crtc_state && intel_crtc_is_joiner_slave(new_crtc_state)) {
> struct intel_crtc *master_crtc =
> intel_master_crtc(new_crtc_state);
> struct intel_plane *master_plane =
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..36fb7ad1d871 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2731,7 +2731,7 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> min_cdclk = max_t(int, min_cdclk,
> DIV_ROUND_UP(crtc_state->pixel_rate,
> num_vdsc_instances));
>
> - if (crtc_state->bigjoiner_pipes) {
> + if (crtc_state->joiner_pipes) {
> int pixel_clock =
> intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
>
> /*
> @@ -2743,13 +2743,13 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>*
>* => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner
> Interface bits)
>*
> - * Since PPC = 2 with bigjoiner
> + * Since PPC = 2 with joiner
>* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> Interface bits
>*/
> - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
> 24;
> + int joiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
> int min_cdclk_bj =
> (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16)
> *
> - pixel_clock) / (2 * bigjoiner_interface_bits);
> + pixel_clock) / (2 * joiner_interface_bits);
>
> min_cdclk = max(min_cdclk, min_cdclk_bj);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ccaa4cb2809b..a999c37293bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -222,10 +222,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> transcoder_name(pipe_config->master_transcoder),
>
Re: [PATCH 05/13] drm/i915: Rename selective fetch plane registers
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Rename the selective fetch plane registers to match the spec. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++-- > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 47e3a2e2977c..f0bd0a726d7a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -276,23 +276,23 @@ > _SEL_FETCH_PLANE_BASE_A(plane)) > > #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_CTL_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) > +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) > > #define _SEL_FETCH_PLANE_POS_1_A 0x70894 > -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_POS_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_SIZE_1_A0x70898 > -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_SIZE_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > _SEL_FETCH_PLANE_OFFSET_1_A - > \ > _SEL_FETCH_PLANE_BASE_1_A) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index d0bfee2ca643..6601baf18ae4 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct > intel_plane *plane, > if (!crtc_state->enable_psr2_sel_fetch) > return; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); > } > > static void > @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = (clip->y1 + plane_state->uapi.dst.y1) << 16; > val |= plane_state->uapi.dst.x1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); > > x = plane_state->view.color_plane[color_plane].x; > > @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = y << 16 | x; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), > val); > > /* Sizes are 0 based */ > val = (drm_rect_height(clip) - 1) << 16; > val |= (drm_rect_width(_state->uapi.src) >> 16) - 1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); > } > > static void > @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct > intel_plane *plane, > return; > > if (drm_rect_height(_state->psr2_sel_fetch_area) > 0) > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), > - PLANE_SEL_FETCH_CTL_ENABLE); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), > + SEL_FETCH_PLANE_CTL_ENABLE); > else > icl_plane_disable_sel_fetch_arm(plane, crtc_state); > } -- Jani Nikula, Intel
Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
On Mon, 20 May 2024, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range.
>> so using _MMIO_TRANS2() for it is not really correct. Also since this
>> is a pipe register, and not present on CHV, the registers will be
>> equally spaced out, so we can use the simpler _MMIO_PIPE() instead
>> of _MMIO_PIPE2().
>>
>> Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani Nikula
Side note, while reviewing this I found this monstrosity:
static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (!dev_priv->display.params.enable_psr2_sel_fetch &&
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(_priv->drm,
"PSR2 sel fetch not enabled, disabled by
parameter\n");
return false;
}
if (crtc_state->uapi.async_flip) {
drm_dbg_kms(_priv->drm,
"PSR2 sel fetch not enabled, async flip enabled\n");
return false;
}
return crtc_state->enable_psr2_sel_fetch = true;
}
Judging by name, a predicate function to check if config is valid,
actually modifies the config in what looks like a typoed return
statement. Ugh.
BR,
Jani.
--
Jani Nikula, Intel
Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range. > so using _MMIO_TRANS2() for it is not really correct. Also since this > is a pipe register, and not present on CHV, the registers will be > equally spaced out, so we can use the simpler _MMIO_PIPE() instead > of _MMIO_PIPE2(). > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++-- > 3 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c > b/drivers/gpu/drm/i915/display/intel_cursor.c > index b44809899502..7983cbaf83f7 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > @@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane, > > intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); > > - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), > + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), > PIPESRC_HEIGHT(et_y_position)); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index df0d14a5023f..d49e869f6be2 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -2381,7 +2381,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct > intel_crtc_state *crtc_st > if (!crtc_state->enable_psr2_su_region_et) > return; > > - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe), > + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), > crtc_state->pipe_srcsz_early_tpt); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index e14cb48f2614..47e3a2e2977c 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -248,8 +248,8 @@ > > /* PSR2 Early transport */ > #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 > - > -#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, > _PIPE_SRCSZ_ERLY_TPT_A) > +#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 > +#define PIPE_SRCSZ_ERLY_TPT(pipe)_MMIO_PIPE((pipe), > _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) > > #define _SEL_FETCH_PLANE_BASE_1_A0x70890 > #define _SEL_FETCH_PLANE_BASE_2_A0x708B0 -- Jani Nikula, Intel
Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
On Thu, 16 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Split the cursor stuff from the rest of the selective fetch
> plane registers so that we can collect all cursor registers
> in intel_cursor_regs.h. Also take the opportunity to rename
> the registers to match the spec.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> b/drivers/gpu/drm/i915/display/intel_cursor.c
> index c780ce146131..b44809899502 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct
> intel_plane *plane,
> if (!crtc_state->enable_psr2_sel_fetch)
> return;
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
> }
>
> static void wa_16021440873(struct intel_plane *plane,
> @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
> ctl &= ~MCURSOR_MODE_MASK;
> ctl |= MCURSOR_MODE_64_2B;
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
>
> intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> PIPESRC_HEIGHT(et_y_position));
> @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
> intel_plane *plane,
> val);
> }
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
> plane->id),
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
> plane_state->ctl);
> } else {
> /* Wa_16021440873 */
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index 270c26c2e6df..ab02d497fba6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -95,4 +95,9 @@
> #define _CUR_BUF_CFG_B 0x7117c
> #define CUR_BUF_CFG(pipe)_MMIO_PIPE((pipe), _CUR_BUF_CFG_A,
> _CUR_BUF_CFG_B)
>
> +#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> +#define _SEL_FETCH_CUR_CTL_B 0x71880
> +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe),
> _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
_SEL_FETCH_CUR_CTL_A is doubled, the latter should be _B.
With that,
Reviewed-by: Jani Nikula
I must admit I was trying to follow how PLANE_SEL_FETCH_CTL(pipe,
CURSOR_A) ends up being identical to this new SEL_FETCH_CUR_CTL(pipe),
but holy crap it trips my brain completely. How did we come up with so
many levels of abstractions for this stuff, in such complicated ways?!
:o
> +#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
> +
> #endif /* __INTEL_CURSOR_REGS_H__ */
--
Jani Nikula, Intel
Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the cursor register defines such that everything to > do with one register is in one place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula but a couple of nitpicks inline... > --- > .../gpu/drm/i915/display/intel_cursor_regs.h | 52 +-- > 1 file changed, 26 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > index c2190af1e9f5..270c26c2e6df 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > @@ -9,6 +9,7 @@ > #include "intel_display_reg_defs.h" > > #define _CURACNTR0x70080 > +#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CURACNTR) In addition to code movement, these add braces around (dev_priv) and (pipe). While it makes review harder by breaking 'git show --color-moved', I also think it's kind of unnecessary when they're only passed on as parameters. Or is there some corner case where it matters? Comma has the lowest precedence, and I don't think you could easily pass in a value with a comma operator. No need to change for this, it's not wrong either. > /* Old style CUR*CNTR flags (desktop 8xx) */ > #define CURSOR_ENABLE REG_BIT(31) > #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) > @@ -38,61 +39,60 @@ > #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) > #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) > #define MCURSOR_MODE_64_ARGB_AX(0x20 | MCURSOR_MODE_64_32B_AX) > + > #define _CURABASE0x70084 > +#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CURABASE) > + > #define _CURAPOS 0x70088 > -#define _CURAPOS_ERLY_TPT0x7008c > +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CURAPOS) > #define CURSOR_POS_Y_SIGN REG_BIT(31) > #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) > #define CURSOR_POS_Y(y)REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) > #define CURSOR_POS_X_SIGN REG_BIT(15) > #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) > #define CURSOR_POS_X(x)REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) > + > +#define _CURAPOS_ERLY_TPT0x7008c > +#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), > (pipe), _CURAPOS_ERLY_TPT) > + > #define _CURASIZE0x700a0 /* 845/865 */ > +#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CURASIZE) > #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) > #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) > #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) > #define CURSOR_WIDTH(w)REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) > + > #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ > +#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CUR_FBC_CTL_A) > #define CUR_FBC_EN REG_BIT(31) > #define CUR_FBC_HEIGHT_MASKREG_GENMASK(7, 0) > #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) > + > #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ > +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CUR_CHICKEN_A) > + > #define _CURASURFLIVE0x700ac /* g4x+ */ > -#define _CURBCNTR0x700c0 > -#define _CURBBASE0x700c4 > -#define _CURBPOS 0x700c8 > - > -#define _CURBCNTR_IVB0x71080 > -#define _CURBBASE_IVB0x71084 > -#define _CURBPOS_IVB 0x71088 > - > -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) > -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) > -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) > -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, > _CURAPOS_ERLY_TPT) > -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) > -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, > _CUR_FBC_CTL_A) > -#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, > _CUR_CHICKEN_A) > -#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, > _CURASURFLIVE) > +#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), > _CURASURFLIVE) > > /* skl+ */ > #define _CUR_WM_A_0 0x70140 > #define _CUR_WM_B_0 0x71140 > +#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_
Re: [PATCH v2 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
On Fri, 17 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
> of unnecessary head scratching. Add aliases using the skl+ plane
> names.
> And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
> as we only ever have 0-2 sprites per pipe on those platforms.
>
> v2: Don't break icl_nv12_y_plane_mask() (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++
> .../drm/i915/display/intel_display_limits.h | 21 ---
> .../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c| 19 -
> 5 files changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 339010384b86..ca6dc1dc56c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - primary = skl_universal_plane_create(dev_priv, pipe,
> - PLANE_PRIMARY);
> + primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
> else
> primary = intel_primary_plane_create(dev_priv, pipe);
> if (IS_ERR(primary)) {
> @@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> struct intel_plane *plane;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - plane = skl_universal_plane_create(dev_priv, pipe,
> -PLANE_SPRITE0 +
> sprite);
> + plane = skl_universal_plane_create(dev_priv, pipe,
> PLANE_2 + sprite);
> else
> plane = intel_sprite_plane_create(dev_priv, pipe,
> sprite);
> if (IS_ERR(plane)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cce1420fb541..ee2df655b0ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct
> intel_crtc_state *crtc_state)
> linked_state->uapi.dst = plane_state->uapi.dst;
>
> if (icl_is_hdr_plane(dev_priv, plane->id)) {
> - if (linked->id == PLANE_SPRITE5)
> + if (linked->id == PLANE_7)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
> - else if (linked->id == PLANE_SPRITE4)
> + else if (linked->id == PLANE_6)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
> - else if (linked->id == PLANE_SPRITE3)
> + else if (linked->id == PLANE_5)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
> - else if (linked->id == PLANE_SPRITE2)
> + else if (linked->id == PLANE_4)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
> else
> MISSING_CASE(linked->id);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h
> b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index 5126d0b5ae5d..c4775c99dc83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -60,16 +60,23 @@ enum transcoder {
> * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> */
> enum plane_id {
> - PLANE_PRIMARY,
> - PLANE_SPRITE0,
> - PLANE_SPRITE1,
> - PLANE_SPRITE2,
> - PLANE_SPRITE3,
> - PLANE_SPRITE4,
> - PLANE_SPRITE5,
> + /* skl+ universal plane names */
> + PLANE_1,
> + PLANE_2,
> + PLANE_3,
> + PLANE_4,
> + PLANE_5,
> + PLANE_6,
> + PLANE_7,
> +
> PLANE_CURSOR,
>
> I915_MAX_PLANES,
> +
> + /* pre-skl plane names */
> + PLANE_PRIMARY = PLANE_1,
> + PLANE_SPRITE0,
> + PLANE_SPRITE1,
> };
>
> enum port {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_u
Re: [PATCH v2 1/3] drm/print: Add generic drm dev printk function
On Fri, 17 May 2024, Michal Wajdeczko wrote:
> We already have some drm printk functions that need to duplicate
> a code to get a similar format of the final result, for example:
>
> [ ] :00:00.0: [drm:foo] bar
> [ ] :00:00.0: [drm] foo bar
> [ ] :00:00.0: [drm] *ERROR* foo
>
> Add a generic __drm_dev_vprintk() function that can format the
> final message like all other existing function do and allows us
> to keep the formatting code in one place.
>
> Cc: Jani Nikula
> Signed-off-by: Michal Wajdeczko
Reviewed-by: Jani Nikula
> ---
> v2: make it static, keep it simple and use braces (Jani)
> ---
> drivers/gpu/drm/drm_print.c | 52 +
> 1 file changed, 30 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
> index cf2efb44722c..41892491a12c 100644
> --- a/drivers/gpu/drm/drm_print.c
> +++ b/drivers/gpu/drm/drm_print.c
> @@ -176,6 +176,32 @@ void __drm_printfn_seq_file(struct drm_printer *p,
> struct va_format *vaf)
> }
> EXPORT_SYMBOL(__drm_printfn_seq_file);
>
> +static void __drm_dev_vprintk(const struct device *dev, const char *level,
> + const void *origin, const char *prefix,
> + struct va_format *vaf)
> +{
> + const char *prefix_pad = prefix ? " " : "";
> +
> + if (!prefix)
> + prefix = "";
> +
> + if (dev) {
> + if (origin)
> + dev_printk(level, dev, "[" DRM_NAME ":%ps]%s%s %pV",
> +origin, prefix_pad, prefix, vaf);
> + else
> + dev_printk(level, dev, "[" DRM_NAME "]%s%s %pV",
> +prefix_pad, prefix, vaf);
> + } else {
> + if (origin)
> + printk("%s" "[" DRM_NAME ":%ps]%s%s %pV",
> +level, origin, prefix_pad, prefix, vaf);
> + else
> + printk("%s" "[" DRM_NAME "]%s%s %pV",
> +level, prefix_pad, prefix, vaf);
> + }
> +}
> +
> void __drm_printfn_info(struct drm_printer *p, struct va_format *vaf)
> {
> dev_info(p->arg, "[" DRM_NAME "] %pV", vaf);
> @@ -187,19 +213,12 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
> va_format *vaf)
> const struct drm_device *drm = p->arg;
> const struct device *dev = drm ? drm->dev : NULL;
> enum drm_debug_category category = p->category;
> - const char *prefix = p->prefix ?: "";
> - const char *prefix_pad = p->prefix ? " " : "";
>
> if (!__drm_debug_enabled(category))
> return;
>
> /* Note: __builtin_return_address(0) is useless here. */
> - if (dev)
> - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME "]%s%s %pV",
> -prefix_pad, prefix, vaf);
> - else
> - printk(KERN_DEBUG "[" DRM_NAME "]%s%s %pV",
> -prefix_pad, prefix, vaf);
> + __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
> }
> EXPORT_SYMBOL(__drm_printfn_dbg);
>
> @@ -287,12 +306,7 @@ void drm_dev_printk(const struct device *dev, const char
> *level,
> vaf.fmt = format;
> vaf.va =
>
> - if (dev)
> - dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
> -__builtin_return_address(0), );
> - else
> - printk("%s" "[" DRM_NAME ":%ps] %pV",
> -level, __builtin_return_address(0), );
> + __drm_dev_vprintk(dev, level, __builtin_return_address(0), NULL, );
>
> va_end(args);
> }
> @@ -312,12 +326,7 @@ void __drm_dev_dbg(struct _ddebug *desc, const struct
> device *dev,
> vaf.fmt = format;
> vaf.va =
>
> - if (dev)
> - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV",
> - __builtin_return_address(0), );
> - else
> - printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
> -__builtin_return_address(0), );
> + __drm_dev_vprintk(dev, KERN_DEBUG, __builtin_return_address(0), NULL,
> );
>
> va_end(args);
> }
> @@ -351,8 +360,7 @@ void __drm_err(const char *format, ...)
> vaf.fmt = format;
> vaf.va =
>
> - printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV",
> -__builtin_return_address(0), );
> + __drm_dev_vprintk(NULL, KERN_ERR, __builtin_return_address(0),
> "*ERROR*", );
>
> va_end(args);
> }
--
Jani Nikula, Intel
Re: [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
On Thu, 16 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
> of unnecessary head scratching. Add aliases using the skl+ plane
> names.
> And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
> as we only ever have 0-2 sprites per pipe on those platforms.
Should these be changed too?
- intel_plane_set_ckey()
- for_each_plane_id_on_crtc()
I'm not sure. But there's one real issue:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 32d10e62b2b9..d0bfee2ca643 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
> alpha)
> static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
> - return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> + return BIT(PLANE_6) | BIT(PLANE_7);
> else
> - return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
> + return BIT(PLANE_4) | BIT(PLANE_5);
The if branches got swapped?
BR,
Jani.
--
Jani Nikula, Intel
Re: [PATCH 3/3] drm/i915: Don't use __func__ as prefix for drm_dbg_printer
On Fri, 17 May 2024, Michal Wajdeczko wrote:
> Updated code of drm_dbg_printer() is already printing symbolic
> name of the caller like drm_dbg() does.
>
> Signed-off-by: Michal Wajdeczko
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 6161f7a3ff70..735cd23a43c6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1025,7 +1025,7 @@ void intel_gt_set_wedged(struct intel_gt *gt)
>
> if (GEM_SHOW_DEBUG()) {
> struct drm_printer p = drm_dbg_printer(>i915->drm,
> -DRM_UT_DRIVER, __func__);
> +DRM_UT_DRIVER, NULL);
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
> b/drivers/gpu/drm/i915/gt/selftest_context.c
> index 12eca750f7d0..5eb46700dc4e 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_context.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_context.c
> @@ -286,7 +286,7 @@ static int __live_active_context(struct intel_engine_cs
> *engine)
>
> if (intel_engine_pm_is_awake(engine)) {
> struct drm_printer p = drm_dbg_printer(>i915->drm,
> -DRM_UT_DRIVER, __func__);
> +DRM_UT_DRIVER, NULL);
>
> intel_engine_dump(engine, ,
> "%s is still awake:%d after idle-barriers\n",
--
Jani Nikula, Intel
Re: [PATCH 2/3] drm/print: Improve drm_dbg_printer
On Fri, 17 May 2024, Michal Wajdeczko wrote:
> With recent introduction of a generic drm dev printk function, we
> can now store and use location where drm_dbg_printer was invoked
> and output it's symbolic name like we do for all drm debug prints.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Jani Nikula
> ---
> drivers/gpu/drm/drm_print.c | 3 +--
> include/drm/drm_print.h | 2 ++
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
> index a2b60c8245a1..0a205fdee7cf 100644
> --- a/drivers/gpu/drm/drm_print.c
> +++ b/drivers/gpu/drm/drm_print.c
> @@ -191,8 +191,7 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
> va_format *vaf)
> if (!__drm_debug_enabled(category))
> return;
>
> - /* Note: __builtin_return_address(0) is useless here. */
> - __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
> + __drm_dev_vprintk(dev, KERN_DEBUG, p->origin, p->prefix, vaf);
> }
> EXPORT_SYMBOL(__drm_printfn_dbg);
>
> diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
> index bb1801c58544..761ce01761b7 100644
> --- a/include/drm/drm_print.h
> +++ b/include/drm/drm_print.h
> @@ -175,6 +175,7 @@ struct drm_printer {
> void (*printfn)(struct drm_printer *p, struct va_format *vaf);
> void (*puts)(struct drm_printer *p, const char *str);
> void *arg;
> + const void *origin;
> const char *prefix;
> enum drm_debug_category category;
> };
> @@ -332,6 +333,7 @@ static inline struct drm_printer drm_dbg_printer(struct
> drm_device *drm,
> struct drm_printer p = {
> .printfn = __drm_printfn_dbg,
> .arg = drm,
> + .origin = (void *)_THIS_IP_, /* it's fine as we will be inlined
> */
Not that it makes a difference, but I guess I'd cast to (const void *)
to match the member.
Reviewed-by: Jani Nikula
> .prefix = prefix,
> .category = category,
> };
--
Jani Nikula, Intel
Re: [PATCH 1/3] drm/print: Add generic drm dev printk function
On Fri, 17 May 2024, Michal Wajdeczko wrote:
> We already have some drm printk functions that need to duplicate
> a code to get a similar format of the final result, for example:
>
> [ ] :00:00.0: [drm:foo] bar
> [ ] :00:00.0: [drm] foo bar
> [ ] :00:00.0: [drm] *ERROR* foo
>
> Add a generic __drm_dev_vprintk() function that can format the
> final message like all other existing function do and allows us
> to keep the formatting code in one place.
Nice idea!
> Signed-off-by: Michal Wajdeczko
> Cc: Jani Nikula
> ---
> drivers/gpu/drm/drm_print.c | 49 -
> include/drm/drm_print.h | 3 +++
> 2 files changed, 30 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
> index cf2efb44722c..a2b60c8245a1 100644
> --- a/drivers/gpu/drm/drm_print.c
> +++ b/drivers/gpu/drm/drm_print.c
> @@ -187,19 +187,12 @@ void __drm_printfn_dbg(struct drm_printer *p, struct
> va_format *vaf)
> const struct drm_device *drm = p->arg;
> const struct device *dev = drm ? drm->dev : NULL;
> enum drm_debug_category category = p->category;
> - const char *prefix = p->prefix ?: "";
> - const char *prefix_pad = p->prefix ? " " : "";
>
> if (!__drm_debug_enabled(category))
> return;
>
> /* Note: __builtin_return_address(0) is useless here. */
> - if (dev)
> - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME "]%s%s %pV",
> -prefix_pad, prefix, vaf);
> - else
> - printk(KERN_DEBUG "[" DRM_NAME "]%s%s %pV",
> -prefix_pad, prefix, vaf);
> + __drm_dev_vprintk(dev, KERN_DEBUG, NULL, p->prefix, vaf);
> }
> EXPORT_SYMBOL(__drm_printfn_dbg);
>
> @@ -277,6 +270,29 @@ void drm_print_bits(struct drm_printer *p, unsigned long
> value,
> }
> EXPORT_SYMBOL(drm_print_bits);
>
> +void __drm_dev_vprintk(const struct device *dev, const char *level,
> +const void *origin, const char *prefix,
> +struct va_format *vaf)
> +{
> + const char *prefix_pad = prefix ? " " : (prefix = "");
Too clever, please just keep it simple:
const char *prefix_pad = prefix ? " " : "";
if (!prefix)
prefix = "";
> +
> + if (dev)
> + if (origin)
> + dev_printk(level, dev, "[" DRM_NAME ":%ps]%s%s %pV",
> +origin, prefix_pad, prefix, vaf);
> + else
> + dev_printk(level, dev, "[" DRM_NAME "]%s%s %pV",
> +prefix_pad, prefix, vaf);
> + else
> + if (origin)
> + printk("%s" "[" DRM_NAME ":%ps]%s%s %pV",
> +level, origin, prefix_pad, prefix, vaf);
> + else
> + printk("%s" "[" DRM_NAME "]%s%s %pV",
> +level, prefix_pad, prefix, vaf);
I'd sprinkle a few curly braces around the top level if-else blocks.
Side note, feels like using DRM_NAME makes things harder, not
easier. But that's for another patch.
> +}
> +EXPORT_SYMBOL(__drm_dev_vprintk);
AFAICT this could be a non-exported static function. And probably moved
earlier in the file to not require a declaration.
BR,
Jani.
> +
> void drm_dev_printk(const struct device *dev, const char *level,
> const char *format, ...)
> {
> @@ -287,12 +303,7 @@ void drm_dev_printk(const struct device *dev, const char
> *level,
> vaf.fmt = format;
> vaf.va =
>
> - if (dev)
> - dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
> -__builtin_return_address(0), );
> - else
> - printk("%s" "[" DRM_NAME ":%ps] %pV",
> -level, __builtin_return_address(0), );
> + __drm_dev_vprintk(dev, level, __builtin_return_address(0), NULL, );
>
> va_end(args);
> }
> @@ -312,12 +323,7 @@ void __drm_dev_dbg(struct _ddebug *desc, const struct
> device *dev,
> vaf.fmt = format;
> vaf.va =
>
> - if (dev)
> - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV",
> -__builtin_return_address(0), );
> - else
> - printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
> -__builtin_return_addres
Re: [PATCH] drm/i915/selftests: Set always_coherent to false when reading from CPU
On Fri, 17 May 2024, Nirmoy Das wrote:
> Hi Jani,
>
> On 5/17/2024 9:39 AM, Jani Nikula wrote:
>> On Thu, 16 May 2024, Nirmoy Das wrote:
>>> The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
>> "previous commit" is a fairly vague reference once this gets
>> committed. It's not going to be "previous" in any meaningful sense.
>>
>> Please just start with:
>>
>> Commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
>> was not complete...
>
> Will do that.
>
>
>>
>> And probably add:
>>
>> Fixes: 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
>
> Do we need Fixes for selftest ? I always assumed it is not required as
> this code is for debug/CI
Maybe not for stuff that's already in stable, but we do run CI on
drm-next and -rc kernels, and if this causes issues there, why not have
them fixed?
BR,
Jani.
>
>
> Thanks,
>
> Nirmoy
>
>>
>> BR,
>> Jani.
>>
>>> correct caching mode.")' was not complete as for non LLC sharing platforms
>>> cpu read can happen from LLC which probably doesn't have the latest
>>> changes made by GPU.
>>>
>>> Cc: Andi Shyti
>>> Cc: Janusz Krzysztofik
>>> Cc: Jonathan Cavitt
>>> Signed-off-by: Nirmoy Das
>>> ---
>>> drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>>> index 65a931ea80e9..3527b8f446fe 100644
>>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>>> @@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
>>> if (err)
>>> goto out_file;
>>>
>>> - mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
>>> + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
>>> vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
>>> if (IS_ERR(vaddr)) {
>>> err = PTR_ERR(vaddr);
--
Jani Nikula, Intel
Re: [PATCH] drm/i915/selftests: Set always_coherent to false when reading from CPU
On Thu, 16 May 2024, Nirmoy Das wrote:
> The previous commit 'commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick
"previous commit" is a fairly vague reference once this gets
committed. It's not going to be "previous" in any meaningful sense.
Please just start with:
Commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
was not complete...
And probably add:
Fixes: 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
BR,
Jani.
> correct caching mode.")' was not complete as for non LLC sharing platforms
> cpu read can happen from LLC which probably doesn't have the latest
> changes made by GPU.
>
> Cc: Andi Shyti
> Cc: Janusz Krzysztofik
> Cc: Jonathan Cavitt
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> index 65a931ea80e9..3527b8f446fe 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
> @@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
> if (err)
> goto out_file;
>
> - mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
> + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
> vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
> if (IS_ERR(vaddr)) {
> err = PTR_ERR(vaddr);
--
Jani Nikula, Intel
Re: [PATCH 0/8] drm/i915: pass dev_priv explicitly to CUR* registers
On Wed, 15 May 2024, Ville Syrjälä wrote: > On Wed, May 15, 2024 at 02:56:40PM +0300, Jani Nikula wrote: >> Update all the register macros in the intel_cursor_regs.h file. >> >> Jani Nikula (8): >> drm/i915: pass dev_priv explicitly to CURCNTR >> drm/i915: pass dev_priv explicitly to CURBASE >> drm/i915: pass dev_priv explicitly to CURPOS >> drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT >> drm/i915: pass dev_priv explicitly to CURSIZE >> drm/i915: pass dev_priv explicitly to CUR_FBC_CTL >> drm/i915: pass dev_priv explicitly to CUR_CHICKEN >> drm/i915: pass dev_priv explicitly to CURSURFLIVE > > Series is > Reviewed-by: Ville Syrjälä Thanks, pushed to din. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
On Wed, 15 May 2024, Dave Hansen wrote: > On 5/15/24 07:25, Jani Nikula wrote: >> No reply from Bjorn, Cc: the x86 maintainers and list, could I get an >> ack from you please? > > x86 is just a consumer of the drm/i915_pciids.h macros. The name change > is perfectly fine with me. No objections. But I really don't think you > need our acks to move forward. > > Either way: > > Acked-by: Dave Hansen # for x86 Thanks, I know the changes are benign, but it's just that I tend to err on the side of getting the acks rather than stepping on anyone's toes. :) BR, Jani. -- Jani Nikula, Intel
[PATCH 2/2] drm/i915: stop redefining INTEL_VGA_DEVICE
Now that the PCI ID macros allow us to pass in the macro to use, stop
redefining INTEL_VGA_DEVICE.
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_device.c | 87 +-
drivers/gpu/drm/i915/intel_device_info.c | 91 +--
2 files changed, 88 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 950e66cdba0a..cf093bc0cb28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev)
return pci_match_id(ids, pdev);
}
-#undef INTEL_VGA_DEVICE
-#define INTEL_VGA_DEVICE(id, info) { id, info }
+#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) }
static const struct {
u32 devid;
const struct intel_display_device_info *info;
} intel_display_ids[] = {
- INTEL_I830_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I845G_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I85X_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I865G_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I915G_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I945G_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I965G_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_G33_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_GM45_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_G45_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_PNV_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, _d_display),
- INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, _m_display),
- INTEL_SNB_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_IVB_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_HSW_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_VLV_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_BDW_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_CHV_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_SKL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_BXT_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_GLK_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_KBL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_CFL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_WHL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_CML_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_ICL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_EHL_IDS(INTEL_VGA_DEVICE, _ehl_display),
- INTEL_JSL_IDS(INTEL_VGA_DEVICE, _ehl_display),
- INTEL_TGL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_DG1_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_RKL_IDS(INTEL_VGA_DEVICE, _display),
- INTEL_ADLS_IDS(INTEL_VGA_DEVICE, _s_display),
- INTEL_RPLS_IDS(INTEL_VGA_DEVICE, _s_display),
- INTEL_ADLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
- INTEL_ADLN_IDS(INTEL_VGA_DEVICE, _lpd_display),
- INTEL_RPLU_IDS(INTEL_VGA_DEVICE, _lpd_display),
- INTEL_RPLP_IDS(INTEL_VGA_DEVICE, _lpd_display),
- INTEL_DG2_IDS(INTEL_VGA_DEVICE, _hpd_display),
+ INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, _d_display),
+ INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, _m_display),
+ INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, _display),
+ INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, _ehl_display
[PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros
The PCI ID macros in xe_pciids.h allow passing in the macro to operate
on each PCI ID, making it more flexible. Convert i915_pciids.h to the
same pattern.
INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
unconditionally uses INTEL_QUANTA_VGA_DEVICE().
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
Tip: It's probably easiest to apply and use 'git show --color-words' for
review.
This transformation is completely scripted:
| #!/bin/bash
|
| FILE=include/drm/i915_pciids.h
|
| sed -i 's/[\t ]*\\/ \\/' $FILE
|
| sed -i 's/^\(#define [A-Za-z0-9_]\+\)_IDS(info)/\1_IDS(MACRO__, ...)/' $FILE
|
| sed -i 's/^\t\([A-Za-z0-9_]\+\)(info)/\t\1(MACRO__, ## __VA_ARGS__)/' $FILE
|
| sed -i 's/^\tINTEL_VGA_DEVICE(\([A-Fa-f0-9x]\+\), info)/\tMACRO__(\1, ##
__VA_ARGS__)/' $FILE
|
| # Special case: IVB Q transcode
| sed -i 's/^\t\(INTEL_QUANTA_VGA_DEVICE\)(MACRO__, ## /\t\1(/' $FILE
|
| # Change all users
| for file in $(git grep -l "#include "); do
| for macro in $(git grep -ho "#define [A-Za-z0-9_]\+_IDS" $FILE | sed
's/#define //'); do
| sed -i "s/$macro(/$macro(INTEL_VGA_DEVICE, /" $file
| done
| done
---
arch/x86/kernel/early-quirks.c| 80 +-
.../drm/i915/display/intel_display_device.c | 86 +-
drivers/gpu/drm/i915/i915_pci.c | 150 +-
drivers/gpu/drm/i915/intel_device_info.c | 88 +-
include/drm/i915_pciids.h | 1348 -
5 files changed, 876 insertions(+), 876 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index fd74d7f26f01..1c137771c5d2 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops
__initconst = {
/* Intel integrated GPUs for which we need to reserve "stolen memory" */
static const struct pci_device_id intel_early_ids[] __initconst = {
- INTEL_I830_IDS(_early_ops),
- INTEL_I845G_IDS(_early_ops),
- INTEL_I85X_IDS(_early_ops),
- INTEL_I865G_IDS(_early_ops),
- INTEL_I915G_IDS(_early_ops),
- INTEL_I915GM_IDS(_early_ops),
- INTEL_I945G_IDS(_early_ops),
- INTEL_I945GM_IDS(_early_ops),
- INTEL_VLV_IDS(_early_ops),
- INTEL_PNV_IDS(_early_ops),
- INTEL_I965G_IDS(_early_ops),
- INTEL_G33_IDS(_early_ops),
- INTEL_I965GM_IDS(_early_ops),
- INTEL_GM45_IDS(_early_ops),
- INTEL_G45_IDS(_early_ops),
- INTEL_ILK_IDS(_early_ops),
- INTEL_SNB_IDS(_early_ops),
- INTEL_IVB_IDS(_early_ops),
- INTEL_HSW_IDS(_early_ops),
- INTEL_BDW_IDS(_early_ops),
- INTEL_CHV_IDS(_early_ops),
- INTEL_SKL_IDS(_early_ops),
- INTEL_BXT_IDS(_early_ops),
- INTEL_KBL_IDS(_early_ops),
- INTEL_CFL_IDS(_early_ops),
- INTEL_WHL_IDS(_early_ops),
- INTEL_CML_IDS(_early_ops),
- INTEL_GLK_IDS(_early_ops),
- INTEL_CNL_IDS(_early_ops),
- INTEL_ICL_IDS(_early_ops),
- INTEL_EHL_IDS(_early_ops),
- INTEL_JSL_IDS(_early_ops),
- INTEL_TGL_IDS(_early_ops),
- INTEL_RKL_IDS(_early_ops),
- INTEL_ADLS_IDS(_early_ops),
- INTEL_ADLP_IDS(_early_ops),
- INTEL_ADLN_IDS(_early_ops),
- INTEL_RPLS_IDS(_early_ops),
- INTEL_RPLU_IDS(_early_ops),
- INTEL_RPLP_IDS(_early_ops),
+ INTEL_I830_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I845G_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I85X_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I865G_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I915G_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I915GM_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I945G_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I945GM_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_VLV_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_PNV_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I965G_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_G33_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_I965GM_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_GM45_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_G45_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_ILK_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_SNB_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_IVB_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_HSW_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_BDW_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_CHV_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_SKL_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_BXT_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_KBL_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_CFL_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_WHL_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_CML_IDS(INTEL_VGA_DEVICE, _early_ops),
+ INTEL_GLK_IDS(INTEL_VGA_DEVICE, _early_ops),
+ IN
Re: [PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
On Wed, 15 May 2024, Bjorn Helgaas wrote: > Sorry, I had ignored this because I didn't think it affected any PCI > stuff. This is fine with me: > > Acked-by: Bjorn Helgaas Thanks, pushed to drm-intel-next. > But since you asked :), I'll gripe again about the fact that this > intel_early_ids[] list needs continual maintenance, which is not the > way things are supposed to work. Long thread about it here: > > https://lore.kernel.org/linux-pci/20201104120506.172447-1-tejaskumarx.surendrakumar.upadh...@intel.com/t/#u Right. I was under the impression we'd cease doing this for new platforms, and see if we can get away with it. For example, we don't have Meteorlake or Lunarlake there. Fingers crossed. But we probably don't want to touch the old stuff. Except now that I'm doing some non-functional refactoring to be able to better reuse the macros for something else. There's a bit more coming, please bear with me. :) I just tend to err on the side of getting the acks than pushing away. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
On Fri, 10 May 2024, Jani Nikula wrote: > On Fri, 10 May 2024, Jani Nikula wrote: >> This is a spin-off from [1], including just the PCI ID macro cleanups, >> as well as adding a bunch more cleanups. >> >> BR, >> Jani. >> >> [1] https://lore.kernel.org/all/cover.1715086509.git.jani.nik...@intel.com/ >> >> >> Jani Nikula (8): >> drm/i915/pciids: add INTEL_PNV_IDS(), use acronym >> drm/i915/pciids: add INTEL_ILK_IDS(), use acronym >> drm/i915/pciids: add INTEL_SNB_IDS() >> drm/i915/pciids: add INTEL_IVB_IDS() >> drm/i915/pciids: don't include WHL/CML PCI IDs in CFL >> drm/i915/pciids: remove 11 from INTEL_ICL_IDS() >> drm/i915/pciids: remove 12 from INTEL_TGL_IDS() >> drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P >> >> arch/x86/kernel/early-quirks.c| 19 +++--- > > Bjorn, ack for merging this via drm-intel-next? No reply from Bjorn, Cc: the x86 maintainers and list, could I get an ack from you please? I'd like to get these PCI ID macro changes moving forward, I've got more work pending on this. Lore link to the whole series [1]. Thanks, Jani. [1] https://lore.kernel.org/r/cover.1715340032.git.jani.nik...@intel.com > >> .../drm/i915/display/intel_display_device.c | 20 +++--- >> drivers/gpu/drm/i915/i915_pci.c | 13 ++-- >> drivers/gpu/drm/i915/intel_device_info.c | 3 +- >> include/drm/i915_pciids.h | 67 --- >> 5 files changed, 71 insertions(+), 51 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
On Wed, 15 May 2024, Gustavo Sousa wrote: > Quoting Gustavo Sousa (2024-05-15 10:23:54-03:00) >>Quoting Mika Kahola (2024-05-15 03:45:23-03:00) >>>As a preparation to remove .clock member from pll state >>>structure, let's move the port clock calculation on better >>>location > > Ah... Also, I noticed that we are not simply moving the implementation > of port calculation functions with this patch. We are also replacing > usage of the "clock" members with function calls. I think the message > subject and body should be reworded. No, code movement is one patch, replacing .clock usage with function calls is another patch, and removing .clock is yet another patch. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 17/20] drm/i915/dp: Add debugfs entries to set a target link rate/lane count
struct link_config_limits *limits)
> {
> - limits->min_rate = intel_dp_common_rate(intel_dp, 0);
> + limits->min_rate = intel_dp_min_link_rate(intel_dp);
> limits->max_rate = intel_dp_max_link_rate(intel_dp);
>
> /* FIXME 128b/132b SST support missing */
> limits->max_rate = min(limits->max_rate, 81);
> + limits->min_rate = min(limits->min_rate, limits->max_rate);
>
> - limits->min_lane_count = 1;
> + limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
> limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
>
> limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> @@ -2307,8 +2350,10 @@ intel_dp_compute_config_limits(struct intel_dp
> *intel_dp,
>* configuration, and typically on older panels these
>* values correspond to the native resolution of the panel.
>*/
> - limits->min_lane_count = limits->max_lane_count;
> - limits->min_rate = limits->max_rate;
> + if (intel_dp->requested_lane_count == 0)
> + limits->min_lane_count = limits->max_lane_count;
> + if (intel_dp->requested_link_rate == 0)
> + limits->min_rate = limits->max_rate;
> }
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> @@ -2947,7 +2992,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
> intel_dp->lane_count = lane_count;
> }
>
> -static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp)
> +void intel_dp_reset_link_train_params(struct intel_dp *intel_dp)
> {
> intel_dp->link_train.max_lane_count =
> intel_dp_max_common_lane_count(intel_dp);
> intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 7c938327fc725..2b639bb2f56ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -95,6 +95,7 @@ void intel_edp_backlight_off(const struct
> drm_connector_state *conn_state);
> void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
> void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
> void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
> +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
> int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> int intel_dp_max_lane_count(struct intel_dp *intel_dp);
> int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
> @@ -104,6 +105,7 @@ int intel_dp_max_common_lane_count(struct intel_dp
> *intel_dp);
> int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
> int intel_dp_rate_index(const int *rates, int len, int rate);
> void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
> +void intel_dp_reset_link_train_params(struct intel_dp *intel_dp);
>
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> u8 *link_bw, u8 *rate_select);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index b80fb25b9204d..352c77f46015e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1114,6 +1114,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp,
> int current_rate)
> int rate_index;
> int new_rate;
>
> + if (intel_dp->requested_link_rate)
> + return -1;
> +
> rate_index = intel_dp_rate_index(intel_dp->common_rates,
>intel_dp->num_common_rates,
>current_rate);
> @@ -1132,6 +1135,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp,
> int current_rate)
>
> static int reduce_lane_count(struct intel_dp *intel_dp, int
> current_lane_count)
> {
> + if (intel_dp->requested_lane_count)
> + return -1;
> +
> if (current_lane_count > 1)
> return current_lane_count >> 1;
--
Jani Nikula, Intel
Re: [PATCH 04/20] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values()
intel_dp->link_train.max_lane_count = lane_count >> 1;
> - } else {
> + new_lane_count = crtc_state->lane_count;
> + new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
> + if (new_link_rate < 0) {
> + new_lane_count = reduce_lane_count(intel_dp,
> crtc_state->lane_count);
> + new_link_rate = intel_dp_max_common_rate(intel_dp);
> + }
> +
> + if (new_lane_count < 0) {
> drm_err(>drm, "Link Training Unsuccessful\n");
> return -1;
> }
>
> + if (intel_dp_is_edp(intel_dp) &&
> + !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
> new_lane_count)) {
> + drm_dbg_kms(>drm,
> + "Retrying Link training for eDP with same
> parameters\n");
> + return 0;
> + }
> +
> + drm_dbg_kms(>drm, "Reducing link parameters from %dx%d to
> %dx%d\n",
> + crtc_state->port_clock, crtc_state->lane_count,
> + new_link_rate, new_lane_count);
> +
> + intel_dp->link_train.max_rate = new_link_rate;
> + intel_dp->link_train.max_lane_count = new_lane_count;
> +
> return 0;
> }
>
> @@ -1178,9 +1200,7 @@ static void
> intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
> lt_dbg(intel_dp, DP_PHY_DPRX,
> "Link Training failed with HOBL active, not enabling it
> from now on\n");
> intel_dp->hobl_failed = true;
> - } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> -
> crtc_state->port_clock,
> -
> crtc_state->lane_count)) {
> + } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> crtc_state)) {
> return;
> }
--
Jani Nikula, Intel
Re: [PATCH 02/20] drm/i915/dp: Move link train params to a substruct in intel_dp
+1382,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
> {
> int len;
>
> - len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
> + len = intel_dp_common_len_rate_limit(intel_dp,
> intel_dp->link_train.max_rate);
>
> return intel_dp_common_rate(intel_dp, len - 1);
> }
> @@ -3017,10 +3017,10 @@ void intel_dp_set_link_params(struct intel_dp
> *intel_dp,
> intel_dp->lane_count = lane_count;
> }
>
> -static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
> +static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp)
> {
> - intel_dp->max_link_lane_count =
> intel_dp_max_common_lane_count(intel_dp);
> - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> + intel_dp->link_train.max_lane_count =
> intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp);
> }
>
> /* Enable backlight PWM and backlight PP control. */
> @@ -3355,7 +3355,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
> intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
>
> if (crtc_state)
> - intel_dp_reset_max_link_params(intel_dp);
> + intel_dp_reset_link_train_params(intel_dp);
> }
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> @@ -5888,7 +5888,7 @@ intel_dp_detect(struct drm_connector *connector,
>* supports link training fallback params.
>*/
> if (intel_dp->reset_link_params || intel_dp->is_mst) {
> - intel_dp_reset_max_link_params(intel_dp);
> + intel_dp_reset_link_train_params(intel_dp);
> intel_dp->reset_link_params = false;
> }
>
> @@ -6740,7 +6740,7 @@ intel_dp_init_connector(struct intel_digital_port
> *dig_port,
>
> intel_dp_set_source_rates(intel_dp);
> intel_dp_set_common_rates(intel_dp);
> - intel_dp_reset_max_link_params(intel_dp);
> + intel_dp_reset_link_train_params(intel_dp);
>
> /* init MST on ports that can support it */
> intel_dp_mst_encoder_init(dig_port,
--
Jani Nikula, Intel
[PATCH 8/8] drm/i915: pass dev_priv explicitly to CURSURFLIVE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSURFLIVE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 13 +
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 3e948526e9ab..c2190af1e9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -73,7 +73,7 @@
#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CUR_FBC_CTL_A)
#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CUR_CHICKEN_A)
-#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
+#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CURASURFLIVE)
/* skl+ */
#define _CUR_WM_A_00x70140
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 98dfd537070c..df0d14a5023f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2352,7 +2352,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
* but testing proved that it works for up display 13, for newer
* than that testing will be needed.
*/
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+ intel_de_write(dev_priv, CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0);
}
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
*crtc_state)
@@ -3100,7 +3100,9 @@ static void _psr_invalidate_handle(struct intel_dp
*intel_dp)
if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
/* Send one update otherwise lag is observed in screen
*/
- intel_de_write(dev_priv,
CURSURFLIVE(intel_dp->psr.pipe), 0);
+ intel_de_write(dev_priv,
+ CURSURFLIVE(dev_priv,
intel_dp->psr.pipe),
+ 0);
return;
}
@@ -3110,7 +3112,8 @@ static void _psr_invalidate_handle(struct intel_dp
*intel_dp)
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
val);
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+ intel_de_write(dev_priv,
+ CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0);
intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
} else {
intel_psr_exit(intel_dp);
@@ -3210,7 +3213,9 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv,
cpu_transcoder),
val);
- intel_de_write(dev_priv,
CURSURFLIVE(intel_dp->psr.pipe), 0);
+ intel_de_write(dev_priv,
+ CURSURFLIVE(dev_priv,
intel_dp->psr.pipe),
+ 0);
intel_dp->psr.psr2_sel_fetch_cff_enabled =
false;
}
} else {
--
2.39.2
[PATCH 7/8] drm/i915: pass dev_priv explicitly to CUR_CHICKEN
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CUR_CHICKEN register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 40b01205e247..3e948526e9ab 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -72,7 +72,7 @@ #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) /* skl+ */ -- 2.39.2
[PATCH 6/8] drm/i915: pass dev_priv explicitly to CUR_FBC_CTL
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CUR_FBC_CTL register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 3 ++-
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 8553f6164760..c780ce146131 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -646,7 +646,8 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
plane->cursor.size != fbc_ctl ||
plane->cursor.cntl != cntl) {
if (HAS_CUR_FBC(dev_priv))
- intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
+ intel_de_write_fw(dev_priv,
+ CUR_FBC_CTL(dev_priv, pipe),
fbc_ctl);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 7c3a76f5151d..40b01205e247 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -71,7 +71,7 @@
#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CURAPOS_ERLY_TPT)
#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
-#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
+#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CUR_FBC_CTL_A)
#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5ea1fbc2e981..b485976976db 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -154,9 +154,9 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(CURBASE(dev_priv, PIPE_A));
MMIO_D(CURBASE(dev_priv, PIPE_B));
MMIO_D(CURBASE(dev_priv, PIPE_C));
- MMIO_D(CUR_FBC_CTL(PIPE_A));
- MMIO_D(CUR_FBC_CTL(PIPE_B));
- MMIO_D(CUR_FBC_CTL(PIPE_C));
+ MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A));
+ MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_B));
+ MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C));
MMIO_D(_MMIO(0x700ac));
MMIO_D(_MMIO(0x710ac));
MMIO_D(_MMIO(0x720ac));
--
2.39.2
[PATCH 5/8] drm/i915: pass dev_priv explicitly to CURSIZE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURSIZE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f8baf25c4a4f..8553f6164760 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -297,7 +297,7 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
- intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
+ intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 0d1ee13ec066..7c3a76f5151d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -70,7 +70,7 @@
#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CURAPOS_ERLY_TPT)
-#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
+#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
--
2.39.2
[PATCH 4/8] drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURPOS_ERLY_TPT register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 4 +++-
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 17039d37dc91..f8baf25c4a4f 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -543,7 +543,9 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
intel_plane *plane,
if (crtc_state->enable_psr2_su_region_et) {
u32 val = intel_cursor_position(crtc_state, plane_state,
true);
- intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
+ intel_de_write_fw(dev_priv,
+ CURPOS_ERLY_TPT(dev_priv, pipe),
+ val);
}
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
plane->id),
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index d0fa251ae8c4..0d1ee13ec066 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -69,7 +69,7 @@
#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
-#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
+#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe,
_CURAPOS_ERLY_TPT)
#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
--
2.39.2
[PATCH 3/8] drm/i915: pass dev_priv explicitly to CURPOS
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURPOS register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 8
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c| 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 573bbdec3e3d..17039d37dc91 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -298,14 +298,14 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
plane->cursor.base = base;
plane->cursor.size = size;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
}
}
@@ -647,14 +647,14 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
fbc_ctl);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
plane->cursor.base = base;
plane->cursor.size = fbc_ctl;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 4a7e27f0c3c1..d0fa251ae8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -68,7 +68,7 @@
#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
-#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
+#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 60f368affb6c..e78de423a6c7 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -384,7 +384,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
return -EINVAL;
}
- val = vgpu_vreg_t(vgpu, CURPOS(pipe));
+ val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe));
plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index f562172995a6..5ea1fbc2e981 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -148,9 +148,9 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(CURCNTR(dev_priv, PIPE_A));
MMIO_D(CURCNTR(dev_priv, PIPE_B));
MMIO_D(CURCNTR(dev_priv, PIPE_C));
- MMIO_D(CURPOS(PIPE_A));
- MMIO_D(CURPOS(PIPE_B));
- MMIO_D(CURPOS(PIPE_C));
+ MMIO_D(CURPOS(dev_priv, PIPE_A));
+ MMIO_D(CURPOS(dev_priv, PIPE_B));
+ MMIO_D(CURPOS(dev_priv, PIPE_C));
MMIO_D(CURBASE(dev_priv, PIPE_A));
MMIO_D(CURBASE(dev_priv, PIPE_B));
MMIO_D(CURBASE(dev_priv, PIPE_C));
--
2.39.2
[PATCH 2/8] drm/i915: pass dev_priv explicitly to CURBASE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURBASE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c| 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 31cb614b6ba8..573bbdec3e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -296,7 +296,7 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
plane->cursor.size != size ||
plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
- intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
@@ -648,14 +648,14 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
fbc_ctl);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
- intel_de_write_fw(dev_priv, CURBASE(pipe), base);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
plane->cursor.base = base;
plane->cursor.size = fbc_ctl;
plane->cursor.cntl = cntl;
} else {
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
- intel_de_write_fw(dev_priv, CURBASE(pipe), base);
+ intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 5f522a4ecc2e..4a7e27f0c3c1 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -67,7 +67,7 @@
#define _CURBPOS_IVB 0x71088
#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
-#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
+#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6e226ea1afa2..60f368affb6c 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -373,7 +373,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
alpha_plane, alpha_force);
- plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
+ plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) &
I915_GTT_PAGE_MASK;
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 18deaf416b7e..f562172995a6 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -151,9 +151,9 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(CURPOS(PIPE_A));
MMIO_D(CURPOS(PIPE_B));
MMIO_D(CURPOS(PIPE_C));
- MMIO_D(CURBASE(PIPE_A));
- MMIO_D(CURBASE(PIPE_B));
- MMIO_D(CURBASE(PIPE_C));
+ MMIO_D(CURBASE(dev_priv, PIPE_A));
+ MMIO_D(CURBASE(dev_priv, PIPE_B));
+ MMIO_D(CURBASE(dev_priv, PIPE_C));
MMIO_D(CUR_FBC_CTL(PIPE_A));
MMIO_D(CUR_FBC_CTL(PIPE_B));
MMIO_D(CUR_FBC_CTL(PIPE_C));
--
2.39.2
[PATCH 1/8] drm/i915: pass dev_priv explicitly to CURCNTR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURCNTR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cursor.c | 10 +-
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/gvt/display.c | 8
drivers/gpu/drm/i915/gvt/fb_decoder.c| 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
6 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 3ecab15d1431..31cb614b6ba8 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -295,11 +295,11 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
if (plane->cursor.base != base ||
plane->cursor.size != size ||
plane->cursor.cntl != cntl) {
- intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
- intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
plane->cursor.base = base;
plane->cursor.size = size;
@@ -328,7 +328,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane
*plane,
if (!wakeref)
return false;
- ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
+ ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) &
CURSOR_ENABLE;
*pipe = PIPE_A;
@@ -646,7 +646,7 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
if (HAS_CUR_FBC(dev_priv))
intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
fbc_ctl);
- intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
+ intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(pipe), base);
@@ -684,7 +684,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
+ val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe));
ret = val & MCURSOR_MODE_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index a478ef5787c5..5f522a4ecc2e 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -66,7 +66,7 @@
#define _CURBBASE_IVB 0x71084
#define _CURBPOS_IVB 0x71088
-#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
+#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e29073b90860..cce1420fb541 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8238,9 +8238,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
drm_WARN_ON(_priv->drm,
intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
drm_WARN_ON(_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_A)) &
MCURSOR_MODE_MASK);
+ intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) &
MCURSOR_MODE_MASK);
drm_WARN_ON(_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_B)) &
MCURSOR_MODE_MASK);
+ intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) &
MCURSOR_MODE_MASK);
intel_de_write(dev_priv, TRANSCONF(pipe), 0);
intel_de_posting_read(dev_priv, TRANSCONF(pipe));
diff --git a/drivers/gpu/drm/i915/gvt/display.c
b/drivers/gpu/drm/i915/gvt/display.c
index 527e0bb2b15e..73ea8be0f80b 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -194,8 +194,8 @@ static void emulate_monitor_status_change(struct intel_vgpu
*vgpu)
~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
[PATCH 0/8] drm/i915: pass dev_priv explicitly to CUR* registers
Update all the register macros in the intel_cursor_regs.h file. Jani Nikula (8): drm/i915: pass dev_priv explicitly to CURCNTR drm/i915: pass dev_priv explicitly to CURBASE drm/i915: pass dev_priv explicitly to CURPOS drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT drm/i915: pass dev_priv explicitly to CURSIZE drm/i915: pass dev_priv explicitly to CUR_FBC_CTL drm/i915: pass dev_priv explicitly to CUR_CHICKEN drm/i915: pass dev_priv explicitly to CURSURFLIVE drivers/gpu/drm/i915/display/intel_cursor.c | 33 ++- .../gpu/drm/i915/display/intel_cursor_regs.h | 16 - drivers/gpu/drm/i915/display/intel_display.c | 4 +-- drivers/gpu/drm/i915/display/intel_psr.c | 13 +--- drivers/gpu/drm/i915/gvt/display.c| 8 ++--- drivers/gpu/drm/i915/gvt/fb_decoder.c | 6 ++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 +++--- 7 files changed, 56 insertions(+), 48 deletions(-) -- 2.39.2
Re: [PATCH] drm/edid: remove drm_do_get_edid()
On Tue, 14 May 2024, Thomas Zimmermann wrote: > Am 13.05.24 um 22:27 schrieb Jani Nikula: >> All users of drm_do_get_edid() have been converted to >> drm_edid_read_custom(). Remove the unused function to prevent new users >> from creeping in. >> >> Signed-off-by: Jani Nikula > > Reviewed-by: Thomas Zimmermann Thanks, pushed to drm-misc-next. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Having the plane WM/DDB regitster write functions in skl_watermarks.c
> is rather annoying when trying to implement DSB based plane updates.
> Move them into the respective files that handle all other plane
> register writes. Less places where I need to worry about the DSB
> vs. MMIO decisions.
>
> The downside is that we spread the wm struct details a bit further
> afield. But if that becomes too annoying we can probably abstract
> things a bit more with a few extra functions.
>
> Signed-off-by: Ville Syrjälä
[snip]
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> index e92e00c01b29..8eb4521ee851 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> @@ -12,6 +12,8 @@ struct drm_i915_private;
> struct intel_crtc;
> struct intel_initial_plane_config;
> struct intel_plane_state;
> +struct skl_ddb_entry;
> +struct skl_wm_level;
>
> enum pipe;
> enum plane_id;
> @@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> u8 icl_hdr_plane_mask(void);
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
> plane_id);
>
> +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
> +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
Yeah, I don't much like interfaces that return register values for
registers that aren't even known... but let's see how this pans out. It
does what it says on the box.
Reviewed-by: Jani Nikula
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1daceb8ef9de..2064f72da675 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct
> intel_crtc_state *crtc_state)
> return data_rate;
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id,
> int level)
> @@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> return >wm[level];
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id)
> {
> @@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state
> *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> -static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> -{
> - if (!entry->end)
> - return 0;
> -
> - return PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start);
> -}
> -
> -static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> -{
> - u32 val = 0;
> -
> - if (level->enable)
> - val |= PLANE_WM_EN;
> - if (level->ignore_lines)
> - val |= PLANE_WM_IGNORE_LINES;
> - val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> - val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
> -
> - return val;
> -}
> -
> -void skl_write_plane_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> - enum plane_id plane_id = plane->id;
> - enum pipe pipe = plane->pipe;
> - const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
> - const struct skl_ddb_entry *ddb =
> - _state->wm.skl.plane_ddb[plane_id];
> - const struct skl_ddb_entry *ddb_y =
> - _state->wm.skl.plane_ddb_y[plane_id];
> - int level;
> -
> - for (level = 0; level < i915->display.wm.num_levels; level++)
> - intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> -
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> -
> - intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
> -
> - if (HAS_HW_SAGV_WM(i915)) {
> - const struct skl_plane_wm *wm = _wm->planes[plane_id];
> -
> - intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> - skl_plane_wm_reg_val(>sagv.wm0));
> - intel_de_write_fw(i915, PLANE_WM_SAGV_TRA
