Re: mem_region_request failed for hypervisor memory in jetson-tx2 kit

[Claudio Scordino]

Dear Jan, dear Saroj,

sorry for the late reply.

On Thu, Jan 30, 2020 at 9:17 AM Jan Kiszka  wrote:

> On 29.01.20 21:45, Saroj Sapkota wrote:
> > NO, its 8GB-version and its iomem is:
> > 0210-02100fff : /axip2p@210
> > 0211-02110fff : /axip2p@211
> > 0212-02120fff : /axip2p@212
> > 0213-02130fff : /axip2p@213
> > 0214-02140fff : /axip2p@214
> > 0215-02150fff : /axip2p@215
> > 0216-02160fff : /axip2p@216
> > 0217-02170fff : /axip2p@217
> > 0218-02180fff : /axip2p@218
> > 0219-02190fff : /axip2p@219
> > 0220-0220 : security
> > 0221-0221 : gpio
> > 0239-02390fff : /axi2apb@239
> > 023a-023a0fff : /axi2apb@23a
> > 023b-023b0fff : /axi2apb@23b
> > 023c-023c0fff : /axi2apb@23c
> > 023d-023d0fff : /axi2apb@23d
> > 0243-02444fff : /pinmux@243
> > 0260-0280 : /dma@260
> > 02900800-02900fff : /aconnect@2a41000/ahub
> > 02901000-029010ff : /aconnect@2a41000/ahub/i2s@2901000
> > 02901100-029011ff : /aconnect@2a41000/ahub/i2s@2901100
> > 02901200-029012ff : /aconnect@2a41000/ahub/i2s@2901200
> > 02901300-029013ff : /aconnect@2a41000/ahub/i2s@2901300
> > 02901400-029014ff : /aconnect@2a41000/ahub/i2s@2901400
> > 02901500-029015ff : /aconnect@2a41000/ahub/i2s@2901500
> > 02902000-029021ff : /aconnect@2a41000/ahub/sfc@2902000
> > 02902200-029023ff : /aconnect@2a41000/ahub/sfc@2902200
> > 02902400-029025ff : /aconnect@2a41000/ahub/sfc@2902400
> > 02902600-029027ff : /aconnect@2a41000/ahub/sfc@2902600
> > 02903000-029030ff : /aconnect@2a41000/ahub/amx@2903000
> > 02903100-029031ff : /aconnect@2a41000/ahub/amx@2903100
> > 02903200-029032ff : /aconnect@2a41000/ahub/amx@2903200
> > 02903300-029033ff : /aconnect@2a41000/ahub/amx@2903300
> > 02903800-029038ff : /aconnect@2a41000/ahub/adx@2903800
> > 02903900-029039ff : /aconnect@2a41000/ahub/adx@2903900
> > 02903a00-02903aff : /aconnect@2a41000/ahub/adx@2903a00
> > 02903b00-02903bff : /aconnect@2a41000/ahub/adx@2903b00
> > 02904000-029040ff : /aconnect@2a41000/ahub/dmic@2904000
> > 02904100-029041ff : /aconnect@2a41000/ahub/dmic@2904100
> > 02904200-029042ff : /aconnect@2a41000/ahub/dmic@2904200
> > 02904300-029043ff : /aconnect@2a41000/ahub/dmic@2904300
> > 02905000-029050ff : /aconnect@2a41000/ahub/dspk@2905000
> > 02905100-029051ff : /aconnect@2a41000/ahub/dspk@2905100
> > 02907000-029070ff : /aconnect@2a41000/ahub/afc@2907000
> > 02907100-029071ff : /aconnect@2a41000/ahub/afc@2907100
> > 02907200-029072ff : /aconnect@2a41000/ahub/afc@2907200
> > 02907300-029073ff : /aconnect@2a41000/ahub/afc@2907300
> > 02907400-029074ff : /aconnect@2a41000/ahub/afc@2907400
> > 02907500-029075ff : /aconnect@2a41000/ahub/afc@2907500
> > 02908000-029080ff : /aconnect@2a41000/ahub/ope@2908000
> > 02908100-029081ff : /aconnect@2a41000/ahub/ope@2908000
> > 02908200-029083ff : /aconnect@2a41000/ahub/ope@2908000
> > 0290a000-0290a1ff : /aconnect@2a41000/ahub/mvc@290a000
> > 0290a200-0290a3ff : /aconnect@2a41000/ahub/mvc@290a200
> > 0290bb00-0290c2ff : /aconnect@2a41000/ahub/amixer@290bb00
> > 0290e400-0290e7ff : /aconnect@2a41000/ahub/arad@290e400
> > 0290f000-0290 : /aconnect@2a41000/ahub/admaif@290f000
> > 0291-02911fff : /aconnect@2a41000/ahub/asrc@291
> > 0293-0297 : /aconnect@2a41000/adma@293
> > 02c0-02c0 : /mc_sid@2c0
> > 02c1-02c1 : /mc_sid@2c0
> > 0301-0301 : /watchdog@30c
> > 0309-0309fffe : /watchdog@30c
> > 030c-030cfffe : /watchdog@30c
> > 0310-0310003f : serial
> > 0311-0311003f : /serial@311
> > 0313-0313003f : /serial@313
> > 0316-031600ff : /i2c@316
> > 0318-031800ff : /i2c@318
> > 0319-031900ff : /i2c@319
> > 031b-031b00ff : /i2c@31b
> > 031c-031c00ff : /i2c@31c
> > 031e-031e00ff : /i2c@31e
> > 0321-0321 : /spi@321
> > 0324-0324 : /spi@324
> > 0328-0328 : /pwm@328
> > 0329-0329 : /pwm@329
> > 032a-032a : /pwm@32a
> > 0340-0340020f : /sdhci@340
> > 0344-0344020f : /sdhci@344
> > 0346-0346020f : /sdhci@346
> > 0350-03500fff : sata-ipfs
> > 03501000-03506fff : sata-config
> > 03507000-03508fff : sata-ahci
> > 0351-0351 : /hda@351
> > 0352-03520fff : padctl
> > 0353-03537fff : /xhci@353
> > 03538000-03538fff : /xhci@353
> > 0354-03540fff : ao
> > 0355-03557fff : /xudc@355
> > 03558000-03558fff : /xudc@355
> > 0382-038205ff : /efuse@382
> > 0383-0383 : /kfuse@0x383
> > 0396-03960fff : 396.tegra_cec
> > 0399-0399 : 399.mipical
> > 039c-039c000f : /tachometer@39c
> > 03a9-03a9 : sata-aux
> > 03ad-03ad : /se_elp@3ad
> > 03ae-03ae : /se_elp@3ad
> > 03c0-03c00fff : Tegra Combined UART TOP0_HSP Linux mailbox interrrupt
> > 03c1-03c10003 : Tegra Combined UART TOP0_HSP Linux 

Re: Using Erika3 with libc support

[Claudio Scordino]

Hi,

Il giorno sab 9 feb 2019 alle ore 18:09 João Reis  ha
scritto:

> sábado, 9 de Fevereiro de 2019 às 16:55:21 UTC, João Reis escreveu:
> > Hello,
> >
> > Is it possible (in jailhouse v0.10) to link an Erika application against
> libc?
>
> In Erika's website, it says that Jailhouse does not allow to select
> different toolchains for compiling the inmate library and the rest of the
> hypervisor (it only does in Jetson TX1 and TX2 cases), so I wonder if it is
> possible to do it now, or if it remains unable (in Zynq Ultrascale+ case).
>

You can build the Jailhouse inmate and link it to the ERIKA Enterprise,
either for Cortex-A or for x86-64.

What is not currently supported by the Jailhouse build system is the
possibility of using different toolchains for the hypervisor firmware and
the inmate library.
This is useful in case you want to use a bare-metal toolchain with libc
(e.g. newlib) for the inmate.
Indeed, we have successfully used a bare-metal toolchain by Linaro (with
libc) in the inmate. We have been able of even using dynamic memory
allocation and C++ data structures.

You can easily patch Jailhouse's makefiles for using different compilers
for the hypervisor firmware and the inmate library (which could eventually
be linked to the ERIKA RTOS, in case of need).

Best regards,

 Claudio

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Re: Customize coloring on Jailhouse v0.10

[Claudio Scordino]

Dear all,

On 301118, 21:00, Ralf Ramsauer wrote:
> Hi,
> 
> On 11/30/18 8:29 PM, João Reis wrote:
> > Hello everyone,
> > 
> > I suppose Jailhouse v0.10 has page coloring, but when i look at 
> > zynqmp-zcu102.c file, i don't see any mention to colored memory regions. Do 
> > i have to add another memory region structure for memory locations of a 
> > given color like this to enable page coloring?
> 
> there is no upstream support for cache coloring in Jailhouse. Let me Cc
> Claudio, I once heard that some guys from Italy are working on this topic.

As Marco Solieri already mentioned, people from University of Modena are
implementing such a feature. Hopefully, it will find its way to mainline
once ready.

Best regards,

Claudio

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[PATCH] tsc_read() renamed tsc_read_ns() to avoid misunderstandings.

[Claudio Scordino]

Signed-off-by: Claudio Scordino 
---
 inmates/demos/x86/apic-demo.c| 6 +++---
 inmates/lib/x86/include/inmate.h | 2 +-
 inmates/lib/x86/timing.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/inmates/demos/x86/apic-demo.c b/inmates/demos/x86/apic-demo.c
index 5100cebd..920fbd71 100644
--- a/inmates/demos/x86/apic-demo.c
+++ b/inmates/demos/x86/apic-demo.c
@@ -55,7 +55,7 @@ static void irq_handler(void)
unsigned long delta;
u32 smis;
 
-   delta = tsc_read() - expected_time;
+   delta = tsc_read_ns() - expected_time;
if (delta < min)
min = delta;
if (delta > max)
@@ -70,7 +70,7 @@ static void irq_handler(void)
printk("\n");
 
expected_time += 100 * NS_PER_MSEC;
-   apic_timer_set(expected_time - tsc_read());
+   apic_timer_set(expected_time - tsc_read_ns());
 }
 
 static void init_apic(void)
@@ -83,7 +83,7 @@ static void init_apic(void)
apic_freq_khz = apic_timer_init(APIC_TIMER_VECTOR);
printk("Calibrated APIC frequency: %lu kHz\n", apic_freq_khz);
 
-   expected_time = tsc_read() + NS_PER_MSEC;
+   expected_time = tsc_read_ns() + NS_PER_MSEC;
apic_timer_set(NS_PER_MSEC);
 
asm volatile("sti");
diff --git a/inmates/lib/x86/include/inmate.h b/inmates/lib/x86/include/inmate.h
index 71687f9b..5fe4e102 100644
--- a/inmates/lib/x86/include/inmate.h
+++ b/inmates/lib/x86/include/inmate.h
@@ -239,7 +239,7 @@ void hypercall_init(void);
 
 unsigned long pm_timer_read(void);
 
-unsigned long tsc_read(void);
+unsigned long tsc_read_ns(void);
 unsigned long tsc_init(void);
 
 void delay_us(unsigned long microsecs);
diff --git a/inmates/lib/x86/timing.c b/inmates/lib/x86/timing.c
index bf70a04f..de41fc35 100644
--- a/inmates/lib/x86/timing.c
+++ b/inmates/lib/x86/timing.c
@@ -72,7 +72,7 @@ static u64 rdtsc(void)
 #endif
 }
 
-unsigned long tsc_read(void)
+unsigned long tsc_read_ns(void)
 {
unsigned int cpu = cpu_id();
unsigned long tmr;
-- 
2.17.1

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Re: Question about MSI-X

[Claudio Scordino]

Hi Jan,

Il 28/09/2018 14:11, Jan Kiszka ha scritto:

On 28.09.18 12:07, Claudio Scordino wrote:

Dear all,

I'm implementing a minimal inmate driver for i210 and I wonder if I have
understood correctly the usage of the MSI-X functions.

Once the correct MSI-X bar (BAR3, in my case) has been mapped, I need to invoke
both:

 int_set_handler(IRQ_VECTOR, irq_handler);
 pci_msix_set_vector(bdf, IRQ_VECTOR, 0);

Is IRQ_VECTOR the value reported by lspci ("pin A routed to IRQ 18") or is it
the value reported by /proc/interrupts (129, in my specific case) ?


No, it is a free APIC vector in your setup. Can be anything >= 32.



BTW, what is the third argument of pci_msix_set_vector() supposed to contain ?


If your device is able and configured to generate multiple MSI-X vectors (e.g.
one vector per queue, one for maintenance etc.), this links them to the desired
APIC vector.


Thank you for the clarifications.

The device seems to be able to either use a single or a multiple MSI-X vector 
(based on the value of a register).
However, in both cases I can't get any interrupt on reception and I can't 
figure out a simple way for understanding if it is a device or a cell 
misconfiguration.
The platform is x86 with Intel i210, programmed to use only the first queue. 
Polling (similar to the e1000-demo) works fine.

This is the lspci output (MSI-X  is available on BAR3):

03:00.0 Ethernet controller: Intel Corporation I210 Gigabit Network 
Connection (rev 03)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- https://groups.google.com/d/optout.

Question about MSI-X

[Claudio Scordino]

Dear all,

I'm implementing a minimal inmate driver for i210 and I wonder if I have 
understood correctly the usage of the MSI-X functions.

Once the correct MSI-X bar (BAR3, in my case) has been mapped, I need to invoke 
both:

int_set_handler(IRQ_VECTOR, irq_handler);
pci_msix_set_vector(bdf, IRQ_VECTOR, 0);

Is IRQ_VECTOR the value reported by lspci ("pin A routed to IRQ 18") or is it 
the value reported by /proc/interrupts (129, in my specific case) ?

BTW, what is the third argument of pci_msix_set_vector() supposed to contain ?

Many thanks and best regards,

 Claudio

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Re: [RFC PATCH] inmates: support for different compiler

[Claudio Scordino]

Il 10/05/2018 16:52, Jan Kiszka ha scritto:

On 2018-05-10 16:20, Claudio Scordino wrote:

Il 10/05/2018 15:46, Jan Kiszka ha scritto:

On 2018-05-10 12:02, Claudio Scordino wrote:

Some inmates might need a library built using a compiler different from
the one used for building the rest of the hypervisor.
This is, for example, the case of an inmate needing the libc support
provided by a bare-metal toolchain.
This patch introduces two additional environment valiables (i.e.
JAILHOUSE_INMATE_CC and JAILHOUSE_INMATE_LD) which, if set, allow to
build the inmate library and demos using a different compiler.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
   inmates/Makefile | 7 +++
   1 file changed, 7 insertions(+)

diff --git a/inmates/Makefile b/inmates/Makefile
index c36de62..1b53ef7 100644
--- a/inmates/Makefile
+++ b/inmates/Makefile
@@ -12,6 +12,13 @@
     -include $(GEN_CONFIG_MK)
   +ifneq ($(JAILHOUSE_INMATE_CC),)
+CC=$(JAILHOUSE_INMATE_CC)
+endif
+ifneq ($(JAILHOUSE_INMATE_LD),)
+LD=$(JAILHOUSE_INMATE_LD)
+endif
+
   INMATES_LIB = $(src)/lib/$(SRCARCH)
   export INMATES_LIB
  


We do not have a use case for this with the existing demos, do we? How
should we ensure this will be tested in the future?



Actually, we do have a use case: an inmate linked to the ERIKA RTOS also
needing some libc/libm stuff.


I actually wanted to write "...in-tree". Obviously, you have something
out-of-tree.


For such use case, we are going to build the inmate library using a
Linaro bare-metal compiler.
That's the primary reason why we proposed the patch.

On the other hand, we cannot ensure that such functionality will be
periodically checked for regressions.
So, feel free to discard it if you feel that this need is not quite common.


How about enhancing the build system so that you can build the inmate
library separately? Then you could also set a different compiler without
breaking the build of the rest.


Yes, that would work as well.

Thanks,

  Claudio

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Re: [RFC PATCH] inmates: support for different compiler

[Claudio Scordino]

Il 10/05/2018 15:46, Jan Kiszka ha scritto:

On 2018-05-10 12:02, Claudio Scordino wrote:

Some inmates might need a library built using a compiler different from
the one used for building the rest of the hypervisor.
This is, for example, the case of an inmate needing the libc support
provided by a bare-metal toolchain.
This patch introduces two additional environment valiables (i.e.
JAILHOUSE_INMATE_CC and JAILHOUSE_INMATE_LD) which, if set, allow to
build the inmate library and demos using a different compiler.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
  inmates/Makefile | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/inmates/Makefile b/inmates/Makefile
index c36de62..1b53ef7 100644
--- a/inmates/Makefile
+++ b/inmates/Makefile
@@ -12,6 +12,13 @@
  
  -include $(GEN_CONFIG_MK)
  
+ifneq ($(JAILHOUSE_INMATE_CC),)

+CC=$(JAILHOUSE_INMATE_CC)
+endif
+ifneq ($(JAILHOUSE_INMATE_LD),)
+LD=$(JAILHOUSE_INMATE_LD)
+endif
+
  INMATES_LIB = $(src)/lib/$(SRCARCH)
  export INMATES_LIB
  



We do not have a use case for this with the existing demos, do we? How
should we ensure this will be tested in the future?



Actually, we do have a use case: an inmate linked to the ERIKA RTOS also 
needing some libc/libm stuff.
For such use case, we are going to build the inmate library using a Linaro 
bare-metal compiler.
That's the primary reason why we proposed the patch.

On the other hand, we cannot ensure that such functionality will be 
periodically checked for regressions.
So, feel free to discard it if you feel that this need is not quite common.

Best regards,

  Claudio

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[PATCH] Jetson TX2: fix root cell config for GPU acceleration

[Claudio Scordino]

From: Luca Cuomo <l.cu...@evidence.eu.com>

This patch fixes the root cell config for the Jetson TX2 platform to
avoid a deadlock occurring when using accelerated graphics. It maps the
VIC memory regions and increment the number of handled IRQs.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
---
 configs/arm64/jetson-tx2.c | 41 ++---
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/configs/arm64/jetson-tx2.c b/configs/arm64/jetson-tx2.c
index 0d23158..2350362 100644
--- a/configs/arm64/jetson-tx2.c
+++ b/configs/arm64/jetson-tx2.c
@@ -26,8 +26,8 @@
 struct {
struct jailhouse_system header;
__u64 cpus[1];
-   struct jailhouse_memory mem_regions[57];
-   struct jailhouse_irqchip irqchips[2];
+   struct jailhouse_memory mem_regions[61];
+   struct jailhouse_irqchip irqchips[3];
 } __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
@@ -274,6 +274,13 @@ struct {
 .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
 JAILHOUSE_MEM_EXECUTE,
 },
+   /* VIC CAR */{
+.phys_start = 0x0556,
+.virt_start = 0x0556,
+.size = 0x1,
+.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+JAILHOUSE_MEM_EXECUTE,
+},
/* CSITE */ {
.phys_start = 0x0800,
.virt_start = 0x0800,
@@ -281,6 +288,13 @@ struct {
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
+   /* SCE VIC registers */ {
+   .phys_start = 0x0b02,
+   .virt_start = 0x0b02,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
/* SCE_PM */ {
.phys_start = 0x0b1f,
.virt_start = 0x0b1f,
@@ -295,6 +309,13 @@ struct {
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
+   /* AON VIC registers */ {
+   .phys_start = 0x0c02,
+   .virt_start = 0x0c02,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
/* More I2C + SPI */ {
.phys_start = 0x0c23,
.virt_start = 0x0c23,
@@ -330,6 +351,13 @@ struct {
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
+   /* BPMP VIC registers */ {
+   .phys_start = 0x0d02,
+   .virt_start = 0x0d02,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
/* ACTMON  + SIMON + SOC_THERM */ {
.phys_start = 0x0d23,
.virt_start = 0x0d23,
@@ -484,7 +512,14 @@ struct {
.address = 0x03881000,
.pin_base = 160,
.pin_bitmap = {
-   0x, 0x
+   0x, 0x, 0x, 0x
+   },
+   },
+   /* GIC */ {
+   .address = 0x03881000,
+   .pin_base = 288,
+   .pin_bitmap = {
+   0x,
},
},
},
-- 
2.7.4

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Re: Share memory among cells on arm64

[Claudio Scordino]

Hi Giovani,

2018-04-12 8:01 GMT+02:00 Jan Kiszka :

> On 2018-04-11 19:40, Giovani Gracioli wrote:
> > Here is the output of the unhandled data read:
> >
> > Unhandled data read at 0xfc10(2)
> >
> > FATAL: unhandled trap (exception class 0x24)
> > Cell state before exception:
> >  pc: 1828   lr: 15f0 spsr: 6005 EL1
> >  sp: 3f30  esr: 24 1 146
> >  x0: fc10   x1:    x2: 0002
> >  x3: fc00   x4:    x5: 
> >  x6: 1000   x7:    x8: 
> >  x9:   x10:   x11: 
> > x12:   x13:   x14: 
> > x15:   x16:   x17: 
> > x18:   x19: 1000  x20: 
> > x21: 1af4  x22: 1110  x23: 1000
> > x24: 2660  x25:   x26: 
> > x27:   x28:   x29: 
> >
> > Parking CPU 3 (Cell: "gic-demo-ivshmem")
> >
> > Am I missing something in the configuration?
>
> Possibly. As this is code of Claudio and his colleagues, he may answer
> this better.
>

A collegue of mine is looking at your issue.

BTW, we plan to have a version of the PCI stuff rebased upstream in a
couple of weeks.
We'll post it on the ML once ready.

Regards,

   Claudio

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[PATCH v2 0/4] Support for Nvidia Jetson TX2

[Claudio Scordino]

Tested on the "next" branch against Nvidia's kernel 4.4 (not Vanilla) by
restoring the ABI for kernels < 4.7 in hypervisor/arch/arm64/entry.S:

/* install bootstrap_vectors */
ldr x0, =bootstrap_vectors
virt2phys x0

Claudio Scordino (4):
  Jetson TX2: root cell config
  Jetson TX2: add inmate support
  Jetson TX2: add demo cell config
  Documentation: Add TX2 to the list of supported hardware

 Documentation/hypervisor-configuration.md |   6 +-
 README.md |   2 +-
 configs/arm64/jetson-tx2-demo.c   |  51 
 configs/arm64/jetson-tx2.c| 492 ++
 inmates/lib/arm64/include/mach.h  |   8 +
 5 files changed, 557 insertions(+), 2 deletions(-)
 create mode 100644 configs/arm64/jetson-tx2-demo.c
 create mode 100644 configs/arm64/jetson-tx2.c

-- 
2.7.4

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[PATCH v2 1/4] Jetson TX2: root cell config

[Claudio Scordino]

Root cell config for Jetson TX2 using Nvidia's kernel 4.4 (not Vanilla).

Tested on the "next" branch by restoring the ABI for kernels < 4.7 in
hypervisor/arch/arm64/entry.S:

/* install bootstrap_vectors */
ldr x0, =bootstrap_vectors
virt2phys x0

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/jetson-tx2.c | 492 +
 1 file changed, 492 insertions(+)
 create mode 100644 configs/arm64/jetson-tx2.c

diff --git a/configs/arm64/jetson-tx2.c b/configs/arm64/jetson-tx2.c
new file mode 100644
index 000..0d23158
--- /dev/null
+++ b/configs/arm64/jetson-tx2.c
@@ -0,0 +1,492 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Jailhouse Jetson TX2 board
+ *
+ * Copyright (C) 2018 Evidence Srl
+ *
+ * Authors:
+ *  Claudio Scordino <clau...@evidence.eu.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command line.
+ *
+ * 2:7000: inmate (size: 100: = 16 MB)
+ * 2:7100: hypervisor (size: 400: = 64 MB)
+ *
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[57];
+   struct jailhouse_irqchip irqchips[2];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .hypervisor_memory = {
+   .phys_start = 0x27100,
+   .size = 0x400,
+   },
+   .debug_console = {
+   .address = 0x310,
+   .size = 0x1,
+   .flags = JAILHOUSE_CON1_TYPE_8250 |
+JAILHOUSE_CON1_ACCESS_MMIO |
+JAILHOUSE_CON1_REGDIST_4 |
+JAILHOUSE_CON2_TYPE_ROOTPAGE,
+   },
+   .platform_info = {
+
+   .arm = {
+   .gicd_base = 0x03881000,
+   .gicc_base = 0x03882000,
+   .gich_base = 0x03884000,
+   .gicv_base = 0x03886000,
+   .gic_version = 2,
+   .maintenance_irq = 25,
+   }
+   },
+   .root_cell = {
+   .name = "Jetson-TX2",
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0x39,
+   },
+
+
+   .mem_regions = {
+   /* BPMP_ATCM */ {
+.phys_start = 0x,
+.virt_start = 0x,
+.size = 0x4,
+.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+JAILHOUSE_MEM_EXECUTE,
+},
+
+   /* MISC */ {
+.phys_start = 0x0010,
+.virt_start = 0x0010,
+.size = 0x1,
+.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+JAILHOUSE_MEM_EXECUTE,
+},
+
+   /* AXIP2P */ {
+   .phys_start = 0x0210,
+   .virt_start = 0x0210,
+   .size = 0x10,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* GPIO_CTL */ {
+   .phys_start = 0x0220,
+   .virt_start = 0x0220,
+   .size = 0x10,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* TSA */ {
+   .phys_start = 0x240,
+   .virt_start = 0x240,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* PADCTL_A (PINMUX) */ {
+   .phys_start = 0x0243,
+   .virt_start = 0x0243,
+   .size = 0x15000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE

[PATCH v2 2/4] Jetson TX2: add inmate support

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 inmates/lib/arm64/include/mach.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/inmates/lib/arm64/include/mach.h b/inmates/lib/arm64/include/mach.h
index 478e32d..498843c 100644
--- a/inmates/lib/arm64/include/mach.h
+++ b/inmates/lib/arm64/include/mach.h
@@ -70,6 +70,14 @@
 #define GICD_V2_BASE   ((void *)0x50041000)
 #define GICC_V2_BASE   ((void *)0x50042000)
 
+#elif defined(CONFIG_MACH_JETSON_TX2)
+#define CON_TYPE   "8250"
+#define CON_BASE   0x310
+
+#define GIC_VERSION2
+#define GICD_V2_BASE   ((void *)0x03881000)
+#define GICC_V2_BASE   ((void *)0x03882000)
+
 #elif defined(CONFIG_MACH_ZYNQMP_ZCU102)
 #define CON_TYPE   "XUARTPS"
 #define CON_BASE   0xff01
-- 
2.7.4

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[PATCH v2 3/4] Jetson TX2: add demo cell config

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/jetson-tx2-demo.c | 51 +
 1 file changed, 51 insertions(+)
 create mode 100644 configs/arm64/jetson-tx2-demo.c

diff --git a/configs/arm64/jetson-tx2-demo.c b/configs/arm64/jetson-tx2-demo.c
new file mode 100644
index 000..7cb8dbe
--- /dev/null
+++ b/configs/arm64/jetson-tx2-demo.c
@@ -0,0 +1,51 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for gic-demo or uart-demo inmate on Nvidia Jetson TX2:
+ * 1 CPU, 64 MB RAM, serial port 0
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .name = "jetson-tx2-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   },
+
+   .cpus = {
+   0x1,
+   },
+
+   .mem_regions = {
+   /* UART */ {
+   .phys_start = 0x310,
+   .virt_start = 0x310,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* RAM */ {
+   .phys_start = 0x27000,
+   .virt_start = 0,
+   .size = 0x100,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   },
+};
-- 
2.7.4

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[PATCH v2 4/4] Documentation: Add TX2 to the list of supported hardware

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 Documentation/hypervisor-configuration.md | 6 +-
 README.md | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/hypervisor-configuration.md 
b/Documentation/hypervisor-configuration.md
index 57b3c88..021093e 100644
--- a/Documentation/hypervisor-configuration.md
+++ b/Documentation/hypervisor-configuration.md
@@ -64,10 +64,14 @@ General configuration parameters
 
  ARM64
 
-# Nvidia Jetson TK1
+# Nvidia Jetson TX1
 
 #define CONFIG_MACH_JETSON_TX1 1
 
+# Nvidia Jetson TX2
+
+#define CONFIG_MACH_JETSON_TX2 1
+
 # Xilinx Zynq UltraScale+ MPSoC ZCU102
 
 #define CONFIG_MACH_ZYNQMP_ZCU102 1
diff --git a/README.md b/README.md
index a4fb59c..1e8433a 100644
--- a/README.md
+++ b/README.md
@@ -132,7 +132,7 @@ Hardware requirements (preliminary)
 
 - LeMaker HiKey
 
-- NVIDIA Jetson TX1
+- NVIDIA Jetson TX1 and TX2
 
 - Xilinx ZCU102 (ZynqMP evaluation board)
 
-- 
2.7.4

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Re: [PATCH 1/4] Jetson TX2: root cell config

[Claudio Scordino]

Hi Jan,

2018-04-10 18:30 GMT+02:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2018-04-10 15:00, Claudio Scordino wrote:
> >
> >
> > 2018-04-09 19:36 GMT+02:00 Jan Kiszka <jan.kis...@siemens.com
> > <mailto:jan.kis...@siemens.com>>:
> >
> > On 2018-04-09 16:35, Claudio Scordino wrote:
> > >
> > >
> > > 2018-04-09 16:28 GMT+02:00 Lokesh Vutla <lokeshvu...@ti.com
> <mailto:lokeshvu...@ti.com>
> > > <mailto:lokeshvu...@ti.com <mailto:lokeshvu...@ti.com>>>:
> > >
> > >
> > >
> > > On Monday 09 April 2018 07:53 PM, Claudio Scordino wrote:
> > > > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com
> <mailto:clau...@evidence.eu.com>
> > > <mailto:clau...@evidence.eu.com <mailto:clau...@evidence.eu.
> com>>>
> > > > ---
> > > >  configs/arm64/jetson-tx2.c | 492
> > > +
> > > >  1 file changed, 492 insertions(+)
> > > >  create mode 100644 configs/arm64/jetson-tx2.c
> > > >
> > > > diff --git a/configs/arm64/jetson-tx2.c
> b/configs/arm64/jetson-tx2.c
> > > > new file mode 100644
> > > > index 000..0d23158
> > > > --- /dev/null
> > > > +++ b/configs/arm64/jetson-tx2.c
> >     > > @@ -0,0 +1,492 @@
> > > > +/*
> > > > + * Jailhouse, a Linux-based partitioning hypervisor
> > > > + *
> > > > + * Configuration for Jailhouse Jetson TX2 board
> > > > + *
> > > > + * Copyright (C) 2018 Evidence Srl
> > > > + *
> > > > + * Authors:
> > > > + *  Claudio Scordino <clau...@evidence.eu.com  clau...@evidence.eu.com>
> > > <mailto:clau...@evidence.eu.com <mailto:clau...@evidence.eu.
> com>>>
> > > > + *
> > > > + * This work is licensed under the terms of the GNU GPL,
> > version
> > > 2.  See
> > > > + * the COPYING file in the top-level directory.
> > > > + *
> > > > + * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command
> > line.
> > > > + *
> > > > + *   2:7000: inmate (size: 100: = 16 MB)
> > > > + *   2:7100: hypervisor (size: 400: = 64 MB)
> > > > + *
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +
> > > > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
> > > > +
> > > > +struct {
> > > > + struct jailhouse_system header;
> > > > + __u64 cpus[1];
> > > > + struct jailhouse_memory mem_regions[57];
> > > > + struct jailhouse_irqchip irqchips[2];
> > > > +} __attribute__((packed)) config = {
> > > > + .header = {
> > > > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > > > + .revision = JAILHOUSE_CONFIG_REVISION,
> > > > + .hypervisor_memory = {
> > > > + .phys_start = 0x27100,
> > > > + .size = 0x400,
> > > > + },
> > > > + .debug_console = {
> > > > + .address = 0x310,
> > > > + .size = 0x1,
> > > > + .flags = JAILHOUSE_CON1_TYPE_8250 |
> > > > +  JAILHOUSE_CON1_ACCESS_MMIO |
> > > > +  JAILHOUSE_CON1_REGDIST_4 |
> > > > +  JAILHOUSE_CON2_TYPE_ROOTPAGE,
> > > > + },
> > > > + .platform_info = {
> > > > +
> > > > + .arm = {
> > > > + .gicd_base = 0x03881000,
> > > > + .gicc_base = 0x03882000,
> > > > + .gich_base = 0x0388400

Re: [PATCH 1/4] Jetson TX2: root cell config

[Claudio Scordino]

2018-04-09 19:36 GMT+02:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2018-04-09 16:35, Claudio Scordino wrote:
> >
> >
> > 2018-04-09 16:28 GMT+02:00 Lokesh Vutla <lokeshvu...@ti.com
> > <mailto:lokeshvu...@ti.com>>:
> >
> >
> >
> > On Monday 09 April 2018 07:53 PM, Claudio Scordino wrote:
> > > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com
> > <mailto:clau...@evidence.eu.com>>
> > > ---
> > >  configs/arm64/jetson-tx2.c | 492
> > +
> > >  1 file changed, 492 insertions(+)
> > >  create mode 100644 configs/arm64/jetson-tx2.c
> > >
> > > diff --git a/configs/arm64/jetson-tx2.c
> b/configs/arm64/jetson-tx2.c
> > > new file mode 100644
> > > index 000..0d23158
> > > --- /dev/null
> > > +++ b/configs/arm64/jetson-tx2.c
> > > @@ -0,0 +1,492 @@
> > > +/*
> > > + * Jailhouse, a Linux-based partitioning hypervisor
> > > + *
> > > + * Configuration for Jailhouse Jetson TX2 board
> > > + *
> > > + * Copyright (C) 2018 Evidence Srl
> > > + *
> > > + * Authors:
> > > + *  Claudio Scordino <clau...@evidence.eu.com
> > <mailto:clau...@evidence.eu.com>>
> > > + *
> > > + * This work is licensed under the terms of the GNU GPL, version
> > 2.  See
> > > + * the COPYING file in the top-level directory.
> > > + *
> > > + * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command line.
> > > + *
> > > + *   2:7000: inmate (size: 100: = 16 MB)
> > > + *   2:7100: hypervisor (size: 400: = 64 MB)
> > > + *
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
> > > +
> > > +struct {
> > > + struct jailhouse_system header;
> > > + __u64 cpus[1];
> > > + struct jailhouse_memory mem_regions[57];
> > > + struct jailhouse_irqchip irqchips[2];
> > > +} __attribute__((packed)) config = {
> > > + .header = {
> > > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > > + .revision = JAILHOUSE_CONFIG_REVISION,
> > > + .hypervisor_memory = {
> > > + .phys_start = 0x27100,
> > > + .size = 0x400,
> > > + },
> > > + .debug_console = {
> > > + .address = 0x310,
> > > + .size = 0x1,
> > > + .flags = JAILHOUSE_CON1_TYPE_8250 |
> > > +  JAILHOUSE_CON1_ACCESS_MMIO |
> > > +  JAILHOUSE_CON1_REGDIST_4 |
> > > +  JAILHOUSE_CON2_TYPE_ROOTPAGE,
> > > + },
> > > + .platform_info = {
> > > +
> > > + .arm = {
> > > + .gicd_base = 0x03881000,
> > > + .gicc_base = 0x03882000,
> > > + .gich_base = 0x03884000,
> > > + .gicv_base = 0x03886000,
> > > + .gic_version = 2,
> > > + .maintenance_irq = 25,
> > > + }
> > > + },
> > > + .root_cell = {
> > > + .name = "Jetson-TX2",
> > > + .cpu_set_size = sizeof(config.cpus),
> > > + .num_memory_regions =
> > ARRAY_SIZE(config.mem_regions),
> > > + .num_irqchips = ARRAY_SIZE(config.irqchips),
> > > + },
> > > + },
> > > +
> > > + .cpus = {
> > > + 0x39,
> > > + },
> >
> > Out of curiosity, is it deliberate that cpu1,2 are skipped?
> >
> >
> > By default, the Linux kernel shipped by Nvidia boots with those two CPUs
> > disabled.
> > They can be easily enabled by echoing 1 into
> > /sys/devices/system/cpu/cpu*/

Re: [PATCH 1/4] Jetson TX2: root cell config

[Claudio Scordino]

2018-04-09 16:28 GMT+02:00 Lokesh Vutla <lokeshvu...@ti.com>:

>
>
> On Monday 09 April 2018 07:53 PM, Claudio Scordino wrote:
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > ---
> >  configs/arm64/jetson-tx2.c | 492 ++
> +++
> >  1 file changed, 492 insertions(+)
> >  create mode 100644 configs/arm64/jetson-tx2.c
> >
> > diff --git a/configs/arm64/jetson-tx2.c b/configs/arm64/jetson-tx2.c
> > new file mode 100644
> > index 000..0d23158
> > --- /dev/null
> > +++ b/configs/arm64/jetson-tx2.c
> > @@ -0,0 +1,492 @@
> > +/*
> > + * Jailhouse, a Linux-based partitioning hypervisor
> > + *
> > + * Configuration for Jailhouse Jetson TX2 board
> > + *
> > + * Copyright (C) 2018 Evidence Srl
> > + *
> > + * Authors:
> > + *  Claudio Scordino <clau...@evidence.eu.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.  See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command line.
> > + *
> > + *   2:7000: inmate (size: 100: = 16 MB)
> > + *   2:7100: hypervisor (size: 400: = 64 MB)
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
> > +
> > +struct {
> > + struct jailhouse_system header;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[57];
> > + struct jailhouse_irqchip irqchips[2];
> > +} __attribute__((packed)) config = {
> > + .header = {
> > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .hypervisor_memory = {
> > + .phys_start = 0x27100,
> > + .size = 0x400,
> > + },
> > + .debug_console = {
> > + .address = 0x310,
> > + .size = 0x1,
> > + .flags = JAILHOUSE_CON1_TYPE_8250 |
> > +  JAILHOUSE_CON1_ACCESS_MMIO |
> > +  JAILHOUSE_CON1_REGDIST_4 |
> > +  JAILHOUSE_CON2_TYPE_ROOTPAGE,
> > + },
> > + .platform_info = {
> > +
> > + .arm = {
> > + .gicd_base = 0x03881000,
> > + .gicc_base = 0x03882000,
> > + .gich_base = 0x03884000,
> > + .gicv_base = 0x03886000,
> > + .gic_version = 2,
> > + .maintenance_irq = 25,
> > + }
> > + },
> > + .root_cell = {
> > + .name = "Jetson-TX2",
> > + .cpu_set_size = sizeof(config.cpus),
> > + .num_memory_regions =
> ARRAY_SIZE(config.mem_regions),
> > + .num_irqchips = ARRAY_SIZE(config.irqchips),
> > + },
> > + },
> > +
> > + .cpus = {
> > + 0x39,
> > + },
>
> Out of curiosity, is it deliberate that cpu1,2 are skipped?
>

By default, the Linux kernel shipped by Nvidia boots with those two CPUs
disabled.
They can be easily enabled by echoing 1 into
/sys/devices/system/cpu/cpu*/online.

Best regards,

Claudio

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[PATCH 0/4] Support for Nvidia Jetson TX2

[Claudio Scordino]

Tested on the "next" branch against Nvidia's kernel 4.4 by restoring the
ABI for kernels < 4.7 in hypervisor/arch/arm64/entry.S:

/* install bootstrap_vectors */
ldr x0, =bootstrap_vectors
virt2phys x0


Claudio Scordino (4):
  Jetson TX2: root cell config
  Jetson TX2: add inmate support
  Jetson TX2: add demo cell config
  Documentation: Add TX2 to the list of supported hardware

 Documentation/hypervisor-configuration.md |   6 +-
 README.md |   2 +-
 configs/arm64/jetson-tx2-demo.c   |  51 
 configs/arm64/jetson-tx2.c| 492 ++
 inmates/lib/arm64/include/mach.h  |   8 +
 5 files changed, 557 insertions(+), 2 deletions(-)
 create mode 100644 configs/arm64/jetson-tx2-demo.c
 create mode 100644 configs/arm64/jetson-tx2.c

-- 
2.7.4

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[PATCH 2/4] Jetson TX2: add inmate support

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 inmates/lib/arm64/include/mach.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/inmates/lib/arm64/include/mach.h b/inmates/lib/arm64/include/mach.h
index 4d18929..02fdcc6 100644
--- a/inmates/lib/arm64/include/mach.h
+++ b/inmates/lib/arm64/include/mach.h
@@ -70,6 +70,14 @@
 #define GICD_V2_BASE   ((void *)0x50041000)
 #define GICC_V2_BASE   ((void *)0x50042000)
 
+#elif defined(CONFIG_MACH_JETSON_TX2)
+#define CON_TYPE   "8250"
+#define CON_BASE   0x310
+
+#define GIC_VERSION2
+#define GICD_V2_BASE   ((void *)0x03881000)
+#define GICC_V2_BASE   ((void *)0x03882000)
+
 #elif defined(CONFIG_MACH_ZYNQMP_ZCU102)
 #define CON_TYPE   "XUARTPS"
 #define CON_BASE   0xff01
-- 
2.7.4

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[PATCH 3/4] Jetson TX2: add demo cell config

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/jetson-tx2-demo.c | 51 +
 1 file changed, 51 insertions(+)
 create mode 100644 configs/arm64/jetson-tx2-demo.c

diff --git a/configs/arm64/jetson-tx2-demo.c b/configs/arm64/jetson-tx2-demo.c
new file mode 100644
index 000..7cb8dbe
--- /dev/null
+++ b/configs/arm64/jetson-tx2-demo.c
@@ -0,0 +1,51 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for gic-demo or uart-demo inmate on Nvidia Jetson TX2:
+ * 1 CPU, 64 MB RAM, serial port 0
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .name = "jetson-tx2-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   },
+
+   .cpus = {
+   0x1,
+   },
+
+   .mem_regions = {
+   /* UART */ {
+   .phys_start = 0x310,
+   .virt_start = 0x310,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* RAM */ {
+   .phys_start = 0x27000,
+   .virt_start = 0,
+   .size = 0x100,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   },
+};
-- 
2.7.4

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[PATCH 1/4] Jetson TX2: root cell config

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/jetson-tx2.c | 492 +
 1 file changed, 492 insertions(+)
 create mode 100644 configs/arm64/jetson-tx2.c

diff --git a/configs/arm64/jetson-tx2.c b/configs/arm64/jetson-tx2.c
new file mode 100644
index 000..0d23158
--- /dev/null
+++ b/configs/arm64/jetson-tx2.c
@@ -0,0 +1,492 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Jailhouse Jetson TX2 board
+ *
+ * Copyright (C) 2018 Evidence Srl
+ *
+ * Authors:
+ *  Claudio Scordino <clau...@evidence.eu.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command line.
+ *
+ * 2:7000: inmate (size: 100: = 16 MB)
+ * 2:7100: hypervisor (size: 400: = 64 MB)
+ *
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[57];
+   struct jailhouse_irqchip irqchips[2];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .hypervisor_memory = {
+   .phys_start = 0x27100,
+   .size = 0x400,
+   },
+   .debug_console = {
+   .address = 0x310,
+   .size = 0x1,
+   .flags = JAILHOUSE_CON1_TYPE_8250 |
+JAILHOUSE_CON1_ACCESS_MMIO |
+JAILHOUSE_CON1_REGDIST_4 |
+JAILHOUSE_CON2_TYPE_ROOTPAGE,
+   },
+   .platform_info = {
+
+   .arm = {
+   .gicd_base = 0x03881000,
+   .gicc_base = 0x03882000,
+   .gich_base = 0x03884000,
+   .gicv_base = 0x03886000,
+   .gic_version = 2,
+   .maintenance_irq = 25,
+   }
+   },
+   .root_cell = {
+   .name = "Jetson-TX2",
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0x39,
+   },
+
+
+   .mem_regions = {
+   /* BPMP_ATCM */ {
+.phys_start = 0x,
+.virt_start = 0x,
+.size = 0x4,
+.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+JAILHOUSE_MEM_EXECUTE,
+},
+
+   /* MISC */ {
+.phys_start = 0x0010,
+.virt_start = 0x0010,
+.size = 0x1,
+.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+JAILHOUSE_MEM_EXECUTE,
+},
+
+   /* AXIP2P */ {
+   .phys_start = 0x0210,
+   .virt_start = 0x0210,
+   .size = 0x10,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* GPIO_CTL */ {
+   .phys_start = 0x0220,
+   .virt_start = 0x0220,
+   .size = 0x10,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* TSA */ {
+   .phys_start = 0x240,
+   .virt_start = 0x240,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* PADCTL_A (PINMUX) */ {
+   .phys_start = 0x0243,
+   .virt_start = 0x0243,
+   .size = 0x15000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE,
+   },
+   /* UFSHC */ {
+   .phys_start = 0x0245,
+   .virt_start = 0x0245,
+   .size = 0x2,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+

Re: Running ivshmem-demo in Jetson TK1.

[Claudio Scordino]

Hi Jonas,

2017-12-10 17:34 GMT+01:00 jonas :

> Hi,
>
> I'll be making an effort to contribute my work to the master branch of
> Jailhouse within the next couple of weeks.
>

If I'm not wrong, those patches were not eventually upstreamed.
Do you still plan to upstream them ?

Many thanks,

  Claudio

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[PATCH v3 2/4] arm64: ignore SIPs used for low-power modes

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

See the following reference:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/arm-sip-service.rst

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/include/asm/sip.h | 16 
 hypervisor/arch/arm64/traps.c| 11 ---
 2 files changed, 24 insertions(+), 3 deletions(-)
 create mode 100644 hypervisor/arch/arm-common/include/asm/sip.h

diff --git a/hypervisor/arch/arm-common/include/asm/sip.h 
b/hypervisor/arch/arm-common/include/asm/sip.h
new file mode 100644
index 000..6de1a15
--- /dev/null
+++ b/hypervisor/arch/arm-common/include/asm/sip.h
@@ -0,0 +1,16 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Authors:
+ *  Peng Fang <peng@nxp.com>
+ *  Claudio Scordino <clau...@evidence.eu.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define IS_SIP_32(hvc) (((hvc) >> 24) == 0x82)
+#define IS_SIP_64(hvc) (((hvc) >> 24) == 0xc2)
+
+#define SIP_NOT_SUPPORTED  (-1)
+
diff --git a/hypervisor/arch/arm64/traps.c b/hypervisor/arch/arm64/traps.c
index cd30923..b44d67b 100644
--- a/hypervisor/arch/arm64/traps.c
+++ b/hypervisor/arch/arm64/traps.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,10 +37,14 @@ static int handle_smc(struct trap_context *ctx)
 {
unsigned long *regs = ctx->regs;
 
-   if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
+   if (IS_PSCI_32(regs[0]) || IS_PSCI_64(regs[0])) {
+   regs[0] = psci_dispatch(ctx);
+   } else if (IS_SIP_32(regs[0]) || IS_SIP_64(regs[0])) {
+   /* This can be ignored */
+   regs[0] = SIP_NOT_SUPPORTED;
+   } else {
return TRAP_UNHANDLED;
-
-   regs[0] = psci_dispatch(ctx);
+   }
 
arch_skip_instruction(ctx);
 
-- 
2.7.4

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[PATCH v3 4/4] README: support for NXP IMX8

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 9dc9841..87be3a3 100644
--- a/README.md
+++ b/README.md
@@ -130,6 +130,8 @@ Hardware requirements (preliminary)
 
 - Xilinx ZCU102 (ZynqMP evaluation board)
 
+- NXP MCIMX8M-EVK
+
 Software requirements
 -
 
-- 
2.7.4

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[PATCH v2 0/4] Support for NXP IMX8

[Claudio Scordino]

Initial support for the NXP IMX8 evaluation board.
---
Changes from v1:
 - Low-power SIPs ignored for all arm64 platforms
   (i.e. imx8-specific #ifdef removed)
 - Defined the more meaningful SIP_NOT_SUPPORTED value

Peng Fang (4):
  imx8mq: add UART support
  arm64: ignore SIPs used for low-power modes
  Cell configs for imx8mq EVK board.
  README: support for NXP IMX8

 README.md |   2 +
 configs/arm64/imx8mq-gic-demo.c   |  56 +
 configs/arm64/imx8mq.c| 108 ++
 hypervisor/arch/arm-common/Kbuild |   2 +-
 hypervisor/arch/arm-common/dbg-write.c|   2 +
 hypervisor/arch/arm-common/include/asm/psci.h |   4 +
 hypervisor/arch/arm-common/include/asm/uart.h |   2 +-
 hypervisor/arch/arm-common/uart-imx.c |  39 ++
 hypervisor/arch/arm64/traps.c |  10 ++-
 include/jailhouse/cell-config.h   |   1 +
 inmates/lib/arm-common/Makefile.lib   |   2 +-
 inmates/lib/arm-common/include/uart.h |   1 +
 inmates/lib/arm-common/printk.c   |   2 +
 inmates/lib/arm-common/uart-imx.c |  63 +++
 inmates/lib/arm64/include/mach.h  |  12 +++
 15 files changed, 300 insertions(+), 6 deletions(-)
 create mode 100644 configs/arm64/imx8mq-gic-demo.c
 create mode 100644 configs/arm64/imx8mq.c
 create mode 100644 hypervisor/arch/arm-common/uart-imx.c
 create mode 100644 inmates/lib/arm-common/uart-imx.c

-- 
2.7.4

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[PATCH v2 2/4] arm64: ignore SIPs used for low-power modes

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

See the following reference:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/arm-sip-service.rst

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/include/asm/psci.h |  4 
 hypervisor/arch/arm64/traps.c | 10 +++---
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/hypervisor/arch/arm-common/include/asm/psci.h 
b/hypervisor/arch/arm-common/include/asm/psci.h
index e635aec..789e022 100644
--- a/hypervisor/arch/arm-common/include/asm/psci.h
+++ b/hypervisor/arch/arm-common/include/asm/psci.h
@@ -32,6 +32,10 @@
 #define PSCI_CPU_IS_ON 0
 #define PSCI_CPU_IS_OFF1
 
+#define IS_SIP_32(hvc) (((hvc) >> 24) == 0x82)
+#define IS_SIP_64(hvc) (((hvc) >> 24) == 0xc2)
+#define SIP_NOT_SUPPORTED  PSCI_NOT_SUPPORTED
+
 #define IS_PSCI_32(hvc)(((hvc) >> 24) == 0x84)
 #define IS_PSCI_64(hvc)(((hvc) >> 24) == 0xc4)
 #define IS_PSCI_UBOOT(hvc) (((hvc) >> 8) == 0x95c1ba)
diff --git a/hypervisor/arch/arm64/traps.c b/hypervisor/arch/arm64/traps.c
index cd30923..896ca53 100644
--- a/hypervisor/arch/arm64/traps.c
+++ b/hypervisor/arch/arm64/traps.c
@@ -36,10 +36,14 @@ static int handle_smc(struct trap_context *ctx)
 {
unsigned long *regs = ctx->regs;
 
-   if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
+   if (IS_PSCI_32(regs[0]) || IS_PSCI_64(regs[0])) {
+   regs[0] = psci_dispatch(ctx);
+   } else if (IS_SIP_32(regs[0]) || IS_SIP_64(regs[0])) {
+   /* This can be ignored */
+   regs[0] = SIP_NOT_SUPPORTED;
+   } else {
return TRAP_UNHANDLED;
-
-   regs[0] = psci_dispatch(ctx);
+   }
 
arch_skip_instruction(ctx);
 
-- 
2.7.4

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[PATCH v2 1/4] imx8mq: add UART support

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/Kbuild |  2 +-
 hypervisor/arch/arm-common/dbg-write.c|  2 +
 hypervisor/arch/arm-common/include/asm/uart.h |  2 +-
 hypervisor/arch/arm-common/uart-imx.c | 39 +
 include/jailhouse/cell-config.h   |  1 +
 inmates/lib/arm-common/Makefile.lib   |  2 +-
 inmates/lib/arm-common/include/uart.h |  1 +
 inmates/lib/arm-common/printk.c   |  2 +
 inmates/lib/arm-common/uart-imx.c | 63 +++
 9 files changed, 111 insertions(+), 3 deletions(-)
 create mode 100644 hypervisor/arch/arm-common/uart-imx.c
 create mode 100644 inmates/lib/arm-common/uart-imx.c

diff --git a/hypervisor/arch/arm-common/Kbuild 
b/hypervisor/arch/arm-common/Kbuild
index 7132312..08cc454 100644
--- a/hypervisor/arch/arm-common/Kbuild
+++ b/hypervisor/arch/arm-common/Kbuild
@@ -17,7 +17,7 @@ ccflags-$(CONFIG_JAILHOUSE_GCOV) += -fprofile-arcs 
-ftest-coverage
 
 OBJS-y += dbg-write.o lib.o psci.o control.o paging.o mmu_cell.o setup.o
 OBJS-y += irqchip.o pci.o ivshmem.o uart-pl011.o uart-xuartps.o uart-mvebu.o
-OBJS-y += uart-hscif.o uart-scifa.o
+OBJS-y += uart-hscif.o uart-scifa.o uart-imx.o
 OBJS-y += gic-v2.o gic-v3.o
 
 COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
diff --git a/hypervisor/arch/arm-common/dbg-write.c 
b/hypervisor/arch/arm-common/dbg-write.c
index 4056778..e9e1467 100644
--- a/hypervisor/arch/arm-common/dbg-write.c
+++ b/hypervisor/arch/arm-common/dbg-write.c
@@ -36,6 +36,8 @@ void arch_dbg_write_init(void)
uart = _hscif_ops;
else if (con_type == JAILHOUSE_CON1_TYPE_SCIFA)
uart = _scifa_ops;
+   else if (con_type == JAILHOUSE_CON1_TYPE_IMX)
+   uart = _imx_ops;
 
if (uart) {
uart->debug_console = _config->debug_console;
diff --git a/hypervisor/arch/arm-common/include/asm/uart.h 
b/hypervisor/arch/arm-common/include/asm/uart.h
index 6301549..9317446 100644
--- a/hypervisor/arch/arm-common/include/asm/uart.h
+++ b/hypervisor/arch/arm-common/include/asm/uart.h
@@ -11,4 +11,4 @@
  */
 
 extern struct uart_chip uart_pl011_ops, uart_xuartps_ops, uart_mvebu_ops,
-   uart_hscif_ops, uart_scifa_ops;
+   uart_hscif_ops, uart_scifa_ops, uart_imx_ops;
diff --git a/hypervisor/arch/arm-common/uart-imx.c 
b/hypervisor/arch/arm-common/uart-imx.c
new file mode 100644
index 000..849f8fc
--- /dev/null
+++ b/hypervisor/arch/arm-common/uart-imx.c
@@ -0,0 +1,39 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright 2017 NXP
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define UTS0xb4
+#define UTXD   0x40
+#define UTS_TXEMPTY(1 << 6)
+
+static void uart_init(struct uart_chip *chip)
+{
+   /* Initialization currently done by Linux */
+}
+
+static bool uart_is_busy(struct uart_chip *chip)
+{
+   return !(mmio_read32(chip->virt_base + UTS) & UTS_TXEMPTY);
+}
+
+static void uart_write_char(struct uart_chip *chip, char c)
+{
+   mmio_write32(chip->virt_base + UTXD, c);
+}
+
+struct uart_chip uart_imx_ops = {
+   .init = uart_init,
+   .is_busy = uart_is_busy,
+   .write_char = uart_write_char,
+};
diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h
index f1810c9..15ed7cd 100644
--- a/include/jailhouse/cell-config.h
+++ b/include/jailhouse/cell-config.h
@@ -190,6 +190,7 @@ struct jailhouse_iommu {
 #define JAILHOUSE_CON1_TYPE_MVEBU  0x0005
 #define JAILHOUSE_CON1_TYPE_HSCIF  0x0006
 #define JAILHOUSE_CON1_TYPE_SCIFA  0x0007
+#define JAILHOUSE_CON1_TYPE_IMX0x0008
 #define JAILHOUSE_CON1_TYPE_MASK   0x000f
 
 #define CON1_TYPE(flags) ((flags) & JAILHOUSE_CON1_TYPE_MASK)
diff --git a/inmates/lib/arm-common/Makefile.lib 
b/inmates/lib/arm-common/Makefile.lib
index c820199..323cabb 100644
--- a/inmates/lib/arm-common/Makefile.lib
+++ b/inmates/lib/arm-common/Makefile.lib
@@ -41,7 +41,7 @@ GCOV_PROFILE := n
 OBJS-y := ../string.o ../cmdline.o
 OBJS-y += printk.o gic.o timer.o
 OBJS-y += uart-jailhouse.o uart-pl011.o uart-8250.o uart-8250-8.o
-OBJS-y += uart-xuartps.o uart-mvebu.o uart-hscif.o uart-scifa.o
+OBJS-y += uart-xuartps.o uart-mvebu.o uart-hscif.o uart-scifa.o uart-imx.o
 OBJS-y += gic-v2.o gic-v3.o
 
 COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
diff --git a/inmates/lib/arm-common/include/uart.h 
b/inmates/lib/arm-common/include/uart.h
index bc65861..abe211e 100644
--- a/inmates/lib/arm-common/include/uart.h
+++ b/inmates/lib/arm-common/include/uart.h
@@ -57,3

[PATCH v2 3/4] Cell configs for imx8mq EVK board.

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/imx8mq-gic-demo.c  |  56 
 configs/arm64/imx8mq.c   | 108 +++
 inmates/lib/arm64/include/mach.h |  12 +
 3 files changed, 176 insertions(+)
 create mode 100644 configs/arm64/imx8mq-gic-demo.c
 create mode 100644 configs/arm64/imx8mq.c

diff --git a/configs/arm64/imx8mq-gic-demo.c b/configs/arm64/imx8mq-gic-demo.c
new file mode 100644
index 000..35a64eb
--- /dev/null
+++ b/configs/arm64/imx8mq-gic-demo.c
@@ -0,0 +1,56 @@
+/*
+ * iMX8MQ target - gic-demo
+ *
+ * Copyright NXP 2018
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .name = "gic-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = 0,
+   .pio_bitmap_size = 0,
+   .num_pci_devices = 0,
+   },
+
+   .cpus = {
+   0x8,
+   },
+
+   .mem_regions = {
+   /* UART1 */ {
+   .phys_start = 0x3086,
+   .virt_start = 0x3086,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+   },
+   /* RAM: Top at 4GB Space */ {
+   .phys_start = 0xffaf,
+   .virt_start = 0,
+   .size = 0x0001,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   }
+};
diff --git a/configs/arm64/imx8mq.c b/configs/arm64/imx8mq.c
new file mode 100644
index 000..608e70b
--- /dev/null
+++ b/configs/arm64/imx8mq.c
@@ -0,0 +1,108 @@
+/*
+ * i.MX8MQ Target
+ *
+ * Copyright 2017 NXP
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * Reservation via device tree: reg = <0x0 0xffaf 0x0 0x51>
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[4];
+   struct jailhouse_irqchip irqchips[3];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .hypervisor_memory = {
+   .phys_start = 0xffc0,
+   .size =   0x0040,
+   },
+   .debug_console = {
+   .address = 0x3086,
+   .size = 0x1000,
+   .flags = JAILHOUSE_CON1_TYPE_IMX |
+JAILHOUSE_CON1_ACCESS_MMIO |
+JAILHOUSE_CON1_REGDIST_4 |
+JAILHOUSE_CON2_TYPE_ROOTPAGE,
+   },
+   .platform_info = {
+   .arm = {
+   .gic_version = 3,
+   .gicd_base = 0x3880,
+   .gicr_base = 0x3888,
+   .maintenance_irq = 25,
+   },
+   },
+   .root_cell = {
+   .name = "imx8mq",
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0xf,
+   },
+
+   .mem_regions = {
+   /* MMIO (permissive) */ {
+   .phys_start = 0x,
+   .virt_start = 0x,
+   .size =   0x4000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* R

[PATCH v2 4/4] README: support for NXP IMX8

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 9dc9841..87be3a3 100644
--- a/README.md
+++ b/README.md
@@ -130,6 +130,8 @@ Hardware requirements (preliminary)
 
 - Xilinx ZCU102 (ZynqMP evaluation board)
 
+- NXP MCIMX8M-EVK
+
 Software requirements
 -
 
-- 
2.7.4

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Re: [PATCH 0/4] Support for NXP IMX8

[Claudio Scordino]

Hi Jan,

2018-03-07 18:27 GMT+01:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2018-03-07 10:13, Claudio Scordino wrote:
> > Initial support for the NXP IMX8 evaluation board.
> >
> > Peng Fang (4):
> >   imx8mq: add UART support
> >   imx8mq: ignore SIP for low-power modes
> >   Cell configs for imx8mq EVK board.
> >   README: support for NXP IMX8
> >
> >  README.md |   2 +
> >  configs/arm64/imx8mq-gic-demo.c   |  56 +
> >  configs/arm64/imx8mq.c| 108
> ++
> >  hypervisor/arch/arm-common/Kbuild |   2 +-
> >  hypervisor/arch/arm-common/dbg-write.c|   2 +
> >  hypervisor/arch/arm-common/include/asm/psci.h |   3 +
> >  hypervisor/arch/arm-common/include/asm/uart.h |   2 +-
> >  hypervisor/arch/arm-common/uart-imx.c |  39 ++
> >  hypervisor/arch/arm64/traps.c |  12 ++-
> >  include/jailhouse/cell-config.h   |   1 +
> >  inmates/lib/arm-common/Makefile.lib   |   2 +-
> >  inmates/lib/arm-common/include/uart.h |   1 +
> >  inmates/lib/arm-common/printk.c   |   2 +
> >  inmates/lib/arm-common/uart-imx.c |  63 +++
> >  inmates/lib/arm64/include/mach.h  |  12 +++
> >  15 files changed, 301 insertions(+), 6 deletions(-)
> >  create mode 100644 configs/arm64/imx8mq-gic-demo.c
> >  create mode 100644 configs/arm64/imx8mq.c
> >  create mode 100644 hypervisor/arch/arm-common/uart-imx.c
> >  create mode 100644 inmates/lib/arm-common/uart-imx.c
> >
>
> Some comments on patch 2, rest looks good on first glance.
>

Good. Going to re-submit soon based on next.


>
> Thanks for sharing early! Too bad I didn't find the live demo at
> Embedded World last week...
>

Ouch! Besides the x86-based demo at our own booth, we had prepared two
additionals demos based on Jailhouse:

   - One at the NXP booth on a imx8 board by SECO, with the RTOS driving a
   DC motor and Linux showing the speed through a Qt application
   - One at the Lauterbach booth on a Ultrascale+ board, with the TRACE32
   tracing information of both the Linux and the RTOS inmates

Considering the effort in preparing such demos, it's a shame if they
haven't respected the promises and haven't shown the demos for all 3 days
long.

Thanks,

   Claudio

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[PATCH 4/4] README: support for NXP IMX8

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 9dc9841..87be3a3 100644
--- a/README.md
+++ b/README.md
@@ -130,6 +130,8 @@ Hardware requirements (preliminary)
 
 - Xilinx ZCU102 (ZynqMP evaluation board)
 
+- NXP MCIMX8M-EVK
+
 Software requirements
 -
 
-- 
2.7.4

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[PATCH 0/4] Support for NXP IMX8

[Claudio Scordino]

Initial support for the NXP IMX8 evaluation board.

Peng Fang (4):
  imx8mq: add UART support
  imx8mq: ignore SIP for low-power modes
  Cell configs for imx8mq EVK board.
  README: support for NXP IMX8

 README.md |   2 +
 configs/arm64/imx8mq-gic-demo.c   |  56 +
 configs/arm64/imx8mq.c| 108 ++
 hypervisor/arch/arm-common/Kbuild |   2 +-
 hypervisor/arch/arm-common/dbg-write.c|   2 +
 hypervisor/arch/arm-common/include/asm/psci.h |   3 +
 hypervisor/arch/arm-common/include/asm/uart.h |   2 +-
 hypervisor/arch/arm-common/uart-imx.c |  39 ++
 hypervisor/arch/arm64/traps.c |  12 ++-
 include/jailhouse/cell-config.h   |   1 +
 inmates/lib/arm-common/Makefile.lib   |   2 +-
 inmates/lib/arm-common/include/uart.h |   1 +
 inmates/lib/arm-common/printk.c   |   2 +
 inmates/lib/arm-common/uart-imx.c |  63 +++
 inmates/lib/arm64/include/mach.h  |  12 +++
 15 files changed, 301 insertions(+), 6 deletions(-)
 create mode 100644 configs/arm64/imx8mq-gic-demo.c
 create mode 100644 configs/arm64/imx8mq.c
 create mode 100644 hypervisor/arch/arm-common/uart-imx.c
 create mode 100644 inmates/lib/arm-common/uart-imx.c

-- 
2.7.4

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[PATCH 1/4] imx8mq: add UART support

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/Kbuild |  2 +-
 hypervisor/arch/arm-common/dbg-write.c|  2 +
 hypervisor/arch/arm-common/include/asm/uart.h |  2 +-
 hypervisor/arch/arm-common/uart-imx.c | 39 +
 include/jailhouse/cell-config.h   |  1 +
 inmates/lib/arm-common/Makefile.lib   |  2 +-
 inmates/lib/arm-common/include/uart.h |  1 +
 inmates/lib/arm-common/printk.c   |  2 +
 inmates/lib/arm-common/uart-imx.c | 63 +++
 9 files changed, 111 insertions(+), 3 deletions(-)
 create mode 100644 hypervisor/arch/arm-common/uart-imx.c
 create mode 100644 inmates/lib/arm-common/uart-imx.c

diff --git a/hypervisor/arch/arm-common/Kbuild 
b/hypervisor/arch/arm-common/Kbuild
index 7132312..08cc454 100644
--- a/hypervisor/arch/arm-common/Kbuild
+++ b/hypervisor/arch/arm-common/Kbuild
@@ -17,7 +17,7 @@ ccflags-$(CONFIG_JAILHOUSE_GCOV) += -fprofile-arcs 
-ftest-coverage
 
 OBJS-y += dbg-write.o lib.o psci.o control.o paging.o mmu_cell.o setup.o
 OBJS-y += irqchip.o pci.o ivshmem.o uart-pl011.o uart-xuartps.o uart-mvebu.o
-OBJS-y += uart-hscif.o uart-scifa.o
+OBJS-y += uart-hscif.o uart-scifa.o uart-imx.o
 OBJS-y += gic-v2.o gic-v3.o
 
 COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
diff --git a/hypervisor/arch/arm-common/dbg-write.c 
b/hypervisor/arch/arm-common/dbg-write.c
index 4056778..e9e1467 100644
--- a/hypervisor/arch/arm-common/dbg-write.c
+++ b/hypervisor/arch/arm-common/dbg-write.c
@@ -36,6 +36,8 @@ void arch_dbg_write_init(void)
uart = _hscif_ops;
else if (con_type == JAILHOUSE_CON1_TYPE_SCIFA)
uart = _scifa_ops;
+   else if (con_type == JAILHOUSE_CON1_TYPE_IMX)
+   uart = _imx_ops;
 
if (uart) {
uart->debug_console = _config->debug_console;
diff --git a/hypervisor/arch/arm-common/include/asm/uart.h 
b/hypervisor/arch/arm-common/include/asm/uart.h
index 6301549..9317446 100644
--- a/hypervisor/arch/arm-common/include/asm/uart.h
+++ b/hypervisor/arch/arm-common/include/asm/uart.h
@@ -11,4 +11,4 @@
  */
 
 extern struct uart_chip uart_pl011_ops, uart_xuartps_ops, uart_mvebu_ops,
-   uart_hscif_ops, uart_scifa_ops;
+   uart_hscif_ops, uart_scifa_ops, uart_imx_ops;
diff --git a/hypervisor/arch/arm-common/uart-imx.c 
b/hypervisor/arch/arm-common/uart-imx.c
new file mode 100644
index 000..849f8fc
--- /dev/null
+++ b/hypervisor/arch/arm-common/uart-imx.c
@@ -0,0 +1,39 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright 2017 NXP
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define UTS0xb4
+#define UTXD   0x40
+#define UTS_TXEMPTY(1 << 6)
+
+static void uart_init(struct uart_chip *chip)
+{
+   /* Initialization currently done by Linux */
+}
+
+static bool uart_is_busy(struct uart_chip *chip)
+{
+   return !(mmio_read32(chip->virt_base + UTS) & UTS_TXEMPTY);
+}
+
+static void uart_write_char(struct uart_chip *chip, char c)
+{
+   mmio_write32(chip->virt_base + UTXD, c);
+}
+
+struct uart_chip uart_imx_ops = {
+   .init = uart_init,
+   .is_busy = uart_is_busy,
+   .write_char = uart_write_char,
+};
diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h
index f1810c9..15ed7cd 100644
--- a/include/jailhouse/cell-config.h
+++ b/include/jailhouse/cell-config.h
@@ -190,6 +190,7 @@ struct jailhouse_iommu {
 #define JAILHOUSE_CON1_TYPE_MVEBU  0x0005
 #define JAILHOUSE_CON1_TYPE_HSCIF  0x0006
 #define JAILHOUSE_CON1_TYPE_SCIFA  0x0007
+#define JAILHOUSE_CON1_TYPE_IMX0x0008
 #define JAILHOUSE_CON1_TYPE_MASK   0x000f
 
 #define CON1_TYPE(flags) ((flags) & JAILHOUSE_CON1_TYPE_MASK)
diff --git a/inmates/lib/arm-common/Makefile.lib 
b/inmates/lib/arm-common/Makefile.lib
index c820199..323cabb 100644
--- a/inmates/lib/arm-common/Makefile.lib
+++ b/inmates/lib/arm-common/Makefile.lib
@@ -41,7 +41,7 @@ GCOV_PROFILE := n
 OBJS-y := ../string.o ../cmdline.o
 OBJS-y += printk.o gic.o timer.o
 OBJS-y += uart-jailhouse.o uart-pl011.o uart-8250.o uart-8250-8.o
-OBJS-y += uart-xuartps.o uart-mvebu.o uart-hscif.o uart-scifa.o
+OBJS-y += uart-xuartps.o uart-mvebu.o uart-hscif.o uart-scifa.o uart-imx.o
 OBJS-y += gic-v2.o gic-v3.o
 
 COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
diff --git a/inmates/lib/arm-common/include/uart.h 
b/inmates/lib/arm-common/include/uart.h
index bc65861..abe211e 100644
--- a/inmates/lib/arm-common/include/uart.h
+++ b/inmates/lib/arm-common/include/uart.h
@@ -57,3

[PATCH 3/4] Cell configs for imx8mq EVK board.

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/arm64/imx8mq-gic-demo.c  |  56 
 configs/arm64/imx8mq.c   | 108 +++
 inmates/lib/arm64/include/mach.h |  12 +
 3 files changed, 176 insertions(+)
 create mode 100644 configs/arm64/imx8mq-gic-demo.c
 create mode 100644 configs/arm64/imx8mq.c

diff --git a/configs/arm64/imx8mq-gic-demo.c b/configs/arm64/imx8mq-gic-demo.c
new file mode 100644
index 000..35a64eb
--- /dev/null
+++ b/configs/arm64/imx8mq-gic-demo.c
@@ -0,0 +1,56 @@
+/*
+ * iMX8MQ target - gic-demo
+ *
+ * Copyright NXP 2018
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .name = "gic-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = 0,
+   .pio_bitmap_size = 0,
+   .num_pci_devices = 0,
+   },
+
+   .cpus = {
+   0x8,
+   },
+
+   .mem_regions = {
+   /* UART1 */ {
+   .phys_start = 0x3086,
+   .virt_start = 0x3086,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+   },
+   /* RAM: Top at 4GB Space */ {
+   .phys_start = 0xffaf,
+   .virt_start = 0,
+   .size = 0x0001,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   }
+};
diff --git a/configs/arm64/imx8mq.c b/configs/arm64/imx8mq.c
new file mode 100644
index 000..608e70b
--- /dev/null
+++ b/configs/arm64/imx8mq.c
@@ -0,0 +1,108 @@
+/*
+ * i.MX8MQ Target
+ *
+ * Copyright 2017 NXP
+ *
+ * Authors:
+ *  Peng Fan <peng@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * Reservation via device tree: reg = <0x0 0xffaf 0x0 0x51>
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[4];
+   struct jailhouse_irqchip irqchips[3];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .hypervisor_memory = {
+   .phys_start = 0xffc0,
+   .size =   0x0040,
+   },
+   .debug_console = {
+   .address = 0x3086,
+   .size = 0x1000,
+   .flags = JAILHOUSE_CON1_TYPE_IMX |
+JAILHOUSE_CON1_ACCESS_MMIO |
+JAILHOUSE_CON1_REGDIST_4 |
+JAILHOUSE_CON2_TYPE_ROOTPAGE,
+   },
+   .platform_info = {
+   .arm = {
+   .gic_version = 3,
+   .gicd_base = 0x3880,
+   .gicr_base = 0x3888,
+   .maintenance_irq = 25,
+   },
+   },
+   .root_cell = {
+   .name = "imx8mq",
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0xf,
+   },
+
+   .mem_regions = {
+   /* MMIO (permissive) */ {
+   .phys_start = 0x,
+   .virt_start = 0x,
+   .size =   0x4000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* R

[PATCH 2/4] imx8mq: ignore SIP for low-power modes

[Claudio Scordino]

From: Peng Fang <peng@nxp.com>

On i.MX8MQ, SIP is mainly used for low-power mode, so it can be ignored.
See the following reference:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/arm-sip-service.rst

Signed-off-by: Peng Fang <peng@nxp.com>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/include/asm/psci.h |  3 +++
 hypervisor/arch/arm64/traps.c | 12 +---
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/hypervisor/arch/arm-common/include/asm/psci.h 
b/hypervisor/arch/arm-common/include/asm/psci.h
index e635aec..76684db 100644
--- a/hypervisor/arch/arm-common/include/asm/psci.h
+++ b/hypervisor/arch/arm-common/include/asm/psci.h
@@ -32,6 +32,9 @@
 #define PSCI_CPU_IS_ON 0
 #define PSCI_CPU_IS_OFF1
 
+#define IS_SIP_32(hvc) (((hvc) >> 24) == 0x82)
+#define IS_SIP_64(hvc) (((hvc) >> 24) == 0xc2)
+
 #define IS_PSCI_32(hvc)(((hvc) >> 24) == 0x84)
 #define IS_PSCI_64(hvc)(((hvc) >> 24) == 0xc4)
 #define IS_PSCI_UBOOT(hvc) (((hvc) >> 8) == 0x95c1ba)
diff --git a/hypervisor/arch/arm64/traps.c b/hypervisor/arch/arm64/traps.c
index cd30923..d0a2737 100644
--- a/hypervisor/arch/arm64/traps.c
+++ b/hypervisor/arch/arm64/traps.c
@@ -36,10 +36,16 @@ static int handle_smc(struct trap_context *ctx)
 {
unsigned long *regs = ctx->regs;
 
-   if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
+   if (IS_PSCI_32(regs[0]) || IS_PSCI_64(regs[0])) {
+   regs[0] = psci_dispatch(ctx);
+#ifdef CONFIG_MACH_IMX8MQ
+   } else if (IS_SIP_32(regs[0]) || IS_SIP_64(regs[0])) {
+   /* This can be ignored */
+   regs[0] = PSCI_NOT_SUPPORTED;
+#endif
+   } else {
return TRAP_UNHANDLED;
-
-   regs[0] = psci_dispatch(ctx);
+   }
 
arch_skip_instruction(ctx);
 
-- 
2.7.4

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[PATCH v2] Documentation: supported free OSs; memory reservation through DT

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 FAQ.md| 9 +
 README.md | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/FAQ.md b/FAQ.md
index 81985f8..cf87a52 100644
--- a/FAQ.md
+++ b/FAQ.md
@@ -48,6 +48,15 @@ Otherwise, use the ```msg_reply_timeout``` field in the cell 
config to specify
 the number of idle loops the root cell must wait for a reply before considering
 the cell as failing.
 
+**Q: Which open-source OSs can be currently run in non-root cells?**
+
+A: The following open-source OSs have been currently ported to Jailhouse:
+* [Linux](Documentation/non-root-linux.txt)
+* [FreeRTOS](https://github.com/siemens/freertos-cell)
+* [ERIKA3 
RTOS](http://www.erika-enterprise.com/wiki/index.php?title=ERIKA3_on_the_Jailhouse_hypervisor)
+* [Zephyr](https://www.zephyrproject.org)
+
+
 Debugging
 -
 
diff --git a/README.md b/README.md
index 9dc9841..71ac911 100644
--- a/README.md
+++ b/README.md
@@ -170,7 +170,7 @@ Software requirements
 additional cell. This currently has to be pre-allocated during boot-up.
 On ARM this can be obtained by reducing the amount of memory seen by the
 kernel (through the `mem=` kernel boot parameter) or by modifying the
-Device Tree.
+Device Tree (i.e. the `reserved-memory` node).
 
 
 Build & Installation
-- 
2.7.4

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[PATCH] FAQ: references for non-root OSs

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 FAQ.md| 8 
 README.md | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/FAQ.md b/FAQ.md
index 81985f8..f139fa2 100644
--- a/FAQ.md
+++ b/FAQ.md
@@ -48,6 +48,14 @@ Otherwise, use the ```msg_reply_timeout``` field in the cell 
config to specify
 the number of idle loops the root cell must wait for a reply before considering
 the cell as failing.
 
+**Q: Which OSs can be currently run in non-root cells?**
+
+A: The following OSs have been currently ported to Jailhouse:
+* [Linux](Documentation/non-root-linux.txt)
+* [FreeRTOS](https://github.com/siemens/freertos-cell)
+* [ERIKA3 
RTOS](http://www.erika-enterprise.com/wiki/index.php?title=ERIKA3_on_the_Jailhouse_hypervisor)
+
+
 Debugging
 -
 
diff --git a/README.md b/README.md
index 9dc9841..71ac911 100644
--- a/README.md
+++ b/README.md
@@ -170,7 +170,7 @@ Software requirements
 additional cell. This currently has to be pre-allocated during boot-up.
 On ARM this can be obtained by reducing the amount of memory seen by the
 kernel (through the `mem=` kernel boot parameter) or by modifying the
-Device Tree.
+Device Tree (i.e. the `reserved-memory` node).
 
 
 Build & Installation
-- 
2.7.4

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Re: Jailhouse on imx8

[Claudio Scordino]

Hi Jan,

>>>
> >>> -   if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
> >>> +   if (IS_PSCI_32(regs[0]) || IS_PSCI_64(regs[0])) {
> >>> +   regs[0] = psci_dispatch(ctx);
> >>> +   } else if (IS_SIP_32(regs[0]) || IS_SIP_64(regs[0])) {
> >>> +   /* Nothing */
> >>> +   //printk("SIP service\n");
> >>> +   //regs[0] = sip_dispatch(ctx);
> >>
> >> Hmm. What is SIP? Why can we simply ignore the calls? Why no returning
> >> of some code in regs[0])? And are these function call ID
> >> architecture-wide reserved, just like PSCI?
> >
> > See here for SIP.
> > https://github.com/ARM-software/arm-trusted-firmware/
> blob/master/docs/arm-sip-service.rst
> >
> > on i.MX8MQ, SIP is mainly used for Low Power related controll. The
> > previous patch is a hack method. Per my understanding, jailhouse is
> > for real time case, low power feature will introduce lots latency,
> > so ignore them here no harm for me, the previous patch is a hack.
> >
> > Since SIP is silicon provider service, it is better to provide a callback
> > function for different SoCs.
> >
>
> Thanks for the pointer! From reading through it and studying the SMC
> calling convention again, I guess we should at least return -1 on
> ignored calls.
>

You mean, returning TRAP_FORBIDDEN ? Wouldn't TRAP_UNHANDLED be more
meaningful ?

In both cases, we should also modify the behavior of arch_handle_trap() to
not panic (the SMC must be just ignored).

What about adding also a TRAP_IGNORED flag ?

Thanks,

 Claudio

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ERIKA Enterprise RTOS on Jailhouse

[Claudio Scordino]

 Dear all,

we are glad to announce the availability of the source code of the ERIKA
Enterprise RTOS for Jailhouse on the ARMv8 Cortex-A architecture. The
support has been successfully tested on the NVIDIA Jetson TX1 and the
Xilinx Zynq Ultrascale+ ZCU102 boards. The source code is available on
GitHub (https://github.com/evidence/erika3).

ERIKA Enterprise (http://www.erika-enterprise.com) is an open-source RTOS
designed and certified for the automotive market, already used in
production by some companies operating in this domain. The development
activity has been financed by the European Commission through the HERCULES
H2020 project (http://hercules2020.eu).

Our Proof Of Concept consists of a mixed-criticality system for automotive,
with ERIKA Enterprise running safety-critical tasks (e.g., Electronic
Control Unit), Linux performing less critical tasks (e.g., networking,
logging, HMI) and Jailhouse enforcing the isolation between the two
partitions.

This Proof Of Concept will be shown at the next Embedded World through some
demos (Hall 4 stand 545) and a presentation at the conference. Feel free to
contact me privately in case you need a free ticket for the event.

In the next weeks, we will improve the documentation about building and
running the RTOS on Jailhouse.

Best regards,

Claudio

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Re: Jailhouse on imx8

[Claudio Scordino]

Hi Peng,

2018-02-11 8:30 GMT+01:00 Peng Fan <van.free...@gmail.com>:

> Hi Claudio,
>
> On Mon, Feb 05, 2018 at 09:40:29AM +0100, Claudio Scordino wrote:
> >Hi all,
> >
> >thanks to the patch by Peng Fan I have been able of successfully enable
> >Jailhouse and create a cell.
> >
> >However, the gic-demo does not work properly (i.e. it does not fire).
> >It could be some misconfiguration of the GIC.
> >The dts entry says:
> >
> >interrupt-controller@3880 {
> >compatible = "arm,gic-v3";
> >reg = <0x0 0x3880 0x0 0x1 0x0 0x3888 0x0
> 0xc
> >0x0 0x30340x0 0x1>;
> >#interrupt-cells = <0x3>;
> >interrupt-controller;
> >interrupts = <0x1 0x9 0x4>;
> >interrupt-parent = <0xa>;
> >linux,phandle = <0xa>;
> >phandle = <0xa>;
> >};
> >
> >
> >The board is the MCIMX8M-EVK (https://www.nxp.com/support/
> developer-resources/
> >run-time-software/i.mx-developer-resources/
> >evaluation-kit-for-the-i.mx-8m-applications-processor:MCIMX8M-EVK).
> >The SoC is an i.MX 8MQuad (i.e. Cortex-A53).
> >The reference manual (available here: https://www.nxp.com/docs/en/
> >reference-manual/IMX8MDQLQRM.pdf) mentions a GICv3/v4, without providing
> much
> >information.
> >
> >Attached the configs of the cells and the dts.
>
> I just bringup jailhouse and gic-demo on my i.MX8MQ EVK board.
> Code has been pushed to https://github.com/MrVan/jailhouse/tree/imx8mq-evk
> You may give a look and see if there is something wrong configured in your
> side.
> I did not try other demo, only gic-demo tested.
>

Thank you so much.
So my problem turned out to be:

+/*
+ * Note: The GICR_V3_BASE needs to be CPU0/1/2/3 specific
+ * If the gic-demo use CPU2, then the GICR_V3_BASE needs to be CPU3 GICR
+ * Address is 0x3888 + x * 2 * 64K
+ */
+#define GICR_V3_BASE   ((void *)0x388e)/* CPU 3 */

The rest of the code was almost identical.

@Jan: should we put the GICR_V3_BASE field inside the cell config file, as
it is cpu-dependent ?

@Peng: I think you should split the commits and post the patches for
upstreaming...


>
> Also would you mind share more information that what are you going to
> achieve or solve what problem with jailhouse and your rtos?
>

Well, the general idea is a mixed-criticality system, with the RTOS
handling safet-critical tasks and Linux the non-critical tasks.
We plan to show the demo a the next Embedded World.
I'll give you more details (and the location of the source code of the
RTOS) by the next week.

Many thanks and best regards,

Claudio

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Re: Jailhouse on imx8

[Claudio Scordino]

Hi all,

thanks to the patch by Peng Fan I have been able of successfully enable
Jailhouse and create a cell.

However, the gic-demo does not work properly (i.e. it does not fire).
It could be some misconfiguration of the GIC.
The dts entry says:

interrupt-controller@3880 {
compatible = "arm,gic-v3";
reg = <0x0 0x3880 0x0 0x1 0x0 0x3888 0x0
0xc 0x0 0x30340x0 0x1>;
#interrupt-cells = <0x3>;
interrupt-controller;
interrupts = <0x1 0x9 0x4>;
interrupt-parent = <0xa>;
linux,phandle = <0xa>;
phandle = <0xa>;
};


The board is the MCIMX8M-EVK (
https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/evaluation-kit-for-the-i.mx-8m-applications-processor:MCIMX8M-EVK
).
The SoC is an i.MX 8MQuad (i.e. Cortex-A53).
The reference manual (available here:
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf) mentions a
GICv3/v4, without providing much information.

Attached the configs of the cells and the dts.

Many thanks and best regards,

  Claudio






2018-02-04 13:03 GMT+01:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2018-02-03 11:52, Peng Fan wrote:
> > Hi Jan,
> > On Tue, Jan 30, 2018 at 03:00:34PM +0100, Jan Kiszka wrote:
> >> On 2018-01-30 13:04, Peng Fan wrote:
> >>>
> >>> Hi,
> >>> On Tue, Jan 30, 2018 at 09:50:25AM +0100, Claudio Scordino wrote:
> >>>> addr2line reported arch/arm64/kernel/smccc-call.S:41
> >>>>
> >>>> grepping __arm_smccc_smc (then, arm_smccc_smc), we've found the value
> of x0
> >>>> (0xC200) to be
> >>>>
> >>>>
> >>>>#define FSL_SIP_GPC 0xC200
> >>>>
> >>>>
> >>>> which is used by drivers/soc/imx/gpc-psci.c (e.g., by
> imx_gpc_pd_power_off).
> >>>> This file gets compiled when the symbol CONFIG_ARCH_FSL_IMX8MQ is
> defined.
> >>>>
> >>>> We cannot exclude such file from the kernel build, so I guess we need
> to make
> >>>> Jailhouse aware of this SMC.
> >>>> If so, should we add an entry to psci_dispatch() ? How should behave
> the
> >>>> function ?
> >>>
> >>> If this is SIP issue, you could try the following patch.
> >>>
> >>> From cd0c701c1b67215e7769e10ad015be0616611465 Mon Sep 17 00:00:00 2001
> >>> From: Peng Fan <peng@nxp.com>
> >>> Date: Fri, 27 Oct 2017 13:42:37 +0800
> >>> Subject: [PATCH] ignore sip now
> >>>
> >>> Signed-off-by: Peng Fan <peng@nxp.com>
> >>> ---
> >>>  hypervisor/arch/arm-common/include/asm/psci.h |  2 ++
> >>>  hypervisor/arch/arm64/traps.c | 10 +++---
> >>>  2 files changed, 9 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/hypervisor/arch/arm-common/include/asm/psci.h
> b/hypervisor/arch/arm-common/include/asm/psci.h
> >>> index 09712c6e..71e725ce 100644
> >>> --- a/hypervisor/arch/arm-common/include/asm/psci.h
> >>> +++ b/hypervisor/arch/arm-common/include/asm/psci.h
> >>> @@ -35,6 +35,8 @@
> >>>  #define PSCI_CPU_IS_ON 0
> >>>  #define PSCI_CPU_IS_OFF1
> >>>
> >>> +#define IS_SIP_32(hvc) (((hvc) >> 24) == 0x82)
> >>> +#define IS_SIP_64(hvc) (((hvc) >> 24) == 0xc2)
> >>>  #define IS_PSCI_32(hvc)(((hvc) >> 24) == 0x84)
> >>>  #define IS_PSCI_64(hvc)(((hvc) >> 24) == 0xc4)
> >>>  #define IS_PSCI_UBOOT(hvc) (((hvc) >> 8) == 0x95c1ba)
> >>> diff --git a/hypervisor/arch/arm64/traps.c
> b/hypervisor/arch/arm64/traps.c
> >>> index 4a35d0d5..65ded596 100644
> >>> --- a/hypervisor/arch/arm64/traps.c
> >>> +++ b/hypervisor/arch/arm64/traps.c
> >>> @@ -35,11 +35,15 @@ static int handle_smc(struct trap_context *ctx)
> >>>  {
> >>> unsigned long *regs = ctx->regs;
> >>>
> >>> -   if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
> >>> +   if (IS_PSCI_32(regs[0]) || IS_PSCI_64(regs[0])) {
> >>> +   regs[0] = psci_dispatch(ctx);
> >>> +   } else if (IS_SIP_32(regs[0]) || IS_SIP_64(regs[0])) {
> >>> +   /* Nothing */
> >>> +   //print

Re: Jailhouse on imx8

[Claudio Scordino]

addr2line reported arch/arm64/kernel/smccc-call.S:41

grepping __arm_smccc_smc (then, arm_smccc_smc), we've found the value of x0
(0xC200) to be

#define FSL_SIP_GPC 0xC200


which is used by drivers/soc/imx/gpc-psci.c (e.g., by imx_gpc_pd_power_off).
This file gets compiled when the symbol CONFIG_ARCH_FSL_IMX8MQ is defined.

We cannot exclude such file from the kernel build, so I guess we need to
make Jailhouse aware of this SMC.
If so, should we add an entry to psci_dispatch() ? How should behave the
function ?

Many thanks and best regards,

   Claudio



2018-01-29 16:16 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>:

> On 01/29/2018 03:53 PM, Claudio Scordino wrote:
> > Hi Ralf,
> >
> > thank you for the help.
> >
> > Attached: dts, kernel config and the two config files (root and inmate).
> So according to imx8.dts, they're using default function ids for CPU
> suspend/off/on.
>
> But there's an interesting comment in
> ./arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts:
>
> /* First 128KB is for PSCI ATF. */
> /memreserve/ 0x4000 0x0002;
>
> So seems like there's at least some monitor.
>
> Anyway, could you objdump your kernel and look where PC is pointing to?
>
> Thanks
>   Ralf
> >
> > Kernel is available here:
> > https://source.codeaurora.org/external/imx/linux-imx
> > <https://source.codeaurora.org/external/imx/linux-imx> (likely the
> > branch is imx_4.9.51_imx8_beta1).
> > I've applied the patch for exporting __hyp_stub_vectors and set
> > "mem=2992M vmalloc=512M" in the cmdline.
> >
> > Unfortunately, CONFIG_CRASH_CELL_ON_PANIC  did not print the expected
> > backtrace (is it possible ?)
> >
> > Many thanks and best regards,
> >
> >Claudio
> >
> >
> >
> >
> >
> > 2018-01-29 11:25 GMT+01:00 Ralf Ramsauer
> > <ralf.ramsa...@oth-regensburg.de <mailto:ralf.ramsa...@oth-regensburg.de
> >>:
> >
> > Hi Claudio,
> >
> > On 01/29/2018 10:15 AM, Claudio Scordino wrote:
> > > Hi all,
> > >
> > > I'm porting Jailhouse on the imx8 EVK board.
> > >
> > > After implementing the uart driver (thanks, Ralf) I've been able of
> > > successfully running the "jailhouse enable" command.
> > >
> > > However, the "jailhouse cell create" deadlocks the machine with the
> > > following error message:
> > >
> > > FATAL: unhandled trap (exception class 0x17)
> > This means Jailhouse is missing a trap handler (see
> > hypervisor/arch/arm64/traps.c:185).
> >
> > The exception class 0x17 stands for:
> > hypervisor/arch/arm64/include/asm/sysregs.h:#define ESR_EC_SMC64
> >0x17
> >
> > So we're missing a PSCI handler, because this is the only path in
> > handle_smc() that can return TRAP_UNHANDLED:
> > if (!IS_PSCI_32(regs[0]) && !IS_PSCI_64(regs[0]))
> > return TRAP_UNHANDLED;
> >
> > And those definitions are:
> > hypervisor/arch/arm-common/include/asm/psci.h:#define
> IS_PSCI_32(hvc)
> >(((hvc) >> 24) == 0x84)
> > hypervisor/arch/arm-common/include/asm/psci.h:#define
> IS_PSCI_64(hvc)
> >(((hvc) >> 24) == 0xc4)
> >
> > So looks like we have some unimplemented PSCI/SMC call.
> > > Cell state before exception:
> > >  pc: 0808eb60   lr: 0852cbf8 spsr: 21c5
>  EL1
> > What's behind PC? Could you also share your config with us?
> > >  sp: 8000b20afbe0  esr: 17 1 000
> > >  x0: c200   x1: 0004   x2:
> 0040
> > PSCI calls store their function id in x0.
> >
> > And here we have 0xc200. In case of SMC64, we shr by 24 bits,
> which
> > means 0xc200 >> 24 = 0xc2 Jailhouse expects 0xc4 in case of
> > PSCI. Hmm.
> >
> > So this doesn't look like a typical PSCI call to me (just looked at
> the
> > PSCI platform design document, 0xc200 is not valid). Looks like
> this
> > is some other platform specific SMC. Is there another monitor
> running?
> >
> > So who emits this call?
> >
> > Just a guess: your root cell is probably trying to offline the CPU,
> > emits the PSCI and crashes.
> >
> > PSCI function IDs can usually be found in the DTS(I). Could you
> please
> > poi

[PATCH v2] FAQ: handling inmates that do not reply to requests

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 FAQ.md | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/FAQ.md b/FAQ.md
index 720eec1..68319f8 100644
--- a/FAQ.md
+++ b/FAQ.md
@@ -38,6 +38,16 @@ announced for new Xeon processors. Of course, running code 
under Jailhouse is
 slightly slower than on a dedicated uniprocessor machine, but virtualization
 always comes at price.
 
+**Q: Fault tolerance: how can I prevent a buggy/misbehaving inmate from hanging
+the root cell by never replying to a request?**
+
+A: If the cell does not need or should not be able to vote over system
+reconfigurations, you can simply set ```.flags = 
JAILHOUSE_CELL_PASSIVE_COMMREG```
+in the cell config.
+Otherwise, use the ```msg_reply_timeout``` field in the cell config to specify
+the number of idle loops the root cell must wait a reply before considering the
+cell as failing.
+
 Debugging
 -
 
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[PATCH] FAQ: how to stop waiting a message reply after a certain amount of time

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 FAQ.md | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/FAQ.md b/FAQ.md
index 720eec1..fc0a164 100644
--- a/FAQ.md
+++ b/FAQ.md
@@ -38,6 +38,13 @@ announced for new Xeon processors. Of course, running code 
under Jailhouse is
 slightly slower than on a dedicated uniprocessor machine, but virtualization
 always comes at price.
 
+**Q: Fault tolerance: how can I prevent a buggy/misbehaving inmate from hanging
+the root cell by never replying to a request?**
+
+A: Use the ```msg_reply_timeout``` field in the cell config to specify the
+number of idle loops the root cell must wait a reply before considering the
+cell as failing.
+
 Debugging
 -
 
-- 
2.7.4

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Re: booting linux on non-root cell on TX1(arm64) board

[Claudio Scordino]

Hi,

Il 19/12/2017 08:45, vmore5...@gmail.com ha scritto:

Hi,

Greeting to all.I am doing some testing with jailhouse hypervisor.

Hardware - Nvidia TX1(arm64)
Kernel   - Linux 4.14.rc4 (maintained by JH-devel team)

I have booted TX1 board with kernel(linux 4.14.rc4).I have succesfully tested 
the bare metal applications provided by JH team.
Now i am trying to boot a linux kernel(3.10.96)on non-root cell.But here i got 
stucked.


Note that the latest version of the Linux kernel provided by Nvidia for TX1 is 
4.4 (which superseded the previous 3.10 kernel).
You'll probably need the latest version of JetPack to install it.

Best regards,

  Claudio

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Re: Running ivshmem-demo in Jetson TK1.

[Claudio Scordino]

Hi guys,

2017-08-09 15:23 GMT+02:00 Henning Schild :

> Hey,
>
> unfortunately Jonas never published his overall changes, maybe now he
> understands why i kindly asked him to do so.
> I think Jonas maybe ran into every single problem one could encounter
> on the way, so if you read the thread you will probably be able to come
> up with a similar patch at some point. That would be the duplication of
> efforts, getting a first working patch into a mergeable form is another
> story.
>
> If there are legal reasons to not publish code on the list i suggest
> you exchange patches between each other. But of cause i would like to
> see contributions eventually ;).
>
>
We need to run IVSHMEM on the TX1.
Any chance of upstreaming those patches to not waste time re-inventing the
wheel ?
If that's not possible, please send me a copy privately.

Many thanks and best regards,

 Claudio

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[PATCH v5] Stop waiting for message reply after a certain amount of time

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance. We therefore wait a
certain amount of time after which we consider the cell as failing.

Since the hypervisor does not currently have any notion of time (to
check the amount of elapsed time waiting), we just wait a certain amount
of loops.  The number of loops is set through the "msg_reply_timeout"
field in the cell config. By default, the timeout mechanism is disabled.
We will likely want to go from loops to a proper timing unit if the
hypervisor will get support for timers.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c   | 17 +++--
 hypervisor/include/jailhouse/cell-config.h |  3 ++-
 tools/jailhouse-cell-linux |  2 +-
 tools/jailhouse-hardware-check |  2 +-
 4 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index 7d38a34..b8797a5 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -101,12 +101,16 @@ static void cell_resume(struct per_cpu *cpu_data)
  * @return True if a request message was approved or reception of an
  *informational message was acknowledged by the target cell. It also
  *returns true if the target cell does not support an active
- *communication region, is shut down or in failed state. Returns
- *false on request denial or invalid replies.
+ *communication region, is shut down or in failed state.
+ *In case of timeout (if enabled) it also stops the cell and put it
+ *in failed state.
+ *Returns false on request denial or invalid replies.
  */
 static bool cell_exchange_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
+   u64 timeout = cell->config->msg_reply_timeout;
+
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
return true;
 
@@ -129,6 +133,15 @@ static bool cell_exchange_message(struct cell *cell, u32 
message,
if (reply != JAILHOUSE_MSG_NONE)
return false;
 
+   if ((cell->config->msg_reply_timeout > 0) && (--timeout == 0)) {
+   printk("Timeout expired when waiting for reply from "
+   "target cell\n");
+   cell_suspend(cell, this_cpu_data());
+   cell->comm_page.comm_region.cell_state =
+   JAILHOUSE_CELL_FAILED;
+   return true;
+   }
+
cpu_relax();
}
 }
diff --git a/hypervisor/include/jailhouse/cell-config.h 
b/hypervisor/include/jailhouse/cell-config.h
index 92c9a4b..2eda1bc 100644
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -43,7 +43,7 @@
  * Incremented on any layout or semantic change of system or cell config.
  * Also update HEADER_REVISION in tools.
  */
-#define JAILHOUSE_CONFIG_REVISION  6
+#define JAILHOUSE_CONFIG_REVISION  7
 
 #define JAILHOUSE_CELL_NAME_MAXLEN 31
 
@@ -77,6 +77,7 @@ struct jailhouse_cell_desc {
__u32 vpci_irq_base;
 
__u64 cpu_reset_address;
+   __u64 msg_reply_timeout;
 } __attribute__((packed));
 
 #define JAILHOUSE_MEM_READ 0x0001
diff --git a/tools/jailhouse-cell-linux b/tools/jailhouse-cell-linux
index 15bbeac..ecfb569 100755
--- a/tools/jailhouse-cell-linux
+++ b/tools/jailhouse-cell-linux
@@ -510,7 +510,7 @@ class MemoryRegion:
 
 class Config:
 _HEADER_FORMAT = '6sH32s4xIQ'
-_HEADER_REVISION = 6
+_HEADER_REVISION = 7
 
 def __init__(self, config_file):
 self.data = config_file.read()
diff --git a/tools/jailhouse-hardware-check b/tools/jailhouse-hardware-check
index 690928e..357280d 100755
--- a/tools/jailhouse-hardware-check
+++ b/tools/jailhouse-hardware-check
@@ -113,7 +113,7 @@ class Sysconfig:
 X86_MAX_IOMMU_UNITS = 8
 X86_IOMMU_SIZE = 20
 
-HEADER_REVISION = 6
+HEADER_REVISION = 7
 HEADER_FORMAT = '6sH'
 
 def __init__(self, path):
-- 
2.7.4

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Re: Jailhouse compilation error?

[Claudio Scordino]

Hi,

2017-09-26 6:17 GMT+02:00 Arun raj :

> Hi team,
>
>   I'm trying to bring the jailhouse on jetson TX2 board.while
> compilation
>   itself i'm facing error.i'm having kernel 4.4.38 version.Is anyone
> knkow
>   how to resolve this following error?
>

Note that you will need a more recent release of the kernel to run
Jailhouse on ARM64.
See the Requirements section on the main page.

If you really need the kernel provided by Nvidia and you can't run a
Vanilla kernel, you could try using Jailhouse for TX1
(available at https://github.com/evidence/linux-jailhouse-tx1).
However, this path is discouraged as you would miss all the latest features
and improvements.
If you can, use the mainline tree.

Best regards,

  Claudio

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[PATCH v4 0/2] Don't let inmates hang the root cell by never replying

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance. We therefore wait a certain
amount of time after which we consider the cell as failing.

Claudio Scordino (2):
  Rename cell_send_message() to cell_exchange_message()
  Stop waiting for message reply after a certain amount of time

 hypervisor/control.c   | 23 ++-
 hypervisor/include/jailhouse/cell-config.h |  3 ++-
 2 files changed, 20 insertions(+), 6 deletions(-)

-- 
2.7.4

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[PATCH v4 1/2] Rename cell_send_message() to cell_exchange_message()

[Claudio Scordino]

This patch simply renames function cell_send_message() to
cell_exchange_message().

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index b1beed9..230e21a 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -101,10 +101,10 @@ static void cell_resume(struct per_cpu *cpu_data)
  * @return True if a request message was approved or reception of an
  *informational message was acknowledged by the target cell. It also
  *returns true if the target cell does not support an active
- *communication region, is shut down or in failed state. Returns
- *false on request denial or invalid replies.
+ *communication region, is shut down or in failed state.
+ *Returns false on request denial or invalid replies.
  */
-static bool cell_send_message(struct cell *cell, u32 message,
+static bool cell_exchange_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
@@ -150,7 +150,7 @@ static void cell_reconfig_completed(void)
struct cell *cell;
 
for_each_non_root_cell(cell)
-   cell_send_message(cell, JAILHOUSE_MSG_RECONFIG_COMPLETED,
+   cell_exchange_message(cell, JAILHOUSE_MSG_RECONFIG_COMPLETED,
  MSG_INFORMATION);
 }
 
@@ -489,7 +489,7 @@ err_resume:
 
 static bool cell_shutdown_ok(struct cell *cell)
 {
-   return cell_send_message(cell, JAILHOUSE_MSG_SHUTDOWN_REQUEST,
+   return cell_exchange_message(cell, JAILHOUSE_MSG_SHUTDOWN_REQUEST,
 MSG_REQUEST);
 }
 
-- 
2.7.4

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[PATCH v4 2/2] Stop waiting for message reply after a certain amount of time

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance. We therefore wait a
certain amount of time after which we consider the cell as failing.

Since the hypervisor does not currently have any notion of time (to
check the amount of elapsed time waiting), we just wait a certain amount
of loops.  The number of loops is set through the "msg_reply_timeout"
field in the cell config. By default, the timeout mechanism is disabled.
We will likely want to go from loops to a proper timing unit if the
hypervisor will get support for timers.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c   | 13 +
 hypervisor/include/jailhouse/cell-config.h |  3 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index 230e21a..9a68360 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -102,11 +102,15 @@ static void cell_resume(struct per_cpu *cpu_data)
  *informational message was acknowledged by the target cell. It also
  *returns true if the target cell does not support an active
  *communication region, is shut down or in failed state.
+ *In case of timeout (if enabled) it also stops the cell and put it
+ *in failed state.
  *Returns false on request denial or invalid replies.
  */
 static bool cell_exchange_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
+   u64 timeout = cell->config->msg_reply_timeout;
+
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
return true;
 
@@ -129,6 +133,15 @@ static bool cell_exchange_message(struct cell *cell, u32 
message,
if (reply != JAILHOUSE_MSG_NONE)
return false;
 
+   if ((cell->config->msg_reply_timeout > 0) && (--timeout == 0)) {
+   printk("Timeout expired when waiting for reply from "
+   "target cell\n");
+   cell_suspend(cell, this_cpu_data());
+   cell->comm_page.comm_region.cell_state =
+   JAILHOUSE_CELL_FAILED;
+   return true;
+   }
+
cpu_relax();
}
 }
diff --git a/hypervisor/include/jailhouse/cell-config.h 
b/hypervisor/include/jailhouse/cell-config.h
index 92c9a4b..2eda1bc 100644
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -43,7 +43,7 @@
  * Incremented on any layout or semantic change of system or cell config.
  * Also update HEADER_REVISION in tools.
  */
-#define JAILHOUSE_CONFIG_REVISION  6
+#define JAILHOUSE_CONFIG_REVISION  7
 
 #define JAILHOUSE_CELL_NAME_MAXLEN 31
 
@@ -77,6 +77,7 @@ struct jailhouse_cell_desc {
__u32 vpci_irq_base;
 
__u64 cpu_reset_address;
+   __u64 msg_reply_timeout;
 } __attribute__((packed));
 
 #define JAILHOUSE_MEM_READ 0x0001
-- 
2.7.4

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[PATCH v3 0/2] Don't let inmates hang the root cell by never replying

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance. We therefore wait a certain
amount of time after which we consider the cell as failing.

Claudio Scordino (2):
  Make cell_send_message() return errors
  Stop waiting message reply after a certain amount of time

 hypervisor/control.c   | 33 --
 hypervisor/include/jailhouse/cell-config.h |  1 +
 hypervisor/include/jailhouse/entry.h   |  1 +
 3 files changed, 24 insertions(+), 11 deletions(-)

-- 
2.7.4

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[PATCH v3 2/2] Stop waiting message reply after a certain amount of time

[Claudio Scordino]

Since the hypervisor does not currently have any notion of time (to
check the amount of elapsed time waiting), we just wait a certain amount
of loops.

The number of loops is set through the "reply_timeout" field in the cell
config. By default, the timeout mechanism is disabled.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c   | 13 -
 hypervisor/include/jailhouse/cell-config.h |  1 +
 hypervisor/include/jailhouse/entry.h   |  1 +
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index 42206c4..f480ea1 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -103,10 +103,13 @@ static void cell_resume(struct per_cpu *cpu_data)
  *It also returns 0 if the target cell does not support an active
  *communication region, is shut down or in failed state.
  *Returns a negative error code on request denial or invalid replies.
+ *In case of timeout (if enabled) it also stops the cell and put it in
+ *failed state.
  */
 static int cell_send_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
+   u32 timeout = cell->config->reply_timeout;
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
return 0;
 
@@ -129,6 +132,14 @@ static int cell_send_message(struct cell *cell, u32 
message,
if (reply != JAILHOUSE_MSG_NONE)
return -EPERM;
 
+   if (!!(cell->config->reply_timeout) && !timeout) {
+   printk("Timeout expired when waiting reply from target 
cell\n");
+   cell->comm_page.comm_region.cell_state = 
JAILHOUSE_CELL_FAILED;
+   cell_suspend(cell, this_cpu_data());
+   return -ETIMEDOUT;
+   }
+   timeout--;
+
cpu_relax();
}
 }
@@ -519,7 +530,7 @@ static int cell_management_prologue(enum management_task 
task,
}
 
if ((task == CELL_DESTROY && !cell_reconfig_ok(*cell_ptr)) ||
-   !cell_shutdown_ok(*cell_ptr)) {
+   (cell_shutdown_ok(*cell_ptr) == -EPERM)) {
cell_resume(cpu_data);
return -EPERM;
}
diff --git a/hypervisor/include/jailhouse/cell-config.h 
b/hypervisor/include/jailhouse/cell-config.h
index 92c9a4b..fb36f6b 100644
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -77,6 +77,7 @@ struct jailhouse_cell_desc {
__u32 vpci_irq_base;
 
__u64 cpu_reset_address;
+   __u32 reply_timeout;
 } __attribute__((packed));
 
 #define JAILHOUSE_MEM_READ 0x0001
diff --git a/hypervisor/include/jailhouse/entry.h 
b/hypervisor/include/jailhouse/entry.h
index 9357b50..de1a906 100644
--- a/hypervisor/include/jailhouse/entry.h
+++ b/hypervisor/include/jailhouse/entry.h
@@ -29,6 +29,7 @@
 #define EINVAL 22
 #define ERANGE 34
 #define ENOSYS 38
+#define ETIMEDOUT  110
 
 struct per_cpu;
 struct cell;
-- 
2.7.4

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[PATCH v2 2/2] Stop waiting message reply after a certain amount of time

[Claudio Scordino]

Since the hypervisor does not currently have any notion of time (to
check the amount of elapsed time waiting), we just wait a certain amount
of loops. The number of loops is set through the variable
JAILHOUSE_REPLY_TIMEOUT whose default value can be overwritten in
hypervisor/include/jailhouse/config.h. If set to -1 the timeout
mechanism is disabled.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c | 8 +++-
 hypervisor/include/jailhouse/entry.h | 1 +
 hypervisor/include/jailhouse/hypercall.h | 5 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index abfe6cb..ac80b56 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -103,12 +103,13 @@ static void cell_resume(struct per_cpu *cpu_data)
 static int cell_send_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
+   u32 timeout = JAILHOUSE_REPLY_TIMEOUT;
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
return -ECOMM;
 
jailhouse_send_msg_to_cell(>comm_page.comm_region, message);
 
-   while (1) {
+   while (timeout) {
u32 reply = cell->comm_page.comm_region.reply_from_cell;
u32 cell_state = cell->comm_page.comm_region.cell_state;
 
@@ -125,8 +126,13 @@ static int cell_send_message(struct cell *cell, u32 
message,
if (reply != JAILHOUSE_MSG_NONE)
return -EPERM;
 
+#if JAILHOUSE_REPLY_TIMEOUT != -1
+   timeout--;
+#endif
cpu_relax();
}
+   printk("Timeout expired when waiting reply from target cell\n");
+   return -ETIMEDOUT;
 }
 
 static bool cell_reconfig_ok(struct cell *excluded_cell)
diff --git a/hypervisor/include/jailhouse/entry.h 
b/hypervisor/include/jailhouse/entry.h
index 8d61cf1..3d61e84 100644
--- a/hypervisor/include/jailhouse/entry.h
+++ b/hypervisor/include/jailhouse/entry.h
@@ -30,6 +30,7 @@
 #define ERANGE 34
 #define ENOSYS 38
 #defineECOMM   70
+#defineETIMEDOUT   110
 
 struct per_cpu;
 struct cell;
diff --git a/hypervisor/include/jailhouse/hypercall.h 
b/hypervisor/include/jailhouse/hypercall.h
index 08bf73f..2e05ebb 100644
--- a/hypervisor/include/jailhouse/hypercall.h
+++ b/hypervisor/include/jailhouse/hypercall.h
@@ -77,6 +77,11 @@
 #define JAILHOUSE_MSG_SHUTDOWN_REQUEST 1
 #define JAILHOUSE_MSG_RECONFIG_COMPLETED   2
 
+/* Number of cycles after which to stop waiting for cell's reply */
+#ifndef JAILHOUSE_REPLY_TIMEOUT
+#define JAILHOUSE_REPLY_TIMEOUT4
+#endif
+
 /* replies from cell */
 #define JAILHOUSE_MSG_UNKNOWN  1
 #define JAILHOUSE_MSG_REQUEST_DENIED   2
-- 
2.7.4

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[PATCH v2 0/2] Don't let inmates hang the root cell by never replying

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance. We therefore wait a
(configurable) amount of time after which we stop waiting for such reply.

Claudio Scordino (2):
  Make cell_send_message() return errors
  Stop waiting message reply after a certain amount of time

 hypervisor/control.c | 28 +++-
 hypervisor/include/jailhouse/entry.h |  2 ++
 hypervisor/include/jailhouse/hypercall.h |  5 +
 3 files changed, 22 insertions(+), 13 deletions(-)

-- 
2.7.4

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[PATCH v2 1/2] Make cell_send_message() return errors

[Claudio Scordino]

This patch makes cell_send_message() return errors and let the caller to
decide how to handle them.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c | 20 
 hypervisor/include/jailhouse/entry.h |  1 +
 2 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index b1beed9..abfe6cb 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -98,17 +98,13 @@ static void cell_resume(struct per_cpu *cpu_data)
  * @param message  Message code to be sent (JAILHOUSE_MSG_*).
  * @param type Message type, defines the valid replies.
  *
- * @return True if a request message was approved or reception of an
- *informational message was acknowledged by the target cell. It also
- *returns true if the target cell does not support an active
- *communication region, is shut down or in failed state. Returns
- *false on request denial or invalid replies.
+ * @return 0 on success, negative error code otherwise.
  */
-static bool cell_send_message(struct cell *cell, u32 message,
+static int cell_send_message(struct cell *cell, u32 message,
  enum msg_type type)
 {
if (cell->config->flags & JAILHOUSE_CELL_PASSIVE_COMMREG)
-   return true;
+   return -ECOMM;
 
jailhouse_send_msg_to_cell(>comm_page.comm_region, message);
 
@@ -118,16 +114,16 @@ static bool cell_send_message(struct cell *cell, u32 
message,
 
if (cell_state == JAILHOUSE_CELL_SHUT_DOWN ||
cell_state == JAILHOUSE_CELL_FAILED)
-   return true;
+   return -ECOMM;
 
if ((type == MSG_REQUEST &&
 reply == JAILHOUSE_MSG_REQUEST_APPROVED) ||
(type == MSG_INFORMATION &&
 reply == JAILHOUSE_MSG_RECEIVED))
-   return true;
+   return 0;
 
if (reply != JAILHOUSE_MSG_NONE)
-   return false;
+   return -EPERM;
 
cpu_relax();
}
@@ -489,8 +485,8 @@ err_resume:
 
 static bool cell_shutdown_ok(struct cell *cell)
 {
-   return cell_send_message(cell, JAILHOUSE_MSG_SHUTDOWN_REQUEST,
-MSG_REQUEST);
+   return (cell_send_message(cell, JAILHOUSE_MSG_SHUTDOWN_REQUEST,
+MSG_REQUEST) != -EPERM);
 }
 
 static int cell_management_prologue(enum management_task task,
diff --git a/hypervisor/include/jailhouse/entry.h 
b/hypervisor/include/jailhouse/entry.h
index 9357b50..8d61cf1 100644
--- a/hypervisor/include/jailhouse/entry.h
+++ b/hypervisor/include/jailhouse/entry.h
@@ -29,6 +29,7 @@
 #define EINVAL 22
 #define ERANGE 34
 #define ENOSYS 38
+#defineECOMM   70
 
 struct per_cpu;
 struct cell;
-- 
2.7.4

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[RFC][PATCH] Stop waiting message reply after a certain amount of time

[Claudio Scordino]

A buggy/misbehaving inmate can hang the root cell by never replying to a
request. That's not good for fault tolerance.
Since the hypervisor does not currently have any notion of time (to
check the amount of elapsed time waiting), we can just wait a certain
amount of loops after which we stop waiting such reply. The number of
cycles is equivalent to a few seconds on a fast machine.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c | 17 +++--
 hypervisor/include/jailhouse/hypercall.h |  3 +++
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index b1beed9..19aefae 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -98,11 +98,13 @@ static void cell_resume(struct per_cpu *cpu_data)
  * @param message  Message code to be sent (JAILHOUSE_MSG_*).
  * @param type Message type, defines the valid replies.
  *
- * @return True if a request message was approved or reception of an
- *informational message was acknowledged by the target cell. It also
- *returns true if the target cell does not support an active
- *communication region, is shut down or in failed state. Returns
- *false on request denial or invalid replies.
+ * @return True if one of the following cases occurs:
+ * - a request message was approved by the target cell
+ * - reception of an informational message was acknowledged by the 
target cell
+ * - the target cell doesn't support an active communication region
+ * - the target cell is shut down or in failed state
+ * - the target cell didn't reply in time
+ *Returns false on request denial or invalid replies.
  */
 static bool cell_send_message(struct cell *cell, u32 message,
  enum msg_type type)
@@ -112,7 +114,8 @@ static bool cell_send_message(struct cell *cell, u32 
message,
 
jailhouse_send_msg_to_cell(>comm_page.comm_region, message);
 
-   while (1) {
+   for(unsigned long long int cycles = 0 ;
+   cycles < JAILHOUSE_MSG_REPLY_TIMEOUT; ++cycles) {
u32 reply = cell->comm_page.comm_region.reply_from_cell;
u32 cell_state = cell->comm_page.comm_region.cell_state;
 
@@ -131,6 +134,8 @@ static bool cell_send_message(struct cell *cell, u32 
message,
 
cpu_relax();
}
+
+   return true;
 }
 
 static bool cell_reconfig_ok(struct cell *excluded_cell)
diff --git a/hypervisor/include/jailhouse/hypercall.h 
b/hypervisor/include/jailhouse/hypercall.h
index 08bf73f..ad390c8 100644
--- a/hypervisor/include/jailhouse/hypercall.h
+++ b/hypervisor/include/jailhouse/hypercall.h
@@ -77,6 +77,9 @@
 #define JAILHOUSE_MSG_SHUTDOWN_REQUEST 1
 #define JAILHOUSE_MSG_RECONFIG_COMPLETED   2
 
+/* Number of cycles after which to stop waiting for cell's reply */
+#define JAILHOUSE_MSG_REPLY_TIMEOUT4
+
 /* replies from cell */
 #define JAILHOUSE_MSG_UNKNOWN  1
 #define JAILHOUSE_MSG_REQUEST_DENIED   2
-- 
2.7.4

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Re: Create output with debug symbols, elf

[Claudio Scordino]

Dear Florian,

I use the following settings when using Lauterbach on the TX1 (otherwise
the watchdog reboots the machine after blocking):

echo 0 > /sys/devices/system/cpu/cpuquiet/tegra_cpuquiet/enable
echo 1 > /sys/kernel/debug/cpuidle_t210/fast_cluster_states_enable
echo 1 > /sys/kernel/debug/cpuidle_t210/slow_cluster_states_enable
echo 1 > /sys/kernel/debug/clock/csite/state
echo 0 > /proc/sys/kernel/nmi_watchdog
echo 0 > /proc/sys/kernel/watchdog_thresh
echo 0 > /proc/sys/kernel/watchdog

Hope it helps.

Best regards,

 Claudio

2017-08-24 15:24 GMT+02:00 'florian' via Jailhouse <
jailhouse-dev@googlegroups.com>:

> Am Donnerstag, 24. August 2017 15:20:15 UTC+2 schrieb Ralf Ramsauer:
> > On 08/24/2017 03:16 PM, 'florian' via Jailhouse wrote:
> > > Am Donnerstag, 24. August 2017 15:10:05 UTC+2 schrieb Ralf Ramsauer:
> > >> On 08/24/2017 03:03 PM, 'florian' via Jailhouse wrote:
> > >>> Am Donnerstag, 24. August 2017 14:59:55 UTC+2 schrieb Henning Schild:
> > >>>> Am Thu, 24 Aug 2017 05:47:38 -0700
> > >>>> schrieb 'florian' via Jailhouse <jailhouse-dev@googlegroups.com>:
> > >>>>
> > >>>>> I want to debug Jailhouse with a Lauterbach but getting crazy to
> load
> > >>>>> symbols into trace32. Is there any way to get an elf file as an
> > >>>>> output of the compilation process (important part for me: debug
> > >>>>> symbols of jailhouse.bin and of the inmates examples)?
> > >>>>
> > >>>> There are elf files with symbols and locations i.e.
> > >>>> hypervisor/hypervisor-intel.o
> > >>>> and
> > >>>> inmates/demos/x86/*-demo-linked.o
> > >>>>
> > >>>> Not sure whether you can use them for your Lauterbach, but should be
> > >>>> close to what you need.
> > >>>>
> > >>>> Henning
> > >>>
> > >>> Ok, then I'm on the right way. Am I right when thinking when using
> ARM then hypervisor/hypervisor.o should be the right and well linked elf
> file? (starting with .elf^^)
> > >>>
> > >> Right.
> > >>
> > >> Simply follow the compilation process, hypervisor.o is the last linked
> > >> file before the flat binary is objcopied:
> > >>
> > >>   CC  /root/workspace/jailhouse/hypervisor/uart.o
> > >>   CC  /root/workspace/jailhouse/hypervisor/uart-8250.o
> > >>   LD  /root/workspace/jailhouse/hypervisor/hypervisor.o
> > >>   OBJCOPY /root/workspace/jailhouse/hypervisor/jailhouse.bin
> > >>
> > >> Could you keep us up-to-date if Lauterbach debugging works fine or if
> > >> there are some obstacles? I'm interested in that.
> > >>
> > >> Thanks,
> > >>   Ralf
> > >
> > > Yeah of course I will like I promised to you and also Paolo.
> > > But "works fine" will be a little bit to much I think, but debugging
> itself works in this stage (but without loaded symbols).
> > > The only problem at the moment is that the TX1 sometimes do not want
> to start again after breaking with the debugger :/.
> > >
> > So resuming from the breakpoint crashes the whole system? Does this only
> > happen in combination with a hypervisor/jailhouse or is it a
> > platform-related problem?
> >
> >   Ralf
>
> It sometimtes happen if resuming from Jailhouse. But I think is no problem
> of Jailhouse, its feels more to be a problem of the debug interface of the
> TX1. It happens totally undetermenistic after break and continue. It's also
> no watchdog issue. But it also happens if Jailhouse is not running.
>
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56010 S.Giuliano Terme - Pisa - Italy
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Re: Crosscompiling for TX1 - Cannot start jailhouse

[Claudio Scordino]

Hi Florian,

Il 21/giu/2017 17:14, "'florian' via Jailhouse" <
jailhouse-dev@googlegroups.com> ha scritto:
>
> Hi,
> I want to run jailhouse on the TX1 (like I described you Ralf).
> Because we use the TX1 for several other projects I want to cross compile
all the things (also the kernel, so kernel objects are available). I used
the description of https://github.com/evidence/linux-jailhouse-tx1

Note that this tree is meant for the Linux kernel 3.10 shipped by Nvidia.

If you instead have a newer kernel (4.7+) you must use the mainline
Jailhouse tree.

Best regards,

  Claudio

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Re: Reenabling of ARM64

[Claudio Scordino]

Dear Ralf,

2017-06-12 16:44 GMT+02:00 Ralf Ramsauer :
> Hi,
>
> during implementation of hyp-stub compatibility fixes for arm64 I
> experienced that reenabling of Jailhouse fails, if there is only a very
> short period of time between jailhouse disable and jailhouse enable.
>
> Reenabling only works if I wait a few seconds after jailhouse disable,
> otherwise the platforms freezes, no UART output.
>
> I first thought that my patches somehow triggered that behavior, but
> this also happens on mainline jailhouse.
>
> Claudio, did you experience anything similar on your TX1?

No, I didn't. But it could also be that I never tried.

I'm currently out of office. I can try to reproduce on TX1 by the end
of the week.

Best,

  Claudio

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Re: Question about licensing of linked inmates

[Claudio Scordino]

Dear guys,

2017-06-08 20:24 GMT+02:00 Jan Kiszka <jan.kis...@siemens.com>:
>
> On 2017-06-08 19:27, Gustavo Lima Chaves wrote:
> > * Jan Kiszka <jan.kis...@siemens.com> [2017-06-08 19:13:20 +0200]:
> >
> >> On 2017-06-08 18:48, Gustavo Lima Chaves wrote:
> >>>> We are currently evaluating Zephyr on Jailhouse, but that is still in a
> >>>> too early stage to contribute to this discussion or even a decision. How
> >>>> urgent is the topic for you?
> >>>
> >>> How far are you into Zephyr? I have patches doing a preliminar port, so 
> >>> that
> >>> at least UART and LOAPIC timers are working from Zephyr just fine:
> >>>
> >>> """
> >>> Created cell "tiny-demo"
> >>> Page pool usage after cell creation: mem 275/1480, remap 65607/131072
> >>> Cell "tiny-demo" can be loaded
> >>> CPU 3 received SIPI, vector 100
> >>> Started cell "tiny-demo"
> >>> * BOOTING ZEPHYR OS v1.7.99 - BUILD: Jun  8 2017 00:36:18 *
> >>> Hello World!
> >>> Hello World!
> >>> Hello World!
> >>> """
> >>>
> >>
> >> Hoho, good that I dropped this note - great to see this!
> >>
> >> I added Andreas to CC who is just starting off, maybe still a bit wet
> >> from the first bucket of cold Jailhouse water.
> >
> > :)
> >
> >>
> >>> This code lies on my hard disk only, for now, but sure I want to make
> >>> it upstream, if both parties agree on its usefulness (Zephyr and
> >>> Jailhouse). From a licensing POV, I just used a bare minimal excerpt
> >>> from header-32.S, and would indeed be great to have that code more
> >>> permissive, so that I would not have to bother re-writing it myself.
> >>
> >> Individual files would be easier to relicense, header-32.S is only owned
> >> by us e.g.
> >
> > Cool.
> >
> >>
> >>>
> >>> One thing I lost from not using the inmate lib was xAPIC access to the
> >>> LOAPIC, so my preliminar patch does rewrite those accesses to be
> >>> x2APIC (MSR-based).
> >>
> >> x2APIC is the better choice.
> >
> > Yeah, maybe, but the ifdefs on my patch are looking uglish (they might
> > want to keep the xAPIC access for the MCUs, I'm afraid).
>
> Sure, for bare-metal you likely need this (the Quark has no x2APIC, not
> even the big, I bet :).
>
> >
> >>
> >> But back to the topic, and actually there are two: writing applications
> >> on top of a permissive runtime - inmates lib or a permissively licensed
> >> RTOS - and providing reusable material to porting RTOSes over Jailhouse.
> >
> > Sure, the second approach is exactly what we'd have with my patches
> > (and possible right after header-32.S is good WRT licensing).
> >
> >> When doing a relicensing, the motivation and intended usage should be
> >> clearly defined before approaching all the copyright holders. And we
> >> should then also think about how to (re-)structure the code when we want
> >> to support the second case.
> >
> > Yeah. The 1st approach is very valid for me as well, and you got a
> > supporter here too for making its license different than of the rest
> > of the codebase.
> >
>
> OK, let's get serious: Claudio, you offered to go after the copyright
> holders. Could you prepare a reasoning email for the license change and
> a patch to perform it? That could be sent to those folks, collect their
> acks, and I could also use it for starting the process internally to add
> ours.


Pasted below. Let me get your feedback.

Many thanks and best regards,

  Claudio




Subject: Request for relicensing your contribution to Jailhouse


Dear developer,

your name is listed among the authors of the source code within the
inmates/lib/ directory of Jailhouse, and therefore you are among the copyright
holders of a part of such library.

The library is currently licensed under GPL, meaning that it cannot be linked
to proprietary code unless by releasing such code under GPL. This prevents the
usage of the hypervisor in all industrial contexts where the inmate code cannot
be disclosed. For this reason, the jailhouse community is currently discussing
[1] the possibility/opportunity of changing the license of just the inmate
library to one allowing static linking of proprietary code (e.g., GPL+linking
exception [2]). The license of the hypervis

Re: Question about licensing of linked inmates

[Claudio Scordino]

Dear Jan,

thank you for clarifying. Let's see how the topic evolves.

In case, the easiest path could be the addition of the linking exception
clause (https://en.wikipedia.org/wiki/GPL_linking_exception) to the plain
GPL just for the inmate library.

Best regards,

   Claudio

2017-03-21 11:00 GMT+01:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2017-03-21 10:27, Claudio Scordino wrote:
> > Dear all,
> >
> > I apologize if this topic has been already discussed in list.
> >
> > I've noted that the inmate lib is licensed under GPL. Therefore, if I'm
> > not wrong, its license also affects the inmate binaries that get linked
> > to it.
> >
> > If licensing the hypervisor code under GPL is reasonable for a plethora
> > of reasons, I wonder if applying the same license for the inmate library
> > is wise or not, since it may prevent the usage of such library in an
> > industrial context where the inmate code must remain proprietary.
>
> Correct, the inmate library in its current form is not suitable for
> proprietary inmate development. We only licensed interface header of the
> hypervisor under dual GPL/BSD, not the library.
>
> I wouldn't refuse a relicensing proposal if there is a real need and
> someone has the time to drive it (hunt down all copyright holders), but
> I would also like to have a discussion about technical alternatives
> first, i.e. RTOSes that already come with permissive licenses. I
> consider Zephyr as the hottest candidate for this right now (x86
> support, consistent licensing, vivid and growing industrial community).
>
> The library may still play a role in future when we start adding more
> test cases.
>
> Jan
>
> --
> Siemens AG, Corporate Technology, CT RDA ITP SES-DE
> Corporate Competence Center Embedded Linux
>



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Question about licensing of linked inmates

[Claudio Scordino]

Dear all,

I apologize if this topic has been already discussed in list.

I've noted that the inmate lib is licensed under GPL. Therefore, if I'm not
wrong, its license also affects the inmate binaries that get linked to it.

If licensing the hypervisor code under GPL is reasonable for a plethora of
reasons, I wonder if applying the same license for the inmate library is
wise or not, since it may prevent the usage of such library in an
industrial context where the inmate code must remain proprietary.

Best regards,

 Claudio

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Unexpected exception with apic timer as PWM

[Claudio Scordino]

Dear all,

we are facing an unexpected exception when running the apic timer to drive
a GPIO as a software PWM.

The platform is x86. The software runs in a bare-metal cell. The PWM
frequency is 5 KHz.

When the duty cycle is very high or very low (i.e., two subsequent
interrupts get closer) we face the following unexpected exception:

FATAL: Unhandled VM-Exit, reason 2
qualification 0
vectoring info: 0 interrupt info: 0
RIP: 0x000f15d6 RSP: 0x000dff08 FLAGS: 10002
RAX: 0x00044b82f9d8 RBX: 0x000f060f RCX: 0x0838
RDX: 0x0004 RSI: 0x0a36 RDI: 0xe134
CS: 10 BASE: 0x AR-BYTES: a09b EFER.LMA 1
CR0: 0x80010031 CR3: 0x000f3000 CR4: 0x2020
EFER: 0x0500
Parking CPU 3 (Cell: "pwm-demo")
Closing cell "pwm-demo"
Page pool usage after cell destruction: mem 4316/16327, remap 16459/131072
CPU 3 received SIPI, vector 98


Attached the code of the inmate.

Any suggestion about the reason of this behavior ?

Many thanks and best regards,

   Claudio

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Mobile: + 39 393 811 7491
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#include 

#define APIC_TIMER_VECTOR   (32U)

#define KILO (1000U)
#define MEGA (100U)

#define TICKS_TO_NANO(TICKS, REF_FREQ_HZ)   \
  (((TICKS) / KILO)?\
((TICKS) * KILO) / ((REF_FREQ_HZ) / MEGA):  \
((TICKS) * MEGA) / ((REF_FREQ_HZ) / KILO))

/*==
GPIO Drv
 =*/
#define GPIO_PORT_COMMAND   0xA35U
#define GPIO_PORT_DATA  0xA36U

#define GPIO_COMMAND_READ_ALL   0xA2U
#define GPIO_COMMAND_READ_IGNITION  0xF2U
#define GPIO_COMMAND_WRITE_ALL  0xA1U

#define GPIO_PIN_0  0x0U
#define GPIO_PIN_1  0x1U
#define GPIO_PIN_2  0x2U
#define GPIO_PIN_3  0x3U
#define GPIO_PIN_4  0x4U
#define GPIO_PIN_5  0x5U
#define GPIO_PIN_6  0x6U
#define GPIO_PIN_7  0x7U

#define GPIO_PIN_0_MASK 0x1U
#define GPIO_PIN_1_MASK 0x2U
#define GPIO_PIN_2_MASK 0x4U
#define GPIO_PIN_3_MASK 0x8U
#define GPIO_PIN_4_MASK 0x10U
#define GPIO_PIN_5_MASK 0x20U
#define GPIO_PIN_6_MASK 0x40U
#define GPIO_PIN_7_MASK 0x80U

#define GPIO_PIN_INPUT_0GPIO_PIN_0
#define GPIO_PIN_INPUT_1GPIO_PIN_1
#define GPIO_PIN_INPUT_2GPIO_PIN_2
#define GPIO_PIN_INPUT_3GPIO_PIN_3
#define GPIO_PIN_OUTPUT_0   GPIO_PIN_4
#define GPIO_PIN_OUTPUT_1   GPIO_PIN_5
#define GPIO_PIN_OUTPUT_2   GPIO_PIN_6
#define GPIO_PIN_OUTPUT_3   GPIO_PIN_7

#define GPIO_PIN_IGNITION   GPIO_PIN_INPUT_3

#define WATCHDOG_PORT_DATA  0xA16U
#define WATCHDOG_PORT_COMMAND   0xA15U
#define WATCHDOG_PORT_PME   0xA1AU
#define WATCHDOG_VALUE_ENABLE   0x20U
#define WATCHDOG_VALUE_PME_ENABLE   0x40U
#define WATCHDOG_VALUE_DISABLE  0x0U
#define WATCHDOG_TIME_SECONDS   0x0U
#define WATCHDOG_TIME_MINUTES   0x1U

/** Return all I/O flags. */
static inline u8 gpio_get_pins(void) {
outb(GPIO_COMMAND_READ_ALL, GPIO_PORT_COMMAND);
return inb(GPIO_PORT_DATA);
}

/** Write \b all I/O flags. */
static inline void gpio_set_pins(u8 value) {
outb(GPIO_COMMAND_WRITE_ALL, GPIO_PORT_COMMAND);
outb(value, GPIO_PORT_DATA);
}

/**
 * \brief Read pin pin from flags.
 * \param[in] pin The pin \b index, [0-7].
 * \return The bit status, 0 or 1.
 * \note It is recommended to use GPIO_PIN_X or GPIO_PIN_INPUT/OUTPUT_X macros.
 */
static inline u8 gpio_get_pin(u8 pin) {
return (gpio_get_pins() >> pin) & 1;
}

/** Return ignition status, 0 or 1. */
static inline u8 gpio_get_ignition(void) {
outb(GPIO_COMMAND_READ_IGNITION, GPIO_PORT_COMMAND);
return (gpio_get_pins() >> GPIO_PIN_IGNITION) & 1;
}

/**
 * \brief Write the value value to pin pin.
 * \param[in] pin The pin \b index, [0-7].
 * \param[in] value The value of the pin to write, must be 0 or 1.
 * \note It is recommended to use GPIO_PIN_X or GPIO_PIN_INPUT/OUTPUT_X macros.
 */
static inline void gpio_set_pin(u8 pin, u8 value) {
u8 pins = gpio_get_pins();
pins &= ~(1 << pin);
pins |= ((value &a

Re: [PATCH] Set default UART divider for x86

[Claudio Scordino]

Hi Ralf,

to answer your previous questions:

stty -F /dev/ttyS0

reports a baudrate of 9600.

Of course, issuing a

stty -F /dev/(ttyS0 115200

before starting Jailhouse fixes the problem of the garbage on the console.

We're running a Ubuntu 16.04 with kernel 4.4 on a i7.

Apparently, the console gets initialized to 9600 by the kernel or by
the hardware itself.

Best regards,

   Claudio


2017-03-09 10:24 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>:
> On 03/09/2017 12:36 AM, Jan Kiszka wrote:
>> On 2017-03-09 09:30, Ralf Ramsauer wrote:
>>> On 03/08/2017 11:28 PM, Jan Kiszka wrote:
>>>> On 2017-03-09 02:07, Ralf Ramsauer wrote:
>>>>> Hi Claudio,
>>>>>
>>>>> On 03/08/2017 01:37 PM, Claudio Scordino wrote:
>>>>>> Hi Ralf,
>>>>>>
>>>>>> sorry, I didn't recall the discussion on list.
>>>>>>
>>>>>> Using the config currently generated by "jailhouse config create", our
>>>>>> i7 prints junk on the console, unless we manually add such divider.
>>>>>> If this is the intended behavior and we are supposed to add it, then I'm 
>>>>>> fine.
>>>>>> However, I'm afraid that several newbies could flood the list
>>>>>> complaining that their serial "doesn't work" if we don't properly
>>>>>> document such information.
>>>>> Usually we make the assumption that Linux initialises UARTs beforehand.
>>>>
>>>> We do this on ARM, we didn't do this on x86 prior to that commit as
>>>> Claudio pointed out.
>>>>
>>>> ARM is trickier to configure because we tend to have different dividers
>>>> on the different boards. For the x86 standard UARTs, we know the
>>>> divider, though. As long as the right value is applied,
>>>> re-initialization should cause no harm and will cover the case Linux is
>>>> configured to not use the UART at all.
>>> That's the point. As long as the 'right value' is applied. And if the
>>> right value is applied, nothing will happen and we can leave it out :)
>>>
>>> As Claudio received garbage on his serial line, I assume that the serial
>>> port was simply not configured with 115200 baud on Linux side before and
>>> as the UART is typically root-shared with Linux, enforcing 115200 baud
>>> in Jailhouse leads to corrupt settings in Root-Linux. If the divider
>>> would have been 0 (i.e., the device would not have been initialised at
>>> all), then he would not have received anything.
>>>
>>> By default, many distributions spawn a console on the serial line(s)
>>> that are configured with a baudrate different than 115200 (commonly
>>> 38400 or 9600). Better change those settings than overriding them.
>>
>> Hmm, my experience is that x86 distros leave the PC UARTs alone by
>> default, unless you tell them to use one. Which one does that differently?
> I have to admit that my experience is limited to ARM-based derivates,
> and they all tend to have the serial line enabled by default. And I
> guess that this applies to most x86-based dev-boards as well.
>
> Still, if you receive garbage on your serial line, then someone must
> have initialised it, otherwise you wouldn't receive anything. And I
> think it's better to not override a potentially running application that
> might have acquired the resource, as Jailhouse can not be aware of that
> with its limited knowledge.
>
> What happened to me once: On (Gentoo based) ARM-Linux, systemd spawns
> the console right *after* it received the first character and set the
> baudrate back to 38400. Pretty confusing, if this happens after you
> successfully started Jailhouse and saw its output, followed by garbage...
>>
>>>
>>> I understand the divider in the system config as an explicit setting
>>> that should only be used if the serial line is not handled by Linux,
>>> which could be detected by 'jailhouse config create'. And we have
>>> 'jailhouse console' that will work independent of the baudrate.
> BTW: This is exactly how Documentation/debug-output.md puts it:
> [...]
> A zero value means that the hypervisor will skip the initialisation of
> the UART console.  This is the case in most scenarios, as the
> hypervisor's UART console was initialised by Linux before.
> [...]
>>>
>>> I would rather suggest a FAQ and recommend to check the baudrate of the
>>> serial device before starting jailhouse than overriding Linux settings
>>> (by default).
> What abo

Re: [PATCH] Set default UART divider for x86

[Claudio Scordino]

Hi Ralf,

sorry, I didn't recall the discussion on list.

Using the config currently generated by "jailhouse config create", our
i7 prints junk on the console, unless we manually add such divider.
If this is the intended behavior and we are supposed to add it, then I'm fine.
However, I'm afraid that several newbies could flood the list
complaining that their serial "doesn't work" if we don't properly
document such information.

Many thanks and best regards,

   Claudio

2017-03-08 20:03 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>:
> On 03/08/2017 07:55 AM, Jan Kiszka wrote:
>> On 2017-03-08 15:57, Claudio Scordino wrote:
>>> This patch fixes a regression introduced by commit
>>> 2a7c8733b6a3d47fb507eca4de5a33433199424c
>>> which by default does not initialize the UART divider to 0x1
>>> on the x86 platform.
> Isn't this intended behaviour? I remember that we had discussions on
> that on the list, and according to the commit message,
>
> ...
> If the divider is zero, the hypervisor will skip UART initialisation and
> assume that the UART was already initialised by Linux.
> ...
>
> All we do on x86 is to skip those four instructions if the divider is zero:
> uart_reg_out(UART_LCR, UART_LCR_DLAB);
> uart_reg_out(UART_DLL, divider & 0xff);
> uart_reg_out(UART_DLM, (divider >> 8) & 0xff);
> uart_reg_out(UART_LCR, UART_LCR_8N1);
>
> which should in deed be done by Linux before, if this is what we define
> default behaviour.
>>>
>>> Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
>>> Signed-off-by: Michele Pes <m@evidence.eu.com>
>>> ---
>>>  tools/root-cell-config.c.tmpl | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/tools/root-cell-config.c.tmpl b/tools/root-cell-config.c.tmpl
>>> index 11956b7..a971f56 100644
>>> --- a/tools/root-cell-config.c.tmpl
>>> +++ b/tools/root-cell-config.c.tmpl
>>> @@ -62,6 +62,7 @@ struct {
>>>  },
>>>  .debug_console = {
>>>  .address = 0x3f8,
>>> +.divider = 0x1,
> I'd rather insert this as a comment.
>>>  .flags = JAILHOUSE_CON1_TYPE_UART_X86 |
>>>   JAILHOUSE_CON1_FLAG_PIO |
>>>       JAILHOUSE_CON2_TYPE_ROOTPAGE,
>>>
>>
>> We probably want this fixed for the in-tree x86 configs as well, namely
>>
>> configs/f2a88xm-hd3.c
>> configs/imb-a180.c
>> configs/qemu-vm.c
> Just tested qemu, on my VM everything works fine.
>
>   Ralf
>>
>> Ralf, am I right?
>>
>> Jan
>>



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[PATCH] Set default UART divider for x86

[Claudio Scordino]

This patch fixes a regression introduced by commit
2a7c8733b6a3d47fb507eca4de5a33433199424c
which by default does not initialize the UART divider to 0x1
on the x86 platform.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Michele Pes <m@evidence.eu.com>
---
 tools/root-cell-config.c.tmpl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/root-cell-config.c.tmpl b/tools/root-cell-config.c.tmpl
index 11956b7..a971f56 100644
--- a/tools/root-cell-config.c.tmpl
+++ b/tools/root-cell-config.c.tmpl
@@ -62,6 +62,7 @@ struct {
},
.debug_console = {
.address = 0x3f8,
+   .divider = 0x1,
.flags = JAILHOUSE_CON1_TYPE_UART_X86 |
 JAILHOUSE_CON1_FLAG_PIO |
 JAILHOUSE_CON2_TYPE_ROOTPAGE,
-- 
2.7.4

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Re: [PATCH 2/2] Split jetson-demo config between TK1 and TX1

[Claudio Scordino]

Dear Ralf,

2017-02-28 22:27 GMT+01:00 Ralf Ramsauer :

> > > + /* RAM */ {
> > > + .phys_start = 0x17bfe,
> > shouldn't this rather be 0x17bff in order to not introduce memory
> > holes? The HV start at 0x17c00, and we don't have an shmem region
> > before the hypervisor's region.
> >
> >
> > Right.
> > The actual reason is that we are using such "hole" for an additional
> > region for sharing data between Linux and the RTOS,
> > and we didn't put such region into the config because we thought that it
> > was too specific.
> Ah, ok, I see, I was just wondering.
> > At the same time we thought that a memory hole could ease the debugging.
> Hmm, all other inmates are typically physically located right before the
> hypervisor, without holes (except the ones that have an IVSHMEM region).
>
> Can't we just place the inmate close to the hypervisor, and you place
> you shared memory region before the inmate? This approach should work
> for mainline as well as for your downstream branch.
>

Of course. I will send a new patchset in the next days.

Best regards,

  Claudio

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Re: [PATCH 2/2] Split jetson-demo config between TK1 and TX1

[Claudio Scordino]

Hi Ralf,

2017-02-28 6:19 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>:

> Hi Claudio,
>
> On 02/27/2017 02:52 AM, Claudio Scordino wrote:
> > This patch splits the jetson-demo config into two different config files
> > because TK1 and TX1 put the inmate at different addresses.
> >
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > Signed-off-by: Errico Guidieri <e.guidi...@evidence.eu.com>
> > ---
> >  configs/{jetson-demo.c => jetson-tk1-demo.c} |  2 +-
> >  configs/jetson-tx1-demo.c| 56
> 
> >  2 files changed, 57 insertions(+), 1 deletion(-)
> >  rename configs/{jetson-demo.c => jetson-tk1-demo.c} (94%)
> >  create mode 100644 configs/jetson-tx1-demo.c
> >
> > diff --git a/configs/jetson-demo.c b/configs/jetson-tk1-demo.c
> > similarity index 94%
> > rename from configs/jetson-demo.c
> > rename to configs/jetson-tk1-demo.c
> > index 35d92ea..378ed08 100644
> > --- a/configs/jetson-demo.c
> > +++ b/configs/jetson-tk1-demo.c
> > @@ -1,7 +1,7 @@
> >  /*
> >   * Jailhouse, a Linux-based partitioning hypervisor
> >   *
> > - * Configuration for gic-demo or uart-demo inmate on Jetson TK1 and TX1:
> > + * Configuration for gic-demo or uart-demo inmate on Jetson TK1:
> >   * 1 CPU, 64K RAM, serial port 0
> >   *
> >   * Copyright (c) Siemens AG, 2015
> > diff --git a/configs/jetson-tx1-demo.c b/configs/jetson-tx1-demo.c
> > new file mode 100644
> > index 000..0c46b64
> > --- /dev/null
> > +++ b/configs/jetson-tx1-demo.c
> > @@ -0,0 +1,56 @@
> > +/*
> > + * Jailhouse, a Linux-based partitioning hypervisor
> > + *
> > + * Configuration for gic-demo or uart-demo inmate on Jetson TX1:
> > + * 1 CPU, 64K RAM, serial port 0
> > + *
> > + * Copyright (c) Siemens AG, 2015
> > + *
> > + * Authors:
> > + *  Jan Kiszka <jan.kis...@siemens.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.  See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> > +
> > +struct {
> > + struct jailhouse_cell_desc cell;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[2];
> > +} __attribute__((packed)) config = {
> > + .cell = {
> > + .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .name = "jetson-demo",
> This should become jetson-tx1-demo again. (same for the TK1)
> > + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
> > +
> > + .cpu_set_size = sizeof(config.cpus),
> > + .num_memory_regions = ARRAY_SIZE(config.mem_regions),
> > + },
> > +
> > + .cpus = {
> > + 0x8,
> > + },
> > +
> > + .mem_regions = {
> > + /* UART */ {
> > + .phys_start = 0x70006000,
> > + .virt_start = 0x70006000,
> > + .size = 0x1000,
> > + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> > + JAILHOUSE_MEM_IO,
> > + },
> > + /* RAM */ {
> > + .phys_start = 0x17bfe,
> shouldn't this rather be 0x17bff in order to not introduce memory
> holes? The HV start at 0x17c00, and we don't have an shmem region
> before the hypervisor's region.
>

Right.
The actual reason is that we are using such "hole" for an additional region
for sharing data between Linux and the RTOS,
and we didn't put such region into the config because we thought that it
was too specific.
At the same time we thought that a memory hole could ease the debugging.

We can enlarge such area if you wish. Let me know.

Best regards,

  Claudio

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Re: [PATCH 1/2] New cell config file for TX1

[Claudio Scordino]

Hi,

2017-02-28 10:07 GMT+01:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2017-02-27 10:52, Claudio Scordino wrote:
> > This patch updates the config file for the Nvidia TX1 board.
> > Besides enlarging the amount of memory for the root cell, the patch
> > fixes an issue with pulseaudio on X11 and error messages printed by
> > the memory controller driver on the stock Nvidia 3.10 kernel.
> > Tested on both the Nvidia 3.10 and the Vanilla 4.9 kernels.
> >
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > Signed-off-by: Errico Guidieri <e.guidi...@evidence.eu.com>
> > ---
> >  configs/jetson-tx1.c | 318 ++
> -
> >  1 file changed, 113 insertions(+), 205 deletions(-)
> >
> > diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
> > index f47ebfd..5c97a48 100644
> > --- a/configs/jetson-tx1.c
> > +++ b/configs/jetson-tx1.c
>
> ...
>
> > @@ -231,14 +182,14 @@ struct {
> >   /* UARTs */ {
> >   .phys_start = 0x70006000,
> >   .virt_start = 0x70006000,
> > - .size = 0x600,
> > + .size = 0x1000,
> >   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> >   JAILHOUSE_MEM_IO,
> >   },
> >   /* PWM Controller */ {
> >   .phys_start = 0x7000a000,
> >   .virt_start = 0x7000a000,
> > - .size = 0x100,
> > + .size = 0x1000,
>
> Are these size changes a necessity or an optimization? Just to clarify
> the context.
>

Actually, I encountered several different issues with the previous config:
access to undocumented memory addresses, undocumented error messages by the
Nividia's MC driver, pulseaudio at 100% when logging into X11, etc.

This new version of the config doesn't print any error message on the
Jailhouse console nor in the dmesg, and it has been tested on both the 3.10
(even running X11) and the 4.09 with the standard smoke test (gic-demo).
But, honestly, I can't recall the reason for each change made when trying
to fix all the issues above.

Best regards,

 Claudio

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[PATCH 0/2] Update cell config file for Nvidia TX1

[Claudio Scordino]

This patchset updates the root config file for the Nvidia TX1 board and splits
the existing jetson-demo config file into two different configs for TK1 and
TX1, respectively.

Claudio Scordino (2):
  Update config file for TX1
  Split jetson-demo config between TK1 and TX1

 configs/{jetson-demo.c => jetson-tk1-demo.c} |   2 +-
 configs/jetson-tx1-demo.c|  56 +
 configs/jetson-tx1.c | 318 ++-
 3 files changed, 170 insertions(+), 206 deletions(-)
 rename configs/{jetson-demo.c => jetson-tk1-demo.c} (94%)
 create mode 100644 configs/jetson-tx1-demo.c

-- 
2.7.4

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[PATCH 1/2] New cell config file for TX1

[Claudio Scordino]

This patch updates the config file for the Nvidia TX1 board.
Besides enlarging the amount of memory for the root cell, the patch
fixes an issue with pulseaudio on X11 and error messages printed by
the memory controller driver on the stock Nvidia 3.10 kernel.
Tested on both the Nvidia 3.10 and the Vanilla 4.9 kernels.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Errico Guidieri <e.guidi...@evidence.eu.com>
---
 configs/jetson-tx1.c | 318 ++-
 1 file changed, 113 insertions(+), 205 deletions(-)

diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
index f47ebfd..5c97a48 100644
--- a/configs/jetson-tx1.c
+++ b/configs/jetson-tx1.c
@@ -10,7 +10,7 @@
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
  *
- * NOTE: Add "mem=1920M vmalloc=512M" to the kernel command line.
+ * NOTE: Add "mem=3968M vmalloc=512M" to the kernel command line.
  */
 
 #include 
@@ -21,14 +21,14 @@
 struct {
struct jailhouse_system header;
__u64 cpus[1];
-   struct jailhouse_memory mem_regions[55];
+   struct jailhouse_memory mem_regions[42];
struct jailhouse_irqchip irqchips[2];
 } __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.hypervisor_memory = {
-   .phys_start = 0xfc00,
+   .phys_start = 0x17c00,
.size = 0x400,
},
.debug_console = {
@@ -60,6 +60,13 @@ struct {
 
.mem_regions = {
 
+   /* APE 1 */ {
+   .phys_start = 0x,
+   .virt_start = 0x,
+   .size = 0x00D0,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
/* PCIE */ {
.phys_start = 0x0100,
.virt_start = 0x0100,
@@ -81,87 +88,10 @@ struct {
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
-   /* host1x/vi */ {
-   .phys_start = 0x5408,
-   .virt_start = 0x5408,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* TSEC2 */ {
-   .phys_start = 0x5410,
-   .virt_start = 0x5410,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* Display 2 */ {
-   .phys_start = 0x5424,
-   .virt_start = 0x5424,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* VIC */ {
-   .phys_start = 0x5434,
-   .virt_start = 0x5434,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* NVJPG */ {
-   .phys_start = 0x5438,
-   .virt_start = 0x5438,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* NVDEC */ {
-   .phys_start = 0x5448,
-   .virt_start = 0x5448,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* NVENC */ {
-   .phys_start = 0x544c,
-   .virt_start = 0x544c,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* TSEC */ {
-   .phys_start = 0x5450,
-   .virt_start = 0x5450,
-   .size = 0x4,
-   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
-   JAILHOUSE_MEM_IO,
-   },
-   /* SOR1 */ {
-   .phys_start = 0x5458,
-   

[PATCH 2/2] Split jetson-demo config between TK1 and TX1

[Claudio Scordino]

This patch splits the jetson-demo config into two different config files
because TK1 and TX1 put the inmate at different addresses.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Errico Guidieri <e.guidi...@evidence.eu.com>
---
 configs/{jetson-demo.c => jetson-tk1-demo.c} |  2 +-
 configs/jetson-tx1-demo.c| 56 
 2 files changed, 57 insertions(+), 1 deletion(-)
 rename configs/{jetson-demo.c => jetson-tk1-demo.c} (94%)
 create mode 100644 configs/jetson-tx1-demo.c

diff --git a/configs/jetson-demo.c b/configs/jetson-tk1-demo.c
similarity index 94%
rename from configs/jetson-demo.c
rename to configs/jetson-tk1-demo.c
index 35d92ea..378ed08 100644
--- a/configs/jetson-demo.c
+++ b/configs/jetson-tk1-demo.c
@@ -1,7 +1,7 @@
 /*
  * Jailhouse, a Linux-based partitioning hypervisor
  *
- * Configuration for gic-demo or uart-demo inmate on Jetson TK1 and TX1:
+ * Configuration for gic-demo or uart-demo inmate on Jetson TK1:
  * 1 CPU, 64K RAM, serial port 0
  *
  * Copyright (c) Siemens AG, 2015
diff --git a/configs/jetson-tx1-demo.c b/configs/jetson-tx1-demo.c
new file mode 100644
index 000..0c46b64
--- /dev/null
+++ b/configs/jetson-tx1-demo.c
@@ -0,0 +1,56 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for gic-demo or uart-demo inmate on Jetson TX1:
+ * 1 CPU, 64K RAM, serial port 0
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .revision = JAILHOUSE_CONFIG_REVISION,
+   .name = "jetson-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   },
+
+   .cpus = {
+   0x8,
+   },
+
+   .mem_regions = {
+   /* UART */ {
+   .phys_start = 0x70006000,
+   .virt_start = 0x70006000,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* RAM */ {
+   .phys_start = 0x17bfe,
+   .virt_start = 0,
+   .size = 0x0001,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   },
+};
-- 
2.7.4

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Re: [PATCH 4/6] configs: add config files for Jetson TX1

[Claudio Scordino]

Hi Ralf,

we are currently using one single jetson-demo.c for both the TK1 and the
TX1.

In principle, this seemed a good idea to reduce the amount of config files.

However, if I enlarge the amount of memory of the root cell for the TX1,
then the inmate for the two boards need to be put at different addresses.

Should I split the demo config once again ?

Many thanks and best regards,

 Claudio


2017-02-24 13:36 GMT+01:00 Claudio Scordino <clau...@evidence.eu.com>:

> Hi Ralf,
>
> probably it was just pasted from another board, but it's worth fixing it.
>
> However, since we have a few other pending fixes for this config, we'll
> send a patch next week fixing all at once.
>
> Many thanks and best regards,
>
>  Claudio
>
>
> 2017-02-23 21:37 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
> :
>
>> On 12/07/2016 01:43 PM, Ralf Ramsauer wrote:
>> > From: Claudio Scordino <clau...@evidence.eu.com>
>> >
>> > This patch adds the config file for Jetson TX1.
>> >
>> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
>> > Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
>> > [ralf: remove trailing newline in jetson-tx1.c, amend commit message,
>> >align debug_console, add config file revision]
>> > Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
>> > ---
>> >  configs/jetson-tx1.c | 465 ++
>> +
>> >  1 file changed, 465 insertions(+)
>> >  create mode 100644 configs/jetson-tx1.c
>> >
>> > diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
>> > new file mode 100644
>> > index 00..cf80aa4786
>> > --- /dev/null
>> > +++ b/configs/jetson-tx1.c
>> > @@ -0,0 +1,465 @@
>> > +/*
>> > + * Jailhouse Jetson TX1 support
>> > + *
>> > + * Copyright (C) 2016 Evidence Srl
>> > + *
>> > + * Authors:
>> > + *  Claudio Scordino <clau...@evidence.eu.com>
>> > + *  Bruno Morelli <b.more...@evidence.eu.com>
>> > + *
>> > + * This work is licensed under the terms of the GNU GPL, version 2.
>> See
>> > + * the COPYING file in the top-level directory.
>> > + *
>> > + * NOTE: Add "mem=1920M vmalloc=512M" to the kernel command line.
>> > + */
>> > +
>> > +#include 
>> > +#include 
>> > +
>> > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
>> > +
>> > +struct {
>> > + struct jailhouse_system header;
>> > + __u64 cpus[1];
>> > + struct jailhouse_memory mem_regions[55];
>> > + struct jailhouse_irqchip irqchips[2];
>> > +} __attribute__((packed)) config = {
>> > + .header = {
>> > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
>> > + .revision = JAILHOUSE_CONFIG_REVISION,
>> > + .hypervisor_memory = {
>> > + .phys_start = 0xfc00,
>> > + .size = 0x400,
>> > +         },
>>
>> Hi Claudio and Bruno,
>>
>> TX1 comes with 4GiB of memory, that reaches from 0x8000 to
>> 0x17fff, right?
>>
>> Is there any reason why you plcae the hypervisor at 0xFC00, in the
>> middle of the physical memory?
>>
>>   Ralf
>>
>
>
>
> --
> Claudio Scordino, Ph.D.
> Project Manager - Funded research projects
>
> Evidence Srl
> Via Carducci 56
> 56010 S.Giuliano Terme - Pisa - Italy
> Phone:  +39 050 99 11 224
> Mobile: + 39 393 811 7491
> Fax:   +39 050 99 10 812
> http://www.evidence.eu.com
>
> *VISIT US AT EMBEDDED WORLD 2017 --- Hall 4 Stand 545*
>
>


-- 
Claudio Scordino, Ph.D.
Project Manager - Funded research projects

Evidence Srl
Via Carducci 56
56010 S.Giuliano Terme - Pisa - Italy
Phone:  +39 050 99 11 224
Mobile: + 39 393 811 7491
Fax:   +39 050 99 10 812
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*VISIT US AT EMBEDDED WORLD 2017 --- Hall 4 Stand 545*

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Re: [PATCH 4/6] configs: add config files for Jetson TX1

[Claudio Scordino]

Hi Ralf,

probably it was just pasted from another board, but it's worth fixing it.

However, since we have a few other pending fixes for this config, we'll
send a patch next week fixing all at once.

Many thanks and best regards,

 Claudio


2017-02-23 21:37 GMT+01:00 Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>:

> On 12/07/2016 01:43 PM, Ralf Ramsauer wrote:
> > From: Claudio Scordino <clau...@evidence.eu.com>
> >
> > This patch adds the config file for Jetson TX1.
> >
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
> > [ralf: remove trailing newline in jetson-tx1.c, amend commit message,
> >align debug_console, add config file revision]
> > Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
> > ---
> >  configs/jetson-tx1.c | 465 ++
> +
> >  1 file changed, 465 insertions(+)
> >  create mode 100644 configs/jetson-tx1.c
> >
> > diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
> > new file mode 100644
> > index 00..cf80aa4786
> > --- /dev/null
> > +++ b/configs/jetson-tx1.c
> > @@ -0,0 +1,465 @@
> > +/*
> > + * Jailhouse Jetson TX1 support
> > + *
> > + * Copyright (C) 2016 Evidence Srl
> > + *
> > + * Authors:
> > + *  Claudio Scordino <clau...@evidence.eu.com>
> > + *  Bruno Morelli <b.more...@evidence.eu.com>
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2.  See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * NOTE: Add "mem=1920M vmalloc=512M" to the kernel command line.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
> > +
> > +struct {
> > + struct jailhouse_system header;
> > + __u64 cpus[1];
> > + struct jailhouse_memory mem_regions[55];
> > + struct jailhouse_irqchip irqchips[2];
> > +} __attribute__((packed)) config = {
> > + .header = {
> > + .signature = JAILHOUSE_SYSTEM_SIGNATURE,
> > + .revision = JAILHOUSE_CONFIG_REVISION,
> > + .hypervisor_memory = {
> > + .phys_start = 0xfc00,
> > + .size = 0x400,
> > + },
>
> Hi Claudio and Bruno,
>
> TX1 comes with 4GiB of memory, that reaches from 0x8000 to
> 0x17fff, right?
>
> Is there any reason why you plcae the hypervisor at 0xFC00, in the
> middle of the physical memory?
>
>   Ralf
>



-- 
Claudio Scordino, Ph.D.
Project Manager - Funded research projects

Evidence Srl
Via Carducci 56
56010 S.Giuliano Terme - Pisa - Italy
Phone:  +39 050 99 11 224
Mobile: + 39 393 811 7491
Fax:   +39 050 99 10 812
http://www.evidence.eu.com

*VISIT US AT EMBEDDED WORLD 2017 --- Hall 4 Stand 545*

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Error messages using 3.10 on TX1

[Claudio Scordino]

Dear all,

after a while using Jailhouse on 4.09 on TX1, I came back to the stock
Nvidia kernel since (as far as I've understood) X is not yet fully
supported when using the free GPU driver, and I'd like to setup a
demonstrator with graphics over Jailhouse.

When enabling Jailhouse on the 3.10 kernel I've got these errors on dmesg.
Jailhouse didn't print any error message on the serial console.
The system seems fully functional most of the times, even using X (the
system crashed only once)

I've progressively increased the address spaces for the root cell in the
hope of resolving the possible conflict, but without success (the root cell
now has access to almost the whole address space).

Can you help me in figuring out what this problem could be related to ?

Many thanks and best regards,

 Claudio


[   68.271660] mc-err: (255) csw_mpcorew: GSC access violation
[   68.271672] mc-err:   status = 0x75010039; addr = 0xff30
[   68.271681] mc-err:   secure: no, access-type: write, SMMU fault: none
[   68.271726] mc-err: (255) csr_mpcorer: GSC access violation
[   68.271732] mc-err:   status = 0x75046027; addr = 0xff321f80
[   68.271738] mc-err:   secure: no, access-type: read, SMMU fault: none
[   68.271778] mc-err: (255) csr_mpcorer: GSC access violation
[   68.271784] mc-err:   status = 0x75005027; addr = 0xff339b40
[   68.271789] mc-err:   secure: no, access-type: read, SMMU fault: none
[   68.271829] mc-err: (255) csr_mpcorer: GSC access violation
[   68.271834] mc-err:   status = 0x75046027; addr = 0xff350f80
[   68.271839] mc-err:   secure: no, access-type: read, SMMU fault: none
[   68.271878] mc-err: Too many MC errors; throttling prints
[   68.273213] [ cut here ]
[   68.273224] WARNING: at drivers/platform/tegra/mc/mcerr.c:262
tegra_mc_error_thread+0xa0/0x474()
[   68.273227] Unknown error! intr sig: 0x00020100
[   68.273230] Modules linked in: jailhouse(O) bnep bcmdhd cfg80211
bluedroid_pm
[   68.273244] CPU: 1 PID: 34 Comm: irq/109-mc_stat Tainted: G   O
3.10.96cloud #11
[   68.273248] Call trace:
[   68.273255] [] dump_backtrace+0x0/0xf4
[   68.273259] [] show_stack+0x14/0x1c
[   68.273265] [] dump_stack+0x20/0x28
[   68.273270] [] warn_slowpath_common+0x78/0x9c
[   68.273274] [] warn_slowpath_fmt+0x50/0x58
[   68.273279] [] tegra_mc_error_thread+0xa0/0x474
[   68.273285] [] irq_thread_fn+0x28/0x4c
[   68.273289] [] irq_thread+0x80/0xdc
[   68.273294] [] kthread+0xc0/0xc8
[   68.273297] ---[ end trace 69316f5a53a3a15c ]---
[   68.273426] [ cut here ]
[   68.273431] WARNING: at drivers/platform/tegra/mc/mcerr.c:262
tegra_mc_error_thread+0xa0/0x474()
[   68.273434] Unknown error! intr sig: 0x00020100
[   68.273437] Modules linked in: jailhouse(O) bnep bcmdhd cfg80211
bluedroid_pm
[   68.273448] CPU: 1 PID: 34 Comm: irq/109-mc_stat Tainted: GW  O
3.10.96cloud #11
[   68.273450] Call trace:
[   68.273454] [] dump_backtrace+0x0/0xf4
[   68.273458] [] show_stack+0x14/0x1c
[   68.273461] [] dump_stack+0x20/0x28
[   68.273466] [] warn_slowpath_common+0x78/0x9c
[   68.273470] [] warn_slowpath_fmt+0x50/0x58
[   68.273474] [] tegra_mc_error_thread+0xa0/0x474
[   68.273478] [] irq_thread_fn+0x28/0x4c
[   68.273482] [] irq_thread+0x80/0xdc
[   68.273486] [] kthread+0xc0/0xc8
[   68.273489] ---[ end trace 69316f5a53a3a15d ]---
[   68.273617] [ cut here ]
[   68.273622] WARNING: at drivers/platform/tegra/mc/mcerr.c:262
tegra_mc_error_thread+0xa0/0x474()
[   68.273625] Unknown error! intr sig: 0x00020100
[   68.273627] Modules linked in: jailhouse(O) bnep bcmdhd cfg80211
bluedroid_pm
[   68.273638] CPU: 1 PID: 34 Comm: irq/109-mc_stat Tainted: GW  O
3.10.96cloud #11
[   68.273641] Call trace:
[   68.273645] [] dump_backtrace+0x0/0xf4
[   68.273648] [] show_stack+0x14/0x1c
[   68.273652] [] dump_stack+0x20/0x28
[   68.273656] [] warn_slowpath_common+0x78/0x9c
[   68.273660] [] warn_slowpath_fmt+0x50/0x58
[   68.273664] [] tegra_mc_error_thread+0xa0/0x474
[   68.273668] [] irq_thread_fn+0x28/0x4c
[   68.273672] [] irq_thread+0x80/0xdc
[   68.273676] [] kthread+0xc0/0xc8
[   68.273679] ---[ end trace 69316f5a53a3a15e ]---
[   68.273741] [ cut here ]

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Re: CPU gets hot on ARM64 when jailhouse is enabled

[Claudio Scordino]

I didn't notice such behavior on my TX1 with the stock 3.10 kernel.
What have you used to measure the temperature ? proc entry ? dmesg ?

 Claudio

2016-11-23 13:52 GMT+01:00 Ralf Ramsauer <r...@ramses-pyramidenbau.de>:

> Hi,
>
> I first noticed that on the LeMaker Hikey: After jailhouse is
> (successfully) enabled, the CPU board gets incredibly hot (after a few
> seconds), though the root Linux still idles and no cells are created so
> far. When jailhouse is disabled again, it immediately cools down within
> seconds.
>
> Same applies to the TX1. The difference is that the TX1 comes with a
> huge heatsink, so it takes a few more minutes but still it gets somewhat
> 'warmer' than usual.
>
> Is this the expected behavior?
>
>   Ralf
>
> --
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-- 
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Project Manager - Funded research projects

Evidence Srl
Via Carducci 56
56010 S.Giuliano Terme - Pisa - Italy
Phone:  +39 050 99 11 224
Mobile: + 39 393 811 7491
Fax:   +39 050 99 10 812
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Re: [PATCH v3 0/6] Initial support for NVIDIA Jetson TX1

[Claudio Scordino]

Thank you. I've tested your branch succesfully too

The only difference I've noticed with respect to master is that I have to
explicitly specify ARCH=arm64 otherwise it looks for inmates/tools/aarch64/
This wasn't previously required, so it is probably related to some recent
change in next.

Have you tested it on TK1 as well ?

Best,
Claudio



2016-11-23 11:57 GMT+01:00 Ralf Ramsauer <r...@ramses-pyramidenbau.de>:

> Hi Claudio,
>
> rebased with minor modifications and successfully tested your patches.
> You can find them here:
> https://github.com/lfd/jailhouse/commits/tx1
>
>   Ralf
>
> On 11/23/2016 09:49 AM, Claudio Scordino wrote:
> > This patchset adds the support for NVIDIA Jetson TX1, by moving the
> uart-tegra
> > driver to arm-common/ and adding the config file for the TX1.
> >
> > Since the changes affect the uart-tegra driver, some testing on TK1 is
> needed
> > as well.
> >
> > Claudio Scordino (4):
> >   inmates: add support for Tegra TX1
> >   Config files for Jetson TX1
> >   Renaming jetson-tk1-demo.c as jetson-demo.c
> >   README: add Nvidia TX1 among the supported boards
> >
> > Ralf Ramsauer (2):
> >   uart-tegra: remove hardcoded offset
> >   uart-tegra: move driver to arm-common
> >
> >  README.md  |   2 +
> >  configs/{jetson-tk1-demo.c => jetson-demo.c}   |   4 +-
> >  configs/jetson-tk1.c   |   4 +-
> >  configs/jetson-tx1.c   | 464
> +
> >  hypervisor/arch/arm-common/Kbuild  |   1 +
> >  .../{arm => arm-common}/include/asm/uart-tegra.h   |   1 -
> >  hypervisor/arch/{arm => arm-common}/uart-tegra.c   |   0
> >  hypervisor/arch/arm/Kbuild |   2 +-
> >  hypervisor/arch/arm64/Kbuild   |   1 +
> >  inmates/lib/arm/include/mach-tegra124/mach/uart.h  |   2 +-
> >  inmates/lib/arm64/Makefile |   1 +
> >  inmates/lib/arm64/Makefile.lib |   1 +
> >  .../lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h |  14 +
> >  .../lib/arm64/include/mach-tegra-tx1/mach/timer.h  |  13 +
> >  .../lib/arm64/include/mach-tegra-tx1/mach/uart.h   |  13 +
> >  15 files changed, 516 insertions(+), 7 deletions(-)
> >  rename configs/{jetson-tk1-demo.c => jetson-demo.c} (92%)
> >  create mode 100644 configs/jetson-tx1.c
> >  rename hypervisor/arch/{arm => arm-common}/include/asm/uart-tegra.h
> (96%)
> >  rename hypervisor/arch/{arm => arm-common}/uart-tegra.c (100%)
> >  create mode 100644 inmates/lib/arm64/include/
> mach-tegra-tx1/mach/gic_v2.h
> >  create mode 100644 inmates/lib/arm64/include/
> mach-tegra-tx1/mach/timer.h
> >  create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
> >
>
> --
> Ralf Ramsauer
> PGP: 0x8F10049B
>



-- 
Claudio Scordino, Ph.D.
Project Manager - Funded research projects

Evidence Srl
Via Carducci 56
56010 S.Giuliano Terme - Pisa - Italy
Phone:  +39 050 99 11 224
Mobile: + 39 393 811 7491
Fax:   +39 050 99 10 812
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[PATCH v2] README: more explicit requirements

[Claudio Scordino]

This patch aims at reorganizing the README and making the (hardware and
software) requirements more explicit.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 README.md | 128 +++---
 1 file changed, 80 insertions(+), 48 deletions(-)

diff --git a/README.md b/README.md
index eab2ffa..7218b48 100644
--- a/README.md
+++ b/README.md
@@ -1,9 +1,12 @@
 JAILHOUSE
 =
 
+Introduction
+
+
 Jailhouse is a partitioning Hypervisor based on Linux. It is able to run
 bare-metal applications or (adapted) operating systems besides Linux. For this
-purpose it configures CPU and device virtualization features of the hardware
+purpose, it configures CPU and device virtualization features of the hardware
 platform in a way that none of these domains, called "cells" here, can
 interfere with each other in an unacceptable way.
 
@@ -20,8 +23,7 @@ Its management interface is based on Linux infrastructure. So 
you boot Linux
 first, then you enable Jailhouse and finally you split off parts of the
 system's resources and assign them to additional cells.
 
-
-WARNING: This is work in progress! Don't expect things to be complete in any
+**WARNING**: This is work in progress! Don't expect things to be complete in 
any
 dimension. Use at your own risk. And keep the reset button in reach.
 
 
@@ -72,10 +74,10 @@ See the [contribution documentation](CONTRIBUTING.md) for 
details
 on how to write Jailhouse patches and propose them for upstream integration.
 
 
-Requirements (preliminary)
---
+Hardware requirements (preliminary)
+---
 
-x86 architecture:
+ x86 architecture:
 
   - Intel system:
 
@@ -95,31 +97,15 @@ x86 architecture:
 
 - AMD IOMMU (AMD-Vi) is unsupported now but will be required in future
 
-  - at least 2 logical CPUs
-
-  - x86-64 Linux kernel (tested against >= 3.14)
-
-- VT-d IOMMU usage (DMAR) has to be disabled in the Linux kernel, e.g. via
-  the command line parameter:
-
-  intel_iommu=off
-
-- To exploit the faster x2APIC, interrupt remapping needs to be on in the
-  kernel (check for CONFIG_IRQ_REMAP)
-
-ARM architecture:
+  - At least 2 logical CPUs
 
-  - Abstract:
+ ARM architecture:
 
-- ARMv7 with virtualization extensions or ARMv8
+  - ARMv7 with virtualization extensions or ARMv8
 
-- Appropriate boot loader support (typically U-Boot)
-  - Linux is started in HYP mode
-  - PSCI support for CPU offlining
+  - At least 2 logical CPUs
 
-- at least 2 logical CPUs
-
-  - ARM board:
+  - Supported ARM boards:
 
 - Banana Pi ([see more](Documentation/setup-on-banana-pi-arm-board.md))
 
@@ -128,31 +114,75 @@ ARM architecture:
 - ARM Versatile Express with Cortex-A15 or A7 cores
   (includes ARM Fast Model)
 
-  - ARM64 board:
+  - Supported ARM64 boards:
 
 - AMD Seattle / SoftIron Overdrive 3000
 
 - LeMaker HiKey
 
-On x86, hardware capabilities can be validated by running
 
-jailhouse hardware check sysconfig.cell
+Software requirements
+-
+
+ x86 architecture:
 
-using the binary system configuration created for the target (see
-[below](#configuration)).
+  - x86-64 Linux kernel (tested against 3.14+)
+
+- VT-d IOMMU usage (DMAR) has to be disabled in the Linux kernel, e.g. via
+  the command line parameter:
+
+  intel_iommu=off
+
+- To exploit the faster x2APIC, interrupt remapping needs to be on in the
+  kernel (check for CONFIG_IRQ_REMAP)
+
+  - The hypervisor requires a contiguous piece of RAM for itself and each
+additional cell. This currently has to be pre-allocated during boot-up.
+On x86 this is typically done by adding
+
+memmap=66M$0x3b00
+
+as parameter to the command line of the virtual machine's kernel. Note that
+if you plan to put this parameter in GRUB2 variables in /etc/default/grub,
+then you will need three escape characters before the dollar
+(e.g. ```GRUB_CMDLINE_LINUX_DEFAULT="memmap=66M\\\$0x3b00"```).
+
+ ARM architecture:
+
+  - Linux kernel:
+- 3.17+ for ARM
+- 4.7+ for ARM64
+
+  - Appropriate boot loader support (typically U-Boot)
+ - Linux is started in HYP mode
+ - PSCI support for CPU offlining
+
+  - The hypervisor requires a contiguous piece of RAM for itself and each
+additional cell. This currently has to be pre-allocated during boot-up.
+On ARM this can be obtained by reducing the amount of memory seen by the
+kernel (through the `mem=` kernel boot parameter) or by modifying the
+Device Tree.
 
 
 Build & Installation
 
 
-Simply run make, optionally specifying the target kernel directory:
+Simply run `make`, optionally specifying the target kernel directory:
 
 make [KDIR=/path/to/kernel/objects]
 
 Except for the hypervisor image `jailhouse*.bin` that has to be availa

[PATCH v3 3/6] inmates: add support for Tegra TX1

[Claudio Scordino]

This patch adds the inmate support for the Tegra TX1 board.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 inmates/lib/arm64/Makefile |  1 +
 inmates/lib/arm64/Makefile.lib |  1 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h | 14 ++
 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h  | 13 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h   | 13 +
 5 files changed, 42 insertions(+)
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h

diff --git a/inmates/lib/arm64/Makefile b/inmates/lib/arm64/Makefile
index b4f2bc8..0af5b90 100644
--- a/inmates/lib/arm64/Makefile
+++ b/inmates/lib/arm64/Makefile
@@ -19,3 +19,4 @@ lib-y += ../arm/gic.o ../arm/printk.o 
../arm/timer.o
 lib-y  += ../string.o ../cmdline.o
 lib-$(CONFIG_ARM_GIC_V2)   += ../arm/gic-v2.o
 lib-$(CONFIG_SERIAL_AMBA_PL011)+= ../arm/uart-pl011.o
+lib-$(CONFIG_SERIAL_TEGRA) += ../arm/uart-tegra.o
diff --git a/inmates/lib/arm64/Makefile.lib b/inmates/lib/arm64/Makefile.lib
index f8519d8..b28b753 100644
--- a/inmates/lib/arm64/Makefile.lib
+++ b/inmates/lib/arm64/Makefile.lib
@@ -28,6 +28,7 @@ endef
 mach-$(CONFIG_MACH_FOUNDATION_V8)  := foundation-v8
 mach-$(CONFIG_MACH_AMD_SEATTLE) := amd-seattle
 mach-$(CONFIG_MACH_HI6220) := hi6220
+mach-$(CONFIG_MACH_TEGRA_TX1)  := tegra-tx1
 
 MACHINE:= mach-$(mach-y)
 KBUILD_CFLAGS  += -I$(INMATES_LIB)/include/$(MACHINE)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
new file mode 100644
index 000..e513194
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
@@ -0,0 +1,14 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define GICD_BASE  ((void *)0x50041000)
+#define GICC_BASE  ((void *)0x50042000)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
new file mode 100644
index 000..428162d
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define TIMER_IRQ  27
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
new file mode 100644
index 000..7b97dc7
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define UART_BASE  ((void *)0x70006000)
-- 
2.7.4

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[PATCH v3 2/6] uart-tegra: move driver to arm-common

[Claudio Scordino]

From: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>

This patch moves the uart-tegra driver from the arm32-specific directory
to arm-common/ since such driver is used on both arm32 (e.g. TK1) and
arm64 (e.g. TX1) boards.

Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/arch/arm-common/Kbuild| 1 +
 hypervisor/arch/{arm => arm-common}/include/asm/uart-tegra.h | 0
 hypervisor/arch/{arm => arm-common}/uart-tegra.c | 0
 hypervisor/arch/arm/Kbuild   | 2 +-
 hypervisor/arch/arm64/Kbuild | 1 +
 5 files changed, 3 insertions(+), 1 deletion(-)
 rename hypervisor/arch/{arm => arm-common}/include/asm/uart-tegra.h (100%)
 rename hypervisor/arch/{arm => arm-common}/uart-tegra.c (100%)

diff --git a/hypervisor/arch/arm-common/Kbuild 
b/hypervisor/arch/arm-common/Kbuild
index 42c3a9d..6580a70 100644
--- a/hypervisor/arch/arm-common/Kbuild
+++ b/hypervisor/arch/arm-common/Kbuild
@@ -16,5 +16,6 @@ OBJS-y += dbg-write.o lib.o psci.o control.o paging.o 
mmu_cell.o
 OBJS-y += irqchip.o gic-common.o
 OBJS-$(CONFIG_ARM_GIC_V2) += gic-v2.o
 OBJS-$(CONFIG_SERIAL_AMBA_PL011) += uart-pl011.o
+OBJS-$(CONFIG_SERIAL_TEGRA) += uart-tegra.o
 
 COMMON_OBJECTS = $(addprefix ../arm-common/,$(OBJS-y))
diff --git a/hypervisor/arch/arm/include/asm/uart-tegra.h 
b/hypervisor/arch/arm-common/include/asm/uart-tegra.h
similarity index 100%
rename from hypervisor/arch/arm/include/asm/uart-tegra.h
rename to hypervisor/arch/arm-common/include/asm/uart-tegra.h
diff --git a/hypervisor/arch/arm/uart-tegra.c 
b/hypervisor/arch/arm-common/uart-tegra.c
similarity index 100%
rename from hypervisor/arch/arm/uart-tegra.c
rename to hypervisor/arch/arm-common/uart-tegra.c
diff --git a/hypervisor/arch/arm/Kbuild b/hypervisor/arch/arm/Kbuild
index bbdfef3..5b62838 100644
--- a/hypervisor/arch/arm/Kbuild
+++ b/hypervisor/arch/arm/Kbuild
@@ -22,5 +22,5 @@ obj-y += mmu_hyp.o caches.o mach-stubs.o
 
 obj-$(CONFIG_ARM_GIC_V3) += gic-v3.o
 obj-$(CONFIG_SERIAL_8250_DW) += uart-8250-dw.o
-obj-$(CONFIG_SERIAL_TEGRA) += uart-tegra.o
+obj-$(CONFIG_SERIAL_TEGRA) += ../arm-common/uart-tegra.o
 obj-$(CONFIG_MACH_VEXPRESS) += mach-vexpress.o
diff --git a/hypervisor/arch/arm64/Kbuild b/hypervisor/arch/arm64/Kbuild
index 91c2a91..e4b8594 100644
--- a/hypervisor/arch/arm64/Kbuild
+++ b/hypervisor/arch/arm64/Kbuild
@@ -19,3 +19,4 @@ always := built-in.o
 obj-y := $(COMMON_OBJECTS)
 obj-y += entry.o setup.o control.o mmio.o caches.o
 obj-y += exception.o traps.o
+obj-$(CONFIG_SERIAL_TEGRA) += ../arm-common/uart-tegra.o
-- 
2.7.4

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[PATCH v3 5/6] Renaming jetson-tk1-demo.c as jetson-demo.c

[Claudio Scordino]

This patch renames jetson-tk1-demo.c as jetson-demo.c since the demo can
work on both Jetson TK1 and TX1.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/{jetson-tk1-demo.c => jetson-demo.c} | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 rename configs/{jetson-tk1-demo.c => jetson-demo.c} (92%)

diff --git a/configs/jetson-tk1-demo.c b/configs/jetson-demo.c
similarity index 92%
rename from configs/jetson-tk1-demo.c
rename to configs/jetson-demo.c
index 90fcac6..a7f8358 100644
--- a/configs/jetson-tk1-demo.c
+++ b/configs/jetson-demo.c
@@ -1,7 +1,7 @@
 /*
  * Jailhouse, a Linux-based partitioning hypervisor
  *
- * Configuration for gic-demo or uart-demo inmate on Jetson TK1:
+ * Configuration for gic-demo or uart-demo inmate on Jetson TK1 and TX1:
  * 1 CPU, 64K RAM, serial port 0
  *
  * Copyright (c) Siemens AG, 2015
@@ -25,7 +25,7 @@ struct {
 } __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
-   .name = "jetson-tk1-demo",
+   .name = "jetson-demo",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
 
.cpu_set_size = sizeof(config.cpus),
-- 
2.7.4

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[PATCH v3 4/6] Config files for Jetson TX1

[Claudio Scordino]

This patch adds the config file for Jetson TX1.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
---
 configs/jetson-tx1.c | 464 +++
 1 file changed, 464 insertions(+)
 create mode 100644 configs/jetson-tx1.c

diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
new file mode 100644
index 000..be6cfcb
--- /dev/null
+++ b/configs/jetson-tx1.c
@@ -0,0 +1,464 @@
+/*
+ * Jailhouse Jetson TX1 support
+ *
+ * Copyright (C) 2016 Evidence Srl
+ *
+ * Authors:
+ *  Claudio Scordino <clau...@evidence.eu.com>
+ *  Bruno Morelli <b.more...@evidence.eu.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * NOTE: Add "mem=1920M vmalloc=512M" to the kernel command line.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[55];
+   struct jailhouse_irqchip irqchips[2];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .hypervisor_memory = {
+   .phys_start = 0xfc00,
+   .size = 0x400,
+   },
+   .debug_console = {
+   .phys_start = 0x70006000,
+   .size = 0x0040,
+   .flags = JAILHOUSE_MEM_IO,
+   },
+   .platform_info.arm = {
+   .gicd_base = 0x50041000,
+   .gicc_base = 0x50042000,
+   .gich_base = 0x50044000,
+   .gicv_base = 0x50046000,
+   .maintenance_irq = 25,
+   },
+   .root_cell = {
+   .name = "Jetson-TX1",
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0xf,
+   },
+
+
+   .mem_regions = {
+
+   /* PCIE */ {
+   .phys_start = 0x0100,
+   .virt_start = 0x0100,
+   .size = 0x3F00,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* Data memory */ {
+   .phys_start = 0x04000,
+   .virt_start = 0x04000,
+   .size = 0x100,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* host1x */ {
+   .phys_start = 0x5000,
+   .virt_start = 0x5000,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* host1x/vi */ {
+   .phys_start = 0x5408,
+   .virt_start = 0x5408,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* TSEC2 */ {
+   .phys_start = 0x5410,
+   .virt_start = 0x5410,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* Display 2 */ {
+   .phys_start = 0x5424,
+   .virt_start = 0x5424,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* VIC */ {
+   .phys_start = 0x5434,
+   .virt_start = 0x5434,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* NVJPG */ {
+   .phys_start = 0x5438,
+   .virt_start = 0x5438,
+   .size = 0x4,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* NVDEC */ {
+   .phys_start = 0x5448,
+   .virt_start

[PATCH v3 6/6] README: add Nvidia TX1 among the supported boards

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index eab2ffa..841b57b 100644
--- a/README.md
+++ b/README.md
@@ -134,6 +134,8 @@ ARM architecture:
 
 - LeMaker HiKey
 
+- NVIDIA Jetson TX1
+
 On x86, hardware capabilities can be validated by running
 
 jailhouse hardware check sysconfig.cell
-- 
2.7.4

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[PATCH v3 1/6] uart-tegra: remove hardcoded offset

[Claudio Scordino]

From: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>

This patch removes the hard-coded 0x300 offset from the uart tegra
driver since such offset depends on the specific board.

Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 configs/jetson-tk1.c  | 4 ++--
 hypervisor/arch/arm/include/asm/uart-tegra.h  | 1 -
 inmates/lib/arm/include/mach-tegra124/mach/uart.h | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/jetson-tk1.c b/configs/jetson-tk1.c
index 37fc46e..df6c3b5 100644
--- a/configs/jetson-tk1.c
+++ b/configs/jetson-tk1.c
@@ -33,8 +33,8 @@ struct {
.size = 0x400 - 0x10, /* -1MB (PSCI) */
},
.debug_console = {
-   .phys_start = 0x70006000,
-   .size = 0x1000,
+   .phys_start = 0x70006300,
+   .size = 0x40,
.flags = JAILHOUSE_MEM_IO,
},
.platform_info.arm = {
diff --git a/hypervisor/arch/arm/include/asm/uart-tegra.h 
b/hypervisor/arch/arm/include/asm/uart-tegra.h
index d40274e..bedface 100644
--- a/hypervisor/arch/arm/include/asm/uart-tegra.h
+++ b/hypervisor/arch/arm/include/asm/uart-tegra.h
@@ -25,7 +25,6 @@
 
 static void uart_init(struct uart_chip *chip)
 {
-   chip->virt_base += 0x300;
 }
 
 static void uart_wait(struct uart_chip *chip)
diff --git a/inmates/lib/arm/include/mach-tegra124/mach/uart.h 
b/inmates/lib/arm/include/mach-tegra124/mach/uart.h
index 7b97dc7..ce23468 100644
--- a/inmates/lib/arm/include/mach-tegra124/mach/uart.h
+++ b/inmates/lib/arm/include/mach-tegra124/mach/uart.h
@@ -10,4 +10,4 @@
  * the COPYING file in the top-level directory.
  */
 
-#define UART_BASE  ((void *)0x70006000)
+#define UART_BASE  ((void *)0x70006300)
-- 
2.7.4

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Re: [PATCH v2 4/5] Config files for Jetson TX1

[Claudio Scordino]

2016-11-22 17:01 GMT+01:00 Jan Kiszka <jan.kis...@siemens.com>:

> On 2016-11-22 15:48, Claudio Scordino wrote:
> > This patch adds the config files for Jetson TX1.
> >
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
> > ---
> >  ci/jailhouse-config-jetson-tx1.h |   4 +
> >  configs/jetson-tx1-demo.c|  55 +
> >  configs/jetson-tx1.c | 464 ++
> +
> >  3 files changed, 523 insertions(+)
> >  create mode 100644 ci/jailhouse-config-jetson-tx1.h
> >  create mode 100644 configs/jetson-tx1-demo.c
> >  create mode 100644 configs/jetson-tx1.c
> >
> > diff --git a/ci/jailhouse-config-jetson-tx1.h
> b/ci/jailhouse-config-jetson-tx1.h
> > new file mode 100644
> > index 000..7b5fd51
> > --- /dev/null
> > +++ b/ci/jailhouse-config-jetson-tx1.h
> > @@ -0,0 +1,4 @@
> > +#define CONFIG_TRACE_ERROR   1
> > +#define CONFIG_ARM_GIC_V21
> > +#define CONFIG_MACH_TEGRA_TX1   1
> > +#define CONFIG_SERIAL_TEGRA  1
>
> No need to add this file, we are not building the TX1 in our CI.
>
> > diff --git a/configs/jetson-tx1-demo.c b/configs/jetson-tx1-demo.c
> > new file mode 100644
> > index 000..11c0dd9
> > --- /dev/null
> > +++ b/configs/jetson-tx1-demo.c
> > @@ -0,0 +1,55 @@
> > +/*
> > + * Jailhouse, a Linux-based partitioning hypervisor
> > + *
> > + * Configuration for gic-demo or uart-demo inmate on Jetson TK1:
> > + * 1 CPU, 64K RAM, serial port 0
> > + *
> > + * Copyright (c) Siemens AG, 2015
> > + *
> > + * Authors:
> > + *  Jan Kiszka <jan.kis...@siemens.com>
>
> Please update both copyright and description.
>

Actually, jetson-tx1-demo.c is a 1:1 copy of jetson-tk1-demo.c.
I just checked the addressing, so I'd prefer not claiming any copyright on
this.
I wonder if we should duplicate config files or rather just rename
jetson-tx1-demo.c as jetson-demo.c ...

Best regards,

Claudio

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[PATCH v2 3/5] inmates: add support for Tegra TX1

[Claudio Scordino]

This patch adds the inmate support for the Tegra TX1 board.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 inmates/lib/arm64/Makefile |  1 +
 inmates/lib/arm64/Makefile.lib |  1 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h | 14 ++
 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h  | 13 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h   | 13 +
 5 files changed, 42 insertions(+)
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h

diff --git a/inmates/lib/arm64/Makefile b/inmates/lib/arm64/Makefile
index b4f2bc8..0af5b90 100644
--- a/inmates/lib/arm64/Makefile
+++ b/inmates/lib/arm64/Makefile
@@ -19,3 +19,4 @@ lib-y += ../arm/gic.o ../arm/printk.o 
../arm/timer.o
 lib-y  += ../string.o ../cmdline.o
 lib-$(CONFIG_ARM_GIC_V2)   += ../arm/gic-v2.o
 lib-$(CONFIG_SERIAL_AMBA_PL011)+= ../arm/uart-pl011.o
+lib-$(CONFIG_SERIAL_TEGRA) += ../arm/uart-tegra.o
diff --git a/inmates/lib/arm64/Makefile.lib b/inmates/lib/arm64/Makefile.lib
index f8519d8..b28b753 100644
--- a/inmates/lib/arm64/Makefile.lib
+++ b/inmates/lib/arm64/Makefile.lib
@@ -28,6 +28,7 @@ endef
 mach-$(CONFIG_MACH_FOUNDATION_V8)  := foundation-v8
 mach-$(CONFIG_MACH_AMD_SEATTLE) := amd-seattle
 mach-$(CONFIG_MACH_HI6220) := hi6220
+mach-$(CONFIG_MACH_TEGRA_TX1)  := tegra-tx1
 
 MACHINE:= mach-$(mach-y)
 KBUILD_CFLAGS  += -I$(INMATES_LIB)/include/$(MACHINE)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
new file mode 100644
index 000..e513194
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
@@ -0,0 +1,14 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define GICD_BASE  ((void *)0x50041000)
+#define GICC_BASE  ((void *)0x50042000)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
new file mode 100644
index 000..428162d
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define TIMER_IRQ  27
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
new file mode 100644
index 000..7b97dc7
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define UART_BASE  ((void *)0x70006000)
-- 
2.7.4

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[PATCH v2 5/5] README: add Nvidia TX1 among the supported boards

[Claudio Scordino]

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index eab2ffa..841b57b 100644
--- a/README.md
+++ b/README.md
@@ -134,6 +134,8 @@ ARM architecture:
 
 - LeMaker HiKey
 
+- NVIDIA Jetson TX1
+
 On x86, hardware capabilities can be validated by running
 
 jailhouse hardware check sysconfig.cell
-- 
2.7.4

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[PATCH] README: more explicit requirements

[Claudio Scordino]

This patch aims at reorganizing the README and making the (hardware and
software) requirements more explicit.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 README.md | 213 ++
 1 file changed, 118 insertions(+), 95 deletions(-)

diff --git a/README.md b/README.md
index eab2ffa..afc858c 100644
--- a/README.md
+++ b/README.md
@@ -1,9 +1,12 @@
 JAILHOUSE
 =
 
+Introduction
+
+
 Jailhouse is a partitioning Hypervisor based on Linux. It is able to run
 bare-metal applications or (adapted) operating systems besides Linux. For this
-purpose it configures CPU and device virtualization features of the hardware
+purpose, it configures CPU and device virtualization features of the hardware
 platform in a way that none of these domains, called "cells" here, can
 interfere with each other in an unacceptable way.
 
@@ -20,62 +23,14 @@ Its management interface is based on Linux infrastructure. 
So you boot Linux
 first, then you enable Jailhouse and finally you split off parts of the
 system's resources and assign them to additional cells.
 
-
-WARNING: This is work in progress! Don't expect things to be complete in any
+**WARNING**: This is work in progress! Don't expect things to be complete in 
any
 dimension. Use at your own risk. And keep the reset button in reach.
 
 
-Community Resources

-
-Project home:
-
- - https://github.com/siemens/jailhouse
-
-Source code:
-
- - https://github.com/siemens/jailhouse.git
- - g...@github.com:siemens/jailhouse.git
-
-Frequently Asked Questions (FAQ):
-
- - See [FAQ file](FAQ.md)
-
-Mailing list:
-
-  - jailhouse-dev@googlegroups.com
-
-  - Subscription:
-- jailhouse-dev+subscr...@googlegroups.com
-- https://groups.google.com/forum/#!forum/jailhouse-dev/join
-
-  - Archives
-- https://groups.google.com/forum/#!forum/jailhouse-dev
-- http://news.gmane.org/gmane.linux.jailhouse
-
-Continuous integration:
-
-  - https://travis-ci.org/siemens/jailhouse
-
-  - Status:
-- ![](https://travis-ci.org/siemens/jailhouse.svg?branch=master) on master
-- ![](https://travis-ci.org/siemens/jailhouse.svg?branch=next) on next
-
-Static code analysis:
+Hardware requirements (preliminary)
+---
 
-  - https://scan.coverity.com/projects/4114
-
-  - Status:
-- ![](https://scan.coverity.com/projects/4114/badge.svg) on coverity_scan
-
-See the [contribution documentation](CONTRIBUTING.md) for details
-on how to write Jailhouse patches and propose them for upstream integration.
-
-
-Requirements (preliminary)
---
-
-x86 architecture:
+ x86 architecture:
 
   - Intel system:
 
@@ -95,31 +50,15 @@ x86 architecture:
 
 - AMD IOMMU (AMD-Vi) is unsupported now but will be required in future
 
-  - at least 2 logical CPUs
-
-  - x86-64 Linux kernel (tested against >= 3.14)
-
-- VT-d IOMMU usage (DMAR) has to be disabled in the Linux kernel, e.g. via
-  the command line parameter:
-
-  intel_iommu=off
-
-- To exploit the faster x2APIC, interrupt remapping needs to be on in the
-  kernel (check for CONFIG_IRQ_REMAP)
-
-ARM architecture:
-
-  - Abstract:
+  - At least 2 logical CPUs
 
-- ARMv7 with virtualization extensions or ARMv8
+ ARM architecture:
 
-- Appropriate boot loader support (typically U-Boot)
-  - Linux is started in HYP mode
-  - PSCI support for CPU offlining
+  - ARMv7 with virtualization extensions or ARMv8
 
-- at least 2 logical CPUs
+  - At least 2 logical CPUs
 
-  - ARM board:
+  - Supported ARM boards:
 
 - Banana Pi ([see more](Documentation/setup-on-banana-pi-arm-board.md))
 
@@ -128,31 +67,70 @@ ARM architecture:
 - ARM Versatile Express with Cortex-A15 or A7 cores
   (includes ARM Fast Model)
 
-  - ARM64 board:
+  - Supported ARM64 boards:
 
 - AMD Seattle / SoftIron Overdrive 3000
 
 - LeMaker HiKey
 
-On x86, hardware capabilities can be validated by running
 
-jailhouse hardware check sysconfig.cell
+Software requirements
+-
+
+ x86 architecture:
 
-using the binary system configuration created for the target (see
-[below](#configuration)).
+  - x86-64 Linux kernel (tested against 3.14+)
+
+- VT-d IOMMU usage (DMAR) has to be disabled in the Linux kernel, e.g. via
+  the command line parameter:
+
+  intel_iommu=off
+
+- To exploit the faster x2APIC, interrupt remapping needs to be on in the
+  kernel (check for CONFIG_IRQ_REMAP)
+
+  - The hypervisor requires a contiguous piece of RAM for itself and each
+additional cell. This currently has to be pre-allocated during boot-up.
+On x86 this is typically done by adding
+
+memmap=66M$0x3b00
+
+as parameter to the command line of the virtual machine's kernel. Note that
+if you plan to put this parameter in GRUB2 variables in /etc/default/grub,
+then you wil

[PATCH 0/5] Initial support for NVIDIA Jetson TX1

[Claudio Scordino]

This patchset adds the support for NVIDIA Jetson TX1, by moving the uart-tegra
driver to arm-common/ and adding the configs file for the TX1.


Claudio Scordino (5):
  uart-tegra: remove hardcoded offset
  uart-tegra: move driver to arm-common
  inmates: add support for Tegra TX1
  Config files for Jetson TX1
  README: add Nvidia TX1 among the supported boards

 README.md  |   2 +
 ci/jailhouse-config-jetson-tx1.h   |   4 +
 configs/jetson-tk1.c   |   4 +-
 configs/jetson-tx1-demo.c  |  55 +++
 configs/jetson-tx1.c   | 463 +
 hypervisor/arch/arm-common/Kbuild  |   1 +
 .../{arm => arm-common}/include/asm/uart-tegra.h   |   1 -
 hypervisor/arch/{arm => arm-common}/uart-tegra.c   |   0
 hypervisor/arch/arm/Kbuild |   2 +-
 hypervisor/arch/arm64/Kbuild   |   1 +
 inmates/lib/arm/include/mach-tegra124/mach/uart.h  |   2 +-
 inmates/lib/arm64/Makefile |   1 +
 inmates/lib/arm64/Makefile.lib |   1 +
 .../lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h |  14 +
 .../lib/arm64/include/mach-tegra-tx1/mach/timer.h  |  13 +
 .../lib/arm64/include/mach-tegra-tx1/mach/uart.h   |  13 +
 16 files changed, 572 insertions(+), 5 deletions(-)
 create mode 100644 ci/jailhouse-config-jetson-tx1.h
 create mode 100644 configs/jetson-tx1-demo.c
 create mode 100644 configs/jetson-tx1.c
 rename hypervisor/arch/{arm => arm-common}/include/asm/uart-tegra.h (96%)
 rename hypervisor/arch/{arm => arm-common}/uart-tegra.c (100%)
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h

-- 
2.7.4

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[PATCH 4/5] Config files for Jetson TX1

[Claudio Scordino]

This patch adds the config files for Jetson TX1.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Bruno Morelli <b.more...@evidence.eu.com>
---
 ci/jailhouse-config-jetson-tx1.h |   4 +
 configs/jetson-tx1-demo.c|  55 +
 configs/jetson-tx1.c | 463 +++
 3 files changed, 522 insertions(+)
 create mode 100644 ci/jailhouse-config-jetson-tx1.h
 create mode 100644 configs/jetson-tx1-demo.c
 create mode 100644 configs/jetson-tx1.c

diff --git a/ci/jailhouse-config-jetson-tx1.h b/ci/jailhouse-config-jetson-tx1.h
new file mode 100644
index 000..7b5fd51
--- /dev/null
+++ b/ci/jailhouse-config-jetson-tx1.h
@@ -0,0 +1,4 @@
+#define CONFIG_TRACE_ERROR 1
+#define CONFIG_ARM_GIC_V2  1
+#define CONFIG_MACH_TEGRA_TX1   1
+#define CONFIG_SERIAL_TEGRA1
diff --git a/configs/jetson-tx1-demo.c b/configs/jetson-tx1-demo.c
new file mode 100644
index 000..11c0dd9
--- /dev/null
+++ b/configs/jetson-tx1-demo.c
@@ -0,0 +1,55 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for gic-demo or uart-demo inmate on Jetson TK1:
+ * 1 CPU, 64K RAM, serial port 0
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+   struct jailhouse_cell_desc cell;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+   .cell = {
+   .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+   .name = "jetson-tx1-demo",
+   .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   },
+
+   .cpus = {
+   0x8,
+   },
+
+   .mem_regions = {
+   /* UART */ {
+   .phys_start = 0x70006000,
+   .virt_start = 0x70006000,
+   .size = 0x1000,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_IO,
+   },
+   /* RAM */ {
+   .phys_start = 0xfbfe,
+   .virt_start = 0,
+   .size = 0x0001,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+   JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+   },
+   },
+};
diff --git a/configs/jetson-tx1.c b/configs/jetson-tx1.c
new file mode 100644
index 000..57da380
--- /dev/null
+++ b/configs/jetson-tx1.c
@@ -0,0 +1,463 @@
+/*
+ * Jailhouse AArch64 support
+ *
+ * Copyright (C) 2015 Huawei Technologies Duesseldorf GmbH
+ *
+ * Authors:
+ *  Antonios Motakis <antonios.mota...@huawei.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * NOTE: Add "mem=1920M vmalloc=512M" to the kernel command line.
+ */
+
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+   struct jailhouse_system header;
+   __u64 cpus[1];
+   struct jailhouse_memory mem_regions[55];
+   struct jailhouse_irqchip irqchips[2];
+} __attribute__((packed)) config = {
+   .header = {
+   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+   .hypervisor_memory = {
+   .phys_start = 0xfc00,
+   .size = 0x400,
+   },
+   .debug_console = {
+   .phys_start = 0x70006000,
+   .size = 0x0040,
+   .flags = JAILHOUSE_MEM_IO,
+   },
+   .platform_info.arm = {
+   .gicd_base = 0x50041000,
+   .gicc_base = 0x50042000,
+   .gich_base = 0x50044000,
+   .gicv_base = 0x50046000,
+   .maintenance_irq = 25,
+   },
+   .root_cell = {
+   .name = "Jetson-TX1",
+   .cpu_set_size = sizeof(config.cpus),
+   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+   .num_irqchips = ARRAY_SIZE(config.irqchips),
+   },
+   },
+
+   .cpus = {
+   0xf,
+   },
+
+
+   .mem_regions = {
+
+   /* PCIE */ {
+   .phys_start = 0x0100,
+   .virt_start = 0x0100,
+   .size = 0x3F00,
+   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WR

[PATCH 1/5] uart-tegra: remove hardcoded offset

[Claudio Scordino]

This patch removes the hard-coded offset for the uart on tegra boards
since such offset depends on the specific board.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
---
 configs/jetson-tk1.c  | 4 ++--
 hypervisor/arch/arm/include/asm/uart-tegra.h  | 1 -
 inmates/lib/arm/include/mach-tegra124/mach/uart.h | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/configs/jetson-tk1.c b/configs/jetson-tk1.c
index 37fc46e..df6c3b5 100644
--- a/configs/jetson-tk1.c
+++ b/configs/jetson-tk1.c
@@ -33,8 +33,8 @@ struct {
.size = 0x400 - 0x10, /* -1MB (PSCI) */
},
.debug_console = {
-   .phys_start = 0x70006000,
-   .size = 0x1000,
+   .phys_start = 0x70006300,
+   .size = 0x40,
.flags = JAILHOUSE_MEM_IO,
},
.platform_info.arm = {
diff --git a/hypervisor/arch/arm/include/asm/uart-tegra.h 
b/hypervisor/arch/arm/include/asm/uart-tegra.h
index d40274e..bedface 100644
--- a/hypervisor/arch/arm/include/asm/uart-tegra.h
+++ b/hypervisor/arch/arm/include/asm/uart-tegra.h
@@ -25,7 +25,6 @@
 
 static void uart_init(struct uart_chip *chip)
 {
-   chip->virt_base += 0x300;
 }
 
 static void uart_wait(struct uart_chip *chip)
diff --git a/inmates/lib/arm/include/mach-tegra124/mach/uart.h 
b/inmates/lib/arm/include/mach-tegra124/mach/uart.h
index 7b97dc7..ce23468 100644
--- a/inmates/lib/arm/include/mach-tegra124/mach/uart.h
+++ b/inmates/lib/arm/include/mach-tegra124/mach/uart.h
@@ -10,4 +10,4 @@
  * the COPYING file in the top-level directory.
  */
 
-#define UART_BASE  ((void *)0x70006000)
+#define UART_BASE  ((void *)0x70006300)
-- 
2.7.4

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[PATCH 3/5] inmates: add support for Tegra TX1

[Claudio Scordino]

This patch adds the inmate support for the Tegra TX1 board.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 inmates/lib/arm64/Makefile |  1 +
 inmates/lib/arm64/Makefile.lib |  1 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h | 14 ++
 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h  | 13 +
 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h   | 13 +
 5 files changed, 42 insertions(+)
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
 create mode 100644 inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h

diff --git a/inmates/lib/arm64/Makefile b/inmates/lib/arm64/Makefile
index b4f2bc8..0af5b90 100644
--- a/inmates/lib/arm64/Makefile
+++ b/inmates/lib/arm64/Makefile
@@ -19,3 +19,4 @@ lib-y += ../arm/gic.o ../arm/printk.o 
../arm/timer.o
 lib-y  += ../string.o ../cmdline.o
 lib-$(CONFIG_ARM_GIC_V2)   += ../arm/gic-v2.o
 lib-$(CONFIG_SERIAL_AMBA_PL011)+= ../arm/uart-pl011.o
+lib-$(CONFIG_SERIAL_TEGRA) += ../arm/uart-tegra.o
diff --git a/inmates/lib/arm64/Makefile.lib b/inmates/lib/arm64/Makefile.lib
index f8519d8..b28b753 100644
--- a/inmates/lib/arm64/Makefile.lib
+++ b/inmates/lib/arm64/Makefile.lib
@@ -28,6 +28,7 @@ endef
 mach-$(CONFIG_MACH_FOUNDATION_V8)  := foundation-v8
 mach-$(CONFIG_MACH_AMD_SEATTLE) := amd-seattle
 mach-$(CONFIG_MACH_HI6220) := hi6220
+mach-$(CONFIG_MACH_TEGRA_TX1)  := tegra-tx1
 
 MACHINE:= mach-$(mach-y)
 KBUILD_CFLAGS  += -I$(INMATES_LIB)/include/$(MACHINE)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
new file mode 100644
index 000..e513194
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/gic_v2.h
@@ -0,0 +1,14 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define GICD_BASE  ((void *)0x50041000)
+#define GICC_BASE  ((void *)0x50042000)
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
new file mode 100644
index 000..428162d
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/timer.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define TIMER_IRQ  27
diff --git a/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h 
b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
new file mode 100644
index 000..7b97dc7
--- /dev/null
+++ b/inmates/lib/arm64/include/mach-tegra-tx1/mach/uart.h
@@ -0,0 +1,13 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) Siemens AG, 2015
+ *
+ * Authors:
+ *  Jan Kiszka <jan.kis...@siemens.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#define UART_BASE  ((void *)0x70006000)
-- 
2.7.4

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Re: [PATCH 1/1] FAQ: minimal kernel versions

[Claudio Scordino]

I see your point.
Should we then collect information about versions under which jailhouse
cannot work even with a reasoanable amount of effort ?
Or should we add some note saying to ask in list for lower kernel versions ?

[ I just discovered that the arm64 code assumes a kernel 4.7+, and this is
not reported anywhere in the existing documentation. ]

Claudio

2016-11-17 12:40 GMT+01:00 Henning Schild <henning.sch...@siemens.com>:

> Am Thu, 17 Nov 2016 11:59:04 +0100
> schrieb Claudio Scordino <clau...@evidence.eu.com>:
>
> > This patch adds a section to the FAQ to specify the minimal version of
> > the Linux kernel required under each architecture.
> >
> > Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
> > ---
> >  FAQ.md | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/FAQ.md b/FAQ.md
> > index 0cf5a18..28d6651 100644
> > --- a/FAQ.md
> > +++ b/FAQ.md
> > @@ -38,6 +38,15 @@ announced for new Xeon processors. Of course,
> > running code under Jailhouse is slightly slower than on a dedicated
> > uniprocessor machine, but virtualization always comes at price.
> >
> > +**Q: Which is the minimal version of the Linux kernel needed to run
> > Jailhouse ?** +
> > +Architecture| Kernel version
> > +| --
> > +x86 | 3.14+
> > +arm | 3.14+
> > +arm64   | 4.7+
> > +x86 on Qemu/KVM | 4.4+ host / 3.14+ guest
> > +
>
> Good idea to collect that information somewhere. But i guess it should
> also be noted that lower kernel versions can often be enabled without
> much effort. Otherwise the table might be discouraging for people stuck
> with older kernels.
>
> >  Debugging
> >  -
> >
>
>


-- 
Claudio Scordino, Ph.D.
Project Manager - Funded research projects

Evidence Srl
Via Carducci 56
56010 S.Giuliano Terme - Pisa - Italy
Phone:  +39 050 99 11 224
Mobile: + 39 393 811 7491
Fax:   +39 050 99 10 812
http://www.evidence.eu.com

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[PATCH 1/1] FAQ: minimal kernel versions

[Claudio Scordino]

This patch adds a section to the FAQ to specify the minimal version of
the Linux kernel required under each architecture.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 FAQ.md | 9 +
 1 file changed, 9 insertions(+)

diff --git a/FAQ.md b/FAQ.md
index 0cf5a18..28d6651 100644
--- a/FAQ.md
+++ b/FAQ.md
@@ -38,6 +38,15 @@ announced for new Xeon processors. Of course, running code 
under Jailhouse is
 slightly slower than on a dedicated uniprocessor machine, but virtualization
 always comes at price.
 
+**Q: Which is the minimal version of the Linux kernel needed to run Jailhouse 
?**
+
+Architecture| Kernel version
+| --
+x86 | 3.14+
+arm | 3.14+
+arm64   | 4.7+
+x86 on Qemu/KVM | 4.4+ host / 3.14+ guest
+
 Debugging
 -
 
-- 
2.7.4

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[PATCH 4/6] Driver: change function name jailhouse_fw_name()

[Claudio Scordino]

Change the name of jailhouse_fw_name() to the clearer jailhouse_get_fw_name().

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 driver/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/driver/main.c b/driver/main.c
index e3d58bc..2ab9a4c 100644
--- a/driver/main.c
+++ b/driver/main.c
@@ -169,7 +169,7 @@ static void enter_hypervisor(void *info)
atomic_inc(_done);
 }
 
-static inline const char * jailhouse_fw_name(void)
+static inline const char * jailhouse_get_fw_name(void)
 {
 #ifdef CONFIG_X86
if (boot_cpu_has(X86_FEATURE_SVM))
@@ -204,7 +204,7 @@ static int jailhouse_cmd_enable(struct jailhouse_system 
__user *arg)
}
 #endif
 
-   fw_name = jailhouse_fw_name();
+   fw_name = jailhouse_get_fw_name();
if (!fw_name) {
pr_err("jailhouse: Missing or unsupported HVM technology\n");
return -ENODEV;
-- 
2.7.4

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[PATCH 6/6] Additional headers for old kernel versions

[Claudio Scordino]

Include additional headers for compatibility with old kernel versions (e.g. 
3.10)

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 driver/sysfs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/driver/sysfs.c b/driver/sysfs.c
index 4ee5d00..be53dbe 100644
--- a/driver/sysfs.c
+++ b/driver/sysfs.c
@@ -19,6 +19,8 @@
 
 /* For compatibility with older kernel versions */
 #include 
+#include 
+#include 
 
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,11,0)
 #define DEVICE_ATTR_RO(_name) \
-- 
2.7.4

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[PATCH 0/6] General comments

[Claudio Scordino]

This patchset aims at a better understandability of the source code by adding a
few comments and renaming one function.

Claudio Scordino (6):
  Driver: general comments in the source code
  Core: general comments in the source code
  arch: general comments in the source code
  Driver: change function name jailhouse_fw_name()
  FAQ: explain how to build automatic documentation.
  Additional headers for old kernel versions

 FAQ.md | 10 ++
 driver/cell.c  |  2 ++
 driver/main.c  | 16 ++--
 driver/sysfs.c |  2 ++
 hypervisor/arch/arm-common/control.c   |  6 ++
 hypervisor/arch/arm/include/asm/percpu.h   |  3 +++
 hypervisor/arch/x86/apic.c | 12 
 hypervisor/arch/x86/control.c  |  6 ++
 hypervisor/arch/x86/entry.S|  7 +++
 hypervisor/arch/x86/vmx.c  |  6 ++
 hypervisor/control.c   |  8 
 hypervisor/include/jailhouse/cell-config.h |  5 +
 hypervisor/include/jailhouse/control.h |  4 ++--
 hypervisor/include/jailhouse/header.h  | 15 +++
 hypervisor/paging.c|  2 ++
 hypervisor/setup.c |  6 ++
 16 files changed, 102 insertions(+), 8 deletions(-)

-- 
2.7.4

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[PATCH 2/6] Core: general comments in the source code

[Claudio Scordino]

This patch contains a few general comments in the source code of the
core subsystem.

Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
 hypervisor/control.c   |  8 
 hypervisor/include/jailhouse/cell-config.h |  5 +
 hypervisor/include/jailhouse/header.h  | 15 +++
 hypervisor/paging.c|  2 ++
 hypervisor/setup.c |  6 ++
 5 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/hypervisor/control.c b/hypervisor/control.c
index bdb8eae..def3b31 100644
--- a/hypervisor/control.c
+++ b/hypervisor/control.c
@@ -69,6 +69,10 @@ bool cpu_id_valid(unsigned long cpu_id)
test_bit(cpu_id, system_cpu_set));
 }
 
+/*
+ * Suspend all CPUs assigned to the cell except the one executing
+ * the function (if it is in the cell's CPU set) to prevent races.
+ */
 static void cell_suspend(struct cell *cell, struct per_cpu *cpu_data)
 {
unsigned int cpu;
@@ -401,6 +405,10 @@ static int cell_create(struct per_cpu *cpu_data, unsigned 
long config_address)
if (err)
goto err_cell_exit;
 
+   /*
+* Shrinking: the new cell's CPUs are parked, then removed from the root
+* cell, assigned to the new cell and get their stats cleared.
+*/
for_each_cpu(cpu, cell->cpu_set) {
arch_park_cpu(cpu);
 
diff --git a/hypervisor/include/jailhouse/cell-config.h 
b/hypervisor/include/jailhouse/cell-config.h
index e4d6006..bf86068 100644
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -158,8 +158,13 @@ struct jailhouse_iommu {
 
 #define JAILHOUSE_SYSTEM_SIGNATURE "JAILSYST"
 
+/**
+ * General descriptor of the system.
+ */
 struct jailhouse_system {
char signature[8];
+
+   /** Jailhouse's location in memory */
struct jailhouse_memory hypervisor_memory;
struct jailhouse_memory debug_console;
union {
diff --git a/hypervisor/include/jailhouse/header.h 
b/hypervisor/include/jailhouse/header.h
index 4a4d1cb..54cfab9 100644
--- a/hypervisor/include/jailhouse/header.h
+++ b/hypervisor/include/jailhouse/header.h
@@ -24,15 +24,22 @@
  */
 typedef int (*jailhouse_entry)(unsigned int);
 
-/** Hypervisor description. */
+/**
+ * Hypervisor description.
+ * Located at the beginning of the hypervisor binary image and loaded by
+ * the driver (which also initializes some fields).
+ */
 struct jailhouse_header {
-   /** Signature "JAILHOUS".
+   /** Signature "JAILHOUS" used for basic validity check of the
+* hypervisor image.
 * @note Filled at build time. */
char signature[8];
-   /** Size of hypervisor core, rounded up to page boundary.
+   /** Size of hypervisor core.
+* It starts with the hypervisor's header and ends after its bss
+* section. Rounded up to page boundary.
 * @note Filled at build time. */
unsigned long core_size;
-   /** Size of per-CPU data structure.
+   /** Size of the per-CPU data structure.
 * @note Filled at build time. */
unsigned long percpu_size;
/** Entry point (arch_entry()).
diff --git a/hypervisor/paging.c b/hypervisor/paging.c
index b0f4013..07e6fcd 100644
--- a/hypervisor/paging.c
+++ b/hypervisor/paging.c
@@ -27,6 +27,8 @@ extern u8 __page_pool[];
 /**
  * Offset between virtual and physical hypervisor addresses.
  *
+ * Jailhouse operates in a physically contiguous memory region,
+ * enabling offset-based address conversion.
  * @note Private, use page_map_hvirt2phys() or page_map_phys2hvirt() instead.
  */
 unsigned long page_offset;
diff --git a/hypervisor/setup.c b/hypervisor/setup.c
index b76f845..0e2be9c 100644
--- a/hypervisor/setup.c
+++ b/hypervisor/setup.c
@@ -152,6 +152,10 @@ static void init_late(void)
paging_dump_stats("after late setup");
 }
 
+/*
+ * This is the entry point, called by the Linux driver on each CPU
+ * when initializing Jailhouse.
+ */
 int entry(unsigned int cpu_id, struct per_cpu *cpu_data)
 {
static volatile bool activate;
@@ -162,6 +166,8 @@ int entry(unsigned int cpu_id, struct per_cpu *cpu_data)
spin_lock(_lock);
 
if (master_cpu_id == -1) {
+   /* Only the master CPU, the first to enter this
+* function, performs system-wide initializations. */
master = true;
init_early(cpu_id);
}
-- 
2.7.4

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