Re: [PATCH v2 1/3] mmc: add Coldfire esdhc support
Hi Adrian, On Tue, Jul 02, 2019 at 12:10:54PM +0300, Adrian Hunter wrote: > On 20/06/19 1:22 AM, Angelo Dureghello wrote: > > Hi Christoph, > > > > On Sun, Jun 16, 2019 at 11:58:07PM -0700, Christoph Hellwig wrote: > >> On Sun, Jun 16, 2019 at 10:48:21PM +0200, Angelo Dureghello wrote: > >>> This driver has been developed as a separate module starting > >>> from the similar sdhci-esdhc-fls.c. > >>> Separation has been mainly driven from change in endianness. > >> > >> Can't we have a way to define the endianess at build or even runtime? > >> We have plenty of that elsewhere in the kernel. > > > > well, the base sdhci layer wants to access byte-size fields of the > > esdhc controller registers. > > But this same Freescale esdhc controller may be found in 2 > > flavors, big-endian or little-endian organized. > > So in this driver i am actually correcting byte-addresses to > > access the wanted byte-field in the big-endian hw controller. > > > > So this is a bit different from a be-le endian swap of a > > long or a short that the kernel is organized to do.. > > Did you consider just using different sdhci_ops so that you could support > different sdhci I/O accessors? Initially i tried to modify the IMX/Vybrid (arm) driver. But was stopped from several points, trying to remember now, - the I/O accessors was a const struct, but this of course is not a big issue, - here and there bitfields and positions of the ColdFire controller registers, compared to the arm versions, are different, so controller hw is not exactly the same, - on ColdFire controller and some behaviors and errata are different, - dma endiannes not hw-configurable, - ColdFire has max clock limitations, a bit different clock init. Finally, since there is already a common library (shdci.c) i decided to go as a separate driver, instead of filling the driver of "if (coldfire)" also mainly for the following reasons: 1) separated ColdFire driver has a quite small amount of code, simple to understand. 2) having drivers used by multiple architectures, it add risks, each time i perform a change, i can test it only on ColdFire, and can break the driver for the other architectures (i see this not rarely happening for multiple-arch used drivers). So let me know if the way chosen can be ok. Otherwise i will roll back trying to modify the iMX/Vybrid driver, likely adding a lot of "if (coldfire)" complicating it quite a lot. Regards, Angelo
Re: [PATCH v2 3/3] mmc: enabling ColdFire esdhc controller support
Hi Adrian, On Tue, Jul 02, 2019 at 12:11:02PM +0300, Adrian Hunter wrote: > On 16/06/19 11:48 PM, Angelo Dureghello wrote: > > Signed-off-by: Angelo Dureghello > > --- > > drivers/mmc/host/Kconfig | 13 + > > drivers/mmc/host/Makefile | 3 ++- > > 2 files changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > > index 931770f17087..9b426094d10a 100644 > > --- a/drivers/mmc/host/Kconfig > > +++ b/drivers/mmc/host/Kconfig > > @@ -221,6 +221,19 @@ config MMC_SDHCI_CNS3XXX > > > > If unsure, say N. > > > > +config MMC_SDHCI_ESDHC_MCF > > + tristate "SDHCI support for the Freescale eSDHC ColdFire controller" > > + depends on M5441x > > + depends on MMC_SDHCI_PLTFM > > + select MMC_SDHCI_IO_ACCESSORS > > + help > > + This selects the Freescale eSDHC controller support for > > + ColdFire mcf5441x devices. > > + > > + If you have a controller with this interface, say Y or M here. > > + > > + If unsure, say N. > > + > > config MMC_SDHCI_ESDHC_IMX > > tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller" > > depends on ARCH_MXC > > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > > index 73578718f119..b2127ee5e71e 100644 > > --- a/drivers/mmc/host/Makefile > > +++ b/drivers/mmc/host/Makefile > > @@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o > > obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o > > obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o > > obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o > > +obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o > > obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o > > obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o > > obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o > > @@ -103,4 +104,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y) > > endif > > > > obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o > > -sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o > > +sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy. > > Inadvertent change there Aaargh, sorry, good cactch :) Will fix it. Reagrds, Angelo
Re: [PATCH v2 2/3] mmc: sdhci: add quirks for be to le byte swapping
Hi Adrian,
thanks for the feedbacks.
On Tue, Jul 02, 2019 at 12:10:44PM +0300, Adrian Hunter wrote:
> On 16/06/19 11:48 PM, Angelo Dureghello wrote:
> > Some controller as the ColdFire eshdc may require an endianness
> > byte swap, because DMA read endianness is not configurable.
>
> I would prefer something more generic, like adding another callback
> for ->request_done() e.g.
>
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index f56ae6f153d4..a63e528cb885 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -2729,7 +2729,10 @@ static bool sdhci_request_done(struct sdhci_host *host)
>
> spin_unlock_irqrestore(>lock, flags);
>
> - mmc_request_done(host->mmc, mrq);
> + if (host->ops->request_done)
> + host->ops->request_done(host, mrq);
> + else
> + mmc_request_done(host->mmc, mrq);
>
> return false;
> }
>
>
> Then you can use the ->request_done() callback to iterate over the data->sg
> and make byte-swaps as needed.
>
Ok, good to know, will try.
> >
> > Signed-off-by: Angelo Dureghello
> > ---
> > drivers/mmc/host/sdhci.c | 19 +++
> > drivers/mmc/host/sdhci.h | 7 +++
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 59acf8e3331e..f56ae6f153d4 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -2600,6 +2600,18 @@ static const struct mmc_host_ops sdhci_ops = {
> > .card_busy = sdhci_card_busy,
> > };
> >
> > +static void sdhci_be_to_le(char *buff, u32 length)
> > +{
> > + int i, size = length >> 2;
> > + u32 *buffer = (u32 *)buff;
> > + u32 temp;
> > +
> > + for (i = 0; i < size; i++) {
> > + temp = *buffer;
> > + *buffer++ = __le32_to_cpu(temp);
> > + }
> > +}
> > +
> >
> > /*\
> > *
> > *
> > * Request done
> > *
> > @@ -2655,6 +2667,13 @@ static bool sdhci_request_done(struct sdhci_host
> > *host)
> > host->bounce_addr,
> > host->bounce_buffer_size,
> > DMA_FROM_DEVICE);
> > +
> > + if (host->quirks2 &
> > + SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP)
> > + sdhci_be_to_le(
> > + host->bounce_buffer,
> > + length);
> > +
> > sg_copy_from_buffer(data->sg,
> > data->sg_len,
> > host->bounce_buffer,
> > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> > index 199712e7adbb..be08ff1a8c6f 100644
> > --- a/drivers/mmc/host/sdhci.h
> > +++ b/drivers/mmc/host/sdhci.h
> > @@ -482,6 +482,13 @@ struct sdhci_host {
> > */
> > #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
> >
> > +/*
> > + * On some architectures, as ColdFire/m68k, native endianness is big
> > endian,
> > + * and the dma buffer is filled in big endian order only (no other
> > options).
> > + * So, a swap is needed for these specific cases.
> > + */
> > +#define SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP (1<<19)
> > +
> > int irq;/* Device IRQ */
> > void __iomem *ioaddr; /* Mapped address */
> > char *bounce_buffer;/* For packing SDMA reads/writes */
> >
>
Reagrds,
Angelo
Re: [PATCH v2 1/3] mmc: add Coldfire esdhc support
Hi Christoph, On Sun, Jun 16, 2019 at 11:58:07PM -0700, Christoph Hellwig wrote: > On Sun, Jun 16, 2019 at 10:48:21PM +0200, Angelo Dureghello wrote: > > This driver has been developed as a separate module starting > > from the similar sdhci-esdhc-fls.c. > > Separation has been mainly driven from change in endianness. > > Can't we have a way to define the endianess at build or even runtime? > We have plenty of that elsewhere in the kernel. well, the base sdhci layer wants to access byte-size fields of the esdhc controller registers. But this same Freescale esdhc controller may be found in 2 flavors, big-endian or little-endian organized. So in this driver i am actually correcting byte-addresses to access the wanted byte-field in the big-endian hw controller. So this is a bit different from a be-le endian swap of a long or a short that the kernel is organized to do.. Regards, Angelo
[PATCH v2 1/3] mmc: add Coldfire esdhc support
This driver has been developed as a separate module starting
from the similar sdhci-esdhc-fls.c.
Separation has been mainly driven from change in endianness.
Signed-off-by: Angelo Dureghello
---
drivers/mmc/host/sdhci-esdhc-mcf.c | 442
include/linux/platform_data/mmc-esdhc-mcf.h | 17 +
2 files changed, 459 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-esdhc-mcf.c
create mode 100644 include/linux/platform_data/mmc-esdhc-mcf.h
diff --git a/drivers/mmc/host/sdhci-esdhc-mcf.c
b/drivers/mmc/host/sdhci-esdhc-mcf.c
new file mode 100644
index ..8e910ee412a8
--- /dev/null
+++ b/drivers/mmc/host/sdhci-esdhc-mcf.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Freescale eSDHC ColdFire family controller driver, platform bus.
+ *
+ * Copyright (c) 2019 Sysam, Italy
+ * Author: Angelo Dureghello
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "sdhci-pltfm.h"
+#include "sdhci-esdhc.h"
+
+#defineESDHC_PROCTL_D3CD 0x08
+#define ESDHC_PROCTL_AI0x20
+#define ESDHC_PROCTL_DTW_MASK (0x3 << 1)
+#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
+#define ESDHC_DEFAULT_HOST_CONTROL 0x28
+
+/*
+ * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
+ */
+#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
+
+struct pltfm_mcf_data {
+ struct clk *clk_ipg;
+ struct clk *clk_ahb;
+ struct clk *clk_per;
+ int aside;
+ int current_bus_width;
+};
+
+static inline void esdhc_clrset_be(struct sdhci_host *host,
+ u32 mask, u32 val, int reg)
+{
+ void __iomem *base = host->ioaddr + (reg & ~3);
+ u8 shift = (reg & 3) << 3;
+
+ mask <<= shift;
+ val <<= shift;
+
+ if (reg == SDHCI_HOST_CONTROL)
+ val |= ESDHC_PROCTL_D3CD;
+
+ writel((readl(base) & ~mask) | val, base);
+}
+
+/*
+ * Note: mcf is big-endian, single bytes need to be accessed at big endian
+ * offsets.
+ */
+static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
+{
+ void __iomem *base = host->ioaddr + (reg & ~3);
+ u8 shift = (reg & 3) << 3;
+ u32 mask = ~(0xff << shift);
+
+ switch (reg) {
+ case SDHCI_HOST_CONTROL:
+ /*
+* Recomposition needed, restore always endianness and
+* keep D3CD and AI, just setting bus width.
+*/
+ writel(ESDHC_DEFAULT_HOST_CONTROL | (val & 0x6),
+ host->ioaddr + SDHCI_HOST_CONTROL);
+ return;
+ }
+
+ writel((readl(base) & mask) | (val << shift), base);
+}
+
+static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
+ void __iomem *base = host->ioaddr + (reg & ~3);
+ u8 shift = (reg & 3) << 3;
+ u32 mask = ~(0x << shift);
+
+ switch (reg) {
+ case SDHCI_TRANSFER_MODE:
+ mcf_data->aside = val;
+ return;
+ case SDHCI_COMMAND:
+ /*
+* As for the fsl driver,
+* we have to set the mode in a single write here.
+*/
+ writel(val << 16 | mcf_data->aside,
+ host->ioaddr + SDHCI_TRANSFER_MODE);
+ return;
+ }
+
+ writel((readl(base) & mask) | (val << shift), base);
+}
+
+static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
+{
+ u32 data;
+
+ if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
+ reg == SDHCI_INT_STATUS)) {
+ if (val & SDHCI_INT_CARD_INT) {
+ /*
+* eSDHC issue, errata:
+* ECF218: Misses SDIO interrupt when CINT is disabled
+*/
+ data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
+ data &= ~ESDHC_PROCTL_D3CD;
+ writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
+ data |= ESDHC_PROCTL_D3CD;
+ writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
+ }
+ /*
+* On some commands, mcf controller gives a false data CRC
+* error, since checking the read buffer, it is correct.
+* Workaround, suppressing CRC error interrupt flag.
+*/
+ if (reg == SDHCI_INT_ENABLE)
+ val &= ~SDHCI_INT_DATA_CRC;
+ }
+
+ writel(val, host->ioaddr + reg);
+}
+
+static u8 esdhc_mcf_readb_be(st
[PATCH v2 3/3] mmc: enabling ColdFire esdhc controller support
Signed-off-by: Angelo Dureghello --- drivers/mmc/host/Kconfig | 13 + drivers/mmc/host/Makefile | 3 ++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..9b426094d10a 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -221,6 +221,19 @@ config MMC_SDHCI_CNS3XXX If unsure, say N. +config MMC_SDHCI_ESDHC_MCF + tristate "SDHCI support for the Freescale eSDHC ColdFire controller" + depends on M5441x + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the Freescale eSDHC controller support for + ColdFire mcf5441x devices. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_SDHCI_ESDHC_IMX tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller" depends on ARCH_MXC diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..b2127ee5e71e 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o +obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o @@ -103,4 +104,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y) endif obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o -sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o +sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy. -- 2.20.1
[PATCH v2 2/3] mmc: sdhci: add quirks for be to le byte swapping
Some controller as the ColdFire eshdc may require an endianness
byte swap, because DMA read endianness is not configurable.
Signed-off-by: Angelo Dureghello
---
drivers/mmc/host/sdhci.c | 19 +++
drivers/mmc/host/sdhci.h | 7 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 59acf8e3331e..f56ae6f153d4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2600,6 +2600,18 @@ static const struct mmc_host_ops sdhci_ops = {
.card_busy = sdhci_card_busy,
};
+static void sdhci_be_to_le(char *buff, u32 length)
+{
+ int i, size = length >> 2;
+ u32 *buffer = (u32 *)buff;
+ u32 temp;
+
+ for (i = 0; i < size; i++) {
+ temp = *buffer;
+ *buffer++ = __le32_to_cpu(temp);
+ }
+}
+
/*\
* *
* Request done *
@@ -2655,6 +2667,13 @@ static bool sdhci_request_done(struct sdhci_host *host)
host->bounce_addr,
host->bounce_buffer_size,
DMA_FROM_DEVICE);
+
+ if (host->quirks2 &
+ SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP)
+ sdhci_be_to_le(
+ host->bounce_buffer,
+ length);
+
sg_copy_from_buffer(data->sg,
data->sg_len,
host->bounce_buffer,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 199712e7adbb..be08ff1a8c6f 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -482,6 +482,13 @@ struct sdhci_host {
*/
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
+/*
+ * On some architectures, as ColdFire/m68k, native endianness is big endian,
+ * and the dma buffer is filled in big endian order only (no other options).
+ * So, a swap is needed for these specific cases.
+ */
+#define SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP (1<<19)
+
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
char *bounce_buffer;/* For packing SDMA reads/writes */
--
2.20.1
Re: [PATCH 2/3] mmc: sdhci: add quirks for be to le byte swapping
Hi Adrian,
On Wed, Jun 12, 2019 at 09:42:27AM +0300, Adrian Hunter wrote:
> On 12/05/19 10:41 PM, Angelo Dureghello wrote:
> > Some controller as the ColdFire eshdc may require an endianness
> > byte swap, becouse DMA read endianness is not configurable.
>
> becouse -> because
>
ok
> Do any other drivers have this issue?
>
host/mxcmmc.c for PPC devices is doing a similar swap (buffer_swap32).
> >
> > Signed-off-by: Angelo Dureghello
> > ---
> > drivers/mmc/host/sdhci.c | 19 +++
> > drivers/mmc/host/sdhci.h | 7 +++
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 97158344b862..317dcfb4bb4c 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -2592,6 +2592,18 @@ static const struct mmc_host_ops sdhci_ops = {
> > .card_busy = sdhci_card_busy,
> > };
> >
> > +static void sdhci_be_to_le(char *buff, u32 length)
> > +{
> > + int i, size = length >> 2;
> > + u32 *buffer = (u32 *)buff;
> > + u32 temp;
> > +
> > + for (i = 0; i < size; i++) {
> > + temp = *buffer;
> > + *buffer++ = __le32_to_cpu(temp);
> > + }
> > +}
> > +
> >
> > /*\
> > *
> > *
> > * Request done
> > *
> > @@ -2647,6 +2659,13 @@ static bool sdhci_request_done(struct sdhci_host
> > *host)
> > host->bounce_addr,
> > host->bounce_buffer_size,
> > DMA_FROM_DEVICE);
> > +
> > + if (host->quirks2 &
> > + SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP)
> > + sdhci_be_to_le(
> > + host->bounce_buffer,
> > + length);
>
> How come it only affects the bounce buffer? What about if there is no
> bounce buffer?
>
Right, Will check where how to apply the swap also without bounce buffer.
> > +
> > sg_copy_from_buffer(data->sg,
> > data->sg_len,
> > host->bounce_buffer,
> > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> > index d6bcc584c92b..38fa69678cec 100644
> > --- a/drivers/mmc/host/sdhci.h
> > +++ b/drivers/mmc/host/sdhci.h
> > @@ -486,6 +486,13 @@ struct sdhci_host {
> > */
> > #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
> >
> > +/*
> > + * On some architectures, as ColdFire/m68k, native endianness is big
> > endian,
> > + * and the dma buffer is filled in big endian order only (no other
> > options).
> > + * So, a swap is needed for these specific cases.
> > + */
> > +#define SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP (1<<19)
> > +
> > int irq;/* Device IRQ */
> > void __iomem *ioaddr; /* Mapped address */
> > char *bounce_buffer;/* For packing SDMA reads/writes */
> >
>
Regards,
Angelo
Re: [PATCH 1/3] mmc: add Coldfire esdhc support
Hi Adrian,
many thanks for the feedbacks,
On Wed, Jun 12, 2019 at 09:30:46AM +0300, Adrian Hunter wrote:
> On 12/05/19 10:41 PM, Angelo Dureghello wrote:
> > This driver has been developed as a separate module starting
> > from the similar sdhci-esdhc-fls.c.
>
> Which is not in the mainline kernel?
>
Sorry, my fsl/imx mistake, it is drivers/mmc/host/sdhci-esdhc-imx.c
> > Separation has been mainly driven from change in endianness.
> >
> > Signed-off-by: Angelo Dureghello
> > ---
> > drivers/mmc/host/sdhci-esdhc-mcf.c | 432
> > include/linux/platform_data/mmc-esdhc-mcf.h | 17 +
> > 2 files changed, 449 insertions(+)
> > create mode 100644 drivers/mmc/host/sdhci-esdhc-mcf.c
> > create mode 100644 include/linux/platform_data/mmc-esdhc-mcf.h
> >
> > diff --git a/drivers/mmc/host/sdhci-esdhc-mcf.c
> > b/drivers/mmc/host/sdhci-esdhc-mcf.c
> > new file mode 100644
> > index ..1ba6e0431813
> > --- /dev/null
> > +++ b/drivers/mmc/host/sdhci-esdhc-mcf.c
> > @@ -0,0 +1,432 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Freescale eSDHC ColdFire family controller driver, platform bus.
> > + *
> > + * Copyright (c) 2019 Sysam, Italy
> > + * Author: Angelo Dureghello
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "sdhci-pltfm.h"
> > +#include "sdhci-esdhc.h"
> > +
> > +#defineESDHC_PROCTL_D3CD 0x08
> > +#define ESDHC_PROCTL_AI0x20
> > +#define ESDHC_PROCTL_DTW_MASK (0x3 << 1)
> > +#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
> > +#define ESDHC_DEFAULT_HOST_CONTROL 0x28
> > +
> > +/*
> > + * Freescale eSDHC has DMA ERR omn bit 28, not as std spec says, bit 25.
>
> omn -> own ?
>
ack, will fix
> > + */
> > +#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
> > +
> > +struct pltfm_mcf_data {
> > + struct mcf_esdhc_platform_data plat_data;
> > + struct clk *clk_ipg;
> > + struct clk *clk_ahb;
> > + struct clk *clk_per;
> > + int aside;
> > + int current_bus_width;
> > +};
> > +
> > +static inline void esdhc_clrset_be(struct sdhci_host *host,
> > + u32 mask, u32 val, int reg)
> > +{
> > + void __iomem *base = host->ioaddr + (reg & ~3);
> > + u8 shift = (reg & 3) << 3;
> > +
> > + mask <<= shift;
> > + val <<= shift;
> > +
> > + if (reg == SDHCI_HOST_CONTROL)
> > + val |= ESDHC_PROCTL_D3CD;
> > +
> > + writel((readl(base) & ~mask) | val, base);
> > +}
> > +
> > +/*
> > + * Note: mcf is big-endian, single bytes need to be accessed at big endian
> > + * offsets.
> > + */
> > +static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
> > +{
> > + void __iomem *base = host->ioaddr + (reg & ~3);
> > + u8 shift = (reg & 3) << 3;
> > + u32 mask = ~(0xff << shift);
> > +
> > + switch (reg) {
> > + case SDHCI_HOST_CONTROL:
> > + /*
> > +* Recomposition needed, restore always endianness and
> > +* keep D3CD and AI, just setting bus width.
> > +*/
> > + writel(ESDHC_DEFAULT_HOST_CONTROL | (val & 0x6),
> > + host->ioaddr + SDHCI_HOST_CONTROL);
> > + return;
> > + }
> > +
> > + writel((readl(base) & mask) | (val << shift), base);
> > +}
> > +
> > +static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
> > +{
> > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> > + struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
> > + void __iomem *base = host->ioaddr + (reg & ~3);
> > + u8 shift = (reg & 3) << 3;
> > + u32 mask = ~(0x << shift);
> > +
> > + switch (reg) {
> > + case SDHCI_TRANSFER_MODE:
> > + mcf_data->aside = val;
> > + return;
> > + case SDHCI_COMMAND:
> > + /*
> > +* As for the fsl driver,
> > +* we have to set the mode in a single write here.
> > +*/
> > + writel(val << 16 | mcf_data->aside,
> > + host->ioaddr + SDHCI_TRANSFER_MODE);
> > + return;
> > + }
> &g
Re: mcf5441x, mmu boot not working anymore
Hi Greg, On Mon, May 13, 2019 at 03:06:16PM +1000, Greg Ungerer wrote: > Hi Angelo, > > On 12/5/19 5:59 pm, Angelo Dureghello wrote: > > Hi all, > > > > resending this in the proper mailing (sent to lkml for error). > > > > Just rebased to master right now, so @ > 5.1.1, > > nommu boot works, mmu boot hangs without any message. > > > > Before rebase i was near 5.1-rc1 but lost the log, unfortunately. > > > > I am booting linux passing a ramfs address of a ramfs loaded > > in memory from u-boot. > > > > After some investigations, just found this: > > - without passing the ramfs, kernel boots. > > - with ramfs, adding some low level traces, i get: > > > > 5Linux version 5.1.0stmark2-001-09826-gd881126bf3f8-dirty (angelo@box) > > (gcc version 5.2.0 (crosstools-sysam-2016.04.16)) > > #221 Sun May 12 00:31:57 CEST 2019 > > > > initrd at 0x47d33000:0x47d85e44 > > overlap at 1073741889 for chunk 0 > > overlap at 1073746160 for chunk 0 > > overlap at 1073746719 for chunk 0 > > overlap at 1073746720 for chunk 0 > > overlap at 1073746721 for chunk 0 > > overlap at 1073746722 for chunk 0 > > Can you git bisect to find which commit breaks it? > Sure. I bisect-ed. The offending commit is: d55535232c3dbde9a523a9d10d68670f5fe5dec3 is the first bad commit commit d55535232c3dbde9a523a9d10d68670f5fe5dec3 Author: Kees Cook Date: Fri Apr 19 23:27:05 2019 -0400 random: move rand_initialize() earlier Right now rand_initialize() is run as an early_initcall(), but it only depends on timekeeping_init() (for mixing ktime_get_real() into the pools). However, the call to boot_init_stack_canary() for stack canary initialization runs earlier, which triggers a warning at boot: random: get_random_bytes called from start_kernel+0x357/0x548 with crng_init=0 Instead, this moves rand_initialize() to after timekeeping_init(), and moves canary initialization here as well. Note that this warning may still remain for machines that do not have UEFI RNG support (which initializes the RNG pools during setup_arch()), or for x86 machines without RDRAND (or booting without "random.trust=on" or CONFIG_RANDOM_TRUST_CPU=y). Signed-off-by: Kees Cook Signed-off-by: Theodore Ts'o > Regards > Greg > > Regards, Angelo
Re: [PATCH 3/3] mmc: enabling ColdFire esdhc controller support
Hi Greg, On Mon, May 13, 2019 at 02:19:57PM +1000, Greg Ungerer wrote: > Hi Angelo, > > On 13/5/19 5:41 am, Angelo Dureghello wrote: > > Signed-off-by: Angelo Dureghello > > --- > > drivers/mmc/host/Kconfig | 13 + > > drivers/mmc/host/Makefile | 3 +++ > > 2 files changed, 16 insertions(+) > > > > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > > index 0e86340536b6..91007572a097 100644 > > --- a/drivers/mmc/host/Kconfig > > +++ b/drivers/mmc/host/Kconfig > > @@ -220,6 +220,19 @@ config MMC_SDHCI_CNS3XXX > > If unsure, say N. > > +config MMC_SDHCI_ESDHC_MCF > > + tristate "SDHCI support for the Freescale eSDHC ColdFire controller" > > + depends on M5441x > > + depends on MMC_SDHCI_PLTFM > > + select MMC_SDHCI_IO_ACCESSORS > > + help > > + This selects the Freescale eSDHC/uSDHC controller support > > + found on i.MX25, i.MX35 i.MX5x and i.MX6x. > > So you copied/pasted this from the entry for the MMC_SDHCI_ESDHC_IMX driver? > > I have not looked at the hardware module of the SHDC controller in > the ColdFire parts, but is it in any way similar or the same as > Freescale uses in the iMX families? > Oh, i forgot those iMX references, need to fix it, thanks for catching it. Initially i tried to use the existing imx driver, but mainly the ColdFire controller needs all ops/accessors functions to be big endian, and there are other minimal differecies in the controllers. Finally the simpliest way was to create a separate module. The base is still sdhci.c. > Regards > Greg > Regards, Angelo > > > > + If you have a controller with this interface, say Y or M here. > > + > > + If unsure, say N. > > + > > config MMC_SDHCI_ESDHC_IMX > > tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller" > > depends on ARCH_MXC > > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > > index 73578718f119..17c3826dfe81 100644 > > --- a/drivers/mmc/host/Makefile > > +++ b/drivers/mmc/host/Makefile > > @@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o > > obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o > > obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o > > obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o > > +obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o > > obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o > > obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o > > obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o > > @@ -104,3 +105,5 @@ endif > > obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o > > sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o > > + > > +CFLAGS_sdhci-esdhc-mcf.o := -DDEBUG > >
[PATCH 3/3] mmc: enabling ColdFire esdhc controller support
Signed-off-by: Angelo Dureghello --- drivers/mmc/host/Kconfig | 13 + drivers/mmc/host/Makefile | 3 +++ 2 files changed, 16 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0e86340536b6..91007572a097 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -220,6 +220,19 @@ config MMC_SDHCI_CNS3XXX If unsure, say N. +config MMC_SDHCI_ESDHC_MCF + tristate "SDHCI support for the Freescale eSDHC ColdFire controller" + depends on M5441x + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the Freescale eSDHC/uSDHC controller support + found on i.MX25, i.MX35 i.MX5x and i.MX6x. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_SDHCI_ESDHC_IMX tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller" depends on ARCH_MXC diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..17c3826dfe81 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o +obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o @@ -104,3 +105,5 @@ endif obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o + +CFLAGS_sdhci-esdhc-mcf.o := -DDEBUG -- 2.20.1
[PATCH 2/3] mmc: sdhci: add quirks for be to le byte swapping
Some controller as the ColdFire eshdc may require an endianness
byte swap, becouse DMA read endianness is not configurable.
Signed-off-by: Angelo Dureghello
---
drivers/mmc/host/sdhci.c | 19 +++
drivers/mmc/host/sdhci.h | 7 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 97158344b862..317dcfb4bb4c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2592,6 +2592,18 @@ static const struct mmc_host_ops sdhci_ops = {
.card_busy = sdhci_card_busy,
};
+static void sdhci_be_to_le(char *buff, u32 length)
+{
+ int i, size = length >> 2;
+ u32 *buffer = (u32 *)buff;
+ u32 temp;
+
+ for (i = 0; i < size; i++) {
+ temp = *buffer;
+ *buffer++ = __le32_to_cpu(temp);
+ }
+}
+
/*\
* *
* Request done *
@@ -2647,6 +2659,13 @@ static bool sdhci_request_done(struct sdhci_host *host)
host->bounce_addr,
host->bounce_buffer_size,
DMA_FROM_DEVICE);
+
+ if (host->quirks2 &
+ SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP)
+ sdhci_be_to_le(
+ host->bounce_buffer,
+ length);
+
sg_copy_from_buffer(data->sg,
data->sg_len,
host->bounce_buffer,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index d6bcc584c92b..38fa69678cec 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -486,6 +486,13 @@ struct sdhci_host {
*/
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
+/*
+ * On some architectures, as ColdFire/m68k, native endianness is big endian,
+ * and the dma buffer is filled in big endian order only (no other options).
+ * So, a swap is needed for these specific cases.
+ */
+#define SDHCI_QUIRK2_USE_32BIT_BE_DMA_SWAP (1<<19)
+
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
char *bounce_buffer;/* For packing SDMA reads/writes */
--
2.20.1
Re: mcf5441x, mmu boot not working anymore
Hi,
On Sun, May 12, 2019 at 09:59:00AM +0200, Angelo Dureghello wrote:
> Hi all,
>
> resending this in the proper mailing (sent to lkml for error).
>
> Just rebased to master right now, so @ > 5.1.1,
> nommu boot works, mmu boot hangs without any message.
>
> Before rebase i was near 5.1-rc1 but lost the log, unfortunately.
>
> I am booting linux passing a ramfs address of a ramfs loaded
> in memory from u-boot.
>
> After some investigations, just found this:
> - without passing the ramfs, kernel boots.
> - with ramfs, adding some low level traces, i get:
>
> 5Linux version 5.1.0stmark2-001-09826-gd881126bf3f8-dirty (angelo@box)
> (gcc version 5.2.0 (crosstools-sysam-2016.04.16))
> #221 Sun May 12 00:31:57 CEST 2019
>
> initrd at 0x47d33000:0x47d85e44
> overlap at 1073741889 for chunk 0
> overlap at 1073746160 for chunk 0
> overlap at 1073746719 for chunk 0
> overlap at 1073746720 for chunk 0
> overlap at 1073746721 for chunk 0
> overlap at 1073746722 for chunk 0
>
i am far from understanding the real issue, btw, i found a workaround:
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 8868a4c9adae..33d14cb60fe5 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -57,7 +57,7 @@ pg_data_t *pg_data_table[65];
EXPORT_SYMBOL(pg_data_table);
#endif
-void __init m68k_setup_node(int node)
+void m68k_setup_node(int node)
{
#ifndef CONFIG_SINGLE_MEMORY_CHUNK
struct m68k_mem_info *info = m68k_memory + node;
In this way i can boot again with mmu enabled.
>
> Regards,
> Angelo
mcf5441x, mmu boot not working anymore
Hi all, resending this in the proper mailing (sent to lkml for error). Just rebased to master right now, so @ > 5.1.1, nommu boot works, mmu boot hangs without any message. Before rebase i was near 5.1-rc1 but lost the log, unfortunately. I am booting linux passing a ramfs address of a ramfs loaded in memory from u-boot. After some investigations, just found this: - without passing the ramfs, kernel boots. - with ramfs, adding some low level traces, i get: 5Linux version 5.1.0stmark2-001-09826-gd881126bf3f8-dirty (angelo@box) (gcc version 5.2.0 (crosstools-sysam-2016.04.16)) #221 Sun May 12 00:31:57 CEST 2019 initrd at 0x47d33000:0x47d85e44 overlap at 1073741889 for chunk 0 overlap at 1073746160 for chunk 0 overlap at 1073746719 for chunk 0 overlap at 1073746720 for chunk 0 overlap at 1073746721 for chunk 0 overlap at 1073746722 for chunk 0 Regards, Angelo
Re: endianness swapped
Hi, looks like the reason of my ioread32be now swapped is: https://patchwork.kernel.org/patch/10766673/ Trying to figure out what to do now. Thanks anyway Regards Angelo On Sat, Apr 27, 2019 at 05:32:22PM +0200, Angelo Dureghello wrote: > Hi all, > > as you may know, i am working on mcf5441x. > Sorry for not following carefully all the threads, but from a certain > kernel version (likely 4.19 or near there), seems ioread32be > reads the bytes swapped in endianness (mcf-edma dma driver not working > anymore). > > Has there been a change about this in the architecture I/O access ? > How should i proceed now ? Fixing the DMA driver read/write, or what ? > > Thanks, > Angelo
endianness swapped
Hi all, as you may know, i am working on mcf5441x. Sorry for not following carefully all the threads, but from a certain kernel version (likely 4.19 or near there), seems ioread32be reads the bytes swapped in endianness (mcf-edma dma driver not working anymore). Has there been a change about this in the architecture I/O access ? How should i proceed now ? Fixing the DMA driver read/write, or what ? Thanks, Angelo
Re: [PATCH] m68k: add ColdFire mcf5441x eDMA platform support
Hi Greg,
On Tue, Feb 05, 2019 at 11:34:34AM +1000, Greg Ungerer wrote:
> Hi Angelo,
>
> On 5/2/19 1:53 am, Angelo Dureghello wrote:
> [snip]
> > Many thanks.
> >
> > I think i found an additional non-functional fix is needed:
> >
> > arch/m68k/coldfire/device.c line 546, edma "id" should be 0 and not 6.
> >
> > Fixed and tested here, let me know if you can do that too, or i can send
> > a v2, as you prefer, not a problem.
>
> No problem, I have fixed and re-pushed to m68knommu git tree for-next branch.
> Just to double check, the change was this:
>
> --- /tmp/device.c 2019-02-05 11:30:00.875259680 +1000
> +++ /home/gerg/src/linux/git/m68knommu/arch/m68k/coldfire/device.c
> 2019-02-05 11:32:38.248684394 +1000
> @@ -542,7 +542,7 @@
> static struct platform_device mcf_edma = {
> .name = "mcf-edma",
> - .id = 6,
> + .id = 0,
> .num_resources = ARRAY_SIZE(mcf_edma_resources),
> .resource = mcf_edma_resources,
> .dev = {
>
>
Thanks, perfect, very kind.
> Regards
> Greg
>
Regards,
Angelo
Re: [PATCH] m68k: add ColdFire mcf5441x eDMA platform support
Hi Greg,
On Wed, Jan 30, 2019 at 04:21:11PM +1000, Greg Ungerer wrote:
> Hi Angelo,
>
> On 20/1/19 6:14 am, Angelo Dureghello wrote:
> > This patch adds support for ColdFire eDMA platform driver.
>
> Just a couple of minor formatting things.
>
>
> > Signed-off-by: Angelo Dureghello
> > ---
> > arch/m68k/coldfire/device.c | 81 +++
> > arch/m68k/coldfire/m5441x.c | 4 +-
> > arch/m68k/include/asm/m5441xsim.h | 15 ++
> > 3 files changed, 98 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
> > index 908d58347790..b5d73c60d547 100644
> > --- a/arch/m68k/coldfire/device.c
> > +++ b/arch/m68k/coldfire/device.c
> > @@ -14,11 +14,14 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > /*
> >*All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
> > @@ -476,6 +479,81 @@ static struct platform_device mcf_i2c5 = {
> > #endif /* MCFI2C_BASE5 */
> > #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
> > +#if IS_ENABLED(CONFIG_MCF_EDMA)
> > +
> > +static const struct dma_slave_map mcf_edma_map[] = {
> > + { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
> > + { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
> > + { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
> > + { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
> > + { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
> > + { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
> > + { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
> > + { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
> > + { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
> > + { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
> > + { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
> > + { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
> > + { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
> > + { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
> > + { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
> > + { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
> > +};
> > +
> > +static struct mcf_edma_platform_data mcf_edma_data = {
> > + .dma_channels = 64,
> > + .slave_map = mcf_edma_map,
> > + .slavecnt = ARRAY_SIZE(mcf_edma_map),
> > +};
> > +
> > +static struct resource mcf_edma_resources[] = {
> > + {
> > + .start = MCFEDMA_BASE,
> > + .end= MCFEDMA_BASE + MCFEDMA_SIZE - 1,
> > + .flags = IORESOURCE_MEM,
> > + },
> > + {
> > + .start = MCFEDMA_IRQ_INTR0,
> > + .end= MCFEDMA_IRQ_INTR0 + 15,
> > + .flags = IORESOURCE_IRQ,
> > + .name = "edma-tx-00-15",
> > + },
> > + {
> > + .start = MCFEDMA_IRQ_INTR16,
> > + .end= MCFEDMA_IRQ_INTR16 + 39,
> > + .flags = IORESOURCE_IRQ,
> > + .name = "edma-tx-16-55",
> > + },
> > + {
> > + .start = MCFEDMA_IRQ_INTR56,
> > + .end= MCFEDMA_IRQ_INTR56,
> > + .flags = IORESOURCE_IRQ,
> > + .name = "edma-tx-56-63",
> > + },
> > + {
> > + .start = MCFEDMA_IRQ_ERR,
> > + .end= MCFEDMA_IRQ_ERR,
> > + .flags = IORESOURCE_IRQ,
> > + .name = "edma-err",
> > + },
> > +};
> > +
> > +static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
> > +
> > +static struct platform_device mcf_edma = {
> > + .name = "mcf-edma",
> > + .id = 6,
> > + .num_resources = ARRAY_SIZE(mcf_edma_resources),
> > + .resource = mcf_edma_resources,
> > + .dev = {
> > + .dma_mask = _edma_dmamask,
> > + .coherent_dma_mask = DMA_BIT_MASK(32),
> > +
[PATCH] m68k: add ColdFire mcf5441x eDMA platform support
This patch adds support for ColdFire eDMA platform driver.
Signed-off-by: Angelo Dureghello
---
arch/m68k/coldfire/device.c | 81 +++
arch/m68k/coldfire/m5441x.c | 4 +-
arch/m68k/include/asm/m5441xsim.h | 15 ++
3 files changed, 98 insertions(+), 2 deletions(-)
diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
index 908d58347790..b5d73c60d547 100644
--- a/arch/m68k/coldfire/device.c
+++ b/arch/m68k/coldfire/device.c
@@ -14,11 +14,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
+#include
/*
* All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
@@ -476,6 +479,81 @@ static struct platform_device mcf_i2c5 = {
#endif /* MCFI2C_BASE5 */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
+#if IS_ENABLED(CONFIG_MCF_EDMA)
+
+static const struct dma_slave_map mcf_edma_map[] = {
+ { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
+ { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
+ { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
+ { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
+ { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
+ { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
+ { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
+ { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
+ { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
+ { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
+ { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
+ { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
+ { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
+ { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
+ { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
+ { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
+};
+
+static struct mcf_edma_platform_data mcf_edma_data = {
+ .dma_channels = 64,
+ .slave_map = mcf_edma_map,
+ .slavecnt = ARRAY_SIZE(mcf_edma_map),
+};
+
+static struct resource mcf_edma_resources[] = {
+ {
+ .start = MCFEDMA_BASE,
+ .end= MCFEDMA_BASE + MCFEDMA_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MCFEDMA_IRQ_INTR0,
+ .end= MCFEDMA_IRQ_INTR0 + 15,
+ .flags = IORESOURCE_IRQ,
+ .name = "edma-tx-00-15",
+ },
+ {
+ .start = MCFEDMA_IRQ_INTR16,
+ .end= MCFEDMA_IRQ_INTR16 + 39,
+ .flags = IORESOURCE_IRQ,
+ .name = "edma-tx-16-55",
+ },
+ {
+ .start = MCFEDMA_IRQ_INTR56,
+ .end= MCFEDMA_IRQ_INTR56,
+ .flags = IORESOURCE_IRQ,
+ .name = "edma-tx-56-63",
+ },
+ {
+ .start = MCFEDMA_IRQ_ERR,
+ .end= MCFEDMA_IRQ_ERR,
+ .flags = IORESOURCE_IRQ,
+ .name = "edma-err",
+ },
+};
+
+static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device mcf_edma = {
+ .name = "mcf-edma",
+ .id = 6,
+ .num_resources = ARRAY_SIZE(mcf_edma_resources),
+ .resource = mcf_edma_resources,
+ .dev = {
+ .dma_mask = _edma_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = _edma_data,
+ }
+};
+
+#endif /* IS_ENABLED(CONFIG_MCF_EDMA) */
+
static struct platform_device *mcf_devices[] __initdata = {
_uart,
#if IS_ENABLED(CONFIG_FEC)
@@ -505,6 +583,9 @@ static struct platform_device *mcf_devices[] __initdata = {
_i2c5,
#endif
#endif
+#if IS_ENABLED(CONFIG_MCF_EDMA)
+ _edma,
+#endif
};
/*
diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c
index 55392af845fb..5bd24c9b865d 100644
--- a/arch/m68k/coldfire/m5441x.c
+++ b/arch/m68k/coldfire/m5441x.c
@@ -137,6 +137,8 @@ struct clk *mcf_clks[] = {
static struct clk * const enable_clks[] __initconst = {
/* make sure these clocks are enabled */
+ &__clk_0_15, /* dspi.1 */
+ &__clk_0_17, /* eDMA */
&__clk_0_18, /* intc0 */
&__clk_0_19, /* intc0 */
&__clk_0_20, /* intc0 */
@@ -157,8 +159,6 @@ static struct clk * const disable_clks[] __initconst = {
&__clk_0_8,
[PATCH v2] m68k: fix command-line parsing when passed from u-boot
This patch fixes command_line array zero-terminated one byte over the end of the array, causing boot to hang. Signed-off-by: Angelo Dureghello --- arch/m68k/kernel/uboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/m68k/kernel/uboot.c b/arch/m68k/kernel/uboot.c index b29c3b241e1b..107082877064 100644 --- a/arch/m68k/kernel/uboot.c +++ b/arch/m68k/kernel/uboot.c @@ -102,5 +102,5 @@ __init void process_uboot_commandline(char *commandp, int size) } parse_uboot_commandline(commandp, len); - commandp[size - 1] = 0; + commandp[len - 1] = 0; } -- 2.18.0
Re: [PATCH] m68k: fix command-line parsing when passed from u-boot
Hi Greg,
please drop this patch.
Issue is not related to additional spaces in the command
line, nor to init.data initializaitons.
It seems qiute hard to track down, issue disappears if i
just add some lines of code in uboot.c or setup.c.
Continuing on this.
Regards,
Angelo Dureghello
On Sat, Sep 01, 2018 at 03:16:21AM +0200, Angelo Dureghello wrote:
> Without MMU, when CONFIG_UBOOT is set, and CONFIG_BOOTPARAM
> is not set, a wrong command-line was produced (boot hangs,
> no console), due to an initial erroneus space appended to the
> command line in process_uboot_commandline().
>
> In MMU mode, the m68k_command_line array was not initially
> terminated to zero, and process_uboot_commandline() was still
> producing an invalid command-line (boot hangs, no console).
>
> Signed-off-by: Angelo Dureghello
> ---
> arch/m68k/kernel/setup_mm.c | 1 +
> arch/m68k/kernel/setup_no.c | 2 ++
> arch/m68k/kernel/uboot.c| 16 ++--
> 3 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c
> index 5d3596c180f9..8fc2999f11fe 100644
> --- a/arch/m68k/kernel/setup_mm.c
> +++ b/arch/m68k/kernel/setup_mm.c
> @@ -265,6 +265,7 @@ void __init setup_arch(char **cmdline_p)
> init_mm.end_data = (unsigned long)_edata;
> init_mm.brk = (unsigned long)_end;
>
> + m68k_command_line[0] = 0;
> #if defined(CONFIG_BOOTPARAM)
> strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE);
> m68k_command_line[CL_SIZE - 1] = 0;
> diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
> index cfd5475bfc31..d65bb433583c 100644
> --- a/arch/m68k/kernel/setup_no.c
> +++ b/arch/m68k/kernel/setup_no.c
> @@ -94,6 +94,8 @@ void __init setup_arch(char **cmdline_p)
> init_mm.end_data = (unsigned long) &_edata;
> init_mm.brk = (unsigned long) 0;
>
> + command_line[0] = 0;
> +
> config_BSP(_line[0], sizeof(command_line));
>
> #if defined(CONFIG_BOOTPARAM)
> diff --git a/arch/m68k/kernel/uboot.c b/arch/m68k/kernel/uboot.c
> index b29c3b241e1b..c4045bbe0a8c 100644
> --- a/arch/m68k/kernel/uboot.c
> +++ b/arch/m68k/kernel/uboot.c
> @@ -92,13 +92,17 @@ __init void process_uboot_commandline(char *commandp, int
> size)
> {
> int len, n;
>
> + len = size;
> +
> n = strnlen(commandp, size);
> - commandp += n;
> - len = size - n;
> - if (len) {
> - /* Add the whitespace separator */
> - *commandp++ = ' ';
> - len--;
> + if (n) {
> + commandp += n;
> + len -= n;
> + if (len) {
> + /* Add the whitespace separator */
> + *commandp++ = ' ';
> + len--;
> + }
> }
>
> parse_uboot_commandline(commandp, len);
> --
> 2.18.0
>
Re: [PATCH] m68k: fix command-line parsing when passed from u-boot
Hi Geert,
On Sat, Sep 01, 2018 at 09:23:42AM +0200, Geert Uytterhoeven wrote:
> Hi Angelo,
>
> On Sat, Sep 1, 2018 at 3:17 AM Angelo Dureghello wrote:
> > Without MMU, when CONFIG_UBOOT is set, and CONFIG_BOOTPARAM
> > is not set, a wrong command-line was produced (boot hangs,
> > no console), due to an initial erroneus space appended to the
> > command line in process_uboot_commandline().
> >
> > In MMU mode, the m68k_command_line array was not initially
> > terminated to zero, and process_uboot_commandline() was still
> > producing an invalid command-line (boot hangs, no console).
>
> It should be all zeroes?
>
> > --- a/arch/m68k/kernel/setup_mm.c
> > +++ b/arch/m68k/kernel/setup_mm.c
> > @@ -265,6 +265,7 @@ void __init setup_arch(char **cmdline_p)
> > init_mm.end_data = (unsigned long)_edata;
> > init_mm.brk = (unsigned long)_end;
> >
> > + m68k_command_line[0] = 0;
>
> This should not be needed:
>
> static char m68k_command_line[CL_SIZE] __initdata;
>
> I.e. m68k_command_line[] should be all zeroes.
>
> Is there a bug in the linker script?
>
Ops, right, but without the zero termination the final commandline
results invalid producing no console.
Investigating further so.
Just noticed some other initialization to 0 ...
void (*mach_sched_init) (irq_handler_t handler) __initdata = NULL;
/* machine dependent irq functions */
void (*mach_init_IRQ) (void) __initdata = NULL;
Noticed another strange thing, if i trace the commandline with
if (m68k_command_line[0] != 0)
pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n",
m68k_command_line[0],
m68k_command_line[1],
m68k_command_line[2],
m68k_command_line[3],
m68k_command_line[4],
m68k_command_line[5],
m68k_command_line[6],
m68k_command_line[7]);
#if defined(CONFIG_BOOTPARAM)
strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE);
...
Then i see all 00 and command line is set correctly and the
system boots. So it seems the fact i just refer to the array fixes
the things ...
> > #if defined(CONFIG_BOOTPARAM)
> > strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE);
> > m68k_command_line[CL_SIZE - 1] = 0;
> > diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
> > index cfd5475bfc31..d65bb433583c 100644
> > --- a/arch/m68k/kernel/setup_no.c
> > +++ b/arch/m68k/kernel/setup_no.c
> > @@ -94,6 +94,8 @@ void __init setup_arch(char **cmdline_p)
> > init_mm.end_data = (unsigned long) &_edata;
> > init_mm.brk = (unsigned long) 0;
> >
> > + command_line[0] = 0;
>
> Likewise:
>
> char __initdata command_line[COMMAND_LINE_SIZE];
>
I just added this for conformity with the above MMU case. But this issue
is only visible in the CONFIG_MMU.
> > +
> > config_BSP(_line[0], sizeof(command_line));
> >
> > #if defined(CONFIG_BOOTPARAM)
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH] m68k: fix command-line parsing when passed from u-boot
Without MMU, when CONFIG_UBOOT is set, and CONFIG_BOOTPARAM
is not set, a wrong command-line was produced (boot hangs,
no console), due to an initial erroneus space appended to the
command line in process_uboot_commandline().
In MMU mode, the m68k_command_line array was not initially
terminated to zero, and process_uboot_commandline() was still
producing an invalid command-line (boot hangs, no console).
Signed-off-by: Angelo Dureghello
---
arch/m68k/kernel/setup_mm.c | 1 +
arch/m68k/kernel/setup_no.c | 2 ++
arch/m68k/kernel/uboot.c| 16 ++--
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c
index 5d3596c180f9..8fc2999f11fe 100644
--- a/arch/m68k/kernel/setup_mm.c
+++ b/arch/m68k/kernel/setup_mm.c
@@ -265,6 +265,7 @@ void __init setup_arch(char **cmdline_p)
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
+ m68k_command_line[0] = 0;
#if defined(CONFIG_BOOTPARAM)
strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE);
m68k_command_line[CL_SIZE - 1] = 0;
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index cfd5475bfc31..d65bb433583c 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -94,6 +94,8 @@ void __init setup_arch(char **cmdline_p)
init_mm.end_data = (unsigned long) &_edata;
init_mm.brk = (unsigned long) 0;
+ command_line[0] = 0;
+
config_BSP(_line[0], sizeof(command_line));
#if defined(CONFIG_BOOTPARAM)
diff --git a/arch/m68k/kernel/uboot.c b/arch/m68k/kernel/uboot.c
index b29c3b241e1b..c4045bbe0a8c 100644
--- a/arch/m68k/kernel/uboot.c
+++ b/arch/m68k/kernel/uboot.c
@@ -92,13 +92,17 @@ __init void process_uboot_commandline(char *commandp, int
size)
{
int len, n;
+ len = size;
+
n = strnlen(commandp, size);
- commandp += n;
- len = size - n;
- if (len) {
- /* Add the whitespace separator */
- *commandp++ = ' ';
- len--;
+ if (n) {
+ commandp += n;
+ len -= n;
+ if (len) {
+ /* Add the whitespace separator */
+ *commandp++ = ' ';
+ len--;
+ }
}
parse_uboot_commandline(commandp, len);
--
2.18.0
[PATCH v10 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/3).
Signed-off-by: Angelo Dureghello
Tested-by: Krzysztof Kozlowski
---
Changes for v8:
- patch rewritten from scratch, this patch (3/3) has just been added.
Changes for v9:
- add compile test for Kconfig,
- fix include guard.
Changes for v10:
- fix robot build "different size" cast,
- fix invalid usage of PTR_ERR.
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl-edma-common.c | 24 +-
drivers/dma/mcf-edma.c | 317 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
5 files changed, 387 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..45ca5e556774 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+ tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+ depends on M5441x || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 227034de256e..8ba80f4b6f55 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -46,8 +46,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan
*fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
- edma_writeb(fsl_chan->edma, ch, regs->serq);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
+ iowrite8(ch, regs->serq);
+ }
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
@@ -55,8 +63,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, regs->cerq);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(ch, regs->cerq);
+ iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
+ }
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..4d30d5302649
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_en
[PATCH v10 3/4] dmaengine: fsl-edma: fix macros
This patch fixes macros to use BIT() and GENMASK(), removing also some unneeded. Signed-off-by: Angelo Dureghello Tested-by: Krzysztof Kozlowski --- Changes for v9: - this patch (3/4) has just been added. Changes for v10: - none --- drivers/dma/fsl-edma-common.h | 50 +++ 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index b2ee89ea895a..a6f5b99ee95f 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -18,34 +18,28 @@ #define EDMA_CR_ECXBIT(16) #define EDMA_CR_CX BIT(17) -#define EDMA_SEEI_SEEI(x) ((x) & 0x1F) -#define EDMA_CEEI_CEEI(x) ((x) & 0x1F) -#define EDMA_CINT_CINT(x) ((x) & 0x1F) -#define EDMA_CERR_CERR(x) ((x) & 0x1F) - -#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) -#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) -#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) -#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) -#define EDMA_TCD_ATTR_SSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) -#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) -#define EDMA_TCD_ATTR_DSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) -#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) - -#define EDMA_TCD_SOFF_SOFF(x) (x) -#define EDMA_TCD_NBYTES_NBYTES(x) (x) -#define EDMA_TCD_SLAST_SLAST(x)(x) -#define EDMA_TCD_DADDR_DADDR(x)(x) -#define EDMA_TCD_CITER_CITER(x)((x) & 0x7FFF) -#define EDMA_TCD_DOFF_DOFF(x) (x) -#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x)(x) -#define EDMA_TCD_BITER_BITER(x)((x) & 0x7FFF) +#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) +#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) +#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) +#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) + +#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) +#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) +#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) +#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) +#define EDMA_TCD_ATTR_DSIZE_8BIT 0 +#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) +#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) +#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) +#define EDMA_TCD_ATTR_SSIZE_8BIT 0 +#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) + +#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0)) +#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0)) #define EDMA_TCD_CSR_START BIT(0) #define EDMA_TCD_CSR_INT_MAJOR BIT(1) -- 2.18.0
[PATCH v10 2/4] dmaengine: fsl-edma: add edma version and configurable registers
This patch adds configurable registers (using __iomem addresses)
to allow the use of fsl-edma-common code with slightly different
edma module versions, as Vybrid (v1) and ColdFire (v2) are.
Signed-off-by: Angelo Dureghello
Tested-by: Krzysztof Kozlowski
---
Changes for v8:
- patch rewritten from scratch, this patch (2/3) has just been added.
Changes for v9:
- comment syntax fixed,
- splitted macro changes away from this patch.
Changes for v10:
- none
---
drivers/dma/fsl-edma-common.c | 106 --
drivers/dma/fsl-edma-common.h | 62 ++--
drivers/dma/fsl-edma.c| 32 +-
3 files changed, 126 insertions(+), 74 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 3fc786b3d03c..227034de256e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -43,20 +43,20 @@
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
@@ -184,7 +184,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
{
struct fsl_edma_desc *edesc = fsl_chan->edesc;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
enum dma_transfer_direction dir = fsl_chan->fsc.dir;
dma_addr_t cur_addr, dma_addr;
@@ -200,11 +200,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
return len;
if (dir == DMA_MEM_TO_DEV)
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
else
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
/* figure out the finished and calculate the residue */
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
@@ -261,7 +259,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
/*
@@ -269,24 +267,24 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
* endian format. However, we need to load the TCD registers in
* big- or little-endian obeying the eDMA engine model endian.
*/
- edma_writew(edma, 0, addr + EDMA_TCD_CSR(ch));
- edma_writel(edma, le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR(ch));
- edma_writel(edma, le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR(ch));
+ edma_writew(edma, 0, >tcd[ch].csr);
+ edma_writel(edma, le32_to_cpu(tcd->saddr), >tcd[ch].saddr);
+ edma_writel(edma, le32_to_cpu(tcd->daddr), >tcd[ch].daddr);
- edma_writew(edma, le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR(ch));
- edma_writew(edma, le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF(ch));
+ edma_writew(edma, le16_to_cpu(tcd->attr), >tcd[ch].attr);
+ edma_writew(edma, le16_to_cpu(tcd->soff), >tcd[ch].soff);
- edma_writel(edma, le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES(ch));
- edma_writel(edma, le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST(ch));
+ edma_writel(edma, le32_to_cpu(tcd->nbytes), >tcd[ch].nbytes);
+ edma_writel(edma, le32_to_cpu(tcd->slast), >tcd[ch].slast);
- edma_writew(edma, le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER(ch));
- edma_writew(edma, le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER(ch));
-
[PATCH v10 1/4] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Signed-off-by: Angelo Dureghello
Tested-by: Krzysztof Kozlowski
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
Changes for v6:
- adjusted comment header
- fixed bit shift with BIT()
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
Changes for v7:
none
Changes for v8:
- patch rewritten from scratch, splitted into 3, common code isolated,
minimal changes from the original Freescale code have been done.
The patch has been tested with both Iris + Colibri Vybrid VF50 and
stmark2/mcf54415 Coldfire boards.
Changes for v9:
- changed small accessors (as edma_read/write functions) as inlined.
- changed licenses to GPL2.0+
Changes for v10:
- none
---
drivers/dma/Makefile | 2 +-
drivers/dma/fsl-edma-common.c | 552 +++
drivers/dma/fsl-edma-common.h | 241
drivers/dma/fsl-edma.c| 697 +-
4 files changed, 795 insertions(+), 697 deletions(-)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 203a99d68315..66022f59fca4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..3fc786b3d03c
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_SERQ 0x1B
+#define EDMA_CERQ 0x1A
+#define EDMA_SEEI 0x19
+#define EDMA_CEEI 0x18
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+
+static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+}
+
+void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+}
+EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
+
+void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
+ unsigned int slot, bool enable)
+{
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+ void __iomem *muxaddr;
+ unsigned int chans_per_mux, ch_off;
+
+ chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
+ ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+ muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
+ slot = EDMAMUX_CHCFG_SOURCE(slot);
+
+ if (enable)
+ iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off);
+ else
+ iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
+}
+EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
+
+static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
+{
+ switch (addr_width) {
+ case 1:
+
Re: [bug report] mmu not working anymore on mcf54415
Hi Mike, On Sun, Aug 19, 2018 at 06:42:36PM +0300, Mike Rapoport wrote: > On Sun, Aug 19, 2018 at 04:51:22PM +0200, angelo wrote: > > Hi Mike, > > > > On 19/08/2018 12:03, Mike Rapoport wrote: > > > On Sat, Aug 18, 2018 at 11:51:41PM +0200, Angelo Dureghello wrote: > > >> Hi, > > >> > > >> On Sat, Aug 18, 2018 at 11:45:51AM +0200, Angelo Dureghello wrote: > > >>> Hi all, > > >>> > > >>> i am testing kernel version 4.18.0 on mcf54415 with mmu > > >>> enabled, just noticed the boot stops silently at: > > >>> > > >>> [9.04] Freeing unused kernel memory: 336K > > >>> [9.04] This architecture does not have kernel memory protection. > > > Can you please send your kernel config and the entire boot log? > > > > > > > Thanks for looking into this. Files attached. > > > > As you can see from the config, my ramfs is embedded in the kernel. > > Actually not :) > > I've expected to see INITRAMFS_SOURCE there... > > > The kernel boot process seems to complete, but boot hangs at the moment the > > ramfs (in my case embedded in the kernel binary) should be loaded. > > Apparently, I've broken some early memory reservations. > > Can you test with this patch: > > > diff --git a/arch/m68k/mm/mcfmmu.c b/arch/m68k/mm/mcfmmu.c > index 70dde04..dae0a41 100644 > --- a/arch/m68k/mm/mcfmmu.c > +++ b/arch/m68k/mm/mcfmmu.c > @@ -172,7 +172,7 @@ void __init cf_bootmem_alloc(void) > high_memory = (void *)_ramend; > > /* Reserve kernel text/data/bss */ > - memblock_reserve(memstart, memstart - _rambase); > + memblock_reserve(_rambase, memstart - _rambase); > > m68k_virt_to_node_shift = fls(_ramend - 1) - 6; > module_fixup(NULL, __start_fixup, __stop_fixup); > Many thanks, the patch fixes the things. In the mcf5441x family memory starts at 0x4000 and not at 0 as in some other mmu Coldfire models. This probably made the issue visible in my board. Tested-by: Angelo Dureghello Regards, Angelo > > I am trying to understand something more. > > > > Regards, > > Angelo > > >>> Just after generally there is the initramfs load and the console prompt, > > >>> while actually nothing happen. > > >>> > > >>> Trying to collect more informations, > > >>> > > >> The commit that breaks mmu on mcf54415 is > > >> > > >> commit 1008a11590b966b469e60dc3756c9226a685ce12 (HEAD) > > >> Author: Mike Rapoport > > >> Date: Wed Jul 4 09:28:16 2018 +0300 > > >> > > >> m68k: switch to MEMBLOCK + NO_BOOTMEM > > >> > > >> Regards, > > >> Angelo Dureghello > > >> > > >>> Regards, > > >>> Angelo Dureghello > > >>> > > > > > U-Boot 2018.07-rc2-00041-g7b920e5579-dirty (Aug 12 2018 - 23:06:24 +0200) > > > > CPU: Freescale MCF54415 (Mask:a0 Version:2) > >CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz > >INP CLK 30 MHz VCO CLK 480 MHz > > SPI: ready > > DRAM: 128 MiB > > MMC: fsl_esdhc_init > > FSL_SDHC: 0 > > Loading Environment from SPI Flash... SF: Detected is25lp128 with page size > > 256 Bytes, erase size 64 KiB, total 16 MiB > > OK > > In:serial > > Out: serial > > Err: serial > > Hit any key to stop autoboot: 0 > > SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total > > 16 MiB > > device 0 offset 0x10, size 0x1ff6d0 > > SF: 2094800 bytes @ 0x10 Read: OK > > ## Booting kernel from Legacy Image at 40001000 ... > >Image Name: mainline kernel > >Created: 2018-08-19 8:55:20 UTC > >Image Type: M68K Linux Kernel Image (uncompressed) > >Data Size:2094736 Bytes = 2 MiB > >Load Address: 40001000 > >Entry Point: 40001000 > >Verifying Checksum ... OK > >Loading Kernel Image ... OK > > [0.00] Linux version > > 4.18.0-rc6stmark2-001-00013-g1008a11590b9-dirty (angelo@jerusalem) (gcc > > version 5.2.0 (crosstools-sysam-2016.04.16)) #58 Sun Aug 19 10:55:19 CEST > > 2018 > > [0.00] Built 1 zonelists, mobility grouping on. Total pages: 16312 > > [0.00] Kernel command line: console=ttyS0,115200 root=/dev/ram0 rw > > rootfstype=ramfs rdinit=/sbin/init devtmpfs.mount=1 > > [0.00] Dentry cache hash table entries: 16384 (order: 3, 65536 > > bytes) > &g
Re: [bug report] mmu not working anymore on mcf54415
Hi Mike, On 19/08/2018 12:03, Mike Rapoport wrote: > On Sat, Aug 18, 2018 at 11:51:41PM +0200, Angelo Dureghello wrote: >> Hi, >> >> On Sat, Aug 18, 2018 at 11:45:51AM +0200, Angelo Dureghello wrote: >>> Hi all, >>> >>> i am testing kernel version 4.18.0 on mcf54415 with mmu >>> enabled, just noticed the boot stops silently at: >>> >>> [9.04] Freeing unused kernel memory: 336K >>> [9.04] This architecture does not have kernel memory protection. > Can you please send your kernel config and the entire boot log? > Thanks for looking into this. Files attached. As you can see from the config, my ramfs is embedded in the kernel. The kernel boot process seems to complete, but boot hangs at the moment the ramfs (in my case embedded in the kernel binary) should be loaded. I am trying to understand something more. Regards, Angelo >>> Just after generally there is the initramfs load and the console prompt, >>> while actually nothing happen. >>> >>> Trying to collect more informations, >>> >> The commit that breaks mmu on mcf54415 is >> >> commit 1008a11590b966b469e60dc3756c9226a685ce12 (HEAD) >> Author: Mike Rapoport >> Date: Wed Jul 4 09:28:16 2018 +0300 >> >> m68k: switch to MEMBLOCK + NO_BOOTMEM >> >> Regards, >> Angelo Dureghello >> >>> Regards, >>> Angelo Dureghello >>> U-Boot 2018.07-rc2-00041-g7b920e5579-dirty (Aug 12 2018 - 23:06:24 +0200) CPU: Freescale MCF54415 (Mask:a0 Version:2) CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz INP CLK 30 MHz VCO CLK 480 MHz SPI: ready DRAM: 128 MiB MMC: fsl_esdhc_init FSL_SDHC: 0 Loading Environment from SPI Flash... SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB OK In:serial Out: serial Err: serial Hit any key to stop autoboot: 0 SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB device 0 offset 0x10, size 0x1ff6d0 SF: 2094800 bytes @ 0x10 Read: OK ## Booting kernel from Legacy Image at 40001000 ... Image Name: mainline kernel Created: 2018-08-19 8:55:20 UTC Image Type: M68K Linux Kernel Image (uncompressed) Data Size:2094736 Bytes = 2 MiB Load Address: 40001000 Entry Point: 40001000 Verifying Checksum ... OK Loading Kernel Image ... OK [0.00] Linux version 4.18.0-rc6stmark2-001-00013-g1008a11590b9-dirty (angelo@jerusalem) (gcc version 5.2.0 (crosstools-sysam-2016.04.16)) #58 Sun Aug 19 10:55:19 CEST 2018 [0.00] Built 1 zonelists, mobility grouping on. Total pages: 16312 [0.00] Kernel command line: console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/sbin/init devtmpfs.mount=1 [0.00] Dentry cache hash table entries: 16384 (order: 3, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 2, 32768 bytes) [0.00] Sorting __ex_table... [0.00] Memory: 128016K/131072K available (1299K kernel code, 102K rwdata, 304K rodata, 328K init, 208K bss, 3056K reserved, 0K cma-reserved) [0.00] SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=8 [0.00] NR_IRQS: 256 [0.00] clocksource: pit: mask: 0x max_cycles: 0x, max_idle_ns: 1019338904850 ns [0.00] Console: colour dummy device 80x25 [0.07] Calibrating delay loop... 238.38 BogoMIPS (lpj=1191936) [0.07] pid_max: default: 32768 minimum: 301 [0.07] Mount-cache hash table entries: 2048 (order: 0, 8192 bytes) [0.07] Mountpoint-cache hash table entries: 2048 (order: 0, 8192 bytes) [0.09] devtmpfs: initialized [0.13] random: get_random_u32 called from bucket_table_alloc+0x174/0x1a6 with crng_init=0 [0.13] clocksource: jiffies: mask: 0x max_cycles: 0x, max_idle_ns: 1911260446275 ns [0.13] futex hash table entries: 256 (order: -2, 3072 bytes) [0.20] clocksource: Switched to clocksource pit [0.20] FS-Cache: Loaded [0.93] workingset: timestamp_bits=27 max_order=14 bucket_order=0 [1.10] io scheduler noop registered [1.10] io scheduler deadline registered [1.10] io scheduler cfq registered (default) [1.10] io scheduler mq-deadline registered [1.10] io scheduler kyber registered [2.30] ColdFire internal UART serial driver [2.30] mcfuart.0: ttyS0 at MMIO 0xfc06 (irq = 90, base_baud = 750) is a ColdFire UART [2.50] console [ttyS0] enabled [2.51] mcfuart.0: ttyS1 at MMIO 0xfc064000 (irq = 91, base_baud = 750) is a ColdFire UART [2.52] mcfuart.0: ttyS2 at MMIO 0xfc068000 (irq = 92, base_baud = 750) is a ColdFire UART [2.53] mcfuart.0: ttyS3 at MMIO 0xfc06c000 (irq = 93, base_baud = 750) is a ColdFire UART
Re: [bug report] mmu not working anymore on mcf54415
Hi, On Sat, Aug 18, 2018 at 11:45:51AM +0200, Angelo Dureghello wrote: > Hi all, > > i am testing kernel version 4.18.0 on mcf54415 with mmu > enabled, just noticed the boot stops silently at: > > [9.04] Freeing unused kernel memory: 336K > [9.04] This architecture does not have kernel memory protection. > > Just after generally there is the initramfs load and the console prompt, > while actually nothing happen. > > Trying to collect more informations, > The commit that breaks mmu on mcf54415 is commit 1008a11590b966b469e60dc3756c9226a685ce12 (HEAD) Author: Mike Rapoport Date: Wed Jul 4 09:28:16 2018 +0300 m68k: switch to MEMBLOCK + NO_BOOTMEM Regards, Angelo Dureghello > Regards, > Angelo Dureghello >
[bug report] mmu not working anymore on mcf54415
Hi all, i am testing kernel version 4.18.0 on mcf54415 with mmu enabled, just noticed the boot stops silently at: [9.04] Freeing unused kernel memory: 336K [9.04] This architecture does not have kernel memory protection. Just after generally there is the initramfs load and the console prompt, while actually nothing happen. Trying to collect more informations, Regards, Angelo Dureghello
[PATCH v9 2/4] dmaengine: fsl-edma: add edma version and configurable registers
This patch adds configurable registers (using __iomem addresses)
to allow the use of fsl-edma-common code with slightly different
edma module versions, as Vybrid (v1) and ColdFire (v2) are.
Signed-off-by: Angelo Dureghello
---
Changes for v8:
- patch rewritten from scratch, this patch (2/3) has just been added.
Changes for v9:
- comment syntax fixed,
- splitted macro changes away from this patch.
---
drivers/dma/fsl-edma-common.c | 106 --
drivers/dma/fsl-edma-common.h | 62 ++--
drivers/dma/fsl-edma.c| 32 +-
3 files changed, 126 insertions(+), 74 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 3fc786b3d03c..227034de256e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -43,20 +43,20 @@
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
@@ -184,7 +184,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
{
struct fsl_edma_desc *edesc = fsl_chan->edesc;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
enum dma_transfer_direction dir = fsl_chan->fsc.dir;
dma_addr_t cur_addr, dma_addr;
@@ -200,11 +200,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
return len;
if (dir == DMA_MEM_TO_DEV)
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
else
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
/* figure out the finished and calculate the residue */
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
@@ -261,7 +259,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
/*
@@ -269,24 +267,24 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
* endian format. However, we need to load the TCD registers in
* big- or little-endian obeying the eDMA engine model endian.
*/
- edma_writew(edma, 0, addr + EDMA_TCD_CSR(ch));
- edma_writel(edma, le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR(ch));
- edma_writel(edma, le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR(ch));
+ edma_writew(edma, 0, >tcd[ch].csr);
+ edma_writel(edma, le32_to_cpu(tcd->saddr), >tcd[ch].saddr);
+ edma_writel(edma, le32_to_cpu(tcd->daddr), >tcd[ch].daddr);
- edma_writew(edma, le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR(ch));
- edma_writew(edma, le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF(ch));
+ edma_writew(edma, le16_to_cpu(tcd->attr), >tcd[ch].attr);
+ edma_writew(edma, le16_to_cpu(tcd->soff), >tcd[ch].soff);
- edma_writel(edma, le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES(ch));
- edma_writel(edma, le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST(ch));
+ edma_writel(edma, le32_to_cpu(tcd->nbytes), >tcd[ch].nbytes);
+ edma_writel(edma, le32_to_cpu(tcd->slast), >tcd[ch].slast);
- edma_writew(edma, le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER(ch));
- edma_writew(edma, le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER(ch));
- edma_writew(edma, le16_to_cpu(tcd->doff), addr + EDMA_
[PATCH v9 3/4] dmaengine: fsl-edma: fix macros
This patch fixes macros to use BIT() and GENMASK(), removing also some unneeded. Signed-off-by: Angelo Dureghello --- Changes for v9: - this patch (3/4) has just been added. --- drivers/dma/fsl-edma-common.h | 50 +++ 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index b2ee89ea895a..a6f5b99ee95f 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -18,34 +18,28 @@ #define EDMA_CR_ECXBIT(16) #define EDMA_CR_CX BIT(17) -#define EDMA_SEEI_SEEI(x) ((x) & 0x1F) -#define EDMA_CEEI_CEEI(x) ((x) & 0x1F) -#define EDMA_CINT_CINT(x) ((x) & 0x1F) -#define EDMA_CERR_CERR(x) ((x) & 0x1F) - -#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) -#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) -#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) -#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) -#define EDMA_TCD_ATTR_SSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) -#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) -#define EDMA_TCD_ATTR_DSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) -#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) - -#define EDMA_TCD_SOFF_SOFF(x) (x) -#define EDMA_TCD_NBYTES_NBYTES(x) (x) -#define EDMA_TCD_SLAST_SLAST(x)(x) -#define EDMA_TCD_DADDR_DADDR(x)(x) -#define EDMA_TCD_CITER_CITER(x)((x) & 0x7FFF) -#define EDMA_TCD_DOFF_DOFF(x) (x) -#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x)(x) -#define EDMA_TCD_BITER_BITER(x)((x) & 0x7FFF) +#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) +#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) +#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) +#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) + +#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) +#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) +#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) +#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) +#define EDMA_TCD_ATTR_DSIZE_8BIT 0 +#define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) +#define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) +#define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) +#define EDMA_TCD_ATTR_SSIZE_8BIT 0 +#define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) + +#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0)) +#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0)) #define EDMA_TCD_CSR_START BIT(0) #define EDMA_TCD_CSR_INT_MAJOR BIT(1) -- 2.18.0
[PATCH v9 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/3).
Signed-off-by: Angelo Dureghello
---
Changes for v8:
- patch rewritten from scratch, this patch (3/3) has just been added.
Changes for v9:
- add compile test for Kconfig,
- fix include guard.
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl-edma-common.c | 24 +-
drivers/dma/mcf-edma.c | 315 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
5 files changed, 385 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..45ca5e556774 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+ tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+ depends on M5441x || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 227034de256e..8ba80f4b6f55 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -46,8 +46,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan
*fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
- edma_writeb(fsl_chan->edma, ch, regs->serq);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
+ iowrite8(ch, regs->serq);
+ }
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
@@ -55,8 +63,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, regs->cerq);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(ch, regs->cerq);
+ iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
+ }
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..d4b2fd871ff4
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_
[PATCH v9 1/4] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
Changes for v6:
- adjusted comment header
- fixed bit shift with BIT()
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
Changes for v7:
none
Changes for v8:
- patch rewritten from scratch, splitted into 3, common code isolated,
minimal changes from the original Freescale code have been done.
The patch has been tested with both Iris + Colibri Vybrid VF50 and
stmark2/mcf54415 Coldfire boards.
Changes for v9:
- changed small accessors (as edma_read/write functions) as inlined.
- changed licenses to GPL2.0+
---
drivers/dma/Makefile | 2 +-
drivers/dma/fsl-edma-common.c | 552 +++
drivers/dma/fsl-edma-common.h | 241
drivers/dma/fsl-edma.c| 697 +-
4 files changed, 795 insertions(+), 697 deletions(-)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 203a99d68315..66022f59fca4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..3fc786b3d03c
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_SERQ 0x1B
+#define EDMA_CERQ 0x1A
+#define EDMA_SEEI 0x19
+#define EDMA_CEEI 0x18
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+
+static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+}
+
+void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+}
+EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
+
+void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
+ unsigned int slot, bool enable)
+{
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+ void __iomem *muxaddr;
+ unsigned int chans_per_mux, ch_off;
+
+ chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
+ ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+ muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
+ slot = EDMAMUX_CHCFG_SOURCE(slot);
+
+ if (enable)
+ iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off);
+ else
+ iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
+}
+EXPORT_SYMBOL_GPL(fsl_edma_chan_mux);
+
+static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
+{
+ switch (addr_width) {
+ case 1:
+ return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_T
Re: [PATCH v8 1/3] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Stefan, On Fri, Aug 10, 2018 at 10:05:06AM +0200, Stefan Agner wrote: > On 10.08.2018 00:37, Angelo Dureghello wrote: > > Hi Stefan, > > > > i am about to post a v9 in short. > > > > On Tue, Aug 07, 2018 at 07:47:19PM +0200, Stefan Agner wrote: > >> On 07.08.2018 14:14, Krzysztof Kozlowski wrote: > >> > On 7 August 2018 at 10:08, Stefan Agner wrote: > >> >> On 03.08.2018 21:32, Angelo Dureghello wrote: > >> >>> This patch adds a new fsl-edma-common module to allow new > >> >>> mcf-edma module code to use most of the fsl-edma code. > >> >>> > >> >>> Signed-off-by: Angelo Dureghello > >> >>> --- > >> >>> Changes for v2: > >> >>> - patch splitted into 4 > >> >>> - add mcf-edma as minimal different parts from fsl-edma > >> >>> > >> >>> Changes for v3: > >> >>> none > >> >>> > >> >>> Changes for v4: > >> >>> - patch simplified from 4/4 into 2/2 > >> >>> - collecting all the mcf-edma-related changes > >> >>> > >> >>> Changes for v5: > >> >>> none > >> >>> > >> >>> Changes for v6: > >> >>> - adjusted comment header > >> >>> - fixed bit shift with BIT() > >> >>> - we need to free the interrupts at remove(), so removed all devm_ > >> >>> interrupt related calls > >> >>> > >> >>> Changes for v7: > >> >>> none > >> >>> > >> >>> Changes for v8: > >> >>> - patch rewritten from scratch, splitted into 3, common code isolated, > >> >>> minimal changes from the original Freescale code have been done. > >> >>> The patch has been tested with both Iris + Colibri Vybrid VF50 and > >> >>> stmark2/mcf54415 Coldfire boards. > >> >>> --- > >> >>> drivers/dma/Makefile | 2 +- > >> >>> drivers/dma/fsl-edma-common.c | 576 > >> >>> drivers/dma/fsl-edma-common.h | 196 ++ > >> >>> drivers/dma/fsl-edma.c| 697 +- > >> >>> 4 files changed, 774 insertions(+), 697 deletions(-) > >> >>> create mode 100644 drivers/dma/fsl-edma-common.c > >> >>> create mode 100644 drivers/dma/fsl-edma-common.h > >> >>> > >> >>> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile > >> >>> index 203a99d68315..66022f59fca4 100644 > >> >>> --- a/drivers/dma/Makefile > >> >>> +++ b/drivers/dma/Makefile > >> >>> @@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ > >> >>> obj-$(CONFIG_DW_DMAC_CORE) += dw/ > >> >>> obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o > >> >>> obj-$(CONFIG_FSL_DMA) += fsldma.o > >> >>> -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o > >> >>> +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o > >> >>> obj-$(CONFIG_FSL_RAID) += fsl_raid.o > >> >>> obj-$(CONFIG_HSU_DMA) += hsu/ > >> >>> obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o > >> >>> diff --git a/drivers/dma/fsl-edma-common.c > >> >>> b/drivers/dma/fsl-edma-common.c > >> >>> new file mode 100644 > >> >>> index ..0ae7094f477a > >> >>> --- /dev/null > >> >>> +++ b/drivers/dma/fsl-edma-common.c > >> >>> @@ -0,0 +1,576 @@ > >> >>> +// SPDX-License-Identifier: GPL-2.0 > >> >>> +// > >> >>> +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc > >> >>> +// Copyright (c) 2017 Sysam, Angelo Dureghello > >> >>> + > >> >>> +#include > >> >>> +#include > >> >>> +#include > >> >>> + > >> >>> +#include "fsl-edma-common.h" > >> >>> + > >> >>> +/* > >> >>> + * R/W functions for big- or little-endian registers: > >> >>> + * The eDMA controller's endian is independent of the CPU core's > >> >>> endian. > >> >>> + * For the big-endian IP module, the offset for 8-bit or 16-bit > >> >>> regis
Re: [PATCH v8 1/3] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Stefan,
i am about to post a v9 in short.
On Tue, Aug 07, 2018 at 07:47:19PM +0200, Stefan Agner wrote:
> On 07.08.2018 14:14, Krzysztof Kozlowski wrote:
> > On 7 August 2018 at 10:08, Stefan Agner wrote:
> >> On 03.08.2018 21:32, Angelo Dureghello wrote:
> >>> This patch adds a new fsl-edma-common module to allow new
> >>> mcf-edma module code to use most of the fsl-edma code.
> >>>
> >>> Signed-off-by: Angelo Dureghello
> >>> ---
> >>> Changes for v2:
> >>> - patch splitted into 4
> >>> - add mcf-edma as minimal different parts from fsl-edma
> >>>
> >>> Changes for v3:
> >>> none
> >>>
> >>> Changes for v4:
> >>> - patch simplified from 4/4 into 2/2
> >>> - collecting all the mcf-edma-related changes
> >>>
> >>> Changes for v5:
> >>> none
> >>>
> >>> Changes for v6:
> >>> - adjusted comment header
> >>> - fixed bit shift with BIT()
> >>> - we need to free the interrupts at remove(), so removed all devm_
> >>> interrupt related calls
> >>>
> >>> Changes for v7:
> >>> none
> >>>
> >>> Changes for v8:
> >>> - patch rewritten from scratch, splitted into 3, common code isolated,
> >>> minimal changes from the original Freescale code have been done.
> >>> The patch has been tested with both Iris + Colibri Vybrid VF50 and
> >>> stmark2/mcf54415 Coldfire boards.
> >>> ---
> >>> drivers/dma/Makefile | 2 +-
> >>> drivers/dma/fsl-edma-common.c | 576
> >>> drivers/dma/fsl-edma-common.h | 196 ++
> >>> drivers/dma/fsl-edma.c| 697 +-
> >>> 4 files changed, 774 insertions(+), 697 deletions(-)
> >>> create mode 100644 drivers/dma/fsl-edma-common.c
> >>> create mode 100644 drivers/dma/fsl-edma-common.h
> >>>
> >>> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> >>> index 203a99d68315..66022f59fca4 100644
> >>> --- a/drivers/dma/Makefile
> >>> +++ b/drivers/dma/Makefile
> >>> @@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
> >>> obj-$(CONFIG_DW_DMAC_CORE) += dw/
> >>> obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
> >>> obj-$(CONFIG_FSL_DMA) += fsldma.o
> >>> -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
> >>> +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
> >>> obj-$(CONFIG_FSL_RAID) += fsl_raid.o
> >>> obj-$(CONFIG_HSU_DMA) += hsu/
> >>> obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
> >>> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> >>> new file mode 100644
> >>> index ..0ae7094f477a
> >>> --- /dev/null
> >>> +++ b/drivers/dma/fsl-edma-common.c
> >>> @@ -0,0 +1,576 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +//
> >>> +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
> >>> +// Copyright (c) 2017 Sysam, Angelo Dureghello
> >>> +
> >>> +#include
> >>> +#include
> >>> +#include
> >>> +
> >>> +#include "fsl-edma-common.h"
> >>> +
> >>> +/*
> >>> + * R/W functions for big- or little-endian registers:
> >>> + * The eDMA controller's endian is independent of the CPU core's endian.
> >>> + * For the big-endian IP module, the offset for 8-bit or 16-bit registers
> >>> + * should also be swapped opposite to that in little-endian IP.
> >>> + */
> >>> +u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
> >>> +{
> >>> + if (edma->big_endian)
> >>> + return ioread32be(addr);
> >>> + else
> >>> + return ioread32(addr);
> >>> +}
> >>> +EXPORT_SYMBOL_GPL(edma_readl);
> >>
> >> In 3/3 you link the common object into the two modules individually:
> >>
> >> obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
> >> obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
> >>
> >> Therefor you do not access those functions from another module (they are
> >> within the module). No exporting should be necessary. Drop all those
> >> exports.
> >
> > The fsl-edma-common wi
Re: [PATCH v8 1/3] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Krzysztof, On Mon, Aug 06, 2018 at 09:43:42AM +0200, Krzysztof Kozlowski wrote: > On 3 August 2018 at 21:32, Angelo Dureghello wrote: > > This patch adds a new fsl-edma-common module to allow new > > mcf-edma module code to use most of the fsl-edma code. > > > > Signed-off-by: Angelo Dureghello > > --- > > Changes for v2: > > - patch splitted into 4 > > - add mcf-edma as minimal different parts from fsl-edma > > > > Changes for v3: > > none > > > > Changes for v4: > > - patch simplified from 4/4 into 2/2 > > - collecting all the mcf-edma-related changes > > > > Changes for v5: > > none > > > > Changes for v6: > > - adjusted comment header > > - fixed bit shift with BIT() > > - we need to free the interrupts at remove(), so removed all devm_ > > interrupt related calls > > > > Changes for v7: > > none > > > > Changes for v8: > > - patch rewritten from scratch, splitted into 3, common code isolated, > > minimal changes from the original Freescale code have been done. > > The patch has been tested with both Iris + Colibri Vybrid VF50 and > > stmark2/mcf54415 Coldfire boards. > > --- > > drivers/dma/Makefile | 2 +- > > drivers/dma/fsl-edma-common.c | 576 > > drivers/dma/fsl-edma-common.h | 196 ++ > > drivers/dma/fsl-edma.c| 697 +- > > 4 files changed, 774 insertions(+), 697 deletions(-) > > create mode 100644 drivers/dma/fsl-edma-common.c > > create mode 100644 drivers/dma/fsl-edma-common.h > > > > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile > > index 203a99d68315..66022f59fca4 100644 > > --- a/drivers/dma/Makefile > > +++ b/drivers/dma/Makefile > > @@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ > > obj-$(CONFIG_DW_DMAC_CORE) += dw/ > > obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o > > obj-$(CONFIG_FSL_DMA) += fsldma.o > > -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o > > +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o > > obj-$(CONFIG_FSL_RAID) += fsl_raid.o > > obj-$(CONFIG_HSU_DMA) += hsu/ > > obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o > > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c > > new file mode 100644 > > index ..0ae7094f477a > > --- /dev/null > > +++ b/drivers/dma/fsl-edma-common.c > > @@ -0,0 +1,576 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > You moved code from fsl-edma.c which is licensed on GPL-2.0+. I think > that's not allowed as you effectively relicense the work on new > license. > Ok, so if i undestrand, i should change that comment to // SPDX-License-Identifier: GPL-2.0+ Right ? > Tested-by: Krzysztof Kozlowski > > Best regards, > Krzysztof > Best regards, Angelo > > +// > > +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc > > +// Copyright (c) 2017 Sysam, Angelo Dureghello > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 2/3] dmaengine: fsl-edma: add edma version and configurable registers
Hi Krzysztof,
many thanks for testing.
On Mon, Aug 06, 2018 at 09:59:35AM +0200, Krzysztof Kozlowski wrote:
> On 3 August 2018 at 21:32, Angelo Dureghello wrote:
> > This patch adds configurable registers (using __iomem addresses)
> > to allow the use of fsl-edma-common code with slightly different
> > edma module versions, as Vybrid (v1) and ColdFire (v2) are.
> >
> > Removal of old membase-referenced registers, amd some fixes on
> > macroes are included.
> >
> > Signed-off-by: Angelo Dureghello
> > ---
> > Changes from v7:
> > - patch rewritten from scratch, this patch (2/3) has just been added.
> > ---
> > drivers/dma/fsl-edma-common.c | 138 ++
> > drivers/dma/fsl-edma-common.h | 115 ++--
> > drivers/dma/fsl-edma.c| 32
> > 3 files changed, 182 insertions(+), 103 deletions(-)
> >
> > diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> > index 0ae7094f477a..948a3ee51bbb 100644
> > --- a/drivers/dma/fsl-edma-common.c
> > +++ b/drivers/dma/fsl-edma-common.c
> > @@ -9,6 +9,38 @@
> >
> > #include "fsl-edma-common.h"
> >
> > +#define EDMA_CR0x00
> > +#define EDMA_ES0x04
> > +#define EDMA_ERQ 0x0C
> > +#define EDMA_EEI 0x14
> > +#define EDMA_SERQ 0x1B
> > +#define EDMA_CERQ 0x1A
> > +#define EDMA_SEEI 0x19
> > +#define EDMA_CEEI 0x18
> > +#define EDMA_CINT 0x1F
> > +#define EDMA_CERR 0x1E
> > +#define EDMA_SSRT 0x1D
> > +#define EDMA_CDNE 0x1C
> > +#define EDMA_INTR 0x24
> > +#define EDMA_ERR 0x2C
> > +
> > +#define EDMA64_ERQH0x08
> > +#define EDMA64_EEIH0x10
> > +#define EDMA64_SERQ0x18
> > +#define EDMA64_CERQ0x19
> > +#define EDMA64_SEEI0x1a
> > +#define EDMA64_CEEI0x1b
> > +#define EDMA64_CINT0x1c
> > +#define EDMA64_CERR0x1d
> > +#define EDMA64_SSRT0x1e
> > +#define EDMA64_CDNE0x1f
> > +#define EDMA64_INTH0x20
> > +#define EDMA64_INTL0x24
> > +#define EDMA64_ERRH0x28
> > +#define EDMA64_ERRL0x2c
> > +
> > +#define EDMA_TCD 0x1000
> > +
> > /*
> > * R/W functions for big- or little-endian registers:
> > * The eDMA controller's endian is independent of the CPU core's endian.
> > @@ -67,20 +99,20 @@ EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
> >
> > static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
> > {
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> >
> > - edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
> > - edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
> > + edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
> > + edma_writeb(fsl_chan->edma, ch, regs->serq);
> > }
> >
> > void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
> > {
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> >
> > - edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
> > - edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
> > + edma_writeb(fsl_chan->edma, ch, regs->cerq);
> > + edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
> > }
> > EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
> >
> > @@ -208,7 +240,7 @@ static size_t fsl_edma_desc_residue(struct
> > fsl_edma_chan *fsl_chan,
> > struct virt_dma_desc *vdesc, bool in_progress)
> > {
> > struct fsl_edma_desc *edesc = fsl_chan->edesc;
> > - void __iomem *addr = fsl_chan->edma->membase;
> > + struct edma_regs *regs = _chan->edma->regs;
> > u32 ch = fsl_chan->vchan.chan.chan_id;
> > enum dma_transfer_direction dir = fsl_chan->fsc.dir;
> > dma_addr_t cur_addr, dma_addr;
> > @@ -224,11 +256,9 @@ static size_t fsl_edma_desc_residue(struct
> > fsl_edma_chan *fsl_chan,
>
Re: [PATCH v8 3/3] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
Hi Stefan, On Mon, Aug 06, 2018 at 02:21:52PM +0200, Stefan Agner wrote: > On 06.08.2018 10:09, Krzysztof Kozlowski wrote: > > On 3 August 2018 at 21:32, Angelo Dureghello wrote: > >> This patch adds support for ColdFire mcf5441x-family edma > >> module. > >> > >> The ColdFire edma module is slightly different from fsl-edma, > >> so a new driver is added. But most of the code is common > >> between fsl-edma and mcf-edma so it has been collected into a > >> separate common module fsl-edma-common (patch 1/3). > >> > >> Signed-off-by: Angelo Dureghello > [...] > >> diff --git a/include/linux/platform_data/dma-mcf-edma.h > >> b/include/linux/platform_data/dma-mcf-edma.h > >> new file mode 100644 > >> index ..9a1819acb28f > >> --- /dev/null > >> +++ b/include/linux/platform_data/dma-mcf-edma.h > >> @@ -0,0 +1,38 @@ > >> +/* SPDX-License-Identifier: GPL-2.0 */ > >> +/* > >> + * Freescale eDMA platform data, ColdFire SoC's family. > >> + * > >> + * Copyright (c) 2017 Angelo Dureghello > >> + * > >> + * This program is free software; you can redistribute it and/or modify > >> + * it under the terms of the GNU General Public License version 2 as > >> + * published by the Free Software Foundation. > >> + * > >> + * This program is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + */ > >> + > >> +#ifndef __MACH_MCF_EDMA_H__ > >> +#define __MACH_MCF_EDMA_H__ > > > > The guard should rather match current location, e.g. > > __LINUX_PLATFORM_DATA_MCF_EDMA_H__ > > > > Tested-by: Krzysztof Kozlowski > > > > So this revision fixed the issue we had seen with the previous version? > Do we know what it was exactly? > Well, no. I restarted completely the patch from scratch moving/changing the code carefully. I avoided changes to Freescale code as much as possible. > -- > Stefan > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html Regards, Angelo -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 3/3] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/3).
Signed-off-by: Angelo Dureghello
---
Changes for v7:
- patch rewritten from scratch, this patch (3/3) has just been added.
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl-edma-common.c | 24 +-
drivers/dma/mcf-edma.c | 315 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
5 files changed, 385 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..b45008e9c7e9 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+ tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+ depends on M5441x
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 948a3ee51bbb..5a830a238a0c 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -102,8 +102,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan
*fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
- edma_writeb(fsl_chan->edma, ch, regs->serq);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
+ iowrite8(ch, regs->serq);
+ }
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
@@ -111,8 +119,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan
*fsl_chan)
struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, regs->cerq);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ if (fsl_chan->edma->version == v1) {
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
+ } else {
+ /* ColdFire is big endian, and accesses natively
+* big endian I/O peripherals
+*/
+ iowrite8(ch, regs->cerq);
+ iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
+ }
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..31e5317a8f90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intm
[PATCH v8 2/3] dmaengine: fsl-edma: add edma version and configurable registers
This patch adds configurable registers (using __iomem addresses)
to allow the use of fsl-edma-common code with slightly different
edma module versions, as Vybrid (v1) and ColdFire (v2) are.
Removal of old membase-referenced registers, amd some fixes on
macroes are included.
Signed-off-by: Angelo Dureghello
---
Changes from v7:
- patch rewritten from scratch, this patch (2/3) has just been added.
---
drivers/dma/fsl-edma-common.c | 138 ++
drivers/dma/fsl-edma-common.h | 115 ++--
drivers/dma/fsl-edma.c| 32
3 files changed, 182 insertions(+), 103 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 0ae7094f477a..948a3ee51bbb 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -9,6 +9,38 @@
#include "fsl-edma-common.h"
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_SERQ 0x1B
+#define EDMA_CERQ 0x1A
+#define EDMA_SEEI 0x19
+#define EDMA_CEEI 0x18
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+
/*
* R/W functions for big- or little-endian registers:
* The eDMA controller's endian is independent of the CPU core's endian.
@@ -67,20 +99,20 @@ EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
+ edma_writeb(fsl_chan->edma, ch, regs->serq);
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
{
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
- edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
- edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+ edma_writeb(fsl_chan->edma, ch, regs->cerq);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
@@ -208,7 +240,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
{
struct fsl_edma_desc *edesc = fsl_chan->edesc;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
enum dma_transfer_direction dir = fsl_chan->fsc.dir;
dma_addr_t cur_addr, dma_addr;
@@ -224,11 +256,9 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan
*fsl_chan,
return len;
if (dir == DMA_MEM_TO_DEV)
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].saddr);
else
- cur_addr = edma_readl(
- fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
+ cur_addr = edma_readl(fsl_chan->edma, >tcd[ch].daddr);
/* figure out the finished and calculate the residue */
for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
@@ -285,7 +315,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
- void __iomem *addr = fsl_chan->edma->membase;
+ struct edma_regs *regs = _chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
/*
@@ -293,24 +323,24 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan
*fsl_chan,
* endian format. However, we need to load the TCD registers in
* big- or l
[PATCH v8 1/3] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
Changes for v6:
- adjusted comment header
- fixed bit shift with BIT()
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
Changes for v7:
none
Changes for v8:
- patch rewritten from scratch, splitted into 3, common code isolated,
minimal changes from the original Freescale code have been done.
The patch has been tested with both Iris + Colibri Vybrid VF50 and
stmark2/mcf54415 Coldfire boards.
---
drivers/dma/Makefile | 2 +-
drivers/dma/fsl-edma-common.c | 576
drivers/dma/fsl-edma-common.h | 196 ++
drivers/dma/fsl-edma.c| 697 +-
4 files changed, 774 insertions(+), 697 deletions(-)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 203a99d68315..66022f59fca4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..0ae7094f477a
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The eDMA controller's endian is independent of the CPU core's endian.
+ * For the big-endian IP module, the offset for 8-bit or 16-bit registers
+ * should also be swapped opposite to that in little-endian IP.
+ */
+u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
+{
+ if (edma->big_endian)
+ return ioread32be(addr);
+ else
+ return ioread32(addr);
+}
+EXPORT_SYMBOL_GPL(edma_readl);
+
+void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr)
+{
+ /* swap the reg offset for these in big-endian mode */
+ if (edma->big_endian)
+ iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
+ else
+ iowrite8(val, addr);
+}
+EXPORT_SYMBOL_GPL(edma_writeb);
+
+void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr)
+{
+ /* swap the reg offset for these in big-endian mode */
+ if (edma->big_endian)
+ iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
+ else
+ iowrite16(val, addr);
+}
+EXPORT_SYMBOL_GPL(edma_writew);
+
+void edma_writel(struct fsl_edma_engine *edma, u32 val, void __iomem *addr)
+{
+ if (edma->big_endian)
+ iowrite32be(val, addr);
+ else
+ iowrite32(val, addr);
+}
+EXPORT_SYMBOL_GPL(edma_writel);
+
+struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct fsl_edma_chan, vchan.chan);
+}
+EXPORT_SYMBOL_GPL(to_fsl_edma_chan);
+
+struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct fsl_edma_desc, vdesc);
+}
+EXPORT_SYMBOL_GPL(to_fsl_edma_desc);
+
+static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
+}
+
+void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
+{
+ void __iomem *addr = fsl_chan->edma->membase;
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+
+ edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
+ edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
+}
+EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
+
+void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
+ unsigned int slot, bool enable)
+{
+ u32 ch = fsl_chan->vchan.chan.chan_id;
+ void __iomem *muxaddr;
+ unsigned int chans_per_mux, ch_off;
+
+ chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
+ ch_off =
Re: [PATCH v7 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Vinod, On Tue, Jul 03, 2018 at 06:00:14PM +0530, Vinod wrote: > On 03-07-18, 12:37, Angelo Dureghello wrote: > > This patch adds a new fsl-edma-common module to allow new > > mcf-edma module code to use most of the fsl-edma code. > > > > Due to some differences between ColdFire edma (64 channels) and > > fsl-edma (32 channels), as register set offsets and some other > > points as the different interrupt organization and other minor > > things, a common module can collect most of the code for both > > 32 and 64 channel edma module versions. > > ?? > > You didn't see my email https://marc.info/?l=dmaengine=153060940829531=2 > Ops, missed it. No prob, new patch follow with the 2 fixes. Regards, Angelo > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/2).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
Changes for v6:
- adjusted comment header
- fixed bit shift with BIT()
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
Changes for v7:
none
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/mcf-edma.c | 315 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
4 files changed, 365 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..23f444608514 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+depends on M5441x
+select DMA_ENGINE
+select DMA_VIRTUAL_CHANNELS
+help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..31e5317a8f90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & BIT(ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch;
+
+ err = ioread32(regs->errl);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
+ if (err & BIT(ch)) {
+
[PATCH v7 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Due to some differences between ColdFire edma (64 channels) and
fsl-edma (32 channels), as register set offsets and some other
points as the different interrupt organization and other minor
things, a common module can collect most of the code for both
32 and 64 channel edma module versions.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add fsl-edma-common module
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the fsl-edma-related changes
Changes for v5:
- add EXPORT_SYMBOL_GPL for all common functions
Changes for v6:
- adjusted comment header
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
Changes for v7:
- fix sparse errors
- fix additional space in header file end
---
drivers/dma/Makefile | 2 +-
drivers/dma/fsl-edma-common.c | 670 ++
drivers/dma/fsl-edma-common.h | 161
drivers/dma/fsl-edma.c| 753 ++
4 files changed, 870 insertions(+), 716 deletions(-)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 203a99d68315..66022f59fca4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..72e52c1b5527
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_CEEI 0x18
+#define EDMA_SEEI 0x19
+#define EDMA_CERQ 0x1A
+#define EDMA_SERQ 0x1B
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+#define EDMA_TCD_SIZE 32
+#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE
+
+#define EDMA_TCD_ATTR_SSIZE_8BIT 0
+#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0)
+#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1)
+#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0))
+#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2)
+#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0))
+#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8)
+
+#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0))
+#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0))
+
+#define EDMA_TCD_CSR_START BIT(0)
+#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
+#define EDMA_TCD_CSR_INT_HALF BIT(2)
+#define EDMA_TCD_CSR_D_REQ BIT(3)
+#define EDMA_TCD_CSR_E_SG BIT(4)
+#define EDMA_TCD_CSR_E_LINKBIT(5)
+#define EDMA_TCD_CSR_ACTIVEBIT(6)
+#define EDMA_TCD_CSR_DONE BIT(7)
+
+struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct fsl_edma_chan, vchan.chan);
+}
+EXPORT_SYMBOL_GPL(to_fsl_edma_chan);
+
+struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
+{
+
Re: [PATCH v6 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Vinod, many thanks ! On Tue, Jul 03, 2018 at 11:19:25AM +0530, Vinod wrote: > On 01-07-18, 18:33, Angelo Dureghello wrote: > > This patch adds a new fsl-edma-common module to allow new > > mcf-edma module code to use most of the fsl-edma code. > > > > Due to some differences between ColdFire edma (64 channels) and > > fsl-edma (32 channels), as register set offsets and some other > > points as the different interrupt organization and other minor > > things, a common module can collect most of the code for both > > 32 and 64 channel edma module versions. > > I have applied these, thanks. > > While applying I saw a trailing whitespace error, have fixed that up as > below. > Strange checkpatch.pl is not signalling it .. > Also, I saw sparse complain a lot, care to fix those too? > Sure. Can send a new version soon. Regards, Angelo > -->8 > > commit 15efb0b488596a929bc00ce23aeb746ee6a7c14d > Author: Vinod Koul > Date: Tue Jul 3 11:16:46 2018 +0530 > > dmaengine: fsl-edma: fix trailing whitespace > > Signed-off-by: Vinod Koul > > diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h > index e87c2bec882b..8e3c609c62fa 100644 > --- a/drivers/dma/fsl-edma-common.h > +++ b/drivers/dma/fsl-edma-common.h > @@ -159,4 +159,3 @@ int fsl_edma_terminate_all(struct dma_chan *chan); > void fsl_edma_issue_pending(struct dma_chan *chan); > > #endif /* _FSL_EDMA_COMMON_H_ */ > - > > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Due to some differences between ColdFire edma (64 channels) and
fsl-edma (32 channels), as register set offsets and some other
points as the different interrupt organization and other minor
things, a common module can collect most of the code for both
32 and 64 channel edma module versions.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add fsl-edma-common module
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the fsl-edma-related changes
Changes for v5:
- add EXPORT_SYMBOL_GPL for all common functions
Changes for v6:
- adjusted comment header
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
---
drivers/dma/Makefile | 2 +-
drivers/dma/fsl-edma-common.c | 670 ++
drivers/dma/fsl-edma-common.h | 162
drivers/dma/fsl-edma.c| 753 ++
4 files changed, 871 insertions(+), 716 deletions(-)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 203a99d68315..66022f59fca4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
-obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
+obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..17d677bd11f9
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_CEEI 0x18
+#define EDMA_SEEI 0x19
+#define EDMA_CERQ 0x1A
+#define EDMA_SERQ 0x1B
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+#define EDMA_TCD_SIZE 32
+#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE
+
+#define EDMA_TCD_ATTR_SSIZE_8BIT 0
+#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0)
+#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1)
+#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0))
+#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2)
+#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0))
+#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8)
+
+#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0))
+#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0))
+
+#define EDMA_TCD_CSR_START BIT(0)
+#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
+#define EDMA_TCD_CSR_INT_HALF BIT(2)
+#define EDMA_TCD_CSR_D_REQ BIT(3)
+#define EDMA_TCD_CSR_E_SG BIT(4)
+#define EDMA_TCD_CSR_E_LINKBIT(5)
+#define EDMA_TCD_CSR_ACTIVEBIT(6)
+#define EDMA_TCD_CSR_DONE BIT(7)
+
+struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct fsl_edma_chan, vchan.chan);
+}
+EXPORT_SYMBOL_GPL(to_fsl_edma_chan);
+
+struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct fsl_edma_desc, vdesc);
+}
+EXPORT_SYMBOL_GPL(to_fsl_edma_de
[PATCH v6 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/2).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
Changes for v6:
- adjusted comment header
- fixed bit shift with BIT()
- we need to free the interrupts at remove(), so removed all devm_
interrupt related calls
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/mcf-edma.c | 315 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
4 files changed, 365 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..23f444608514 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+depends on M5441x
+select DMA_ENGINE
+select DMA_VIRTUAL_CHANNELS
+help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..31e5317a8f90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & BIT(ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch;
+
+ err = ioread32(regs->errl);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
+ if (err & BIT(ch)) {
+ fsl_edma_disable_request(_edma->chans
Re: [PATCH v5 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
Hi Vinod,
fixed mostly all, but sorry, i have still two questions before
proceeding,
On Thu, Jun 28, 2018 at 11:53:41AM +0530, Vinod wrote:
> On 22-06-18, 11:44, Angelo Dureghello wrote:
> > obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
> > obj-$(CONFIG_FSL_DMA) += fsldma.o
> > obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
> > +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
>
> that makes kernel have two copies of common.o one in thsi driver and one
> in previous one why not do:
>
> CONFIG_FSL_COMMON += fsl-edma-common.o
> CONFIG_FSL_EDMA += fsl-edma.o
> CONFIG_MCF_EDMA += mcf-edma.o
>
> and you select CONFIG_FSL_COMMON in both FSL and MCF Kconfig?
>
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
> > +// Copyright (c) 2017 Sysam, Angelo Dureghello
> > +/*
> > + * drivers/dma/mcf-edma.c
> > + *
> > + * Driver for the Freescale ColdFire 64-ch eDMA implementation,
> > + * derived from drivers/dma/fsl-edma.c.
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License as published by the
> > + * Free Software Foundation; either version 2 of the License, or (at your
> > + * option) any later version.
> > + */
>
> again, no need for text
>
It is not clear to me now how the initial header should be (i guess for
all the 3 c files at this point).
Do you want just something as :
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
// Copyright (c) 2017 Sysam, Angelo Dureghello
And nothing else ?
Majority of the files in the dma folder has also generally a line with
the file name and path, a brief driver explaination and the reduced GPL
licence text, and, as imx-sdma.c often copyrights at the end. So what is
the current rule ?
> > +static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
> > +{
> > + struct fsl_edma_engine *mcf_edma = dev_id;
> > + struct edma_regs *regs = _edma->regs;
> > + unsigned int ch;
> > + struct fsl_edma_chan *mcf_chan;
> > + u64 intmap;
> > +
> > + intmap = ioread32(regs->inth);
> > + intmap <<= 32;
> > + intmap |= ioread32(regs->intl);
> > + if (!intmap)
> > + return IRQ_NONE;
> > +
> > + for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> > + if (intmap & (0x1 << ch)) {
>
> intmap & BIT(ch)
>
> > +static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
> > +{
> > + struct fsl_edma_engine *mcf_edma = dev_id;
> > + struct edma_regs *regs = _edma->regs;
> > + unsigned int err, ch;
> > +
> > + err = ioread32(regs->errl);
> > + if (!err)
> > + return IRQ_NONE;
> > +
> > + for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
> > + if (err & (0x1 << ch)) {
>
> here as well
>
> > +static int mcf_edma_remove(struct platform_device *pdev)
> > +{
> > + struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
> > +
> > + fsl_edma_cleanup_vchan(_edma->dma_dev);
> > + dma_async_device_unregister(_edma->dma_dev);
>
> at this point your irqs are still registered and running. You vchan
> tasklet maybe still pending to be eecuted and can be scheduled again
>
> > +static int __init mcf_edma_init(void)
> > +{
> > + return platform_driver_register(_edma_driver);
> > +}
> > +subsys_initcall(mcf_edma_init);
>
> why subsys_initcall?
>
I find subsys_initcall in several dma drivers, my understanding is that
it initializes the driver before other drivers can use it.
It also sets the driver as built in only.
This seems ok for my case.
Regards,
Angelo
> --
> ~Vinod
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Re: [PATCH v5 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
Hi Vinod and Geert, On Thu, Jun 28, 2018 at 04:39:13PM +0530, Vinod wrote: > On 28-06-18, 09:43, Geert Uytterhoeven wrote: > > Hi Vinod, > > > > On Thu, Jun 28, 2018 at 9:29 AM Vinod wrote: > > > On 28-06-18, 08:50, Geert Uytterhoeven wrote: > > > > On Thu, Jun 28, 2018 at 8:29 AM Vinod wrote: > > > > > On 22-06-18, 11:44, Angelo Dureghello wrote: > > > > > > obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o > > > > > > obj-$(CONFIG_FSL_DMA) += fsldma.o > > > > > > obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o > > > > > > +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o > > > > > > > > > > that makes kernel have two copies of common.o one in thsi driver and > > > > > one > > > > > > > > Does it? It's a common pattern in several Makefiles (e.g. > > > > drivers/net/ethernet/8390/Makefile and drivers/scsi/Makefile) > > > > > > won't each static symbol be part each one? > > > > Remember, obj-y is a list, and IIRC it's filtered for duplicates. > > > > > What about when they are modules? > > > > Same thing, you'll have fsl-edma-common.ko, and fsl-edma.ko and/or > > mcf-edma.ko. > > Yeah that is right, I missed the list part > Ok, so if i understand, i'll fix all the Vinod points except the Kconfig/makefile part that seems ok as is. Vinod, what do you think, am i near to a possible "accept" in a v6 or v7 ? Or do you see any additional great job to do or other important blocking points ? Thanks, regards, Angelo Dureghello > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 1/2).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
Changes for v5:
none
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/mcf-edma.c | 299 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
4 files changed, 349 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..23f444608514 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+depends on M5441x
+select DMA_ENGINE
+select DMA_VIRTUAL_CHANNELS
+help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..9e1d55a5cc90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/mcf-edma.c
+ *
+ * Driver for the Freescale ColdFire 64-ch eDMA implementation,
+ * derived from drivers/dma/fsl-edma.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & (0x1 << ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch
[PATCH v5 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new mcf-edma module code to use most of the fsl-edma code. Due to some differences between ColdFire edma (64 channels) and fsl-edma (32 channels), as register set offsets and some other points as the different interrupt organization and other minor things, a common module can collect most of the code for both 32 and 64 channel edma module versions. Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - add fsl-edma-common module Changes for v3: none Changes for v4: - patch simplified from 4/4 into 2/2 - collecting all the fsl-edma-related changes Changes for v5: - add EXPORT_SYMBOL_GPL for all common functions --- drivers/dma/Makefile | 2 +- drivers/dma/fsl-edma-common.c | 683 +++ drivers/dma/fsl-edma-common.h | 175 drivers/dma/fsl-edma.c| 739 ++ 4 files changed, 889 insertions(+), 710 deletions(-) create mode 100644 drivers/dma/fsl-edma-common.c create mode 100644 drivers/dma/fsl-edma-common.h diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 203a99d68315..66022f59fca4 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c new file mode 100644 index ..e3976fdb2752 --- /dev/null +++ b/drivers/dma/fsl-edma-common.c @@ -0,0 +1,683 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc +// Copyright (c) 2017 Sysam, Angelo Dureghello +/* + * drivers/dma/fsl-edma-common.c + * + * Common code for Freescale the edma 32 or 64 channel version. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "fsl-edma-common.h" + +#define EDMA_CR0x00 +#define EDMA_ES0x04 +#define EDMA_ERQ 0x0C +#define EDMA_EEI 0x14 +#define EDMA_CEEI 0x18 +#define EDMA_SEEI 0x19 +#define EDMA_CERQ 0x1A +#define EDMA_SERQ 0x1B +#define EDMA_CINT 0x1F +#define EDMA_CERR 0x1E +#define EDMA_SSRT 0x1D +#define EDMA_CDNE 0x1C +#define EDMA_INTR 0x24 +#define EDMA_ERR 0x2C + +#define EDMA64_ERQH0x08 +#define EDMA64_EEIH0x10 +#define EDMA64_SERQ0x18 +#define EDMA64_CERQ0x19 +#define EDMA64_SEEI0x1a +#define EDMA64_CEEI0x1b +#define EDMA64_CINT0x1c +#define EDMA64_CERR0x1d +#define EDMA64_SSRT0x1e +#define EDMA64_CDNE0x1f +#define EDMA64_INTH0x20 +#define EDMA64_INTL0x24 +#define EDMA64_ERRH0x28 +#define EDMA64_ERRL0x2c + +#define EDMA_TCD 0x1000 +#define EDMA_TCD_SIZE 32 +#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE + +#define EDMA_TCD_ATTR_SSIZE_8BIT 0 +#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0) +#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1) +#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0)) +#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0)) +#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8) + +#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0)) +#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0)) + +#define EDMA_TCD_CSR_START BIT(0) +#define EDMA_TCD_CSR_INT_MAJOR BIT(1) +#define EDMA_TCD_CSR_INT_HALF BIT(2) +#define EDMA_TCD_CSR_D_REQ BIT(3) +#define EDMA_TCD_CSR_E_SG BIT(4) +#define EDMA_TCD_CSR_E_LINK
Re: [PATCH v4 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
Hi Geert,
On Thu, Jun 21, 2018 at 08:31:31PM +0200, Geert Uytterhoeven wrote:
> On Thu, Jun 21, 2018 at 7:36 PM kbuild test robot wrote:
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on linus/master]
> > [also build test ERROR on v4.18-rc1 next-20180621]
> > [if your patch is applied to the wrong git tree, please drop us a note to
> > help improve the system]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Angelo-Dureghello/dmaengine-fsl-edma-extract-common-fsl-edma-code-no-changes-in-behavior-intended/20180620-035341
> > config: x86_64-randconfig-s3-06211901 (attached as .config)
> > compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
> > reproduce:
> > # save the attached .config to linux build tree
> > make ARCH=x86_64
> >
> > All errors (new ones prefixed by >>):
> >
> >WARNING: modpost: missing MODULE_LICENSE() in
> > drivers/dma/fsl-edma-common.o
> >see include/linux/module.h for more information
> > >> ERROR: "fsl_edma_issue_pending" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_terminate_all" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_resume" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_pause" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_slave_config" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_prep_dma_cyclic" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_prep_slave_sg" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_tx_status" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_free_chan_resources" [drivers/dma/fsl-edma.ko]
> > >> undefined!
> > >> ERROR: "fsl_edma_alloc_chan_resources" [drivers/dma/fsl-edma.ko]
> > >> undefined!
> > >> ERROR: "fsl_edma_free_desc" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_setup_regs" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_xfer_desc" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "edma_writeb" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "edma_readl" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "to_fsl_edma_chan" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_cleanup_vchan" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "edma_writel" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "edma_writew" [drivers/dma/fsl-edma.ko] undefined!
> > >> ERROR: "fsl_edma_disable_request" [drivers/dma/fsl-edma.ko] undefined!
>
> EXPORT_SYMBOL_GPL() missing for all exported symbols, breaking the modular
> case?
Yes, seems so. Thanks for following.
Fixing it.
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
Angelo
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
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[PATCH v4 2/2] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 2/4).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
Changes for v4:
- patch simplified from 4/4 into 2/2
- collecting all the mcf-edma-related changes
---
drivers/dma/Kconfig| 11 +
drivers/dma/Makefile | 1 +
drivers/dma/mcf-edma.c | 299 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
4 files changed, 349 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index ca1680afa20a..23f444608514 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -320,6 +320,17 @@ config LPC18XX_DMAMUX
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
+config MCF_EDMA
+tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
+depends on M5441x
+select DMA_ENGINE
+select DMA_VIRTUAL_CHANNELS
+help
+ Support the Freescale ColdFire eDMA engine, 64-channel
+ implementation that performs complex data transfers with
+ minimal intervention from a host processor.
+ This module can be found on Freescale ColdFire mcf5441x SoCs.
+
config MMP_PDMA
bool "MMP PDMA support"
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 66022f59fca4..d97f317f4b34 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
obj-$(CONFIG_HSU_DMA) += hsu/
obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..9e1d55a5cc90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/mcf-edma.c
+ *
+ * Driver for the Freescale ColdFire 64-ch eDMA implementation,
+ * derived from drivers/dma/fsl-edma.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & (0x1 << ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch;
+
+ err = ioread32
[PATCH v4 1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
This patch adds a new fsl-edma-common module to allow new mcf-edma module code to use most of the fsl-edma code. Due to some differences between ColdFire edma (64 channels) and fsl-edma (32 channels), as register set offsets and some other points as the different interrupt organization and other minor things, a common module can collect most of the code for both 32 and 64 channel edma module versions. Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - add fsl-edma-common module Changes for v3: none Changes for v4: - patch simplified from 4/4 into 2/2 - collecting all the fsl-edma-related changes --- drivers/dma/Makefile | 2 +- drivers/dma/fsl-edma-common.c | 662 ++ drivers/dma/fsl-edma-common.h | 175 drivers/dma/fsl-edma.c| 739 ++ 4 files changed, 868 insertions(+), 710 deletions(-) create mode 100644 drivers/dma/fsl-edma-common.c create mode 100644 drivers/dma/fsl-edma-common.h diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 203a99d68315..66022f59fca4 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -31,7 +31,7 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c new file mode 100644 index ..c205cb07f133 --- /dev/null +++ b/drivers/dma/fsl-edma-common.c @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2013-2014 Freescale Semiconductor, Inc +// Copyright (c) 2017 Sysam, Angelo Dureghello +/* + * drivers/dma/fsl-edma-common.c + * + * Common code for Freescale the edma 32 or 64 channel version. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "fsl-edma-common.h" + +#define EDMA_CR0x00 +#define EDMA_ES0x04 +#define EDMA_ERQ 0x0C +#define EDMA_EEI 0x14 +#define EDMA_CEEI 0x18 +#define EDMA_SEEI 0x19 +#define EDMA_CERQ 0x1A +#define EDMA_SERQ 0x1B +#define EDMA_CINT 0x1F +#define EDMA_CERR 0x1E +#define EDMA_SSRT 0x1D +#define EDMA_CDNE 0x1C +#define EDMA_INTR 0x24 +#define EDMA_ERR 0x2C + +#define EDMA64_ERQH0x08 +#define EDMA64_EEIH0x10 +#define EDMA64_SERQ0x18 +#define EDMA64_CERQ0x19 +#define EDMA64_SEEI0x1a +#define EDMA64_CEEI0x1b +#define EDMA64_CINT0x1c +#define EDMA64_CERR0x1d +#define EDMA64_SSRT0x1e +#define EDMA64_CDNE0x1f +#define EDMA64_INTH0x20 +#define EDMA64_INTL0x24 +#define EDMA64_ERRH0x28 +#define EDMA64_ERRL0x2c + +#define EDMA_TCD 0x1000 +#define EDMA_TCD_SIZE 32 +#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE + +#define EDMA_TCD_ATTR_SSIZE_8BIT 0 +#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0) +#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1) +#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0)) +#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2) +#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0)) +#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8) +#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8) +#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8) + +#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0)) +#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0)) + +#define EDMA_TCD_CSR_START BIT(0) +#define EDMA_TCD_CSR_INT_MAJOR BIT(1) +#define EDMA_TCD_CSR_INT_HALF BIT(2) +#define EDMA_TCD_CSR_D_REQ BIT(3) +#define EDMA_TCD_CSR_E_SG BIT(4) +#define EDMA_TCD_CSR_E_LINKBIT(5) +#define EDMA_TCD_CSR_ACTIVEBIT(6) +#define EDMA_TCD_CSR_DO
Re: mcf54415, mmu issues with last 4.18.0
Hi Greg, many thanks, Angelo On Tue, Jun 19, 2018 at 09:55:12AM +1000, Greg Ungerer wrote: > Hi Angelo, > > On 19/06/18 08:19, Angelo Dureghello wrote: > > after rebasing to master today, i am experiencing the following > > issue: > > > > [2.66] mcfuart.0: ttyS3 at MMIO 0xfc06c000 (irq = 93, base_baud = > > 750) is a ColdFire UART > > [2.70] m25p80 spi0.1: is25lp128 (16384 Kbytes) > > [2.71] Creating 3 MTD partitions on "is25lp128": > > [2.71] 0x-0x0010 : "U-Boot (1024K)" > > [2.73] 0x0010-0x0080 : "Kernel+initramfs (7168K)" > > [2.76] 0x0080-0x0100 : "Flash Free Space (8192K)" > > [2.79] Freeing unused kernel memory: 328K > > [2.80] This architecture does not have kernel memory protection. > > [2.97] BUG: Bad page state in process mount pfn:23dff > > [2.97] page:402f97dc count:0 mapcount:-1024 mapping: > > index:0x0 > > [2.97] flags: 0x0() > > [2.97] raw: 0100 0200 > > fbff > > [2.97] raw: 47bfe000 > > [2.97] page dumped because: nonzero mapcount > > See patch at: > > https://www.spinics.net/lists/linux-m68k/msg11810.html > > That fix may be improved yet, but it should fix this specific issue. > > Regards > Greg > > > > [2.97] CPU: 0 PID: 17 Comm: mount Not tainted > > 4.18.0-rc1stmark2-001-00030-g2a657c5c91d9 #721 > > [2.97] Stack from 47bf9de8: > > [2.97] 47bf9de8 401a1644 4003e154 402128a8 40302b74 > > 4003e176 4003e1c8 402f97dc > > [2.97] 40192255 0002 4003e450 402f97dc > > 082e > > [2.97] 0007bfc0 c000 c000 402f97b8 40302b74 > > 402f97e0 bfff 4005d0d4 > > [2.97] 47bf9f32 402729b4 402729b4 4003edbe 402128a8 > > 0003 40302b68 2000 > > [2.97] c000 402f97b8 47bfabfc bfff 4003f6ec > > 402f97b8 bfc0 47bf9f32 > > [2.97] 4005501a 402f97b8 40054e8c bffde000 > > 4005dddc 400591bc 47be1670 > > [2.97] Call Trace: [<4003e154>] bad_page+0xee/0x110 > > [2.97] [<4003e176>] free_pages_check_bad+0x0/0x5a > > [2.97] [<4003e1c8>] free_pages_check_bad+0x52/0x5a > > [2.97] [<4003e450>] free_pcppages_bulk+0x226/0x2aa > > [2.97] [<4005d0d4>] anon_vma_chain_free+0x0/0x14 > > [2.97] [<4003edbe>] free_unref_page_commit.isra.13+0x80/0x8e > > [2.97] [<4003f6ec>] free_unref_page+0x6e/0x78 > > [2.97] [<4005501a>] free_pgd_range+0x18e/0x1ac > > [2.97] [<40054e8c>] free_pgd_range+0x0/0x1ac > > [2.97] [<4005dddc>] unlink_anon_vmas+0x0/0x168 > > [2.97] [<400591bc>] unlink_file_vma+0x0/0x52 > > [2.97] [<4005dddc>] unlink_anon_vmas+0x0/0x168 > > [2.97] [<400591bc>] unlink_file_vma+0x0/0x52 > > [2.97] [<400550bc>] free_pgtables+0x84/0x94 > > [2.97] [<40151114>] down_read+0x0/0x6 > > [2.97] [<40021208>] up_read+0x0/0x6 > > [2.97] [<40058da8>] remove_vma+0x0/0x4c > > [2.97] [<4005a332>] exit_mmap+0xac/0x138 > > [2.97] [<40005e0a>] mmput+0x18/0x72 > > [2.97] [<40008efe>] do_exit+0x224/0x668 > > [2.97] [<4000935c>] sys_exit+0x0/0x14 > > [2.97] [<40085f84>] sys_mount+0x1a/0x20 > > [2.97] [<40009370>] do_group_exit+0x0/0x76 > > [2.97] [<40005190>] system_call+0x54/0x96 > > [2.97] Disabling lock debugging due to kernel taint > > > > And several seems equal issues just after. > > Btw, i can reach the prompt. > > Any idea of what could cause those oops ? > > > > Thanks, > > Angelo > > -- > > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > > the body of a message to majord...@vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
mcf54415, mmu issues with last 4.18.0
Dear all, after rebasing to master today, i am experiencing the following issue: [2.66] mcfuart.0: ttyS3 at MMIO 0xfc06c000 (irq = 93, base_baud = 750) is a ColdFire UART [2.70] m25p80 spi0.1: is25lp128 (16384 Kbytes) [2.71] Creating 3 MTD partitions on "is25lp128": [2.71] 0x-0x0010 : "U-Boot (1024K)" [2.73] 0x0010-0x0080 : "Kernel+initramfs (7168K)" [2.76] 0x0080-0x0100 : "Flash Free Space (8192K)" [2.79] Freeing unused kernel memory: 328K [2.80] This architecture does not have kernel memory protection. [2.97] BUG: Bad page state in process mount pfn:23dff [2.97] page:402f97dc count:0 mapcount:-1024 mapping: index:0x0 [2.97] flags: 0x0() [2.97] raw: 0100 0200 fbff [2.97] raw: 47bfe000 [2.97] page dumped because: nonzero mapcount [2.97] CPU: 0 PID: 17 Comm: mount Not tainted 4.18.0-rc1stmark2-001-00030-g2a657c5c91d9 #721 [2.97] Stack from 47bf9de8: [2.97] 47bf9de8 401a1644 4003e154 402128a8 40302b74 4003e176 4003e1c8 402f97dc [2.97] 40192255 0002 4003e450 402f97dc 082e [2.97] 0007bfc0 c000 c000 402f97b8 40302b74 402f97e0 bfff 4005d0d4 [2.97] 47bf9f32 402729b4 402729b4 4003edbe 402128a8 0003 40302b68 2000 [2.97] c000 402f97b8 47bfabfc bfff 4003f6ec 402f97b8 bfc0 47bf9f32 [2.97] 4005501a 402f97b8 40054e8c bffde000 4005dddc 400591bc 47be1670 [2.97] Call Trace: [<4003e154>] bad_page+0xee/0x110 [2.97] [<4003e176>] free_pages_check_bad+0x0/0x5a [2.97] [<4003e1c8>] free_pages_check_bad+0x52/0x5a [2.97] [<4003e450>] free_pcppages_bulk+0x226/0x2aa [2.97] [<4005d0d4>] anon_vma_chain_free+0x0/0x14 [2.97] [<4003edbe>] free_unref_page_commit.isra.13+0x80/0x8e [2.97] [<4003f6ec>] free_unref_page+0x6e/0x78 [2.97] [<4005501a>] free_pgd_range+0x18e/0x1ac [2.97] [<40054e8c>] free_pgd_range+0x0/0x1ac [2.97] [<4005dddc>] unlink_anon_vmas+0x0/0x168 [2.97] [<400591bc>] unlink_file_vma+0x0/0x52 [2.97] [<4005dddc>] unlink_anon_vmas+0x0/0x168 [2.97] [<400591bc>] unlink_file_vma+0x0/0x52 [2.97] [<400550bc>] free_pgtables+0x84/0x94 [2.97] [<40151114>] down_read+0x0/0x6 [2.97] [<40021208>] up_read+0x0/0x6 [2.97] [<40058da8>] remove_vma+0x0/0x4c [2.97] [<4005a332>] exit_mmap+0xac/0x138 [2.97] [<40005e0a>] mmput+0x18/0x72 [2.97] [<40008efe>] do_exit+0x224/0x668 [2.97] [<4000935c>] sys_exit+0x0/0x14 [2.97] [<40085f84>] sys_mount+0x1a/0x20 [2.97] [<40009370>] do_group_exit+0x0/0x76 [2.97] [<40005190>] system_call+0x54/0x96 [2.97] Disabling lock debugging due to kernel taint And several seems equal issues just after. Btw, i can reach the prompt. Any idea of what could cause those oops ? Thanks, Angelo -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/4] dmaengine: fsl-edma: remove all the edma common code
This patch simplify fsl-edma removing all the code that has been collected in a separated common module (see patch 2/4). Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - remove all the code gone into fsl-edma-common Changes for v3: none --- drivers/dma/fsl-edma.c | 739 ++--- 1 file changed, 30 insertions(+), 709 deletions(-) diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index c7568869284e..2f6e4a65d054 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -1,8 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2013-2014 Freescale Semiconductor, Inc. /* * drivers/dma/fsl-edma.c * - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * * Driver for the Freescale eDMA engine with flexible channel multiplexing * capability for DMA request sources. The eDMA block can be found on some * Vybrid and Layerscape SoCs. @@ -13,242 +13,20 @@ * option) any later version. */ -#include #include #include #include -#include -#include -#include -#include #include #include #include #include #include -#include "virt-dma.h" - -#define EDMA_CR0x00 -#define EDMA_ES0x04 -#define EDMA_ERQ 0x0C -#define EDMA_EEI 0x14 -#define EDMA_SERQ 0x1B -#define EDMA_CERQ 0x1A -#define EDMA_SEEI 0x19 -#define EDMA_CEEI 0x18 -#define EDMA_CINT 0x1F -#define EDMA_CERR 0x1E -#define EDMA_SSRT 0x1D -#define EDMA_CDNE 0x1C -#define EDMA_INTR 0x24 -#define EDMA_ERR 0x2C - -#define EDMA_TCD_SADDR(x) (0x1000 + 32 * (x)) -#define EDMA_TCD_SOFF(x) (0x1004 + 32 * (x)) -#define EDMA_TCD_ATTR(x) (0x1006 + 32 * (x)) -#define EDMA_TCD_NBYTES(x) (0x1008 + 32 * (x)) -#define EDMA_TCD_SLAST(x) (0x100C + 32 * (x)) -#define EDMA_TCD_DADDR(x) (0x1010 + 32 * (x)) -#define EDMA_TCD_DOFF(x) (0x1014 + 32 * (x)) -#define EDMA_TCD_CITER_ELINK(x)(0x1016 + 32 * (x)) -#define EDMA_TCD_CITER(x) (0x1016 + 32 * (x)) -#define EDMA_TCD_DLAST_SGA(x) (0x1018 + 32 * (x)) -#define EDMA_TCD_CSR(x)(0x101C + 32 * (x)) -#define EDMA_TCD_BITER_ELINK(x)(0x101E + 32 * (x)) -#define EDMA_TCD_BITER(x) (0x101E + 32 * (x)) - -#define EDMA_CR_EDBG BIT(1) -#define EDMA_CR_ERCA BIT(2) -#define EDMA_CR_ERGA BIT(3) -#define EDMA_CR_HOEBIT(4) -#define EDMA_CR_HALT BIT(5) -#define EDMA_CR_CLMBIT(6) -#define EDMA_CR_EMLM BIT(7) -#define EDMA_CR_ECXBIT(16) -#define EDMA_CR_CX BIT(17) - -#define EDMA_SEEI_SEEI(x) ((x) & 0x1F) -#define EDMA_CEEI_CEEI(x) ((x) & 0x1F) -#define EDMA_CINT_CINT(x) ((x) & 0x1F) -#define EDMA_CERR_CERR(x) ((x) & 0x1F) - -#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) -#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) -#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) -#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) -#define EDMA_TCD_ATTR_SSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) -#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) -#define EDMA_TCD_ATTR_DSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) -#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) - -#define EDMA_TCD_SOFF_SOFF(x) (x) -#define EDMA_TCD_NBYTES_NBYTES(x) (x) -#define EDMA_TCD_SLAST_SLAST(x)(x) -#define EDMA_TCD_DADDR_DADDR(x)(x) -#define EDMA_TCD_CITER_CITER(x)((x) & 0x7FFF) -#define EDMA_TCD_DOFF_DOFF(x) (x) -#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x)(x) -#define EDMA_TCD_BITER_BITER(x)((x) & 0x7FFF) - -#define EDMA_TCD_CSR_START BIT(0) -#define EDMA_TCD_CSR_INT_MAJOR BIT(1) -#define EDMA_TCD_CSR_INT_HALF BIT(2) -#define EDMA_TCD_CSR_D_REQ BIT(3) -#define EDMA_TCD_CSR_E_SG BIT(4) -#define EDMA_TCD_CSR_E_LINKBIT(5) -#define EDMA_TCD_CSR_ACTIVEBIT(6) -#define EDMA_TCD_CSR_DONE BIT(7) - -#define EDMAMUX_CHCFG_DIS 0x0 -#define EDMAMUX_CHCFG_ENBL 0x80 -#define EDMAMUX_CHCFG_SOURCE(n)((n) & 0x3F) - -#define DMAMUX_NR 2 - -#define FSL_EDMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_8
[PATCH v3 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 2/4).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
Changes for v3:
none
---
drivers/dma/mcf-edma.c | 299 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
2 files changed, 337 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..9e1d55a5cc90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/mcf-edma.c
+ *
+ * Driver for the Freescale ColdFire 64-ch eDMA implementation,
+ * derived from drivers/dma/fsl-edma.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & (0x1 << ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch;
+
+ err = ioread32(regs->errl);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
+ if (err & (0x1 << ch)) {
+ fsl_edma_disable_request(_edma->chans[ch]);
+ iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
+ mcf_edma->chans[ch].status = DMA_ERROR;
+ mcf_edma->chans[ch].idle = true;
+ }
+ }
+
+ err = ioread32(regs->errh);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
+ if (err & (0x1 << (ch - (EDMA_CHANNELS / 2 {
+ fsl_edma_disable_request(_edma->chans[ch]);
+ iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
+ mcf_edma->chans[ch].status = DMA_ERROR;
+ mcf_edma->chans[ch].idle = true;
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int mcf_edma_irq_init(struct platform_device *pdev,
+ struct fsl_edma_engine *mcf_edma)
+{
+ int ret = 0, i;
+ struct resource *res;
+
+ res = platform_get_resource_byname(pdev,
+ IORESOURCE_IRQ, "edma-tx-00-15");
+ if (!res)
+ return -1;
+
+ for (ret = 0, i = res->start; i <= res->end; ++i) {
+ ret |= devm_request_irq(>dev, i,
+ mcf_edma_tx_handler, 0, "eDMA", mcf_edm
[PATCH v3 2/4] dmaengine: fsl-edma: add fsl-edma-common
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Due to some differences between ColdFire edma (64 channels) and
fsl-edma (32 channels), as register set offsets and some other
points as the different interrupt organization and other minor
things, a common module can collect most of the code for both
32 and 64 channel edma module versions.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add fsl-edma-common module
Changes for v3:
none
---
drivers/dma/fsl-edma-common.c | 662 ++
drivers/dma/fsl-edma-common.h | 175 +
2 files changed, 837 insertions(+)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..c205cb07f133
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,662 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/fsl-edma-common.c
+ *
+ * Common code for Freescale the edma 32 or 64 channel version.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_CEEI 0x18
+#define EDMA_SEEI 0x19
+#define EDMA_CERQ 0x1A
+#define EDMA_SERQ 0x1B
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+#define EDMA_TCD_SIZE 32
+#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE
+
+#define EDMA_TCD_ATTR_SSIZE_8BIT 0
+#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0)
+#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1)
+#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0))
+#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2)
+#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0))
+#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8)
+
+#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0))
+#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0))
+
+#define EDMA_TCD_CSR_START BIT(0)
+#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
+#define EDMA_TCD_CSR_INT_HALF BIT(2)
+#define EDMA_TCD_CSR_D_REQ BIT(3)
+#define EDMA_TCD_CSR_E_SG BIT(4)
+#define EDMA_TCD_CSR_E_LINKBIT(5)
+#define EDMA_TCD_CSR_ACTIVEBIT(6)
+#define EDMA_TCD_CSR_DONE BIT(7)
+
+struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct fsl_edma_chan, vchan.chan);
+}
+
+struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct fsl_edma_desc, vdesc);
+}
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The eDMA controller's endian is independent of the CPU core's endian.
+ * For the big-endian IP module, the offset for 8-bit or 16-bit registers
+ * should also be swapped opposite to that in little-endian IP.
+ */
+u32 edma_readl(struct fsl_edma_engine *edma,
+ void __iomem *addr)
+{
+ if (edma->big_endian)
+ return ioread32be(addr);
+
[PATCH v3 1/4] dmaengine: fsl-edma: add config and makefile changes for mcf-edma
This patch adds Kconfig and makefile changes to add ColdFire mcf5441x family edma support. A new fsl-edma-common module has been added, to collect common code to fsl-edma. Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - add fsl-edma-common Changes for v3: - remove Kconfig FSL_EDMA_COMMON and set fsl-edma-common.o as additional object entry where needed. --- drivers/dma/Kconfig | 13 + drivers/dma/Makefile | 3 ++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 6d61cd023633..c7d45e69f021 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -220,6 +220,7 @@ config FSL_EDMA depends on OF select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select FSL_EDMA_COMMON help Support the Freescale eDMA engine with programmable channel multiplexing capability for DMA request sources(slot). @@ -327,6 +328,18 @@ config LPC18XX_DMAMUX Enable support for DMA on NXP LPC18xx/43xx platforms with PL080 and multiplexed DMA request lines. +config MCF_EDMA + tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs" + depends on M5441x + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select FSL_EDMA_COMMON + help + Support the Freescale ColdFire eDMA engine, 64-channel + implementation that performs complex data transfers with + minimal intervention from a host processor. + This module can be found on Freescale ColdFire mcf5441x SoCs. + config MMP_PDMA bool "MMP PDMA support" depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 0f62a4d49aab..cce5e3400580 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -32,7 +32,8 @@ obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o -obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o -- 2.17.0 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/4] dmaengine: fsl-edma: add config and makefile changes for mcf-edma
Hi Geert,
On Wed, Jun 06, 2018 at 09:21:33AM +0200, Geert Uytterhoeven wrote:
> Hi Angelo,
>
> On Tue, Jun 5, 2018 at 11:45 PM, Angelo Dureghello wrote:
> > This patch adds Kconfig and makefile changes to add ColdFire
> > mcf5441x family edma support.
> > A new fsl-edma-common module has been added, to collect common
> > code to fsl-edma.
> >
> > Signed-off-by: Angelo Dureghello
>
> Thanks for your patch!
>
> > --- a/drivers/dma/Kconfig
> > +++ b/drivers/dma/Kconfig
> > @@ -220,11 +220,17 @@ config FSL_EDMA
> > depends on OF
> > select DMA_ENGINE
> > select DMA_VIRTUAL_CHANNELS
> > + select FSL_EDMA_COMMON
> > help
> > Support the Freescale eDMA engine with programmable channel
> > multiplexing capability for DMA request sources(slot).
> > This module can be found on Freescale Vybrid and LS-1 SoCs.
> >
> > +config FSL_EDMA_COMMON
> > + bool
> > + depends on FSL_EDMA || MCF_EDMA
> > + default n
>
> If this symbol is used only for controlling the build of a source file, then
> you don't really need it...
>
> > +
> > config FSL_RAID
> > tristate "Freescale RAID engine Support"
> > depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
> > @@ -327,6 +333,18 @@ config LPC18XX_DMAMUX
> > Enable support for DMA on NXP LPC18xx/43xx platforms
> > with PL080 and multiplexed DMA request lines.
> >
> > +config MCF_EDMA
> > + tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
> > + depends on M5441x
> > + select DMA_ENGINE
> > + select DMA_VIRTUAL_CHANNELS
> > + select FSL_EDMA_COMMON
> > + help
> > + Support the Freescale ColdFire eDMA engine, 64-channel
> > + implementation that performs complex data transfers with
> > + minimal intervention from a host processor.
> > + This module can be found on Freescale ColdFire mcf5441x SoCs.
> > +
> > config MMP_PDMA
> > bool "MMP PDMA support"
> > depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
> > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> > index 0f62a4d49aab..823a590f308b 100644
> > --- a/drivers/dma/Makefile
> > +++ b/drivers/dma/Makefile
> > @@ -33,6 +33,8 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
> > obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
> > obj-$(CONFIG_FSL_DMA) += fsldma.o
> > obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
> > +obj-$(CONFIG_FSL_EDMA_COMMON) += fsl-edma-common.o
> > +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o
>
> ... as you can just write in the Makefile:
>
> obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
> obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
>
many thanks, will do that.
> > obj-$(CONFIG_FSL_RAID) += fsl_raid.o
> > obj-$(CONFIG_HSU_DMA) += hsu/
> > obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
Angelo
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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[PATCH v2 3/4] dmaengine: fsl-edma: remove all the edma common code
This patch simplify fsl-edma removing all the code that has been collected in a separated common module (see patch 2/4). Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - remove all the code gone into fsl-edma-common --- drivers/dma/fsl-edma.c | 739 ++--- 1 file changed, 30 insertions(+), 709 deletions(-) diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index c7568869284e..2f6e4a65d054 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -1,8 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright 2013-2014 Freescale Semiconductor, Inc. /* * drivers/dma/fsl-edma.c * - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * * Driver for the Freescale eDMA engine with flexible channel multiplexing * capability for DMA request sources. The eDMA block can be found on some * Vybrid and Layerscape SoCs. @@ -13,242 +13,20 @@ * option) any later version. */ -#include #include #include #include -#include -#include -#include -#include #include #include #include #include #include -#include "virt-dma.h" - -#define EDMA_CR0x00 -#define EDMA_ES0x04 -#define EDMA_ERQ 0x0C -#define EDMA_EEI 0x14 -#define EDMA_SERQ 0x1B -#define EDMA_CERQ 0x1A -#define EDMA_SEEI 0x19 -#define EDMA_CEEI 0x18 -#define EDMA_CINT 0x1F -#define EDMA_CERR 0x1E -#define EDMA_SSRT 0x1D -#define EDMA_CDNE 0x1C -#define EDMA_INTR 0x24 -#define EDMA_ERR 0x2C - -#define EDMA_TCD_SADDR(x) (0x1000 + 32 * (x)) -#define EDMA_TCD_SOFF(x) (0x1004 + 32 * (x)) -#define EDMA_TCD_ATTR(x) (0x1006 + 32 * (x)) -#define EDMA_TCD_NBYTES(x) (0x1008 + 32 * (x)) -#define EDMA_TCD_SLAST(x) (0x100C + 32 * (x)) -#define EDMA_TCD_DADDR(x) (0x1010 + 32 * (x)) -#define EDMA_TCD_DOFF(x) (0x1014 + 32 * (x)) -#define EDMA_TCD_CITER_ELINK(x)(0x1016 + 32 * (x)) -#define EDMA_TCD_CITER(x) (0x1016 + 32 * (x)) -#define EDMA_TCD_DLAST_SGA(x) (0x1018 + 32 * (x)) -#define EDMA_TCD_CSR(x)(0x101C + 32 * (x)) -#define EDMA_TCD_BITER_ELINK(x)(0x101E + 32 * (x)) -#define EDMA_TCD_BITER(x) (0x101E + 32 * (x)) - -#define EDMA_CR_EDBG BIT(1) -#define EDMA_CR_ERCA BIT(2) -#define EDMA_CR_ERGA BIT(3) -#define EDMA_CR_HOEBIT(4) -#define EDMA_CR_HALT BIT(5) -#define EDMA_CR_CLMBIT(6) -#define EDMA_CR_EMLM BIT(7) -#define EDMA_CR_ECXBIT(16) -#define EDMA_CR_CX BIT(17) - -#define EDMA_SEEI_SEEI(x) ((x) & 0x1F) -#define EDMA_CEEI_CEEI(x) ((x) & 0x1F) -#define EDMA_CINT_CINT(x) ((x) & 0x1F) -#define EDMA_CERR_CERR(x) ((x) & 0x1F) - -#define EDMA_TCD_ATTR_DSIZE(x) (((x) & 0x0007)) -#define EDMA_TCD_ATTR_DMOD(x) (((x) & 0x001F) << 3) -#define EDMA_TCD_ATTR_SSIZE(x) (((x) & 0x0007) << 8) -#define EDMA_TCD_ATTR_SMOD(x) (((x) & 0x001F) << 11) -#define EDMA_TCD_ATTR_SSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_SSIZE_16BIT (0x0100) -#define EDMA_TCD_ATTR_SSIZE_32BIT (0x0200) -#define EDMA_TCD_ATTR_SSIZE_64BIT (0x0300) -#define EDMA_TCD_ATTR_SSIZE_32BYTE (0x0500) -#define EDMA_TCD_ATTR_DSIZE_8BIT (0x) -#define EDMA_TCD_ATTR_DSIZE_16BIT (0x0001) -#define EDMA_TCD_ATTR_DSIZE_32BIT (0x0002) -#define EDMA_TCD_ATTR_DSIZE_64BIT (0x0003) -#define EDMA_TCD_ATTR_DSIZE_32BYTE (0x0005) - -#define EDMA_TCD_SOFF_SOFF(x) (x) -#define EDMA_TCD_NBYTES_NBYTES(x) (x) -#define EDMA_TCD_SLAST_SLAST(x)(x) -#define EDMA_TCD_DADDR_DADDR(x)(x) -#define EDMA_TCD_CITER_CITER(x)((x) & 0x7FFF) -#define EDMA_TCD_DOFF_DOFF(x) (x) -#define EDMA_TCD_DLAST_SGA_DLAST_SGA(x)(x) -#define EDMA_TCD_BITER_BITER(x)((x) & 0x7FFF) - -#define EDMA_TCD_CSR_START BIT(0) -#define EDMA_TCD_CSR_INT_MAJOR BIT(1) -#define EDMA_TCD_CSR_INT_HALF BIT(2) -#define EDMA_TCD_CSR_D_REQ BIT(3) -#define EDMA_TCD_CSR_E_SG BIT(4) -#define EDMA_TCD_CSR_E_LINKBIT(5) -#define EDMA_TCD_CSR_ACTIVEBIT(6) -#define EDMA_TCD_CSR_DONE BIT(7) - -#define EDMAMUX_CHCFG_DIS 0x0 -#define EDMAMUX_CHCFG_ENBL 0x80 -#define EDMAMUX_CHCFG_SOURCE(n)((n) & 0x3F) - -#define DMAMUX_NR 2 - -#define FSL_EDMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) -enum fsl_edma_pm_state
[PATCH v2 4/4] dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma
module.
The ColdFire edma module is slightly different from fsl-edma,
so a new driver is added. But most of the code is common
between fsl-edma and mcf-edma so it has been collected into a
separate common module fsl-edma-common (patch 2/4).
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add mcf-edma as minimal different parts from fsl-edma
---
drivers/dma/mcf-edma.c | 299 +
include/linux/platform_data/dma-mcf-edma.h | 38 +++
2 files changed, 337 insertions(+)
create mode 100644 drivers/dma/mcf-edma.c
create mode 100644 include/linux/platform_data/dma-mcf-edma.h
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
new file mode 100644
index ..9e1d55a5cc90
--- /dev/null
+++ b/drivers/dma/mcf-edma.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/mcf-edma.c
+ *
+ * Driver for the Freescale ColdFire 64-ch eDMA implementation,
+ * derived from drivers/dma/fsl-edma.c.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CHANNELS 64
+#define EDMA_MASK_CH(x)((x) & GENMASK(5, 0))
+
+static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int ch;
+ struct fsl_edma_chan *mcf_chan;
+ u64 intmap;
+
+ intmap = ioread32(regs->inth);
+ intmap <<= 32;
+ intmap |= ioread32(regs->intl);
+ if (!intmap)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < mcf_edma->n_chans; ch++) {
+ if (intmap & (0x1 << ch)) {
+ iowrite8(EDMA_MASK_CH(ch), regs->cint);
+
+ mcf_chan = _edma->chans[ch];
+
+ spin_lock(_chan->vchan.lock);
+ if (!mcf_chan->edesc->iscyclic) {
+ list_del(_chan->edesc->vdesc.node);
+ vchan_cookie_complete(_chan->edesc->vdesc);
+ mcf_chan->edesc = NULL;
+ mcf_chan->status = DMA_COMPLETE;
+ mcf_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(_chan->edesc->vdesc);
+ }
+
+ if (!mcf_chan->edesc)
+ fsl_edma_xfer_desc(mcf_chan);
+
+ spin_unlock(_chan->vchan.lock);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_engine *mcf_edma = dev_id;
+ struct edma_regs *regs = _edma->regs;
+ unsigned int err, ch;
+
+ err = ioread32(regs->errl);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
+ if (err & (0x1 << ch)) {
+ fsl_edma_disable_request(_edma->chans[ch]);
+ iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
+ mcf_edma->chans[ch].status = DMA_ERROR;
+ mcf_edma->chans[ch].idle = true;
+ }
+ }
+
+ err = ioread32(regs->errh);
+ if (!err)
+ return IRQ_NONE;
+
+ for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
+ if (err & (0x1 << (ch - (EDMA_CHANNELS / 2 {
+ fsl_edma_disable_request(_edma->chans[ch]);
+ iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
+ mcf_edma->chans[ch].status = DMA_ERROR;
+ mcf_edma->chans[ch].idle = true;
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int mcf_edma_irq_init(struct platform_device *pdev,
+ struct fsl_edma_engine *mcf_edma)
+{
+ int ret = 0, i;
+ struct resource *res;
+
+ res = platform_get_resource_byname(pdev,
+ IORESOURCE_IRQ, "edma-tx-00-15");
+ if (!res)
+ return -1;
+
+ for (ret = 0, i = res->start; i <= res->end; ++i) {
+ ret |= devm_request_irq(>dev, i,
+ mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
+ }
+ if (r
[PATCH v2 2/4] dmaengine: fsl-edma: add fsl-edma-common
This patch adds a new fsl-edma-common module to allow new
mcf-edma module code to use most of the fsl-edma code.
Due to some differences between ColdFire edma (64 channels) and
fsl-edma (32 channels), as register set offsets and some other
points as the different interrupt organization and other minor
things, a common module can collect most of the code for both
32 and 64 channel edmma module version.
Signed-off-by: Angelo Dureghello
---
Changes for v2:
- patch splitted into 4
- add fsl-edma-common module
---
drivers/dma/fsl-edma-common.c | 662 ++
drivers/dma/fsl-edma-common.h | 175 +
2 files changed, 837 insertions(+)
create mode 100644 drivers/dma/fsl-edma-common.c
create mode 100644 drivers/dma/fsl-edma-common.h
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
new file mode 100644
index ..c205cb07f133
--- /dev/null
+++ b/drivers/dma/fsl-edma-common.c
@@ -0,0 +1,662 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
+// Copyright (c) 2017 Sysam, Angelo Dureghello
+/*
+ * drivers/dma/fsl-edma-common.c
+ *
+ * Common code for Freescale the edma 32 or 64 channel version.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+
+#include "fsl-edma-common.h"
+
+#define EDMA_CR0x00
+#define EDMA_ES0x04
+#define EDMA_ERQ 0x0C
+#define EDMA_EEI 0x14
+#define EDMA_CEEI 0x18
+#define EDMA_SEEI 0x19
+#define EDMA_CERQ 0x1A
+#define EDMA_SERQ 0x1B
+#define EDMA_CINT 0x1F
+#define EDMA_CERR 0x1E
+#define EDMA_SSRT 0x1D
+#define EDMA_CDNE 0x1C
+#define EDMA_INTR 0x24
+#define EDMA_ERR 0x2C
+
+#define EDMA64_ERQH0x08
+#define EDMA64_EEIH0x10
+#define EDMA64_SERQ0x18
+#define EDMA64_CERQ0x19
+#define EDMA64_SEEI0x1a
+#define EDMA64_CEEI0x1b
+#define EDMA64_CINT0x1c
+#define EDMA64_CERR0x1d
+#define EDMA64_SSRT0x1e
+#define EDMA64_CDNE0x1f
+#define EDMA64_INTH0x20
+#define EDMA64_INTL0x24
+#define EDMA64_ERRH0x28
+#define EDMA64_ERRL0x2c
+
+#define EDMA_TCD 0x1000
+#define EDMA_TCD_SIZE 32
+#define EDMA_TCD_MEM_ALIGN EDMA_TCD_SIZE
+
+#define EDMA_TCD_ATTR_SSIZE_8BIT 0
+#define EDMA_TCD_ATTR_SSIZE_16BIT BIT(0)
+#define EDMA_TCD_ATTR_SSIZE_32BIT BIT(1)
+#define EDMA_TCD_ATTR_SSIZE_64BIT (BIT(1) | BIT(0))
+#define EDMA_TCD_ATTR_SSIZE_16BYTE BIT(2)
+#define EDMA_TCD_ATTR_SSIZE_32BYTE (BIT(2) | BIT(0))
+#define EDMA_TCD_ATTR_DSIZE_8BIT (EDMA_TCD_ATTR_SSIZE_8BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BIT (EDMA_TCD_ATTR_SSIZE_16BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BIT (EDMA_TCD_ATTR_SSIZE_32BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_64BIT (EDMA_TCD_ATTR_SSIZE_64BIT << 8)
+#define EDMA_TCD_ATTR_DSIZE_16BYTE (EDMA_TCD_ATTR_SSIZE_16BYTE << 8)
+#define EDMA_TCD_ATTR_DSIZE_32BYTE (EDMA_TCD_ATTR_SSIZE_32BYTE << 8)
+
+#define EDMA_TCD_CITER_CITER(x)((x) & GENMASK(14, 0))
+#define EDMA_TCD_BITER_BITER(x)((x) & GENMASK(14, 0))
+
+#define EDMA_TCD_CSR_START BIT(0)
+#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
+#define EDMA_TCD_CSR_INT_HALF BIT(2)
+#define EDMA_TCD_CSR_D_REQ BIT(3)
+#define EDMA_TCD_CSR_E_SG BIT(4)
+#define EDMA_TCD_CSR_E_LINKBIT(5)
+#define EDMA_TCD_CSR_ACTIVEBIT(6)
+#define EDMA_TCD_CSR_DONE BIT(7)
+
+struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
+{
+ return container_of(chan, struct fsl_edma_chan, vchan.chan);
+}
+
+struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct fsl_edma_desc, vdesc);
+}
+
+/*
+ * R/W functions for big- or little-endian registers:
+ * The eDMA controller's endian is independent of the CPU core's endian.
+ * For the big-endian IP module, the offset for 8-bit or 16-bit registers
+ * should also be swapped opposite to that in little-endian IP.
+ */
+u32 edma_readl(struct fsl_edma_engine *edma,
+ void __iomem *addr)
+{
+ if (edma->big_endian)
+ return ioread32be(addr);
+ else
+ r
[PATCH v2 1/4] dmaengine: fsl-edma: add config and makefile changes for mcf-edma
This patch adds Kconfig and makefile changes to add ColdFire mcf5441x family edma support. A new fsl-edma-common module has been added, to collect common code to fsl-edma. Signed-off-by: Angelo Dureghello --- Changes for v2: - patch splitted into 4 - add fsl-edma-common --- drivers/dma/Kconfig | 18 ++ drivers/dma/Makefile | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 6d61cd023633..9539e2fc2f94 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -220,11 +220,17 @@ config FSL_EDMA depends on OF select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select FSL_EDMA_COMMON help Support the Freescale eDMA engine with programmable channel multiplexing capability for DMA request sources(slot). This module can be found on Freescale Vybrid and LS-1 SoCs. +config FSL_EDMA_COMMON + bool + depends on FSL_EDMA || MCF_EDMA + default n + config FSL_RAID tristate "Freescale RAID engine Support" depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH @@ -327,6 +333,18 @@ config LPC18XX_DMAMUX Enable support for DMA on NXP LPC18xx/43xx platforms with PL080 and multiplexed DMA request lines. +config MCF_EDMA + tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs" + depends on M5441x + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + select FSL_EDMA_COMMON + help + Support the Freescale ColdFire eDMA engine, 64-channel + implementation that performs complex data transfers with + minimal intervention from a host processor. + This module can be found on Freescale ColdFire mcf5441x SoCs. + config MMP_PDMA bool "MMP PDMA support" depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 0f62a4d49aab..823a590f308b 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -33,6 +33,8 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o obj-$(CONFIG_FSL_EDMA) += fsl-edma.o +obj-$(CONFIG_FSL_EDMA_COMMON) += fsl-edma-common.o +obj-$(CONFIG_MCF_EDMA) += mcf-edma.o obj-$(CONFIG_FSL_RAID) += fsl_raid.o obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o -- 2.17.0 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: mcf-edma: add ColdFire mcf5441x eDMA support
Hi Vinod, On Mon, May 28, 2018 at 09:31:23AM +0530, Vinod wrote: > Hi Angelo, > > On 26-05-18, 22:50, Angelo Dureghello wrote: > > > > wouldn't it be easier to just make common parts and then add edma > > > specific code. > > > If I was doing this it would be my apprach and that way code edma > > > specific will > > > be lesser and faster review > > > > > > > I tried to set up a common module, but couldn't reach any good point. > > > > Issues are: > > 1) Edma register set between 32 and 64ch is similar, but some offsets/names > > are not matching between the 2 variants, some registers names are swapped > > over > > the reg. address range, > > 2) interrupt numbers and scheme is still different, handler implementation > > comes > > different, > > 3) as a corollary of the above, all the common functions that needs to > > access > > edma registers should use same structure pointers. I could use a union > > someway but points where register are accessed are many, and i should > > differentiate the access in each case, referencing to a different structure > > in each case. > > > > If you have any idea on how i could reach a common module, with 2 different > > registers set, that's welcome. > > I stay on the thought that a separate 64-channel module is the best > > way to go here. > > > > Currently, as Freescale "edma" variants, i know: > > > > Vybrid VFXXX 32ch DMA multiplexer reg.set 1 > > Kynetis K70 (CortexM4) 32ch DMA multiplexer reg.set 1 > > imx8xx (coming)32ch no multiplexerreg.set 1 > > MPC57xxk 32ch DMA multiplexer reg.set 1 > > ColdFire mcf5441x 64ch no multiplexerreg.set 2 <--- > > > > There may me other cpu using this fsl edma module but not in my knowledge > > right now. > > > > So i still think at the end, to have 2 separate drivers for the 32 and 64 > > variant is good and probably the most ordered/clean solution. > > Okay there are few ways we can do this. One is to use helpers for register > access and these helpers are different for the variant you are loaded on. > > Another is to use register offsets which are set based on the variant loaded.. > Ok i try with register offsets. Lets' see. Thanks, Angelo > HTH > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: mcf-edma: add ColdFire mcf5441x eDMA support
Hi Vinod, thanks for your support. On Wed, May 23, 2018 at 11:07:06AM +0530, Vinod wrote: > On 22-05-18, 23:28, Angelo Dureghello wrote: > > Hi Vinod, > > > > On Mon, May 07, 2018 at 07:45:35PM +0530, Vinod Koul wrote: > > > On Fri, May 04, 2018 at 09:18:19PM +0200, Angelo Dureghello wrote: > > > > Hi Vinod, > > > > > > > > thanks for the review, > > > > > > > > On Thu, May 03, 2018 at 10:18:30PM +0530, Vinod Koul wrote: > > > > > On Wed, Apr 25, 2018 at 10:08:17PM +0200, Angelo Dureghello wrote: > > > > > > This patch adds dma support for NXP mcf5441x (ColdFire) family. > > > > > > > > > > > > ColdFire mcf5441x implements an edma hw module similar to the > > > > > > > > > > Is it similar to to edma ? > > > > > > > > > > > > > It is similar to Freescale "edma" but with a different number of > > > > channels, a bit different register set, different interrupt > > > > structure, no channel multiplexer. > > > > > > ok > > > > > > > > > one implemented in Vybrid VFxxx controllers, but with a slightly > > > > > > different register set, more dma channels (64 instead of 32), > > > > > > a different interrupt mechanism and some other minor differences. > > > > > > > > > > > > For the above reasons, modfying fsl-edma.c was too complex and > > > > > > likely too ugly. From here, the decision to create a different > > > > > > driver, but starting from fsl-edma. > > > > > > > > > > can the common stuff be made into a lib and shared between then two > > > > > rather > > > > > than having a same driver or different drivers? > > > > > > > > It should be possible to collect some common code in a kind of > > > > mcf_edma_core.c common module, but in this case i cannot then test > > > > the Vybrid edma after the changes since i miss that hardware. > > > > > > Sure you should send the patches and folks who care about fsl driver > > > would look it up and test > > > > > > > Would be maybe possible for you to diff fsl-edma and this mcf-edma, > > > > just to confirm if i can still stay this way, or if moving to a > > > > library becomes mandatory ? > > > > > > well since you know the IP you would make a better guess on that, best is > > > to check register sets in drivers > > > > > I fixed all the discussed points. > > > > Actaully mcf-edma (ColdFire) has a slightly different register set (due to > > 64 > > channels in place of 16 of fsl-edma) and, for the same reason, a different > > DMA interrupt structure. > > Also, i simplified some parts of the driver considering ColdFire (mcf) > > big endian architecture. > > > > So i would send a rev 2 patch with all the fixes, than eventually in a > > second > > phase i may try to create some common code, but at least we have the > > ColdFire > > DMA. What do you think ? > > wouldn't it be easier to just make common parts and then add edma specific > code. > If I was doing this it would be my apprach and that way code edma specific > will > be lesser and faster review > I tried to set up a common module, but couldn't reach any good point. Issues are: 1) Edma register set between 32 and 64ch is similar, but some offsets/names are not matching between the 2 variants, some registers names are swapped over the reg. address range, 2) interrupt numbers and scheme is still different, handler implementation comes different, 3) as a corollary of the above, all the common functions that needs to access edma registers should use same structure pointers. I could use a union someway but points where register are accessed are many, and i should differentiate the access in each case, referencing to a different structure in each case. If you have any idea on how i could reach a common module, with 2 different registers set, that's welcome. I stay on the thought that a separate 64-channel module is the best way to go here. Currently, as Freescale "edma" variants, i know: Vybrid VFXXX 32ch DMA multiplexer reg.set 1 Kynetis K70 (CortexM4) 32ch DMA multiplexer reg.set 1 imx8xx (coming)32ch no multiplexerreg.set 1 MPC57xxk 32ch DMA multiplexer reg.set 1 ColdFire mcf5441x 64ch no multiplexerreg.set 2 <--- There may me other cpu using this fsl edma module but not in my knowledge right now. So i still think at the end, to have 2 separate drivers for the 32 and 64 variant is good and probably the most ordered/clean solution. Regards, Angelo > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: mcf-edma: add ColdFire mcf5441x eDMA support
Hi Vinod, On Mon, May 07, 2018 at 07:45:35PM +0530, Vinod Koul wrote: > On Fri, May 04, 2018 at 09:18:19PM +0200, Angelo Dureghello wrote: > > Hi Vinod, > > > > thanks for the review, > > > > On Thu, May 03, 2018 at 10:18:30PM +0530, Vinod Koul wrote: > > > On Wed, Apr 25, 2018 at 10:08:17PM +0200, Angelo Dureghello wrote: > > > > This patch adds dma support for NXP mcf5441x (ColdFire) family. > > > > > > > > ColdFire mcf5441x implements an edma hw module similar to the > > > > > > Is it similar to to edma ? > > > > > > > It is similar to Freescale "edma" but with a different number of > > channels, a bit different register set, different interrupt > > structure, no channel multiplexer. > > ok > > > > > one implemented in Vybrid VFxxx controllers, but with a slightly > > > > different register set, more dma channels (64 instead of 32), > > > > a different interrupt mechanism and some other minor differences. > > > > > > > > For the above reasons, modfying fsl-edma.c was too complex and > > > > likely too ugly. From here, the decision to create a different > > > > driver, but starting from fsl-edma. > > > > > > can the common stuff be made into a lib and shared between then two rather > > > than having a same driver or different drivers? > > > > It should be possible to collect some common code in a kind of > > mcf_edma_core.c common module, but in this case i cannot then test > > the Vybrid edma after the changes since i miss that hardware. > > Sure you should send the patches and folks who care about fsl driver > would look it up and test > > > Would be maybe possible for you to diff fsl-edma and this mcf-edma, > > just to confirm if i can still stay this way, or if moving to a > > library becomes mandatory ? > > well since you know the IP you would make a better guess on that, best is > to check register sets in drivers > I fixed all the discussed points. Actaully mcf-edma (ColdFire) has a slightly different register set (due to 64 channels in place of 16 of fsl-edma) and, for the same reason, a different DMA interrupt structure. Also, i simplified some parts of the driver considering ColdFire (mcf) big endian architecture. So i would send a rev 2 patch with all the fixes, than eventually in a second phase i may try to create some common code, but at least we have the ColdFire DMA. What do you think ? > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > > > Copyright info should be here in c99 style comments > > > > > > > Seems checkpatch.pl, for C files, does not like the C style > > initial line comment: > > > > WARNING: Missing or malformed SPDX-License-Identifier tag in line 1 > > #87: FILE: drivers/dma/mcf-edma.c:1: > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > While c++ type is accepted. > > > > In contrary, in .h files it wants cpp // style and not C style. > > SC99 comments style is > // SPDX-License-Identifier: GPL-2.0 > > Point is the copyright should be added is same formar i.e., > > // Copyright 20018 - foo bar > > this line should follow the spdx line > > > > > + > > > > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt > > > > > > why do you need this, why not use dev_xxx > > > > > > > Well, pr_ style seems to simplify the call a bit, should be allowed > > but if you prefer i can move all to dev_ format. > > in hindsight dev_ makes better sense, been there done that :) > > -- > ~Vinod > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html Regards, Angelo -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] dmaengine: mcf-edma: add ColdFire mcf5441x eDMA support
Hi Vinod,
thanks for the review,
On Thu, May 03, 2018 at 10:18:30PM +0530, Vinod Koul wrote:
> On Wed, Apr 25, 2018 at 10:08:17PM +0200, Angelo Dureghello wrote:
> > This patch adds dma support for NXP mcf5441x (ColdFire) family.
> >
> > ColdFire mcf5441x implements an edma hw module similar to the
>
> Is it similar to to edma ?
>
It is similar to Freescale "edma" but with a different number of
channels, a bit different register set, different interrupt
structure, no channel multiplexer.
> > one implemented in Vybrid VFxxx controllers, but with a slightly
> > different register set, more dma channels (64 instead of 32),
> > a different interrupt mechanism and some other minor differences.
> >
> > For the above reasons, modfying fsl-edma.c was too complex and
> > likely too ugly. From here, the decision to create a different
> > driver, but starting from fsl-edma.
>
> can the common stuff be made into a lib and shared between then two rather
> than having a same driver or different drivers?
>
It should be possible to collect some common code in a kind of
mcf_edma_core.c common module, but in this case i cannot then test
the Vybrid edma after the changes since i miss that hardware.
Would be maybe possible for you to diff fsl-edma and this mcf-edma,
just to confirm if i can still stay this way, or if moving to a
library becomes mandatory ?
> >
> > The driver has been tested with mcf5441x (stmark2 board) and
> > dspi driver, it worked fine and seems reliable at least as a
> > first initial version.
> >
> > Signed-off-by: Angelo Dureghello <ang...@sysam.it>
> > ---
> > arch/m68k/configs/stmark2_defconfig
> this should be a separate patch please
>
Ack.
> > multiplexing capability for DMA request sources(slot).
> > This module can be found on Freescale Vybrid and LS-1 SoCs.
> >
> > +config MCF_EDMA
>
> Alphabetical sort pls
>
Ack.
> > +// SPDX-License-Identifier: GPL-2.0
>
> Copyright info should be here in c99 style comments
>
Seems checkpatch.pl, for C files, does not like the C style
initial line comment:
WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
#87: FILE: drivers/dma/mcf-edma.c:1:
+/* SPDX-License-Identifier: GPL-2.0 */
While c++ type is accepted.
In contrary, in .h files it wants cpp // style and not C style.
> > +
> > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> why do you need this, why not use dev_xxx
>
Well, pr_ style seems to simplify the call a bit, should be allowed
but if you prefer i can move all to dev_ format.
> > +#define EDMA_CHANNELS 64
> > +#define EDMA_MASK_CH(x)((x) & 0x3F)
> > +#define EDMA_MASK_ITER(x) ((x) & 0x7FFF)
> > +#define EDMA_TCD_MEM_ALIGN 32
> > +
> > +#define EDMA_TCD_ATTR_DSZ_8b (0x)
> > +#define EDMA_TCD_ATTR_DSZ_16b (0x0001)
> > +#define EDMA_TCD_ATTR_DSZ_32b (0x0002)
> > +#define EDMA_TCD_ATTR_DSZ_16B (0x0004)
>
> BIT and GENMASK for these..
>
Ack.
> > +static unsigned int mcf_edma_get_tcd_attr(enum dma_slave_buswidth
> > addr_width)
> > +{
> > + switch (addr_width) {
> > + case 1:
> > + return EDMA_TCD_ATTR_SSZ_8b | EDMA_TCD_ATTR_DSZ_8b;
> > + case 2:
> > + return EDMA_TCD_ATTR_SSZ_16b | EDMA_TCD_ATTR_DSZ_16b;
> > + case 4:
> > + default:
>
> why default not treated as error?
>
Ack, will fix that.
> > +static int mcf_edma_slave_config(struct dma_chan *chan,
> > +struct dma_slave_config *cfg)
> > +{
> > + struct mcf_edma_chan *mcf_chan = to_mcf_edma_chan(chan);
> > +
> > + mcf_chan->esc.dir = cfg->direction;
> > + if (cfg->direction == DMA_DEV_TO_MEM) {
> > + mcf_chan->esc.dev_addr = cfg->src_addr;
> > + mcf_chan->esc.addr_width = cfg->src_addr_width;
> > + mcf_chan->esc.burst = cfg->src_maxburst;
> > + mcf_chan->esc.attr = mcf_edma_get_tcd_attr(cfg->src_addr_width);
> > + } else if (cfg->direction == DMA_MEM_TO_DEV) {
> > + mcf_chan->esc.dev_addr = cfg->dst_addr;
> > + mcf_chan->esc.addr_width = cfg->dst_addr_width;
> > + mcf_chan->esc.burst = cfg->dst_maxburst;
> > + mcf_chan->esc.attr = mcf_edma_get_tcd_attr(cfg->dst_addr_width);
>
> please save both src/dstn details here, typically we dont at this point
> about the txn direction... direction comes with prep_xxx call
>
Ack.
> > +static void mcf_edma_free_desc(struct virt_dma_desc
Re: [PATCHv2 00/14] m68k: fix and improve IO access — Linux M68K Devel
Hi Greg, it works as before with dspi driver + MMU. It builds fine. Tested-by: Angelo Dureghello <ang...@sysam.it> On Fri, Apr 20, 2018 at 12:05:48AM +0200, linux-m68k@vger.kernel.org wrote: > Convert the ColdFire IO access functions to use asm-generic/io.h. > > The motivation for these changes is to fix IO access problems found by > Angelo Dureghello during his work on ColdFire 5441x when running with > MMU enabled. It also bought to light problems with ColdFire systems that > have PCI bus support and their ability to access both the internal > peripherals and PCI bus peripherals. > > Along with the fixes I improved the ColdFire PCI support so that it works > with the MMU disabled on the ColdFire 5475. Previously PCI bus support was > only allowed when building with the MMU enabled. Now you can enable and > use the PCI bus in any configuration - MMU enabled or disabled. > > These changes force all ColdFire platforms to use the same IO access > family of functions. The existing code differentiated between systems > built with MMU enabled and MMU disabled - and there is really no reason > to do that. Ultimately it does result in the include/asm/io_no.h file > now being somewhat misnamed. Perhpas I should change that it? > > All in all the changes result in a net removal of ~140 lines, so that is > a good thing too. > > This version 2 of the patch set drops the bulk addition of iomem() macro > use to the local read/write calls using constant addresses. That was a > single huge patch that really needs to be broken up to more managable > chunks for review. As it was it resulted in a number of new compilation > warnings (as expected) where address types were not "void __iomem *" clean. > I'll create a new patch series to deal with that. > > Signed-off-by: Greg Ungerer <gerg@xx> > --- > Kconfig.bus |8 - > coldfire/pci.c| 114 -- > include/asm/atarihw.h |1 > include/asm/io.h | 10 - > include/asm/io_mm.h | 102 + > include/asm/io_no.h | 359 > -- > include/asm/kmap.h| 80 ++ > include/asm/nubus.h |1 > include/asm/q40_master.h |2 > include/asm/raw_io.h | 14 - > include/asm/vga.h |9 + > include/asm/virtconvert.h |2 > include/asm/zorro.h |1 > mm/kmap.c |8 + > 14 files changed, 285 insertions(+), 426 deletions(-) > > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majordomo@xxx > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/15] m68k: move *_relaxed macros into io_no.h and io_mm.h
Hi Greg,
On Wed, Apr 18, 2018 at 10:01:34AM +1000, Greg Ungerer wrote:
> Hi Angelo,
>
> On 18/04/18 06:53, Angelo Dureghello wrote:
> > thanks for this great job.
>
> :-)
>
>
> > On patch 10, PIC is PCI, right ?
>
> Yes, typo on my part. I even managed to get it wrong twice!
> I'll fix that.
>
>
> > In case you hae some time, am interested in understanding how those
> > guards
> >
> > #define xxx xxx
> >
> > works.
>
> In this particular case it is to allow local architecture code to
> have its own version of a function or macro and for the common
> kernel code to define it if it is not otherwise defined.
>
> Consider this example, in our local arch code we want an optimized
> "readb" function. If we just had:
>
> static inline u8 readb(void __iomem *addr)
> { ... }
>
> and the common code (such as include/asm-generic/io.h) had the
> common readb in a similar fashion:
>
> static inline u8 readb(void __iomem *addr)
> { ... }
>
> On compilation you are going to get readb multiply defined.
> If instead the common code had:
>
> #ifndef read
> #define readb readb
> static inline u8 readb(void __iomem *addr)
> { ... }
> #endif
>
> Then all we need to do in our local arch code is define "readb".
> If we defined it as a macro, then no problem that would just work.
> If we want it as a real function (preferable) then we just need to
> make sure that "readb" is somehow defined, so the simplest way is
> to just define it to be itself:
>
> #define read readb
>
> Obviously our local arch code has to be included first.
>
Thanks !
>
> > Is it ok to test the patch now in my mcf54415 based board ?
>
> Yes, please do. I expect it should fix the the issues you found,
> but lets confirm that is really the case.
>
> I will be issuing a v2 of the series - to fix the problems found by
> the autobuilder. But they are minor changes, and I would like to
> know that they actually fix your problems first.
>
Ok i tested it.
* applied all 15 patches
* enabled MMU
* compilied, there was 1 error
LDS arch/m68k/kernel/vmlinux.lds
CC arch/m68k/mm/init.o
CC arch/m68k/mm/cache.o
CC arch/m68k/mm/fault.o
CC arch/m68k/mm/kmap.o
arch/m68k/mm/kmap.c: In function '__ioremap':
arch/m68k/mm/kmap.c:129:6: error: implicit declaration of function
'__cf_internalio' [-Werror=implicit-function-declaration]
if (__cf_internalio(physaddr))
^
arch/m68k/mm/kmap.c: In function 'iounmap':
arch/m68k/mm/kmap.c:243:6: error: implicit declaration of function
'cf_internalio' [-Werror=implicit-function-declaration]
if (cf_internalio(addr))
^
cc1: some warnings being treated as errors
scripts/Makefile.build:312: set di istruzioni per l'obiettivo
"arch/m68k/mm/kmap.o" non riuscito
make[1]: *** [arch/m68k/mm/kmap.o] Errore 1
Makefile:1060: set di istruzioni per l'obiettivo "arch/m68k/mm" non riuscito
make: *** [arch/m68k/mm] Errore 2
Just to pass over the issue i changed line 20 of
from
#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
to
#if defined(CONFIG_PCI) || defined(CONFIG_COLDFIRE)
Then it built fine.
So my dspi driver works fine with MMU enabled.
Tested-by: Angelo Dureghello <ang...@sysam.it>
>
> > Reviewed-by: Angelo Dureghello <ang...@sysam.it>
>
> Thanks for that. I will add that in.
>
> Regards
> Greg
>
>
Regards,
Angelo
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Re: [PATCH 01/15] m68k: move *_relaxed macros into io_no.h and io_mm.h
Hi Greg,
thanks for this great job.
On patch 10, PIC is PCI, right ?
In case you hae some time, am interested in understanding how those
guards
#define xxx xxx
works.
Is it ok to test the patch now in my mcf54415 based board ?
Reviewed-by: Angelo Dureghello <ang...@sysam.it>
On Wed, Apr 11, 2018 at 10:54:14PM +1000, Greg Ungerer wrote:
> Move a copy of the definitions of the *_relaxed() macros into io_no.h
> and io_mm.h. This precedes a change to the io_no.h file to use
> asm-generic/io.h. They will be removed from io_no.h at that point.
>
> Signed-off-by: Greg Ungerer <g...@linux-m68k.org>
> ---
> arch/m68k/include/asm/io.h| 8
> arch/m68k/include/asm/io_mm.h | 8
> arch/m68k/include/asm/io_no.h | 8
> 3 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
> index 756089c..00b4515 100644
> --- a/arch/m68k/include/asm/io.h
> +++ b/arch/m68k/include/asm/io.h
> @@ -4,11 +4,3 @@
> #else
> #include
> #endif
> -
> -#define readb_relaxed(addr) readb(addr)
> -#define readw_relaxed(addr) readw(addr)
> -#define readl_relaxed(addr) readl(addr)
> -
> -#define writeb_relaxed(b, addr) writeb(b, addr)
> -#define writew_relaxed(b, addr) writew(b, addr)
> -#define writel_relaxed(b, addr) writel(b, addr)
> diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
> index ed5333e..22e778e 100644
> --- a/arch/m68k/include/asm/io_mm.h
> +++ b/arch/m68k/include/asm/io_mm.h
> @@ -524,4 +524,12 @@ static inline void ioport_unmap(void __iomem *p)
> {
> }
>
> +#define readb_relaxed(addr) readb(addr)
> +#define readw_relaxed(addr) readw(addr)
> +#define readl_relaxed(addr) readl(addr)
> +
> +#define writeb_relaxed(b, addr) writeb(b, addr)
> +#define writew_relaxed(b, addr) writew(b, addr)
> +#define writel_relaxed(b, addr) writel(b, addr)
> +
> #endif /* _IO_H */
> diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
> index 86f45b4..ffe567e 100644
> --- a/arch/m68k/include/asm/io_no.h
> +++ b/arch/m68k/include/asm/io_no.h
> @@ -189,4 +189,12 @@ static inline void ioport_unmap(void __iomem *p)
>
> #endif /* __KERNEL__ */
>
> +#define readb_relaxed(addr) readb(addr)
> +#define readw_relaxed(addr) readw(addr)
> +#define readl_relaxed(addr) readl(addr)
> +
> +#define writeb_relaxed(b, addr) writeb(b, addr)
> +#define writew_relaxed(b, addr) writew(b, addr)
> +#define writel_relaxed(b, addr) writel(b, addr)
> +
> #endif /* _M68KNOMMU_IO_H */
> --
> 1.9.1
>
> --
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Re: [PATCH v3 2/2] m68k: mmu: fix IO access endianness for ColdFire family
Hi Greg, On Mon, Mar 05, 2018 at 11:30:32PM +1000, Greg Ungerer wrote: > Hi Angelo, > > On 02/03/18 22:24, Angelo Dureghello wrote: > > On Fri, Mar 02, 2018 at 09:28:57AM +1000, Greg Ungerer wrote: > > > On 01/03/18 22:32, Angelo Dureghello wrote: > > > > This patch fixes IO access endianness, that should be big endian. > > > > If any little endian peripheral may be connected, bytes should > > > > be swapped in hardware. > > > > > > I am not sure I follow your meaning here. In many cases peripheral > > > devices will be hooked up and they are inherently little endian > > > but there is no hardware in between that will translate the endian. > > > It is just something that has to be dealt with at the software driver > > > level. > > > > > > So do you need to make this change for specific devices you are > > > working with? > > > > > > > Ok, well, i add some story to this patch. I was stuck from months > > since kernel was hanging silently when SPI driver was enabled in > > conjunction with mmu enbabled (no issues in spi + nommu). > > After hard debugging, i finally found the issue to be related to > > a wrong ioremap, and, together (so a double issue), peripheral > > registers was wrongly accessed as "little" endian. > > > > This was resulting in never getting any reply from SPI device, and > > kernel hanging silently in a wait loop. So, in mmu mode (io_mm.h), > > the mcf5441x IO peripheral address area (0xe000 to 0x) > > needs to be accessed as "big endian". > > That kind of makes sense, the m68k/ColdFire is big-endian. And looking > at the IO access for the non-MMU case that is what it does - just direct > access. (So in other words they are native endianess access). > > > > So to have mmu working on mcf5441x both patches are needed. > > > > As suggester by Geert, i isolated ioread/write to be big endian > > for mcf5441x *only*. > > That for me is a big red flag. The 5441x is not special, so to need > to have something specific for it doesn't really make sense. > > With MMU we have 5441x, 5445x, 547x and 548x. If i am not wrong, 5441x is the only family without PCI, so this was the reason why i isolated it, since looks like PCI access must be "litte endian". > > About my comment on endianness: some time ago i had to connect > > "amcore" cpu (big endian) with dm9000 IO peripheral (little endian). > > Software swap was not accepted, and i was informed that the proper and > > recommended way to go, even if a sw conversion is of course possible, > > was to swap endianness in hardware. So i had to modify my board design > > swapping byte wires, and issue new pcb prototypes. There should be a > > tracked discussion about this searching about dm9000 endianness here > > or in the net mailing list. > > Well I can point to one in-tree place where that is exactly what is done. > Have a look at the swap for COLDFIRE in drivers/net/ethernet/smsc/smc91x.h > Mmm this is interesting. So looks like sw swap is still possible/allowed. > But that is probably a moot point here, because you are talking about > the SPI module that is part of the 5441x SoC right? Yes. > Its bus interface can't be changed. And of course it works when > configured non-MMU. > > I would think that perhaps making then readl/writel native endian for > all ColdFire builds (like non-MMU) makes more sense - its internal > peripherals will certainly always be that. > > A consolidation of the all io access functions/macros so that ColdFire > used the same definitions (irrespective of MMU/non-MMU) would make > sense. That could lead to fixing PCI access in all modes as well. > Ok. So if i understand i could create an include io_cf.h (mmu + nommu) or similar name, with raw io access always as big endian for all. But how to manage the PCI accesses, where the access shoud be little endian ? Then btw, i can olny test the change on mcf5441x. > > > > I can modify that comment if it results wrong or too hard. > > > > I have my system back working now with new drivers and mmu enabled. > > > > (P.S.; i remember you was using an elf toolchain for mmu, do you have > > any link in case ? :) > > Oh, yeah, this is what I use: > > https://sourceforge.net/projects/uclinux/files/Tools/m68k-linux-20160822/ > Many thanks, really. > Regards > Greg > Regards, Angelo > > > > > I don't see that the M5441x parts are really special or different > > > from any of the other ColdFire (or even traditional m68k) devices > > &
Re: [PATCH v3 2/2] m68k: mmu: fix IO access endianness for ColdFire family
On Fri, Mar 02, 2018 at 09:28:57AM +1000, Greg Ungerer wrote: Hi Greg, > Hi Angelo, > > On 01/03/18 22:32, Angelo Dureghello wrote: > > This patch fixes IO access endianness, that should be big endian. > > If any little endian peripheral may be connected, bytes should > > be swapped in hardware. > > I am not sure I follow your meaning here. In many cases peripheral > devices will be hooked up and they are inherently little endian > but there is no hardware in between that will translate the endian. > It is just something that has to be dealt with at the software driver > level. > > So do you need to make this change for specific devices you are > working with? > Ok, well, i add some story to this patch. I was stuck from months since kernel was hanging silently when SPI driver was enabled in conjunction with mmu enbabled (no issues in spi + nommu). After hard debugging, i finally found the issue to be related to a wrong ioremap, and, together (so a double issue), peripheral registers was wrongly accessed as "little" endian. This was resulting in never getting any reply from SPI device, and kernel hanging silently in a wait loop. So, in mmu mode (io_mm.h), the mcf5441x IO peripheral address area (0xe000 to 0x) needs to be accessed as "big endian". So to have mmu working on mcf5441x both patches are needed. As suggester by Geert, i isolated ioread/write to be big endian for mcf5441x *only*. About my comment on endianness: some time ago i had to connect "amcore" cpu (big endian) with dm9000 IO peripheral (little endian). Software swap was not accepted, and i was informed that the proper and recommended way to go, even if a sw conversion is of course possible, was to swap endianness in hardware. So i had to modify my board design swapping byte wires, and issue new pcb prototypes. There should be a tracked discussion about this searching about dm9000 endianness here or in the net mailing list. I can modify that comment if it results wrong or too hard. I have my system back working now with new drivers and mmu enabled. (P.S.; i remember you was using an elf toolchain for mmu, do you have any link in case ? :) > I don't see that the M5441x parts are really special or different > from any of the other ColdFire (or even traditional m68k) devices > we currently support. > > Regards > Greg > > Regards, Angelo > > --- > > Changes from v2: > > - patch reduced form 3/3 to 2/2 > > - isolated big endian IO read/write[w,l] to mcf5441x > > > > Signed-off-by: Angelo Dureghello <ang...@sysam.it> > > --- > > arch/m68k/include/asm/io_mm.h | 16 > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h > > index ed5333e87879..a1a0f870b61b 100644 > > --- a/arch/m68k/include/asm/io_mm.h > > +++ b/arch/m68k/include/asm/io_mm.h > > @@ -444,13 +444,29 @@ static inline void isa_delay(void) > > */ > > #define readb(addr) in_8(addr) > > #define writeb(val,addr) out_8((addr),(val)) > > +#ifdef CONFIG_M5441x > > +/* > > + * mcf5441x only accesses IO/peripheral internal memory. > > + */ > > +#define readw(addr)in_be16(addr) > > +#define writew(val, addr) out_be16((addr), (val)) > > +#else > > #define readw(addr) in_le16(addr) > > #define writew(val,addr) out_le16((addr),(val)) > > +#endif > > > > #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */ > > > > +#ifdef CONFIG_M5441x > > +/* > > + * mcf5441x only accesses IO/peripheral internal memory. > > + */ > > +#define readl(addr)in_be32(addr) > > +#define writel(val, addr) out_be32((addr), (val)) > > +#else > > #define readl(addr) in_le32(addr) > > #define writel(val,addr) out_le32((addr),(val)) > > +#endif > > > > #define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr)) > > #define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr)) > > > > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] m68k: mmu: fix IO access endianness for ColdFire family
This patch fixes IO access endianness, that should be big endian. If any little endian peripheral may be connected, bytes should be swapped in hardware. --- Changes from v2: - patch reduced form 3/3 to 2/2 - isolated big endian IO read/write[w,l] to mcf5441x Signed-off-by: Angelo Dureghello <ang...@sysam.it> --- arch/m68k/include/asm/io_mm.h | 16 1 file changed, 16 insertions(+) diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index ed5333e87879..a1a0f870b61b 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -444,13 +444,29 @@ static inline void isa_delay(void) */ #define readb(addr) in_8(addr) #define writeb(val,addr) out_8((addr),(val)) +#ifdef CONFIG_M5441x +/* + * mcf5441x only accesses IO/peripheral internal memory. + */ +#define readw(addr)in_be16(addr) +#define writew(val, addr) out_be16((addr), (val)) +#else #define readw(addr) in_le16(addr) #define writew(val,addr) out_le16((addr),(val)) +#endif #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */ +#ifdef CONFIG_M5441x +/* + * mcf5441x only accesses IO/peripheral internal memory. + */ +#define readl(addr)in_be32(addr) +#define writel(val, addr) out_be32((addr), (val)) +#else #define readl(addr) in_le32(addr) #define writel(val,addr) out_le32((addr),(val)) +#endif #define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr)) #define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr)) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/2] m68k: mmu: fixed ioremap and iounmap for ColdFire family
This patch fixes ioremap() and iounmap(), since ColdFire family
is setting IO peripheral memory area into ACR0 (ACR0_MODE, head.S).
---
Changes from v2:
- patch reduced form 3/3 to 2/2
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/mm/kmap.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index c2a38321c96d..3d51e1993b1a 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -118,6 +118,14 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned
long size, int cachefla
if (!size || physaddr > (unsigned long)(-size))
return NULL;
+#if defined(CONFIG_COLDFIRE)
+ /*
+* This ColdFire models maps IO space into ACR0_MODE,
+* so they can access IO space directly.
+*/
+ return (void __iomem *)physaddr;
+#endif
+
#ifdef CONFIG_AMIGA
if (MACH_IS_AMIGA) {
if ((physaddr >= 0x4000) && (physaddr + size < 0x6000)
@@ -229,6 +237,13 @@ EXPORT_SYMBOL(__ioremap);
*/
void iounmap(void __iomem *addr)
{
+#if defined(CONFIG_COLDFIRE)
+ /*
+* No virtual io_area is allocated for ColdFire family.
+*/
+ return;
+#endif
+
#ifdef CONFIG_AMIGA
if ((!MACH_IS_AMIGA) ||
(((unsigned long)addr < 0x4000) ||
--
2.15.1
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Re: [PATCH v2 2/3] m68k: mmu: fix IO access endianness for ColdFire family
Hi Geert,
thanks for catching issues.
On Wed, Feb 28, 2018 at 10:59:38AM +0100, Geert Uytterhoeven wrote:
> Hi Angelo,
>
> On Tue, Feb 27, 2018 at 3:45 PM, Angelo Dureghello <ang...@sysam.it> wrote:
> > This patch fixes IO access endianness, that should be big endian.
> > If any little endian peripheral may be connected, bytes should
> > be swapped in hardware.
>
> Thanks for your patch!
>
> In general, {read,write}[wl]() are meant for PCI IO memory access, and thus
> intended to be little endian May vary on some systems, though.
>
Ok, i thought there was a reason but couldn't realize that.
Btw, with mmu enabled, SPI (and likely other drivers) regmap reads and writes
end up to same io_mm.h read,write[wl].
> Yes, I/O macros are a mess.
>
> > ---
> > Changes from v1:
> > - patch split into 3
> >
> > Signed-off-by: Angelo Dureghello <ang...@sysam.it>
> > ---
> > arch/m68k/include/asm/io_mm.h | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
> > index ed5333e87879..5ee6d7729dad 100644
> > --- a/arch/m68k/include/asm/io_mm.h
> > +++ b/arch/m68k/include/asm/io_mm.h
> > @@ -444,13 +444,13 @@ static inline void isa_delay(void)
> > */
> > #define readb(addr) in_8(addr)
> > #define writeb(val,addr) out_8((addr),(val))
> > -#define readw(addr) in_le16(addr)
> > -#define writew(val,addr) out_le16((addr),(val))
> > +#define readw(addr) in_be16(addr)
> > +#define writew(val,addr) out_be16((addr),(val))
>
> The above two affect non-ISA and non-Atari ROM-port ISA systems.
> So that indeed includes your Coldfire system (M54415?).
>
Yes. ColdFire enters that ifdef.
> BTW, is it correct none of the M5441x SoCs have PCI?
Good catch.
I don't see any PCI interface in mcf5441x, but MCF547x has PCI bus.
> Else, enabling CONFIG_PCI will select a completely different set of
> I/O macros at the top of arch/m68k/include/asm/io_mm.h.
>
> > #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
> >
> > -#define readl(addr) in_le32(addr)
> > -#define writel(val,addr) out_le32((addr),(val))
> > +#define readl(addr) in_be32(addr)
> > +#define writel(val,addr) out_be32((addr),(val))
>
> The above two affect _all_ m68k platforms, hence changing them could
> introduce regressions.
>
Ok, big issue so.
Since i cannot test anything else than mcf5441x now, i would isolate
32 bit(and also 16) IO accesses to be big endian for mcf5441x by proper
ifdefs.
> Yes, I/O macros are a mess...
>
> Gr{oetje,eeting}s,
>
> Geert
>
Regards,
Angelo
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
> --
> To unsubscribe from this list: send the line "unsubscribe linux-m68k" in
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[PATCH v2 3/3] m68k: mmu: fixed syntax to avoid style-check errors
This patch fixes spaces (and tabs) to respect kernel style rules. --- Changes from v1: - patch split into 3 Signed-off-by: Angelo Dureghello <ang...@sysam.it> --- arch/m68k/include/asm/io_mm.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index 5ee6d7729dad..e33d0c6dffb2 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -442,10 +442,10 @@ static inline void isa_delay(void) /* * These should be valid on any ioremap()ed region */ -#define readb(addr) in_8(addr) -#define writeb(val,addr) out_8((addr),(val)) -#define readw(addr) in_be16(addr) -#define writew(val,addr) out_be16((addr),(val)) +#define readb(addr)in_8(addr) +#define writeb(val, addr) out_8((addr), (val)) +#define readw(addr)in_be16(addr) +#define writew(val, addr) out_be16((addr), (val)) #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */ -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/3] m68k: mmu: fix IO access endianness for ColdFire family
This patch fixes IO access endianness, that should be big endian. If any little endian peripheral may be connected, bytes should be swapped in hardware. --- Changes from v1: - patch split into 3 Signed-off-by: Angelo Dureghello <ang...@sysam.it> --- arch/m68k/include/asm/io_mm.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index ed5333e87879..5ee6d7729dad 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -444,13 +444,13 @@ static inline void isa_delay(void) */ #define readb(addr) in_8(addr) #define writeb(val,addr) out_8((addr),(val)) -#define readw(addr) in_le16(addr) -#define writew(val,addr) out_le16((addr),(val)) +#define readw(addr) in_be16(addr) +#define writew(val,addr) out_be16((addr),(val)) #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */ -#define readl(addr) in_le32(addr) -#define writel(val,addr) out_le32((addr),(val)) +#define readl(addr) in_be32(addr) +#define writel(val,addr) out_be32((addr),(val)) #define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr)) #define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr)) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/3] m68k: mmu: fixed ioremap and iounmap for ColdFire family
This patch fixes ioremap() and iounmap(), since ColdFire family
is setting IO peripheral memory area into ACR0 (ACR0_MODE, head.S).
---
Changes from v1:
- patch split into 3
- add fix to iounmap()
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/mm/kmap.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index c2a38321c96d..3d51e1993b1a 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -118,6 +118,14 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned
long size, int cachefla
if (!size || physaddr > (unsigned long)(-size))
return NULL;
+#if defined(CONFIG_COLDFIRE)
+ /*
+* This ColdFire models maps IO space into ACR0_MODE,
+* so they can access IO space directly.
+*/
+ return (void __iomem *)physaddr;
+#endif
+
#ifdef CONFIG_AMIGA
if (MACH_IS_AMIGA) {
if ((physaddr >= 0x4000) && (physaddr + size < 0x6000)
@@ -229,6 +237,13 @@ EXPORT_SYMBOL(__ioremap);
*/
void iounmap(void __iomem *addr)
{
+#if defined(CONFIG_COLDFIRE)
+ /*
+* No virtual io_area is allocated for ColdFire family.
+*/
+ return;
+#endif
+
#ifdef CONFIG_AMIGA
if ((!MACH_IS_AMIGA) ||
(((unsigned long)addr < 0x4000) ||
--
2.15.1
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Re: [PATCH] mmu: fix ioremap for mcf54xx and mcf5441x
On Tue, Feb 27, 2018 at 11:06:07PM +1000, Greg Ungerer wrote:
Hi Greg,
> Hi Angelo,
>
> On 27/02/18 05:50, Angelo Dureghello wrote:
> > Also, IO bus access should be big endian, since the general rule
> > is to swap eventually the bytes in hardware when little endian
> > peripherals are connected.
> >
> > Reformatted readx/writex tabs.
>
> You need to break this up into 3 separate patches.
> You have 3 quite distinct logical changes being made here:
>
> 1. fixing iomremap
> 2. changing the behavior of IO buss access
> 3. whitespace change
>
Ok, ack. I'll split into 3.
>
> > Signed-off-by: Angelo Dureghello <ang...@sysam.it>
> > ---
> > arch/m68k/include/asm/io_mm.h | 12 ++--
> > arch/m68k/mm/kmap.c | 8
> > 2 files changed, 14 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
> > index ed5333e87879..a0d44ea82c22 100644
> > --- a/arch/m68k/include/asm/io_mm.h
> > +++ b/arch/m68k/include/asm/io_mm.h
> > @@ -442,15 +442,15 @@ static inline void isa_delay(void)
> > /*
> >* These should be valid on any ioremap()ed region
> >*/
> > -#define readb(addr) in_8(addr)
> > -#define writeb(val,addr) out_8((addr),(val))
> > -#define readw(addr) in_le16(addr)
> > -#define writew(val,addr) out_le16((addr),(val))
> > +#define readb(addr)in_8(addr)
> > +#define writeb(val, addr) out_8((addr), (val))
> > +#define readw(addr)in_be16(addr)
> > +#define writew(val, addr) out_be16((addr), (val))
> > #endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
> > -#define readl(addr) in_le32(addr)
> > -#define writel(val,addr) out_le32((addr),(val))
> > +#define readl(addr)in_be32(addr)
> > +#define writel(val, addr) out_be32((addr), (val))
> > #define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr))
> > #define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr))
> > diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
> > index c2a38321c96d..e8ebfc44ee03 100644
> > --- a/arch/m68k/mm/kmap.c
> > +++ b/arch/m68k/mm/kmap.c
> > @@ -118,6 +118,14 @@ void __iomem *__ioremap(unsigned long physaddr,
> > unsigned long size, int cachefla
> > if (!size || physaddr > (unsigned long)(-size))
> > return NULL;
> > +#if defined(CONFIG_M54xx) || defined(CONFIG_M5441x)
>
> I think this could be changed to "defined(CONFIG_COLDFIRE)". Currently all
> ColdFire configured systems (MMU and non-MMU) will have a direct mapping
> at the same physical address.
>
Ack.
>
> > + /*
> > +* This ColdFire models maps IO space into ACR0_MODE,
> > +* so they can access IO space directly.
> > +*/
> > + return (void __iomem *)physaddr;
> > +#endif
>
> Does this change also require a change to iounmap()?
> It looks like it will try to free resources that it no longer allocates
> afetr this change is made.
>
Likely yes, will fix it.
> Regards
> Greg
>
>
Thanks & regards,
Angelo
> > #ifdef CONFIG_AMIGA
> > if (MACH_IS_AMIGA) {
> > if ((physaddr >= 0x4000) && (physaddr + size < 0x6000)
> >
>
> --
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[PATCH] mmu: fix ioremap for mcf54xx and mcf5441x
Also, IO bus access should be big endian, since the general rule
is to swap eventually the bytes in hardware when little endian
peripherals are connected.
Reformatted readx/writex tabs.
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/include/asm/io_mm.h | 12 ++--
arch/m68k/mm/kmap.c | 8
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index ed5333e87879..a0d44ea82c22 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -442,15 +442,15 @@ static inline void isa_delay(void)
/*
* These should be valid on any ioremap()ed region
*/
-#define readb(addr) in_8(addr)
-#define writeb(val,addr) out_8((addr),(val))
-#define readw(addr) in_le16(addr)
-#define writew(val,addr) out_le16((addr),(val))
+#define readb(addr)in_8(addr)
+#define writeb(val, addr) out_8((addr), (val))
+#define readw(addr)in_be16(addr)
+#define writew(val, addr) out_be16((addr), (val))
#endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
-#define readl(addr) in_le32(addr)
-#define writel(val,addr) out_le32((addr),(val))
+#define readl(addr)in_be32(addr)
+#define writel(val, addr) out_be32((addr), (val))
#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr))
#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr))
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index c2a38321c96d..e8ebfc44ee03 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -118,6 +118,14 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned
long size, int cachefla
if (!size || physaddr > (unsigned long)(-size))
return NULL;
+#if defined(CONFIG_M54xx) || defined(CONFIG_M5441x)
+ /*
+* This ColdFire models maps IO space into ACR0_MODE,
+* so they can access IO space directly.
+*/
+ return (void __iomem *)physaddr;
+#endif
+
#ifdef CONFIG_AMIGA
if (MACH_IS_AMIGA) {
if ((physaddr >= 0x4000) && (physaddr + size < 0x6000)
--
2.15.1
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[RFC] ColdFire mcf5441x eDMA driver
Hi all, was looking inside mcf54415 eDMA support, and just seen that the available fsl-edma.c driver is not suitable for this CPU. The hw module is quite similar but register positions and channels available are different. So, seems a good chance to add a mcf-edma.c driver, starting/looking from fsl-edma.c. What do you think ? Is there anything already done about, maybe ? In case i would like to try to write an initial version of this driver. And Merry Christmas time to all. Regards, Angelo Dureghello -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] m68k/defconfig: fix stmark2 broken local compilation
Signed-off-by: Angelo Dureghello <ang...@sysam.it> --- arch/m68k/configs/stmark2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/m68k/configs/stmark2_defconfig b/arch/m68k/configs/stmark2_defconfig index 55e55dbc2fb6..3d07b1de7eb0 100644 --- a/arch/m68k/configs/stmark2_defconfig +++ b/arch/m68k/configs/stmark2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="../uClinux-dist/romfs" # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set # CONFIG_RD_XZ is not set -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] m68k: add Sysam stmark2 open board support
Hi Greg, On Mon, Dec 04, 2017 at 02:22:22PM +1000, Greg Ungerer wrote: > Hi Angelo, > > On 13/10/17 08:42, Angelo Dureghello wrote: > > Add support for Sysam stmark2 board, an open hardware embedded > > Linux board, see http://sysam.it/cff_stmark2.html for any info. > > > > Signed-off-by: Angelo Dureghello <ang...@sysam.it> > > --- > [snip] > > diff --git a/arch/m68k/configs/stmark2_defconfig > > b/arch/m68k/configs/stmark2_defconfig > > new file mode 100644 > > index ..55e55dbc2fb6 > > --- /dev/null > > +++ b/arch/m68k/configs/stmark2_defconfig > > @@ -0,0 +1,92 @@ > > +CONFIG_LOCALVERSION="stmark2-001" > > +CONFIG_DEFAULT_HOSTNAME="stmark2" > > +CONFIG_SYSVIPC=y > > +# CONFIG_FHANDLE is not set > > +CONFIG_LOG_BUF_SHIFT=14 > > +CONFIG_NAMESPACES=y > > +CONFIG_BLK_DEV_INITRD=y > > +CONFIG_INITRAMFS_SOURCE="../uClinux-dist/romfs" > > This causes a stand alone kernel defconfig build of stmark2 to fail with: > > ... > CC init/calibrate.o > CC init/init_task.o > AR init/built-in.o > HOSTCC usr/gen_init_cpio > ./scripts/gen_initramfs_list.sh: Cannot open '../uClinux-dist/romfs' > make[1]: *** [usr/initramfs_data.cpio.gz] Error 1 > make: *** [usr] Error 2 > > Obviously in a stand alone build you cannot rely on any directory > paths outside of the kernel tree. > > The simple solution is just to remove this CONFIG_INITRAMFS_SOURCE > line - and that results in complete build. Of course it won't > work on your target as expected though. > > Other ColdFire defconfigs don't use an init ramfs, instead using > a local ram based MTD partition. > > Do you want to come up with a patch to fix this? > Otherwise I will create a patch that just removes that one line. > ooh, ok, i'll remove that entry. I'll post a patch in short, just that the build is not breaking anymore. Used this method initially since spi driver was still not available, will check then about local ram based MTD partition. Jfyi, this defconfig will then follow several additions, i am now working on the mmc/sd driver. Also, i tried to enable mmu but seems there are some issues now that i added the spi driver, system hangs someway adding spi platform drivers to the bus. I am investigating into this too. > Regards > Greg > > Regards, Angelo > -- > To unsubscribe from this list: send the line "unsubscribe linux-m68k" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Applied "spi: spi-fsl-dspi: enabling Coldfire mcf5441x dspi" to the spi tree
Hi all,
jfyi,
there was some retries, sorry if i kept you out of cc at a certain point,
but finally patch has been accepted (and i am very happy).
Thanks Greg, Geert and all for support.
Best regards,
Angelo Dureghello
- Forwarded message from Mark Brown <broo...@kernel.org> -
Date: Fri, 3 Nov 2017 11:53:57 + (GMT)
From: Mark Brown <broo...@kernel.org>
To: Angelo Dureghello <ang...@sysam.it>
Cc: Mark Brown <broo...@kernel.org>, linux-...@vger.kernel.org,
linux-...@vger.kernel.org
Subject: Applied "spi: spi-fsl-dspi: enabling Coldfire mcf5441x dspi" to the
spi tree
The patch
spi: spi-fsl-dspi: enabling Coldfire mcf5441x dspi
has been applied to the spi tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From ec7ed7708e009e046d1e16ed53ba4d6048748d07 Mon Sep 17 00:00:00 2001
From: Angelo Dureghello <ang...@sysam.it>
Date: Sat, 28 Oct 2017 00:23:01 +0200
Subject: [PATCH] spi: spi-fsl-dspi: enabling Coldfire mcf5441x dspi
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
Signed-off-by: Mark Brown <broo...@kernel.org>
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-fsl-dspi.c | 66 +++-
include/linux/spi/spi-fsl-dspi.h | 31 +++
3 files changed, 77 insertions(+), 22 deletions(-)
create mode 100644 include/linux/spi/spi-fsl-dspi.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a75f2a2cf780..a8b761979673 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -379,7 +379,7 @@ config SPI_FSL_DSPI
tristate "Freescale DSPI controller"
select REGMAP_MMIO
depends on HAS_DMA
- depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x ||
COMPILE_TEST
help
This enables support for the Freescale DSPI controller in master
mode. VF610 platform uses the controller.
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index d89127f4a46d..f652f70cb8db 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
@@ -151,6 +152,11 @@ static const struct fsl_dspi_devtype_data ls2085a_data = {
.max_clock_factor = 8,
};
+static const struct fsl_dspi_devtype_data coldfire_data = {
+ .trans_mode = DSPI_EOQ_MODE,
+ .max_clock_factor = 8,
+};
+
struct fsl_dspi_dma {
/* Length of transfer in words of DSPI_FIFO_SIZE */
u32 curr_xfer_len;
@@ -741,6 +747,7 @@ static int dspi_setup(struct spi_device *spi)
{
struct chip_data *chip;
struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
+ struct fsl_dspi_platform_data *pdata;
u32 cs_sck_delay = 0, sck_cs_delay = 0;
unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
unsigned char pasc = 0, asc = 0, fmsz = 0;
@@ -761,11 +768,18 @@ static int dspi_setup(struct spi_device *spi)
return -ENOMEM;
}
- of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
- _sck_delay);
+ pdata = dev_get_platdata(>pdev->dev);
- of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
- _cs_delay);
+ if (!pdata) {
+ of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
+ _sck_delay);
+
+ of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
+ _cs_delay);
+ } else {
+ cs_sck_delay = pdata->cs_sck_delay;
+ sck_cs_delay = pdata->sck_cs_delay;
+ }
chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
@@ -949,6 +963,7 @@ static int dspi_probe(struct platform_device *pdev)
struct fsl_dspi *dspi;
struct resource *res;
void __iomem *base;
+ struct fsl_dspi_platform_data *pdata;
int ret = 0,
Re: coldfire uart question
Hi Greg, On 18/10/2017 09:12, Greg Ungerer wrote: Hi Angelo, On 18/10/17 07:18, Angelo Dureghello wrote: On 16/10/2017 01:08, Finn Thain wrote: On Sun, 15 Oct 2017, Angelo Dureghello wrote: Hi all, i was trying a file transfer with xmodem-1k and uClinux "rx" on the mcf54415 stnmark2 board side. This using a recent mainline kernel: / # cat /proc/version uClinux version 4.14.0-rc4stmark2-001-00118-g811fdbb62a9d / # So, as per xmodem-1k, i send 3 bytes header, a 1024 bytes block, and 2 bytes crc16. But "rx" timeouts waiting the block. What is the fastest baud rate that will work? Adding some traces to "rx", it timeouts since some bytes (5 to 10) randomly positioned in the block are not received. Of course they have been sent (scope checked). The same 1024 bytes transfer in u-boot (y-modem) always succeed. Does u-boot need to do any retransmissions? (If it polls the UART, it could probably avoid any fifo overflow.) You may also want to try lrzsz. Since mcf54415 has a 4 slots RX fifo UART, Ouch. At 115200 baud, that FIFO overflows after about 347 microseconds. If the kernel takes one interrupt per 4 bytes, you're looking at thousands of interrupts per second. Add a little unexpected interrupt latency (say, 50 microseconds) and the next byte gets lost. thanks for explaining this. Well, if i understand properly, this mcf54415 CPU has 2 interrupts flags that can be checked: RXRDY, for one or more character received (current mcf.c seems to use this flag) and FFULL, for all 4 fifo slots full. So we probably have even more interrupts per second right now. I am at 115200, will try to decrease, and also, will try zmodem in case. Can you use hardware flow control (the "crtscts" stty setting)? You will need to use a serial cable with RTS and CTS signals wired, and also for the sending end to be set for it. The ColdFire UART has hardware level support for automatically driving RTS/CTS when FIFO is full. many thanks for the hint, well for stmark2 board unfortunately/stupidly i didn't wired them out from the BGA package. But good to know. Regards Greg Regards, Angelo -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: coldfire uart question
Hi Geert and Finn,
On 18/10/2017 08:37, Geert Uytterhoeven wrote:
On Wed, Oct 18, 2017 at 2:06 AM, Finn Thain <fth...@telegraphics.com.au> wrote:
On Tue, 17 Oct 2017, Angelo Dureghello wrote:
On 16/10/2017 01:08, Finn Thain wrote:
On Sun, 15 Oct 2017, Angelo Dureghello wrote:
i was trying a file transfer with xmodem-1k and uClinux "rx" on the
mcf54415 stnmark2 board side.
This using a recent mainline kernel:
/ # cat /proc/version
uClinux version 4.14.0-rc4stmark2-001-00118-g811fdbb62a9d
/ #
So, as per xmodem-1k, i send 3 bytes header, a 1024 bytes block, and
2 bytes crc16. But "rx" timeouts waiting the block.
What is the fastest baud rate that will work?
Adding some traces to "rx", it timeouts since some bytes (5 to 10)
randomly positioned in the block are not received. Of course they
have been sent (scope checked).
The same 1024 bytes transfer in u-boot (y-modem) always succeed.
Does u-boot need to do any retransmissions? (If it polls the UART, it
could probably avoid any fifo overflow.)
You may also want to try lrzsz.
Since mcf54415 has a 4 slots RX fifo UART,
Ouch. At 115200 baud, that FIFO overflows after about 347
microseconds. If the kernel takes one interrupt per 4 bytes, you're
looking at thousands of interrupts per second. Add a little unexpected
interrupt latency (say, 50 microseconds) and the next byte gets lost.
I should have said "86 microseconds", to guarantee an overflow, but the
margin is lower than that even on an idle system, because time is lost in
interrupt dispatch. This margin is the same whether the interrupt happens
after one byte or four bytes.
thanks for explaining this.
Well, if i understand properly, this mcf54415 CPU has 2 interrupts flags
that can be checked: RXRDY, for one or more character received (current
mcf.c seems to use this flag) and FFULL, for all 4 fifo slots full.
So we probably have even more interrupts per second right now.
Even if you can reach 4 bytes per interrupt, the payoff is probably a
reduction in CPU overhead due to interrupt load rather than a reduction in
FIFO overflows.
In addition, if you already have FIFO overflows (of the remaining 3 entries)
in between the issuing of the interrupt and the actual interrupt handling,
you will have them for sure if you make the hardware issue an interrupt
only when the FIFO is already full.
Gr{oetje,eeting}s,
Geert
Ok, many thanks for the clarifications, so mainly this is a linux limitation
and seems i have to live whit it. Ok will do some test, maybe also adding 1
stop bit or killing some processes may help ? I am already
into initramfs, so the write should not be that heavy.
Will try also zmodem in case.
Regards,
Angelo
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: coldfire uart question
Hi Finn, On 16/10/2017 01:08, Finn Thain wrote: On Sun, 15 Oct 2017, Angelo Dureghello wrote: Hi all, i was trying a file transfer with xmodem-1k and uClinux "rx" on the mcf54415 stnmark2 board side. This using a recent mainline kernel: / # cat /proc/version uClinux version 4.14.0-rc4stmark2-001-00118-g811fdbb62a9d / # So, as per xmodem-1k, i send 3 bytes header, a 1024 bytes block, and 2 bytes crc16. But "rx" timeouts waiting the block. What is the fastest baud rate that will work? Adding some traces to "rx", it timeouts since some bytes (5 to 10) randomly positioned in the block are not received. Of course they have been sent (scope checked). The same 1024 bytes transfer in u-boot (y-modem) always succeed. Does u-boot need to do any retransmissions? (If it polls the UART, it could probably avoid any fifo overflow.) You may also want to try lrzsz. Since mcf54415 has a 4 slots RX fifo UART, Ouch. At 115200 baud, that FIFO overflows after about 347 microseconds. If the kernel takes one interrupt per 4 bytes, you're looking at thousands of interrupts per second. Add a little unexpected interrupt latency (say, 50 microseconds) and the next byte gets lost. thanks for explaining this. Well, if i understand properly, this mcf54415 CPU has 2 interrupts flags that can be checked: RXRDY, for one or more character received (current mcf.c seems to use this flag) and FFULL, for all 4 fifo slots full. So we probably have even more interrupts per second right now. I am at 115200, will try to decrease, and also, will try zmodem in case. Regards, Angelo -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: coldfire uart question
Hi Greg and all, On 16/10/2017 01:57, Greg Ungerer wrote: Hi Angelo, On 16/10/17 03:28, Angelo Dureghello wrote: i was trying a file transfer with xmodem-1k and uClinux "rx" on the mcf54415 stnmark2 board side. This using a recent mainline kernel: / # cat /proc/version uClinux version 4.14.0-rc4stmark2-001-00118-g811fdbb62a9d / # So, as per xmodem-1k, i send 3 bytes header, a 1024 bytes block, and 2 bytes crc16. But "rx" timeouts waiting the block. Adding some traces to "rx", it timeouts since some bytes (5 to 10) randomly positioned in the block are not received. Of course they have been sent (scope checked). Check if you are getting overruns on the port: cat /proc/tty/driver/mcf thanks, yes, you are right / # cat /proc/tty/driver/mcf serinfo:1.0 driver revision: 0: uart:ColdFire UART mmio:0xFC06 irq:90 tx:4047 rx:1057 oe:8 RTS|DTR|CD 1: uart:ColdFire UART mmio:0xFC064000 irq:91 tx:0 rx:0 CD 2: uart:ColdFire UART mmio:0xFC068000 irq:92 tx:0 rx:0 CD 3: uart:ColdFire UART mmio:0xFC06C000 irq:93 tx:0 rx:0 CD / # I am at 115200,n,8,1 now. I checked the u-boot driver and there is no interrupt handler, only a coldfire_serial_getc checking USR_RXRDY. Could the RxFIFO_Full interrupt flag be of any help ? Regards Greg Regards, Angelo The same 1024 bytes transfer in u-boot (y-modem) always succeed. Since mcf54415 has a 4 slots RX fifo UART, i was wondering if the mcf.c uart driver is not fast enough to read the data, or, where the "linux" limitation could be. Regards, Angelo Dureghello -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
coldfire uart question
Hi all, i was trying a file transfer with xmodem-1k and uClinux "rx" on the mcf54415 stnmark2 board side. This using a recent mainline kernel: / # cat /proc/version uClinux version 4.14.0-rc4stmark2-001-00118-g811fdbb62a9d / # So, as per xmodem-1k, i send 3 bytes header, a 1024 bytes block, and 2 bytes crc16. But "rx" timeouts waiting the block. Adding some traces to "rx", it timeouts since some bytes (5 to 10) randomly positioned in the block are not received. Of course they have been sent (scope checked). The same 1024 bytes transfer in u-boot (y-modem) always succeed. Since mcf54415 has a 4 slots RX fifo UART, i was wondering if the mcf.c uart driver is not fast enough to read the data, or, where the "linux" limitation could be. Regards, Angelo Dureghello -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] m68k: add Sysam stmark2 open board support
Hi Greg,
On 13/10/2017 08:56, Greg Ungerer wrote:
Hi Angelo,
On 13/10/17 08:42, Angelo Dureghello wrote:
Add support for Sysam stmark2 board, an open hardware embedded
Linux board, see http://sysam.it/cff_stmark2.html for any info.
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/Kconfig.machine | 6 ++
arch/m68k/coldfire/Makefile | 3 +-
arch/m68k/coldfire/stmark2.c| 120
arch/m68k/configs/stmark2_defconfig | 92 +++
4 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 arch/m68k/coldfire/stmark2.c
create mode 100644 arch/m68k/configs/stmark2_defconfig
diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine
index 9225b4ad9aeb..00698404b97f 100644
--- a/arch/m68k/Kconfig.machine
+++ b/arch/m68k/Kconfig.machine
@@ -265,6 +265,12 @@ config AMCORE
help
Support for the Sysam AMCORE open-hardware generic board.
+config STMARK2
+bool "Sysam stmark2 board support"
+depends on M5441x
+help
+ Support for the Sysam stmark2 open-hardware generic board.
+
config FIREBEE
bool "FireBee board support"
depends on M547x
diff --git a/arch/m68k/coldfire/Makefile b/arch/m68k/coldfire/Makefile
index 4aa2c57afc35..e45baeaadac8 100644
--- a/arch/m68k/coldfire/Makefile
+++ b/arch/m68k/coldfire/Makefile
@@ -34,7 +34,8 @@ obj-$(CONFIG_NETtel) += nettel.o
obj-$(CONFIG_CLEOPATRA) += nettel.o
obj-$(CONFIG_FIREBEE) += firebee.o
obj-$(CONFIG_MCF8390) += mcf8390.o
-obj-$(CONFIG_AMCORE)+= amcore.o
+obj-$(CONFIG_AMCORE) += amcore.o
+obj-$(CONFIG_STMARK2) += stmark2.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/m68k/coldfire/stmark2.c b/arch/m68k/coldfire/stmark2.c
new file mode 100644
index ..8eaf869de8e2
--- /dev/null
+++ b/arch/m68k/coldfire/stmark2.c
@@ -0,0 +1,120 @@
+/*
+ * stmark2.c -- Support for Sysam AMCORE open board
+ *
+ * (C) Copyright 2017, Angelo Dureghello <ang...@sysam.it>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Partitioning of parallel NOR flash (39VF3201B)
+ */
+static struct mtd_partition stmark2_partitions[] = {
+ {
+ .name = "U-Boot (1024K)",
+ .size = 0x10,
+ .offset = 0x0
+ }, {
+ .name = "Kernel+initramfs (7168K)",
+ .size = 0x70,
+ .offset = MTDPART_OFS_APPEND
+ }, {
+ .name = "Flash Free Space (8192K)",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND
+ }
+};
+
+static struct flash_platform_data stmark2_spi_flash_data = {
+ .name = "is25lp128",
+ .parts = stmark2_partitions,
+ .nr_parts = ARRAY_SIZE(stmark2_partitions),
+ .type = "is25lp128",
+};
+
+static struct spi_board_info stmark2_board_info[] __initdata = {
^^
Should some of the other structures in this code be __initdata too?
Well, for now it is ok just that structure only as __initdata.
Thanks,
Regards
Greg
Regards,
Angelo
+ {
+ .modalias = "m25p80",
+ .max_speed_hz = 500,
+ .bus_num = 0,
+ .chip_select = 1,
+ .platform_data = _spi_flash_data,
+ .mode = SPI_MODE_3,
+ }
+};
+
+/* SPI controller data, SPI (0) */
+static struct fsl_dspi_platform_data dspi_spi0_info = {
+ .cs_num = 4,
+ .bus_num = 0,
+ .sck_cs_delay = 100,
+ .cs_sck_delay = 100,
+};
+
+static struct resource dspi_spi0_resource[] = {
+ [0] = {
+ .start = MCFDSPI_BASE0,
+ .end = MCFDSPI_BASE0 + 0xFF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 12,
+ .end = 13,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .start = MCF_IRQ_DSPI0,
+ .end = MCF_IRQ_DSPI0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* SPI controller, id = bus number */
+static struct platform_device dspi_spi0_device = {
+ .name = "fsl-dspi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(dspi_spi0_resource),
+ .resource = dspi_spi0_resource,
+ .dev = {
+ .platform_data = _spi0_info,
+ },
+};
+
+static struct platform_device *stmark2_devices[] __initdata = {
+ _spi0_device,
+};
+
+/*
+ * Note: proper pin-mux setup is mandatory for proper SPI functionality.
+ */
+static int __init init_stmark2(void)
+{
+ /* DSPI0, all pin
[PATCH] m68k: coldfire: add dspi0 module support
This patch adds initial module base address and irq for dspi0.
It also defines the dspi0 clock to be used by the Freescale driver.
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/coldfire/m5441x.c | 3 ++-
arch/m68k/include/asm/m5441xsim.h | 6 ++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c
index 04fd7fde9fb3..dc48bb1cf3e3 100644
--- a/arch/m68k/coldfire/m5441x.c
+++ b/arch/m68k/coldfire/m5441x.c
@@ -26,7 +26,7 @@ DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
-DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
@@ -139,6 +139,7 @@ static struct clk * const enable_clks[] __initconst = {
&__clk_0_18, /* intc0 */
&__clk_0_19, /* intc0 */
&__clk_0_20, /* intc0 */
+ &__clk_0_23, /* dspi.0 */
&__clk_0_24, /* uart0 */
&__clk_0_25, /* uart1 */
&__clk_0_26, /* uart2 */
diff --git a/arch/m68k/include/asm/m5441xsim.h
b/arch/m68k/include/asm/m5441xsim.h
index 64f60be47066..adf6701db052 100644
--- a/arch/m68k/include/asm/m5441xsim.h
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -277,4 +277,10 @@
#define MCFGPIO_IRQ_VECBASE(MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
#define MCFGPIO_PIN_MAX87
+/*
+ * DSPI module.
+ */
+#define MCFDSPI_BASE0 0xfc05c000
+#define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0)
+
#endif /* m5441xsim_h */
--
2.14.1
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[PATCH] m68k: add Sysam stmark2 open board support
Add support for Sysam stmark2 board, an open hardware embedded
Linux board, see http://sysam.it/cff_stmark2.html for any info.
Signed-off-by: Angelo Dureghello <ang...@sysam.it>
---
arch/m68k/Kconfig.machine | 6 ++
arch/m68k/coldfire/Makefile | 3 +-
arch/m68k/coldfire/stmark2.c| 120
arch/m68k/configs/stmark2_defconfig | 92 +++
4 files changed, 220 insertions(+), 1 deletion(-)
create mode 100644 arch/m68k/coldfire/stmark2.c
create mode 100644 arch/m68k/configs/stmark2_defconfig
diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine
index 9225b4ad9aeb..00698404b97f 100644
--- a/arch/m68k/Kconfig.machine
+++ b/arch/m68k/Kconfig.machine
@@ -265,6 +265,12 @@ config AMCORE
help
Support for the Sysam AMCORE open-hardware generic board.
+config STMARK2
+bool "Sysam stmark2 board support"
+depends on M5441x
+help
+ Support for the Sysam stmark2 open-hardware generic board.
+
config FIREBEE
bool "FireBee board support"
depends on M547x
diff --git a/arch/m68k/coldfire/Makefile b/arch/m68k/coldfire/Makefile
index 4aa2c57afc35..e45baeaadac8 100644
--- a/arch/m68k/coldfire/Makefile
+++ b/arch/m68k/coldfire/Makefile
@@ -34,7 +34,8 @@ obj-$(CONFIG_NETtel) += nettel.o
obj-$(CONFIG_CLEOPATRA)+= nettel.o
obj-$(CONFIG_FIREBEE) += firebee.o
obj-$(CONFIG_MCF8390) += mcf8390.o
-obj-$(CONFIG_AMCORE)+= amcore.o
+obj-$(CONFIG_AMCORE) += amcore.o
+obj-$(CONFIG_STMARK2) += stmark2.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/m68k/coldfire/stmark2.c b/arch/m68k/coldfire/stmark2.c
new file mode 100644
index ..8eaf869de8e2
--- /dev/null
+++ b/arch/m68k/coldfire/stmark2.c
@@ -0,0 +1,120 @@
+/*
+ * stmark2.c -- Support for Sysam AMCORE open board
+ *
+ * (C) Copyright 2017, Angelo Dureghello <ang...@sysam.it>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Partitioning of parallel NOR flash (39VF3201B)
+ */
+static struct mtd_partition stmark2_partitions[] = {
+ {
+ .name = "U-Boot (1024K)",
+ .size = 0x10,
+ .offset = 0x0
+ }, {
+ .name = "Kernel+initramfs (7168K)",
+ .size = 0x70,
+ .offset = MTDPART_OFS_APPEND
+ }, {
+ .name = "Flash Free Space (8192K)",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND
+ }
+};
+
+static struct flash_platform_data stmark2_spi_flash_data = {
+ .name = "is25lp128",
+ .parts = stmark2_partitions,
+ .nr_parts = ARRAY_SIZE(stmark2_partitions),
+ .type = "is25lp128",
+};
+
+static struct spi_board_info stmark2_board_info[] __initdata = {
+ {
+ .modalias = "m25p80",
+ .max_speed_hz = 500,
+ .bus_num = 0,
+ .chip_select = 1,
+ .platform_data = _spi_flash_data,
+ .mode = SPI_MODE_3,
+ }
+};
+
+/* SPI controller data, SPI (0) */
+static struct fsl_dspi_platform_data dspi_spi0_info = {
+ .cs_num = 4,
+ .bus_num = 0,
+ .sck_cs_delay = 100,
+ .cs_sck_delay = 100,
+};
+
+static struct resource dspi_spi0_resource[] = {
+ [0] = {
+ .start = MCFDSPI_BASE0,
+ .end = MCFDSPI_BASE0 + 0xFF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 12,
+ .end = 13,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .start = MCF_IRQ_DSPI0,
+ .end = MCF_IRQ_DSPI0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* SPI controller, id = bus number */
+static struct platform_device dspi_spi0_device = {
+ .name = "fsl-dspi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(dspi_spi0_resource),
+ .resource = dspi_spi0_resource,
+ .dev = {
+ .platform_data = _spi0_info,
+ },
+};
+
+static struct platform_device *stmark2_devices[] __initdata = {
+ _spi0_device,
+};
+
+/*
+ * Note: proper pin-mux setup is mandatory for proper SPI functionality.
+ */
+static int __init init_stmark2(void)
+{
+ /* DSPI0, all pins as DSPI, and using CS1 */
+ __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
+ __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
+
+ /* Board gpio setup */
+ __raw_writeb(0x00, MCFGPIO_PAR_BE);
+ __raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
+ __raw_writeb(0x00, MCFGPIO_PAR_CS);
+ __raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
+
+ platform_add_devic
Fwd: Re: mcf54415, spi nor and SD drivers
Hi Greg, On 06/10/2017 06:04, Greg Ungerer wrote: Hi Angelo, On 06/10/17 09:06, Angelo Dureghello wrote: jfyi, i finally have dspi working on mcf54415. [ 8.31] m25p80 spi0.1: is25lp128 (16384 Kbytes) [ 8.32] Creating 3 MTD partitions on "is25lp128": [ 8.33] 0x-0x0010 : "U-Boot (1024K)" [ 9.75] ftl_cs: FTL header not found. [ 9.80] 0x0010-0x0080 : "Kernel+initramfs (7168K)" [ 11.23] ftl_cs: FTL header not found. [ 11.27] 0x0080-0x0100 : "Flash Free Space (8192K)" [ 12.01] random: crng init done [ 12.71] ftl_cs: FTL header not found. [ 12.80] Freeing unused kernel memory: 264K / # cat /proc/mtd dev: size erasesize name mtd0: 0010 1000 "U-Boot (1024K)" mtd1: 0070 1000 "Kernel+initramfs (7168K)" mtd2: 0080 1000 "Flash Free Space (8192K)" / # Nice work! welcome Changes to spi-fsl-dspi.c driver is minimal, just mainly had to get some few settings from board c file. Now the issue is how to proceed, likely, spi-list gouys would complain i add board/platform support to the driver. Is it better i send a patch for this stmark2 board.c before ? Sure, start with that. I don't mind if you send spi changes relevant to the 54411 here either for review. well, to post the stmark2 patch there is only one issue btw: stmark2.c contains a dspi-patch reference. #include The above is a new file of few lines i created for the dspi board.c support. So, maybe i should start posting the dspi patch. I attach the patches for your review, the patch n2 (spi-nor.c) is already under testing, so you can ignore it. Regards Greg Regards, Angelo Regards, Angelo Dureghello On 06/07/2017 15:07, Greg Ungerer wrote: Hi Angelo, On 06/07/17 18:36, angelo wrote: i designed here a new board with mcf54415. Testing a first mainline kernel. I would like to load a cramfs rootfs from SPI NOR (mtd, ftl) but actually i don't see the SPI NOR flash detected from dmesg. Next future step then would be load rootfs from SD. Seems there is no selectable driver for - SPI controller - SD (MMC) controller Those should be similar to existing drivers of some other freescale chip, or some new implementation is required ? Attaching dmesg. Most other ColdFire parts use the QSPI hardware module, and its driver is at drivers/spi/spi-coldfire-qspi.c. But, looking at the hardware reference manual for the mcf5441x family it contains a DSPI hardware module - and it looks quite different. That DSPI module looks to be similar to the one in the Freescale iMX parts, and its driver is at drivers/spi/spi-fsl-dspi.c. I don't know that anyone has used that on ColdFire with the mcf5441x parts, but that is where you should start I think. I haven't used any SD/MMC drivers on ColdFire so no advice on where to look for that one. If you are feeling adventurous you may want to look at: https://www.spinics.net/lists/linux-m68k/msg10057.html With a reasonably recent kernel you don't even need to generate a different user space filesystem and binaries. You can run your flat format non-MMU binaries on an MMU configured ColdFire system (as long as you have CONFIG_BINFMT_FLAT=y in your kernel config). I would love to be able to push this patch to mainline. Regards Greg Regards, Angelo Dureghello U-Boot 2017.05-00709-g9d9f074dfe-dirty (Jul 02 2017 - 19:50:16 +0200) CPU: Freescale MCF54410 (Mask:9f Version:2) CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz INP CLK 30 MHz VCO CLK 480 MHz SPI: ready DRAM: 128 MiB SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB device 0 offset 0x10, size 0x20 SF: 2097152 bytes @ 0x10 Read: OK ## Booting kernel from Legacy Image at 40001000 ... Image Name: mainline kernel Created: 2017-07-05 23:58:53 UTC Image Type: M68K Linux Kernel Image (uncompressed) Data Size: 1642496 Bytes = 1.6 MiB Load Address: 40001000 Entry Point: 40001000 Verifying Checksum ... OK Loading Kernel Image ... OK [ 0.00] Linux version 4.10.0-rc2stmark2-001-00020-g0f64df301240 (angelo@jerusalem) (gcc version 4.9.0 (crosstools-sysam-2016.04.16) ) #16 Thu Jul 6 01:58:52 CEST 2017 [ 0.00] uClinux with CPU COLDFIRE(m5441x) [ 0.00] COLDFIRE port done by Greg Ungerer, g...@snapgear.com [ 0.00] Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne [ 0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16320 [ 0.00] Kernel command line: console=ttyS0,115200 root=/dev/mtdblock3 mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs) rw rootwait [ 0.00] PID hash table entri
Re: mcf54415, spi nor and SD drivers
Hi Greg and all, jfyi, i finally have dspi working on mcf54415. [8.31] m25p80 spi0.1: is25lp128 (16384 Kbytes) [8.32] Creating 3 MTD partitions on "is25lp128": [8.33] 0x-0x0010 : "U-Boot (1024K)" [9.75] ftl_cs: FTL header not found. [9.80] 0x0010-0x0080 : "Kernel+initramfs (7168K)" [ 11.23] ftl_cs: FTL header not found. [ 11.27] 0x0080-0x0100 : "Flash Free Space (8192K)" [ 12.01] random: crng init done [ 12.71] ftl_cs: FTL header not found. [ 12.80] Freeing unused kernel memory: 264K / # cat /proc/mtd dev:size erasesize name mtd0: 0010 1000 "U-Boot (1024K)" mtd1: 0070 1000 "Kernel+initramfs (7168K)" mtd2: 0080 1000 "Flash Free Space (8192K)" / # Changes to spi-fsl-dspi.c driver is minimal, just mainly had to get some few settings from board c file. Now the issue is how to proceed, likely, spi-list gouys would complain i add board/platform support to the driver. Is it better i send a patch for this stmark2 board.c before ? Regards, Angelo Dureghello On 06/07/2017 15:07, Greg Ungerer wrote: Hi Angelo, On 06/07/17 18:36, angelo wrote: i designed here a new board with mcf54415. Testing a first mainline kernel. I would like to load a cramfs rootfs from SPI NOR (mtd, ftl) but actually i don't see the SPI NOR flash detected from dmesg. Next future step then would be load rootfs from SD. Seems there is no selectable driver for - SPI controller - SD (MMC) controller Those should be similar to existing drivers of some other freescale chip, or some new implementation is required ? Attaching dmesg. Most other ColdFire parts use the QSPI hardware module, and its driver is at drivers/spi/spi-coldfire-qspi.c. But, looking at the hardware reference manual for the mcf5441x family it contains a DSPI hardware module - and it looks quite different. That DSPI module looks to be similar to the one in the Freescale iMX parts, and its driver is at drivers/spi/spi-fsl-dspi.c. I don't know that anyone has used that on ColdFire with the mcf5441x parts, but that is where you should start I think. I haven't used any SD/MMC drivers on ColdFire so no advice on where to look for that one. If you are feeling adventurous you may want to look at: https://www.spinics.net/lists/linux-m68k/msg10057.html With a reasonably recent kernel you don't even need to generate a different user space filesystem and binaries. You can run your flat format non-MMU binaries on an MMU configured ColdFire system (as long as you have CONFIG_BINFMT_FLAT=y in your kernel config). I would love to be able to push this patch to mainline. Regards Greg Regards, Angelo Dureghello U-Boot 2017.05-00709-g9d9f074dfe-dirty (Jul 02 2017 - 19:50:16 +0200) CPU: Freescale MCF54410 (Mask:9f Version:2) CPU CLK 240 MHz BUS CLK 120 MHz FLB CLK 60 MHz INP CLK 30 MHz VCO CLK 480 MHz SPI: ready DRAM: 128 MiB SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB device 0 offset 0x10, size 0x20 SF: 2097152 bytes @ 0x10 Read: OK ## Booting kernel from Legacy Image at 40001000 ... Image Name: mainline kernel Created: 2017-07-05 23:58:53 UTC Image Type: M68K Linux Kernel Image (uncompressed) Data Size: 1642496 Bytes = 1.6 MiB Load Address: 40001000 Entry Point: 40001000 Verifying Checksum ... OK Loading Kernel Image ... OK [ 0.00] Linux version 4.10.0-rc2stmark2-001-00020-g0f64df301240 (angelo@jerusalem) (gcc version 4.9.0 (crosstools-sysam-2016.04.16) ) #16 Thu Jul 6 01:58:52 CEST 2017 [ 0.00] uClinux with CPU COLDFIRE(m5441x) [ 0.00] COLDFIRE port done by Greg Ungerer, g...@snapgear.com [ 0.00] Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne [ 0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16320 [ 0.00] Kernel command line: console=ttyS0,115200 root=/dev/mtdblock3 mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs) rw rootwait [ 0.00] PID hash table entries: 512 (order: -2, 2048 bytes) [ 0.00] Dentry cache hash table entries: 16384 (order: 3, 65536 bytes) [ 0.00] Inode-cache hash table entries: 8192 (order: 2, 32768 bytes) [ 0.00] Memory: 128664K/131072K available (1154K kernel code, 92K rwdata, 304K rodata, 48K init, 121K bss, 2408K reserved, 0K cma-reserved) [ 0.00] Virtual kernel memory layout: [ 0.00] vector : 0x4000 - 0x4400 ( 1 KiB) [ 0.00] kmap : 0x - 0x (4095 MiB) [ 0.00] vmalloc : 0x - 0xf - Message truncated - -- To unsubscribe from this list: sen
Re: [PATCH 0/3] m68k: coldfire MMU fixes
Dear Greg, On 08/09/2017 09:00, Greg Ungerer wrote: The following patch series fixes some issues with the initialization phase of the ColdFire MMU system startup. With these fixes applied we can also enable and run the ColdFire 5441x family of parts with their MMU enabled. arch/m68k/Kconfig.cpu |2 +- arch/m68k/coldfire/m54xx.c |4 arch/m68k/include/asm/mcfmmu.h |1 + arch/m68k/include/asm/mmu_context.h |1 - arch/m68k/kernel/setup_mm.c |2 ++ arch/m68k/mm/mcfmmu.c |4 ++-- 6 files changed, 6 insertions(+), 8 deletions(-) I just applied this patchset to fresh master and re-verified that enabling MMU works on my mcf54415 based board. Tested-by: Angelo Dureghello <ang...@sysam.it> Regards, Angelo Dureghello -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-m68k" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
