[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken
, VTypeState ,
break;
if (!RISCVVType::isValidLMUL(Lmul, Fractional))
break;
+
+if (Fractional) {
+ unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+ unsigned MinLMUL = ELEN / 8;
+ if (Lmul > MinLMUL)
+Warning(
+Tok.getLoc(),
+Twine("The use of vtype encodings with LMUL < SEWMIN/ELEN == mf") +
+Twine(MinLMUL) + Twine(" is reserved"));
topperc wrote:
nevermind. I see it is reserved.
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for
Application Processors), 'Zve32x' (Vector Extensions for Embedded
Processors){{$}}
# CHECK-UNKNOWN: 0d757657
vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with
all RVV implementations{{$}}
topperc wrote:
Nevermind I see this is mentioned later.
```
The use of vtype encodings with LMUL < SEWMIN/ELEN is reserved, but
implementations can set vill if they do not support these con gurations.**
```
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma
vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible
with all RVV implementations{{$}}
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for
Application Processors), 'Zve32x' (Vector Extensions for Embedded
Processors){{$}}
# CHECK-UNKNOWN: 0d757657
vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 8 may not be compatible with
all RVV implementations{{$}}
topperc wrote:
> Ok, that seems reasonable. Should we maybe then reword the LMUL < SEWMIN/ELEN
> case to mention that the encoding is actually reserved, whereas for SEW >
> LMUL * ELEN it may just not be compatible
I don't think it is reserved. This is the paragraph from the spec
```
Implementations must provide fractional LMUL settings that allow the narrowest
supported type to occupy a fraction of a vector register corresponding to the
ratio of the narrowest supported type’s width to that of the largest supported
type’s width. In general, the requirement is to support LMUL ≥ SEWMIN/ELEN,
where SEWMIN is the narrowest supported SEW value and ELEN is the widest
supported SEW value. In the standard extensions, SEWMIN=8. For standard vector
extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For
standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8
must be supported.
```
It doesn't say it can't be supported. It only says what must be supported.
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken
, VTypeState ,
break;
if (!RISCVVType::isValidLMUL(Lmul, Fractional))
break;
+
+if (Fractional) {
+ unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+ unsigned MinLMUL = ELEN / 8;
+ if (Lmul > MinLMUL)
+Warning(
+Tok.getLoc(),
+Twine("The use of vtype encodings with LMUL < SEWMIN/ELEN == mf") +
+Twine(MinLMUL) + Twine(" is reserved"));
topperc wrote:
Is it actually reserved? I thought it was just implementation defined.
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken
, VTypeState ,
break;
if (!RISCVVType::isValidLMUL(Lmul, Fractional))
break;
+
+if (Fractional) {
+ unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+ unsigned MinLMUL = ELEN / 8;
+ if (Lmul > MinLMUL)
+Warning(
+Tok.getLoc(),
+Twine("The use of vtype encodings with LMUL < SEWMIN/ELEN == mf") +
topperc wrote:
Do no capitalize the first letter of diagnostics
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -2211,6 +2223,18 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector
) {
if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
+if (Fractional) {
+ unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+ unsigned MaxSEW = ELEN / Lmul;
+ // If MaxSEW < 8, we should have printed warning about reserved LMUL.
+ if (MaxSEW >= 8 && Sew > MaxSEW)
+Warning(
+SEWLoc,
+Twine("The use of vtype encodings with SEW > ") + Twine(MaxSEW) +
topperc wrote:
I don't think you need `Twine` around the strings.
https://www.llvm.org/docs/CodingStandards.html#error-and-warning-messages
You can probably drop the word "The" at the beginning.
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)
@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken
, VTypeState ,
break;
if (!RISCVVType::isValidLMUL(Lmul, Fractional))
break;
+
+if (Fractional) {
+ unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 : 32;
+ unsigned MinLMUL = ELEN / 8;
+ if (Lmul > MinLMUL)
+Warning(
+Tok.getLoc(),
+Twine("The use of vtype encodings with LMUL < SEWMIN/ELEN == mf") +
topperc wrote:
I don't think you need `Twine` around the strings. Probably just on the
`MinLMUL`
https://github.com/llvm/llvm-project/pull/94313
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[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > @topperc (or anyone else). If you would like to add a note about this fix in > the release notes (completely optional). Please reply to this comment with a > one or two sentence description of the fix. When you are done, please add the > release:note label to this PR. `-Xclang -target-feature -Xclang +unaligned-scalar-mem` can be used to enable unaligned scalar memory accesses for CPUs that do not support unaligned vector accesses. `-mno-strict-align` will enable unaligned scalar and vector memory accesses. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > @topperc Can this be merged as is? There might not be time to get an updated > patch merged before the last release. I just pushed a modified patch. What is the timeline for the last release? https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/92143
>From e18e442947da7801c915c04e34e397464eca5034 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Thu, 16 May 2024 12:27:05 -0700
Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in
clang 17.
This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:
---
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 5 +++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 5 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++---
llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4
llvm/test/CodeGen/RISCV/memcpy.ll| 4
llvm/test/CodeGen/RISCV/memset-inline.ll | 4
llvm/test/CodeGen/RISCV/pr56110.ll | 1 +
llvm/test/CodeGen/RISCV/unaligned-load-store.ll | 4
8 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 0a314fdd41cbe..89207640ee54a 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -317,8 +317,9 @@ bool
RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock ,
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
-// FIXME: Zdinx RV32 can not work on unaligned memory.
-assert(!STI->hasFastUnalignedAccess());
+// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+assert(!STI->hasFastUnalignedAccess() &&
+ !STI->enableUnalignedScalarMem());
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26451c80f57b4..1bb6b6a561f4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1025,6 +1025,11 @@ def FeatureFastUnalignedAccess
"true", "Has reasonably performant unaligned "
"loads and stores (both scalar and vector)">;
+def FeatureUnalignedScalarMem
+ : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
+ "true", "Has reasonably performant unaligned scalar "
+ "loads and stores">;
+
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d46093b9e260a..3fe7ddfdd4279 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1883,7 +1883,8 @@ bool
RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt ,
// replace. If we don't support unaligned scalar mem, prefer the constant
// pool.
// TODO: Can the caller pass down the alignment?
- if (!Subtarget.hasFastUnalignedAccess())
+ if (!Subtarget.hasFastUnalignedAccess() &&
+ !Subtarget.enableUnalignedScalarMem())
return true;
// Prefer to keep the load if it would require many instructions.
@@ -19772,8 +19773,10 @@ bool
RISCVTargetLowering::allowsMisalignedMemoryAccesses(
unsigned *Fast) const {
if (!VT.isVector()) {
if (Fast)
- *Fast = Subtarget.hasFastUnalignedAccess();
-return Subtarget.hasFastUnalignedAccess();
+ *Fast = Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
+return Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
}
// All vector implementations must support element alignment
diff --git a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
index 343695ee37da8..709b8264b5833 100644
--- a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
+; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
+; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
; --
; Fully unaligned cases
diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll
b/llvm/test/CodeGen/RISCV/memcpy.ll
index 12ec0881b20d9..f8f5d25947d7f 100644
--- a/llvm/test/CodeGen/RISCV/memcpy.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN: llc < %s -mtriple=riscv64
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > I'm not strongly opposed to this or anything, but it feels questionable to be > doing a backport to change the target-feature syntax. My understand is that > these are purely internal names. This isn't a documented public interface. It isn't documented, but some users were using `-Xclang -target-feature -Xclang -unaligned-scalar-mem` with clang 17 to get this functionality. -mno-strict-align does not exist in clang 17. I'm going to experiment with reworking this patch to make `-Xclang -target-feature -Xclang -unaligned-scalar-mem` work and also leave `fast-unaligned-access` working to cover both scalar and vector. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > I don't think we need to backport this at all. None of the in tree cpus fall > into the category where the distinction is important, and I don't feel we > have any obligation to backport support for our of tree forks. There's no out of tree fork involved here. The bug reporter was using stock LLVM to compile for the Kendryte K230 board. A developer from the RISE System Libraries group reported this same issue in a presentation yesterday. It is impacting their work on chromium zlib on the same K230 board. zlib does scalar unaligned accesses. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: Maybe I could make fast-unaligned-access only apply to scalar to avoid a name change. And give a new flag for vector? There's not a lot of RISC-V vector hardware available yet. One of the CPUs that is available only supports unaligned scalars and not vectors. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
topperc wrote: > @topperc Do you have any strong objections to backporting this? This looks > small to me and I think it's OK to fix long-standing bugs. No objection. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > > Note that backporting this may require changes for LLVM users (I know that > > it will require rustc changes at least). This may not be a good candidate > > for the last 18.1 point release. > > Can you point me to the relevant rust code? I found this line which looks > like it wasn't updated for llvm 18. > https://github.com/rust-lang/rust/blob/8387315ab3c26a57a1f53a90f188f0bc88514bca/compiler/rustc_target/src/target_features.rs#L284 Or I guess that line was changed for llvm 19? https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
topperc wrote: > Note that backporting this may require changes for LLVM users (I know that it > will require rustc changes at least). This may not be a good candidate for > the last 18.1 point release. Can you point me to the relevant rust code? I found this line which looks like it wasn't updated for llvm 18. https://github.com/rust-lang/rust/blob/8387315ab3c26a57a1f53a90f188f0bc88514bca/compiler/rustc_target/src/target_features.rs#L284 https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/92143
Backport 9067070d91e9d8cdd8509ffa56a076f08a3d7281 for #92134
>From 5c5c57534751621f775dca5776af10e1870e6eb8 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Tue, 16 Apr 2024 15:40:32 -0700
Subject: [PATCH] [RISCV] Re-separate unaligned scalar and vector memory
features in the backend. (#88954)
This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.
As #88029 shows, there exists hardware that only supports unaligned
scalar.
I'm leaving how this gets exposed to the clang interface to a future
patch.
---
clang/lib/Basic/Targets/RISCV.cpp| 3 ++-
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 10 +++---
clang/test/Driver/riscv-features.c | 4 ++--
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 13 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 16
llvm/lib/Target/RISCV/RISCVProcessors.td | 6 --
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 ++--
llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/memcpy.ll| 4 ++--
llvm/test/CodeGen/RISCV/memset-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/pr56110.ll | 2 +-
.../CodeGen/RISCV/riscv-func-target-feature.ll | 2 +-
.../RISCV/rvv/concat-vectors-constant-stride.ll | 4 ++--
.../rvv/fixed-vectors-strided-load-combine.ll| 2 +-
.../CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/memset-inline.ll | 4 ++--
.../CodeGen/RISCV/rvv/unaligned-loads-stores.ll | 4 ++--
llvm/test/CodeGen/RISCV/unaligned-load-store.ll | 4 ++--
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp| 12 ++--
21 files changed, 67 insertions(+), 47 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index c71b2e9eeb6c1..2bd71a499b63c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -352,7 +352,8 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector ,
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
HasLegalHalfType = true;
- FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
+ FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem")
&&
+llvm::is_contained(Features, "+unaligned-vector-mem");
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index a46b44f9ad2b2..136a5b968cf76 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -68,8 +68,10 @@ static void getRISCFeaturesFromMcpu(const Driver , const
Arg *A,
<< A->getSpelling() << Mcpu;
}
- if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
-Features.push_back("+fast-unaligned-access");
+ if (llvm::RISCV::hasFastUnalignedAccess(Mcpu)) {
+Features.push_back("+unaligned-scalar-mem");
+Features.push_back("+unaligned-vector-mem");
+ }
}
void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -169,7 +171,9 @@ void riscv::getRISCVTargetFeatures(const Driver , const
llvm::Triple ,
// -mno-unaligned-access is default, unless -munaligned-access is specified.
AddTargetFeature(Args, Features, options::OPT_munaligned_access,
- options::OPT_mno_unaligned_access, "fast-unaligned-access");
+ options::OPT_mno_unaligned_access, "unaligned-scalar-mem");
+ AddTargetFeature(Args, Features, options::OPT_munaligned_access,
+ options::OPT_mno_unaligned_access, "unaligned-vector-mem");
// Now add any that the user explicitly requested on the command line,
// which may override the defaults.
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index d3700f71aa7e1..617616dc3f0b5 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -32,8 +32,8 @@
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 |
FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 |
FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
-// FAST-UNALIGNED-ACCESS: "-target-feature" "+fast-unaligned-access"
-// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-fast-unaligned-access"
+// FAST-UNALIGNED-ACCESS: "-target-feature" "+unaligned-scalar-mem"
"-target-feature" "+unaligned-vector-mem"
+// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-unaligned-scalar-mem"
"-target-feature" "-unaligned-vector-mem"
// RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
// RUN: |
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
topperc wrote: > Can you briefly summarize why this is important to backport? At first glance, > this is only relevant for LTO with mixed architecture specifications, > which... I can see someone might want it, I guess, but it seems pretty easy > to work around not having it. It's not just mixed architecture specifications. Even in a non-mixed situation the Compressed instruction flag in the ELF header doesn't get set correctly for LTO. Prior to these patches, the flag is set using the subtarget features from the TargetMachine which are empty in an LTO build. The linker needs this flag to do linker relaxation for alignment correctly. The workaround is to pass `-Wl,-plugin-opt=-mattr=+c`. CC @ilovepi who asked me to try to backport it. https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/91514
>From ee109e3627e5b93297bfc7908f684eedb5feb5ec Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Tue, 13 Feb 2024 16:17:50 -0800
Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in
IR. (#80760)
In an LTO build, we don't set the ELF attributes to indicate what
extensions were compiled with. The target CPU/Attrs in
RISCVTargetMachine do not get set for an LTO build. Each function gets a
target-cpu/feature attribute, but this isn't usable to set ELF attributs
since we wouldn't know what function to use. We can't just once since it
might have been compiler with an attribute likes target_verson.
This patch adds the ISA as Module metadata so we can retrieve it in the
backend. Individual translation units can still be compiled with
different strings so we need to collect the unique set when Modules are
merged.
The backend will need to combine the unique ISA strings to produce a
single value for the ELF attributes. This will be done in a separate
patch.
---
clang/lib/CodeGen/CodeGenModule.cpp | 14 +
.../RISCV/ntlh-intrinsics/riscv32-zihintntl.c | 350 +-
.../test/CodeGen/RISCV/riscv-metadata-arch.c | 20 +
3 files changed, 209 insertions(+), 175 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-metadata-arch.c
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 1280bcd36de94..eb13cd40eb8a2 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -67,6 +67,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ConvertUTF.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/Support/xxhash.h"
#include "llvm/TargetParser/Triple.h"
@@ -1059,6 +1060,19 @@ void CodeGenModule::Release() {
llvm::LLVMContext = TheModule.getContext();
getModule().addModuleFlag(llvm::Module::Error, "target-abi",
llvm::MDString::get(Ctx, ABIStr));
+
+// Add the canonical ISA string as metadata so the backend can set the ELF
+// attributes correctly. We use AppendUnique so LTO will keep all of the
+// unique ISA strings that were linked together.
+const std::vector =
+getTarget().getTargetOpts().Features;
+auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
+Arch == llvm::Triple::riscv64 ? 64 : 32, Features);
+if (!errorToBool(ParseResult.takeError()))
+ getModule().addModuleFlag(
+ llvm::Module::AppendUnique, "riscv-isa",
+ llvm::MDNode::get(
+ Ctx, llvm::MDString::get(Ctx, (*ParseResult)->toString(;
}
if (CodeGenOpts.SanitizeCfiCrossDso) {
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 897edbc6450af..b11c2ca010e7c 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -28,190 +28,190 @@ vint8m1_t *scvc1, *scvc2;
// clang-format off
void ntl_all_sizes() { // CHECK-LABEL:
ntl_all_sizes
- uc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- sc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- us = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ss = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ui = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- si = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- ull = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- sll = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- h1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- f1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- d1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- v4si1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); //
CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4,
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/91514
Resolves #91513
>From f45df1cf1b74957e2f9609b982e964654f9af824 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Tue, 13 Feb 2024 16:17:50 -0800
Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in
IR. (#80760)
In an LTO build, we don't set the ELF attributes to indicate what
extensions were compiled with. The target CPU/Attrs in
RISCVTargetMachine do not get set for an LTO build. Each function gets a
target-cpu/feature attribute, but this isn't usable to set ELF attributs
since we wouldn't know what function to use. We can't just once since it
might have been compiler with an attribute likes target_verson.
This patch adds the ISA as Module metadata so we can retrieve it in the
backend. Individual translation units can still be compiled with
different strings so we need to collect the unique set when Modules are
merged.
The backend will need to combine the unique ISA strings to produce a
single value for the ELF attributes. This will be done in a separate
patch.
---
clang/lib/CodeGen/CodeGenModule.cpp | 14 +
.../RISCV/ntlh-intrinsics/riscv32-zihintntl.c | 350 +-
.../test/CodeGen/RISCV/riscv-metadata-arch.c | 20 +
3 files changed, 209 insertions(+), 175 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-metadata-arch.c
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 1280bcd36de94..f576cd8b853c2 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -67,6 +67,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ConvertUTF.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/Support/xxhash.h"
#include "llvm/TargetParser/Triple.h"
@@ -1059,6 +1060,19 @@ void CodeGenModule::Release() {
llvm::LLVMContext = TheModule.getContext();
getModule().addModuleFlag(llvm::Module::Error, "target-abi",
llvm::MDString::get(Ctx, ABIStr));
+
+// Add the canonical ISA string as metadata so the backend can set the ELF
+// attributes correctly. We use AppendUnique so LTO will keep all of the
+// unique ISA strings that were linked together.
+const std::vector =
+getTarget().getTargetOpts().Features;
+auto ParseResult =
+llvm::RISCVISAInfo::parseFeatures(T.isRISCV64() ? 64 : 32, Features);
+if (!errorToBool(ParseResult.takeError()))
+ getModule().addModuleFlag(
+ llvm::Module::AppendUnique, "riscv-isa",
+ llvm::MDNode::get(
+ Ctx, llvm::MDString::get(Ctx, (*ParseResult)->toString(;
}
if (CodeGenOpts.SanitizeCfiCrossDso) {
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 897edbc6450af..b11c2ca010e7c 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -28,190 +28,190 @@ vint8m1_t *scvc1, *scvc2;
// clang-format off
void ntl_all_sizes() { // CHECK-LABEL:
ntl_all_sizes
- uc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- sc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- us = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ss = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ui = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- si = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- ull = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- sll = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- h1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- f1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- d1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- v4si1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); //
CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4,
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
topperc wrote: @AtariDreams This bug has existed since at least LLVM 10. What makes it a candidate for backporting? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [X86] Enable EVEX512 when host CPU has AVX512 (#90479) (PR #90545)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90545 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV][ISel] Fix types in `tryFoldSelectIntoOp` (#90659) (PR #90682)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)
@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store(
%passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64)
define @vpmerge_vleff( %passthru, ptr %p,
%m, i32 zeroext %vl) {
; CHECK-LABEL: vpmerge_vleff:
; CHECK: # %bb.0:
-; CHECK-NEXT:vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT:vle32ff.v v9, (a0)
-; CHECK-NEXT:vsetvli zero, a1, e32, m1, tu, ma
-; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:vle32ff.v v8, (a0), v0.t
topperc wrote:
I'm trying to decide if this is correct. It's certainly a weird test case. You
would normally want the vp.merge to use vl produced by vleff.
If the VL gets trimmed by the vleff, the elements between the input VL and the
trimmed VL are undefined if the mask bit for those elements are non-zero. The
spec allows hardware to write the active elements past the trimmed VL to any
value.
I think we're ok here. If vleff trims any elements they would be undefined in
`%b`. The vp.merge would propagate them if the mask bit is non-zero. If the
mask is 0 the vp.merge would replace them with passthru. That seems to be what
the combined vp.merge would do.
https://github.com/llvm/llvm-project/pull/90049
___
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[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedXiangShanNanHu.td" +//===--===// +// RISC-V profiles supported. +//===--===// + +include "RISCVProfiles.td" topperc wrote: Why not keep this next to RISCVFeatures.td? https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)
topperc wrote: > For saturating instructions, they may write vxsat. This is like floating-point instructions that may write fflags, but we don't model floating-point instructions as hasSideEffects=1. That's because floating point instructions use mayRaiseFPExceptions=1. And STRICT_* nodes set don't set the NoFPExcept bit in MIFlags. Though we don't have a story for how to make reading FFLAGS work with riscv.* intrinsics. That's an issue on all targets as there is no "constrained" or "strict" support for target specific intrinsics. https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [X86] Fix miscompile in combineShiftRightArithmetic (PR #86728)
topperc wrote: > > @phoebewang What do you think about backporting this? > > I didn't review on it. Maybe @topperc can evaluate it. I think this is ok to backport. https://github.com/llvm/llvm-project/pull/86728 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Revert "[Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072)" (PR #88818)
topperc wrote: > > Hi @nikic (or anyone else). If you would like to add a note about this fix > > in the release notes (completely optional). Please reply to this comment > > with a one or two sentence description of the fix. > > I'm not sure if this description is accurate: Fix the issue where the atomic > instructions on MIPS do not return the correct results. > > cc @topperc Probably should mention min/max specifically. https://github.com/llvm/llvm-project/pull/88818 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)
topperc wrote: > s/master/main/ in the url to get the current version. (master "works" but > it's frozen in time; main will track future changes.) > > otherwise lgtm... Probably someone should update AArch64 which has the same comment? https://github.com/llvm/llvm-project/pull/87672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHECK-NEXT: $v7 = VMV1R_V $v13 -; CHECK-NEXT: $v8 = VMV1R_V $v14 -; CHECK-NEXT: $v9 = VMV1R_V $v15 +; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 +; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 +; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 ; CHECK-NEXT: $v10 = VMV1R_V $v16 -; CHECK-NEXT: $v22 = VMV1R_V $v16 -; CHECK-NEXT: $v21 = VMV1R_V $v15 -; CHECK-NEXT: $v20 = VMV1R_V $v14 -; CHECK-NEXT: $v19 = VMV1R_V $v13 -; CHECK-NEXT: $v18 = VMV1R_V $v12 -; CHECK-NEXT: $v17 = VMV1R_V $v11 +; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2 +; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 +; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 ; CHECK-NEXT: $v16 = VMV1R_V $v10 topperc wrote: And the copy for v11 into v17 is missing. https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHECK-NEXT: $v7 = VMV1R_V $v13 -; CHECK-NEXT: $v8 = VMV1R_V $v14 -; CHECK-NEXT: $v9 = VMV1R_V $v15 +; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 +; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 +; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 ; CHECK-NEXT: $v10 = VMV1R_V $v16 -; CHECK-NEXT: $v22 = VMV1R_V $v16 -; CHECK-NEXT: $v21 = VMV1R_V $v15 -; CHECK-NEXT: $v20 = VMV1R_V $v14 -; CHECK-NEXT: $v19 = VMV1R_V $v13 -; CHECK-NEXT: $v18 = VMV1R_V $v12 -; CHECK-NEXT: $v17 = VMV1R_V $v11 +; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2 topperc wrote: This copies v16-v17 to v22-23, but the copy was for `$v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16` so v23 shouldn't be touched. https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock ,
}
// VR->VR copies.
- if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
-return;
- }
-
- if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2);
-return;
- }
-
- if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4);
-return;
- }
-
- if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8);
-return;
- }
-
- if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/2);
-return;
- }
-
- if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/2);
-return;
- }
-
- if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4,
- /*NF=*/2);
-return;
- }
-
- if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/3);
-return;
- }
-
- if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/3);
-return;
- }
-
- if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/4);
-return;
- }
-
- if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
- /*NF=*/4);
-return;
- }
-
- if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/5);
-return;
- }
-
- if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/6);
-return;
- }
-
- if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/7);
-return;
- }
-
- if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
- /*NF=*/8);
-return;
+ for (const auto :
+ {RISCV::VRRegClass, RISCV::VRM2RegClass, RISCV::VRM4RegClass,
topperc wrote:
What is the type of this initializer list? Is it making copies of all of the
register classes?
https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)
@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext
%val) {
; MIPSELR6-NEXT: $BB6_1: # %entry
; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1
; MIPSELR6-NEXT:ll $2, 0($6)
-; MIPSELR6-NEXT:and $2, $2, $8
topperc wrote:
@yingopq I'm not really a Mips expert so I'm not sure. But my understanding is
that the and was clearing the upper and lower bits so that the unsigned min/max
would only consider the byte or half word that it should and not any other
values around it in memory.
https://github.com/llvm/llvm-project/pull/84566
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[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)
@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext
%val) {
; MIPSELR6-NEXT: $BB6_1: # %entry
; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1
; MIPSELR6-NEXT:ll $2, 0($6)
-; MIPSELR6-NEXT:and $2, $2, $8
topperc wrote:
@brad0 I think I missed this in the previous review. Why is it ok to remove the
AND from the unsigned tests? My original command about the AND being unnecssary
was for the signed cases.
https://github.com/llvm/llvm-project/pull/84566
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[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
topperc wrote: > > JFYI, I don't find the AArch64 data particularly convincing for RISCV. The > > magnitude of the change even on AArch64 is small, and could easily be swung > > one direction or the other by differences in implementation between the > > backends. > > Yeah! The result will differ for different targets/CPUs. One RISCV data for > SPEC 2006 (which is not universal I think) on an OoO RISCV CPU, options: > `-march=rv64gc_zba_zbb_zicond -O3`: > > ``` > 400.perlbench0.538% > 401.bzip20.018% > 403.gcc 0.105% > 429.mcf 1.028% > 445.gobmk-0.221% > 456.hmmer1.582% > 458.sjeng-0.026% > 462.libquantum -0.090% > 464.h264ref 0.905% > 471.omnetpp -0.776% > 473.astar0.205% > ``` > > The geomean is: 0.295%. The result can be better with PGO I think (haven't > tried it). Some related discussions: > https://discourse.llvm.org/t/rfc-cmov-vs-branch-optimization. So I think we > can be just like AArch64, make it a tune feature and processors can add it if > needed. Do we have any data without Zicond? The worst case Zicond sequence is czero.eqz+czero.nez+or which is kind of expensive. Curious if this is pointing to Zicond being used too aggressively. https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", + "true", "Prefer likely predicted branches over selects">; + +def FeatureEnableSelectOptimize + : SubtargetFeature<"enable-select-opt", "EnableSelectOptimize", "true", +"Enable the select optimize pass for select loop heuristics">; topperc wrote: This needs to be indented 1 more space https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
> I think the impact won't be large, since the pass is early out before these
> analysises actully run when enableSelectOptimize returns false .
The pass manager will run the analysis passes before the runOnFunction in the
select optimize pass gets called. Unless those analysis passes do lazy updates
and only compute something when they are queried, they will run before the
early out.
https://github.com/llvm/llvm-project/pull/80124
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[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned VVOpc, VIOpc;
- switch (LMul) {
- default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
- case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
- case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
- case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
- }
-
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
-}
- }
-
- if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
- }
-
- int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal;
bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
- }
-
- for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx +
I));
-if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+ unsigned NumRegs = NF * LMulVal;
+ bool ReversedCopy =
+ forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+ unsigned I = 0;
+ while (I != NumRegs) {
+auto GetCopyInfo =
+[&](unsigned SrcReg,
+unsigned DstReg) -> std::tuple {
+ unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+ unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+ if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)
+return {8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
RISCV::PseudoVMV_V_V_M8,
+RISCV::PseudoVMV_V_I_M8};
+ if (!(SrcEncoding & 0b11) && !(DstEncoding & 0b11) && I + 4 <= NumRegs)
+return {4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
RISCV::PseudoVMV_V_V_M4,
+RISCV::PseudoVMV_V_I_M4};
+ if (!(SrcEncoding & 0b1) && !(DstEncoding & 0b1) && I + 2 <= NumRegs)
+return {2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
RISCV::PseudoVMV_V_V_M2,
+RISCV::PseudoVMV_V_I_M2};
+ return {1, RISCV::VRRegClass, RISCV::VMV1R_V, RISCV::PseudoVMV_V_V_M1,
+ RISCV::PseudoVMV_V_I_M1};
+};
+
+auto [NumCopied, RegClass, Opc, VVOpc, VIOpc] = GetCopyInfo(SrcReg,
DstReg);
+
+MachineBasicBlock::const_iterator DefMBBI;
+if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
topperc wrote:
I don't think we can use vmv.v.v if we use a larger register than the LMul that
is passed to isConvertibleToVMV_V_V
https://github.com/llvm/llvm-project/pull/84455
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned VVOpc, VIOpc;
- switch (LMul) {
- default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
- case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
- case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
- case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
- }
-
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
-}
- }
-
- if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
- }
-
- int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal;
bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
- }
-
- for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx +
I));
-if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+ unsigned NumRegs = NF * LMulVal;
+ bool ReversedCopy =
+ forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+ unsigned I = 0;
+ while (I != NumRegs) {
+auto GetCopyInfo =
+[&](unsigned SrcReg,
+unsigned DstReg) -> std::tuple {
+ unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+ unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+ if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)
+return {8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
RISCV::PseudoVMV_V_V_M8,
+RISCV::PseudoVMV_V_I_M8};
+ if (!(SrcEncoding & 0b11) && !(DstEncoding & 0b11) && I + 4 <= NumRegs)
+return {4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
RISCV::PseudoVMV_V_V_M4,
+RISCV::PseudoVMV_V_I_M4};
+ if (!(SrcEncoding & 0b1) && !(DstEncoding & 0b1) && I + 2 <= NumRegs)
+return {2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
RISCV::PseudoVMV_V_V_M2,
+RISCV::PseudoVMV_V_I_M2};
+ return {1, RISCV::VRRegClass, RISCV::VMV1R_V, RISCV::PseudoVMV_V_V_M1,
+ RISCV::PseudoVMV_V_I_M1};
+};
+
+auto [NumCopied, RegClass, Opc, VVOpc, VIOpc] = GetCopyInfo(SrcReg,
DstReg);
+
+MachineBasicBlock::const_iterator DefMBBI;
+if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
+ Opc = VVOpc;
+
+ if (DefMBBI->getOpcode() == VIOpc) {
topperc wrote:
Drop curly braces
https://github.com/llvm/llvm-project/pull/84455
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned VVOpc, VIOpc;
- switch (LMul) {
- default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
- case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
- case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
- case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
- }
-
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
-}
- }
-
- if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
- }
-
- int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal;
bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
- }
-
- for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx +
I));
-if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+ unsigned NumRegs = NF * LMulVal;
+ bool ReversedCopy =
+ forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+ unsigned I = 0;
+ while (I != NumRegs) {
+auto GetCopyInfo =
+[&](unsigned SrcReg,
+unsigned DstReg) -> std::tuple {
+ unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+ unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+ if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)
+return {8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
RISCV::PseudoVMV_V_V_M8,
+RISCV::PseudoVMV_V_I_M8};
+ if (!(SrcEncoding & 0b11) && !(DstEncoding & 0b11) && I + 4 <= NumRegs)
+return {4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
RISCV::PseudoVMV_V_V_M4,
+RISCV::PseudoVMV_V_I_M4};
+ if (!(SrcEncoding & 0b1) && !(DstEncoding & 0b1) && I + 2 <= NumRegs)
+return {2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
RISCV::PseudoVMV_V_V_M2,
+RISCV::PseudoVMV_V_I_M2};
+ return {1, RISCV::VRRegClass, RISCV::VMV1R_V, RISCV::PseudoVMV_V_V_M1,
+ RISCV::PseudoVMV_V_I_M1};
+};
+
+auto [NumCopied, RegClass, Opc, VVOpc, VIOpc] = GetCopyInfo(SrcReg,
DstReg);
+
+MachineBasicBlock::const_iterator DefMBBI;
+if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
+ Opc = VVOpc;
+
+ if (DefMBBI->getOpcode() == VIOpc) {
+Opc = VIOpc;
+ }
}
+
+for (MCPhysReg Reg : RegClass.getRegisters()) {
topperc wrote:
llvm::find?
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned VVOpc, VIOpc;
- switch (LMul) {
- default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
- case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
- case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
- case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
- }
-
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
-}
- }
-
- if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
- }
-
- int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal;
bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
- }
-
- for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx +
I));
-if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+ unsigned NumRegs = NF * LMulVal;
+ bool ReversedCopy =
+ forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+ unsigned I = 0;
+ while (I != NumRegs) {
+auto GetCopyInfo =
+[&](unsigned SrcReg,
+unsigned DstReg) -> std::tuple {
+ unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
+ unsigned DstEncoding = TRI->getEncodingValue(DstReg);
+ if (!(SrcEncoding & 0b111) && !(DstEncoding & 0b111) && I + 8 <= NumRegs)
+return {8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
RISCV::PseudoVMV_V_V_M8,
+RISCV::PseudoVMV_V_I_M8};
+ if (!(SrcEncoding & 0b11) && !(DstEncoding & 0b11) && I + 4 <= NumRegs)
+return {4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
RISCV::PseudoVMV_V_V_M4,
+RISCV::PseudoVMV_V_I_M4};
+ if (!(SrcEncoding & 0b1) && !(DstEncoding & 0b1) && I + 2 <= NumRegs)
+return {2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
RISCV::PseudoVMV_V_V_M2,
+RISCV::PseudoVMV_V_I_M2};
+ return {1, RISCV::VRRegClass, RISCV::VMV1R_V, RISCV::PseudoVMV_V_V_M1,
+ RISCV::PseudoVMV_V_I_M1};
+};
+
+auto [NumCopied, RegClass, Opc, VVOpc, VIOpc] = GetCopyInfo(SrcReg,
DstReg);
+
+MachineBasicBlock::const_iterator DefMBBI;
+if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
+ Opc = VVOpc;
+
+ if (DefMBBI->getOpcode() == VIOpc) {
+Opc = VIOpc;
+ }
}
+
+for (MCPhysReg Reg : RegClass.getRegisters()) {
+ if (TRI->getEncodingValue(Reg) ==
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)
@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock
,
RISCVII::VLMUL LMul, unsigned NF) const
{
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
- unsigned Opc;
- unsigned SubRegIdx;
- unsigned VVOpc, VIOpc;
- switch (LMul) {
- default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
- case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
- case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
- case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
- case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
- }
-
- bool UseVMV_V_V = false;
- bool UseVMV_V_I = false;
- MachineBasicBlock::const_iterator DefMBBI;
- if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
- UseVMV_V_I = true;
- Opc = VIOpc;
-}
- }
-
- if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
- MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
- }
-
- int I = 0, End = NF, Incr = 1;
unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
unsigned DstEncoding = TRI->getEncodingValue(DstReg);
unsigned LMulVal;
bool Fractional;
std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul);
assert(!Fractional && "It is impossible be fractional lmul here.");
- if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) {
-I = NF - 1;
-End = -1;
-Incr = -1;
- }
-
- for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx +
I));
-if (UseVMV_V_V)
- MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
- MIB = MIB.add(DefMBBI->getOperand(2));
-else
- MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
- getKillRegState(KillSrc));
-if (UseVMV_V_V) {
- const MCInstrDesc = DefMBBI->getDesc();
- MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
- MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
- MIB.addImm(0);// tu, mu
- MIB.addReg(RISCV::VL, RegState::Implicit);
- MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+ unsigned NumRegs = NF * LMulVal;
+ bool ReversedCopy =
+ forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs);
+
+ unsigned I = 0;
+ while (I != NumRegs) {
+auto GetCopyInfo =
topperc wrote:
Can this be outside the loop?
https://github.com/llvm/llvm-project/pull/84455
___
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
@@ -14,12 +14,33 @@
#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#define GET_REGINFO_HEADER
#include "RISCVGenRegisterInfo.inc"
namespace llvm {
+enum {
+ // The VLMul value of this RegisterClass.
+ VLMulShift = 0,
+ VLMulShiftMask = 0b111 << VLMulShift,
+
+ // The NF value of this RegisterClass.
+ NFShift = VLMulShift + 3,
+ NFShiftMask = 0b111 << NFShift,
+};
+
+/// \returns the LMUL for the register class.
+static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) {
topperc wrote:
Or maybe RISCRI since we the other TSFLags is in RISCVII where I think `II` is
Instruction Info.
https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)
@@ -14,12 +14,33 @@
#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#define GET_REGINFO_HEADER
#include "RISCVGenRegisterInfo.inc"
namespace llvm {
+enum {
+ // The VLMul value of this RegisterClass.
+ VLMulShift = 0,
+ VLMulShiftMask = 0b111 << VLMulShift,
+
+ // The NF value of this RegisterClass.
+ NFShift = VLMulShift + 3,
+ NFShiftMask = 0b111 << NFShift,
+};
+
+/// \returns the LMUL for the register class.
+static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) {
topperc wrote:
These should not be in llvm namespace. They should be in RISCV namespace
https://github.com/llvm/llvm-project/pull/84894
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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)
@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap
,
};
}
+static void mergeX3RegUse(DenseMap ,
+ const InputSectionBase *oldSection,
+ const InputSectionBase *newSection,
+ unsigned int oldTag, unsigned int newTag) {
+ // X3/GP register usage ar incompatible and cannot be merged, with the
+ // exception of the UNKNOWN or 0 value
+ using RISCVAttrs::RISCVX3RegUse::X3RegUsage;
+ auto attr = RISCVAttrs::X3_REG_USAGE;
+ if (newTag == X3RegUsage::UNKNOWN)
+return;
+ if (oldTag == X3RegUsage::UNKNOWN) {
+intAttr[attr] = newTag;
topperc wrote:
Can we use the iterator from try_emplace instead of a second map lookup?
https://github.com/llvm/llvm-project/pull/84598
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[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
But we added a bunch of passes to the pipeline. Does that have compile time
impact?
https://github.com/llvm/llvm-project/pull/80124
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[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
If no in tree targets use this, should we default to false?
https://github.com/llvm/llvm-project/pull/80124
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[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
https://github.com/topperc deleted https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)
@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", + "true", "Prefer likely predicted branches over selects">; + +def FeatureEnableSelectOptimize + : SubtargetFeature<"enable-select-opt", "EnableSelectOptimize", "true", topperc wrote: If there are no in tree targets using it should we default this to false? https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)
@@ -11724,13 +11726,27 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode
*N,
Results.push_back(Result);
break;
}
- case ISD::READCYCLECOUNTER: {
-assert(!Subtarget.is64Bit() &&
- "READCYCLECOUNTER only has custom type legalization on riscv32");
+ case ISD::READCYCLECOUNTER:
+ case ISD::READSTEADYCOUNTER: {
+assert(!Subtarget.is64Bit() && "READCYCLECOUNTER/READSTEADYCOUNTER only "
+ "has custom type legalization on riscv32");
+SDValue LoCounter, HiCounter;
+MVT XLenVT = Subtarget.getXLenVT();
+if (N->getOpcode() == ISD::READCYCLECOUNTER) {
+ LoCounter = DAG.getConstant(
topperc wrote:
getTargetConstant
https://github.com/llvm/llvm-project/pull/82322
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[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)
@@ -363,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass {
let DiagnosticType = "InvalidCSRSystemRegister";
}
-def csr_sysreg : RISCVOp {
+def csr_sysreg : RISCVOp, ImmLeaf(Imm);"> {
topperc wrote:
TImmLeaf
https://github.com/llvm/llvm-project/pull/82322
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[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)
@@ -126,9 +126,10 @@ enum NodeType : unsigned {
// Floating point fmax and fmin matching the RISC-V instruction semantics.
FMAX, FMIN,
- // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
- // (returns (Lo, Hi)). It takes a chain operand.
- READ_CYCLE_WIDE,
+ // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
+ // It takes a chain operand.
topperc wrote:
Comment should mention the new operands
https://github.com/llvm/llvm-project/pull/82322
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[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)
@@ -445,6 +450,9 @@ void RISCVPassConfig::addIRPasses() {
if (EnableLoopDataPrefetch)
addPass(createLoopDataPrefetchPass());
+if (EnableSelectOpt && getOptLevel() == CodeGenOptLevel::Aggressive)
topperc wrote:
Shoudl this be after addIRPasses like it is for AArch64?
https://github.com/llvm/llvm-project/pull/80124
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[llvm-branch-commits] [Clang][RISCV] Refactor builtins to TableGen (PR #80280)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/80280 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)
topperc wrote: @tstellar Backport looks good to me. https://github.com/llvm/llvm-project/pull/79931 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] PR for llvm/llvm-project#79479 (PR #79907)
https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/79907
Resolves https://github.com/llvm/llvm-project/issues/79479.
>From 8fb154776db1627da75e6d67cf468d5b55868e93 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Thu, 25 Jan 2024 09:14:52 -0800
Subject: [PATCH 1/2] [RISCV] Support __riscv_v_fixed_vlen for vbool types.
(#76551)
This adopts a similar behavior to AArch64 SVE, where bool vectors are
represented as a vector of chars with 1/8 the number of elements. This
ensures the vector always occupies a power of 2 number of bytes.
A consequence of this is that vbool64_t, vbool32_t, and vool16_t can
only be used with a vector length that guarantees at least 8 bits.
---
clang/docs/ReleaseNotes.rst | 2 +
clang/include/clang/AST/Type.h| 3 +
clang/include/clang/Basic/AttrDocs.td | 5 +-
clang/lib/AST/ASTContext.cpp | 20 +-
clang/lib/AST/ItaniumMangle.cpp | 25 +-
clang/lib/AST/JSONNodeDumper.cpp | 3 +
clang/lib/AST/TextNodeDumper.cpp | 3 +
clang/lib/AST/Type.cpp| 15 +-
clang/lib/AST/TypePrinter.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 21 +-
clang/lib/Sema/SemaExpr.cpp | 6 +-
clang/lib/Sema/SemaType.cpp | 21 +-
.../attr-riscv-rvv-vector-bits-bitcast.c | 100 ++
.../CodeGen/attr-riscv-rvv-vector-bits-call.c | 74 +
.../CodeGen/attr-riscv-rvv-vector-bits-cast.c | 76 -
.../attr-riscv-rvv-vector-bits-codegen.c | 172 +++
.../attr-riscv-rvv-vector-bits-globals.c | 107 +++
.../attr-riscv-rvv-vector-bits-types.c| 284 ++
.../riscv-mangle-rvv-fixed-vectors.cpp| 72 +
clang/test/Sema/attr-riscv-rvv-vector-bits.c | 88 +-
20 files changed, 1065 insertions(+), 34 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 060bc7669b72a5..45d1ab34d0f931 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1227,6 +1227,8 @@ RISC-V Support
- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f
for RV64.
+- ``__attribute__((rvv_vector_bits(N))) is now supported for RVV vbool*_t
types.
+
CUDA/HIP Language Changes
^
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index ea425791fc97f0..6384cf9420b82e 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -3495,6 +3495,9 @@ enum class VectorKind {
/// is RISC-V RVV fixed-length data vector
RVVFixedLengthData,
+
+ /// is RISC-V RVV fixed-length mask vector
+ RVVFixedLengthMask,
};
/// Represents a GCC generic vector type. This type is created using
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index 7e633f8e2635a9..e02a1201e2ad79 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -2424,7 +2424,10 @@ only be a power of 2 between 64 and 65536.
For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the
LMUL
of the type before passing to the attribute.
-``vbool*_t`` types are not supported at this time.
+For ``vbool*_t`` types, ``__riscv_v_fixed_vlen`` needs to be divided by the
+number from the type name. For example, ``vbool8_t`` needs to use
+``__riscv_v_fixed_vlen`` / 8. If the resulting value is not a multiple of 8,
+the type is not supported for that value of ``__riscv_v_fixed_vlen``.
}];
}
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5eb7aa3664569d..ab16ca10395fa8 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -1945,7 +1945,8 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) const
{
else if (VT->getVectorKind() == VectorKind::SveFixedLengthPredicate)
// Adjust the alignment for fixed-length SVE predicates.
Align = 16;
-else if (VT->getVectorKind() == VectorKind::RVVFixedLengthData)
+else if (VT->getVectorKind() == VectorKind::RVVFixedLengthData ||
+ VT->getVectorKind() == VectorKind::RVVFixedLengthMask)
// Adjust the alignment for fixed-length RVV vectors.
Align = std::min(64, Width);
break;
@@ -9416,7 +9417,9 @@ bool ASTContext::areCompatibleVectorTypes(QualType
FirstVec,
Second->getVectorKind() != VectorKind::SveFixedLengthData &&
Second->getVectorKind() != VectorKind::SveFixedLengthPredicate &&
First->getVectorKind() != VectorKind::RVVFixedLengthData &&
- Second->getVectorKind() != VectorKind::RVVFixedLengthData)
+ Second->getVectorKind() != VectorKind::RVVFixedLengthData &&
+ First->getVectorKind() != VectorKind::RVVFixedLengthMask &&
+ Second->getVectorKind() != VectorKind::RVVFixedLengthMask)
return true;
return false;
@@ -9522,8 +9525,11 @@ static uint64_t
[llvm-branch-commits] [llvm] b92bf0d - [RISCV] Disable clang-format around the RISCVISD opcode enum. NFC
Author: Craig Topper
Date: 2023-11-29T14:01:30-08:00
New Revision: b92bf0dad6ec9760e008a0fa22d7dbd0b045c776
URL:
https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776
DIFF:
https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776.diff
LOG: [RISCV] Disable clang-format around the RISCVISD opcode enum. NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.h
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h
b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 45200b54595a0b9..486efeb8339ab0b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -25,7 +25,9 @@ namespace llvm {
class InstructionCost;
class RISCVSubtarget;
struct RISCVRegisterInfo;
+
namespace RISCVISD {
+// clang-format off
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
RET_GLUE,
@@ -421,6 +423,7 @@ enum NodeType : unsigned {
TH_SWD,
TH_SDD,
};
+// clang-format on
} // namespace RISCVISD
class RISCVTargetLowering : public TargetLowering {
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[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
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[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, ::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, ::FPCCRRegClass);
return Res;
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[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
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[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, ::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, ::FPCCRRegClass);
return Res;
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[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Author: Craig Topper
Date: 2023-11-22T19:49:52-08:00
New Revision: dc683d2e66de79bbea786f51788961eec5d0b793
URL:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793
DIFF:
https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff
LOG: [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC
Added:
Modified:
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 008075163b90a8d..f6fe7c9be7e4f46 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -422,7 +422,6 @@ class X86AsmParser : public MCTargetAsmParser {
IES_RPAREN,
IES_REGISTER,
IES_INTEGER,
-IES_IDENTIFIER,
IES_ERROR
};
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[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.
Author: Craig Topper
Date: 2023-11-22T18:59:41-08:00
New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c
URL:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c
DIFF:
https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff
LOG: [X86] Reject fpsr in inline asm constraints other than clobber.
Fixes #73197 and #69201.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 05a2ab093bb86f9..99866c811eb6faf 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -57236,7 +57236,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
return std::make_pair(X86::DF, ::DFCCRRegClass);
// fpsr -> FPSW
-if (StringRef("{fpsr}").equals_insensitive(Constraint))
+// Only allow for clobber.
+if (StringRef("{fpsr}").equals_insensitive(Constraint) && VT == MVT::Other)
return std::make_pair(X86::FPSW, ::FPCCRRegClass);
return Res;
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[llvm-branch-commits] [llvm] 4eb4f89 - [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.
Author: Craig Topper
Date: 2021-01-25T09:33:48-08:00
New Revision: 4eb4f8963f1e4998748bca66a512c3298f6d2289
URL:
https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289
DIFF:
https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289.diff
LOG: [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on
RV64.
As far as I know 32 bits arguments and returns on RV64 are always
sign extended to i64. So I think we should be taking this into
account around libcalls.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D95285
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0f9da5600a34..54208fc187c9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4250,6 +4250,13 @@ bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT
Type) const {
return true;
}
+bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool
IsSigned) const {
+ if (Subtarget.is64Bit() && Type == MVT::i32)
+return true;
+
+ return IsSigned;
+}
+
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext , EVT VT,
SDValue C) const {
// Check integral scalar types.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h
b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 3b7134341c8b..da16c6970d33 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -217,6 +217,7 @@ class RISCVTargetLowering : public TargetLowering {
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
bool shouldExtendTypeInLibCall(EVT Type) const override;
+ bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
/// Returns the register with the specified architectural or ABI name. This
/// method is necessary to lower the llvm.read_register.* and
diff --git a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
index 0b450c127077..31897d02e4c5 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
@@ -80,7 +80,6 @@ define i32 @flt_s(float %a, float %b) nounwind {
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:call __ltsf2@plt
-; RV64I-NEXT:sext.w a0, a0
; RV64I-NEXT:slti a0, a0, 0
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:addi sp, sp, 16
@@ -96,7 +95,6 @@ define i32 @fle_s(float %a, float %b) nounwind {
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:call __lesf2@plt
-; RV64I-NEXT:sext.w a0, a0
; RV64I-NEXT:slti a0, a0, 1
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:addi sp, sp, 16
@@ -112,7 +110,6 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind {
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:call __gtsf2@plt
-; RV64I-NEXT:sext.w a0, a0
; RV64I-NEXT:sgtz a0, a0
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:addi sp, sp, 16
@@ -128,7 +125,6 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT:call __gesf2@plt
-; RV64I-NEXT:sext.w a0, a0
; RV64I-NEXT:addi a1, zero, -1
; RV64I-NEXT:slt a0, a1, a0
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
@@ -214,8 +210,7 @@ define float @fcvt_s_wu(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:slli a0, a0, 32
-; RV64I-NEXT:srli a0, a0, 32
+; RV64I-NEXT:sext.w a0, a0
; RV64I-NEXT:call __floatunsisf@plt
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:addi sp, sp, 16
@@ -675,8 +670,7 @@ define float @fpowi_s(float %a, i32 %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT:addi sp, sp, -16
; RV64I-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:slli a1, a1, 32
-; RV64I-NEXT:srli a1, a1, 32
+; RV64I-NEXT:sext.w a1, a1
; RV64I-NEXT:call __powisf2@plt
; RV64I-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT:addi sp, sp, 16
___
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[llvm-branch-commits] [llvm] 12d0753 - [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
Author: Craig Topper
Date: 2021-01-24T13:58:14-08:00
New Revision: 12d0753aca22896fda2cf76781b0ee0524d55065
URL:
https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065
DIFF:
https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065.diff
LOG: [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and
assertzexti32.
The patterns that use this really want to know if the operand has at
least 32 sign/zero bits.
This increases opportunities to use W instructions when the original
source used i8/i16. Not sure how much this matters for performance,
but it makes i8/i16 code more consistent with i32.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index c03a406972a5..1b5683ab64cb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -838,13 +838,13 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A,
node:$B), [{
return isOrEquivalentToAdd(N);
}]>;
def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
- return cast(N->getOperand(1))->getVT() == MVT::i32;
+ return cast(N->getOperand(1))->getVT().bitsLE(MVT::i32);
}]>;
def sexti32 : PatFrags<(ops node:$src),
[(sext_inreg node:$src, i32),
(assertsexti32 node:$src)]>;
def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
- return cast(N->getOperand(1))->getVT() == MVT::i32;
+ return cast(N->getOperand(1))->getVT().bitsLE(MVT::i32);
}]>;
def zexti32 : PatFrags<(ops node:$src),
[(and node:$src, 0x),
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll
b/llvm/test/CodeGen/RISCV/double-convert.ll
index 5599775ffd68..a2e53a5a48d2 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -281,7 +281,7 @@ define double @fcvt_d_w_i8(i8 signext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_w_i8:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT:fcvt.d.l ft0, a0
+; RV64IFD-NEXT:fcvt.d.w ft0, a0
; RV64IFD-NEXT:fmv.x.d a0, ft0
; RV64IFD-NEXT:ret
%1 = sitofp i8 %a to double
@@ -301,7 +301,7 @@ define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_wu_i8:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT:fcvt.d.lu ft0, a0
+; RV64IFD-NEXT:fcvt.d.wu ft0, a0
; RV64IFD-NEXT:fmv.x.d a0, ft0
; RV64IFD-NEXT:ret
%1 = uitofp i8 %a to double
@@ -321,7 +321,7 @@ define double @fcvt_d_w_i16(i16 signext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_w_i16:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT:fcvt.d.l ft0, a0
+; RV64IFD-NEXT:fcvt.d.w ft0, a0
; RV64IFD-NEXT:fmv.x.d a0, ft0
; RV64IFD-NEXT:ret
%1 = sitofp i16 %a to double
@@ -341,7 +341,7 @@ define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
;
; RV64IFD-LABEL: fcvt_d_wu_i16:
; RV64IFD: # %bb.0:
-; RV64IFD-NEXT:fcvt.d.lu ft0, a0
+; RV64IFD-NEXT:fcvt.d.wu ft0, a0
; RV64IFD-NEXT:fmv.x.d a0, ft0
; RV64IFD-NEXT:ret
%1 = uitofp i16 %a to double
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll
b/llvm/test/CodeGen/RISCV/float-convert.ll
index de4be78f3cf6..bf9f576b68f0 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -202,7 +202,7 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_w_i8:
; RV64IF: # %bb.0:
-; RV64IF-NEXT:fcvt.s.l ft0, a0
+; RV64IF-NEXT:fcvt.s.w ft0, a0
; RV64IF-NEXT:fmv.x.w a0, ft0
; RV64IF-NEXT:ret
%1 = sitofp i8 %a to float
@@ -218,7 +218,7 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_wu_i8:
; RV64IF: # %bb.0:
-; RV64IF-NEXT:fcvt.s.lu ft0, a0
+; RV64IF-NEXT:fcvt.s.wu ft0, a0
; RV64IF-NEXT:fmv.x.w a0, ft0
; RV64IF-NEXT:ret
%1 = uitofp i8 %a to float
@@ -234,7 +234,7 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_w_i16:
; RV64IF: # %bb.0:
-; RV64IF-NEXT:fcvt.s.l ft0, a0
+; RV64IF-NEXT:fcvt.s.w ft0, a0
; RV64IF-NEXT:fmv.x.w a0, ft0
; RV64IF-NEXT:ret
%1 = sitofp i16 %a to float
@@ -250,7 +250,7 @@ define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
;
; RV64IF-LABEL: fcvt_s_wu_i16:
; RV64IF: # %bb.0:
-; RV64IF-NEXT:fcvt.s.lu ft0, a0
+; RV64IF-NEXT:fcvt.s.wu ft0, a0
; RV64IF-NEXT:fmv.x.w a0, ft0
; RV64IF-NEXT:ret
%1 = uitofp i16 %a to float
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll
b/llvm/test/CodeGen/RISCV/half-convert.ll
index
[llvm-branch-commits] [llvm] f22aa8f - [RISCV] Add test cases for missed opportunities to use *W instructions for div/rem when inputs are sign/zero extended from i8/16 instead of i32.
Author: Craig Topper
Date: 2021-01-24T13:56:38-08:00
New Revision: f22aa8f87931075834f973cebaa84c07ab1a26b1
URL:
https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1
DIFF:
https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1.diff
LOG: [RISCV] Add test cases for missed opportunities to use *W instructions for
div/rem when inputs are sign/zero extended from i8/16 instead of i32.
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
index f980c1885707..a6d9e294f85e 100644
--- a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -526,6 +526,24 @@ define zeroext i32 @zext_divuw_zext_zext(i32 zeroext %a,
i32 zeroext %b) nounwin
ret i32 %1
}
+define zeroext i8 @zext_divuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b)
nounwind {
+; RV64IM-LABEL: zext_divuw_zext_zext_i8:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:divu a0, a0, a1
+; RV64IM-NEXT:ret
+ %1 = udiv i8 %a, %b
+ ret i8 %1
+}
+
+define zeroext i16 @zext_divuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b)
nounwind {
+; RV64IM-LABEL: zext_divuw_zext_zext_i16:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:divu a0, a0, a1
+; RV64IM-NEXT:ret
+ %1 = udiv i16 %a, %b
+ ret i16 %1
+}
+
define i32 @aext_divw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: aext_divw_aext_aext:
; RV64IM: # %bb.0:
@@ -787,6 +805,28 @@ define zeroext i32 @zext_divw_zext_zext(i32 zeroext %a,
i32 zeroext %b) nounwind
ret i32 %1
}
+define signext i8 @sext_divw_sext_sext_i8(i8 signext %a, i8 signext %b)
nounwind {
+; RV64IM-LABEL: sext_divw_sext_sext_i8:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:div a0, a0, a1
+; RV64IM-NEXT:slli a0, a0, 56
+; RV64IM-NEXT:srai a0, a0, 56
+; RV64IM-NEXT:ret
+ %1 = sdiv i8 %a, %b
+ ret i8 %1
+}
+
+define signext i16 @sext_divw_sext_sext_i16(i16 signext %a, i16 signext %b)
nounwind {
+; RV64IM-LABEL: sext_divw_sext_sext_i16:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:div a0, a0, a1
+; RV64IM-NEXT:slli a0, a0, 48
+; RV64IM-NEXT:srai a0, a0, 48
+; RV64IM-NEXT:ret
+ %1 = sdiv i16 %a, %b
+ ret i16 %1
+}
+
define i32 @aext_remw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: aext_remw_aext_aext:
; RV64IM: # %bb.0:
@@ -1048,6 +1088,28 @@ define zeroext i32 @zext_remw_zext_zext(i32 zeroext %a,
i32 zeroext %b) nounwind
ret i32 %1
}
+define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b)
nounwind {
+; RV64IM-LABEL: sext_remw_sext_sext_i8:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:rem a0, a0, a1
+; RV64IM-NEXT:slli a0, a0, 56
+; RV64IM-NEXT:srai a0, a0, 56
+; RV64IM-NEXT:ret
+ %1 = srem i8 %a, %b
+ ret i8 %1
+}
+
+define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b)
nounwind {
+; RV64IM-LABEL: sext_remw_sext_sext_i16:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:rem a0, a0, a1
+; RV64IM-NEXT:slli a0, a0, 48
+; RV64IM-NEXT:srai a0, a0, 48
+; RV64IM-NEXT:ret
+ %1 = srem i16 %a, %b
+ ret i16 %1
+}
+
define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
; RV64IM-LABEL: aext_remuw_aext_aext:
; RV64IM: # %bb.0:
@@ -1306,3 +1368,21 @@ define zeroext i32 @zext_remuw_zext_zext(i32 zeroext %a,
i32 zeroext %b) nounwin
%1 = urem i32 %a, %b
ret i32 %1
}
+
+define zeroext i8 @zext_remuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b)
nounwind {
+; RV64IM-LABEL: zext_remuw_zext_zext_i8:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:remu a0, a0, a1
+; RV64IM-NEXT:ret
+ %1 = urem i8 %a, %b
+ ret i8 %1
+}
+
+define zeroext i16 @zext_remuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b)
nounwind {
+; RV64IM-LABEL: zext_remuw_zext_zext_i16:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT:remu a0, a0, a1
+; RV64IM-NEXT:ret
+ %1 = urem i16 %a, %b
+ ret i16 %1
+}
___
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[llvm-branch-commits] [llvm] 60ebf64 - [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16.
Author: Craig Topper
Date: 2021-01-24T13:48:29-08:00
New Revision: 60ebf6408e965635deb94bcdead8ac9451bf0ee9
URL:
https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9
DIFF:
https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9.diff
LOG: [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u)
instructions on RV64 when input is known to be extended from i8/i16.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/half-convert.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll
b/llvm/test/CodeGen/RISCV/double-convert.ll
index 7a27a8e569a9..5599775ffd68 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -267,3 +267,83 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
%3 = fadd double %1, %2
ret double %3
}
+
+define double @fcvt_d_w_i8(i8 signext %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_w_i8:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT:addi sp, sp, -16
+; RV32IFD-NEXT:fcvt.d.w ft0, a0
+; RV32IFD-NEXT:fsd ft0, 8(sp)
+; RV32IFD-NEXT:lw a0, 8(sp)
+; RV32IFD-NEXT:lw a1, 12(sp)
+; RV32IFD-NEXT:addi sp, sp, 16
+; RV32IFD-NEXT:ret
+;
+; RV64IFD-LABEL: fcvt_d_w_i8:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT:fcvt.d.l ft0, a0
+; RV64IFD-NEXT:fmv.x.d a0, ft0
+; RV64IFD-NEXT:ret
+ %1 = sitofp i8 %a to double
+ ret double %1
+}
+
+define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_wu_i8:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT:addi sp, sp, -16
+; RV32IFD-NEXT:fcvt.d.wu ft0, a0
+; RV32IFD-NEXT:fsd ft0, 8(sp)
+; RV32IFD-NEXT:lw a0, 8(sp)
+; RV32IFD-NEXT:lw a1, 12(sp)
+; RV32IFD-NEXT:addi sp, sp, 16
+; RV32IFD-NEXT:ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_i8:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT:fcvt.d.lu ft0, a0
+; RV64IFD-NEXT:fmv.x.d a0, ft0
+; RV64IFD-NEXT:ret
+ %1 = uitofp i8 %a to double
+ ret double %1
+}
+
+define double @fcvt_d_w_i16(i16 signext %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_w_i16:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT:addi sp, sp, -16
+; RV32IFD-NEXT:fcvt.d.w ft0, a0
+; RV32IFD-NEXT:fsd ft0, 8(sp)
+; RV32IFD-NEXT:lw a0, 8(sp)
+; RV32IFD-NEXT:lw a1, 12(sp)
+; RV32IFD-NEXT:addi sp, sp, 16
+; RV32IFD-NEXT:ret
+;
+; RV64IFD-LABEL: fcvt_d_w_i16:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT:fcvt.d.l ft0, a0
+; RV64IFD-NEXT:fmv.x.d a0, ft0
+; RV64IFD-NEXT:ret
+ %1 = sitofp i16 %a to double
+ ret double %1
+}
+
+define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_wu_i16:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT:addi sp, sp, -16
+; RV32IFD-NEXT:fcvt.d.wu ft0, a0
+; RV32IFD-NEXT:fsd ft0, 8(sp)
+; RV32IFD-NEXT:lw a0, 8(sp)
+; RV32IFD-NEXT:lw a1, 12(sp)
+; RV32IFD-NEXT:addi sp, sp, 16
+; RV32IFD-NEXT:ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_i16:
+; RV64IFD: # %bb.0:
+; RV64IFD-NEXT:fcvt.d.lu ft0, a0
+; RV64IFD-NEXT:fmv.x.d a0, ft0
+; RV64IFD-NEXT:ret
+ %1 = uitofp i16 %a to double
+ ret double %1
+}
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll
b/llvm/test/CodeGen/RISCV/float-convert.ll
index c160ae5d8cd5..de4be78f3cf6 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -192,3 +192,67 @@ define float @fcvt_s_lu(i64 %a) nounwind {
%1 = uitofp i64 %a to float
ret float %1
}
+
+define float @fcvt_s_w_i8(i8 signext %a) nounwind {
+; RV32IF-LABEL: fcvt_s_w_i8:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT:fcvt.s.w ft0, a0
+; RV32IF-NEXT:fmv.x.w a0, ft0
+; RV32IF-NEXT:ret
+;
+; RV64IF-LABEL: fcvt_s_w_i8:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT:fcvt.s.l ft0, a0
+; RV64IF-NEXT:fmv.x.w a0, ft0
+; RV64IF-NEXT:ret
+ %1 = sitofp i8 %a to float
+ ret float %1
+}
+
+define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
+; RV32IF-LABEL: fcvt_s_wu_i8:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT:fcvt.s.wu ft0, a0
+; RV32IF-NEXT:fmv.x.w a0, ft0
+; RV32IF-NEXT:ret
+;
+; RV64IF-LABEL: fcvt_s_wu_i8:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT:fcvt.s.lu ft0, a0
+; RV64IF-NEXT:fmv.x.w a0, ft0
+; RV64IF-NEXT:ret
+ %1 = uitofp i8 %a to float
+ ret float %1
+}
+
+define float @fcvt_s_w_i16(i16 signext %a) nounwind {
+; RV32IF-LABEL: fcvt_s_w_i16:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT:fcvt.s.w ft0, a0
+; RV32IF-NEXT:fmv.x.w a0, ft0
+; RV32IF-NEXT:ret
+;
+; RV64IF-LABEL: fcvt_s_w_i16:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT:fcvt.s.l ft0, a0
+; RV64IF-NEXT:fmv.x.w a0, ft0
+; RV64IF-NEXT:ret
+ %1 = sitofp i16 %a to float
+ ret float %1
+}
+
+define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
+; RV32IF-LABEL: fcvt_s_wu_i16:
+; RV32IF:
[llvm-branch-commits] [llvm] 116177a - [RISCV] Use SRLIWPat in the PACKUW pattern.
Author: Craig Topper Date: 2021-01-24T10:41:58-08:00 New Revision: 116177afcce88d807c1beffcb9221999ad8a69a9 URL: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9 DIFF: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9.diff LOG: [RISCV] Use SRLIWPat in the PACKUW pattern. This makes the code more tolerant if we ever change SimplifyDemandedBits to not remove 1s from the lsbs of a contiguous mask. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td Removed: diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index 9940063d5f9a..501137a934d6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -1046,7 +1046,6 @@ def : Pat<(sext_inreg (or (shl GPR:$rs2, (i64 16)), i32), (PACKW GPR:$rs1, GPR:$rs2)>; def : Pat<(or (and (assertsexti32 GPR:$rs2), 0x), - (srl (and GPR:$rs1, 0x), - (i64 16))), + (SRLIWPat GPR:$rs1, (i64 16))), (PACKUW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] c50457f - [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.
Author: Craig Topper
Date: 2021-01-24T00:34:45-08:00
New Revision: c50457f3e4209b0cd0d4a6baa881bac30a9d3016
URL:
https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016
DIFF:
https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016.diff
LOG: [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask
where the shift has guaranteed zeros.
This avoids being dependent on SimplifyDemandedBits having cleared
those bits.
It could make sense to teach SimplifyDemandedBits to keep all
lower bits 1 in an AND mask when possible. This could be
implemented with slli+srli in the general case rather than
needing to materialize the constant.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 078ed1b8d8d1..2198b275ec11 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -871,7 +871,7 @@ bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
// Immediate range should be enforced by uimm5 predicate.
assert(VC2 < 32 && "Unexpected immediate");
- return VC1 == ((uint64_t)0x << VC2);
+ return (VC1 >> VC2) == UINT64_C(0x);
}
bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue ) {
___
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[llvm-branch-commits] [llvm] c7d5d8f - [RISCV] Group some Zbs isel patterns together and remove a stale comment. NFC
Author: Craig Topper
Date: 2021-01-23T16:45:05-08:00
New Revision: c7d5d8fa33a0f23b262b695d17fdffdefa8dc940
URL:
https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940
DIFF:
https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940.diff
LOG: [RISCV] Group some Zbs isel patterns together and remove a stale comment.
NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 8740e61b1ee1..9940063d5f9a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -725,6 +725,9 @@ def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
(BSETI GPR:$rs1, (BSETINVXForm imm:$mask))>;
def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
(BINVI GPR:$rs1, (BSETINVXForm imm:$mask))>;
+
+def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
+ (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
}
let Predicates = [HasStdExtZbp] in {
@@ -743,12 +746,6 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
(RORI GPR:$rs1, (ImmROTL2R uimmlog2xlen:$shamt))>;
}
-// We don't pattern-match sbclri[w], sbseti[w], sbinvi[w] because they are
-// pattern-matched by simple andi, ori, and xori.
-let Predicates = [HasStdExtZbs] in
-def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
- (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
-
def riscv_grevi: SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
def riscv_gorci: SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
___
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[llvm-branch-commits] [llvm] 998057e - [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.
Author: Craig Topper
Date: 2021-01-23T15:57:41-08:00
New Revision: 998057ec06ae7e0fb1e0be0f2702df4d6338a128
URL:
https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128
DIFF:
https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128.diff
LOG: [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index f075699c17f0..8740e61b1ee1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -694,9 +694,9 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1,
GPR:$rs2)>;
} // Predicates = [HasStdExtZbbOrZbp]
let Predicates = [HasStdExtZbp] in {
-def : Pat<(not (shl (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftop (not GPR:$rs1), GPR:$rs2)),
(SLO GPR:$rs1, GPR:$rs2)>;
-def : Pat<(not (srl (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftop (not GPR:$rs1), GPR:$rs2)),
(SRO GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbp]
@@ -960,9 +960,9 @@ def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 3)), GPR:$rs2),
} // Predicates = [HasStdExtZba, IsRV64]
let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftopw (not GPR:$rs1), GPR:$rs2)),
(SLOW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
+def : Pat<(not (shiftopw (not GPR:$rs1), GPR:$rs2)),
(SROW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbp, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
index 8fc772931f3a..de315dfb2d5a 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
@@ -39,13 +39,11 @@ define i32 @slo_i32_mask(i32 %a, i32 %b) nounwind {
;
; RV32IB-LABEL: slo_i32_mask:
; RV32IB: # %bb.0:
-; RV32IB-NEXT:andi a1, a1, 31
; RV32IB-NEXT:slo a0, a0, a1
; RV32IB-NEXT:ret
;
; RV32IBP-LABEL: slo_i32_mask:
; RV32IBP: # %bb.0:
-; RV32IBP-NEXT:andi a1, a1, 31
; RV32IBP-NEXT:slo a0, a0, a1
; RV32IBP-NEXT:ret
%neg = xor i32 %a, -1
@@ -243,13 +241,11 @@ define i32 @sro_i32_mask(i32 %a, i32 %b) nounwind {
;
; RV32IB-LABEL: sro_i32_mask:
; RV32IB: # %bb.0:
-; RV32IB-NEXT:andi a1, a1, 31
; RV32IB-NEXT:sro a0, a0, a1
; RV32IB-NEXT:ret
;
; RV32IBP-LABEL: sro_i32_mask:
; RV32IBP: # %bb.0:
-; RV32IBP-NEXT:andi a1, a1, 31
; RV32IBP-NEXT:sro a0, a0, a1
; RV32IBP-NEXT:ret
%neg = xor i32 %a, -1
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
index 243ebc17a86b..d2191afd5b79 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
@@ -86,13 +86,11 @@ define i64 @slo_i64_mask(i64 %a, i64 %b) nounwind {
;
; RV64IB-LABEL: slo_i64_mask:
; RV64IB: # %bb.0:
-; RV64IB-NEXT:andi a1, a1, 63
; RV64IB-NEXT:slo a0, a0, a1
; RV64IB-NEXT:ret
;
; RV64IBP-LABEL: slo_i64_mask:
; RV64IBP: # %bb.0:
-; RV64IBP-NEXT:andi a1, a1, 63
; RV64IBP-NEXT:slo a0, a0, a1
; RV64IBP-NEXT:ret
%neg = xor i64 %a, -1
@@ -182,13 +180,11 @@ define i64 @sro_i64_mask(i64 %a, i64 %b) nounwind {
;
; RV64IB-LABEL: sro_i64_mask:
; RV64IB: # %bb.0:
-; RV64IB-NEXT:andi a1, a1, 63
; RV64IB-NEXT:sro a0, a0, a1
; RV64IB-NEXT:ret
;
; RV64IBP-LABEL: sro_i64_mask:
; RV64IBP: # %bb.0:
-; RV64IBP-NEXT:andi a1, a1, 63
; RV64IBP-NEXT:sro a0, a0, a1
; RV64IBP-NEXT:ret
%neg = xor i64 %a, -1
___
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[llvm-branch-commits] [llvm] 5a73daf - [RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC
Author: Craig Topper
Date: 2021-01-23T15:45:51-08:00
New Revision: 5a73daf907873a8757213932f814361a59f02da5
URL:
https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5
DIFF:
https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5.diff
LOG: [RISCV] Add test cases for SRO/SLO with shift amounts masked to
bitwidth-1. NFC
The sro/slo instructions ignore extra bits in the shift amount,
so we can ignore the mask just like we do for sll, srl, and sra.
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll
Removed:
diff --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
index 7e2c6ad46a15..8fc772931f3a 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
@@ -29,6 +29,32 @@ define i32 @slo_i32(i32 %a, i32 %b) nounwind {
ret i32 %neg1
}
+define i32 @slo_i32_mask(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: slo_i32_mask:
+; RV32I: # %bb.0:
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:sll a0, a0, a1
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: slo_i32_mask:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT:andi a1, a1, 31
+; RV32IB-NEXT:slo a0, a0, a1
+; RV32IB-NEXT:ret
+;
+; RV32IBP-LABEL: slo_i32_mask:
+; RV32IBP: # %bb.0:
+; RV32IBP-NEXT:andi a1, a1, 31
+; RV32IBP-NEXT:slo a0, a0, a1
+; RV32IBP-NEXT:ret
+ %neg = xor i32 %a, -1
+ %and = and i32 %b, 31
+ %shl = shl i32 %neg, %and
+ %neg1 = xor i32 %shl, -1
+ ret i32 %neg1
+}
+
; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b
@@ -39,12 +65,12 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT:addi a3, a2, -32
; RV32I-NEXT:not a0, a0
-; RV32I-NEXT:bltz a3, .LBB1_2
+; RV32I-NEXT:bltz a3, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT:mv a2, zero
; RV32I-NEXT:sll a1, a0, a3
-; RV32I-NEXT:j .LBB1_3
-; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT:j .LBB2_3
+; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT:not a1, a1
; RV32I-NEXT:sll a1, a1, a2
; RV32I-NEXT:addi a3, zero, 31
@@ -53,7 +79,7 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT:srl a3, a4, a3
; RV32I-NEXT:or a1, a1, a3
; RV32I-NEXT:sll a2, a0, a2
-; RV32I-NEXT: .LBB1_3:
+; RV32I-NEXT: .LBB2_3:
; RV32I-NEXT:not a1, a1
; RV32I-NEXT:not a0, a2
; RV32I-NEXT:ret
@@ -83,12 +109,12 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
; RV32IBP: # %bb.0:
; RV32IBP-NEXT:addi a3, a2, -32
; RV32IBP-NEXT:not a0, a0
-; RV32IBP-NEXT:bltz a3, .LBB1_2
+; RV32IBP-NEXT:bltz a3, .LBB2_2
; RV32IBP-NEXT: # %bb.1:
; RV32IBP-NEXT:mv a2, zero
; RV32IBP-NEXT:sll a1, a0, a3
-; RV32IBP-NEXT:j .LBB1_3
-; RV32IBP-NEXT: .LBB1_2:
+; RV32IBP-NEXT:j .LBB2_3
+; RV32IBP-NEXT: .LBB2_2:
; RV32IBP-NEXT:not a1, a1
; RV32IBP-NEXT:sll a1, a1, a2
; RV32IBP-NEXT:addi a3, zero, 31
@@ -97,7 +123,7 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
; RV32IBP-NEXT:srl a3, a4, a3
; RV32IBP-NEXT:or a1, a1, a3
; RV32IBP-NEXT:sll a2, a0, a2
-; RV32IBP-NEXT: .LBB1_3:
+; RV32IBP-NEXT: .LBB2_3:
; RV32IBP-NEXT:not a1, a1
; RV32IBP-NEXT:not a0, a2
; RV32IBP-NEXT:ret
@@ -107,6 +133,83 @@ define i64 @slo_i64(i64 %a, i64 %b) nounwind {
ret i64 %neg1
}
+define i64 @slo_i64_mask(i64 %a, i64 %b) nounwind {
+; RV32I-LABEL: slo_i64_mask:
+; RV32I: # %bb.0:
+; RV32I-NEXT:andi a3, a2, 63
+; RV32I-NEXT:addi a4, a3, -32
+; RV32I-NEXT:not a0, a0
+; RV32I-NEXT:bltz a4, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT:mv a2, zero
+; RV32I-NEXT:sll a1, a0, a4
+; RV32I-NEXT:j .LBB3_3
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT:not a1, a1
+; RV32I-NEXT:sll a1, a1, a2
+; RV32I-NEXT:addi a4, zero, 31
+; RV32I-NEXT:sub a3, a4, a3
+; RV32I-NEXT:srli a4, a0, 1
+; RV32I-NEXT:srl a3, a4, a3
+; RV32I-NEXT:or a1, a1, a3
+; RV32I-NEXT:sll a2, a0, a2
+; RV32I-NEXT: .LBB3_3:
+; RV32I-NEXT:not a1, a1
+; RV32I-NEXT:not a0, a2
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: slo_i64_mask:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT:not a0, a0
+; RV32IB-NEXT:not a1, a1
+; RV32IB-NEXT:sll a1, a1, a2
+; RV32IB-NEXT:andi a3, a2, 63
+; RV32IB-NEXT:addi a4, zero, 31
+; RV32IB-NEXT:sub a4, a4, a3
+; RV32IB-NEXT:srli a5, a0, 1
+; RV32IB-NEXT:srl a4, a5, a4
+; RV32IB-NEXT:or a1, a1, a4
+; RV32IB-NEXT:addi a3, a3, -32
+; RV32IB-NEXT:sll a4, a0, a3
+; RV32IB-NEXT:slti a5, a3, 0
+; RV32IB-NEXT:cmov a1, a5, a1, a4
+; RV32IB-NEXT:sll a0, a0, a2
+; RV32IB-NEXT:srai a2, a3, 31
+;
[llvm-branch-commits] [llvm] d2927f7 - [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
Author: Craig Topper
Date: 2021-01-23T15:08:18-08:00
New Revision: d2927f786e877410d90c1e6f0e0c7d99524529c5
URL:
https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5
DIFF:
https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5.diff
LOG: [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift
amounts.
We try to do this during DAG combine with SimplifyDemandedBits,
but it fails if there are multiple nodes using the AND. For
example, multiple shifts using the same shift amount.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 38a8e6a151a8..c03a406972a5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -885,6 +885,10 @@ class shiftop
: PatFrags<(ops node:$val, node:$count),
[(operator node:$val, node:$count),
(operator node:$val, (and node:$count, immbottomxlenset))]>;
+class shiftopw
+: PatFrags<(ops node:$val, node:$count),
+ [(operator node:$val, node:$count),
+(operator node:$val, (and node:$count, (XLenVT 31)))]>;
def : PatGprGpr, SLL>;
def : PatGprGpr, SRL>;
@@ -1186,9 +1190,9 @@ def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
-def : PatGprGpr;
-def : PatGprGpr;
-def : PatGprGpr;
+def : PatGprGpr, SLLW>;
+def : PatGprGpr, SRLW>;
+def : PatGprGpr, SRAW>;
/// Loads
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 6656e3d964d6..818b15a1ed9c 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -63,7 +63,6 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -141,7 +140,6 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -219,7 +217,6 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp,
i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -297,7 +294,6 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -375,7 +371,6 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp,
i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -453,7 +448,6 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -531,7 +525,6 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp,
i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -609,7 +602,6 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0, 3
-; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
; RV64IA-NEXT:andi a1, a1, 255
@@ -687,7 +679,6 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp,
i8 %val) nounwind {
; RV64IA: # %bb.0:
; RV64IA-NEXT:andi a3, a0, -4
; RV64IA-NEXT:slli a0, a0,
[llvm-branch-commits] [llvm] 147c0c2 - [TargetLowering] Use isOneConstant to simplify some code. NFC
Author: Craig Topper
Date: 2021-01-22T19:32:19-08:00
New Revision: 147c0c263d88a9702aba17fbeac62ff83e6c1319
URL:
https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319
DIFF:
https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319.diff
LOG: [TargetLowering] Use isOneConstant to simplify some code. NFC
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b0b4a6ae9227..80b745e0354a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3780,8 +3780,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0,
SDValue N1,
(N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::XOR &&
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
- isa(N0.getOperand(1)) &&
- cast(N0.getOperand(1))->isOne()) {
+ isOneConstant(N0.getOperand(1))) {
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
// can only do this if the top bits are known zero.
unsigned BitWidth = N0.getValueSizeInBits();
@@ -3825,9 +3824,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0,
SDValue N1,
return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond);
}
}
-if (Op0.getOpcode() == ISD::AND &&
-isa(Op0.getOperand(1)) &&
-cast(Op0.getOperand(1))->isOne()) {
+if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1))) {
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
if (Op0.getValueType().bitsGT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT,
___
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[llvm-branch-commits] [llvm] d65e8ee - [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
Author: Craig Topper
Date: 2021-01-22T14:51:22-08:00
New Revision: d65e8ee507f82ddca018267d0ce627518dd07337
URL:
https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337
DIFF:
https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337.diff
LOG: [RISCV] Add more cmov isel patterns to handle seteq/ne with a small
non-zero immediate.
Similar to our free standing setcc patterns, we can use ADDI to
subtract the immediate from the other operand. Then the cmov
can check if the result is zero or non-zero.
Reviewed By: mundaym
Differential Revision: https://reviews.llvm.org/D95169
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index d4ba4f8e285c..f075699c17f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -778,10 +778,15 @@ def : Pat<(riscv_grevi GPR:$rs1, (i64 56)), (REV8_RV64
GPR:$rs1)>;
let Predicates = [HasStdExtZbt] in {
def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
(CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+
def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
(CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1,
GPR:$rs3),
+ (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3,
GPR:$rs1),
+ (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
(CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index b6ecf3930b24..2b7f275bf6d6 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -27,8 +27,7 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind
{
;
; RV32IBT-LABEL: cmovcc64:
; RV32IBT: # %bb.0: # %entry
-; RV32IBT-NEXT:addi a5, zero, 123
-; RV32IBT-NEXT:xor a5, a0, a5
+; RV32IBT-NEXT:addi a5, a0, -123
; RV32IBT-NEXT:cmov a0, a5, a3, a1
; RV32IBT-NEXT:cmov a1, a5, a4, a2
; RV32IBT-NEXT:ret
@@ -45,8 +44,7 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind
{
;
; RV64IBT-LABEL: cmovcc64:
; RV64IBT: # %bb.0: # %entry
-; RV64IBT-NEXT:addi a3, zero, 123
-; RV64IBT-NEXT:xor a0, a0, a3
+; RV64IBT-NEXT:addi a0, a0, -123
; RV64IBT-NEXT:cmov a0, a0, a2, a1
; RV64IBT-NEXT:ret
entry:
@@ -133,8 +131,7 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c)
nounwind {
;
; RV64IBT-LABEL: cmovcc128:
; RV64IBT: # %bb.0: # %entry
-; RV64IBT-NEXT:addi a5, zero, 123
-; RV64IBT-NEXT:xor a5, a0, a5
+; RV64IBT-NEXT:addi a5, a0, -123
; RV64IBT-NEXT:cmov a0, a5, a3, a1
; RV64IBT-NEXT:cmov a1, a5, a4, a2
; RV64IBT-NEXT:ret
@@ -434,8 +431,7 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32
%d) nounwind {
;
; RV32IBT-LABEL: cmovccdep:
; RV32IBT: # %bb.0: # %entry
-; RV32IBT-NEXT:addi a4, zero, 123
-; RV32IBT-NEXT:xor a0, a0, a4
+; RV32IBT-NEXT:addi a0, a0, -123
; RV32IBT-NEXT:cmov a1, a0, a2, a1
; RV32IBT-NEXT:cmov a0, a0, a3, a1
; RV32IBT-NEXT:add a0, a1, a0
@@ -462,8 +458,7 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32
%d) nounwind {
;
; RV64IBT-LABEL: cmovccdep:
; RV64IBT: # %bb.0: # %entry
-; RV64IBT-NEXT:addi a4, zero, 123
-; RV64IBT-NEXT:xor a0, a0, a4
+; RV64IBT-NEXT:addi a0, a0, -123
; RV64IBT-NEXT:cmov a1, a0, a2, a1
; RV64IBT-NEXT:cmov a0, a0, a3, a1
; RV64IBT-NEXT:addw a0, a1, a0
___
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[llvm-branch-commits] [llvm] 607e5a5 - [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.
Author: Craig Topper Date: 2021-01-22T13:52:26-08:00 New Revision: 607e5a5000bddec24061b54a7e7955d51fe0d049 URL: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049 DIFF: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049.diff LOG: [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32. Add tests to make sure common instructions are accepted in RV64 and not just RV32. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D95150 Added: llvm/test/MC/RISCV/rv64zbc-valid.s Modified: llvm/test/MC/RISCV/rv32zba-invalid.s llvm/test/MC/RISCV/rv32zbb-invalid.s llvm/test/MC/RISCV/rv32zbbp-invalid.s llvm/test/MC/RISCV/rv32zbe-invalid.s llvm/test/MC/RISCV/rv32zbf-invalid.s llvm/test/MC/RISCV/rv32zbp-invalid.s llvm/test/MC/RISCV/rv32zbproposedc-invalid.s llvm/test/MC/RISCV/rv32zbr-invalid.s llvm/test/MC/RISCV/rv32zbs-invalid.s llvm/test/MC/RISCV/rv32zbt-invalid.s llvm/test/MC/RISCV/rv64zba-valid.s llvm/test/MC/RISCV/rv64zbb-valid.s llvm/test/MC/RISCV/rv64zbbp-valid.s llvm/test/MC/RISCV/rv64zbe-valid.s llvm/test/MC/RISCV/rv64zbf-valid.s llvm/test/MC/RISCV/rv64zbp-valid.s llvm/test/MC/RISCV/rv64zbproposedc-valid.s llvm/test/MC/RISCV/rv64zbr-valid.s llvm/test/MC/RISCV/rv64zbs-valid.s llvm/test/MC/RISCV/rv64zbt-valid.s Removed: diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s b/llvm/test/MC/RISCV/rv32zba-invalid.s index 64adfe03fdfb..1005fab1b8ed 100644 --- a/llvm/test/MC/RISCV/rv32zba-invalid.s +++ b/llvm/test/MC/RISCV/rv32zba-invalid.s @@ -6,3 +6,8 @@ sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +slli.uw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +sh1add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +sh2add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +sh3add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32zbb-invalid.s b/llvm/test/MC/RISCV/rv32zbb-invalid.s index 4e40b44ee02c..ea6a17032fef 100644 --- a/llvm/test/MC/RISCV/rv32zbb-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbb-invalid.s @@ -18,3 +18,6 @@ max t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction minu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands maxu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +clzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +ctzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +cpopw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32zbbp-invalid.s b/llvm/test/MC/RISCV/rv32zbbp-invalid.s index a8ba4a659498..286f6050434b 100644 --- a/llvm/test/MC/RISCV/rv32zbbp-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbbp-invalid.s @@ -15,3 +15,7 @@ rori t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Immediate operand out of range rori t0, t1, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] rori t0, t1, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +rolw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +rorw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +roriw t0, t1, 31 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +roriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32zbe-invalid.s b/llvm/test/MC/RISCV/rv32zbe-invalid.s index 537154d3fc60..4d4124778f13 100644 --- a/llvm/test/MC/RISCV/rv32zbe-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbe-invalid.s @@ -4,3 +4,5 @@ bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error:
[llvm-branch-commits] [llvm] 095e245 - [RISCV] Add isel patterns for SH*ADD(.UW)
Author: Craig Topper
Date: 2021-01-22T13:28:41-08:00
New Revision: 095e245e164584b5de3c2938452b48d1f8ba4dda
URL:
https://github.com/llvm/llvm-project/commit/095e245e164584b5de3c2938452b48d1f8ba4dda
DIFF:
https://github.com/llvm/llvm-project/commit/095e245e164584b5de3c2938452b48d1f8ba4dda.diff
LOG: [RISCV] Add isel patterns for SH*ADD(.UW)
This adds an initial set of patterns for these instructions. Its
more complicated that I would like for the sh*add.uw instructions
because there is no guaranteed canonicalization for shl/and with
constants.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D95106
Added:
llvm/test/CodeGen/RISCV/rv32Zba.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv64Zba.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 0ba314dd6ecf..d4ba4f8e285c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -921,6 +921,15 @@ def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64
0x)),
(SHFLI GPR:$rs1, (i64 1))>;
} // Predicates = [HasStdExtZbp, IsRV64]
+let Predicates = [HasStdExtZba] in {
+def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), GPR:$rs2),
+ (SH1ADD GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), GPR:$rs2),
+ (SH2ADD GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), GPR:$rs2),
+ (SH3ADD GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZba]
+
let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
@@ -929,7 +938,21 @@ def : Pat<(shl (and GPR:$rs1, 0x), uimm5:$shamt),
def : Pat<(add (and GPR:$rs1, (i64 0x)), GPR:$rs2),
(ADDUW GPR:$rs1, GPR:$rs2)>;
def : Pat<(and GPR:$rs, 0x), (ADDUW GPR:$rs, X0)>;
-}
+
+def : Pat<(add (shl (and GPR:$rs1, (i64 0x)), (XLenVT 1)), GPR:$rs2),
+ (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl (and GPR:$rs1, (i64 0x)), (XLenVT 2)), GPR:$rs2),
+ (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (shl (and GPR:$rs1, (i64 0x)), (XLenVT 3)), GPR:$rs2),
+ (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 1)), GPR:$rs2),
+ (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 2)), GPR:$rs2),
+ (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(add (SLLIUWPat GPR:$rs1, (XLenVT 3)), GPR:$rs2),
+ (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtZba, IsRV64]
let Predicates = [HasStdExtZbp, IsRV64] in {
def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
diff --git a/llvm/test/CodeGen/RISCV/rv32Zba.ll
b/llvm/test/CodeGen/RISCV/rv32Zba.ll
new file mode 100644
index ..b4e4ffc5ca72
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv32Zba.ll
@@ -0,0 +1,82 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba -verify-machineinstrs <
%s \
+; RUN: | FileCheck %s -check-prefix=RV32IBA
+
+define signext i16 @sh1add(i64 %0, i16* %1) {
+; RV32I-LABEL: sh1add:
+; RV32I: # %bb.0:
+; RV32I-NEXT:slli a0, a0, 1
+; RV32I-NEXT:add a0, a2, a0
+; RV32I-NEXT:lh a0, 0(a0)
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: sh1add:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT:sh1add a0, a0, a2
+; RV32IB-NEXT:lh a0, 0(a0)
+; RV32IB-NEXT:ret
+;
+; RV32IBA-LABEL: sh1add:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT:sh1add a0, a0, a2
+; RV32IBA-NEXT:lh a0, 0(a0)
+; RV32IBA-NEXT:ret
+ %3 = getelementptr inbounds i16, i16* %1, i64 %0
+ %4 = load i16, i16* %3
+ ret i16 %4
+}
+
+define i32 @sh2add(i64 %0, i32* %1) {
+; RV32I-LABEL: sh2add:
+; RV32I: # %bb.0:
+; RV32I-NEXT:slli a0, a0, 2
+; RV32I-NEXT:add a0, a2, a0
+; RV32I-NEXT:lw a0, 0(a0)
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: sh2add:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT:sh2add a0, a0, a2
+; RV32IB-NEXT:lw a0, 0(a0)
+; RV32IB-NEXT:ret
+;
+; RV32IBA-LABEL: sh2add:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT:sh2add a0, a0, a2
+; RV32IBA-NEXT:lw a0, 0(a0)
+; RV32IBA-NEXT:ret
+ %3 = getelementptr inbounds i32, i32* %1, i64 %0
+ %4 = load i32, i32* %3
+ ret i32 %4
+}
+
+define i64 @sh3add(i64 %0, i64* %1) {
+; RV32I-LABEL: sh3add:
+; RV32I: # %bb.0:
+; RV32I-NEXT:slli a0, a0, 3
+; RV32I-NEXT:add a1, a2, a0
+; RV32I-NEXT:lw a0, 0(a1)
+; RV32I-NEXT:lw a1, 4(a1)
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: sh3add:
+;
[llvm-branch-commits] [llvm] f25f7e8 - [RISCV] Add xperm.* instructions to Zbp extension.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
URL:
https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff
DIFF:
https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff.diff
LOG: [RISCV] Add xperm.* instructions to Zbp extension.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94999
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/MC/RISCV/rv32zbp-invalid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64zbp-invalid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 5a733c4bf771..37c64cc1631a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -252,6 +252,12 @@ def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
+let Predicates = [HasStdExtZbp] in {
+def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
+def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
+def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
+
let Predicates = [HasStdExtZbp] in {
def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>;
def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>;
@@ -405,6 +411,10 @@ def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64]
+let Predicates = [HasStdExtZbp, IsRV64] in {
+def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
+} // Predicates = [HasStdExtZbp, IsRV64]
+
let Predicates = [HasStdExtZbp, IsRV64] in {
def SLOIW : RVBShiftW_ri<0b001, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>;
def SROIW : RVBShiftW_ri<0b001, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>;
diff --git a/llvm/test/MC/RISCV/rv32zbp-invalid.s
b/llvm/test/MC/RISCV/rv32zbp-invalid.s
index de65a71bd0f6..f5eac72b3b88 100644
--- a/llvm/test/MC/RISCV/rv32zbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-invalid.s
@@ -48,3 +48,9 @@ pack t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands
for instruction
packu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
packh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.n t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.b t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.h t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zbp-valid.s
b/llvm/test/MC/RISCV/rv32zbp-valid.s
index 3ca28573addd..f05d72dc9ec2 100644
--- a/llvm/test/MC/RISCV/rv32zbp-valid.s
+++ b/llvm/test/MC/RISCV/rv32zbp-valid.s
@@ -78,3 +78,12 @@ orc.b t0, t1
# CHECK-OBJ: orc.b t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
gorci t0, t1, 7
+# CHECK-ASM-AND-OBJ: xperm.n t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28]
+xperm.n t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.b t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
+xperm.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm.h t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x28
+xperm.h t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zbp-invalid.s
b/llvm/test/MC/RISCV/rv64zbp-invalid.s
index 8b98bdfa41b0..88adf2d47779 100644
--- a/llvm/test/MC/RISCV/rv64zbp-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbp-invalid.s
@@ -32,3 +32,5 @@ greviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate
must be an integer in
shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xperm.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbp-valid.s
b/llvm/test/MC/RISCV/rv64zbp-valid.s
index ec4e918173b3..7fbc684b9c3d 100644
--- a/llvm/test/MC/RISCV/rv64zbp-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbp-valid.s
@@ -69,3 +69,6 @@ orc.b t0, t1
# CHECK-OBJ: orc.b t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x73,0x28]
gorci t0, t1, 7
+# CHECK-ASM-AND-OBJ: xperm.w t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x02,0x73,0x28]
+xperm.w t0, t1, t2
___
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[llvm-branch-commits] [llvm] 4d5aa76 - [RISCV] Add support for rev8 and orc.b to Zbb.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 4d5aa760a7d78b601fcfbda4d6196091a9188ea6
URL:
https://github.com/llvm/llvm-project/commit/4d5aa760a7d78b601fcfbda4d6196091a9188ea6
DIFF:
https://github.com/llvm/llvm-project/commit/4d5aa760a7d78b601fcfbda4d6196091a9188ea6.diff
LOG: [RISCV] Add support for rev8 and orc.b to Zbb.
These instructions use a portion of the encodings for grevi and
gorci. The full encodings are only supported with Zbp. Note,
rev8 has a different encoding between rv32 and rv64.
Zbb is closer to being finalized that Zbp which has motivated
some decisions in this patch.
I'm treating rev8 and orc.b as separate instructions when
either Zbb or Zbp is enabled. This allows us to print to suggest
that either feature needs to be enabled to support these mnemonics.
I had tried to put HasStdExtZbbAndNotZbp on the Zbb instructions,
but that caused a diagnostic that said Zbp is required if neither
feature is enabled. We should really mention Zbb since its closer
to final.
This does require extra isel patterns for the different cases so
that bswap will always print as rev8 in assembly listing since
we can't use an InstAlias.
llvm-objdump disassembling should always pick the rev8 or orc.b
instructions. llvm-mc parsing and printing text will not convert
the grevi/gorci spellings to rev8/gorc.b. We could probably fix
this with a special case in processInstruction in the assembly
parser if it its important.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94944
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbb.ll
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/MC/RISCV/rv32b-aliases-valid.s
llvm/test/MC/RISCV/rv32zbb-valid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64b-aliases-valid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f78e0a236b63..a24e10318c78 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -224,6 +224,8 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine ,
}
if (Subtarget.hasStdExtZbp()) {
+// Custom lower bswap/bitreverse so we can convert them to GREVI to enable
+// more combining.
setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
setOperationAction(ISD::BSWAP, XLenVT, Custom);
@@ -232,7 +234,10 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine ,
setOperationAction(ISD::BSWAP, MVT::i32, Custom);
}
} else {
-setOperationAction(ISD::BSWAP, XLenVT, Expand);
+// With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
+// pattern match it directly in isel.
+setOperationAction(ISD::BSWAP, XLenVT,
+ Subtarget.hasStdExtZbb() ? Legal : Expand);
}
if (Subtarget.hasStdExtZbb()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 74660973e805..5a733c4bf771 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -481,6 +481,37 @@ def ZEXTH_RV64 : RVInstR<0b100, 0b100, OPC_OP_32,
(outs GPR:$rd),
}
} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+// We treat rev8 and orc.b as standalone instructions even though they use a
+// portion of the encodings for grevi and gorci. This allows us to support only
+// those encodings when only Zbb is enabled. We do this even when grevi and
+// gorci are available with Zbp. Trying to use 'HasStdExtZbb, NotHasStdExtZbp'
+// causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
+// or gorci. Since Zbb is closer to being finalized than Zbp this will be
+// misleading to users.
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+"rev8", "$rd, $rs1">, Sched<[]> {
+ let imm12 = { 0b01101, 0b0011000 };
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+"rev8", "$rd, $rs1">, Sched<[]> {
+ let imm12 = { 0b01101, 0b0111000 };
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
+ "orc.b", "$rd, $rs1">, Sched<[]> {
+ let imm12 = { 0b00101, 0b111 };
+}
+} // Predicates =
[llvm-branch-commits] [llvm] 3c94cee - [RISCV] Add zext.h instruction to Zbb.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 3c94cee63b401ca12457395bb1f4d70e161f9ec4
URL:
https://github.com/llvm/llvm-project/commit/3c94cee63b401ca12457395bb1f4d70e161f9ec4
DIFF:
https://github.com/llvm/llvm-project/commit/3c94cee63b401ca12457395bb1f4d70e161f9ec4.diff
LOG: [RISCV] Add zext.h instruction to Zbb.
zext.h uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.
I've added two new instructions with these specific encodings with
predicates that enable them when either Zbb or Zbp is enabled.
The pack spelling will only be accepted with Zbp. The disassembler
will use the zext.h instruction when either feature is enabled.
Using the pack spelling will print as pack when llvm-mc is
emitting text. We could fix this with some custom code in
processInstruction if this is important, but I'm not sure it is.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94818
Added:
Modified:
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbb.ll
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/MC/RISCV/rv32b-aliases-valid.s
llvm/test/MC/RISCV/rv32zbb-valid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64b-aliases-valid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 8f83b164baf7..a17abd0f96da 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -131,7 +131,9 @@ def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
// subextensions. They should be enabled if either has been specified.
def HasStdExtZbbOrZbp
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
-AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>;
+AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp),
+ "'Zbb' (Base 'B' Instructions) or "
+ "'Zbp' (Permutation 'B' Instructions)">;
def FeatureExtZbproposedc
: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc",
"true",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 120a47c3d36f..74660973e805 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -465,6 +465,22 @@ def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">,
Sched<[]>;
let Predicates = [HasStdExtZbf, IsRV64] in
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ZEXTH_RV32 : RVInstR<0b100, 0b100, OPC_OP, (outs GPR:$rd),
+ (ins GPR:$rs1), "zext.h", "$rd, $rs1">, Sched<[]> {
+ let rs2 = 0b0;
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def ZEXTH_RV64 : RVInstR<0b100, 0b100, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs1), "zext.h", "$rd, $rs1">, Sched<[]> {
+ let rs2 = 0b0;
+}
+} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+
//===--===//
// Future compressed instructions
//===--===//
@@ -500,14 +516,6 @@ def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
// Pseudo Instructions
//===--===//
-let Predicates = [HasStdExtZbp, IsRV32] in {
-def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
-} // Predicates = [HasStdExtZbb, IsRV32]
-
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
-} // Predicates = [HasStdExtZbb, IsRV64]
-
let Predicates = [HasStdExtZba, IsRV64] in {
// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
// changed to add.uw in a draft after 0.94.
@@ -805,10 +813,10 @@ def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00),
(and GPR:$rs1, 0x00FF)),
(PACKH GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbp, IsRV32] in
-def : Pat<(and GPR:$rs, 0x), (PACK GPR:$rs, X0)>;
-let Predicates = [HasStdExtZbp, IsRV64] in {
-def : Pat<(and GPR:$rs, 0x), (PACKW GPR:$rs, X0)>;
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
+def : Pat<(and GPR:$rs, 0x), (ZEXTH_RV32 GPR:$rs)>;
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def : Pat<(and GPR:$rs, 0x), (ZEXTH_RV64 GPR:$rs)>;
}
let Predicates = [HasStdExtZbp,
[llvm-branch-commits] [llvm] 83c92fd - [RISCV] Move pack instructions to Zbp extension only.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 83c92fdeda6be9a42739fa699926d41ce8a001fb
URL:
https://github.com/llvm/llvm-project/commit/83c92fdeda6be9a42739fa699926d41ce8a001fb
DIFF:
https://github.com/llvm/llvm-project/commit/83c92fdeda6be9a42739fa699926d41ce8a001fb.diff
LOG: [RISCV] Move pack instructions to Zbp extension only.
Zext.h will need to come back to Zbb, but that only uses specific
encodings of pack.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94742
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbbp.ll
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll
llvm/test/MC/RISCV/rv32zbbp-invalid.s
llvm/test/MC/RISCV/rv32zbbp-valid.s
llvm/test/MC/RISCV/rv32zbp-invalid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64zbbp-valid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 64dbbdc702fb..120a47c3d36f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -356,19 +356,17 @@ def BDECOMPRESS : ALU_rr<0b0100100, 0b110,
"bdecompress">, Sched<[]>;
def BCOMPRESS : ALU_rr<0b100, 0b110, "bcompress">, Sched<[]>;
} // Predicates = [HasStdExtZbe]
-let Predicates = [HasStdExtZbbOrZbp] in {
+let Predicates = [HasStdExtZbp] in {
def PACK : ALU_rr<0b100, 0b100, "pack">, Sched<[]>;
def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
-} // Predicates = [HasStdExtZbbOrZbp]
+def PACKH : ALU_rr<0b100, 0b111, "packh">, Sched<[]>;
+} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbm, IsRV64] in {
def BMATOR : ALU_rr<0b100, 0b011, "bmator">, Sched<[]>;
def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
} // Predicates = [HasStdExtZbm, IsRV64]
-let Predicates = [HasStdExtZbbOrZbp] in
-def PACKH : ALU_rr<0b100, 0b111, "packh">, Sched<[]>;
-
let Predicates = [HasStdExtZbf] in
def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
@@ -459,10 +457,10 @@ def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110,
"bdecompressw">, Sched<[]>;
def BCOMPRESSW : ALUW_rr<0b100, 0b110, "bcompressw">, Sched<[]>;
} // Predicates = [HasStdExtZbe, IsRV64]
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let Predicates = [HasStdExtZbp, IsRV64] in {
def PACKW : ALUW_rr<0b100, 0b100, "packw">, Sched<[]>;
def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
-} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
+} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbf, IsRV64] in
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
@@ -502,11 +500,11 @@ def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
// Pseudo Instructions
//===--===//
-let Predicates = [HasStdExtZbb, IsRV32] in {
+let Predicates = [HasStdExtZbp, IsRV32] in {
def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV32]
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZbp, IsRV64] in {
def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV64]
@@ -790,26 +788,26 @@ def : Pat<(umin GPR:$rs1, GPR:$rs2), (MINU GPR:$rs1,
GPR:$rs2)>;
def : Pat<(umax GPR:$rs1, GPR:$rs2), (MAXU GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbb]
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
+let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(or (and GPR:$rs1, 0x), (shl GPR:$rs2, (i32 16))),
(PACK GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
+let Predicates = [HasStdExtZbp, IsRV64] in
def : Pat<(or (and GPR:$rs1, 0x), (shl GPR:$rs2, (i64 32))),
(PACK GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
+let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(or (and GPR:$rs2, 0x), (srl GPR:$rs1, (i32 16))),
(PACKU GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
+let Predicates = [HasStdExtZbp, IsRV64] in
def : Pat<(or (and GPR:$rs2, 0x), (srl GPR:$rs1, (i64 32))),
(PACKU GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbbOrZbp] in
+let Predicates = [HasStdExtZbp] in
def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFF00),
(and GPR:$rs1, 0x00FF)),
(PACKH GPR:$rs1, GPR:$rs2)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
+let Predicates = [HasStdExtZbp, IsRV32] in
def : Pat<(and GPR:$rs, 0x), (PACK GPR:$rs, X0)>;
-let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+let Predicates = [HasStdExtZbp, IsRV64] in {
def : Pat<(and GPR:$rs,
[llvm-branch-commits] [llvm] 5ae92f1 - [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc
URL:
https://github.com/llvm/llvm-project/commit/5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc
DIFF:
https://github.com/llvm/llvm-project/commit/5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc.diff
LOG: [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack.
This didn't make it into the published 0.93 spec, but it was the
intention.
But it is in the tex source as of this commit
https://github.com/riscv/riscv-bitmanip/commit/d172f029c074d47026a0c0d0f12d8b475c86a472
This means zext.w now requires Zba. Not sure if we should still use
pack if Zbp is enabled and Zba isn't. I'll leave that for the future
when pack is closer to being final.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94736
Added:
Modified:
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv64Zba.ll
llvm/test/CodeGen/RISCV/rv64Zbbp.ll
llvm/test/MC/RISCV/rv64b-aliases-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 7b0eac7c2f1d..8f83b164baf7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -62,6 +62,7 @@ def FeatureExtZba
def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
AssemblerPredicate<(all_of FeatureExtZba),
"'Zba' (Address calculation 'B' Instructions)">;
+def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
def FeatureExtZbb
: SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
@@ -131,8 +132,6 @@ def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
def HasStdExtZbbOrZbp
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
AssemblerPredicate<(any_of FeatureExtZbb, FeatureExtZbp)>;
-def NotHasStdExtZbbOrZbp
-: Predicate<"!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp())">;
def FeatureExtZbproposedc
: SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc",
"true",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 0210a29e2ab4..38a8e6a151a8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1158,7 +1158,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1,
i32imm:$amt2),
/// RV64 patterns
-let Predicates = [IsRV64, NotHasStdExtZbbOrZbp] in
+let Predicates = [IsRV64, NotHasStdExtZba] in
def : Pat<(and GPR:$rs1, 0x), (SRLI (SLLI GPR:$rs1, 32), 32)>;
let Predicates = [IsRV64] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index ce1cbfc77520..64dbbdc702fb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -495,7 +495,7 @@ def C_NOT : RVBInstC<0b00, "c.not">, Sched<[]>;
def C_NEG : RVBInstC<0b01, "c.neg">, Sched<[]>;
} // DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC]
-let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc,
HasStdExtZbbOrZbp, HasStdExtC, IsRV64] in
+let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc,
HasStdExtZba, HasStdExtC, IsRV64] in
def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
//===--===//
@@ -508,9 +508,14 @@ def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs,
X0)>;
let Predicates = [HasStdExtZbb, IsRV64] in {
def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
-def : InstAlias<"zext.w $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>;
} // Predicates = [HasStdExtZbb, IsRV64]
+let Predicates = [HasStdExtZba, IsRV64] in {
+// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been
+// changed to add.uw in a draft after 0.94.
+def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
+}
+
let Predicates = [HasStdExtZbp] in {
def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b1)>;
def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
@@ -626,8 +631,8 @@ def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1),
(C_NEG GPRC:$rs1)>;
} // Predicates = [HasStdExtZbproposedc, HasStdExtC]
-let Predicates = [HasStdExtZbproposedc, HasStdExtZbbOrZbp, HasStdExtC, IsRV64]
in {
-def : CompressPat<(PACK GPRC:$rs1, GPRC:$rs1, X0),
+let Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in {
+def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
(C_ZEXTW GPRC:$rs1)>;
} // Predicates = [HasStdExtZbproposedc, HasStdExtC, IsRV64]
@@ -806,7 +811,6 @@ let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
def : Pat<(and
[llvm-branch-commits] [llvm] efbcd66 - [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2
URL:
https://github.com/llvm/llvm-project/commit/efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2
DIFF:
https://github.com/llvm/llvm-project/commit/efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2.diff
LOG: [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to
match 0.93 bitmanip spec.
Also renamed Zbe instructions to resolve name conflict even though
that change is in the 0.94 draft.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94653
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbs.ll
llvm/test/CodeGen/RISCV/rv32Zbt.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbs.ll
llvm/test/MC/RISCV/rv32zbe-invalid.s
llvm/test/MC/RISCV/rv32zbe-valid.s
llvm/test/MC/RISCV/rv32zbs-invalid.s
llvm/test/MC/RISCV/rv32zbs-valid.s
llvm/test/MC/RISCV/rv64zbe-invalid.s
llvm/test/MC/RISCV/rv64zbe-valid.s
llvm/test/MC/RISCV/rv64zbs-invalid.s
llvm/test/MC/RISCV/rv64zbs-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 8ac886228249..ed277939b635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -85,26 +85,26 @@ def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
}]>;
// Checks if this mask has a single 0 bit and cannot be used with ANDI.
-def SBCLRMask : ImmLeafis64Bit())
return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
}]>;
// Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
-def SBSETINVMask : ImmLeafis64Bit())
return !isInt<12>(Imm) && isPowerOf2_64(Imm);
return !isInt<12>(Imm) && isPowerOf2_32(Imm);
}]>;
-def SBCLRXForm : SDNodeXFormgetTargetConstant(N->getAPIntValue().countTrailingOnes(),
SDLoc(N), N->getValueType(0));
}]>;
-def SBSETINVXForm : SDNodeXFormgetTargetConstant(N->getAPIntValue().countTrailingZeros(),
SDLoc(N), N->getValueType(0));
@@ -112,13 +112,13 @@ def SBSETINVXForm : SDNodeXForm(Imm) && !isInt<12>(Imm) && isPowerOf2_32(~Imm);
}]>;
-def SBSETINVWMask : ImmLeaf(Imm) && !isInt<12>(Imm) && isPowerOf2_32(Imm);
}]>;
@@ -241,10 +241,10 @@ def ROR : ALU_rr<0b011, 0b101, "ror">, Sched<[]>;
} // Predicates = [HasStdExtZbbOrZbp]
let Predicates = [HasStdExtZbs] in {
-def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">, Sched<[]>;
-def SBSET : ALU_rr<0b0010100, 0b001, "sbset">, Sched<[]>;
-def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">, Sched<[]>;
-def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">, Sched<[]>;
+def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, Sched<[]>;
+def BSET : ALU_rr<0b0010100, 0b001, "bset">, Sched<[]>;
+def BINV : ALU_rr<0b0110100, 0b001, "binv">, Sched<[]>;
+def BEXT : ALU_rr<0b0100100, 0b101, "bext">, Sched<[]>;
} // Predicates = [HasStdExtZbs]
let Predicates = [HasStdExtZbp] in {
@@ -261,10 +261,10 @@ let Predicates = [HasStdExtZbbOrZbp] in
def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, Sched<[]>;
let Predicates = [HasStdExtZbs] in {
-def SBCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "sbclri">, Sched<[]>;
-def SBSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "sbseti">, Sched<[]>;
-def SBINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "sbinvi">, Sched<[]>;
-def SBEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "sbexti">, Sched<[]>;
+def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">, Sched<[]>;
+def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">, Sched<[]>;
+def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">, Sched<[]>;
+def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, Sched<[]>;
} // Predicates = [HasStdExtZbs]
let Predicates = [HasStdExtZbp] in {
@@ -350,8 +350,10 @@ def UNSHFL : ALU_rr<0b100, 0b101, "unshfl">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbe] in {
-def BDEP : ALU_rr<0b0100100, 0b110, "bdep">, Sched<[]>;
-def BEXT : ALU_rr<0b100, 0b110, "bext">, Sched<[]>;
+// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
+// bext in the 0.93 spec.
+def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
+def BCOMPRESS : ALU_rr<0b100, 0b110, "bcompress">, Sched<[]>;
} // Predicates = [HasStdExtZbe]
let Predicates = [HasStdExtZbbOrZbp] in {
@@ -394,10 +396,10 @@ def RORW : ALUW_rr<0b011, 0b101, "rorw">, Sched<[]>;
} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
let Predicates = [HasStdExtZbs, IsRV64] in {
-def SBCLRW : ALUW_rr<0b0100100, 0b001, "sbclrw">, Sched<[]>;
-def SBSETW : ALUW_rr<0b0010100, 0b001, "sbsetw">, Sched<[]>;
-def SBINVW : ALUW_rr<0b0110100, 0b001, "sbinvw">,
[llvm-branch-commits] [llvm] 9d499e0 - [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 9d499e037e6bc3365e6ad1423a388dc7a37627b0
URL:
https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0
DIFF:
https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0.diff
LOG: [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match
0.93 bitmanip spec.
The 0.93 spec has this implementation for add.uw
uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
uint_xlen_t rs1u = (uint32_t)rs1;
return rs1u + rs2;
}
The 0.92 spec had the usages of rs1 and rs2 swapped.
Reviewed By: frasercrmck, asb
Differential Revision: https://reviews.llvm.org/D95090
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv64Zba.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index ed277939b635..ce1cbfc77520 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -856,7 +856,7 @@ def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(shl (and GPR:$rs1, 0x), uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0x))),
+def : Pat<(add (and GPR:$rs1, (i64 0x)), GPR:$rs2),
(ADDUW GPR:$rs1, GPR:$rs2)>;
}
diff --git a/llvm/test/CodeGen/RISCV/rv64Zba.ll
b/llvm/test/CodeGen/RISCV/rv64Zba.ll
index b5a9704ae54b..597ad5fc3cd0 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zba.ll
@@ -72,12 +72,12 @@ define i64 @adduw(i64 %a, i64 %b) nounwind {
;
; RV64IB-LABEL: adduw:
; RV64IB: # %bb.0:
-; RV64IB-NEXT:add.uw a0, a0, a1
+; RV64IB-NEXT:add.uw a0, a1, a0
; RV64IB-NEXT:ret
;
; RV64IBA-LABEL: adduw:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT:add.uw a0, a0, a1
+; RV64IBA-NEXT:add.uw a0, a1, a0
; RV64IBA-NEXT:ret
%and = and i64 %b, 4294967295
%add = add i64 %and, %a
@@ -95,13 +95,13 @@ define signext i8 @adduw_2(i32 signext %0, i8* %1) {
;
; RV64IB-LABEL: adduw_2:
; RV64IB: # %bb.0:
-; RV64IB-NEXT:add.uw a0, a1, a0
+; RV64IB-NEXT:add.uw a0, a0, a1
; RV64IB-NEXT:lb a0, 0(a0)
; RV64IB-NEXT:ret
;
; RV64IBA-LABEL: adduw_2:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT:add.uw a0, a1, a0
+; RV64IBA-NEXT:add.uw a0, a0, a1
; RV64IBA-NEXT:lb a0, 0(a0)
; RV64IBA-NEXT:ret
%3 = zext i32 %0 to i64
___
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[llvm-branch-commits] [llvm] 1355458 - [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 1355458ef665b3044e3dfb57acf0c2e7439560fe
URL:
https://github.com/llvm/llvm-project/commit/1355458ef665b3044e3dfb57acf0c2e7439560fe
DIFF:
https://github.com/llvm/llvm-project/commit/1355458ef665b3044e3dfb57acf0c2e7439560fe.diff
LOG: [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93
bitmanip spec.
It's not really clear in the spec that these are in Zbp now, but
that's what I've gather from previous commits to the spec. I've
file an issue to get it documented properly.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94652
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbb.ll
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll
llvm/test/MC/RISCV/rv32zbb-invalid.s
llvm/test/MC/RISCV/rv32zbb-valid.s
llvm/test/MC/RISCV/rv32zbp-invalid.s
llvm/test/MC/RISCV/rv32zbp-valid.s
llvm/test/MC/RISCV/rv64zbb-invalid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
llvm/test/MC/RISCV/rv64zbp-invalid.s
llvm/test/MC/RISCV/rv64zbp-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index ef0a29d40893..8ac886228249 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -230,10 +230,10 @@ def SH2ADD : ALU_rr<0b001, 0b100, "sh2add">,
Sched<[]>;
def SH3ADD : ALU_rr<0b001, 0b110, "sh3add">, Sched<[]>;
} // Predicates = [HasStdExtZba]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbp] in {
def SLO : ALU_rr<0b001, 0b001, "slo">, Sched<[]>;
def SRO : ALU_rr<0b001, 0b101, "sro">, Sched<[]>;
-} // Predicates = [HasStdExtZbb]
+} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbbOrZbp] in {
def ROL : ALU_rr<0b011, 0b001, "rol">, Sched<[]>;
@@ -252,10 +252,10 @@ def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbp] in {
def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>;
def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>;
-} // Predicates = [HasStdExtZbb]
+} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbbOrZbp] in
def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, Sched<[]>;
@@ -383,10 +383,10 @@ def SH2ADDUW : ALUW_rr<0b001, 0b100, "sh2add.uw">,
Sched<[]>;
def SH3ADDUW : ALUW_rr<0b001, 0b110, "sh3add.uw">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZbp, IsRV64] in {
def SLOW : ALUW_rr<0b001, 0b001, "slow">, Sched<[]>;
def SROW : ALUW_rr<0b001, 0b101, "srow">, Sched<[]>;
-} // Predicates = [HasStdExtZbb, IsRV64]
+} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
def ROLW : ALUW_rr<0b011, 0b001, "rolw">, Sched<[]>;
@@ -405,10 +405,10 @@ def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">,
Sched<[]>;
def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64]
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZbp, IsRV64] in {
def SLOIW : RVBShiftW_ri<0b001, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>;
def SROIW : RVBShiftW_ri<0b001, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>;
-} // Predicates = [HasStdExtZbb, IsRV64]
+} // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
def RORIW : RVBShiftW_ri<0b011, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[]>;
@@ -637,12 +637,12 @@ def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1,
GPR:$rs2)>;
def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbbOrZbp]
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbp] in {
def : Pat<(not (shl (not GPR:$rs1), GPR:$rs2)),
(SLO GPR:$rs1, GPR:$rs2)>;
def : Pat<(not (srl (not GPR:$rs1), GPR:$rs2)),
(SRO GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtZbb]
+} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbbOrZbp] in {
def : Pat<(rotl GPR:$rs1, GPR:$rs2), (ROL GPR:$rs1, GPR:$rs2)>;
@@ -671,12 +671,12 @@ def : Pat<(xor GPR:$rs1, SBSETINVMask:$mask),
(SBINVI GPR:$rs1, (SBSETINVXForm imm:$mask))>;
}
-let Predicates = [HasStdExtZbb] in {
+let Predicates = [HasStdExtZbp] in {
def : Pat<(SLOIPat GPR:$rs1, uimmlog2xlen:$shamt),
(SLOI GPR:$rs1, uimmlog2xlen:$shamt)>;
def : Pat<(SROIPat GPR:$rs1, uimmlog2xlen:$shamt),
(SROI GPR:$rs1, uimmlog2xlen:$shamt)>;
-} // Predicates = [HasStdExtZbb]
+} //
[llvm-branch-commits] [llvm] 4e6ad11 - [RISCV] Add Zba feature and move add.uw and slli.uw to it.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024
URL:
https://github.com/llvm/llvm-project/commit/4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024
DIFF:
https://github.com/llvm/llvm-project/commit/4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024.diff
LOG: [RISCV] Add Zba feature and move add.uw and slli.uw to it.
Still need to add SH*ADD instructions.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94617
Added:
llvm/test/CodeGen/RISCV/rv64Zba.ll
llvm/test/MC/RISCV/rv64zba-invalid.s
llvm/test/MC/RISCV/rv64zba-valid.s
Modified:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-arch.c
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/rv64Zbb.ll
llvm/test/MC/RISCV/rv64zbb-invalid.s
llvm/test/MC/RISCV/rv64zbb-valid.s
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index aa1a5d8c803f..22a4625946f8 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -58,9 +58,9 @@ static StringRef getExtensionType(StringRef Ext) {
// extension that the compiler currently supports.
static Optional
isExperimentalExtension(StringRef Ext) {
- if (Ext == "b" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" ||
- Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" ||
- Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+ if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
+ Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
+ Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
return RISCVExtensionVersion{"0", "92"};
if (Ext == "v")
return RISCVExtensionVersion{"0", "9"};
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 533f1cff42af..58e5eb2c8332 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -365,6 +365,10 @@
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s
// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name
'rv32izbb0p92zbp0p92', multi-character extensions must be separated by
underscores
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izba0p92
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
+// RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
// RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 02424f6d86ff..7b0eac7c2f1d 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -56,6 +56,13 @@ def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
"'C' (Compressed Instructions)">;
+def FeatureExtZba
+: SubtargetFeature<"experimental-zba", "HasStdExtZba", "true",
+ "'Zba' (Base 'B' Instructions)">;
+def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
+ AssemblerPredicate<(all_of FeatureExtZba),
+ "'Zba' (Address calculation 'B' Instructions)">;
+
def FeatureExtZbb
: SubtargetFeature<"experimental-zbb", "HasStdExtZbb", "true",
"'Zbb' (Base 'B' Instructions)">;
@@ -137,7 +144,8 @@ def HasStdExtZbproposedc :
Predicate<"Subtarget->hasStdExtZbproposedc()">,
def FeatureStdExtB
: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
"'B' (Bit Manipulation Instructions)",
- [FeatureExtZbb,
+ [FeatureExtZba,
+FeatureExtZbb,
FeatureExtZbc,
FeatureExtZbe,
FeatureExtZbf,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index e68aa90310a0..537fbf9a7676 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -369,7 +369,7 @@ def SHFLI : RVBShfl_ri<0b10, 0b001, OPC_OP_IMM,
"shfli">, Sched<[]>;
def UNSHFLI : RVBShfl_ri<0b10, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
-let Predicates = [HasStdExtZbb, IsRV64] in {
+let Predicates = [HasStdExtZba, IsRV64] in {
def SLLIUW : RVBShift_ri<0b1, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
def ADDUW : ALUW_rr<0b100, 0b000, "add.uw">, Sched<[]>;
}
[llvm-branch-commits] [llvm] 83a93ae - [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec.
Author: Craig Topper
Date: 2021-01-22T12:49:10-08:00
New Revision: 83a93ae63b1c8cc515a08c7fc4b78813e448c874
URL:
https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874
DIFF:
https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874.diff
LOG: [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93
bitmanip spec.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D94637
Added:
llvm/test/MC/RISCV/rv32zba-invalid.s
llvm/test/MC/RISCV/rv32zba-valid.s
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/MC/RISCV/rv64zba-invalid.s
llvm/test/MC/RISCV/rv64zba-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 537fbf9a7676..ef0a29d40893 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -224,6 +224,12 @@ def ORN : ALU_rr<0b010, 0b110, "orn">, Sched<[]>;
def XNOR : ALU_rr<0b010, 0b100, "xnor">, Sched<[]>;
} // Predicates = [HasStdExtZbbOrZbp]
+let Predicates = [HasStdExtZba] in {
+def SH1ADD : ALU_rr<0b001, 0b010, "sh1add">, Sched<[]>;
+def SH2ADD : ALU_rr<0b001, 0b100, "sh2add">, Sched<[]>;
+def SH3ADD : ALU_rr<0b001, 0b110, "sh3add">, Sched<[]>;
+} // Predicates = [HasStdExtZba]
+
let Predicates = [HasStdExtZbb] in {
def SLO : ALU_rr<0b001, 0b001, "slo">, Sched<[]>;
def SRO : ALU_rr<0b001, 0b101, "sro">, Sched<[]>;
@@ -372,6 +378,9 @@ def UNSHFLI : RVBShfl_ri<0b10, 0b101, OPC_OP_IMM,
"unshfli">, Sched<[]>;
let Predicates = [HasStdExtZba, IsRV64] in {
def SLLIUW : RVBShift_ri<0b1, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
def ADDUW : ALUW_rr<0b100, 0b000, "add.uw">, Sched<[]>;
+def SH1ADDUW : ALUW_rr<0b001, 0b010, "sh1add.uw">, Sched<[]>;
+def SH2ADDUW : ALUW_rr<0b001, 0b100, "sh2add.uw">, Sched<[]>;
+def SH3ADDUW : ALUW_rr<0b001, 0b110, "sh3add.uw">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbb, IsRV64] in {
diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s
b/llvm/test/MC/RISCV/rv32zba-invalid.s
new file mode 100644
index ..64adfe03fdfb
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zba-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zba <
%s 2>&1 | FileCheck %s
+
+# Too few operands
+sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32zba-valid.s
b/llvm/test/MC/RISCV/rv32zba-valid.s
new file mode 100644
index ..20f40d8d44da
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zba-valid.s
@@ -0,0 +1,23 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
+# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zba -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zba < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zba -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sh1add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x20]
+sh1add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh2add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x20]
+sh2add t0, t1, t2
+# CHECK-ASM-AND-OBJ: sh3add t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x20]
+sh3add t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64zba-invalid.s
b/llvm/test/MC/RISCV/rv64zba-invalid.s
index 28f04e33fc0d..02ba66d87949 100644
--- a/llvm/test/MC/RISCV/rv64zba-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zba-invalid.s
@@ -7,3 +7,9 @@ slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate
must be an integer i
slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer
in the range [0, 63]
# Too few operands
add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh1add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh2add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sh3add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64zba-valid.s
b/llvm/test/MC/RISCV/rv64zba-valid.s
