Mesa (main): glsl/nir: fix gl_nir_cross_validate_outputs_to_inputs() memory leak

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: bacace8634346f853547f51a0ea6ff8082a8dcb8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bacace8634346f853547f51a0ea6ff8082a8dcb8

Author: Patrick Lerda 
Date:   Fri Jan 12 02:18:35 2024 +0100

glsl/nir: fix gl_nir_cross_validate_outputs_to_inputs() memory leak

For instance, this issue is triggered with
vs-to-fs-overlap.shader_test -auto -fbo:
Direct leak of 24 byte(s) in 1 object(s) allocated from:
#0 0x7fe64f58e9a7 in calloc (/usr/lib64/libasan.so.6+0xb19a7)
#1 0x7fe642ca2839 in _mesa_symbol_table_ctor 
../src/mesa/program/symbol_table.c:286
#2 0x7fe642ff003d in gl_nir_cross_validate_outputs_to_inputs 
../src/compiler/glsl/gl_nir_link_varyings.c:728
#3 0x7fe642d7c7d8 in gl_nir_link_glsl 
../src/compiler/glsl/gl_nir_linker.c:1357
#4 0x7fe642be6931 in st_link_glsl_to_nir 
../src/mesa/state_tracker/st_glsl_to_nir.cpp:562
#5 0x7fe642be6931 in st_link_shader 
../src/mesa/state_tracker/st_glsl_to_nir.cpp:944
#6 0x7fe642acab55 in link_program ../src/mesa/main/shaderapi.c:1336
#7 0x7fe642acab55 in link_program_error ../src/mesa/main/shaderapi.c:1447
#8 0x7fe6424aa389 in _mesa_unmarshal_LinkProgram 
src/mapi/glapi/gen/marshal_generated2.c:1911
#9 0x7fe641fd912b in glthread_unmarshal_batch 
../src/mesa/main/glthread.c:139
#10 0x7fe641f48d48 in util_queue_thread_func ../src/util/u_queue.c:309
#11 0x7fe641fa442a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67

Fixes: 7d1948e9b5d9 ("glsl: implement cross_validate_outputs_to_inputs() in nir 
linker")
Signed-off-by: Patrick Lerda 
Reviewed-by: Marek Olšák 
Part-of: 

---

 src/compiler/glsl/gl_nir_link_varyings.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/gl_nir_link_varyings.c 
b/src/compiler/glsl/gl_nir_link_varyings.c
index 234d4485c1c..4f576f2ee71 100644
--- a/src/compiler/glsl/gl_nir_link_varyings.c
+++ b/src/compiler/glsl/gl_nir_link_varyings.c
@@ -745,7 +745,7 @@ gl_nir_cross_validate_outputs_to_inputs(const struct 
gl_constants *consts,
  if (!validate_explicit_variable_location(consts,
   output_explicit_locations,
   var, prog, producer)) {
-return;
+goto out;
  }
   }
}
@@ -799,7 +799,7 @@ gl_nir_cross_validate_outputs_to_inputs(const struct 
gl_constants *consts,
 if (!validate_explicit_variable_location(consts,
  input_explicit_locations,
  input, prog, consumer)) {
-   return;
+   goto out;
 }
 
 while (idx < slot_limit) {
@@ -807,7 +807,7 @@ gl_nir_cross_validate_outputs_to_inputs(const struct 
gl_constants *consts,
   linker_error(prog,
"Invalid location %u in %s shader\n", idx,
_mesa_shader_stage_to_string(consumer->Stage));
-  return;
+  goto out;
}
 
output = 
output_explicit_locations[idx][input->data.location_frac].var;
@@ -870,6 +870,7 @@ gl_nir_cross_validate_outputs_to_inputs(const struct 
gl_constants *consts,
   }
}
 
+ out:
_mesa_symbol_table_dtor(table);
 }
 

Mesa (main): util: Optimize mesa_hex_to_bytes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 0a68a94a513716884c4a8c46c543ffc8bcf8e9c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a68a94a513716884c4a8c46c543ffc8bcf8e9c7

Author: Tatsuyuki Ishi 
Date:   Sun Jan 14 01:25:17 2024 +0900

util: Optimize mesa_hex_to_bytes

This function ends up getting called an awful lot when loading a large
Fossilize cache db, so let's replace strtol with something more
reasonable.

For a game with 97k shaders, this reduces instance creation time from
203ms to 52ms.

Reviewed-by: Marek Olšák 
Reviewed-by: Georg Lehmann 
Part-of: 

---

 src/util/hex.h | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/util/hex.h b/src/util/hex.h
index 5bd618046e1..20a26a0e18a 100644
--- a/src/util/hex.h
+++ b/src/util/hex.h
@@ -23,8 +23,6 @@
 #ifndef UTIL_HEX_H
 #define UTIL_HEX_H
 
-#include 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -47,18 +45,24 @@ static inline char *mesa_bytes_to_hex(char *buf, const 
unsigned char *binary,
   return buf;
 }
 
+static inline int _mesa_hex_to_int(unsigned char c)
+{
+  return c - (c >= 'a' ? 'a' - 10 : '0');
+}
+
 /*
  * Read `len` pairs of hexadecimal digits from `hex` and write the values to
  * `binary` as `len` bytes.
+ * Hexadecimals must be lower case.
  */
 static inline void mesa_hex_to_bytes(unsigned char *buf, const char *hex,
- unsigned len) {
+ unsigned len)
+{
   for (unsigned i = 0; i < len; i++) {
-char tmp[3];
-tmp[0] = hex[i * 2];
-tmp[1] = hex[(i * 2) + 1];
-tmp[2] = '\0';
-buf[i] = strtol(tmp, NULL, 16);
+int hi = _mesa_hex_to_int(hex[i * 2]);
+int lo = _mesa_hex_to_int(hex[i * 2 + 1]);
+
+buf[i] = (hi << 4) | lo;
   }
 }
 
@@ -66,4 +70,4 @@ static inline void mesa_hex_to_bytes(unsigned char *buf, 
const char *hex,
 }
 #endif
 
-#endif
\ No newline at end of file
+#endif

Mesa (main): vulkan/video: rename some of the parameter tracking structs.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b72b4d8a0eda81c306746f453462d1d9752f7d4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b72b4d8a0eda81c306746f453462d1d9752f7d4f

Author: Dave Airlie 
Date:   Mon Jan 15 15:07:03 2024 +1000

vulkan/video: rename some of the parameter tracking structs.

This will make it easier to add deep copy support.

Reviewed-by: Hyunjun Ko 
Part-of: 

---

 src/amd/vulkan/radv_video.c   |   2 +-
 src/vulkan/runtime/vk_video.c | 236 +-
 src/vulkan/runtime/vk_video.h |  64 ++--
 3 files changed, 151 insertions(+), 151 deletions(-)

diff --git a/src/amd/vulkan/radv_video.c b/src/amd/vulkan/radv_video.c
index 7591d4e6143..8df25754f05 100644
--- a/src/amd/vulkan/radv_video.c
+++ b/src/amd/vulkan/radv_video.c
@@ -785,7 +785,7 @@ get_h264_msg(struct radv_video_session *vid, struct 
radv_video_session_params *p
 
memset(, 0, sizeof(result));
 
-   assert(params->vk.h264_dec.std_sps_count > 0);
+   assert(params->vk.h264_dec.h264_sps_count > 0);
const StdVideoH264SequenceParameterSet *sps =
   vk_video_find_h264_dec_std_sps(>vk, 
h264_pic_info->pStdPictureInfo->seq_parameter_set_id);
switch (sps->profile_idc) {
diff --git a/src/vulkan/runtime/vk_video.c b/src/vulkan/runtime/vk_video.c
index 167c5879120..18e555652e8 100644
--- a/src/vulkan/runtime/vk_video.c
+++ b/src/vulkan/runtime/vk_video.c
@@ -122,18 +122,18 @@ vk_video_session_init(struct vk_device *device,
   return VK_SUCCESS;\
}
 
-FIND(StdVideoH264SequenceParameterSet, h264_dec, std_sps, seq_parameter_set_id)
-FIND(StdVideoH264PictureParameterSet, h264_dec, std_pps, pic_parameter_set_id)
-FIND(StdVideoH265VideoParameterSet, h265_dec, std_vps, 
vps_video_parameter_set_id)
-FIND(StdVideoH265SequenceParameterSet, h265_dec, std_sps, 
sps_seq_parameter_set_id)
-FIND(StdVideoH265PictureParameterSet, h265_dec, std_pps, 
pps_pic_parameter_set_id)
+FIND(StdVideoH264SequenceParameterSet, h264_dec, h264_sps, 
seq_parameter_set_id)
+FIND(StdVideoH264PictureParameterSet, h264_dec, h264_pps, pic_parameter_set_id)
+FIND(StdVideoH265VideoParameterSet, h265_dec, h265_vps, 
vps_video_parameter_set_id)
+FIND(StdVideoH265SequenceParameterSet, h265_dec, h265_sps, 
sps_seq_parameter_set_id)
+FIND(StdVideoH265PictureParameterSet, h265_dec, h265_pps, 
pps_pic_parameter_set_id)
 
-FIND(StdVideoH264SequenceParameterSet, h264_enc, std_sps, seq_parameter_set_id)
-FIND(StdVideoH264PictureParameterSet, h264_enc, std_pps, pic_parameter_set_id)
+FIND(StdVideoH264SequenceParameterSet, h264_enc, h264_sps, 
seq_parameter_set_id)
+FIND(StdVideoH264PictureParameterSet, h264_enc, h264_pps, pic_parameter_set_id)
 
-FIND(StdVideoH265VideoParameterSet, h265_enc, std_vps, 
vps_video_parameter_set_id)
-FIND(StdVideoH265SequenceParameterSet, h265_enc, std_sps, 
sps_seq_parameter_set_id)
-FIND(StdVideoH265PictureParameterSet, h265_enc, std_pps, 
pps_pic_parameter_set_id)
+FIND(StdVideoH265VideoParameterSet, h265_enc, h265_vps, 
vps_video_parameter_set_id)
+FIND(StdVideoH265SequenceParameterSet, h265_enc, h265_sps, 
sps_seq_parameter_set_id)
+FIND(StdVideoH265PictureParameterSet, h265_enc, h265_pps, 
pps_pic_parameter_set_id)
 
 static void
 init_add_h264_dec_session_parameters(struct vk_video_session_parameters 
*params,
@@ -144,23 +144,23 @@ init_add_h264_dec_session_parameters(struct 
vk_video_session_parameters *params,
 
if (h264_add) {
   for (i = 0; i < h264_add->stdSPSCount; i++) {
- add_h264_dec_std_sps(params, _add->pStdSPSs[i], false);
+ add_h264_dec_h264_sps(params, _add->pStdSPSs[i], false);
   }
}
if (templ) {
-  for (i = 0; i < templ->h264_dec.std_sps_count; i++) {
- add_h264_dec_std_sps(params, >h264_dec.std_sps[i], true);
+  for (i = 0; i < templ->h264_dec.h264_sps_count; i++) {
+ add_h264_dec_h264_sps(params, >h264_dec.h264_sps[i], true);
   }
}
 
if (h264_add) {
   for (i = 0; i < h264_add->stdPPSCount; i++) {
- add_h264_dec_std_pps(params, _add->pStdPPSs[i], false);
+ add_h264_dec_h264_pps(params, _add->pStdPPSs[i], false);
   }
}
if (templ) {
-  for (i = 0; i < templ->h264_dec.std_pps_count; i++) {
- add_h264_dec_std_pps(params, >h264_dec.std_pps[i], true);
+  for (i = 0; i < templ->h264_dec.h264_pps_count; i++) {
+ add_h264_dec_h264_pps(params, >h264_dec.h264_pps[i], true);
   }
}
 }
@@ -173,23 +173,23 @@ init_add_h264_enc_session_parameters(struct 
vk_video_session_parameters *params,
unsigned i;
if (h264_add) {
   for (i = 0; i < h264_add->stdSPSCount; i++) {
- add_h264_enc_std_sps(params, _add->pStdSPSs[i], false);
+ add_h264_enc_h264_sps(params, _add->pStdSPSs[i], false);
   }
}
if (templ) {
-  for (i = 0; i < templ->h264_dec.std_sps_count; i++) {
- add_h264_enc_std_sps(params, 

Mesa (main): vulkan/video: start to wrap the video structs for deep copies.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b4a6a876bee8d2f3ec74aeee0da4fa75f8c0df62
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4a6a876bee8d2f3ec74aeee0da4fa75f8c0df62

Author: Dave Airlie 
Date:   Mon Jan 15 15:14:48 2024 +1000

vulkan/video: start to wrap the video structs for deep copies.

This doesn't do any of the deep copies, it's just more non-functional changes
in preparation.

v2: fix alloc sizes

Reviewed-by: Hyunjun Ko 
Part-of: 

---

 src/vulkan/runtime/vk_video.c | 74 +--
 src/vulkan/runtime/vk_video.h | 40 +--
 2 files changed, 67 insertions(+), 47 deletions(-)

diff --git a/src/vulkan/runtime/vk_video.c b/src/vulkan/runtime/vk_video.c
index 18e555652e8..382fcdfe511 100644
--- a/src/vulkan/runtime/vk_video.c
+++ b/src/vulkan/runtime/vk_video.c
@@ -94,30 +94,30 @@ vk_video_session_init(struct vk_device *device,
 }
 
 #define FIND(PARAMSET, SS, SET, ID) \
-   static PARAMSET *find_##SS##_##SET(const struct vk_video_session_parameters 
*params, uint32_t id) { \
+   static struct vk_video_##SET *find_##SS##_##SET(const struct 
vk_video_session_parameters *params, uint32_t id) { \
   for (unsigned i = 0; i < params->SS.SET##_count; i++) {   \
- if (params->SS.SET[i].ID == id)\
-return >SS.SET[i];  \
+ if (params->SS.SET[i].base.ID == id)   \
+return >SS.SET[i]; \
   } \
   return NULL;  \
}\
 \
static void add_##SS##_##SET(struct vk_video_session_parameters *params, \
 const PARAMSET *new_set, bool noreplace) {  \
-  PARAMSET *set = find_##SS##_##SET(params, new_set->ID);   \
+  struct vk_video_##SET *set = find_##SS##_##SET(params, new_set->ID); 
  \
   if (set) {\
 if (noreplace) \
 return; \
- *set = *new_set;   \
+ set->base = *new_set;  \
   } else\
- params->SS.SET[params->SS.SET##_count++] = *new_set;   \
+ params->SS.SET[params->SS.SET##_count++].base = *new_set;  \
}\
 \
static VkResult update_##SS##_##SET(struct vk_video_session_parameters 
*params, \
uint32_t count, const PARAMSET 
*updates) { \
   if (params->SS.SET##_count + count >= params->SS.max_##SET##_count) \
  return VK_ERROR_TOO_MANY_OBJECTS;  \
-  typed_memcpy(>SS.SET[params->SS.SET##_count], updates, count); \
+  typed_memcpy(>SS.SET[params->SS.SET##_count].base, updates, 
count); \
   params->SS.SET##_count += count;  \
   return VK_SUCCESS;\
}
@@ -149,7 +149,7 @@ init_add_h264_dec_session_parameters(struct 
vk_video_session_parameters *params,
}
if (templ) {
   for (i = 0; i < templ->h264_dec.h264_sps_count; i++) {
- add_h264_dec_h264_sps(params, >h264_dec.h264_sps[i], true);
+ add_h264_dec_h264_sps(params, >h264_dec.h264_sps[i].base, 
true);
   }
}
 
@@ -160,7 +160,7 @@ init_add_h264_dec_session_parameters(struct 
vk_video_session_parameters *params,
}
if (templ) {
   for (i = 0; i < templ->h264_dec.h264_pps_count; i++) {
- add_h264_dec_h264_pps(params, >h264_dec.h264_pps[i], true);
+ add_h264_dec_h264_pps(params, >h264_dec.h264_pps[i].base, 
true);
   }
}
 }
@@ -178,7 +178,7 @@ init_add_h264_enc_session_parameters(struct 
vk_video_session_parameters *params,
}
if (templ) {
   for (i = 0; i < templ->h264_dec.h264_sps_count; i++) {
- add_h264_enc_h264_sps(params, >h264_enc.h264_sps[i], true);
+ add_h264_enc_h264_sps(params, >h264_enc.h264_sps[i].base, 
true);
   }
}
 
@@ -189,7 +189,7 @@ init_add_h264_enc_session_parameters(struct 
vk_video_session_parameters *params,
}
if (templ) {
   for (i = 0; i < templ->h264_enc.h264_pps_count; i++) {
- add_h264_enc_h264_pps(params, >h264_enc.h264_pps[i], true);
+ add_h264_enc_h264_pps(params, 

Mesa (main): vulkan/video: drop unused function.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 57d83cb99cab81be58534c7d468c8bd7bb9f9e6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57d83cb99cab81be58534c7d468c8bd7bb9f9e6f

Author: Dave Airlie 
Date:   Mon Jan 15 15:23:13 2024 +1000

vulkan/video: drop unused function.

This looks to have been left over.

Reviewed-by: Hyunjun Ko 
Part-of: 

---

 src/vulkan/runtime/vk_video.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/src/vulkan/runtime/vk_video.c b/src/vulkan/runtime/vk_video.c
index f3153b4a1f6..167c5879120 100644
--- a/src/vulkan/runtime/vk_video.c
+++ b/src/vulkan/runtime/vk_video.c
@@ -415,18 +415,6 @@ vk_video_session_parameters_finish(struct vk_device 
*device,
vk_object_base_finish(>base);
 }
 
-static VkResult
-update_sps(struct vk_video_session_parameters *params,
-   uint32_t count, const StdVideoH264SequenceParameterSet *adds)
-{
-if (params->h264_dec.std_sps_count + count >= 
params->h264_dec.max_std_sps_count)
-  return VK_ERROR_TOO_MANY_OBJECTS;
-
-   typed_memcpy(>h264_dec.std_sps[params->h264_dec.std_sps_count], 
adds, count);
-   params->h264_dec.std_sps_count += count;
-   return VK_SUCCESS;
-}
-
 static VkResult
 update_h264_dec_session_parameters(struct vk_video_session_parameters *params,
const struct 
VkVideoDecodeH264SessionParametersAddInfoKHR *h264_add)

Mesa (main): vulkan/video: start deep copying the parameters structures

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 34e72579cda63681c2d49ef6eb3e9ddd2bca705e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34e72579cda63681c2d49ef6eb3e9ddd2bca705e

Author: Dave Airlie 
Date:   Mon Jan 15 15:20:55 2024 +1000

vulkan/video: start deep copying the parameters structures

Joshua Ashton pointed out we aren't copying these deeply,
and we really should be.

This introduces deep copies of all the h264/h265 parameter sets.

Reviewed-by: Hyunjun Ko 
Part-of: 

---

 src/vulkan/runtime/vk_video.c | 147 --
 src/vulkan/runtime/vk_video.h |  22 +++
 2 files changed, 164 insertions(+), 5 deletions(-)

diff --git a/src/vulkan/runtime/vk_video.c b/src/vulkan/runtime/vk_video.c
index 382fcdfe511..99cf30f35ff 100644
--- a/src/vulkan/runtime/vk_video.c
+++ b/src/vulkan/runtime/vk_video.c
@@ -93,11 +93,147 @@ vk_video_session_init(struct vk_device *device,
return VK_SUCCESS;
 }
 
+static void
+vk_video_deep_copy_h264_sps(struct vk_video_h264_sps *dst,
+const StdVideoH264SequenceParameterSet *src)
+{
+   memcpy(>base, src, sizeof(StdVideoH264SequenceParameterSet));
+   if (src->num_ref_frames_in_pic_order_cnt_cycle && src->pOffsetForRefFrame) {
+  memcpy(dst->offsets_for_ref_frame, src->pOffsetForRefFrame, 
sizeof(int32_t) * src->num_ref_frames_in_pic_order_cnt_cycle);
+  dst->base.pOffsetForRefFrame = dst->offsets_for_ref_frame;
+   }
+   if (src->flags.seq_scaling_matrix_present_flag && src->pScalingLists) {
+  memcpy(>scaling_lists, src->pScalingLists, 
sizeof(StdVideoH264ScalingLists));
+  dst->base.pScalingLists = >scaling_lists;
+   }
+   if (src->flags.vui_parameters_present_flag && 
src->pSequenceParameterSetVui) {
+  memcpy(>vui, src->pSequenceParameterSetVui, 
sizeof(StdVideoH264SequenceParameterSetVui));
+  dst->base.pSequenceParameterSetVui = >vui;
+
+  if (src->pSequenceParameterSetVui->pHrdParameters) {
+ memcpy(>vui_hrd_parameters, 
src->pSequenceParameterSetVui->pHrdParameters,
+sizeof(StdVideoH264HrdParameters));
+ dst->vui.pHrdParameters = >vui_hrd_parameters;
+  }
+   }
+}
+
+static void
+vk_video_deep_copy_h264_pps(struct vk_video_h264_pps *dst,
+const StdVideoH264PictureParameterSet *src)
+{
+   memcpy(>base, src, sizeof(StdVideoH264PictureParameterSet));
+   if (src->flags.pic_scaling_matrix_present_flag && src->pScalingLists) {
+  memcpy(>scaling_lists, src->pScalingLists, 
sizeof(StdVideoH264ScalingLists));
+  dst->base.pScalingLists = >scaling_lists;
+   }
+}
+
+static void
+vk_video_deep_copy_h265_vps(struct vk_video_h265_vps *dst,
+const StdVideoH265VideoParameterSet *src)
+{
+   memcpy(>base, src, sizeof(StdVideoH265VideoParameterSet));
+   if (src->pDecPicBufMgr) {
+  memcpy(>dec_pic_buf_mgr, src->pDecPicBufMgr, 
sizeof(StdVideoH265DecPicBufMgr));
+  dst->base.pDecPicBufMgr = >dec_pic_buf_mgr;
+   }
+   if (src->pHrdParameters) {
+  memcpy(>hrd_parameters, src->pHrdParameters, 
sizeof(StdVideoH265HrdParameters));
+  dst->base.pHrdParameters = >hrd_parameters;
+  if (src->pHrdParameters->pSubLayerHrdParametersNal) {
+ memcpy(>hrd_parameters_nal, 
src->pHrdParameters->pSubLayerHrdParametersNal,
+sizeof(StdVideoH265SubLayerHrdParameters));
+ dst->hrd_parameters.pSubLayerHrdParametersNal = 
>hrd_parameters_nal;
+  }
+  if (src->pHrdParameters->pSubLayerHrdParametersVcl) {
+ memcpy(>hrd_parameters_vcl, 
src->pHrdParameters->pSubLayerHrdParametersVcl,
+sizeof(StdVideoH265SubLayerHrdParameters));
+ dst->hrd_parameters.pSubLayerHrdParametersVcl = 
>hrd_parameters_vcl;
+  }
+   }
+
+   if (src->pProfileTierLevel) {
+  memcpy(>tier_level, src->pProfileTierLevel, 
sizeof(StdVideoH265ProfileTierLevel));
+  dst->base.pProfileTierLevel = >tier_level;
+   }
+}
+
+static void
+vk_video_deep_copy_h265_sps(struct vk_video_h265_sps *dst,
+const StdVideoH265SequenceParameterSet *src)
+{
+   memcpy(>base, src, sizeof(StdVideoH265SequenceParameterSet));
+   if (src->pProfileTierLevel) {
+  memcpy(>tier_level, src->pProfileTierLevel, 
sizeof(StdVideoH265ProfileTierLevel));
+  dst->base.pProfileTierLevel = >tier_level;
+   }
+   if (src->pDecPicBufMgr) {
+  memcpy(>dec_pic_buf_mgr, src->pDecPicBufMgr, 
sizeof(StdVideoH265DecPicBufMgr));
+  dst->base.pDecPicBufMgr = >dec_pic_buf_mgr;
+   }
+   if (src->flags.sps_scaling_list_data_present_flag && src->pScalingLists) {
+  memcpy(>scaling_lists, src->pScalingLists, 
sizeof(StdVideoH265ScalingLists));
+  dst->base.pScalingLists = >scaling_lists;
+   }
+
+   if (src->pShortTermRefPicSet) {
+  memcpy(>short_term_ref_pic_set, src->pShortTermRefPicSet, 
sizeof(StdVideoH265ShortTermRefPicSet));
+  dst->base.pShortTermRefPicSet = 

Mesa (main): winsys/amdgpu: represent max_ib_size_dw in bytes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6e1dae77a9664e36290954ed81647e58b6cb9834
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1dae77a9664e36290954ed81647e58b6cb9834

Author: Marek Olšák 
Date:   Sun Jan  7 17:06:32 2024 -0500

winsys/amdgpu: represent max_ib_size_dw in bytes

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 15 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  2 +-
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 9218887c502..6cac797e763 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -725,9 +725,9 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
 * INDIRECT_BUFFER packet.
 */
if (cs->has_chaining)
-  buffer_size = 4 * util_next_power_of_two(main_ib->max_ib_size_dw);
+  buffer_size = util_next_power_of_two(main_ib->max_ib_bytes);
else
-  buffer_size = 4 * util_next_power_of_two(4 * main_ib->max_ib_size_dw);
+  buffer_size = util_next_power_of_two(4 * main_ib->max_ib_bytes);
 
const unsigned min_size = MAX2(main_ib->max_check_space_size, 8 * 1024 * 4);
const unsigned max_size = 512 * 1024 * 4;
@@ -792,12 +792,11 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
ib_size = MAX2(ib_size, main_ib->max_check_space_size);
 
if (!cs->has_chaining) {
-  ib_size = MAX2(ib_size,
- MIN2(4 * util_next_power_of_two(main_ib->max_ib_size_dw),
-  IB_MAX_SUBMIT_BYTES));
+  ib_size = MAX2(ib_size, 
MIN2(util_next_power_of_two(main_ib->max_ib_bytes),
+   IB_MAX_SUBMIT_BYTES));
}
 
-   main_ib->max_ib_size_dw = main_ib->max_ib_size_dw - main_ib->max_ib_size_dw 
/ 32;
+   main_ib->max_ib_bytes = main_ib->max_ib_bytes - main_ib->max_ib_bytes / 32;
 
rcs->prev_dw = 0;
rcs->num_prev = 0;
@@ -847,7 +846,7 @@ static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, 
struct radeon_cmdbuf *r
amdgpu_set_ib_size(rcs, ib);
ib->used_ib_space += rcs->current.cdw * 4;
ib->used_ib_space = align(ib->used_ib_space, 
ws->info.ip[ip_type].ib_alignment);
-   ib->max_ib_size_dw = MAX2(ib->max_ib_size_dw, rcs->prev_dw + 
rcs->current.cdw);
+   ib->max_ib_bytes = MAX2(ib->max_ib_bytes, (rcs->prev_dw + rcs->current.cdw) 
* 4);
 }
 
 static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
@@ -1085,7 +1084,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf 
*rcs, unsigned dw)
/* 125% of the size for IB epilog. */
unsigned safe_byte_size = need_byte_size + need_byte_size / 4;
main_ib->max_check_space_size = MAX2(main_ib->max_check_space_size, 
safe_byte_size);
-   main_ib->max_ib_size_dw = MAX2(main_ib->max_ib_size_dw, projected_size_dw);
+   main_ib->max_ib_bytes = MAX2(main_ib->max_ib_bytes, projected_size_dw * 4);
 
if (!cs->has_chaining)
   return false;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 2084a48d6b7..aa192e5ad8b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -59,7 +59,7 @@ struct amdgpu_ib {
 */
unsignedmax_check_space_size;
 
-   unsignedmax_ib_size_dw;
+   unsignedmax_ib_bytes;
/* ptr_ib_size initially points to cs->csc->chunk_ib->ib_bytes.
 * If in amdgpu_cs_check_space() ib chaining is required, then ptr_ib_size 
will point
 * to indirect buffer packet size field.

Mesa (main): winsys/amdgpu: don't clear buffer list elements after IB submission

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a94319d29b466c48ff0e00d6f986e36b99d2ed7b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a94319d29b466c48ff0e00d6f986e36b99d2ed7b

Author: Marek Olšák 
Date:   Sun Jan  7 15:11:26 2024 -0500

winsys/amdgpu: don't clear buffer list elements after IB submission

amdgpu_winsys_bo_reference(dst, NULL) sets *dst to NULL, but we never read
*dst again because we set num_buffers to 0. So don't touch the buffer list
elements and only decrement the BO refcount. It makes a difference when you
have 10k BOs.

The CS thread overhead in VP2020/Catia1: 9.23% -> 8.74%

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/include/winsys/radeon_winsys.h | 16 
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.h  | 14 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c  |  8 
 3 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/src/gallium/include/winsys/radeon_winsys.h 
b/src/gallium/include/winsys/radeon_winsys.h
index 22d10cbe370..02f7ee48d6d 100644
--- a/src/gallium/include/winsys/radeon_winsys.h
+++ b/src/gallium/include/winsys/radeon_winsys.h
@@ -792,6 +792,22 @@ radeon_bo_reference(struct radeon_winsys *rws, struct 
pb_buffer_lean **dst,
*dst = src;
 }
 
+/* Same as radeon_bo_reference, but ignore the value in *dst. */
+static inline void
+radeon_bo_set_reference(struct pb_buffer_lean **dst, struct pb_buffer_lean 
*src)
+{
+   *dst = src;
+   pipe_reference(NULL, >reference); /* only increment refcount */
+}
+
+/* Unreference dst, but don't assign anything. */
+static inline void
+radeon_bo_drop_reference(struct radeon_winsys *rws, struct pb_buffer_lean *dst)
+{
+   if (pipe_reference(>reference, NULL)) /* only decrement refcount */
+  rws->buffer_destroy(rws, dst);
+}
+
 /* The following bits describe the heaps managed by slab allocators (pb_slab) 
and
  * the allocation cache (pb_cache).
  */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 9d2bb04f66e..1fcb233d921 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -265,4 +265,18 @@ amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws, 
struct amdgpu_winsys_bo **d
(struct pb_buffer_lean**)dst, (struct 
pb_buffer_lean*)src);
 }
 
+/* Same as amdgpu_winsys_bo_reference, but ignore the value in *dst. */
+static inline void
+amdgpu_winsys_bo_set_reference(struct amdgpu_winsys_bo **dst, struct 
amdgpu_winsys_bo *src)
+{
+   radeon_bo_set_reference((struct pb_buffer_lean**)dst, (struct 
pb_buffer_lean*)src);
+}
+
+/* Unreference dst, but don't assign anything. */
+static inline void
+amdgpu_winsys_bo_drop_reference(struct amdgpu_winsys *ws, struct 
amdgpu_winsys_bo *dst)
+{
+   radeon_bo_drop_reference(>dummy_ws.base, >base);
+}
+
 #endif
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 3bef8a1ed28..4b52c99894a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -617,7 +617,7 @@ amdgpu_do_add_buffer(struct amdgpu_cs_context *cs, struct 
amdgpu_winsys_bo *bo,
struct amdgpu_cs_buffer *buffer = >buffers[idx];
 
memset(buffer, 0, sizeof(*buffer));
-   amdgpu_winsys_bo_reference(cs->ws, >bo, bo);
+   amdgpu_winsys_bo_set_reference(>bo, bo);
list->num_buffers++;
 
unsigned hash = bo->unique_id & (BUFFER_HASHLIST_SIZE-1);
@@ -882,7 +882,7 @@ static void amdgpu_cs_context_cleanup_buffers(struct 
amdgpu_winsys *ws, struct a
   unsigned num_buffers = cs->buffer_lists[i].num_buffers;
 
   for (unsigned j = 0; j < num_buffers; j++)
- amdgpu_winsys_bo_reference(ws, [j].bo, NULL);
+ amdgpu_winsys_bo_drop_reference(ws, buffers[j].bo);
 
   cs->buffer_lists[i].num_buffers = 0;
}
@@ -1638,10 +1638,10 @@ cleanup:
 
   for (i = 0; i < num_dec_buffers; i++) {
  p_atomic_dec([i].bo->num_active_ioctls);
- amdgpu_winsys_bo_reference(ws, [i].bo, NULL);
+ amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo);
   }
   for (; i < num_buffers; i++)
- amdgpu_winsys_bo_reference(ws, [i].bo, NULL);
+ amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo);
 
   cs->buffer_lists[list].num_buffers = 0;
}

Mesa (main): winsys/amdgpu: cosmetic touchups around IB sizes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 7ed27bff0beacf5d6b965afc0792ead588c11045
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ed27bff0beacf5d6b965afc0792ead588c11045

Author: Marek Olšák 
Date:   Sun Jan  7 17:11:45 2024 -0500

winsys/amdgpu: cosmetic touchups around IB sizes

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 26 ++
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 6cac797e763..e09f5b38cf3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -718,19 +718,18 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
uint8_t *mapped;
unsigned buffer_size;
 
-   /* Always create a buffer that is at least as large as the maximum seen IB
-* size, aligned to a power of two (and multiplied by 4 to reduce internal
-* fragmentation if chaining is not available). Limit to 512k dwords, which
-* is the largest power of two that fits into the size field of the
-* INDIRECT_BUFFER packet.
+   /* Always create a buffer that is at least as large as the maximum seen IB 
size,
+* aligned to a power of two.
 */
-   if (cs->has_chaining)
-  buffer_size = util_next_power_of_two(main_ib->max_ib_bytes);
-   else
-  buffer_size = util_next_power_of_two(4 * main_ib->max_ib_bytes);
+   buffer_size = util_next_power_of_two(main_ib->max_ib_bytes);
 
-   const unsigned min_size = MAX2(main_ib->max_check_space_size, 8 * 1024 * 4);
-   const unsigned max_size = 512 * 1024 * 4;
+   /* Multiply by 4 to reduce internal fragmentation if chaining is not 
available.*/
+   if (!cs->has_chaining)
+  buffer_size *= 4;
+
+   const unsigned min_size = MAX2(main_ib->max_check_space_size, 32 * 1024);
+   /* This is the maximum size that fits into the INDIRECT_BUFFER packet. */
+   const unsigned max_size = 2 * 1024 * 1024;
 
buffer_size = MIN2(buffer_size, max_size);
buffer_size = MAX2(buffer_size, min_size); /* min_size is more important */
@@ -784,7 +783,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
 {
struct drm_amdgpu_cs_chunk_ib *chunk_ib = >csc->chunk_ib[IB_MAIN];
/* This is the minimum size of a contiguous IB. */
-   unsigned ib_size = 4 * 1024 * 4;
+   unsigned ib_size = 16 * 1024;
 
/* Always allocate at least the size of the biggest cs_check_space call,
 * because precisely the last call might have requested this size.
@@ -796,6 +795,9 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
IB_MAX_SUBMIT_BYTES));
}
 
+   /* Decay the IB buffer size over time, so that memory usage decreases after
+* a temporary peak.
+*/
main_ib->max_ib_bytes = main_ib->max_ib_bytes - main_ib->max_ib_bytes / 32;
 
rcs->prev_dw = 0;

Mesa (main): winsys/amdgpu: add more fence_reference helpers

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: fb3171b653bd39a6521928fd8d41df1972e6b43d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb3171b653bd39a6521928fd8d41df1972e6b43d

Author: Marek Olšák 
Date:   Sun Jan  7 16:01:58 2024 -0500

winsys/amdgpu: add more fence_reference helpers

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 11 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 31 +--
 2 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 4b52c99894a..acdad8bca0d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -15,6 +15,17 @@
 
 /* FENCES */
 
+void amdgpu_fence_destroy(struct amdgpu_fence *fence)
+{
+   if (amdgpu_fence_is_syncobj(fence))
+  amdgpu_cs_destroy_syncobj(fence->ws->dev, fence->syncobj);
+   else
+  amdgpu_ctx_reference(>ctx, NULL);
+
+   util_queue_fence_destroy(>submitted);
+   FREE(fence);
+}
+
 static struct pipe_fence_handle *
 amdgpu_fence_create(struct amdgpu_cs *cs)
 {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 2476c2f7fc2..0ad4e62831b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -173,6 +173,8 @@ struct amdgpu_fence {
uint_seq_no queue_seq_no;  /* winsys-generated sequence number */
 };
 
+void amdgpu_fence_destroy(struct amdgpu_fence *fence);
+
 static inline bool amdgpu_fence_is_syncobj(struct amdgpu_fence *fence)
 {
return fence->ctx == NULL;
@@ -197,20 +199,29 @@ static inline void amdgpu_fence_reference(struct 
pipe_fence_handle **dst,
struct amdgpu_fence **adst = (struct amdgpu_fence **)dst;
struct amdgpu_fence *asrc = (struct amdgpu_fence *)src;
 
-   if (pipe_reference(&(*adst)->reference, >reference)) {
-  struct amdgpu_fence *fence = *adst;
-
-  if (amdgpu_fence_is_syncobj(fence))
- amdgpu_cs_destroy_syncobj(fence->ws->dev, fence->syncobj);
-  else
- amdgpu_ctx_reference(>ctx, NULL);
+   if (pipe_reference(&(*adst)->reference, >reference))
+  amdgpu_fence_destroy(*adst);
 
-  util_queue_fence_destroy(>submitted);
-  FREE(fence);
-   }
*adst = asrc;
 }
 
+/* Same as amdgpu_fence_reference, but ignore the value in *dst. */
+static inline void amdgpu_fence_set_reference(struct pipe_fence_handle **dst,
+  struct pipe_fence_handle *src)
+{
+   *dst = src;
+   pipe_reference(NULL, &((struct amdgpu_fence *)src)->reference); /* only 
increment refcount */
+}
+
+/* Unreference dst, but don't assign anything. */
+static inline void amdgpu_fence_drop_reference(struct pipe_fence_handle *dst)
+{
+   struct amdgpu_fence *adst = (struct amdgpu_fence *)dst;
+
+   if (pipe_reference(>reference, NULL)) /* only decrement refcount */
+  amdgpu_fence_destroy(adst);
+}
+
 struct amdgpu_cs_buffer *
 amdgpu_lookup_buffer_any_type(struct amdgpu_cs_context *cs, struct 
amdgpu_winsys_bo *bo);
 

Mesa (main): winsys/amdgpu: merge loops decrementing num_active_ioctls & unreferencing bufs

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 1e06cdad0d6ee04ef3fa1d955f569281deaddb15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e06cdad0d6ee04ef3fa1d955f569281deaddb15

Author: Marek Olšák 
Date:   Sun Jan  7 14:44:48 2024 -0500

winsys/amdgpu: merge loops decrementing num_active_ioctls & unreferencing bufs

We have 2 separate loops doing that. num_active_ioctls was decremented
in amdgpu_cs_submit_ib, while buffers were unreferenced
in amdgpu_cs_context_cleanup immediately after it.

Split unreferencing buffers from amdgpu_cs_context_cleanup, so that it's
not done in amdgpu_cs_submit_ib, which will do it in the same loop where
num_active_ioctls is unreferenced.

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 34 +--
 1 file changed, 23 insertions(+), 11 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 0831874296c..8c6e4b91e4c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -875,7 +875,7 @@ static void cleanup_fence_list(struct amdgpu_fence_list 
*fences)
fences->num = 0;
 }
 
-static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct 
amdgpu_cs_context *cs)
+static void amdgpu_cs_context_cleanup_buffers(struct amdgpu_winsys *ws, struct 
amdgpu_cs_context *cs)
 {
for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++) {
   struct amdgpu_cs_buffer *buffers = cs->buffer_lists[i].buffers;
@@ -886,7 +886,10 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_winsys 
*ws, struct amdgpu_cs
 
   cs->buffer_lists[i].num_buffers = 0;
}
+}
 
+static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct 
amdgpu_cs_context *cs)
+{
cs->seq_no_dependencies.valid_fence_mask = 0;
cleanup_fence_list(>fence_dependencies);
cleanup_fence_list(>syncobj_dependencies);
@@ -897,6 +900,7 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_winsys 
*ws, struct amdgpu_cs
 
 static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct 
amdgpu_cs_context *cs)
 {
+   amdgpu_cs_context_cleanup_buffers(ws, cs);
amdgpu_cs_context_cleanup(ws, cs);
for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++)
   FREE(cs->buffer_lists[i].buffers);
@@ -1621,17 +1625,23 @@ cleanup:
 
cs->error_code = r;
 
-   /* Only decrement num_active_ioctls for those buffers where we incremented 
it. */
-   for (i = 0; i < initial_num_real_buffers; i++)
-  
p_atomic_dec(>buffer_lists[AMDGPU_BO_REAL].buffers[i].bo->num_active_ioctls);
-
-   unsigned num_slab_buffers = 
cs->buffer_lists[AMDGPU_BO_SLAB_ENTRY].num_buffers;
-   for (i = 0; i < num_slab_buffers; i++)
-  
p_atomic_dec(>buffer_lists[AMDGPU_BO_SLAB_ENTRY].buffers[i].bo->num_active_ioctls);
+   /* Clear the buffer lists. */
+   for (unsigned list = 0; list < ARRAY_SIZE(cs->buffer_lists); list++) {
+  struct amdgpu_cs_buffer *buffers = cs->buffer_lists[list].buffers;
+  unsigned num_buffers = cs->buffer_lists[list].num_buffers;
+  /* Only decrement num_active_ioctls for those buffers where we 
incremented it. */
+  unsigned num_dec_buffers = list == AMDGPU_BO_REAL ? 
initial_num_real_buffers : num_buffers;
+  unsigned i;
+
+  for (i = 0; i < num_dec_buffers; i++) {
+ p_atomic_dec([i].bo->num_active_ioctls);
+ amdgpu_winsys_bo_reference(ws, [i].bo, NULL);
+  }
+  for (; i < num_buffers; i++)
+ amdgpu_winsys_bo_reference(ws, [i].bo, NULL);
 
-   unsigned num_sparse_buffers = 
cs->buffer_lists[AMDGPU_BO_SPARSE].num_buffers;
-   for (i = 0; i < num_sparse_buffers; i++)
-  
p_atomic_dec(>buffer_lists[AMDGPU_BO_SPARSE].buffers[i].bo->num_active_ioctls);
+  cs->buffer_lists[list].num_buffers = 0;
+   }
 
amdgpu_cs_context_cleanup(ws, cs);
 }
@@ -1749,6 +1759,8 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
} else {
   if (flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION)
  cs->csc->secure = !cs->csc->secure;
+
+  amdgpu_cs_context_cleanup_buffers(ws, cs->csc);
   amdgpu_cs_context_cleanup(ws, cs->csc);
}
 

Mesa (main): winsys/amdgpu: remove misplaced duplicated comment

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a008a7dcdf18acb7d74d63c53ca89fc84e3620e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a008a7dcdf18acb7d74d63c53ca89fc84e3620e2

Author: Marek Olšák 
Date:   Sun Jan  7 16:58:17 2024 -0500

winsys/amdgpu: remove misplaced duplicated comment

The same comment is in the header file where it should be.

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index c67322b4681..7243ff75dc9 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -782,10 +782,6 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
   struct amdgpu_ib *main_ib,
   struct amdgpu_cs *cs)
 {
-   /* Small IBs are better than big IBs, because the GPU goes idle quicker
-* and there is less waiting for buffers and fences. Proof:
-*   http://www.phoronix.com/scan.php?page=article=mesa-111-si=1
-*/
struct drm_amdgpu_cs_chunk_ib *chunk_ib = >csc->chunk_ib[IB_MAIN];
/* This is the minimum size of a contiguous IB. */
unsigned ib_size = 4 * 1024 * 4;

Mesa (main): winsys/amdgpu: represent IB_MAX_SUBMIT_DWORDS in bytes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: fd1e36a044bb2a23356df025fff16f015ad34130
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd1e36a044bb2a23356df025fff16f015ad34130

Author: Marek Olšák 
Date:   Sun Jan  7 17:00:35 2024 -0500

winsys/amdgpu: represent IB_MAX_SUBMIT_DWORDS in bytes

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 +++---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 7243ff75dc9..9218887c502 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -793,8 +793,8 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
 
if (!cs->has_chaining) {
   ib_size = MAX2(ib_size,
- 4 * MIN2(util_next_power_of_two(main_ib->max_ib_size_dw),
-  IB_MAX_SUBMIT_DWORDS));
+ MIN2(4 * util_next_power_of_two(main_ib->max_ib_size_dw),
+  IB_MAX_SUBMIT_BYTES));
}
 
main_ib->max_ib_size_dw = main_ib->max_ib_size_dw - main_ib->max_ib_size_dw 
/ 32;
@@ -1074,7 +1074,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf 
*rcs, unsigned dw)
 
unsigned projected_size_dw = rcs->prev_dw + rcs->current.cdw + dw;
 
-   if (projected_size_dw > IB_MAX_SUBMIT_DWORDS)
+   if (projected_size_dw * 4 > IB_MAX_SUBMIT_BYTES)
   return false;
 
if (rcs->current.max_dw - rcs->current.cdw >= dw)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 0ad4e62831b..2084a48d6b7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -16,7 +16,7 @@
  * waiting for buffers and fences. Proof:
  *   http://www.phoronix.com/scan.php?page=article=mesa-111-si=1
  */
-#define IB_MAX_SUBMIT_DWORDS (20 * 1024)
+#define IB_MAX_SUBMIT_BYTES (80 * 1024)
 
 struct amdgpu_ctx {
struct pipe_reference reference;

Mesa (main): winsys/amdgpu: cosmetic touchups

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2da16e963593a91381766a84573ae76e1849920e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2da16e963593a91381766a84573ae76e1849920e

Author: Marek Olšák 
Date:   Sun Jan  7 14:58:40 2024 -0500

winsys/amdgpu: cosmetic touchups

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 11 +--
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 13 -
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 4da7b20fa72..9d2bb04f66e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -251,16 +251,15 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned 
heap, unsigned entry_s
 void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab);
 uint64_t amdgpu_bo_get_va(struct pb_buffer_lean *buf);
 
-static inline
-struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer_lean *bo)
+static inline struct amdgpu_winsys_bo *
+amdgpu_winsys_bo(struct pb_buffer_lean *bo)
 {
return (struct amdgpu_winsys_bo *)bo;
 }
 
-static inline
-void amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws,
-struct amdgpu_winsys_bo **dst,
-struct amdgpu_winsys_bo *src)
+static inline void
+amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo 
**dst,
+   struct amdgpu_winsys_bo *src)
 {
radeon_bo_reference(>dummy_ws.base,
(struct pb_buffer_lean**)dst, (struct 
pb_buffer_lean*)src);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 8c6e4b91e4c..3bef8a1ed28 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1205,10 +1205,11 @@ static void amdgpu_add_bo_fences_to_dependencies(struct 
amdgpu_cs *acs,
 {
struct amdgpu_winsys *ws = acs->ws;
unsigned queue_index = acs->queue_index;
+   struct amdgpu_cs_buffer *buffers = list->buffers;
unsigned num_buffers = list->num_buffers;
 
for (unsigned i = 0; i < num_buffers; i++) {
-  struct amdgpu_cs_buffer *buffer = >buffers[i];
+  struct amdgpu_cs_buffer *buffer = [i];
   struct amdgpu_winsys_bo *bo = buffer->bo;
 
   /* Add BO fences from queues other than 'queue_index' to dependencies. */
@@ -1243,10 +1244,11 @@ static void amdgpu_cs_add_syncobj_signal(struct 
radeon_cmdbuf *rws,
  */
 static bool amdgpu_add_sparse_backing_buffers(struct amdgpu_cs_context *cs)
 {
+   struct amdgpu_cs_buffer *buffers = 
cs->buffer_lists[AMDGPU_BO_SPARSE].buffers;
unsigned num_sparse_buffers = 
cs->buffer_lists[AMDGPU_BO_SPARSE].num_buffers;
 
for (unsigned i = 0; i < num_sparse_buffers; ++i) {
-  struct amdgpu_cs_buffer *buffer = 
>buffer_lists[AMDGPU_BO_SPARSE].buffers[i];
+  struct amdgpu_cs_buffer *buffer = [i];
   struct amdgpu_bo_sparse *bo = get_sparse_bo(buffer->bo);
 
   simple_mtx_lock(>commit_lock);
@@ -1277,7 +1279,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, 
int thread_index)
struct amdgpu_cs *acs = (struct amdgpu_cs*)job;
struct amdgpu_winsys *ws = acs->ws;
struct amdgpu_cs_context *cs = acs->cst;
-   int i, r;
+   int r;
uint64_t seq_no = 0;
bool has_user_fence = amdgpu_cs_has_user_fence(acs);
 
@@ -1423,11 +1425,12 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, 
int thread_index)
  goto cleanup;
   }
 
+  struct amdgpu_cs_buffer *real_buffers = 
cs->buffer_lists[AMDGPU_BO_REAL].buffers;
   unsigned num_real_buffers = cs->buffer_lists[AMDGPU_BO_REAL].num_buffers;
   bo_list = alloca((num_real_buffers + 2) * sizeof(struct 
drm_amdgpu_bo_list_entry));
 
-  for (i = 0; i < num_real_buffers; ++i) {
- struct amdgpu_cs_buffer *buffer = 
>buffer_lists[AMDGPU_BO_REAL].buffers[i];
+  for (unsigned i = 0; i < num_real_buffers; ++i) {
+ struct amdgpu_cs_buffer *buffer = _buffers[i];
 
  bo_list[num_bo_handles].bo_handle = 
get_real_bo(buffer->bo)->kms_handle;
  bo_list[num_bo_handles].bo_priority =

Mesa (main): winsys/amdgpu: don't clear fence list elements after IB submission

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b2b7603ecbf35b5c805d5bf5bcc51f85bc5ca8e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2b7603ecbf35b5c805d5bf5bcc51f85bc5ca8e2

Author: Marek Olšák 
Date:   Sun Jan  7 16:07:35 2024 -0500

winsys/amdgpu: don't clear fence list elements after IB submission

Same idea as with the buffer lists.

Reviewed-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index acdad8bca0d..c67322b4681 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -882,7 +882,7 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
 static void cleanup_fence_list(struct amdgpu_fence_list *fences)
 {
for (unsigned i = 0; i < fences->num; i++)
-  amdgpu_fence_reference(>list[i], NULL);
+  amdgpu_fence_drop_reference(fences->list[i]);
fences->num = 0;
 }
 
@@ -1181,11 +1181,8 @@ static void add_fence_to_list(struct amdgpu_fence_list 
*fences,
   fences->max = idx + increment;
   size = fences->max * sizeof(fences->list[0]);
   fences->list = realloc(fences->list, size);
-  /* Clear the newly-allocated elements. */
-  memset(fences->list + idx, 0,
- increment * sizeof(fences->list[0]));
}
-   amdgpu_fence_reference(>list[idx], (struct 
pipe_fence_handle*)fence);
+   amdgpu_fence_set_reference(>list[idx], (struct 
pipe_fence_handle*)fence);
 }
 
 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rcs,

Mesa (staging/23.3): util: Add DETECT_ARCH_HPPA macro

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: c24841d1e2543d7a7f6e6c645aef1c999c14d382
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24841d1e2543d7a7f6e6c645aef1c999c14d382

Author: Matt Turner 
Date:   Wed Jan 10 17:31:08 2024 -0500

util: Add DETECT_ARCH_HPPA macro

Cc: mesa-stable
Part-of: 
(cherry picked from commit 0540c9de447730e5efe73a0c5a1a5b6c1e902722)

---

 .pick_status.json  | 2 +-
 src/util/detect_arch.h | 8 
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 398794940f2..9fc93a99059 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -514,7 +514,7 @@
 "description": "util: Add DETECT_ARCH_HPPA macro",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 1,
 "main_sha": null,
 "because_sha": null,
 "notes": null
diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
index 334358fcc26..b3f7f90ac96 100644
--- a/src/util/detect_arch.h
+++ b/src/util/detect_arch.h
@@ -97,6 +97,10 @@
 #define DETECT_ARCH_MIPS 1
 #endif
 
+#if defined(__hppa__)
+#define DETECT_ARCH_HPPA 1
+#endif
+
 #ifndef DETECT_ARCH_X86
 #define DETECT_ARCH_X86 0
 #endif
@@ -137,4 +141,8 @@
 #define DETECT_ARCH_MIPS 0
 #endif
 
+#ifndef DETECT_ARCH_HPPA
+#define DETECT_ARCH_HPPA 0
+#endif
+
 #endif /* UTIL_DETECT_ARCH_H_ */

Mesa (staging/23.3): anv: hide vendor ID for The Finals

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 5d7b3812b2b9af04736430a4204f0e9890ab629a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d7b3812b2b9af04736430a4204f0e9890ab629a

Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:51:05 2024 +0200

anv: hide vendor ID for The Finals

XeSS workaround.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10436
Cc: mesa-stable
Part-of: 
(cherry picked from commit a34a113059f55947cc08624897999f7f066f000a)

---

 .pick_status.json  | 2 +-
 src/util/00-mesa-defaults.conf | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 0a4a9542e2d..394f2da964f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -54,7 +54,7 @@
 "description": "anv: hide vendor ID for The Finals",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 1,
 "main_sha": null,
 "because_sha": null,
 "notes": null
diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 9e9fbb89913..54d0569da93 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -1169,6 +1169,9 @@ TODO: document the other workarounds.
 
 
 
+
+
+
 

Mesa (staging/23.3): util/tests: Disable half-float NaN test on hppa/old-mips

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 685cc5f6f2dac0b4fda7d209252dd7d1a2ab34b2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=685cc5f6f2dac0b4fda7d209252dd7d1a2ab34b2

Author: Matt Turner 
Date:   Wed Jan 10 17:32:06 2024 -0500

util/tests: Disable half-float NaN test on hppa/old-mips

Bug: https://bugs.gentoo.org/908079
Fixes: 067023dce2c ("util: Add some unit tests of the half-float conversions.")
Part-of: 
(cherry picked from commit 5b7c73390247caa847c56c442298107a1e568a6d)

---

 .pick_status.json  |  2 +-
 src/util/tests/half_float_test.cpp | 39 +++---
 2 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 9fc93a99059..49e74ac2ae7 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -504,7 +504,7 @@
 "description": "util/tests: Disable half-float NaN test on 
hppa/old-mips",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "main_sha": null,
 "because_sha": "067023dce2cae5ef44d2b8cd52a81aa880256037",
 "notes": null
diff --git a/src/util/tests/half_float_test.cpp 
b/src/util/tests/half_float_test.cpp
index 051e0d0376a..5b11f60576d 100644
--- a/src/util/tests/half_float_test.cpp
+++ b/src/util/tests/half_float_test.cpp
@@ -46,18 +46,35 @@ static bool issignaling(float x)
 }
 #endif
 
-/* Sanity test our test values */
-TEST(half_to_float_test, nan_test)
+/* The sign of the bit for signaling is different on some old processors
+ * (PA-RISC, old MIPS without IEEE-754-2008 support).
+ *
+ * Disable the tests on those platforms, because it's not clear how to
+ * correctly handle NaNs when the CPU and GPU differ in their convention.
+ */
+#if DETECT_ARCH_HPPA || ((DETECT_ARCH_MIPS || DETECT_ARCH_MIPS64) && !defined 
__mips_nan2008)
+#define IEEE754_2008_NAN 0
+#else
+#define IEEE754_2008_NAN 1
+#endif
+
+/* Sanity test our inf test values */
+TEST(half_to_float_test, inf_test)
 {
EXPECT_TRUE(isinf(TEST_POS_INF));
EXPECT_TRUE(isinf(TEST_NEG_INF));
+}
 
+/* Make sure that our 32-bit float nan test value we're using is a
+ * non-signaling NaN.
+ */
+#if IEEE754_2008_NAN
+TEST(half_to_float_test, nan_test)
+#else
+TEST(half_to_float_test, DISABLED_nan_test)
+#endif
+{
EXPECT_TRUE(isnan(TEST_NAN));
-   /* Make sure that our 32-bit float nan test value we're using is a
-* non-signaling NaN.  The sign of the bit for signaling was apparently
-* different on some old processors (PA-RISC, MIPS?).  This test value 
should
-* cover Intel, ARM, and PPC, for sure.
-*/
EXPECT_FALSE(issignaling(TEST_NAN));
 }
 
@@ -82,12 +99,20 @@ test_half_to_float_limits(float (*func)(uint16_t))
 }
 
 /* Test the optionally HW instruction-using path. */
+#if IEEE754_2008_NAN
 TEST(half_to_float_test, half_to_float_test)
+#else
+TEST(half_to_float_test, DISABLED_half_to_float_test)
+#endif
 {
test_half_to_float_limits(_mesa_half_to_float);
 }
 
+#if IEEE754_2008_NAN
 TEST(half_to_float_test, half_to_float_slow_test)
+#else
+TEST(half_to_float_test, DISABLED_half_to_float_slow_test)
+#endif
 {
test_half_to_float_limits(_mesa_half_to_float_slow);
 }

Mesa (staging/23.3): anv: check for wa 16013994831 in emit_so_memcpy_end

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 2f0a118afee441f2f1d7ec7b6a655f0adc77b208
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f0a118afee441f2f1d7ec7b6a655f0adc77b208

Author: Tapani Pälli 
Date:   Thu Jan 11 15:50:09 2024 +0200

anv: check for wa 16013994831 in emit_so_memcpy_end

We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli 
Reviewed-by: Lionel Landwerlin 
Part-of: 
(cherry picked from commit 36f428f1de78d6bd2c0aa6719da06cd5233a8c7f)

---

 .pick_status.json  | 2 +-
 src/intel/vulkan/genX_gpu_memcpy.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 394f2da964f..2d482414016 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -24,7 +24,7 @@
 "description": "anv: check for wa 16013994831 in emit_so_memcpy_end",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 1,
 "main_sha": null,
 "because_sha": null,
 "notes": null
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c 
b/src/intel/vulkan/genX_gpu_memcpy.c
index 112f94fd2c0..2c561473c30 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -272,7 +272,7 @@ genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
 void
 genX(emit_so_memcpy_end)(struct anv_memcpy_state *state)
 {
-   if (intel_device_info_is_dg2(state->device->info))
+   if (intel_needs_workaround(state->device->info, 16013994831))
   genX(batch_set_preemption)(state->batch, state->device->info, true);
 
anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);

Mesa (staging/23.3): .pick_status.json: Update to 4fe5f06d400a7310ffc280761c27b036aec86646

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 0c942965e22d8d55ffc159890f9c6278299400fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c942965e22d8d55ffc159890f9c6278299400fa

Author: Eric Engestrom 
Date:   Mon Jan 15 09:43:40 2024 +

.pick_status.json: Update to 4fe5f06d400a7310ffc280761c27b036aec86646

---

 .pick_status.json | 520 ++
 1 file changed, 520 insertions(+)

diff --git a/.pick_status.json b/.pick_status.json
index feba6c3d211..398794940f2 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1,4 +1,524 @@
 [
+{
+"sha": "4fe5f06d400a7310ffc280761c27b036aec86646",
+"description": "radv/rt: re-use radv_ray_tracing_stage::sha1 for 
hashing RT pipelines",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "bb86fc03596a1aca0862a10eb251c1c71ed81d10",
+"description": "radv: constify stages in radv_rt_fill_group_info()",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "36f428f1de78d6bd2c0aa6719da06cd5233a8c7f",
+"description": "anv: check for wa 16013994831 in emit_so_memcpy_end",
+"nominated": true,
+"nomination_type": 0,
+"resolution": 0,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "73835874a82f741e10cbc8da9128a4f5cd46e347",
+"description": "intel/disasm: Remove duplicate variable reg_file",
+"nominated": false,
+"nomination_type": 1,
+"resolution": 4,
+"main_sha": null,
+"because_sha": "1c92dad5cb7f5d46dfaf56d2f9ce0203c2fbefbe",
+"notes": null
+},
+{
+"sha": "e84aa455e550bb151cccbc8668c5dd64719342e9",
+"description": "iris: Use Mesa internal drm-uapi headers",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "a34a113059f55947cc08624897999f7f066f000a",
+"description": "anv: hide vendor ID for The Finals",
+"nominated": true,
+"nomination_type": 0,
+"resolution": 0,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "ff6041afdf2df9f048aa192f602c191e96ce92fd",
+"description": "intel/aux_map: fix fallback unmapping range on 
failure",
+"nominated": false,
+"nomination_type": 1,
+"resolution": 4,
+"main_sha": null,
+"because_sha": "7c6faa1efe8f50263bfc1f71cb1c4a1c2302b5df",
+"notes": null
+},
+{
+"sha": "33b77ec774a10f052a2814d9ff3668cc0aa13083",
+"description": "cso: don't unbind vertex buffers when 
enabling/disabling u_vbuf",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "eb20ef92772c6a4963128370260d578f100efee9",
+"description": "gallium: remove unbind_trailing_count from 
set_vertex_buffers",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "2725b095ea2a16a1ce28aca8ae31e9d3df448c67",
+"description": "gallium/u_vbuf: replace unnecessary dst_index with 
\"i\"",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "cfba24ccb548af0ad3427b525def602383cd204a",
+"description": "nvk: Add a couple more features to features.txt",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "27a1b4e4f314832c164380ea332c096fe394c8f0",
+"description": "ci/deqp: ensure that in `default` builds, wayland + 
x11 + xcb are all built",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "3c7460c0238a4c7823aea22d9fbfb795ea738fc4",
+"description": "nvk: Advertise variableMultisampleRate and 
EDS3RasterizationSamples",
+"nominated": false,
+"nomination_type": 3,
+"resolution": 4,
+"main_sha": null,
+"because_sha": null,
+"notes": null
+},
+{
+"sha": "0e33dba6256f0da5882a55081616004d3f5dc1e2",
+"description": "nvk: Move 

Mesa (staging/23.3): mesa: Consider mesa format in addition to internal format for mip/cube completeness

[GitLab Mirror]

Module: Mesa
Branch: staging/23.3
Commit: 4c37d02fe238a3b1ff1257417315dbb963696616
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c37d02fe238a3b1ff1257417315dbb963696616

Author: Jesse Natalie 
Date:   Thu Jan 11 15:46:07 2024 -0800

mesa: Consider mesa format in addition to internal format for mip/cube 
completeness

Prior to 06b526de, the mesa format was used for these completeness checks.
That was to address the case where a *different* internal format selected
the *same* mesa format, and the texture shouldn't be considered compatible.
But this didn't address the case where the *same* internal format selected
a *different* mesa format, e.g. because the type passed to the TexImage
API was different.

An old WGL demo app called TexFilter.exe tries to redefine a mipped RGBA16
texture as RGBA8. This incorrect logic caused Mesa to try to copy the RGBA16
data from the smaller mips into the newly created RGBA8 data, because it
thought that the texture was still mip-complete, despite the format changing.

Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz 
Part-of: 
(cherry picked from commit 4cb9c77e8e08507b5c181a480259e42b43dd647e)

---

 .pick_status.json  | 2 +-
 src/mesa/main/texobj.c | 6 --
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 49e74ac2ae7..0a4a9542e2d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -284,7 +284,7 @@
 "description": "mesa: Consider mesa format in addition to internal 
format for mip/cube completeness",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 1,
 "main_sha": null,
 "because_sha": null,
 "notes": null
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 20e14ee21ee..5c960c730bf 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -817,7 +817,8 @@ _mesa_test_texobj_completeness( const struct gl_context 
*ctx,
 return;
  }
  if (t->Image[face][baseLevel]->InternalFormat !=
- baseImage->InternalFormat) {
+ baseImage->InternalFormat ||
+ t->Image[face][baseLevel]->TexFormat != baseImage->TexFormat) {
 incomplete(t, BASE, "Cube face format mismatch");
 return;
  }
@@ -876,7 +877,8 @@ _mesa_test_texobj_completeness( const struct gl_context 
*ctx,
   incomplete(t, MIPMAP, "TexImage[%d] is missing", i);
   return;
}
-   if (img->InternalFormat != baseImage->InternalFormat) {
+   if (img->InternalFormat != baseImage->InternalFormat ||
+   img->TexFormat != baseImage->TexFormat) {
   incomplete(t, MIPMAP, "Format[i] != Format[baseLevel]");
   return;
}

Mesa (staging/24.0): 22 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc4180339ca3238ba4eb2cb62466af085c1fee23
Author: Tapani Pälli 
Date:   Thu Jan 11 15:50:09 2024 +0200

anv: check for wa 16013994831 in emit_so_memcpy_end

We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli 
Reviewed-by: Lionel Landwerlin 
Part-of: 
(cherry picked from commit 36f428f1de78d6bd2c0aa6719da06cd5233a8c7f)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b39ee4d7669c93fcb52ec570faaca2a4736ec886
Author: Vinson Lee 
Date:   Sat Jan 13 21:06:38 2024 -0800

intel/disasm: Remove duplicate variable reg_file

Fix defects reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = 
brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.

Fixes: 1c92dad5cb7 ("intel/disasm: Disassembly support for DPAS")
Signed-off-by: Vinson Lee 
Reviewed-by: Lionel Landwerlin 
Part-of: 
(cherry picked from commit 73835874a82f741e10cbc8da9128a4f5cd46e347)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b8984f32f9fb4e45e167fdd0147e28e6b4c8759
Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:51:05 2024 +0200

anv: hide vendor ID for The Finals

XeSS workaround.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10436
Cc: mesa-stable
Part-of: 
(cherry picked from commit a34a113059f55947cc08624897999f7f066f000a)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb3d73073ffb76a14af5746baecca51d6fd5763c
Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:49:57 2024 +0200

intel/aux_map: fix fallback unmapping range on failure

Signed-off-by: Lionel Landwerlin 
Fixes: 7c6faa1efe ("intel/aux_map: introduce ref count of L1 entries")
Reviewed-by: Tapani Pälli 
Part-of: 
(cherry picked from commit ff6041afdf2df9f048aa192f602c191e96ce92fd)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f19b7d8dfc49b9923aa235ada4c43ff11b5bc9ef
Author: Jesse Natalie 
Date:   Thu Jan 11 15:46:07 2024 -0800

mesa: Consider mesa format in addition to internal format for mip/cube 
completeness

Prior to 06b526de, the mesa format was used for these completeness checks.
That was to address the case where a *different* internal format selected
the *same* mesa format, and the texture shouldn't be considered compatible.
But this didn't address the case where the *same* internal format selected
a *different* mesa format, e.g. because the type passed to the TexImage
API was different.

An old WGL demo app called TexFilter.exe tries to redefine a mipped RGBA16
texture as RGBA8. This incorrect logic caused Mesa to try to copy the RGBA16
data from the smaller mips into the newly created RGBA8 data, because it
thought that the texture was still mip-complete, despite the format 
changing.

Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz 
Part-of: 
(cherry picked from commit 4cb9c77e8e08507b5c181a480259e42b43dd647e)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04ffe4771e598e8216106696c04694082e7e86ad
Author: José Roberto de Souza 
Date:   Fri Jan 12 08:31:31 2024 -0800

anv: Fix PAT entry for userptr in integrated GPUs

Fixes: 060439bdf0e7 ("anv: Add ANV_BO_ALLOC_IMPORTED")
Signed-off-by: José Roberto de Souza 
Reviewed-by: Lionel Landwerlin 
Part-of: 
(cherry picked from commit 49fe060b5f39eb673b0c6a8757730386c6ce5570)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ebdd39d85295f7c2da70f3ec915f9b854c9f2be
Author: Yiwei Zhang 
Date:   Thu Jan 11 20:47:10 2024 -0800

venus: populate oom from ring submit alloc failures

ring_seqno_valid indicates a successful ring cmd submission, and can be
used to avoid invalid reply decoding due to failed submit alloc.
Otherwise, the garbled VkResult will mislead into initialization failure
instead of oom.

Below cts failure is fixed:
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic

Fixes: ec131c6e553 ("venus: use instance allocator for ring allocs")
Signed-off-by: Yiwei Zhang 
Part-of: 
(cherry picked from commit ecd50e70d4d23802c4c102ca2e5723ebf4a19c0c)

URL:

Mesa (main): nak: Stop passing --explicit-padding to bindgen

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f1cf7f0d869c6daf2104d1cb975cc21b7a3e5433
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1cf7f0d869c6daf2104d1cb975cc21b7a3e5433

Author: Faith Ekstrand 
Date:   Mon Jan 15 12:37:52 2024 -0600

nak: Stop passing --explicit-padding to bindgen

It's apparently broken on 32-bit builds and screws up our NIR bindings.
Instead, using -Wpadded with a pragma to ensure we don't add padding to
the struct.

Part-of: 

---

 src/nouveau/compiler/meson.build |  2 --
 src/nouveau/compiler/nak.h   |  8 
 src/nouveau/compiler/nak/api.rs  | 21 -
 3 files changed, 4 insertions(+), 27 deletions(-)

diff --git a/src/nouveau/compiler/meson.build b/src/nouveau/compiler/meson.build
index f8a55046edb..535294ecf1f 100644
--- a/src/nouveau/compiler/meson.build
+++ b/src/nouveau/compiler/meson.build
@@ -78,13 +78,11 @@ nak_bindings_rs = rust.bindgen(
 '--allowlist-type', 'mesa_scope',
 '--allowlist-type', 'mesa_prim',
 '--allowlist-type', 'tess_primitive_mode',
-'--allowlist-var', 'NAK_.*',
 '--allowlist-var', 'nir_.*_infos',
 '--allowlist-function', '_mesa_shader_stage_to_string',
 '--allowlist-function', 'nak_.*',
 '--allowlist-function', 'nir_.*',
 '--allowlist-function', 'glsl_.*',
-'--explicit-padding',
 '--no-prepend-enum-name',
   ],
   dependencies : libnak_deps,
diff --git a/src/nouveau/compiler/nak.h b/src/nouveau/compiler/nak.h
index cfec9e4f738..db768e14e6c 100644
--- a/src/nouveau/compiler/nak.h
+++ b/src/nouveau/compiler/nak.h
@@ -79,9 +79,6 @@ struct nak_xfb_info {
uint8_t attr_index[4][128];
 };
 
-/* This is an enum so bindgen will generate it */
-#define NAK_SHADER_INFO_STAGE_UNION_SIZE 12
-
 /* This struct MUST have explicit padding fields to ensure that all padding is
  * zeroed and the zeros get properly copied, even across API boundaries.  This
  * is ensured in two ways:
@@ -93,6 +90,8 @@ struct nak_xfb_info {
  *  - There is a set of const asserts in nak/api.rs which ensure that all of
  *the union fields are equal to NAK_SHADER_INFO_STAGE_UNION_SIZE.
  */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic error "-Wpadded"
 struct nak_shader_info {
gl_shader_stage stage;
 
@@ -137,7 +136,7 @@ struct nak_shader_info {
   } ts;
 
   /* Used to initialize the union for other stages */
-  uint8_t _pad[NAK_SHADER_INFO_STAGE_UNION_SIZE];
+  uint8_t _pad[12];
};
 
struct {
@@ -153,6 +152,7 @@ struct nak_shader_info {
/** Shader header for 3D stages */
uint32_t hdr[32];
 };
+#pragma GCC diagnostic pop
 
 struct nak_shader_bin {
struct nak_shader_info info;
diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs
index 35fad6f2aa2..3ad0aaab8cf 100644
--- a/src/nouveau/compiler/nak/api.rs
+++ b/src/nouveau/compiler/nak/api.rs
@@ -154,7 +154,6 @@ pub extern "C" fn nak_compiler_create(
 let nak = Box::new(nak_compiler {
 sm: dev.sm,
 nir_options: nir_options(dev),
-..unsafe { std::mem::zeroed() }
 });
 
 Box::into_raw(nak)
@@ -199,7 +198,6 @@ impl ShaderBin {
 } else {
 asm.as_ptr()
 },
-..unsafe { std::mem::zeroed() }
 };
 ShaderBin {
 bin: bin,
@@ -228,25 +226,6 @@ fn eprint_hex(label: , data: &[u32]) {
 eprintln!("");
 }
 
-const _: () = {
-assert!(
-std::mem::size_of::()
-== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
-);
-assert!(
-std::mem::size_of::()
-== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
-);
-assert!(
-std::mem::size_of::()
-== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
-);
-assert!(
-std::mem::size_of::()
-== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
-);
-};
-
 #[no_mangle]
 pub extern "C" fn nak_compile_shader(
 nir: *mut nir_shader,

Mesa (main): util/format/fxt1: include "u_format_pack.h" instead of "util/format/u_format_pack.h"

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f079b6a18d87bb2a99ebb4365ef426b39019efed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f079b6a18d87bb2a99ebb4365ef426b39019efed

Author: chyyran 
Date:   Sat Dec  9 02:39:58 2023 -0500

util/format/fxt1: include "u_format_pack.h" instead of 
"util/format/u_format_pack.h"

Signed-off-by: Ronny Chan 
Reviewed-by: Yonggang Luo 
Reviewed-by: Jesse Natalie 
Part-of: 

---

 src/util/format/u_format_fxt1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/util/format/u_format_fxt1.c b/src/util/format/u_format_fxt1.c
index 7aaee79e274..d4512ebb74f 100644
--- a/src/util/format/u_format_fxt1.c
+++ b/src/util/format/u_format_fxt1.c
@@ -23,9 +23,9 @@
  *
  **/
 
+#include "u_format_pack.h"
 #include "util/format/u_format.h"
 #include "util/format/u_format_fxt1.h"
-#include "util/format/u_format_pack.h"
 #include "util/format_srgb.h"
 #include "util/u_math.h"
 

Mesa (main): ir3: Add fullsync and fullnop ir3 dbg options for over-syncing

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 43bc212aeb8b5905ddd69d1a39ac7b5e2d175426
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43bc212aeb8b5905ddd69d1a39ac7b5e2d175426

Author: Danylo Piliaiev 
Date:   Thu Jan 11 17:46:04 2024 +0100

ir3: Add fullsync and fullnop ir3 dbg options for over-syncing

- fullsync - adds (ss)(sy) after each cat4/cat5/cat6
- fullnop - adds (rpt4) nop before every instruction

Useful to debug errors in inter-instruction synchronization.

Signed-off-by: Danylo Piliaiev 
Part-of: 

---

 src/freedreno/ir3/ir3_compiler.c |  2 ++
 src/freedreno/ir3/ir3_compiler.h |  2 ++
 src/freedreno/ir3/ir3_legalize.c | 35 +++
 src/freedreno/vulkan/tu_device.h |  2 +-
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index 80ca0656df7..7c38d392a2d 100644
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -47,6 +47,8 @@ static const struct debug_named_value shader_debug_options[] 
= {
{"nocache",IR3_DBG_NOCACHE,"Disable shader cache"},
{"spillall",   IR3_DBG_SPILLALL,   "Spill as much as possible to test the 
spiller"},
{"nopreamble", IR3_DBG_NOPREAMBLE, "Disable the preamble pass"},
+   {"fullsync",   IR3_DBG_FULLSYNC,   "Add (sy) + (ss) after each cat5/cat6"},
+   {"fullnop",IR3_DBG_FULLNOP,"Add nops before each instruction"},
 #ifdef DEBUG
/* DEBUG-only options: */
{"schedmsgs",  IR3_DBG_SCHEDMSGS,  "Enable scheduler debug messages"},
diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h
index 08eb53e9e82..7a550dcea08 100644
--- a/src/freedreno/ir3/ir3_compiler.h
+++ b/src/freedreno/ir3/ir3_compiler.h
@@ -299,6 +299,8 @@ enum ir3_shader_debug {
IR3_DBG_SPILLALL = BITFIELD_BIT(12),
IR3_DBG_NOPREAMBLE = BITFIELD_BIT(13),
IR3_DBG_SHADER_INTERNAL = BITFIELD_BIT(14),
+   IR3_DBG_FULLSYNC = BITFIELD_BIT(15),
+   IR3_DBG_FULLNOP = BITFIELD_BIT(16),
 
/* DEBUG-only options: */
IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20),
diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c
index e7db858ba28..958a08d23a9 100644
--- a/src/freedreno/ir3/ir3_legalize.c
+++ b/src/freedreno/ir3/ir3_legalize.c
@@ -948,6 +948,33 @@ nop_sched(struct ir3 *ir, struct ir3_shader_variant *so)
}
 }
 
+static void
+dbg_sync_sched(struct ir3 *ir, struct ir3_shader_variant *so)
+{
+   foreach_block (block, >block_list) {
+  foreach_instr_safe (instr, >instr_list) {
+ if (opc_cat(instr->opc) == 4 || opc_cat(instr->opc) == 5 ||
+ opc_cat(instr->opc) == 6) {
+struct ir3_instruction *nop = ir3_NOP(block);
+nop->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
+ir3_instr_move_after(nop, instr);
+ }
+  }
+   }
+}
+
+static void
+dbg_nop_sched(struct ir3 *ir, struct ir3_shader_variant *so)
+{
+   foreach_block (block, >block_list) {
+  foreach_instr_safe (instr, >instr_list) {
+ struct ir3_instruction *nop = ir3_NOP(block);
+ nop->repeat = 5;
+ ir3_instr_move_before(nop, instr);
+  }
+   }
+}
+
 struct ir3_helper_block_data {
/* Whether helper invocations may be used on any path starting at the
 * beginning of the block.
@@ -1230,6 +1257,14 @@ ir3_legalize(struct ir3 *ir, struct ir3_shader_variant 
*so, int *max_bary)
 
nop_sched(ir, so);
 
+   if (ir3_shader_debug & IR3_DBG_FULLSYNC) {
+  dbg_sync_sched(ir, so);
+   }
+
+   if (ir3_shader_debug & IR3_DBG_FULLNOP) {
+  dbg_nop_sched(ir, so);
+   }
+
while (opt_jump(ir))
   ;
 
diff --git a/src/freedreno/vulkan/tu_device.h b/src/freedreno/vulkan/tu_device.h
index bd7e715807c..e0434148211 100644
--- a/src/freedreno/vulkan/tu_device.h
+++ b/src/freedreno/vulkan/tu_device.h
@@ -31,7 +31,7 @@
 #define TU_BORDER_COLOR_COUNT 4096
 #define TU_BORDER_COLOR_BUILTIN 6
 
-#define TU_BLIT_SHADER_SIZE 1024
+#define TU_BLIT_SHADER_SIZE 4096
 
 /* extra space in vsc draw/prim streams */
 #define VSC_PAD 0x40

Mesa (main): ir3: Fix "print" meta instruction synchronization

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 123c5e7c3a19c169a6116b3081ae777ebb81d8d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=123c5e7c3a19c169a6116b3081ae777ebb81d8d9

Author: Danylo Piliaiev 
Date:   Thu Jan 11 18:19:30 2024 +0100

ir3: Fix "print" meta instruction synchronization

There was a WAR hazard if something writes to sources last STG is
using. (sy)nop did not wait for sources to become "free", we
need to use (ss).

Signed-off-by: Danylo Piliaiev 
Part-of: 

---

 src/freedreno/ir3/ir3_parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index b88d8ae529d..2a5ceb5fa6b 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -1395,7 +1395,7 @@ meta_print: T_OP_PRINT T_REGISTER ',' T_REGISTER {
new_src(0, IR3_REG_IMMED)->iim_val = 1;
 
new_instr(OPC_NOP);
-   instr->flags = IR3_INSTR_SY;
+   instr->flags = IR3_INSTR_SS;
 }
 
 src:   T_REGISTER { $$ = new_src($1, 0); }

Mesa (main): rusticl/kernel: add a few comments in regards to pass ordering

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 835c208578b333f4624dc7d81158058e99e5efb0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=835c208578b333f4624dc7d81158058e99e5efb0

Author: Karol Herbst 
Date:   Mon Jan 15 12:37:17 2024 +0100

rusticl/kernel: add a few comments in regards to pass ordering

This is helpful as otherwise I'll keep doing the same mistakes trying to
fix anything in here.

Part-of: 

---

 src/gallium/frontends/rusticl/core/kernel.rs | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/frontends/rusticl/core/kernel.rs 
b/src/gallium/frontends/rusticl/core/kernel.rs
index 05296c0cd0e..cbe02152c41 100644
--- a/src/gallium/frontends/rusticl/core/kernel.rs
+++ b/src/gallium/frontends/rusticl/core/kernel.rs
@@ -516,6 +516,8 @@ fn lower_and_optimize_nir(
 nir_variable_mode::nir_var_mem_constant,
 Some(glsl_get_cl_type_size_align),
 );
+
+// has to run before adding internal kernel arguments
 nir.extract_constant_initializers();
 
 // run before gather info
@@ -615,6 +617,8 @@ fn lower_and_optimize_nir(
 );
 }
 
+// need to run after first opt loop and remove_dead_variables to get rid 
of uneccessary scratch
+// memory
 nir_pass!(
 nir,
 nir_lower_vars_to_explicit_types,

Mesa (main): rusticl/kernel: no need to reset the scratch size anymore

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: ea023ff5cddf91521436b6d3f24021ae35774997
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea023ff5cddf91521436b6d3f24021ae35774997

Author: Karol Herbst 
Date:   Mon Jan 15 12:34:46 2024 +0100

rusticl/kernel: no need to reset the scratch size anymore

The scratch size gets assigned by nir_lower_vars_to_explicit_types. Now
that we only run it once on temp memory, there is no need to reset the
value.

Signed-off-by: Karol Herbst 
Part-of: 

---

 src/gallium/frontends/rusticl/core/kernel.rs   | 1 -
 src/gallium/frontends/rusticl/mesa/compiler/nir.rs | 6 --
 2 files changed, 7 deletions(-)

diff --git a/src/gallium/frontends/rusticl/core/kernel.rs 
b/src/gallium/frontends/rusticl/core/kernel.rs
index cbe02152c41..73ebcbb1ff1 100644
--- a/src/gallium/frontends/rusticl/core/kernel.rs
+++ b/src/gallium/frontends/rusticl/core/kernel.rs
@@ -509,7 +509,6 @@ fn lower_and_optimize_nir(
 !dev.samplers_as_deref(),
 );
 
-nir.reset_scratch_size();
 nir_pass!(
 nir,
 nir_lower_vars_to_explicit_types,
diff --git a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs 
b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs
index b61ec9254a9..5845d017d13 100644
--- a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs
+++ b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs
@@ -308,12 +308,6 @@ impl NirShader {
 unsafe { (*self.nir.as_ptr()).info.num_textures }
 }
 
-pub fn reset_scratch_size( self) {
-unsafe {
-(*self.nir.as_ptr()).scratch_size = 0;
-}
-}
-
 pub fn scratch_size() -> u32 {
 unsafe { (*self.nir.as_ptr()).scratch_size }
 }

Mesa (main): rusticl/kernel: run opt/lower_memcpy later to fix a crash

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f8966598940ad46fb1ff2cbd9c23013289ef0736
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8966598940ad46fb1ff2cbd9c23013289ef0736

Author: Karol Herbst 
Date:   Mon Jan 15 12:37:02 2024 +0100

rusticl/kernel: run opt/lower_memcpy later to fix a crash

nir_opt_memcpy requires explicit types to function properly. So run them
after lowering vars to explicit types.

Cc: mesa-stable
Signed-off-by: Karol Herbst 
Part-of: 

---

 src/gallium/frontends/rusticl/core/kernel.rs | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/gallium/frontends/rusticl/core/kernel.rs 
b/src/gallium/frontends/rusticl/core/kernel.rs
index a73638fdb54..05296c0cd0e 100644
--- a/src/gallium/frontends/rusticl/core/kernel.rs
+++ b/src/gallium/frontends/rusticl/core/kernel.rs
@@ -317,7 +317,7 @@ where
 res
 }
 
-fn opt_nir(nir:  NirShader, dev: ) {
+fn opt_nir(nir:  NirShader, dev: , has_explicit_types: bool) {
 let nir_options = unsafe {
 &*dev
 .screen
@@ -342,7 +342,9 @@ fn opt_nir(nir:  NirShader, dev: ) {
 }
 
 progress |= nir_pass!(nir, nir_opt_deref);
-progress |= nir_pass!(nir, nir_opt_memcpy);
+if has_explicit_types {
+progress |= nir_pass!(nir, nir_opt_memcpy);
+}
 progress |= nir_pass!(nir, nir_opt_dce);
 progress |= nir_pass!(nir, nir_opt_undef);
 progress |= nir_pass!(nir, nir_opt_constant_folding);
@@ -451,11 +453,10 @@ fn lower_and_optimize_nir(
 printf_opts.max_buffer_size = dev.printf_buffer_size() as u32;
 nir_pass!(nir, nir_lower_printf, _opts);
 
-opt_nir(nir, dev);
+opt_nir(nir, dev, false);
 
 let mut args = KernelArg::from_spirv_nir(args, nir);
 let mut internal_args = Vec::new();
-nir_pass!(nir, nir_lower_memcpy);
 
 let dv_opts = nir_remove_dead_variables_options {
 can_remove_var: Some(can_remove_var),
@@ -626,7 +627,8 @@ fn lower_and_optimize_nir(
 Some(glsl_get_cl_type_size_align),
 );
 
-opt_nir(nir, dev);
+opt_nir(nir, dev, true);
+nir_pass!(nir, nir_lower_memcpy);
 
 nir_pass!(
 nir,
@@ -655,7 +657,7 @@ fn lower_and_optimize_nir(
 
 nir_pass!(nir, nir_lower_convert_alu_types, None);
 
-opt_nir(nir, dev);
+opt_nir(nir, dev, true);
 
 /* before passing it into drivers, assign locations as drivers might 
remove nir_variables or
  * other things we depend on

Mesa (main): etnaviv: only add shared resources to implicit flush list

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 27ac55873a1cce5584a61992600382aa0acba97f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27ac55873a1cce5584a61992600382aa0acba97f

Author: Lucas Stach 
Date:   Mon Oct 16 20:07:42 2023 +0200

etnaviv: only add shared resources to implicit flush list

The implicit flushing is only required if the resource is shared
and changes to the resource must be visible outside of the screen
after the flush. For non-shared resources we can rely on the
screen internal tracking of data updates.

Signed-off-by: Lucas Stach 
Reviewed-by: Christian Gmeiner 
Part-of: 

---

 src/gallium/drivers/etnaviv/etnaviv_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
b/src/gallium/drivers/etnaviv/etnaviv_state.c
index c7619a512b0..a50071d1ae0 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -802,8 +802,9 @@ etna_record_flush_resources(struct etna_context *ctx)
 
if (fb->nr_cbufs > 0) {
   struct etna_surface *surf = etna_surface(fb->cbufs[0]);
+  struct etna_resource *rsc = etna_resource(surf->prsc);
 
-  if (!etna_resource(surf->prsc)->explicit_flush)
+  if (rsc->shared && !rsc->explicit_flush)
  etna_context_add_flush_resource(ctx, surf->prsc);
}
 

Mesa (main): etnaviv: track resource sharing

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 9ab9df39417af23bf07967fb66eaf8f9e6c8dab3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ab9df39417af23bf07967fb66eaf8f9e6c8dab3

Author: Lucas Stach 
Date:   Mon Oct 16 20:03:39 2023 +0200

etnaviv: track resource sharing

Track if resources are shared outside of the screen, which means
changes to the resource must be visible to the external observers
after a flush and the resource might be manipulated by other
agents than the contexts from the screen.

Signed-off-by: Lucas Stach 
Reviewed-by: Christian Gmeiner 
Part-of: 

---

 src/gallium/drivers/etnaviv/etnaviv_resource.c | 2 ++
 src/gallium/drivers/etnaviv/etnaviv_resource.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index aab21d95d95..87fdf8a4a90 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -678,6 +678,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
rsc->layout = modifier_to_layout(modifier);
rsc->modifier = modifier;
 
+   rsc->shared = true;
if (usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)
   rsc->explicit_flush = true;
 
@@ -780,6 +781,7 @@ etna_resource_get_handle(struct pipe_screen *pscreen,
}
handle->modifier = etna_resource_modifier(rsc);
 
+   rsc->shared = true;
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
   rsc->explicit_flush = false;
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h 
b/src/gallium/drivers/etnaviv/etnaviv_resource.h
index 1c480a8666f..df1b1c42032 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h
@@ -209,6 +209,8 @@ struct etna_resource {
struct pipe_resource *render;
/* frontend flushes resource via an explicit call to flush_resource */
bool explicit_flush;
+   /* resource is shared outside of the screen */
+   bool shared;
 };
 
 /* returns TRUE if a is newer than b */

Mesa (main): etnaviv: implicitly update shared texture resources

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2f229a8ba63d5840d6fb9ed430acdbfb1272ebee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f229a8ba63d5840d6fb9ed430acdbfb1272ebee

Author: Lucas Stach 
Date:   Mon Oct 16 20:44:01 2023 +0200

etnaviv: implicitly update shared texture resources

Implicitly update shared texture resources whenever they are first
used after the context has been flushed. This implements the
necessary behavior to get updated content for resources shared
outside of the screen without relying on any other API level
trigger, discussed to be necessary in [1].

[1] https://github.com/KhronosGroup/OpenGL-Registry/issues/566

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6220
Signed-off-by: Lucas Stach 
Reviewed-by: Christian Gmeiner 
Part-of: 

---

 src/gallium/drivers/etnaviv/etnaviv_context.c | 15 +++
 src/gallium/drivers/etnaviv/etnaviv_context.h |  2 ++
 src/gallium/drivers/etnaviv/etnaviv_texture.c |  8 
 3 files changed, 25 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index ec7cc282538..9561260b2b8 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -109,6 +109,9 @@ etna_context_destroy(struct pipe_context *pctx)
if (ctx->pending_resources)
   _mesa_hash_table_destroy(ctx->pending_resources, NULL);
 
+   if (ctx->updated_resources)
+  _mesa_set_destroy(ctx->updated_resources, NULL);
+
if (ctx->flush_resources)
   _mesa_set_destroy(ctx->flush_resources, NULL);
 
@@ -534,6 +537,13 @@ etna_flush(struct pipe_context *pctx, struct 
pipe_fence_handle **fence,
  pipe_resource_reference(, NULL);
   }
   _mesa_set_clear(ctx->flush_resources, NULL);
+
+  /* reset shared resources update tracking */
+  set_foreach(ctx->updated_resources, entry) {
+ struct pipe_resource *prsc = (struct pipe_resource *)entry->key;
+ pipe_resource_reference(, NULL);
+  }
+  _mesa_set_clear(ctx->updated_resources, NULL);
}
 
etna_cmd_stream_flush(ctx->stream, ctx->in_fence_fd,
@@ -625,6 +635,11 @@ etna_context_create(struct pipe_screen *pscreen, void 
*priv, unsigned flags)
if (!ctx->flush_resources)
   goto fail;
 
+   ctx->updated_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
+ _mesa_key_pointer_equal);
+   if (!ctx->updated_resources)
+  goto fail;
+
/* context ctxate setup */
ctx->screen = screen;
/* need some sane default in case gallium frontends don't set some state: */
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h 
b/src/gallium/drivers/etnaviv/etnaviv_context.h
index 874867d7da2..807fc0f14ff 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
@@ -201,6 +201,8 @@ struct etna_context {
 
/* resources that must be flushed implicitly at the context flush time */
struct set *flush_resources;
+   /* resources that need to be updated after a context flush */
+   struct set *updated_resources;
 
bool is_noop;
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c 
b/src/gallium/drivers/etnaviv/etnaviv_texture.c
index 1cd06d308ff..0ad354d5667 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_texture.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c
@@ -165,6 +165,14 @@ etna_update_sampler_source(struct pipe_sampler_view *view, 
int num)
struct etna_context *ctx = etna_context(view->context);
bool enable_sampler_ts = false;
 
+   if (base->shared && !_mesa_set_search(ctx->updated_resources, 
view->texture)) {
+  for (int i = view->u.tex.first_level; i <= view->u.tex.last_level; i++)
+ etna_resource_level_mark_changed(>levels[i]);
+
+  pipe_reference(NULL, >texture->reference);
+  _mesa_set_add(ctx->updated_resources, view->texture);
+   }
+
if (base->render && etna_resource_newer(etna_resource(base->render), base))
   from = etna_resource(base->render);
 

Mesa (main): v3d/ci: run OpenGL 3.1 tests

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 22c4a5e1272321e94a04bc316055e004fe8615fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22c4a5e1272321e94a04bc316055e004fe8615fe

Author: Juan A. Suarez Romero 
Date:   Fri Jan 12 16:02:23 2024 +0100

v3d/ci: run OpenGL 3.1 tests

As driver supports OpenGL 3.1, run proper tests, besides the OpenGL ES
tests.

Note that including GL3.1 is not required to include previous versions.

Reviewed-by: Eric Engestrom 
Signed-off-by: Juan A. Suarez Romero 
Part-of: 

---

 src/broadcom/ci/broadcom-rpi4-fails.txt | 3 +++
 src/broadcom/ci/deqp-broadcom-rpi4.toml | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/broadcom/ci/broadcom-rpi4-fails.txt 
b/src/broadcom/ci/broadcom-rpi4-fails.txt
index df86de42485..8a947f498b6 100644
--- a/src/broadcom/ci/broadcom-rpi4-fails.txt
+++ b/src/broadcom/ci/broadcom-rpi4-fails.txt
@@ -533,3 +533,6 @@ 
dEQP-VK.pipeline.shader_object_linked_binary.framebuffer_attachment.unused_attac
 
dEQP-VK.pipeline.shader_object_linked_spirv.framebuffer_attachment.unused_attachment,Crash
 
dEQP-VK.pipeline.shader_object_unlinked_binary.framebuffer_attachment.unused_attachment,Crash
 
dEQP-VK.pipeline.shader_object_unlinked_spirv.framebuffer_attachment.unused_attachment,Crash
+
+# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/4422
+KHR-GL31.texture_size_promotion.functional,Fail
diff --git a/src/broadcom/ci/deqp-broadcom-rpi4.toml 
b/src/broadcom/ci/deqp-broadcom-rpi4.toml
index 1fe67b427be..f4a1b7b724d 100644
--- a/src/broadcom/ci/deqp-broadcom-rpi4.toml
+++ b/src/broadcom/ci/deqp-broadcom-rpi4.toml
@@ -7,6 +7,7 @@ caselists = [
 "/deqp/mustpass/gles31-khr-master.txt",
 "/deqp/mustpass/gles3-khr-master.txt",
 "/deqp/mustpass/gles2-khr-master.txt",
+"/deqp/mustpass/gl31-master.txt",
 ]
 deqp_args = [
 "--deqp-gl-config-name=rgbad24s8ms0",

Mesa (main): freedreno/replay: Add WSL backend for Windows

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 480ec5b1d480c62bc9984a44bbb6453bca1970be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=480ec5b1d480c62bc9984a44bbb6453bca1970be

Author: Danylo Piliaiev 
Date:   Thu Nov  2 13:53:03 2023 +0100

freedreno/replay: Add WSL backend for Windows

d3dkmthk.h contains only non driver specific structs, private
data structs are not defined anywhere public but contain
important information for memory allocation and submissions.
Luckily only small parts of these structs are relevant for what
we want to do and most of them are not changed between calls.

Signed-off-by: Danylo Piliaiev 
Part-of: 

---

 include/drm-uapi/d3dkmthk.h  | 1794 ++
 meson_options.txt|2 +-
 src/freedreno/decode/meson.build |5 +-
 src/freedreno/decode/replay.c|  412 -
 4 files changed, 2197 insertions(+), 16 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=480ec5b1d480c62bc9984a44bbb6453bca1970be

Mesa (main): freedreno/replay: Correctly free iova on msm backend

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 16de8e99cf6500758295c73aaf878366caf99065
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16de8e99cf6500758295c73aaf878366caf99065

Author: Danylo Piliaiev 
Date:   Thu Nov  2 14:02:37 2023 +0100

freedreno/replay: Correctly free iova on msm backend

Signed-off-by: Danylo Piliaiev 
Part-of: 

---

 src/freedreno/decode/replay.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/freedreno/decode/replay.c b/src/freedreno/decode/replay.c
index 8955dcd88b1..eefecb1505d 100644
--- a/src/freedreno/decode/replay.c
+++ b/src/freedreno/decode/replay.c
@@ -634,6 +634,19 @@ buffer_mem_free(struct device *dev, struct buffer *buf)
if (dev->has_set_iova) {
   munmap(buf->map, buf->size);
 
+  struct drm_msm_gem_info req_iova = {
+ .handle = buf->gem_handle,
+ .info = MSM_INFO_SET_IOVA,
+ .value = 0,
+  };
+
+  int ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_INFO, _iova,
+sizeof(req_iova));
+  if (ret < 0) {
+ err(1, "MSM_INFO_SET_IOVA(0) failed! %d", ret);
+ return;
+  }
+
   struct drm_gem_close req = {
  .handle = buf->gem_handle,
   };

Mesa (main): freedreno/replay: Delete all buffers after each submission

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 56a6bc758d5be2c6e137369590c9cfdc247242b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56a6bc758d5be2c6e137369590c9cfdc247242b5

Author: Danylo Piliaiev 
Date:   Thu Nov  2 14:00:44 2023 +0100

freedreno/replay: Delete all buffers after each submission

We expect all buffers to be dumped before each submission, so tracking
whether buffer is used is wrong.

Signed-off-by: Danylo Piliaiev 
Part-of: 

---

 src/freedreno/decode/replay.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/freedreno/decode/replay.c b/src/freedreno/decode/replay.c
index 6081640c711..8955dcd88b1 100644
--- a/src/freedreno/decode/replay.c
+++ b/src/freedreno/decode/replay.c
@@ -245,14 +245,12 @@ device_mark_buffers(struct device *dev)
 }
 
 static void
-device_free_unused_buffers(struct device *dev)
+device_free_buffers(struct device *dev)
 {
rb_tree_foreach_safe (struct buffer, buf, >buffers, node) {
-  if (!buf->used) {
- buffer_mem_free(dev, buf);
- rb_tree_remove(>buffers, >node);
- free(buf);
-  }
+  buffer_mem_free(dev, buf);
+  rb_tree_remove(>buffers, >node);
+  free(buf);
}
 }
 
@@ -451,11 +449,10 @@ device_create()
 static void
 device_submit_cmdstreams(struct device *dev)
 {
-   device_free_unused_buffers(dev);
-   device_mark_buffers(dev);
-
-   if (!u_vector_length(>cmdstreams))
+   if (!u_vector_length(>cmdstreams)) {
+  device_free_buffers(dev);
   return;
+   }
 
struct drm_msm_gem_submit_cmd cmds[u_vector_length(>cmdstreams)];
 
@@ -566,6 +563,8 @@ device_submit_cmdstreams(struct device *dev)
device_print_cp_log(dev);
 
device_dump_wrbuf(dev);
+
+   device_free_buffers(dev);
 }
 
 static void
@@ -709,11 +708,10 @@ device_create()
 static void
 device_submit_cmdstreams(struct device *dev)
 {
-   device_free_unused_buffers(dev);
-   device_mark_buffers(dev);
-
-   if (!u_vector_length(>cmdstreams))
+   if (!u_vector_length(>cmdstreams)) {
+  device_free_buffers(dev);
   return;
+   }
 
struct kgsl_command_object cmds[u_vector_length(>cmdstreams)];
 
@@ -761,6 +759,8 @@ device_submit_cmdstreams(struct device *dev)
device_print_cp_log(dev);
 
device_dump_wrbuf(dev);
+
+   device_free_buffers(dev);
 }
 
 static void
@@ -988,10 +988,10 @@ handle_file(const char *filename, uint32_t first_submit, 
uint32_t last_submit,
cs->iova = gpuaddr;
cs->size = sizedwords * sizeof(uint32_t);
 }
-
-need_submit = true;
  }
 
+ need_submit = true;
+
  submit++;
  break;
   }

Mesa (main): broadcom/simulator: protect simulator BO rallocs with mutexes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 985a5c8f1ad7c0cdaa9c8e874442145c156a1181
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=985a5c8f1ad7c0cdaa9c8e874442145c156a1181

Author: Juan A. Suarez Romero 
Date:   Mon Jan 15 10:59:56 2024 +0100

broadcom/simulator: protect simulator BO rallocs with mutexes

Move ralloc allocations and frees for BOs into the critical sections
protected with mutexes.

This fixes several double-free and use-after-free crashes that happens
sometimes when using the simulator to run Vulkan CTS tests, specially
when these tests involve multithreading, like
`dEQP-VK.api.object_management.multithreaded_per_thread_resources.device_memory_small`.

Reviewed-by: Alejandro Piñeiro 
Signed-off-by: Juan A. Suarez Romero 
Part-of: 

---

 src/broadcom/simulator/v3d_simulator.c | 14 ++
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/broadcom/simulator/v3d_simulator.c 
b/src/broadcom/simulator/v3d_simulator.c
index 5b43e269fdc..ee062504fc1 100644
--- a/src/broadcom/simulator/v3d_simulator.c
+++ b/src/broadcom/simulator/v3d_simulator.c
@@ -216,17 +216,15 @@ static struct v3d_simulator_bo *
 v3d_create_simulator_bo(int fd, unsigned size)
 {
 struct v3d_simulator_file *file = v3d_get_simulator_file_for_fd(fd);
-struct v3d_simulator_bo *sim_bo = rzalloc(file,
-  struct v3d_simulator_bo);
-size = align(size, 4096);
-
-sim_bo->file = file;
 
 simple_mtx_lock(_state.mutex);
+struct v3d_simulator_bo *sim_bo = rzalloc(file,
+  struct v3d_simulator_bo);
 sim_bo->block = u_mmAllocMem(sim_state.heap, size + 4, GMP_ALIGN2, 0);
 simple_mtx_unlock(_state.mutex);
 assert(sim_bo->block);
-
+size = align(size, 4096);
+sim_bo->file = file;
 set_gmp_flags(file, sim_bo->block->ofs, size, 0x3);
 
 sim_bo->size = size;
@@ -344,8 +342,8 @@ v3d_free_simulator_bo(struct v3d_simulator_bo *sim_bo)
 _mesa_hash_table_remove_key(sim_file->bo_map,
 int_to_key(sim_bo->handle));
 }
-simple_mtx_unlock(_state.mutex);
 ralloc_free(sim_bo);
+simple_mtx_unlock(_state.mutex);
 }
 
 static struct v3d_simulator_bo *
@@ -1208,8 +1206,8 @@ v3d_simulator_destroy(struct v3d_simulator_file *sim_file)
 /* No memsetting the struct, because it contains the mutex. */
 sim_state.mem = NULL;
 }
-simple_mtx_unlock(_state.mutex);
 ralloc_free(sim_file);
+simple_mtx_unlock(_state.mutex);
 }
 
 #endif /* USE_V3D_SIMULATOR */

Mesa (main): anv: export descriptor flushing functions

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6bb3ae99c52be4707ccebc5d62b6215e5a52baee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bb3ae99c52be4707ccebc5d62b6215e5a52baee

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:07:31 2024 +0200

anv: export descriptor flushing functions

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/anv_genX.h| 11 
 src/intel/vulkan/genX_cmd_buffer.c | 57 +++---
 2 files changed, 40 insertions(+), 28 deletions(-)

diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h
index 477f1688353..bd3dc52f910 100644
--- a/src/intel/vulkan/anv_genX.h
+++ b/src/intel/vulkan/anv_genX.h
@@ -133,6 +133,17 @@ void genX(emit_l3_config)(struct anv_batch *batch,
 void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
 const struct intel_l3_config *cfg);
 
+uint32_t
+genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_cmd_pipeline_state 
*pipe_state,
+   const VkShaderStageFlags dirty,
+   struct anv_shader_bin **shaders,
+   uint32_t num_shaders);
+void
+genX(cmd_buffer_flush_push_descriptor_set)(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_cmd_pipeline_state 
*state,
+   struct anv_pipeline *pipeline);
+
 void genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer);
 
 void genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer 
*cmd_buffer);
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index e922ffd60a9..01fa76b16a5 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2266,12 +2266,12 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer,
return VK_SUCCESS;
 }
 
-static uint32_t
-flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer,
-  struct anv_cmd_pipeline_state *pipe_state,
-  const VkShaderStageFlags dirty,
-  struct anv_shader_bin **shaders,
-  uint32_t num_shaders)
+uint32_t
+genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_cmd_pipeline_state 
*pipe_state,
+   const VkShaderStageFlags dirty,
+   struct anv_shader_bin **shaders,
+   uint32_t num_shaders)
 {
VkShaderStageFlags flushed = 0;
 
@@ -2346,10 +2346,10 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer,
  * and surface state generation when a pipeline is not going to use the
  * binding table to access any push descriptor data.
  */
-static void
-flush_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
-  struct anv_cmd_pipeline_state *state,
-  struct anv_pipeline *pipeline)
+void
+genX(cmd_buffer_flush_push_descriptor_set)(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_cmd_pipeline_state 
*state,
+   struct anv_pipeline *pipeline)
 {
assert(pipeline->use_push_descriptor &&
   pipeline->layout.push_descriptor_set_index != -1);
@@ -3167,9 +3167,9 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer 
*cmd_buffer)
   cmd_buffer->state.push_descriptors_dirty &
   pipeline->base.base.use_push_descriptor;
if (push_descriptor_dirty) {
-  flush_push_descriptor_set(cmd_buffer,
-_buffer->state.gfx.base,
->base.base);
+  genX(cmd_buffer_flush_push_descriptor_set)(cmd_buffer,
+ _buffer->state.gfx.base,
+ >base.base);
   descriptors_dirty |= push_descriptor_dirty;
   cmd_buffer->state.push_descriptors_dirty &= ~push_descriptor_dirty;
}
@@ -3280,11 +3280,12 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer 
*cmd_buffer)
 */
uint32_t dirty = 0;
if (descriptors_dirty) {
-  dirty = flush_descriptor_sets(cmd_buffer,
-_buffer->state.gfx.base,
-descriptors_dirty,
-pipeline->base.shaders,
-ARRAY_SIZE(pipeline->base.shaders));
+  dirty = genX(cmd_buffer_flush_descriptor_sets)(
+ cmd_buffer,
+ _buffer->state.gfx.base,
+ descriptors_dirty,
+ pipeline->base.shaders,
+ ARRAY_SIZE(pipeline->base.shaders));
   cmd_buffer->state.descriptors_dirty &= 

Mesa (main): anv: rename video command file

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 56eb09480b6ffe4488e9527628ab0444046d5347
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56eb09480b6ffe4488e9527628ab0444046d5347

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:23:00 2024 +0200

anv: rename video command file

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/{genX_video.c => genX_cmd_video.c} | 0
 src/intel/vulkan/meson.build| 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_video.c b/src/intel/vulkan/genX_cmd_video.c
similarity index 100%
rename from src/intel/vulkan/genX_video.c
rename to src/intel/vulkan/genX_cmd_video.c
diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
index 8bd725fd73f..58381c8629c 100644
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -105,13 +105,13 @@ anv_per_hw_ver_files = files(
   'genX_cmd_draw.c',
   'genX_cmd_draw_generated_flush.h',
   'genX_cmd_draw_generated_indirect.h',
+  'genX_cmd_video.c',
   'genX_gfx_state.c',
   'genX_gpu_memcpy.c',
   'genX_init_state.c',
   'genX_pipeline.c',
   'genX_query.c',
   'genX_simple_shader.c',
-  'genX_video.c',
 )
 if with_intel_vk_rt
   anv_per_hw_ver_files += files('genX_acceleration_structure.c',)

Mesa (main): anv: fix missing header

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: df1dc882cb22603621ecdcf292dace835efde8ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df1dc882cb22603621ecdcf292dace835efde8ff

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:13:32 2024 +0200

anv: fix missing header

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
index aee37f48887..918596e1bd9 100644
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -101,6 +101,7 @@ libanv_per_hw_ver_libs = []
 anv_per_hw_ver_files = files(
   'genX_blorp_exec.c',
   'genX_cmd_buffer.c',
+  'genX_cmd_draw_generated_indirect.h',
   'genX_gfx_state.c',
   'genX_gpu_memcpy.c',
   'genX_init_state.c',

Mesa (main): anv: move draw commands to their own file

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: cfe894e1e94a33a290d78cbebb6ebdfb4aaa5426
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfe894e1e94a33a290d78cbebb6ebdfb4aaa5426

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:14:49 2024 +0200

anv: move draw commands to their own file

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/genX_cmd_buffer.c | 2356 +---
 src/intel/vulkan/genX_cmd_draw.c   | 2329 +++
 src/intel/vulkan/meson.build   |1 +
 3 files changed, 2370 insertions(+), 2316 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=cfe894e1e94a33a290d78cbebb6ebdfb4aaa5426

Mesa (main): anv: move compute/ray-tracing commands to their own file

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 51d63f22363d08e7b9477fd795d4c1bcc04acf72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51d63f22363d08e7b9477fd795d4c1bcc04acf72

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:21:29 2024 +0200

anv: move compute/ray-tracing commands to their own file

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/genX_cmd_buffer.c  | 1121 -
 src/intel/vulkan/genX_cmd_compute.c | 1169 +++
 src/intel/vulkan/meson.build|1 +
 3 files changed, 1170 insertions(+), 1121 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=51d63f22363d08e7b9477fd795d4c1bcc04acf72

Mesa (main): anv: move generated draw flush helper to its own file

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: ddc18b4e78407901396266ba53c4fad6098cc655
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ddc18b4e78407901396266ba53c4fad6098cc655

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:14:28 2024 +0200

anv: move generated draw flush helper to its own file

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/genX_cmd_buffer.c |  1 +
 src/intel/vulkan/genX_cmd_draw_generated_flush.h   | 79 ++
 .../vulkan/genX_cmd_draw_generated_indirect.h  | 43 
 src/intel/vulkan/meson.build   |  1 +
 4 files changed, 81 insertions(+), 43 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 01fa76b16a5..1d15459f47c 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3313,6 +3313,7 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer 
*cmd_buffer)
cmd_buffer->state.gfx.dirty = 0;
 }
 
+#include "genX_cmd_draw_generated_flush.h"
 #include "genX_cmd_draw_generated_indirect.h"
 
 ALWAYS_INLINE static bool
diff --git a/src/intel/vulkan/genX_cmd_draw_generated_flush.h 
b/src/intel/vulkan/genX_cmd_draw_generated_flush.h
new file mode 100644
index 000..d810bee746c
--- /dev/null
+++ b/src/intel/vulkan/genX_cmd_draw_generated_flush.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright © 2024 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GENX_CMD_DRAW_GENERATED_FLUSH_H
+#define GENX_CMD_DRAW_GENERATED_FLUSH_H
+
+#include 
+#include 
+
+#include "util/macros.h"
+
+#include "common/intel_genX_state.h"
+
+#include "anv_private.h"
+
+static void
+genX(cmd_buffer_flush_generated_draws)(struct anv_cmd_buffer *cmd_buffer)
+{
+   if (!anv_cmd_buffer_is_render_queue(cmd_buffer))
+  return;
+
+   /* No return address setup means we don't have to do anything */
+   if (anv_address_is_null(cmd_buffer->generation.return_addr))
+  return;
+
+   struct anv_batch *batch = _buffer->generation.batch;
+
+   /* Wait for all the generation vertex shader to generate the commands. */
+   genX(emit_apply_pipe_flushes)(batch,
+ cmd_buffer->device,
+ _3D,
+#if GFX_VER == 9
+ ANV_PIPE_VF_CACHE_INVALIDATE_BIT |
+#endif
+ ANV_PIPE_DATA_CACHE_FLUSH_BIT |
+ ANV_PIPE_CS_STALL_BIT,
+ NULL /* emitted_bits */);
+
+#if GFX_VER >= 12
+   anv_batch_emit(batch, GENX(MI_ARB_CHECK), arb) {
+  arb.PreParserDisableMask = true;
+  arb.PreParserDisable = true;
+   }
+#else
+   /* Prior to Gfx12 we cannot disable the CS prefetch but it doesn't matter
+* as the prefetch shouldn't follow the MI_BATCH_BUFFER_START.
+*/
+#endif
+
+   /* Return to the main batch. */
+   anv_batch_emit(batch, GENX(MI_BATCH_BUFFER_START), bbs) {
+  bbs.AddressSpaceIndicator = ASI_PPGTT;
+  bbs.BatchBufferStartAddress = cmd_buffer->generation.return_addr;
+   }
+
+   cmd_buffer->generation.return_addr = ANV_NULL_ADDRESS;
+}
+
+#endif /* GENX_CMD_DRAW_GENERATED_FLUSH_H */
diff --git a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h 
b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
index e9c00a33665..4eb27d262d5 100644
--- a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
+++ b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
@@ -636,47 +636,4 @@ genX(cmd_buffer_emit_indirect_generated_draws)(struct 
anv_cmd_buffer *cmd_buffer
}
 }
 
-static void
-genX(cmd_buffer_flush_generated_draws)(struct anv_cmd_buffer *cmd_buffer)
-{
-   if (!anv_cmd_buffer_is_render_queue(cmd_buffer))
-  return;
-
-   /* No return address setup means we don't have to do anything */
-   

Mesa (main): anv: fix include guards

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 74c8edd288fd67fc3b2ba5623738422d3018991f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74c8edd288fd67fc3b2ba5623738422d3018991f

Author: Lionel Landwerlin 
Date:   Wed Jan 10 14:11:36 2024 +0200

anv: fix include guards

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/vulkan/genX_cmd_draw_generated_indirect.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h 
b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
index b3c9db48932..e9c00a33665 100644
--- a/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
+++ b/src/intel/vulkan/genX_cmd_draw_generated_indirect.h
@@ -21,8 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-#ifndef GENX_CMD_GENERATED_INDIRECT_DRAW_H
-#define GENX_CMD_GENERATED_INDIRECT_DRAW_H
+#ifndef GENX_CMD_DRAW_GENERATED_INDIRECT_H
+#define GENX_CMD_DRAW_GENERATED_INDIRECT_H
 
 #include 
 #include 
@@ -679,4 +679,4 @@ genX(cmd_buffer_flush_generated_draws)(struct 
anv_cmd_buffer *cmd_buffer)
cmd_buffer->generation.return_addr = ANV_NULL_ADDRESS;
 }
 
-#endif /* GENX_CMD_GENERATED_INDIRECT_DRAW_H */
+#endif /* GENX_CMD_DRAW_GENERATED_INDIRECT_H */

Mesa (main): radv: never set DISABLE_WR_CONFIRM for CP DMA clears and copies

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 43fb43ba2cfe673d5b6693bfe93d0331f86817ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43fb43ba2cfe673d5b6693bfe93d0331f86817ed

Author: Tatsuyuki Ishi 
Date:   Sun Jan 14 02:49:23 2024 +0900

radv: never set DISABLE_WR_CONFIRM for CP DMA clears and copies

This mirrors the changes in 69ff9c16bbb ("radeonsi: never set
DISABLE_WR_CONFIRM for CP DMA clears and copies").

Cc: mesa-stable
Suggested-by: Vitaliy Triang3l Kuzmin 
Reviewed-by: Bas Nieuwenhuizen 
Part-of: 

---

 src/amd/vulkan/si_cmd_buffer.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index adcaffa64d6..73a8b847a5c 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1606,12 +1606,6 @@ radv_cs_emit_cp_dma(struct radv_device *device, struct 
radeon_cmdbuf *cs, bool p
/* Sync flags. */
if (flags & CP_DMA_SYNC)
   header |= S_411_CP_SYNC(1);
-   else {
-  if (device->physical_device->rad_info.gfx_level >= GFX9)
- command |= S_415_DISABLE_WR_CONFIRM_GFX9(1);
-  else
- command |= S_415_DISABLE_WR_CONFIRM_GFX6(1);
-   }
 
if (flags & CP_DMA_RAW_WAIT)
   command |= S_415_RAW_WAIT(1);

Mesa (main): radv: introduce radv_graphics_state_key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b555f9451cc3a22209cc7ff91e2f29fdb6f946ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b555f9451cc3a22209cc7ff91e2f29fdb6f946ed

Author: Samuel Pitoiset 
Date:   Thu Jan 11 15:32:38 2024 +0100

radv: introduce radv_graphics_state_key

This struct only contains graphics related state.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir.h  |  15 +-
 src/amd/vulkan/nir/radv_nir_lower_abi.c|  28 ++--
 src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c |   6 +-
 src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c  |  10 +-
 .../vulkan/nir/radv_nir_lower_intrinsics_early.c   |   4 +-
 .../vulkan/nir/radv_nir_lower_poly_line_smooth.c   |   8 +-
 src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c  |  20 +--
 src/amd/vulkan/radv_pipeline.c |  22 +--
 src/amd/vulkan/radv_pipeline_graphics.c| 180 +++--
 src/amd/vulkan/radv_private.h  |   6 +-
 src/amd/vulkan/radv_shader.c   |  48 +++---
 src/amd/vulkan/radv_shader.h   |  37 +++--
 src/amd/vulkan/radv_shader_args.c  |  30 ++--
 src/amd/vulkan/radv_shader_args.h  |   4 +-
 src/amd/vulkan/radv_shader_info.c  |  90 +--
 15 files changed, 264 insertions(+), 244 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=b555f9451cc3a22209cc7ff91e2f29fdb6f946ed

Mesa (main): radv: use radv_shader_stage_key directly with pre-existing fields

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3a776f036fc9d47f9afaf6003f256f098ef934a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a776f036fc9d47f9afaf6003f256f098ef934a1

Author: Samuel Pitoiset 
Date:   Tue Jan  9 14:43:23 2024 +0100

radv: use radv_shader_stage_key directly with pre-existing fields

More fields will be moved to radv_shader_stage_key but start using it
with pre-existing fields.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline.c  |  4 ++--
 src/amd/vulkan/radv_pipeline_compute.c  |  4 ++--
 src/amd/vulkan/radv_pipeline_graphics.c |  6 +++---
 src/amd/vulkan/radv_pipeline_rt.c   |  4 ++--
 src/amd/vulkan/radv_shader.c|  2 +-
 src/amd/vulkan/radv_shader.h|  3 ++-
 src/amd/vulkan/radv_shader_info.c   | 23 +++
 7 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4eac4fbf839..3e5cde9c794 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -519,10 +519,10 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
   .has_shared2_amd = gfx_level >= GFX7,
};
 
-   if (pipeline_key->stage_info[stage->stage].uniform_robustness2)
+   if (stage->key.uniform_robustness2)
   vectorize_opts.robust_modes |= nir_var_mem_ubo;
 
-   if (pipeline_key->stage_info[stage->stage].storage_robustness2)
+   if (stage->key.storage_robustness2)
   vectorize_opts.robust_modes |= nir_var_mem_ssbo;
 
if (!pipeline_key->optimisations_disabled) {
diff --git a/src/amd/vulkan/radv_pipeline_compute.c 
b/src/amd/vulkan/radv_pipeline_compute.c
index 1255e935b1f..7122f4055f8 100644
--- a/src/amd/vulkan/radv_pipeline_compute.c
+++ b/src/amd/vulkan/radv_pipeline_compute.c
@@ -148,8 +148,8 @@ radv_compile_cs(struct radv_device *device, struct 
vk_pipeline_cache *cache, str
 
/* Run the shader info pass. */
radv_nir_shader_info_init(cs_stage->stage, MESA_SHADER_NONE, 
_stage->info);
-   radv_nir_shader_info_pass(device, cs_stage->nir, _stage->layout, 
pipeline_key, RADV_PIPELINE_COMPUTE, false,
- _stage->info);
+   radv_nir_shader_info_pass(device, cs_stage->nir, _stage->layout, 
_stage->key, pipeline_key,
+ RADV_PIPELINE_COMPUTE, false, _stage->info);
 
radv_declare_shader_args(device, pipeline_key, _stage->info, 
MESA_SHADER_COMPUTE, MESA_SHADER_NONE,
 _stage->args);
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c 
b/src/amd/vulkan/radv_pipeline_graphics.c
index 3235ebca881..874171ebbd7 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -2102,7 +2102,7 @@ radv_fill_shader_info(struct radv_device *device, const 
enum radv_pipeline_type
  consider_force_vrs = radv_consider_force_vrs(pipeline_key, 
[i], [MESA_SHADER_FRAGMENT]);
   }
 
-  radv_nir_shader_info_pass(device, stages[i].nir, [i].layout, 
pipeline_key, pipeline_type,
+  radv_nir_shader_info_pass(device, stages[i].nir, [i].layout, 
[i].key, pipeline_key, pipeline_type,
 consider_force_vrs, [i].info);
}
 
@@ -2177,8 +2177,8 @@ radv_create_gs_copy_shader(struct radv_device *device, 
struct vk_pipeline_cache
   .shader_sha1 = {0},
};
radv_nir_shader_info_init(gs_copy_stage.stage, MESA_SHADER_FRAGMENT, 
_copy_stage.info);
-   radv_nir_shader_info_pass(device, nir, _stage->layout, pipeline_key, 
RADV_PIPELINE_GRAPHICS, false,
- _copy_stage.info);
+   radv_nir_shader_info_pass(device, nir, _stage->layout, _stage->key, 
pipeline_key, RADV_PIPELINE_GRAPHICS,
+ false, _copy_stage.info);
gs_copy_stage.info.wave_size = 64;  /* Wave32 not supported. */
gs_copy_stage.info.workgroup_size = 64; /* HW VS: separate waves, no 
workgroups */
gs_copy_stage.info.so = gs_info->so;
diff --git a/src/amd/vulkan/radv_pipeline_rt.c 
b/src/amd/vulkan/radv_pipeline_rt.c
index 86da0d27f94..f28769cedc8 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -369,8 +369,8 @@ radv_rt_nir_to_asm(struct radv_device *device, struct 
vk_pipeline_cache *cache,
/* Gather shader info. */
nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir));
radv_nir_shader_info_init(stage->stage, MESA_SHADER_NONE, >info);
-   radv_nir_shader_info_pass(device, stage->nir, >layout, pipeline_key, 
RADV_PIPELINE_RAY_TRACING, false,
- >info);
+   radv_nir_shader_info_pass(device, stage->nir, >layout, >key, 
pipeline_key, RADV_PIPELINE_RAY_TRACING,
+ false, >info);
 
/* Declare shader arguments. */
radv_declare_shader_args(device, pipeline_key, >info, stage->stage, 
MESA_SHADER_NONE, >args);
diff --git 

Mesa (main): radv: re-organize radv_pipeline_key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f2f87d08721d53f6b5821d378b71b186e8a7deb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2f87d08721d53f6b5821d378b71b186e8a7deb4

Author: Samuel Pitoiset 
Date:   Thu Jan 11 14:31:43 2024 +0100

radv: re-organize radv_pipeline_key

Rename and regroup fields per PSO basically.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir_lower_abi.c| 10 +++
 src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c |  2 +-
 src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c  |  4 +--
 .../vulkan/nir/radv_nir_lower_poly_line_smooth.c   |  2 +-
 src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c  | 14 -
 src/amd/vulkan/radv_pipeline_graphics.c| 30 +--
 src/amd/vulkan/radv_private.h  |  4 +--
 src/amd/vulkan/radv_shader.c   |  4 +--
 src/amd/vulkan/radv_shader.h   | 34 +-
 src/amd/vulkan/radv_shader_args.c  |  4 +--
 src/amd/vulkan/radv_shader_info.c  | 18 ++--
 11 files changed, 66 insertions(+), 60 deletions(-)

diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c 
b/src/amd/vulkan/nir/radv_nir_lower_abi.c
index 97d916c9966..95ff340e0f9 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c
@@ -157,8 +157,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr 
*intrin, void *state)
   break;
case nir_intrinsic_load_patch_vertices_in:
   if (stage == MESA_SHADER_TESS_CTRL) {
- if (s->pl_key->tcs.tess_input_vertices) {
-replacement = nir_imm_int(b, s->pl_key->tcs.tess_input_vertices);
+ if (s->pl_key->ts.patch_control_points) {
+replacement = nir_imm_int(b, s->pl_key->ts.patch_control_points);
  } else {
 replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, 
TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS);
  }
@@ -351,7 +351,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr 
*intrin, void *state)
   if (s->pl_key->dynamic_rasterization_samples) {
  replacement = GET_SGPR_FIELD_NIR(s->args->ps_state, 
PS_STATE_NUM_SAMPLES);
   } else {
- replacement = nir_imm_int(b, s->pl_key->ps.num_samples);
+ replacement = nir_imm_int(b, s->pl_key->ms.rasterization_samples);
   }
   break;
case nir_intrinsic_load_provoking_vtx_in_prim_amd: {
@@ -359,7 +359,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr 
*intrin, void *state)
  replacement = ac_nir_load_arg(b, >args->ac, 
s->args->ngg_provoking_vtx);
   } else {
  unsigned provoking_vertex = 0;
- if (s->pl_key->vs.provoking_vtx_last) {
+ if (s->pl_key->rs.provoking_vtx_last) {
 if (stage == MESA_SHADER_VERTEX) {
provoking_vertex = radv_get_num_vertices_per_prim(s->pl_key) - 
1;
 } else if (stage == MESA_SHADER_GEOMETRY) {
@@ -489,7 +489,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr 
*intrin, void *state)
  nir_def *line_rast_mode = GET_SGPR_FIELD_NIR(s->args->ps_state, 
PS_STATE_LINE_RAST_MODE);
  replacement = nir_ieq_imm(b, line_rast_mode, 
VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT);
   } else {
- replacement = nir_imm_bool(b, s->pl_key->ps.line_smooth_enabled);
+ replacement = nir_imm_bool(b, s->pl_key->rs.line_smooth_enabled);
   }
   break;
case nir_intrinsic_load_initial_edgeflags_amd:
diff --git a/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c 
b/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c
index d97c4117591..41a86b5b856 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_fs_barycentric.c
@@ -266,7 +266,7 @@ radv_nir_lower_fs_barycentric(nir_shader *shader, const 
struct radv_pipeline_key
 
lower_fs_barycentric_state state = {
   .dynamic_rasterization_samples = key->dynamic_rasterization_samples,
-  .num_rasterization_samples = key->ps.num_samples,
+  .num_rasterization_samples = key->ms.rasterization_samples,
   .rast_prim = rast_prim,
};
 
diff --git a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c 
b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c
index 4300f795715..8686972deb2 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c
@@ -52,7 +52,7 @@ radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct 
radv_shader_stage *fs
 nir_def *sample_coverage = nir_load_vector_arg_amd(, 1, .base = 
args->ac.sample_coverage.arg_index);
 
 nir_def *def = NULL;
-if (info->ps.uses_sample_shading || key->ps.sample_shading_enable) 
{
+if (info->ps.uses_sample_shading || key->ms.sample_shading_enable) 
{
/* gl_SampleMaskIn[0] = (SampleCoverage & 

Mesa (main): radv: stop passing the pipeline key when compiling compute/rt shaders

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: fb80421a62356c3c8af6f868dc4f690b59efb33b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb80421a62356c3c8af6f868dc4f690b59efb33b

Author: Samuel Pitoiset 
Date:   Thu Jan 11 16:20:06 2024 +0100

radv: stop passing the pipeline key when compiling compute/rt shaders

The pipeline key now essentially contains graphics state.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir_rt_shader.c |  2 +-
 src/amd/vulkan/radv_pipeline_compute.c  | 24 +++-
 src/amd/vulkan/radv_pipeline_rt.c   | 23 +++
 3 files changed, 23 insertions(+), 26 deletions(-)

diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c 
b/src/amd/vulkan/nir/radv_nir_rt_shader.c
index 8a8b3a08236..9fb0b25abda 100644
--- a/src/amd/vulkan/nir/radv_nir_rt_shader.c
+++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c
@@ -815,7 +815,7 @@ radv_parse_rt_stage(struct radv_device *device, const 
VkPipelineShaderStageCreat
 
radv_pipeline_stage_init(sinfo, pipeline_layout, key, _stage);
 
-   nir_shader *shader = radv_shader_spirv_to_nir(device, _stage, key, 
false);
+   nir_shader *shader = radv_shader_spirv_to_nir(device, _stage, NULL, 
false);
 
NIR_PASS(_, shader, nir_lower_vars_to_explicit_types, nir_var_function_temp 
| nir_var_shader_call_data,
 glsl_get_natural_size_align_bytes);
diff --git a/src/amd/vulkan/radv_pipeline_compute.c 
b/src/amd/vulkan/radv_pipeline_compute.c
index 1c4bf9d4946..6d3ace8c13e 100644
--- a/src/amd/vulkan/radv_pipeline_compute.c
+++ b/src/amd/vulkan/radv_pipeline_compute.c
@@ -133,13 +133,13 @@ radv_compute_pipeline_init(const struct radv_device 
*device, struct radv_compute
 
 static struct radv_shader *
 radv_compile_cs(struct radv_device *device, struct vk_pipeline_cache *cache, 
struct radv_shader_stage *cs_stage,
-const struct radv_pipeline_key *pipeline_key, bool 
keep_executable_info, bool keep_statistic_info,
-bool is_internal, struct radv_shader_binary **cs_binary)
+bool keep_executable_info, bool keep_statistic_info, bool 
is_internal,
+struct radv_shader_binary **cs_binary)
 {
struct radv_shader *cs_shader;
 
/* Compile SPIR-V shader to NIR. */
-   cs_stage->nir = radv_shader_spirv_to_nir(device, cs_stage, pipeline_key, 
is_internal);
+   cs_stage->nir = radv_shader_spirv_to_nir(device, cs_stage, NULL, 
is_internal);
 
radv_optimize_nir(cs_stage->nir, cs_stage->key.optimisations_disabled);
 
@@ -148,17 +148,16 @@ radv_compile_cs(struct radv_device *device, struct 
vk_pipeline_cache *cache, str
 
/* Run the shader info pass. */
radv_nir_shader_info_init(cs_stage->stage, MESA_SHADER_NONE, 
_stage->info);
-   radv_nir_shader_info_pass(device, cs_stage->nir, _stage->layout, 
_stage->key, pipeline_key,
- RADV_PIPELINE_COMPUTE, false, _stage->info);
+   radv_nir_shader_info_pass(device, cs_stage->nir, _stage->layout, 
_stage->key, NULL, RADV_PIPELINE_COMPUTE,
+ false, _stage->info);
 
-   radv_declare_shader_args(device, pipeline_key, _stage->info, 
MESA_SHADER_COMPUTE, MESA_SHADER_NONE,
-_stage->args);
+   radv_declare_shader_args(device, NULL, _stage->info, 
MESA_SHADER_COMPUTE, MESA_SHADER_NONE, _stage->args);
 
cs_stage->info.user_sgprs_locs = cs_stage->args.user_sgprs_locs;
cs_stage->info.inline_push_constant_mask = 
cs_stage->args.ac.inline_push_const_mask;
 
/* Postprocess NIR. */
-   radv_postprocess_nir(device, pipeline_key, cs_stage);
+   radv_postprocess_nir(device, NULL, cs_stage);
 
if (radv_can_dump_shader(device, cs_stage->nir, false))
   nir_print_shader(cs_stage->nir, stderr);
@@ -166,8 +165,8 @@ radv_compile_cs(struct radv_device *device, struct 
vk_pipeline_cache *cache, str
/* Compile NIR shader to AMD assembly. */
bool dump_shader = radv_can_dump_shader(device, cs_stage->nir, false);
 
-   *cs_binary = radv_shader_nir_to_asm(device, cs_stage, _stage->nir, 1, 
pipeline_key, keep_executable_info,
-   keep_statistic_info);
+   *cs_binary =
+  radv_shader_nir_to_asm(device, cs_stage, _stage->nir, 1, NULL, 
keep_executable_info, keep_statistic_info);
 
cs_shader = radv_shader_create(device, cache, *cs_binary, 
keep_executable_info || dump_shader);
 
@@ -222,9 +221,8 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline 
*pipeline, struct rad
 
int64_t stage_start = os_time_get_nano();
 
-   pipeline->base.shaders[MESA_SHADER_COMPUTE] =
-  radv_compile_cs(device, cache, _stage, pipeline_key, 
keep_executable_info, keep_statistic_info,
-  pipeline->base.is_internal, _binary);
+   pipeline->base.shaders[MESA_SHADER_COMPUTE] = radv_compile_cs(
+  device, cache, _stage, keep_executable_info, keep_statistic_info, 
pipeline->base.is_internal, 

Mesa (main): radv: add radv_shader_stage_key to radv_shader_stage

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 28e330c24536d353ec25be7b78ce20c7770d1e23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28e330c24536d353ec25be7b78ce20c7770d1e23

Author: Samuel Pitoiset 
Date:   Tue Jan  9 14:27:16 2024 +0100

radv: add radv_shader_stage_key to radv_shader_stage

For storing the per-stage key information like robustness etc. This
will fit well with ESO as well.

For pipelines, they are copied from radv_pipeline_key, similarly to
the radv_pipeline_layout/radv_shader_layout pair.

This will also allow us to kill radv_pipeline_key for compute/rt
pipelines.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir_rt_shader.c |  2 +-
 src/amd/vulkan/radv_pipeline.c  | 11 ++-
 src/amd/vulkan/radv_pipeline_compute.c  |  2 +-
 src/amd/vulkan/radv_pipeline_graphics.c | 11 +++
 src/amd/vulkan/radv_pipeline_rt.c   |  5 +++--
 src/amd/vulkan/radv_private.h   |  6 +-
 6 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c 
b/src/amd/vulkan/nir/radv_nir_rt_shader.c
index d78dfecbae3..f22d15dc07b 100644
--- a/src/amd/vulkan/nir/radv_nir_rt_shader.c
+++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c
@@ -813,7 +813,7 @@ radv_parse_rt_stage(struct radv_device *device, const 
VkPipelineShaderStageCreat
 {
struct radv_shader_stage rt_stage;
 
-   radv_pipeline_stage_init(sinfo, pipeline_layout, _stage);
+   radv_pipeline_stage_init(sinfo, pipeline_layout, key, _stage);
 
nir_shader *shader = radv_shader_spirv_to_nir(device, _stage, key, 
false);
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e14b7a75d06..4eac4fbf839 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -212,9 +212,17 @@ radv_generate_pipeline_key(const struct radv_device 
*device, const VkPipelineSha
return key;
 }
 
+void
+radv_shader_stage_key_init(const struct radv_pipeline_key *pipeline_key, 
gl_shader_stage stage,
+   struct radv_shader_stage_key *stage_key)
+{
+   *stage_key = pipeline_key->stage_info[stage];
+}
+
 void
 radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo,
- const struct radv_pipeline_layout *pipeline_layout, 
struct radv_shader_stage *out_stage)
+ const struct radv_pipeline_layout *pipeline_layout,
+ const struct radv_pipeline_key *pipeline_key, struct 
radv_shader_stage *out_stage)
 {
const VkShaderModuleCreateInfo *minfo = vk_find_struct_const(sinfo->pNext, 
SHADER_MODULE_CREATE_INFO);
const VkPipelineShaderStageModuleIdentifierCreateInfoEXT *iinfo =
@@ -245,6 +253,7 @@ radv_pipeline_stage_init(const 
VkPipelineShaderStageCreateInfo *sinfo,
}
 
radv_shader_layout_init(pipeline_layout, out_stage->stage, 
_stage->layout);
+   radv_shader_stage_key_init(pipeline_key, out_stage->stage, _stage->key);
 
vk_pipeline_hash_shader_stage(sinfo, NULL, out_stage->shader_sha1);
 }
diff --git a/src/amd/vulkan/radv_pipeline_compute.c 
b/src/amd/vulkan/radv_pipeline_compute.c
index e4ab79c48c7..1255e935b1f 100644
--- a/src/amd/vulkan/radv_pipeline_compute.c
+++ b/src/amd/vulkan/radv_pipeline_compute.c
@@ -202,7 +202,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline 
*pipeline, struct rad
 
int64_t pipeline_start = os_time_get_nano();
 
-   radv_pipeline_stage_init(pStage, pipeline_layout, _stage);
+   radv_pipeline_stage_init(pStage, pipeline_layout, pipeline_key, _stage);
 
radv_hash_shaders(device, hash, _stage, 1, pipeline_layout, 
pipeline_key);
 
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c 
b/src/amd/vulkan/radv_pipeline_graphics.c
index 66c10fc9322..3235ebca881 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -2291,6 +2291,7 @@ radv_pipeline_retain_shaders(struct radv_retained_shaders 
*retained_shaders, str
 
 static void
 radv_pipeline_import_retained_shaders(const struct radv_device *device, struct 
radv_graphics_pipeline *pipeline,
+  const struct radv_pipeline_key 
*pipeline_key,
   struct radv_graphics_lib_pipeline *lib, 
struct radv_shader_stage *stages)
 {
struct radv_retained_shaders *retained_shaders = >retained_shaders;
@@ -2304,7 +2305,7 @@ radv_pipeline_import_retained_shaders(const struct 
radv_device *device, struct r
   if (!(shader_stage_to_pipeline_library_flags(sinfo->stage) & 
lib->lib_flags))
  continue;
 
-  radv_pipeline_stage_init(sinfo, >layout, [s]);
+  radv_pipeline_stage_init(sinfo, >layout, pipeline_key, [s]);
}
 
/* Import the NIR shaders (after SPIRV->NIR). */
@@ -2326,6 +2327,7 @@ radv_pipeline_import_retained_shaders(const struct 
radv_device *device, struct r
   memcpy(stages[s].shader_sha1, 

Mesa (main): radv/nir: remove useless struct for nir_shader typedef

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 138ce72860be3815eee81a39014382c8cfd225c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=138ce72860be3815eee81a39014382c8cfd225c5

Author: Samuel Pitoiset 
Date:   Tue Jan  9 13:58:43 2024 +0100

radv/nir: remove useless struct for nir_shader typedef

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h
index 3e75845e557..c49657dad46 100644
--- a/src/amd/vulkan/nir/radv_nir.h
+++ b/src/amd/vulkan/nir/radv_nir.h
@@ -51,7 +51,7 @@ void radv_nir_lower_abi(nir_shader *shader, enum 
amd_gfx_level gfx_level, const
 
 bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader);
 
-bool radv_nir_lower_ray_queries(struct nir_shader *shader, struct radv_device 
*device);
+bool radv_nir_lower_ray_queries(nir_shader *shader, struct radv_device 
*device);
 
 bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct 
radv_shader_stage *vs_stage,
   const struct radv_pipeline_key *pl_key, const 
struct radeon_info *rad_info);

Mesa (main): radv: remove one unused parameter in radv_fill_shader_info_ngg()

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: d74150fc66131f23e2a54dd4920fa33d6604f13c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d74150fc66131f23e2a54dd4920fa33d6604f13c

Author: Samuel Pitoiset 
Date:   Thu Jan 11 14:48:34 2024 +0100

radv: remove one unused parameter in radv_fill_shader_info_ngg()

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline_graphics.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline_graphics.c 
b/src/amd/vulkan/radv_pipeline_graphics.c
index 35345680b43..66c10fc9322 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -1963,8 +1963,8 @@ radv_generate_graphics_pipeline_key(const struct 
radv_device *device, const stru
 }
 
 static void
-radv_fill_shader_info_ngg(struct radv_device *device, const struct 
radv_pipeline_key *pipeline_key,
-  struct radv_shader_stage *stages, 
VkShaderStageFlagBits active_nir_stages)
+radv_fill_shader_info_ngg(struct radv_device *device, struct radv_shader_stage 
*stages,
+  VkShaderStageFlagBits active_nir_stages)
 {
if (device->cache_key.use_ngg) {
   if (stages[MESA_SHADER_TESS_CTRL].nir) {
@@ -2487,7 +2487,7 @@ radv_graphics_shaders_compile(struct radv_device *device, 
struct vk_pipeline_cac
}
 
/* Determine if shaders uses NGG before linking because it's needed for 
some NIR pass. */
-   radv_fill_shader_info_ngg(device, pipeline_key, stages, active_nir_stages);
+   radv_fill_shader_info_ngg(device, stages, active_nir_stages);
 
if (stages[MESA_SHADER_GEOMETRY].nir) {
   unsigned nir_gs_flags = nir_lower_gs_intrinsics_per_stream;

Mesa (main): radv: remove unecessary radv_nir_compiler_options::key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: ea89328fb41a0ebc497e8045e468070ea8af5931
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea89328fb41a0ebc497e8045e468070ea8af5931

Author: Samuel Pitoiset 
Date:   Thu Jan 11 13:47:15 2024 +0100

radv: remove unecessary radv_nir_compiler_options::key

This is no longer useful.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_shader.c | 5 +
 src/amd/vulkan/radv_shader.h | 1 -
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 4564d6b4256..22172813bdc 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -2413,9 +2413,6 @@ radv_fill_nir_compiler_options(struct 
radv_nir_compiler_options *options, struct
const struct radv_pipeline_key *key, bool 
should_use_wgp, bool can_dump_shader,
bool is_meta_shader, bool keep_shader_info, 
bool keep_statistic_info)
 {
-   if (key)
-  options->key = *key;
-
/* robust_buffer_access_llvm here used by LLVM only, pipeline robustness is 
not exposed there. */
options->robust_buffer_access_llvm = device->buffer_robustness >= 
RADV_BUFFER_ROBUSTNESS_1;
options->wgp_mode = should_use_wgp;
@@ -2425,7 +2422,7 @@ radv_fill_nir_compiler_options(struct 
radv_nir_compiler_options *options, struct
options->record_ir = keep_shader_info;
options->record_stats = keep_statistic_info;
options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
-   options->enable_mrt_output_nan_fixup = 
options->key.ps.epilog.enable_mrt_output_nan_fixup;
+   options->enable_mrt_output_nan_fixup = key ? 
key->ps.epilog.enable_mrt_output_nan_fixup : false;
 }
 
 static void
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 1ba3fd4e759..09918ac6ae0 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -170,7 +170,6 @@ struct radv_pipeline_key {
 };
 
 struct radv_nir_compiler_options {
-   struct radv_pipeline_key key;
bool robust_buffer_access_llvm;
bool dump_shader;
bool dump_preoptir;

Mesa (main): radv: add vertex_robustness1 to radv_shader_stage_key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b888677dcfe0d522189d05099d9d006c9c88739b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b888677dcfe0d522189d05099d9d006c9c88739b

Author: Samuel Pitoiset 
Date:   Thu Jan 11 16:50:23 2024 +0100

radv: add vertex_robustness1 to radv_shader_stage_key

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline.c| 2 +-
 src/amd/vulkan/radv_shader.h  | 3 +--
 src/amd/vulkan/radv_shader_info.c | 6 +++---
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a515f063758..8a9309ecd22 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -206,7 +206,7 @@ radv_generate_pipeline_key(const struct radv_device 
*device, const VkPipelineSha
   if (uniform_robustness >= RADV_BUFFER_ROBUSTNESS_2)
  key.stage_info[stage].uniform_robustness2 = 1;
   if (stage == MESA_SHADER_VERTEX && vertex_robustness >= 
RADV_BUFFER_ROBUSTNESS_1)
- key.vertex_robustness1 = 1u;
+ key.stage_info[stage].vertex_robustness1 = 1u;
}
 
key.keep_statistic_info = radv_pipeline_capture_shader_stats(device, flags);
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index a4be370817b..c254c442e18 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -92,6 +92,7 @@ struct radv_shader_stage_key {
 
uint8_t storage_robustness2 : 1;
uint8_t uniform_robustness2 : 1;
+   uint8_t vertex_robustness1 : 1;
 
uint8_t optimisations_disabled : 1;
 };
@@ -125,8 +126,6 @@ struct radv_pipeline_key {
uint32_t enable_remove_point_size : 1;
uint32_t unknown_rast_prim : 1;
 
-   uint32_t vertex_robustness1 : 1;
-
uint32_t keep_statistic_info : 1;
 
/* Pipeline shader version (up to 8) to force re-compilation when 
RADV_BUILD_ID_OVERRIDE is enabled. */
diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index c32004aa5e1..7d54db7fb58 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -417,7 +417,7 @@ gather_info_input_decl_vs(const nir_shader *nir, unsigned 
location, const struct
 
 static void
 gather_shader_info_vs(struct radv_device *device, const nir_shader *nir, const 
struct radv_pipeline_key *pipeline_key,
-  struct radv_shader_info *info)
+  const struct radv_shader_stage_key *stage_key, struct 
radv_shader_info *info)
 {
if (pipeline_key->vs.has_prolog && nir->info.inputs_read) {
   info->vs.has_prolog = true;
@@ -425,7 +425,7 @@ gather_shader_info_vs(struct radv_device *device, const 
nir_shader *nir, const s
}
 
/* Use per-attribute vertex descriptors to prevent faults and for correct 
bounds checking. */
-   info->vs.use_per_attribute_vb_descs = pipeline_key->vertex_robustness1 || 
info->vs.dynamic_inputs;
+   info->vs.use_per_attribute_vb_descs = stage_key->vertex_robustness1 || 
info->vs.dynamic_inputs;
 
/* We have to ensure consistent input register assignments between the main 
shader and the
 * prolog.
@@ -1211,7 +1211,7 @@ radv_nir_shader_info_pass(struct radv_device *device, 
const struct nir_shader *n
   gather_shader_info_tcs(device, nir, pipeline_key, info);
   break;
case MESA_SHADER_VERTEX:
-  gather_shader_info_vs(device, nir, pipeline_key, info);
+  gather_shader_info_vs(device, nir, pipeline_key, stage_key, info);
   break;
case MESA_SHADER_MESH:
   gather_shader_info_mesh(device, nir, pipeline_key, info);

Mesa (main): radv: remove unused lower_rt_instruction_monolithic_state::key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6e7018e74d6e674967f18363fbceff5881d3ad11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e7018e74d6e674967f18363fbceff5881d3ad11

Author: Samuel Pitoiset 
Date:   Thu Jan 11 16:25:14 2024 +0100

radv: remove unused lower_rt_instruction_monolithic_state::key

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir_rt_shader.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/amd/vulkan/nir/radv_nir_rt_shader.c 
b/src/amd/vulkan/nir/radv_nir_rt_shader.c
index f22d15dc07b..8a8b3a08236 100644
--- a/src/amd/vulkan/nir/radv_nir_rt_shader.c
+++ b/src/amd/vulkan/nir/radv_nir_rt_shader.c
@@ -1544,7 +1544,6 @@ radv_build_traversal_shader(struct radv_device *device, 
struct radv_ray_tracing_
 struct lower_rt_instruction_monolithic_state {
struct radv_device *device;
struct radv_ray_tracing_pipeline *pipeline;
-   const struct radv_pipeline_key *key;
const VkRayTracingPipelineCreateInfoKHR *pCreateInfo;
 
struct rt_variables *vars;

Mesa (main): radv: move radv_pipeline_key::mesh_fast_launch_2 to the per-device cache key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: cff2a3aafcc449d95c3405b21938c6225a67c9ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cff2a3aafcc449d95c3405b21938c6225a67c9ef

Author: Samuel Pitoiset 
Date:   Thu Jan 11 13:56:09 2024 +0100

radv: move radv_pipeline_key::mesh_fast_launch_2 to the per-device cache key

This is a global thing.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_device.c   | 1 +
 src/amd/vulkan/radv_pipeline.c | 5 -
 src/amd/vulkan/radv_private.h  | 1 +
 src/amd/vulkan/radv_shader.h   | 1 -
 4 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 261cf4f6856..cbba5f54d4c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -723,6 +723,7 @@ radv_device_init_cache_key(struct radv_device *device)
key->image_2d_view_of_3d = device->image_2d_view_of_3d && 
device->physical_device->rad_info.gfx_level == GFX9;
key->invariant_geom = !!(device->instance->debug_flags & 
RADV_DEBUG_INVARIANT_GEOM);
key->lower_discard_to_demote = !!(device->instance->debug_flags & 
RADV_DEBUG_DISCARD_TO_DEMOTE);
+   key->mesh_fast_launch_2 = device->mesh_fast_launch_2;
key->mesh_shader_queries = device->mesh_shader_queries;
key->no_fmask = !!(device->instance->debug_flags & RADV_DEBUG_NO_FMASK);
key->no_rt = !!(device->instance->debug_flags & RADV_DEBUG_NO_RT);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index ee080aa2322..e14b7a75d06 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -207,11 +207,6 @@ radv_generate_pipeline_key(const struct radv_device 
*device, const VkPipelineSha
  key.vertex_robustness1 = 1u;
}
 
-   for (uint32_t i = 0; i < num_stages; i++) {
-  if (stages[i].stage == VK_SHADER_STAGE_MESH_BIT_EXT && 
device->mesh_fast_launch_2)
- key.mesh_fast_launch_2 = 1u;
-   }
-
key.keep_statistic_info = radv_pipeline_capture_shader_stats(device, flags);
 
return key;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 814c1ec1867..3c70729ff21 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -890,6 +890,7 @@ struct radv_device_cache_key {
uint32_t image_2d_view_of_3d : 1;
uint32_t invariant_geom : 1;
uint32_t lower_discard_to_demote : 1;
+   uint32_t mesh_fast_launch_2 : 1;
uint32_t mesh_shader_queries : 1;
uint32_t no_fmask : 1;
uint32_t no_rt : 1;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index c4ceed01d1d..bc74781f3d7 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -125,7 +125,6 @@ struct radv_pipeline_key {
uint32_t unknown_rast_prim : 1;
 
uint32_t vertex_robustness1 : 1;
-   uint32_t mesh_fast_launch_2 : 1;
 
uint32_t keep_statistic_info : 1;
 

Mesa (main): radv: add optimisations_disabled to radv_shader_stage_key

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6e1a73a53d1640c1732b4566683b8455143b0aa9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1a73a53d1640c1732b4566683b8455143b0aa9

Author: Samuel Pitoiset 
Date:   Tue Jan  9 15:35:43 2024 +0100

radv: add optimisations_disabled to radv_shader_stage_key

At some point, we will probably have a VK_SHADER_CREATE_xxx flag
matching the pipeline one. So, I think it's more like a per-shader
field. It can also be useful to disable optimisations per stage when
debugging.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_aco_shader_info.h   |  4 ++--
 src/amd/vulkan/radv_pipeline.c  | 20 +++-
 src/amd/vulkan/radv_pipeline_compute.c  |  2 +-
 src/amd/vulkan/radv_pipeline_graphics.c | 33 +
 src/amd/vulkan/radv_pipeline_rt.c   |  4 ++--
 src/amd/vulkan/radv_shader.c| 27 ---
 src/amd/vulkan/radv_shader.h|  3 ++-
 7 files changed, 51 insertions(+), 42 deletions(-)

diff --git a/src/amd/vulkan/radv_aco_shader_info.h 
b/src/amd/vulkan/radv_aco_shader_info.h
index 05cc681b03b..2b6be698d42 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -126,7 +126,7 @@ radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info 
*aco_info, const struct
 
 static inline void
 radv_aco_convert_opts(struct aco_compiler_options *aco_info, const struct 
radv_nir_compiler_options *radv,
-  const struct radv_shader_args *radv_args)
+  const struct radv_shader_args *radv_args, const struct 
radv_shader_stage_key *stage_key)
 {
ASSIGN_FIELD(dump_shader);
ASSIGN_FIELD(dump_preoptir);
@@ -139,7 +139,7 @@ radv_aco_convert_opts(struct aco_compiler_options 
*aco_info, const struct radv_n
ASSIGN_FIELD(debug.private_data);
aco_info->is_opengl = false;
aco_info->load_grid_size_from_user_sgpr = 
radv_args->load_grid_size_from_user_sgpr;
-   aco_info->optimisations_disabled = radv->key.optimisations_disabled;
+   aco_info->optimisations_disabled = stage_key->optimisations_disabled;
aco_info->gfx_level = radv->info->gfx_level;
aco_info->family = radv->info->family;
aco_info->address32_hi = radv->info->address32_hi;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 3e5cde9c794..a515f063758 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -151,8 +151,10 @@ radv_generate_pipeline_key(const struct radv_device 
*device, const VkPipelineSha
 
memset(, 0, sizeof(key));
 
-   if (flags & VK_PIPELINE_CREATE_2_DISABLE_OPTIMIZATION_BIT_KHR)
-  key.optimisations_disabled = 1;
+   for (unsigned i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) {
+  if (flags & VK_PIPELINE_CREATE_2_DISABLE_OPTIMIZATION_BIT_KHR)
+ key.stage_info[i].optimisations_disabled = 1;
+   }
 
for (unsigned i = 0; i < num_stages; ++i) {
   const VkPipelineShaderStageCreateInfo *const stage = [i];
@@ -476,7 +478,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
assert(stage->info.wave_size && stage->info.workgroup_size);
 
if (stage->stage == MESA_SHADER_FRAGMENT) {
-  if (!pipeline_key->optimisations_disabled) {
+  if (!stage->key.optimisations_disabled) {
  NIR_PASS(_, stage->nir, nir_opt_cse);
   }
   NIR_PASS(_, stage->nir, radv_nir_lower_fs_intrinsics, stage, 
pipeline_key);
@@ -492,7 +494,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
 * thus a cheaper and likely to fail check is run first.
 */
if (nir_has_non_uniform_access(stage->nir, lower_non_uniform_access_types)) 
{
-  if (!pipeline_key->optimisations_disabled) {
+  if (!stage->key.optimisations_disabled) {
  NIR_PASS(_, stage->nir, nir_opt_non_uniform_access);
   }
 
@@ -525,7 +527,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
if (stage->key.storage_robustness2)
   vectorize_opts.robust_modes |= nir_var_mem_ssbo;
 
-   if (!pipeline_key->optimisations_disabled) {
+   if (!stage->key.optimisations_disabled) {
   progress = false;
   NIR_PASS(progress, stage->nir, nir_opt_load_store_vectorize, 
_opts);
   if (progress) {
@@ -569,7 +571,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
 
NIR_PASS_V(stage->nir, radv_nir_apply_pipeline_layout, device, stage);
 
-   if (!pipeline_key->optimisations_disabled) {
+   if (!stage->key.optimisations_disabled) {
   NIR_PASS(_, stage->nir, nir_opt_shrink_vectors);
}
 
@@ -577,7 +579,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
 
nir_move_options sink_opts = nir_move_const_undef | nir_move_copies;
 
-   if (!pipeline_key->optimisations_disabled) {
+   if 

Mesa (main): radv/nir: pass radv_shader_stage to some radv_nir_xxx() functions

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 18349692d0e2726dcd0c441c067f2995989ce19b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18349692d0e2726dcd0c441c067f2995989ce19b

Author: Samuel Pitoiset 
Date:   Tue Jan  9 13:57:42 2024 +0100

radv/nir: pass radv_shader_stage to some radv_nir_xxx() functions

Instead of passing separate parameters for args, layout, info etc.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/nir/radv_nir.h   |  9 -
 src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c |  9 -
 src/amd/vulkan/nir/radv_nir_lower_abi.c | 10 +-
 src/amd/vulkan/radv_pipeline.c  |  4 ++--
 src/amd/vulkan/radv_pipeline_graphics.c |  4 ++--
 5 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h
index a93678dc214..3e75845e557 100644
--- a/src/amd/vulkan/nir/radv_nir.h
+++ b/src/amd/vulkan/nir/radv_nir.h
@@ -43,12 +43,11 @@ struct radv_shader_args;
 struct radv_shader_layout;
 struct radv_device;
 
-void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device 
*device, const struct radv_shader_info *info,
-const struct radv_shader_args *args, const 
struct radv_shader_layout *layout);
+void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device 
*device,
+const struct radv_shader_stage *stage);
 
-void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, 
const struct radv_shader_info *info,
-const struct radv_shader_args *args, const struct 
radv_pipeline_key *pl_key,
-uint32_t address32_hi);
+void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, 
const struct radv_shader_stage *stage,
+const struct radv_pipeline_key *pl_key, uint32_t 
address32_hi);
 
 bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader);
 
diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c 
b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
index 7428b38eade..602c2b75d24 100644
--- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
+++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
@@ -499,8 +499,7 @@ apply_layout_to_tex(nir_builder *b, apply_layout_state 
*state, nir_tex_instr *te
 }
 
 void
-radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, 
const struct radv_shader_info *info,
-   const struct radv_shader_args *args, const 
struct radv_shader_layout *layout)
+radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, 
const struct radv_shader_stage *stage)
 {
apply_layout_state state = {
   .gfx_level = device->physical_device->rad_info.gfx_level,
@@ -509,9 +508,9 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct 
radv_device *device, c
   .has_image_load_dcc_bug = 
device->physical_device->rad_info.has_image_load_dcc_bug,
   .disable_tg4_trunc_coord =
  !device->physical_device->rad_info.conformant_trunc_coord && 
!device->disable_trunc_coord,
-  .args = args,
-  .info = info,
-  .layout = layout,
+  .args = >args,
+  .info = >info,
+  .layout = >layout,
};
 
nir_builder b;
diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c 
b/src/amd/vulkan/nir/radv_nir_lower_abi.c
index bd94770c30a..97d916c9966 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c
@@ -547,18 +547,18 @@ load_gsvs_ring(nir_builder *b, lower_abi_state *s, 
unsigned stream_id)
 }
 
 void
-radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const 
struct radv_shader_info *info,
-   const struct radv_shader_args *args, const struct 
radv_pipeline_key *pl_key, uint32_t address32_hi)
+radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const 
struct radv_shader_stage *stage,
+   const struct radv_pipeline_key *pl_key, uint32_t 
address32_hi)
 {
lower_abi_state state = {
   .gfx_level = gfx_level,
-  .info = info,
-  .args = args,
+  .info = >info,
+  .args = >args,
   .pl_key = pl_key,
   .address32_hi = address32_hi,
};
 
-   if (shader->info.stage == MESA_SHADER_GEOMETRY && !info->is_ngg) {
+   if (shader->info.stage == MESA_SHADER_GEOMETRY && !stage->info.is_ngg) {
   nir_function_impl *impl = nir_shader_get_entrypoint(shader);
 
   nir_builder b = nir_builder_at(nir_before_impl(impl));
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2699eaa792f..ee080aa2322 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -563,7 +563,7 @@ radv_postprocess_nir(struct radv_device *device, const 
struct radv_pipeline_key
if 

Mesa (main): intel/decoder: make vertex data decoding optional

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 7107ed55c01840c7bea21c01f8d3e3c9b10fe9c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7107ed55c01840c7bea21c01f8d3e3c9b10fe9c2

Author: Lionel Landwerlin 
Date:   Sun Jan 14 11:00:44 2024 +0200

intel/decoder: make vertex data decoding optional

When capturing INTEL_DEBUG=capture-all and the application has like
1Gb of vertex data, you might not want to actually decode it when
looking at the error state.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/common/intel_batch_decoder.c | 4 +++-
 src/intel/common/intel_decoder.h   | 5 -
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/intel/common/intel_batch_decoder.c 
b/src/intel/common/intel_batch_decoder.c
index ba37f938030..987e9d0b514 100644
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -37,6 +37,7 @@ static const struct debug_control debug_control[] = {
{ "floats", INTEL_BATCH_DECODE_FLOATS },
{ "surfaces",   INTEL_BATCH_DECODE_SURFACES },
{ "accumulate", INTEL_BATCH_DECODE_ACCUMULATE },
+   { "vb-data",INTEL_BATCH_DECODE_VB_DATA },
{ NULL,0 }
 };
 
@@ -580,7 +581,8 @@ handle_3dstate_vertex_buffers(struct intel_batch_decode_ctx 
*ctx,
  if (vb.map == 0 || vb_size == 0)
 continue;
 
- ctx_print_buffer(ctx, vb, vb_size, pitch, ctx->max_vbo_decoded_lines);
+ if (ctx->flags & INTEL_BATCH_DECODE_VB_DATA)
+ctx_print_buffer(ctx, vb, vb_size, pitch, 
ctx->max_vbo_decoded_lines);
 
  vb.map = NULL;
  vb_size = 0;
diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h
index eb821a61091..4210438eb5f 100644
--- a/src/intel/common/intel_decoder.h
+++ b/src/intel/common/intel_decoder.h
@@ -231,6 +231,8 @@ enum intel_batch_decode_flags {
 * - COMPUTE_WALKER
 */
INTEL_BATCH_DECODE_ACCUMULATE  = (1 << 6),
+   /** Print vertex buffer data */
+   INTEL_BATCH_DECODE_VB_DATA = (1 << 7),
 };
 
 #define INTEL_BATCH_DECODE_DEFAULT_FLAGS \
@@ -238,7 +240,8 @@ enum intel_batch_decode_flags {
 INTEL_BATCH_DECODE_OFFSETS | \
 INTEL_BATCH_DECODE_FLOATS |  \
 INTEL_BATCH_DECODE_SURFACES |\
-INTEL_BATCH_DECODE_SAMPLERS)
+INTEL_BATCH_DECODE_SAMPLERS |\
+INTEL_BATCH_DECODE_VB_DATA)
 
 struct intel_batch_decode_bo {
uint64_t addr;

Mesa (main): intel/genxml: add CCS_INSTDONE register

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 547c2f3d3f9d736f5d3bdb487faf05fd122ee5ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=547c2f3d3f9d736f5d3bdb487faf05fd122ee5ca

Author: Lionel Landwerlin 
Date:   Wed Dec  7 12:51:35 2022 +0200

intel/genxml: add CCS_INSTDONE register

Gives us the ability to check whether the compute command streamer is
hung.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/genxml/gen125.xml | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 3d5fe2ff925..9b3695b449d 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -2128,6 +2128,12 @@
   
 
   
+  
+
+
+
+
+  
   
 
 

Mesa (main): intel/hang_viewer: add aux-tt view

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 7e111268f12fa5b8abda8c3297211a25387592cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e111268f12fa5b8abda8c3297211a25387592cb

Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:57:29 2024 +0200

intel/hang_viewer: add aux-tt view

Allows you to visualize the AUX-TT.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/tools/intel_hang_viewer.cpp | 145 --
 1 file changed, 121 insertions(+), 24 deletions(-)

diff --git a/src/intel/tools/intel_hang_viewer.cpp 
b/src/intel/tools/intel_hang_viewer.cpp
index 680e771b122..eca20044ef6 100644
--- a/src/intel/tools/intel_hang_viewer.cpp
+++ b/src/intel/tools/intel_hang_viewer.cpp
@@ -118,6 +118,9 @@ static struct Context {
/* Map hang file in RW for edition */
bool edit = false;
 
+   /* AUX-TT */
+   uint64_t aux_tt_addr = 0;
+
struct intel_device_info devinfo;
struct intel_spec *spec = NULL;
struct brw_isa_info isa;
@@ -142,6 +145,15 @@ static struct Context {
 
 thread_local ImGuiContext* __MesaImGui;
 
+hang_bo *find_bo(uint64_t addr)
+{
+   for (auto  : context.bos) {
+  if (addr >= bo.offset && addr < (bo.offset + bo.size))
+ return 
+   }
+   return NULL;
+}
+
 /**/
 
 static uint8_t
@@ -204,21 +216,19 @@ public:
   snprintf(m_name, sizeof(m_name),
"%s (0x%" PRIx64 ")##%p", m_description.c_str(), m_address, 
this);
 
-  for (auto  : context.bos) {
- if (address >= bo.offset &&
- address < (bo.offset + bo.size)) {
-char *shader_txt = NULL;
-size_t shader_txt_size = 0;
-FILE *f = open_memstream(_txt, _txt_size);
-if (f) {
-   intel_disassemble(,
- (const uint8_t *) bo.map +
- (address - bo.offset), 0, f);
-   fclose(f);
-}
-
-m_shader = std::string(shader_txt);
+  hang_bo *bo = find_bo(address);
+  if (bo != NULL) {
+ char *shader_txt = NULL;
+ size_t shader_txt_size = 0;
+ FILE *f = open_memstream(_txt, _txt_size);
+ if (f) {
+intel_disassemble(,
+  (const uint8_t *) bo->map +
+  (address - bo->offset), 0, f);
+fclose(f);
  }
+
+ m_shader = std::string(shader_txt);
   }
}
 
@@ -232,6 +242,86 @@ public:
void destroy() {}
 };
 
+class aux_tt_window : public window {
+public:
+   aux_tt_window(uint64_t l3_addr)
+  : m_l3_addr(l3_addr)
+  , m_bo(find_bo(l3_addr)) {
+  snprintf(m_name, sizeof(m_name), "AUX TT##%p", this);
+   }
+
+   void display() {
+  ImGui::BeginChild(ImGui::GetID("##toplevel"));
+  if (m_bo != NULL)
+ display_level(3, m_l3_addr, 0);
+  else
+ ImGui::Text("AUX table buffer not found: 0x%" PRIx64,
+ m_l3_addr);
+  ImGui::EndChild();
+   }
+
+   void destroy() {}
+
+private:
+   void display_level(int level, uint64_t table_addr, uint64_t base_addr) {
+  assert(level >= 1 && level <= 3);
+
+  const hang_bo *bo =
+ table_addr == m_l3_addr ? m_bo : find_bo(table_addr);
+  if (bo == NULL) {
+ ImGui::Text("level %u not found addr=0x%016" PRIx64,
+ level, table_addr);
+ return;
+  }
+
+  static struct {
+ uint32_t top;
+ uint32_t bottom;
+  } levels[4] = {
+ {  0,  0, },
+ { 23, 16, },
+ { 35, 24, },
+ { 47, 36, },
+  };
+
+  const uint64_t *entries =
+ (const uint64_t *)((const uint8_t *)bo->map + (table_addr - 
bo->offset));
+
+  if (level == 1) {
+ uint32_t n_entries = context.devinfo.verx10 == 125 ? 16 : 256;
+ for (uint32_t i = 0; i < n_entries; i++) {
+uint64_t addr = entries[i] & 0xff00ull;
+ImGui::Text("entry%04u: addr=0x%012" PRIx64 " entry=0x%012" PRIx64
+" range=0x%012" PRIx64 "-0x%012" PRIx64,
+i, addr, entries[i],
+base_addr + (uint64_t)i << levels[level].bottom,
+base_addr + (uint64_t)i << levels[level].bottom);
+ }
+  } else {
+ for (uint32_t i = 0; i < 4096; i++) {
+uint64_t entry_addr = base_addr + (uint64_t)i << 
levels[level].bottom;
+uint64_t addr = entries[i] & 0x8000ull;
+bool valid = (entries[i] & 0x1) != 0;
+if (valid &&
+ImGui::TreeNodeEx(
+   (void *)[i],
+   ImGuiTreeNodeFlags_Framed,
+   "entry%04u: addr=0x%012" PRIx64 " entry=0x%012" PRIx64
+   " range=0x%012" PRIx64 "-0x%012" PRIx64,
+   i, addr, entries[i],
+   entry_addr, entry_addr)) {
+ 

Mesa (main): intel/decoder: don't ignore BT entries at offset 0

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f78fac623a1043fc9f42048651aca77f1cca8644
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f78fac623a1043fc9f42048651aca77f1cca8644

Author: Lionel Landwerlin 
Date:   Sun Jan 14 11:00:01 2024 +0200

intel/decoder: don't ignore BT entries at offset 0

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/common/intel_batch_decoder.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/intel/common/intel_batch_decoder.c 
b/src/intel/common/intel_batch_decoder.c
index 987e9d0b514..126a6e946c3 100644
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -352,8 +352,7 @@ dump_binding_table(struct intel_batch_decode_ctx *ctx,
 
const uint32_t *pointers = bind_bo.map;
for (int i = 0; i < count; i++) {
-  if (((uintptr_t)[i] >= ((uintptr_t)bind_bo.map + bind_bo.size)) 
||
-  pointers[i] == 0)
+  if (((uintptr_t)[i] >= ((uintptr_t)bind_bo.map + bind_bo.size)))
  break;
 
   uint64_t addr = ctx->surface_base + pointers[i];

Mesa (main): intel/genxml: add GAM done register description

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 78a881af4391006ead4c2e728647cfea70544d5e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78a881af4391006ead4c2e728647cfea70544d5e

Author: Lionel Landwerlin 
Date:   Thu Oct  5 11:06:38 2023 +0300

intel/genxml: add GAM done register description

Useful if you encounter some kind of pagefault (including with
AUX-TT).

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/genxml/gen12.xml   | 33 
 src/intel/tools/aubinator_error_decode.c |  4 
 2 files changed, 37 insertions(+)

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 42a08a6cde2..9a7daa64461 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -1426,6 +1426,39 @@
 
 
   
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
   
 
   
diff --git a/src/intel/tools/aubinator_error_decode.c 
b/src/intel/tools/aubinator_error_decode.c
index bec874edd8f..072b7d0649a 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -592,6 +592,10 @@ read_data_file(FILE *file)
print_register(spec, reg_name, reg);
  }
 
+ matched = sscanf(line, "  GAM_DONE: 0x%08x\n", );
+ if (matched == 1)
+print_register(spec, "GAM_DONE", reg);
+
  matched = sscanf(line, "  SC_INSTDONE: 0x%08x\n", );
  if (matched == 1)
 print_register(spec, "SC_INSTDONE", reg);

Mesa (main): etnaviv: disable 64bpp render/sampler formats

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e481c1269c36efae6fad9e3c60af9c66cc8bbf74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e481c1269c36efae6fad9e3c60af9c66cc8bbf74

Author: Lucas Stach 
Date:   Tue Jan  9 17:31:03 2024 +0100

etnaviv: disable 64bpp render/sampler formats

Vivante hardware handles 64bpp render targets and samplers in a odd way
by splitting the buffer and using a pair of texture samplers or a pair
of MRT outputs to access those resources. This isn't implemented in the
driver right now, so we should not advertise support for those formats.

CC: mesa-stable
Signed-off-by: Lucas Stach 
Reviewed-by: Christian Gmeiner 
Part-of: 

---

 src/gallium/drivers/etnaviv/etnaviv_screen.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 8f8e7c8d428..801562602fe 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -458,6 +458,11 @@ gpu_supports_texture_format(struct etna_screen *screen, 
uint32_t fmt,
 {
bool supported = true;
 
+   /* Requires split sampler support, which the driver doesn't support, yet. */
+   if (!util_format_is_compressed(format) &&
+   util_format_get_blocksizebits(format) > 32)
+  return false;
+
if (fmt == TEXTURE_FORMAT_ETC1)
   supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 
@@ -500,6 +505,10 @@ gpu_supports_render_format(struct etna_screen *screen, 
enum pipe_format format,
if (fmt == ETNA_NO_MATCH)
   return false;
 
+   /* Requires split target support, which the driver doesn't support, yet. */
+   if (util_format_get_blocksizebits(format) > 32)
+  return false;
+
if (sample_count > 1) {
   /* Explicitly enabled. */
   if (!DBG_ENABLED(ETNA_DBG_MSAA))

Mesa (main): radv: correctly return VK_ERROR_OUT_OF_DEVICE_MEMORY when mapping a BO fails

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6febec12e444ff8a52eb831361e2055d58b68b0b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6febec12e444ff8a52eb831361e2055d58b68b0b

Author: Samuel Pitoiset 
Date:   Fri Jan 12 16:50:50 2024 +0100

radv: correctly return VK_ERROR_OUT_OF_DEVICE_MEMORY when mapping a BO fails

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_queue.c   | 4 +++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 4 ++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index 3d4382878d1..59183d506bf 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -981,8 +981,10 @@ radv_update_preamble_cs(struct radv_queue_state *queue, 
struct radv_device *devi
 
if (descriptor_bo != queue->descriptor_bo) {
   uint32_t *map = (uint32_t *)ws->buffer_map(descriptor_bo);
-  if (!map)
+  if (!map) {
+ result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
  goto fail;
+  }
 
   radv_fill_shader_rings(device, map, scratch_bo, needs->esgs_ring_size, 
esgs_ring_bo, needs->gsvs_ring_size,
  gsvs_ring_bo, tess_rings_bo, task_rings_bo, 
mesh_scratch_ring_bo, needs->attr_ring_size,
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index e0b642a7829..5f753a2203a 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -265,7 +265,7 @@ radv_amdgpu_cs_get_new_ib(struct radeon_cmdbuf *_cs, 
uint32_t ib_size)
cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
if (!cs->ib_mapped) {
   cs->ws->base.buffer_destroy(>ws->base, cs->ib_buffer);
-  return VK_ERROR_OUT_OF_HOST_MEMORY;
+  return VK_ERROR_OUT_OF_DEVICE_MEMORY;
}
 
cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
@@ -730,7 +730,7 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf 
*_parent, struct radeon_cm
 
  mapped = ws->base.buffer_map(ib->bo);
  if (!mapped) {
-parent->status = VK_ERROR_OUT_OF_HOST_MEMORY;
+parent->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 return;
  }
 

Mesa (main): radv: constify stages in radv_rt_fill_group_info()

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: bb86fc03596a1aca0862a10eb251c1c71ed81d10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb86fc03596a1aca0862a10eb251c1c71ed81d10

Author: Samuel Pitoiset 
Date:   Fri Jan 12 11:55:53 2024 +0100

radv: constify stages in radv_rt_fill_group_info()

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline_rt.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline_rt.c 
b/src/amd/vulkan/radv_pipeline_rt.c
index c7f3047f561..5675977cffa 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -35,7 +35,7 @@ struct rt_handle_hash_entry {
 };
 
 static uint32_t
-handle_from_stages(struct radv_device *device, struct radv_ray_tracing_stage 
*stages, unsigned stage_count,
+handle_from_stages(struct radv_device *device, const struct 
radv_ray_tracing_stage *stages, unsigned stage_count,
bool replay_namespace)
 {
struct mesa_sha1 ctx;
@@ -110,8 +110,8 @@ radv_generate_rt_pipeline_key(const struct radv_device 
*device, const struct rad
 
 static VkResult
 radv_create_group_handles(struct radv_device *device, const struct 
radv_ray_tracing_pipeline *pipeline,
-  const VkRayTracingPipelineCreateInfoKHR 
*pCreateInfo, struct radv_ray_tracing_stage *stages,
-  struct radv_ray_tracing_group *groups)
+  const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
+  const struct radv_ray_tracing_stage *stages, struct 
radv_ray_tracing_group *groups)
 {
bool capture_replay =
   pipeline->base.base.create_flags & 
VK_PIPELINE_CREATE_2_RAY_TRACING_SHADER_GROUP_HANDLE_CAPTURE_REPLAY_BIT_KHR;
@@ -168,7 +168,8 @@ radv_create_group_handles(struct radv_device *device, const 
struct radv_ray_trac
 
 static VkResult
 radv_rt_fill_group_info(struct radv_device *device, const struct 
radv_ray_tracing_pipeline *pipeline,
-const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, 
struct radv_ray_tracing_stage *stages,
+const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
+const struct radv_ray_tracing_stage *stages,
 struct radv_serialized_shader_arena_block 
*capture_replay_blocks,
 struct radv_ray_tracing_group *groups)
 {

Mesa (main): radv/rt: re-use radv_ray_tracing_stage::sha1 for hashing RT pipelines

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 4fe5f06d400a7310ffc280761c27b036aec86646
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fe5f06d400a7310ffc280761c27b036aec86646

Author: Samuel Pitoiset 
Date:   Fri Jan 12 12:01:51 2024 +0100

radv/rt: re-use radv_ray_tracing_stage::sha1 for hashing RT pipelines

radv_ray_tracing_stage::sha1 is radv_pipeline_key+shader_sha1 which
should be similar to what the code was doing.

Signed-off-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline_cache.c | 21 +
 src/amd/vulkan/radv_pipeline_rt.c|  2 +-
 src/amd/vulkan/radv_private.h|  6 +++---
 3 files changed, 9 insertions(+), 20 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index fc357ad9058..98a69505965 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -68,19 +68,8 @@ radv_hash_shaders(const struct radv_device *device, unsigned 
char *hash, const s
 }
 
 void
-radv_hash_rt_stages(struct mesa_sha1 *ctx, const 
VkPipelineShaderStageCreateInfo *stages, unsigned stage_count)
-{
-   for (unsigned i = 0; i < stage_count; ++i) {
-  unsigned char hash[20];
-  vk_pipeline_hash_shader_stage([i], NULL, hash);
-  _mesa_sha1_update(ctx, hash, sizeof(hash));
-   }
-}
-
-void
-radv_hash_rt_shaders(const struct radv_device *device, unsigned char *hash,
- const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, 
const struct radv_pipeline_key *key,
- const struct radv_ray_tracing_group *groups)
+radv_hash_rt_shaders(const struct radv_device *device, unsigned char *hash, 
const struct radv_ray_tracing_stage *stages,
+ const VkRayTracingPipelineCreateInfoKHR *pCreateInfo, 
const struct radv_ray_tracing_group *groups)
 {
RADV_FROM_HANDLE(radv_pipeline_layout, layout, pCreateInfo->layout);
struct mesa_sha1 ctx;
@@ -90,9 +79,9 @@ radv_hash_rt_shaders(const struct radv_device *device, 
unsigned char *hash,
if (layout)
   _mesa_sha1_update(, layout->sha1, sizeof(layout->sha1));
 
-   _mesa_sha1_update(, key, sizeof(*key));
-
-   radv_hash_rt_stages(, pCreateInfo->pStages, pCreateInfo->stageCount);
+   for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
+  _mesa_sha1_update(, stages[i].sha1, sizeof(stages[i].sha1));
+   }
 
for (uint32_t i = 0; i < pCreateInfo->groupCount; i++) {
   _mesa_sha1_update(, >pGroups[i].type, 
sizeof(pCreateInfo->pGroups[i].type));
diff --git a/src/amd/vulkan/radv_pipeline_rt.c 
b/src/amd/vulkan/radv_pipeline_rt.c
index 5675977cffa..44f15b442d2 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -788,7 +788,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache 
_cache, const VkRayTra
 
bool keep_executable_info = radv_pipeline_capture_shaders(device, 
pipeline->base.base.create_flags);
 
-   radv_hash_rt_shaders(device, pipeline->sha1, pCreateInfo, , 
pipeline->groups);
+   radv_hash_rt_shaders(device, pipeline->sha1, stages, pCreateInfo, 
pipeline->groups);
pipeline->base.base.pipeline_hash = *(uint64_t *)pipeline->sha1;
 
bool cache_hit = false;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 9f08b2abbd9..814c1ec1867 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2015,10 +2015,10 @@ void radv_hash_shaders(const struct radv_device 
*device, unsigned char *hash, co
uint32_t stage_count, const struct radv_pipeline_layout 
*layout,
const struct radv_pipeline_key *key);
 
-void radv_hash_rt_stages(struct mesa_sha1 *ctx, const 
VkPipelineShaderStageCreateInfo *stages, unsigned stage_count);
-
+struct radv_ray_tracing_stage;
 void radv_hash_rt_shaders(const struct radv_device *device, unsigned char 
*hash,
-  const VkRayTracingPipelineCreateInfoKHR 
*pCreateInfo, const struct radv_pipeline_key *key,
+  const struct radv_ray_tracing_stage *stages,
+  const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
   const struct radv_ray_tracing_group *groups);
 
 bool radv_enable_rt(const struct radv_physical_device *pdevice, bool 
rt_pipelines);

Mesa (main): anv: check for wa 16013994831 in emit_so_memcpy_end

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 36f428f1de78d6bd2c0aa6719da06cd5233a8c7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36f428f1de78d6bd2c0aa6719da06cd5233a8c7f

Author: Tapani Pälli 
Date:   Thu Jan 11 15:50:09 2024 +0200

anv: check for wa 16013994831 in emit_so_memcpy_end

We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.

Cc: mesa-stable
Signed-off-by: Tapani Pälli 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 src/intel/vulkan/genX_gpu_memcpy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_gpu_memcpy.c 
b/src/intel/vulkan/genX_gpu_memcpy.c
index 5e78d2ab387..70b0851850f 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -272,7 +272,7 @@ genX(emit_so_memcpy_fini)(struct anv_memcpy_state *state)
 void
 genX(emit_so_memcpy_end)(struct anv_memcpy_state *state)
 {
-   if (intel_device_info_is_dg2(state->device->info))
+   if (intel_needs_workaround(state->device->info, 16013994831))
   genX(batch_set_preemption)(state->batch, state->device->info, _3D, true);
 
anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);

Mesa (main): intel/disasm: Remove duplicate variable reg_file

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 73835874a82f741e10cbc8da9128a4f5cd46e347
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73835874a82f741e10cbc8da9128a4f5cd46e347

Author: Vinson Lee 
Date:   Sat Jan 13 21:06:38 2024 -0800

intel/disasm: Remove duplicate variable reg_file

Fix defects reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = 
brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.

Fixes: 1c92dad5cb7 ("intel/disasm: Disassembly support for DPAS")
Signed-off-by: Vinson Lee 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 src/intel/compiler/brw_disasm.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index c56d4e554ca..7c482eae0c6 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1061,8 +1061,7 @@ static int
 dest_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst)
 {
-   uint32_t reg_file =
-  reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst);
+   uint32_t reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst);
 
if (reg(file, reg_file, brw_inst_dpas_3src_dst_reg_nr(devinfo, inst)) == -1)
   return 0;
@@ -1557,8 +1556,7 @@ static int
 src0_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst)
 {
-   uint32_t reg_file =
-  reg_file = brw_inst_dpas_3src_src0_reg_file(devinfo, inst);
+   uint32_t reg_file = brw_inst_dpas_3src_src0_reg_file(devinfo, inst);
 
if (reg(file, reg_file, brw_inst_dpas_3src_src0_reg_nr(devinfo, inst)) == 
-1)
   return 0;
@@ -1579,8 +1577,7 @@ static int
 src1_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst)
 {
-   uint32_t reg_file =
-  reg_file = brw_inst_dpas_3src_src1_reg_file(devinfo, inst);
+   uint32_t reg_file = brw_inst_dpas_3src_src1_reg_file(devinfo, inst);
 
if (reg(file, reg_file, brw_inst_dpas_3src_src1_reg_nr(devinfo, inst)) == 
-1)
   return 0;
@@ -1601,8 +1598,7 @@ static int
 src2_dpas_3src(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst)
 {
-   uint32_t reg_file =
-  reg_file = brw_inst_dpas_3src_src2_reg_file(devinfo, inst);
+   uint32_t reg_file = brw_inst_dpas_3src_src2_reg_file(devinfo, inst);
 
if (reg(file, reg_file, brw_inst_dpas_3src_src2_reg_nr(devinfo, inst)) == 
-1)
   return 0;

Mesa (main): iris: Use Mesa internal drm-uapi headers

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e84aa455e550bb151cccbc8668c5dd64719342e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e84aa455e550bb151cccbc8668c5dd64719342e9

Author: Dmitry Osipenko 
Date:   Sun Jan  7 00:45:55 2024 +0300

iris: Use Mesa internal drm-uapi headers

Iris driver includes system DRM UAPI header before the Mesa's internal
ones, which makes Iris to use the system headers. Correct the included
header for consistency with the rest of the Intel driver code by changing
the inclusion order, like it's done by the rest of the Intel driver code.

Reviewed-by: Lionel Landwerlin 
Signed-off-by: Dmitry Osipenko 
Part-of: 

---

 src/gallium/drivers/iris/iris_bufmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/iris/iris_bufmgr.c 
b/src/gallium/drivers/iris/iris_bufmgr.c
index 088f34f1e28..d24c14cb294 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -31,7 +31,6 @@
  * - main interface to GEM in the kernel
  */
 
-#include 
 #include 
 #include 
 #include 
@@ -72,6 +71,7 @@
 #include "xe/iris_bufmgr.h"
 
 #include "drm-uapi/i915_drm.h"
+#include 
 
 #ifdef HAVE_VALGRIND
 #include 

Mesa (main): anv: hide vendor ID for The Finals

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a34a113059f55947cc08624897999f7f066f000a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a34a113059f55947cc08624897999f7f066f000a

Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:51:05 2024 +0200

anv: hide vendor ID for The Finals

XeSS workaround.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Tapani Pälli 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10436
Cc: mesa-stable
Part-of: 

---

 src/util/00-mesa-defaults.conf | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf
index 8366765b71d..051b6ee4b52 100644
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -1199,6 +1199,9 @@ TODO: document the other workarounds.
 
 
 
+
+
+
 

Mesa (main): intel/aux_map: fix fallback unmapping range on failure

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: ff6041afdf2df9f048aa192f602c191e96ce92fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff6041afdf2df9f048aa192f602c191e96ce92fd

Author: Lionel Landwerlin 
Date:   Sun Jan 14 10:49:57 2024 +0200

intel/aux_map: fix fallback unmapping range on failure

Signed-off-by: Lionel Landwerlin 
Fixes: 7c6faa1efe ("intel/aux_map: introduce ref count of L1 entries")
Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/intel/common/intel_aux_map.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/common/intel_aux_map.c b/src/intel/common/intel_aux_map.c
index 3040d25d6dc..2804e30ec77 100644
--- a/src/intel/common/intel_aux_map.c
+++ b/src/intel/common/intel_aux_map.c
@@ -728,7 +728,7 @@ intel_aux_map_add_mapping(struct intel_aux_map_context 
*ctx, uint64_t main_addre
if (!success && (main_inc_addr - main_address) > 0) {
   /* If the mapping failed, remove the mapped portion. */
   remove_mapping_locked(ctx, main_address,
-main_size_B - (main_inc_addr - main_address),
+main_inc_addr - main_address,
 false /* reset_refcount */, _changed);
}
pthread_mutex_unlock(>mutex);

Mesa (main): gallium: remove unbind_trailing_count from set_vertex_buffers

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: eb20ef92772c6a4963128370260d578f100efee9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb20ef92772c6a4963128370260d578f100efee9

Author: Marek Olšák 
Date:   Mon Nov 20 13:48:09 2023 -0500

gallium: remove unbind_trailing_count from set_vertex_buffers

It should implicitly unbind all bound buffers after "count".
This also slightly simplies u_vbuf.

This is a cleanup suggested by:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/8142

Reviewed-by: Alyssa Rosenzweig  (asahi & panfrost)
Reviewed-By: Mike Blumenkrantz 
Part-of: 

---

 src/gallium/auxiliary/cso_cache/cso_context.c |  34 ++---
 src/gallium/auxiliary/cso_cache/cso_context.h |   2 -
 src/gallium/auxiliary/draw/draw_context.c |   4 +-
 src/gallium/auxiliary/draw/draw_context.h |   1 -
 src/gallium/auxiliary/driver_ddebug/dd_context.c  |  12 +-
 src/gallium/auxiliary/driver_ddebug/dd_pipe.h |   1 +
 src/gallium/auxiliary/driver_noop/noop_state.c|   1 -
 src/gallium/auxiliary/driver_trace/tr_context.c   |   6 +-
 src/gallium/auxiliary/hud/hud_context.c   |   8 +-
 src/gallium/auxiliary/util/u_blitter.c|  14 ++-
 src/gallium/auxiliary/util/u_blitter.h|  15 ++-
 src/gallium/auxiliary/util/u_draw_quad.c  |   8 +-
 src/gallium/auxiliary/util/u_helpers.c|  28 ++---
 src/gallium/auxiliary/util/u_helpers.h|   2 -
 src/gallium/auxiliary/util/u_threaded_context.c   |  30 ++---
 src/gallium/auxiliary/util/u_threaded_context.h   |   2 +-
 src/gallium/auxiliary/util/u_vbuf.c   | 146 ++
 src/gallium/auxiliary/util/u_vbuf.h   |   1 -
 src/gallium/auxiliary/vl/vl_bicubic_filter.c  |   2 +-
 src/gallium/auxiliary/vl/vl_compositor_gfx.c  |   2 +-
 src/gallium/auxiliary/vl/vl_deint_filter.c|   2 +-
 src/gallium/auxiliary/vl/vl_matrix_filter.c   |   2 +-
 src/gallium/auxiliary/vl/vl_median_filter.c   |   2 +-
 src/gallium/auxiliary/vl/vl_mpeg12_decoder.c  |   6 +-
 src/gallium/drivers/asahi/agx_blit.c  |   3 +-
 src/gallium/drivers/asahi/agx_state.c |   5 +-
 src/gallium/drivers/crocus/crocus_blit.c  |   3 +-
 src/gallium/drivers/crocus/crocus_state.c |   6 +-
 src/gallium/drivers/d3d12/d3d12_blit.cpp  |   2 +-
 src/gallium/drivers/d3d12/d3d12_context.cpp   |   8 +-
 src/gallium/drivers/etnaviv/etnaviv_clear_blit.c  |   3 +-
 src/gallium/drivers/etnaviv/etnaviv_state.c   |   6 +-
 src/gallium/drivers/freedreno/freedreno_blitter.c |   6 +-
 src/gallium/drivers/freedreno/freedreno_state.c   |   6 +-
 src/gallium/drivers/i915/i915_state.c |   7 +-
 src/gallium/drivers/i915/i915_surface.c   |   3 +-
 src/gallium/drivers/iris/iris_state.c |   9 +-
 src/gallium/drivers/lima/lima_resource.c  |   4 +-
 src/gallium/drivers/lima/lima_state.c |   7 +-
 src/gallium/drivers/llvmpipe/lp_state_vertex.c|   5 +-
 src/gallium/drivers/llvmpipe/lp_surface.c |   3 +-
 src/gallium/drivers/nouveau/nv30/nv30_draw.c  |   2 +-
 src/gallium/drivers/nouveau/nv30/nv30_miptree.c   |   2 +-
 src/gallium/drivers/nouveau/nv30/nv30_state.c |   5 +-
 src/gallium/drivers/nouveau/nv50/nv50_state.c |   8 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c |   8 +-
 src/gallium/drivers/panfrost/pan_blit.c   |   3 +-
 src/gallium/drivers/panfrost/pan_context.c|   4 +-
 src/gallium/drivers/r300/r300_blit.c  |   3 +-
 src/gallium/drivers/r300/r300_context.c   |   2 +-
 src/gallium/drivers/r300/r300_state.c |  20 ++-
 src/gallium/drivers/r600/r600_blit.c  |   3 +-
 src/gallium/drivers/r600/r600_pipe_common.c   |   2 +-
 src/gallium/drivers/r600/r600_state_common.c  |  59 -
 src/gallium/drivers/radeonsi/si_pipe.h|   1 +
 src/gallium/drivers/radeonsi/si_state.c   |  83 +---
 src/gallium/drivers/softpipe/sp_state_vertex.c|   4 +-
 src/gallium/drivers/softpipe/sp_surface.c |   3 +-
 src/gallium/drivers/svga/svga_pipe_blit.c |   3 +-
 src/gallium/drivers/svga/svga_pipe_clear.c|   3 +-
 src/gallium/drivers/svga/svga_pipe_vertex.c   |   5 +-
 src/gallium/drivers/svga/svga_swtnl_state.c   |   2 +-
 src/gallium/drivers/tegra/tegra_context.c |   3 +-
 src/gallium/drivers/v3d/v3d_blit.c|   2 +-
 src/gallium/drivers/v3d/v3dx_state.c  |   4 +-
 src/gallium/drivers/vc4/vc4_blit.c|   3 +-
 src/gallium/drivers/vc4/vc4_state.c   |   4 +-
 src/gallium/drivers/virgl/virgl_context.c |   2 -
 src/gallium/drivers/zink/zink_blit.c  |   3 +-
 src/gallium/drivers/zink/zink_context.c   |  66 +-
 src/gallium/frontends/lavapipe/lvp_execute.c  |   2 +-
 

Mesa (main): cso: don't unbind vertex buffers when enabling/disabling u_vbuf

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 33b77ec774a10f052a2814d9ff3668cc0aa13083
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33b77ec774a10f052a2814d9ff3668cc0aa13083

Author: Marek Olšák 
Date:   Sun Dec 10 16:20:57 2023 -0500

cso: don't unbind vertex buffers when enabling/disabling u_vbuf

The next set_vertex_buffers call always overwrites all slots anyway.

Reviewed-By: Mike Blumenkrantz 
Part-of: 

---

 src/gallium/auxiliary/cso_cache/cso_context.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c 
b/src/gallium/auxiliary/cso_cache/cso_context.c
index bfaec3ca975..4e2d640df57 100644
--- a/src/gallium/auxiliary/cso_cache/cso_context.c
+++ b/src/gallium/auxiliary/cso_cache/cso_context.c
@@ -1329,9 +1329,6 @@ cso_set_vertex_buffers_and_elements(struct cso_context 
*cso,
 
if (vbuf && (ctx->always_use_vbuf || uses_user_vertex_buffers)) {
   if (!ctx->vbuf_current) {
- /* Unbind all buffers in cso_context, because we'll use u_vbuf. */
- pipe->set_vertex_buffers(pipe, 0, false, NULL);
-
  /* Unset this to make sure the CSO is re-bound on the next use. */
  ctx->velements = NULL;
  ctx->vbuf_current = pipe->vbuf = vbuf;
@@ -1345,9 +1342,6 @@ cso_set_vertex_buffers_and_elements(struct cso_context 
*cso,
}
 
if (ctx->vbuf_current) {
-  /* Unbind all buffers in u_vbuf, because we'll use cso_context. */
-  u_vbuf_set_vertex_buffers(vbuf, 0, false, NULL);
-
   /* Unset this to make sure the CSO is re-bound on the next use. */
   u_vbuf_unset_vertex_elements(vbuf);
   ctx->vbuf_current = pipe->vbuf = NULL;

Mesa (main): gallium/u_vbuf: replace unnecessary dst_index with "i"

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2725b095ea2a16a1ce28aca8ae31e9d3df448c67
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2725b095ea2a16a1ce28aca8ae31e9d3df448c67

Author: Marek Olšák 
Date:   Sat Jan  6 16:49:51 2024 -0500

gallium/u_vbuf: replace unnecessary dst_index with "i"

Reviewed-by: Christian Gmeiner 
Reviewed-By: Mike Blumenkrantz 
Part-of: 

---

 src/gallium/auxiliary/util/u_vbuf.c | 23 ++-
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_vbuf.c 
b/src/gallium/auxiliary/util/u_vbuf.c
index 63e400e5b25..1ab194cfe52 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -1022,10 +1022,8 @@ void u_vbuf_set_vertex_buffers(struct u_vbuf *mgr,
   mgr->unaligned_vb_mask[1] &= mask;
 
   for (i = 0; i < total_count; i++) {
- unsigned dst_index = i;
-
- pipe_vertex_buffer_unreference(>vertex_buffer[dst_index]);
- pipe_vertex_buffer_unreference(>real_vertex_buffer[dst_index]);
+ pipe_vertex_buffer_unreference(>vertex_buffer[i]);
+ pipe_vertex_buffer_unreference(>real_vertex_buffer[i]);
   }
 
   pipe->set_vertex_buffers(pipe, count, unbind_num_trailing_slots, false, 
NULL);
@@ -1033,10 +1031,9 @@ void u_vbuf_set_vertex_buffers(struct u_vbuf *mgr,
}
 
for (i = 0; i < count; i++) {
-  unsigned dst_index = i;
   const struct pipe_vertex_buffer *vb = [i];
-  struct pipe_vertex_buffer *orig_vb = >vertex_buffer[dst_index];
-  struct pipe_vertex_buffer *real_vb = >real_vertex_buffer[dst_index];
+  struct pipe_vertex_buffer *orig_vb = >vertex_buffer[i];
+  struct pipe_vertex_buffer *real_vb = >real_vertex_buffer[i];
 
   if (!vb->buffer.resource) {
  pipe_vertex_buffer_unreference(orig_vb);
@@ -1048,7 +1045,7 @@ void u_vbuf_set_vertex_buffers(struct u_vbuf *mgr,
   /* struct isn't tightly packed: do not use memcmp */
   if (not_user &&
   orig_vb->buffer_offset == vb->buffer_offset && 
orig_vb->buffer.resource == vb->buffer.resource) {
- mask |= BITFIELD_BIT(dst_index);
+ mask |= BITFIELD_BIT(i);
  if (take_ownership) {
  pipe_vertex_buffer_unreference(orig_vb);
  /* the pointer was unset in the line above, so copy it back */
@@ -1066,10 +1063,10 @@ void u_vbuf_set_vertex_buffers(struct u_vbuf *mgr,
  pipe_vertex_buffer_reference(orig_vb, vb);
   }
 
-  enabled_vb_mask |= 1 << dst_index;
+  enabled_vb_mask |= 1 << i;
 
   if ((!mgr->caps.buffer_offset_unaligned && vb->buffer_offset % 4 != 0)) {
- incompatible_vb_mask |= 1 << dst_index;
+ incompatible_vb_mask |= 1 << i;
  real_vb->buffer_offset = vb->buffer_offset;
  pipe_vertex_buffer_unreference(real_vb);
  real_vb->is_user_buffer = false;
@@ -1078,13 +1075,13 @@ void u_vbuf_set_vertex_buffers(struct u_vbuf *mgr,
 
   if (!mgr->caps.attrib_component_unaligned) {
  if (vb->buffer_offset % 2 != 0)
-unaligned_vb_mask[0] |= BITFIELD_BIT(dst_index);
+unaligned_vb_mask[0] |= BITFIELD_BIT(i);
  if (vb->buffer_offset % 4 != 0)
-unaligned_vb_mask[1] |= BITFIELD_BIT(dst_index);
+unaligned_vb_mask[1] |= BITFIELD_BIT(i);
   }
 
   if (!mgr->caps.user_vertex_buffers && vb->is_user_buffer) {
- user_vb_mask |= 1 << dst_index;
+ user_vb_mask |= 1 << i;
  real_vb->buffer_offset = vb->buffer_offset;
  pipe_vertex_buffer_unreference(real_vb);
  real_vb->is_user_buffer = false;

Mesa (main): nvk: Add a couple more features to features.txt

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: cfba24ccb548af0ad3427b525def602383cd204a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfba24ccb548af0ad3427b525def602383cd204a

Author: Faith Ekstrand 
Date:   Sun Jan 14 12:15:52 2024 -0600

nvk: Add a couple more features to features.txt

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10429
Part-of: 

---

 docs/features.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index 953696a58fc..d9557875c57 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -461,7 +461,7 @@ Vulkan 1.2 -- all DONE: anv, tu, vn
   VK_KHR_shader_atomic_int64DONE (anv/gen9+, lvp, 
nvk, radv, vn)
   VK_KHR_shader_float16_int8DONE (anv/gen8+, dzn, 
hasvk, lvp, radv, tu, vn)
   VK_KHR_shader_float_controls  DONE (anv/gen8+, dzn, 
hasvk, lvp, nvk, radv, tu, v3dv, vn)
-  VK_KHR_shader_subgroup_extended_types DONE (anv/gen8+, 
hasvk, lvp, radv, tu, vn)
+  VK_KHR_shader_subgroup_extended_types DONE (anv/gen8+, 
hasvk, lvp, nvk, radv, tu, vn)
   VK_KHR_spirv_1_4  DONE (anv, dzn, hasvk, 
lvp, nvk, radv, tu, v3dv, vn)
   VK_KHR_timeline_semaphore DONE (anv, dzn, hasvk, 
lvp, nvk, pvr, radv, tu, v3dv, vn)
   VK_KHR_uniform_buffer_standard_layout DONE (anv, dzn, hasvk, 
lvp, nvk, pvr, radv, tu, v3dv, vn)
@@ -483,7 +483,7 @@ Vulkan 1.3 -- all DONE: anv, radv, tu, lvp, vn
   VK_KHR_shader_non_semantic_info   DONE (anv, hasvk, nvk, 
radv, tu, v3dv, vn)
   VK_KHR_shader_terminate_invocationDONE (anv, hasvk, lvp, 
nvk, radv, tu, v3dv, vn)
   VK_KHR_synchronization2   DONE (anv, dzn, hasvk, 
lvp, nvk, panvk, radv, tu, v3dv, vn)
-  VK_KHR_zero_initialize_workgroup_memory   DONE (anv, hasvk, lvp, 
radv, tu, v3dv, vn)
+  VK_KHR_zero_initialize_workgroup_memory   DONE (anv, hasvk, lvp, 
nvk, radv, tu, v3dv, vn)
   VK_EXT__formats   DONE (anv, hasvk, lvp, 
nvk, radv, tu, v3dv, vn)
   VK_EXT_extended_dynamic_state DONE (anv, hasvk, lvp, 
nvk, radv, tu, vn)
   VK_EXT_extended_dynamic_state2DONE (anv, hasvk, lvp, 
nvk, radv, tu, vn)

Mesa (main): ci/deqp: ensure that in `default` builds, wayland + x11 + xcb are all built

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 27a1b4e4f314832c164380ea332c096fe394c8f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27a1b4e4f314832c164380ea332c096fe394c8f0

Author: Eric Engestrom 
Date:   Wed Jan 10 21:50:45 2024 +

ci/deqp: ensure that in `default` builds, wayland + x11 + xcb are all built

If someone were to remove the libraries that are needed for these,
`default` would simply not enable these tests, and the only thing we
could notice is that test jobs would suddenly take less time to run.

Instead, let's have a check to make sure dEQP's cmake has detected
everything and enabled these platforms.

Reviewed-by: David Heidelberg 
Part-of: 

---

 .gitlab-ci/container/build-deqp.sh | 8 
 .gitlab-ci/image-tags.yml  | 8 
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/.gitlab-ci/container/build-deqp.sh 
b/.gitlab-ci/container/build-deqp.sh
index 850642c77d9..2c27288ae87 100644
--- a/.gitlab-ci/container/build-deqp.sh
+++ b/.gitlab-ci/container/build-deqp.sh
@@ -101,6 +101,14 @@ cmake -S /VK-GL-CTS -B . -G Ninja \
   -DDEQP_TARGET=${DEQP_TARGET:-default} \
   -DCMAKE_BUILD_TYPE=Release \
   $EXTRA_CMAKE_ARGS
+
+# Make sure `default` doesn't silently stop detecting one of the platforms we 
care about
+if [ "${DEQP_TARGET}" = 'default' ]; then
+  grep -q DEQP_SUPPORT_WAYLAND=1 build.ninja
+  grep -q DEQP_SUPPORT_X11=1 build.ninja
+  grep -q DEQP_SUPPORT_XCB=1 build.ninja
+fi
+
 mold --run ninja
 
 if [ "${DEQP_TARGET}" = 'android' ]; then
diff --git a/.gitlab-ci/image-tags.yml b/.gitlab-ci/image-tags.yml
index fe55edf7213..addc7aff056 100644
--- a/.gitlab-ci/image-tags.yml
+++ b/.gitlab-ci/image-tags.yml
@@ -18,14 +18,14 @@ variables:
DEBIAN_X86_64_TEST_IMAGE_VK_PATH: "debian/x86_64_test-vk"
DEBIAN_X86_64_TEST_ANDROID_IMAGE_PATH: "debian/x86_64_test-android"
 
-   DEBIAN_X86_64_TEST_ANDROID_TAG: "2024-01-04-default"
-   DEBIAN_X86_64_TEST_GL_TAG: "2024-01-04-default"
-   DEBIAN_X86_64_TEST_VK_TAG: "2024-01-04-default"
+   DEBIAN_X86_64_TEST_ANDROID_TAG: "2024-01-14-check-deqp"
+   DEBIAN_X86_64_TEST_GL_TAG: "2024-01-14-check-deqp"
+   DEBIAN_X86_64_TEST_VK_TAG: "2024-01-14-check-deqp"
 
ALPINE_X86_64_BUILD_TAG: "2023-01-07-libdrm2_4_119"
ALPINE_X86_64_LAVA_SSH_TAG: "2023-06-26-first-version"
FEDORA_X86_64_BUILD_TAG: "2024-01-06-libdrm"
-   KERNEL_ROOTFS_TAG: "2024-01-10-default"
+   KERNEL_ROOTFS_TAG: "2024-01-14-check-deqp"
KERNEL_TAG: "v6.6.4-for-mesa-ci-e4f4c500f7fb"
KERNEL_REPO: "gfx-ci/linux"
PKG_REPO_REV: "67f2c46b"

Mesa (main): nvk: Move SET_HYBRID_ANTI_ALIAS_CONTROL to draw time

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 0e33dba6256f0da5882a55081616004d3f5dc1e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e33dba6256f0da5882a55081616004d3f5dc1e2

Author: Faith Ekstrand 
Date:   Thu Jan 11 18:17:31 2024 -0600

nvk: Move SET_HYBRID_ANTI_ALIAS_CONTROL to draw time

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_draw.c  | 15 +--
 src/nouveau/vulkan/nvk_graphics_pipeline.c | 24 +++-
 src/nouveau/vulkan/nvk_pipeline.h  |  2 ++
 3 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c 
b/src/nouveau/vulkan/nvk_cmd_draw.c
index bde6429f597..d2851e48c81 100644
--- a/src/nouveau/vulkan/nvk_cmd_draw.c
+++ b/src/nouveau/vulkan/nvk_cmd_draw.c
@@ -1428,13 +1428,13 @@ nvk_flush_ms_state(struct nvk_cmd_buffer *cmd)
   >vk.dynamic_graphics_state;
 
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES)) {
+  struct nv_push *p = nvk_cmd_buffer_push(cmd, 4);
+
   /* When we don't have any attachments, we can't know the sample count
* from the render pass so we need to emit SET_ANTI_ALIAS here.  See the
* comment in nvk_BeginRendering() for more details.
*/
   if (render->samples == 0) {
- struct nv_push *p = nvk_cmd_buffer_push(cmd, 2);
-
  /* Multisample information MAY be missing (rasterizationSamples == 0)
   * if rasterizer discard is enabled.  However, this isn't valid in
   * the hardware so always use at least one sample.
@@ -1449,6 +1449,17 @@ nvk_flush_ms_state(struct nvk_cmd_buffer *cmd)
  assert(dyn->ms.rasterization_samples == 0 ||
 dyn->ms.rasterization_samples == render->samples);
   }
+
+  const struct nvk_graphics_pipeline *pipeline = cmd->state.gfx.pipeline;
+  uint32_t min_samples = ceilf(dyn->ms.rasterization_samples *
+   pipeline->min_sample_shading);
+  min_samples = util_next_power_of_two(MAX2(1, min_samples));
+
+  P_IMMD(p, NV9097, SET_HYBRID_ANTI_ALIAS_CONTROL, {
+ .passes = min_samples,
+ .centroid = min_samples > 1 ? CENTROID_PER_PASS
+ : CENTROID_PER_FRAGMENT,
+  });
}
 
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_COVERAGE_ENABLE) ||
diff --git a/src/nouveau/vulkan/nvk_graphics_pipeline.c 
b/src/nouveau/vulkan/nvk_graphics_pipeline.c
index 61b489bb01a..019ecd56ca7 100644
--- a/src/nouveau/vulkan/nvk_graphics_pipeline.c
+++ b/src/nouveau/vulkan/nvk_graphics_pipeline.c
@@ -46,22 +46,6 @@ nvk_populate_fs_key(struct nak_fs_key *key,
   key->force_sample_shading = true;
 }
 
-static void
-emit_pipeline_ms_state(struct nv_push *p,
-   const struct vk_multisample_state *ms,
-   bool force_max_samples)
-{
-   const float min_sample_shading = force_max_samples ? 1 :
-  (ms->sample_shading_enable ? CLAMP(ms->min_sample_shading, 0, 1) : 0);
-   uint32_t min_samples = ceilf(ms->rasterization_samples * 
min_sample_shading);
-   min_samples = util_next_power_of_two(MAX2(1, min_samples));
-
-   P_IMMD(p, NV9097, SET_HYBRID_ANTI_ALIAS_CONTROL, {
-  .passes = min_samples,
-  .centroid = min_samples > 1 ? CENTROID_PER_PASS : CENTROID_PER_FRAGMENT,
-   });
-}
-
 static void
 emit_pipeline_ct_write_state(struct nv_push *p,
  const struct vk_color_blend_state *cb,
@@ -435,11 +419,17 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
 
emit_pipeline_xfb_state(, _geom->info.vtg.xfb);
 
-   if (state.ms) emit_pipeline_ms_state(, state.ms, force_max_samples);
emit_pipeline_ct_write_state(, state.cb, state.rp);
 
pipeline->push_dw_count = nv_push_dw_count();
 
+   if (force_max_samples)
+  pipeline->min_sample_shading = 1;
+   else if (state.ms != NULL && state.ms->sample_shading_enable)
+  pipeline->min_sample_shading = CLAMP(state.ms->min_sample_shading, 0, 1);
+   else
+  pipeline->min_sample_shading = 0;
+
pipeline->dynamic.vi = >_dynamic_vi;
pipeline->dynamic.ms.sample_locations = >_dynamic_sl;
vk_dynamic_graphics_state_fill(>dynamic, );
diff --git a/src/nouveau/vulkan/nvk_pipeline.h 
b/src/nouveau/vulkan/nvk_pipeline.h
index b7a33249ddb..a68b353a9c8 100644
--- a/src/nouveau/vulkan/nvk_pipeline.h
+++ b/src/nouveau/vulkan/nvk_pipeline.h
@@ -57,6 +57,8 @@ struct nvk_graphics_pipeline {
uint32_t push_data[192];
uint32_t push_dw_count;
 
+   float min_sample_shading;
+
struct vk_vertex_input_state _dynamic_vi;
struct vk_sample_locations_state _dynamic_sl;
struct vk_dynamic_graphics_state dynamic;

Mesa (main): vulkan: Fix null pointer dereferencing on sample locations state

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 48d510ac578c859ce2046f055d1e6dc37716a499
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48d510ac578c859ce2046f055d1e6dc37716a499

Author: George Ouzounoudis 
Date:   Thu Aug 10 23:02:50 2023 +0300

vulkan: Fix null pointer dereferencing on sample locations state

In the case both sample locations and rasterization samples is supported by a
driver as dynamic state, there is a case 
vk_multisample_sample_locations_state_init()
does not fill ms->sample_locations at all. In this case we need to check
this pointer when dereferencing it in vk_dynamic_graphics_state_init_ms().

Reviewed-by: Faith Ekstrand 
Reviewed-by: Mike Blumenkrantz 
Part-of: 

---

 src/vulkan/runtime/vk_graphics_state.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/vulkan/runtime/vk_graphics_state.c 
b/src/vulkan/runtime/vk_graphics_state.c
index d4f42c3083b..1b86e5a4d39 100644
--- a/src/vulkan/runtime/vk_graphics_state.c
+++ b/src/vulkan/runtime/vk_graphics_state.c
@@ -776,6 +776,9 @@ vk_multisample_sample_locations_state_init(
  ms->sample_locations =
 vk_standard_sample_locations_state(ms_info->rasterizationSamples);
   }
+  /* In the case that the rasterization samples are dynamic we cannot
+   * pre-populate with a specific set of standard sample locations
+   */
}
 }
 
@@ -790,7 +793,7 @@ vk_dynamic_graphics_state_init_ms(struct 
vk_dynamic_graphics_state *dst,
dst->ms.alpha_to_one_enable = ms->alpha_to_one_enable;
dst->ms.sample_locations_enable = ms->sample_locations_enable;
 
-   if (IS_NEEDED(MS_SAMPLE_LOCATIONS))
+   if (IS_NEEDED(MS_SAMPLE_LOCATIONS) && ms->sample_locations)
   *dst->ms.sample_locations = *ms->sample_locations;
 }
 

Mesa (main): nvk: Advertise variableMultisampleRate and EDS3RasterizationSamples

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3c7460c0238a4c7823aea22d9fbfb795ea738fc4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c7460c0238a4c7823aea22d9fbfb795ea738fc4

Author: Faith Ekstrand 
Date:   Thu Jan 11 18:18:44 2024 -0600

nvk: Advertise variableMultisampleRate and EDS3RasterizationSamples

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9665
Part-of: 

---

 src/nouveau/vulkan/nvk_physical_device.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_physical_device.c 
b/src/nouveau/vulkan/nvk_physical_device.c
index a9ef92e3106..739fe10e362 100644
--- a/src/nouveau/vulkan/nvk_physical_device.c
+++ b/src/nouveau/vulkan/nvk_physical_device.c
@@ -259,8 +259,7 @@ nvk_get_device_features(const struct nv_device_info *info,
   .sparseBinding = true,
   .sparseResidencyBuffer = info->cls_eng3d >= MAXWELL_A,
   /* TODO: sparseResidency* */
-  /* TODO: variableMultisampleRate */
-  /* TODO: inheritedQueries */
+  .variableMultisampleRate = true,
   .inheritedQueries = true,
 
   /* Vulkan 1.1 */
@@ -414,7 +413,7 @@ nvk_get_device_features(const struct nv_device_info *info,
   .extendedDynamicState3TessellationDomainOrigin = true,
   .extendedDynamicState3DepthClampEnable = true,
   .extendedDynamicState3PolygonMode = true,
-  .extendedDynamicState3RasterizationSamples = false,
+  .extendedDynamicState3RasterizationSamples = true,
   .extendedDynamicState3SampleMask = true,
   .extendedDynamicState3AlphaToCoverageEnable = true,
   .extendedDynamicState3AlphaToOneEnable = true,

Mesa (main): nvk: Emit SET_ANTI_ALIAS at draw time when no render targets are bound

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 148ea7792f32d6a454c610fa8a49994ff954a61f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=148ea7792f32d6a454c610fa8a49994ff954a61f

Author: Faith Ekstrand 
Date:   Thu Jan 11 18:08:56 2024 -0600

nvk: Emit SET_ANTI_ALIAS at draw time when no render targets are bound

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_buffer.h |  1 +
 src/nouveau/vulkan/nvk_cmd_draw.c   | 58 ++---
 2 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.h 
b/src/nouveau/vulkan/nvk_cmd_buffer.h
index 86ec031f21e..67a1dcdce3f 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.h
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.h
@@ -91,6 +91,7 @@ struct nvk_rendering_state {
VkRect2D area;
uint32_t layer_count;
uint32_t view_mask;
+   uint32_t samples;
 
uint32_t color_att_count;
struct nvk_attachment color_att[NVK_MAX_RTS];
diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c 
b/src/nouveau/vulkan/nvk_cmd_draw.c
index f0b2df87922..bde6429f597 100644
--- a/src/nouveau/vulkan/nvk_cmd_draw.c
+++ b/src/nouveau/vulkan/nvk_cmd_draw.c
@@ -455,6 +455,9 @@ nvk_cmd_buffer_dirty_render_pass(struct nvk_cmd_buffer *cmd)
BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE);
BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE);
BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE);
+
+   /* This may depend on render targets for ESO */
+   BITSET_SET(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
 }
 
 void
@@ -496,6 +499,7 @@ nvk_cmd_buffer_begin_graphics(struct nvk_cmd_buffer *cmd,
  render->area = (VkRect2D) { };
  render->layer_count = 0;
  render->view_mask = inheritance_info->viewMask;
+ render->samples = inheritance_info->rasterizationSamples;
 
  render->color_att_count = inheritance_info->colorAttachmentCount;
  for (uint32_t i = 0; i < render->color_att_count; i++) {
@@ -592,6 +596,7 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
render->area = pRenderingInfo->renderArea;
render->view_mask = pRenderingInfo->viewMask;
render->layer_count = pRenderingInfo->layerCount;
+   render->samples = 0;
 
const uint32_t layer_count =
   render->view_mask ? util_last_bit(render->view_mask) :
@@ -647,6 +652,7 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
  assert(sample_layout == NIL_SAMPLE_LAYOUT_INVALID ||
 sample_layout == image->planes[ip].nil.sample_layout);
  sample_layout = image->planes[ip].nil.sample_layout;
+ render->samples = image->vk.samples;
 
  uint64_t addr = nvk_image_base_address(image, ip) + level->offset_B;
 
@@ -767,6 +773,7 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
   assert(sample_layout == NIL_SAMPLE_LAYOUT_INVALID ||
  sample_layout == nil_image.sample_layout);
   sample_layout = nil_image.sample_layout;
+  render->samples = image->vk.samples;
 
   P_MTHD(p, NV9097, SET_ZT_A);
   P_NV9097_SET_ZT_A(p, addr >> 32);
@@ -807,10 +814,28 @@ nvk_CmdBeginRendering(VkCommandBuffer commandBuffer,
   P_IMMD(p, NV9097, SET_ZT_SELECT, 0 /* target_count */);
}
 
-   if (sample_layout == NIL_SAMPLE_LAYOUT_INVALID)
-  sample_layout = NIL_SAMPLE_LAYOUT_1X1;
-
-   P_IMMD(p, NV9097, SET_ANTI_ALIAS, 
nil_to_nv9097_samples_mode(sample_layout));
+   /* From the Vulkan 1.3.275 spec:
+*
+*"It is legal for a subpass to use no color or depth/stencil
+*attachments, either because it has no attachment references or
+*because all of them are VK_ATTACHMENT_UNUSED. This kind of subpass
+*can use shader side effects such as image stores and atomics to
+*produce an output. In this case, the subpass continues to use the
+*width, height, and layers of the framebuffer to define the dimensions
+*of the rendering area, and the rasterizationSamples from each
+*pipeline’s VkPipelineMultisampleStateCreateInfo to define the number
+*of samples used in rasterization;"
+*
+* In the case where we have attachments, we emit SET_ANTI_ALIAS here
+* because SET_COLOR_TARGET_* and SET_ZT_* don't have any other way of
+* specifying the sample layout and we want to ensure it matches.  When
+* we don't have any attachments, we defer SET_ANTI_ALIAS to draw time
+* where we base it on dynamic rasterizationSamples.
+*/
+   if (sample_layout != NIL_SAMPLE_LAYOUT_INVALID) {
+  P_IMMD(p, NV9097, SET_ANTI_ALIAS,
+ nil_to_nv9097_samples_mode(sample_layout));
+   }
 
if (render->flags & VK_RENDERING_RESUMING_BIT)
   return;
@@ -1398,9 +1423,34 @@ static void
 nvk_flush_ms_state(struct nvk_cmd_buffer *cmd)
 {
struct nvk_descriptor_state *desc = >state.gfx.descriptors;
+   const struct nvk_rendering_state *render = >state.gfx.render;

Mesa (main): aco: reassign split vector to SOPC

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e36235e6d530e037cffd189d48fb6ae88f5dd613
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e36235e6d530e037cffd189d48fb6ae88f5dd613

Author: Georg Lehmann 
Date:   Fri Jan 12 21:54:03 2024 +0100

aco: reassign split vector to SOPC

Foz-DB Navi21:
Totals from 2669 (3.42% of 78112) affected shaders:
Instrs: 3570360 -> 3562026 (-0.23%)
CodeSize: 19049784 -> 19017092 (-0.17%)
Latency: 25343555 -> 25337767 (-0.02%); split: -0.03%, +0.00%
InvThroughput: 6191344 -> 6191079 (-0.00%); split: -0.01%, +0.00%
VClause: 90803 -> 90802 (-0.00%)
SClause: 114858 -> 114842 (-0.01%); split: -0.03%, +0.01%
Copies: 269287 -> 260999 (-3.08%)

Reviewed-by: Timur Kristóf 
Part-of: 

---

 src/amd/compiler/aco_optimizer_postRA.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp 
b/src/amd/compiler/aco_optimizer_postRA.cpp
index 5978e7c4b46..cee1fd0cb57 100644
--- a/src/amd/compiler/aco_optimizer_postRA.cpp
+++ b/src/amd/compiler/aco_optimizer_postRA.cpp
@@ -575,7 +575,7 @@ unsigned
 num_encoded_alu_operands(const aco_ptr& instr)
 {
if (instr->isSALU()) {
-  if (instr->isSOP2())
+  if (instr->isSOP2() || instr->isSOPC())
  return 2;
   else if (instr->isSOP1())
  return 1;

Mesa (main): nak: Disallow gl_FragData and set MRT correctly

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: d280160a1352e8f05be27a9573fead98c617e2ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d280160a1352e8f05be27a9573fead98c617e2ac

Author: Faith Ekstrand 
Date:   Wed Jan 10 10:11:06 2024 -0600

nak: Disallow gl_FragData and set MRT correctly

Part-of: 

---

 src/nouveau/compiler/nak/sph.rs | 9 -
 src/nouveau/compiler/nak_nir.c  | 3 +--
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/nouveau/compiler/nak/sph.rs b/src/nouveau/compiler/nak/sph.rs
index 034ab999e6f..e5f70b42f9d 100644
--- a/src/nouveau/compiler/nak/sph.rs
+++ b/src/nouveau/compiler/nak/sph.rs
@@ -533,7 +533,14 @@ pub fn encode_header(
 
 let zs_self_dep = fs_key.map_or(false, |key| key.zs_self_dep);
 
-sph.set_multiple_render_target_enable(io.writes_color > 0xf);
+// This isn't so much a "Do we write multiple render targets?" bit
+// as a "Should color0 be broadcast to all render targets?" bit. In
+// other words, it's the gl_FragCoord behavior, not gl_FragData.
+//
+// For now, we always set it to true because Vulkan requires
+// explicit fragment output locations.
+sph.set_multiple_render_target_enable(true);
+
 sph.set_kills_pixels(io.uses_kill || zs_self_dep);
 sph.set_omap_sample_mask(io.writes_sample_mask);
 sph.set_omap_depth(io.writes_depth);
diff --git a/src/nouveau/compiler/nak_nir.c b/src/nouveau/compiler/nak_nir.c
index 22df7a5a774..ac736a73098 100644
--- a/src/nouveau/compiler/nak_nir.c
+++ b/src/nouveau/compiler/nak_nir.c
@@ -986,8 +986,7 @@ nak_nir_lower_fs_outputs(nir_shader *nir)
  unreachable("EXT_shader_stencil_export not supported");
  break;
   case FRAG_RESULT_COLOR:
- assert(var->data.index == 0);
- var->data.driver_location = NAK_FS_OUT_COLOR0;
+ unreachable("Vulkan alway uses explicit locations");
  break;
   case FRAG_RESULT_SAMPLE_MASK:
  assert(var->data.index == 0);

Mesa (main): nak: Add explicit padding to nak_shader_info

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 94d96dac601ff2126996ac37a0b637961d06dfab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94d96dac601ff2126996ac37a0b637961d06dfab

Author: Faith Ekstrand 
Date:   Mon Jan  8 17:50:26 2024 -0600

nak: Add explicit padding to nak_shader_info

This ensures that the padding bits stay zero, even as we copy the
structure around through multiple languages.

Part-of: 

---

 src/nouveau/compiler/meson.build |  2 ++
 src/nouveau/compiler/nak.h   | 26 +-
 src/nouveau/compiler/nak/api.rs  | 31 ++-
 3 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/src/nouveau/compiler/meson.build b/src/nouveau/compiler/meson.build
index 535294ecf1f..f8a55046edb 100644
--- a/src/nouveau/compiler/meson.build
+++ b/src/nouveau/compiler/meson.build
@@ -78,11 +78,13 @@ nak_bindings_rs = rust.bindgen(
 '--allowlist-type', 'mesa_scope',
 '--allowlist-type', 'mesa_prim',
 '--allowlist-type', 'tess_primitive_mode',
+'--allowlist-var', 'NAK_.*',
 '--allowlist-var', 'nir_.*_infos',
 '--allowlist-function', '_mesa_shader_stage_to_string',
 '--allowlist-function', 'nak_.*',
 '--allowlist-function', 'nir_.*',
 '--allowlist-function', 'glsl_.*',
+'--explicit-padding',
 '--no-prepend-enum-name',
   ],
   dependencies : libnak_deps,
diff --git a/src/nouveau/compiler/nak.h b/src/nouveau/compiler/nak.h
index 5a3cf249401..cfec9e4f738 100644
--- a/src/nouveau/compiler/nak.h
+++ b/src/nouveau/compiler/nak.h
@@ -79,6 +79,20 @@ struct nak_xfb_info {
uint8_t attr_index[4][128];
 };
 
+/* This is an enum so bindgen will generate it */
+#define NAK_SHADER_INFO_STAGE_UNION_SIZE 12
+
+/* This struct MUST have explicit padding fields to ensure that all padding is
+ * zeroed and the zeros get properly copied, even across API boundaries.  This
+ * is ensured in two ways:
+ *
+ *  - Bindgen is invoked with --explicit-padding and if a __bindgen_paddingN
+ *member ever crops up, that tells us we need to add an explicit member
+ *here.
+ *
+ *  - There is a set of const asserts in nak/api.rs which ensure that all of
+ *the union fields are equal to NAK_SHADER_INFO_STAGE_UNION_SIZE.
+ */
 struct nak_shader_info {
gl_shader_stage stage;
 
@@ -88,6 +102,8 @@ struct nak_shader_info {
/** Number of barriers used */
uint8_t num_barriers;
 
+   uint16_t _pad0;
+
/** Size of shader local (scratch) memory */
uint32_t slm_size;
 
@@ -98,6 +114,8 @@ struct nak_shader_info {
 
  /* Shared memory size */
  uint16_t smem_size;
+
+ uint8_t _pad[4];
   } cs;
 
   struct {
@@ -106,16 +124,20 @@ struct nak_shader_info {
  bool post_depth_coverage;
  bool uses_sample_shading;
  bool early_fragment_tests;
+
+ uint8_t _pad[7];
   } fs;
 
   struct {
  enum nak_ts_domain domain;
  enum nak_ts_spacing spacing;
  enum nak_ts_prims prims;
+
+ uint8_t _pad[9];
   } ts;
 
   /* Used to initialize the union for other stages */
-  uint32_t dummy;
+  uint8_t _pad[NAK_SHADER_INFO_STAGE_UNION_SIZE];
};
 
struct {
@@ -123,6 +145,8 @@ struct nak_shader_info {
   uint8_t clip_enable;
   uint8_t cull_enable;
 
+  uint8_t _pad[1];
+
   struct nak_xfb_info xfb;
} vtg;
 
diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs
index 69ceb774feb..35fad6f2aa2 100644
--- a/src/nouveau/compiler/nak/api.rs
+++ b/src/nouveau/compiler/nak/api.rs
@@ -154,6 +154,7 @@ pub extern "C" fn nak_compiler_create(
 let nak = Box::new(nak_compiler {
 sm: dev.sm,
 nir_options: nir_options(dev),
+..unsafe { std::mem::zeroed() }
 });
 
 Box::into_raw(nak)
@@ -198,6 +199,7 @@ impl ShaderBin {
 } else {
 asm.as_ptr()
 },
+..unsafe { std::mem::zeroed() }
 };
 ShaderBin {
 bin: bin,
@@ -226,6 +228,25 @@ fn eprint_hex(label: , data: &[u32]) {
 eprintln!("");
 }
 
+const _: () = {
+assert!(
+std::mem::size_of::()
+== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
+);
+assert!(
+std::mem::size_of::()
+== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
+);
+assert!(
+std::mem::size_of::()
+== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
+);
+assert!(
+std::mem::size_of::()
+== NAK_SHADER_INFO_STAGE_UNION_SIZE as usize
+);
+};
+
 #[no_mangle]
 pub extern "C" fn nak_compile_shader(
 nir: *mut nir_shader,
@@ -304,6 +325,7 @@ pub extern "C" fn nak_compile_shader(
 max(4, s.info.num_gprs)
 },
 num_barriers: s.info.num_barriers,
+_pad0: Default::default(),
 slm_size: s.info.slm_size,
 __bindgen_anon_1: match  {
 

Mesa (main): nvk: Invalidate state after secondary command buffers

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2cab67a9f1825b21584b86fbec5d03cca671830d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cab67a9f1825b21584b86fbec5d03cca671830d

Author: Faith Ekstrand 
Date:   Mon Jan  8 09:33:32 2024 -0600

nvk: Invalidate state after secondary command buffers

Today, the only thing that this really affects is descriptor sets and
dynamic state as everything else is re-emitted almost every time.
However, as we add more dirtying, we'll need to be more and more careful
about stale state leaking across secondary command buffer executions.

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_buffer.c   | 24 
 src/nouveau/vulkan/nvk_cmd_buffer.h   |  3 +++
 src/nouveau/vulkan/nvk_cmd_dispatch.c |  6 ++
 src/nouveau/vulkan/nvk_cmd_draw.c | 19 +++
 4 files changed, 52 insertions(+)

diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c 
b/src/nouveau/vulkan/nvk_cmd_buffer.c
index 24615afb5b5..c15ce19659b 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.c
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.c
@@ -307,6 +307,9 @@ nvk_CmdExecuteCommands(VkCommandBuffer commandBuffer,
 {
VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
 
+   if (commandBufferCount == 0)
+  return;
+
nvk_cmd_buffer_flush_push(cmd);
 
for (uint32_t i = 0; i < commandBufferCount; i++) {
@@ -327,6 +330,27 @@ nvk_CmdExecuteCommands(VkCommandBuffer commandBuffer,
*/
   util_dynarray_append_dynarray(>pushes, >pushes);
}
+
+   /* From the Vulkan 1.3.275 spec:
+*
+*"When secondary command buffer(s) are recorded to execute on a
+*primary command buffer, the secondary command buffer inherits no
+*state from the primary command buffer, and all state of the primary
+*command buffer is undefined after an execute secondary command buffer
+*command is recorded. There is one exception to this rule - if the
+*primary command buffer is inside a render pass instance, then the
+*render pass and subpass state is not disturbed by executing secondary
+*command buffers. For state dependent commands (such as draws and
+*dispatches), any state consumed by those commands must not be
+*undefined."
+*
+* Therefore, it's the client's job to reset all the state in the primary
+* after the secondary executes.  However, if we're doing any internal
+* dirty tracking, we may miss the fact that a secondary has messed with
+* GPU state if we don't invalidate all our internal tracking.
+*/
+   nvk_cmd_invalidate_graphics_state(cmd);
+   nvk_cmd_invalidate_compute_state(cmd);
 }
 
 enum nvk_barrier {
diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.h 
b/src/nouveau/vulkan/nvk_cmd_buffer.h
index 32a2065dea3..86ec031f21e 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.h
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.h
@@ -204,6 +204,9 @@ void nvk_cmd_buffer_begin_graphics(struct nvk_cmd_buffer 
*cmd,
 void nvk_cmd_buffer_begin_compute(struct nvk_cmd_buffer *cmd,
   const VkCommandBufferBeginInfo *pBeginInfo);
 
+void nvk_cmd_invalidate_graphics_state(struct nvk_cmd_buffer *cmd);
+void nvk_cmd_invalidate_compute_state(struct nvk_cmd_buffer *cmd);
+
 void nvk_cmd_bind_graphics_pipeline(struct nvk_cmd_buffer *cmd,
 struct nvk_graphics_pipeline *pipeline);
 void nvk_cmd_bind_compute_pipeline(struct nvk_cmd_buffer *cmd,
diff --git a/src/nouveau/vulkan/nvk_cmd_dispatch.c 
b/src/nouveau/vulkan/nvk_cmd_dispatch.c
index c43bf377360..bbd886fb2e7 100644
--- a/src/nouveau/vulkan/nvk_cmd_dispatch.c
+++ b/src/nouveau/vulkan/nvk_cmd_dispatch.c
@@ -63,6 +63,12 @@ nvk_cmd_buffer_begin_compute(struct nvk_cmd_buffer *cmd,
}
 }
 
+void
+nvk_cmd_invalidate_compute_state(struct nvk_cmd_buffer *cmd)
+{
+   memset(>state.cs, 0, sizeof(cmd->state.cs));
+}
+
 static void
 nva0c0_qmd_set_dispatch_size(UNUSED struct nvk_device *dev, uint32_t *qmd,
  uint32_t x, uint32_t y, uint32_t z)
diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c 
b/src/nouveau/vulkan/nvk_cmd_draw.c
index 49b6e9e1d9e..4ef277c982f 100644
--- a/src/nouveau/vulkan/nvk_cmd_draw.c
+++ b/src/nouveau/vulkan/nvk_cmd_draw.c
@@ -512,6 +512,25 @@ nvk_cmd_buffer_begin_graphics(struct nvk_cmd_buffer *cmd,
}
 }
 
+void
+nvk_cmd_invalidate_graphics_state(struct nvk_cmd_buffer *cmd)
+{
+   vk_dynamic_graphics_state_dirty_all(>vk.dynamic_graphics_state);
+
+   /* From the Vulkan 1.3.275 spec:
+*
+*"...There is one exception to this rule - if the primary command
+*buffer is inside a render pass instance, then the render pass and
+*subpass state is not disturbed by executing secondary command
+*buffers."
+*
+* We need to reset everything EXCEPT the render pass state.
+*/
+   struct nvk_rendering_state render_save = cmd->state.gfx.render;
+   

Mesa (main): nvk: Set a minimum of one patch control point

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 005b5b1464518201dbb25907094268e0e0ca4cb3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=005b5b1464518201dbb25907094268e0e0ca4cb3

Author: Faith Ekstrand 
Date:   Mon Jan  8 12:00:13 2024 -0600

nvk: Set a minimum of one patch control point

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_draw.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c 
b/src/nouveau/vulkan/nvk_cmd_draw.c
index 4ef277c982f..f0b2df87922 100644
--- a/src/nouveau/vulkan/nvk_cmd_draw.c
+++ b/src/nouveau/vulkan/nvk_cmd_draw.c
@@ -1030,7 +1030,10 @@ nvk_flush_ts_state(struct nvk_cmd_buffer *cmd)
struct nv_push *p = nvk_cmd_buffer_push(cmd, 4);
 
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS)) {
-  P_IMMD(p, NV9097, SET_PATCH, dyn->ts.patch_control_points);
+  /* The hardware gets grumpy if we set this to 0 so make sure we set it
+   * to at least 1 in case it's dirty but uninitialized.
+   */
+  P_IMMD(p, NV9097, SET_PATCH, MAX2(1, dyn->ts.patch_control_points));
}
 
if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN)) {

Mesa (main): nvk: Rework descriptor set binding

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e0d907f56fd84c119af22d6b4d14c52d99fd7b0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0d907f56fd84c119af22d6b4d14c52d99fd7b0c

Author: Faith Ekstrand 
Date:   Fri Jan 12 13:53:30 2024 -0600

nvk: Rework descriptor set binding

This prepares us for VK_EXT_graphics_pipeline_library by allowing null
descriptor sets to be bound and handling holes in pipeline layouts.  We
also add a set_dynamic_buffer_start map to the root descriptor table
which says where in dynamic_buffers each set starts.  This can be used
by the pipeline layout lowering in the case where we can't statically
the dynamic buffer index for a binding.

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_buffer.c | 49 +
 src/nouveau/vulkan/nvk_cmd_buffer.h |  5 +++-
 2 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c 
b/src/nouveau/vulkan/nvk_cmd_buffer.c
index 33bbdf92df0..c20917bdb24 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.c
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.c
@@ -572,12 +572,29 @@ nvk_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
struct nvk_descriptor_state *desc =
   nvk_get_descriptors_state(cmd, pipelineBindPoint);
 
+   /* Fro the Vulkan 1.3.275 spec:
+*
+*"When binding a descriptor set (see Descriptor Set Binding) to
+*set number N...
+*
+*If, additionally, the previously bound descriptor set for set
+*N was bound using a pipeline layout not compatible for set N,
+*then all bindings in sets numbered greater than N are
+*disturbed."
+*
+* This means that, if some earlier set gets bound in such a way that
+* it changes set_dynamic_buffer_start[s], this binding is implicitly
+* invalidated.  Therefore, we can always look at the current value
+* of set_dynamic_buffer_start[s] as the base of our dynamic buffer
+* range and it's only our responsibility to adjust all
+* set_dynamic_buffer_start[p] for p > s as needed.
+*/
+   uint8_t dyn_buffer_start = desc->root.set_dynamic_buffer_start[firstSet];
+
uint32_t next_dyn_offset = 0;
for (uint32_t i = 0; i < descriptorSetCount; ++i) {
   unsigned s = i + firstSet;
   VK_FROM_HANDLE(nvk_descriptor_set, set, pDescriptorSets[i]);
-  const struct nvk_descriptor_set_layout *set_layout =
- vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[s]);
 
   if (desc->sets[s] != set) {
  desc->root.sets[s] = nvk_descriptor_set_addr(set);
@@ -589,19 +606,31 @@ nvk_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
  desc->push_dirty &= ~BITFIELD_BIT(s);
   }
 
-  if (set_layout->dynamic_buffer_count > 0) {
- const uint32_t dynamic_buffer_start =
-nvk_descriptor_set_layout_dynbuf_start(pipeline_layout, s);
+  desc->root.set_dynamic_buffer_start[s] = dyn_buffer_start;
+
+  if (pipeline_layout->set_layouts[s] != NULL) {
+ const struct nvk_descriptor_set_layout *set_layout =
+vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[s]);
 
- for (uint32_t j = 0; j < set_layout->dynamic_buffer_count; j++) {
-struct nvk_buffer_address addr = set->dynamic_buffers[j];
-addr.base_addr += pDynamicOffsets[next_dyn_offset + j];
-desc->root.dynamic_buffers[dynamic_buffer_start + j] = addr;
+ if (set != NULL && set_layout->dynamic_buffer_count > 0) {
+for (uint32_t j = 0; j < set_layout->dynamic_buffer_count; j++) {
+   struct nvk_buffer_address addr = set->dynamic_buffers[j];
+   addr.base_addr += pDynamicOffsets[next_dyn_offset + j];
+   desc->root.dynamic_buffers[dyn_buffer_start + j] = addr;
+}
+next_dyn_offset += set->layout->dynamic_buffer_count;
  }
- next_dyn_offset += set->layout->dynamic_buffer_count;
+
+ dyn_buffer_start += set_layout->dynamic_buffer_count;
+  } else {
+ assert(set == NULL);
   }
}
+   assert(dyn_buffer_start <= NVK_MAX_DYNAMIC_BUFFERS);
assert(next_dyn_offset <= dynamicOffsetCount);
+
+   for (uint32_t s = firstSet + descriptorSetCount; s < NVK_MAX_SETS; s++)
+  desc->root.set_dynamic_buffer_start[s] = dyn_buffer_start;
 }
 
 VKAPI_ATTR void VKAPI_CALL
diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.h 
b/src/nouveau/vulkan/nvk_cmd_buffer.h
index ec6042e3c73..32a2065dea3 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.h
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.h
@@ -56,8 +56,11 @@ struct nvk_root_descriptor_table {
/* Dynamic buffer bindings */
struct nvk_buffer_address dynamic_buffers[NVK_MAX_DYNAMIC_BUFFERS];
 
+   /* Start index in dynamic_buffers where each set starts */
+   uint8_t set_dynamic_buffer_start[NVK_MAX_SETS];
+
/* enfore alignment to 0x100 as needed pre pascal */
-   uint8_t 

Mesa (main): nvk: Handle missing descriptor sets in nvk_nir_lower_descriptors

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: bc36dfdb5d80c3e1d939ac881b81472c160960b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc36dfdb5d80c3e1d939ac881b81472c160960b9

Author: Faith Ekstrand 
Date:   Thu Jan  4 17:01:53 2024 -0600

nvk: Handle missing descriptor sets in nvk_nir_lower_descriptors

For VK_EXT_graphics_pipeline_library, we need to be able to handle
missing descriptor sets.  THis screws up dynamic buffers because we're
no longer guaranteed to be able to statically compute the index into
nvk_root_descriptor_table::dynamic_buffers while lowering descriptors.
Instead, we may need to look up the start index for the set in
nvk_root_descriptor_table::set_dynamic_buffer_start and compute from
there.

We also rework nvk_nir_lower_descriptors to take an array of (possibly
NULL) descriptor sets.  This ensures that we don't make any assumptions
about the pipeline layout.  It's also the interface we'll want for
implementing VK_EXT_shader_object.

Part-of: 

---

 src/nouveau/vulkan/nvk_descriptor_set_layout.c | 17 --
 src/nouveau/vulkan/nvk_descriptor_set_layout.h |  3 --
 src/nouveau/vulkan/nvk_nir_lower_descriptors.c | 73 +++---
 src/nouveau/vulkan/nvk_shader.c|  3 +-
 src/nouveau/vulkan/nvk_shader.h|  4 +-
 5 files changed, 58 insertions(+), 42 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_descriptor_set_layout.c 
b/src/nouveau/vulkan/nvk_descriptor_set_layout.c
index d5796660e93..35dec3c4b55 100644
--- a/src/nouveau/vulkan/nvk_descriptor_set_layout.c
+++ b/src/nouveau/vulkan/nvk_descriptor_set_layout.c
@@ -403,20 +403,3 @@ nvk_GetDescriptorSetLayoutSupport(VkDevice device,
   }
}
 }
-
-uint8_t
-nvk_descriptor_set_layout_dynbuf_start(const struct vk_pipeline_layout 
*pipeline_layout,
- int set_layout_idx)
-{
-   uint8_t dynamic_buffer_start = 0;
-
-   assert(set_layout_idx <= pipeline_layout->set_count);
-
-   for (uint32_t i = 0; i < set_layout_idx; i++) {
-  const struct nvk_descriptor_set_layout *set_layout =
- vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[i]);
-
-  dynamic_buffer_start += set_layout->dynamic_buffer_count;
-   }
-   return dynamic_buffer_start;
-}
diff --git a/src/nouveau/vulkan/nvk_descriptor_set_layout.h 
b/src/nouveau/vulkan/nvk_descriptor_set_layout.h
index d23b65acb57..d1d7e6b3a80 100644
--- a/src/nouveau/vulkan/nvk_descriptor_set_layout.h
+++ b/src/nouveau/vulkan/nvk_descriptor_set_layout.h
@@ -75,7 +75,4 @@ vk_to_nvk_descriptor_set_layout(struct 
vk_descriptor_set_layout *layout)
return container_of(layout, struct nvk_descriptor_set_layout, vk);
 }
 
-uint8_t
-nvk_descriptor_set_layout_dynbuf_start(const struct vk_pipeline_layout 
*pipeline_layout,
-   int set_layout_idx);
 #endif
diff --git a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c 
b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
index 0e57eb2acd9..44028dc29f3 100644
--- a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
+++ b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
@@ -8,7 +8,6 @@
 #include "nvk_shader.h"
 
 #include "vk_pipeline.h"
-#include "vk_pipeline_layout.h"
 
 #include "nir_builder.h"
 #include "nir_deref.h"
@@ -59,7 +58,8 @@ compar_cbufs(const void *_a, const void *_b)
 }
 
 struct lower_descriptors_ctx {
-   const struct vk_pipeline_layout *layout;
+   const struct nvk_descriptor_set_layout *set_layouts[NVK_MAX_SETS];
+
bool clamp_desc_array_bounds;
nir_address_format ubo_addr_format;
nir_address_format ssbo_addr_format;
@@ -95,11 +95,10 @@ static const struct nvk_descriptor_set_binding_layout *
 get_binding_layout(uint32_t set, uint32_t binding,
const struct lower_descriptors_ctx *ctx)
 {
-   const struct vk_pipeline_layout *layout = ctx->layout;
+   assert(set < NVK_MAX_SETS);
+   assert(ctx->set_layouts[set] != NULL);
 
-   assert(set < layout->set_count);
-   const struct nvk_descriptor_set_layout *set_layout =
-  vk_to_nvk_descriptor_set_layout(layout->set_layouts[set]);
+   const struct nvk_descriptor_set_layout *set_layout = ctx->set_layouts[set];
 
assert(binding < set_layout->binding_count);
return _layout->binding[binding];
@@ -519,6 +518,33 @@ load_descriptor_set_addr(nir_builder *b, uint32_t set,
.align_mul = 8, .align_offset = 0, .range = ~0);
 }
 
+static nir_def *
+load_dynamic_buffer_start(nir_builder *b, uint32_t set,
+  const struct lower_descriptors_ctx *ctx)
+{
+   int dynamic_buffer_start_imm = 0;
+   for (uint32_t s = 0; s < set; s++) {
+  if (ctx->set_layouts[s] == NULL) {
+ dynamic_buffer_start_imm = -1;
+ break;
+  }
+
+  dynamic_buffer_start_imm += ctx->set_layouts[s]->dynamic_buffer_count;
+   }
+
+   if (dynamic_buffer_start_imm >= 0) {
+  return nir_imm_int(b, dynamic_buffer_start_imm);
+   } else {
+  

Mesa (main): nvk: Add an explicit mapping from shader stages to cbuf bindings

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f62b5582ea398bba0bbc67006ac4ed5f34b5a77a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f62b5582ea398bba0bbc67006ac4ed5f34b5a77a

Author: Faith Ekstrand 
Date:   Fri Jan  5 11:29:25 2024 -0600

nvk: Add an explicit mapping from shader stages to cbuf bindings

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_draw.c  | 29 ++---
 src/nouveau/vulkan/nvk_graphics_pipeline.c |  2 +-
 src/nouveau/vulkan/nvk_shader.h|  6 ++
 3 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c 
b/src/nouveau/vulkan/nvk_cmd_draw.c
index 5cbf6b978c8..49b6e9e1d9e 100644
--- a/src/nouveau/vulkan/nvk_cmd_draw.c
+++ b/src/nouveau/vulkan/nvk_cmd_draw.c
@@ -1881,16 +1881,25 @@ nvk_flush_descriptors(struct nvk_cmd_buffer *cmd)
desc->root.root_desc_addr = root_desc_addr;
memcpy(root_desc_map, >root, sizeof(desc->root));
 
-   uint32_t root_cbuf_count = 0;
+   /* Find cbuf maps for the 5 cbuf groups */
+   const struct nvk_cbuf_map *cbuf_maps[5] = { NULL, };
for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
   const struct nvk_shader *shader = pipeline->base.shaders[stage];
   if (!shader || shader->code_size == 0)
  continue;
 
-  uint32_t group = stage;
+  uint32_t group = nvk_cbuf_binding_for_stage(stage);
+  assert(group < ARRAY_SIZE(cbuf_maps));
+  cbuf_maps[group] = >cbuf_map;
+   }
+
+   uint32_t root_cbuf_count = 0;
+   for (uint32_t group = 0; group < ARRAY_SIZE(cbuf_maps); group++) {
+  if (cbuf_maps[group] == NULL)
+ continue;
 
-  for (uint32_t c = 0; c < shader->cbuf_map.cbuf_count; c++) {
- const struct nvk_cbuf *cbuf = >cbuf_map.cbufs[c];
+  for (uint32_t c = 0; c < cbuf_maps[group]->cbuf_count; c++) {
+ const struct nvk_cbuf *cbuf = _maps[group]->cbufs[c];
 
  /* We bind these at the very end */
  if (cbuf->type == NVK_CBUF_TYPE_ROOT_DESC) {
@@ -1952,15 +1961,13 @@ nvk_flush_descriptors(struct nvk_cmd_buffer *cmd)
P_NV9097_SET_CONSTANT_BUFFER_SELECTOR_B(p, root_desc_addr >> 32);
P_NV9097_SET_CONSTANT_BUFFER_SELECTOR_C(p, root_desc_addr);
 
-   for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
-  const struct nvk_shader *shader = pipeline->base.shaders[stage];
-  if (!shader || shader->code_size == 0)
+   for (uint32_t group = 0; group < ARRAY_SIZE(cbuf_maps); group++) {
+  if (cbuf_maps[group] == NULL)
  continue;
 
-  uint32_t group = stage;
-
-  for (uint32_t c = 0; c < shader->cbuf_map.cbuf_count; c++) {
- if (shader->cbuf_map.cbufs[c].type == NVK_CBUF_TYPE_ROOT_DESC) {
+  for (uint32_t c = 0; c < cbuf_maps[group]->cbuf_count; c++) {
+ const struct nvk_cbuf *cbuf = _maps[group]->cbufs[c];
+ if (cbuf->type == NVK_CBUF_TYPE_ROOT_DESC) {
 P_IMMD(p, NV9097, BIND_GROUP_CONSTANT_BUFFER(group), {
.valid = VALID_TRUE,
.shader_slot = c,
diff --git a/src/nouveau/vulkan/nvk_graphics_pipeline.c 
b/src/nouveau/vulkan/nvk_graphics_pipeline.c
index a3911e4eab3..9be4786fa25 100644
--- a/src/nouveau/vulkan/nvk_graphics_pipeline.c
+++ b/src/nouveau/vulkan/nvk_graphics_pipeline.c
@@ -352,7 +352,7 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
 
   P_MTHD(p, NVC397, SET_PIPELINE_REGISTER_COUNT(idx));
   P_NVC397_SET_PIPELINE_REGISTER_COUNT(p, idx, shader->info.num_gprs);
-  P_NVC397_SET_PIPELINE_BINDING(p, idx, stage);
+  P_NVC397_SET_PIPELINE_BINDING(p, idx, nvk_cbuf_binding_for_stage(stage));
 
   switch (stage) {
   case MESA_SHADER_VERTEX:
diff --git a/src/nouveau/vulkan/nvk_shader.h b/src/nouveau/vulkan/nvk_shader.h
index dae7e6fef1b..867a97c51f2 100644
--- a/src/nouveau/vulkan/nvk_shader.h
+++ b/src/nouveau/vulkan/nvk_shader.h
@@ -27,6 +27,12 @@ struct vk_shader_module;
 #define TU102_SHADER_HEADER_SIZE (32 * 4)
 #define NVC0_MAX_SHADER_HEADER_SIZE TU102_SHADER_HEADER_SIZE
 
+static inline uint32_t
+nvk_cbuf_binding_for_stage(gl_shader_stage stage)
+{
+   return stage;
+}
+
 enum ENUM_PACKED nvk_cbuf_type {
NVK_CBUF_TYPE_INVALID = 0,
NVK_CBUF_TYPE_ROOT_DESC,

Mesa (main): nvk: Use s instead of set_idx in CmdBindDescriptorSets

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a11adbe40845d9cb60f71cc3ca2d43f3a78a7b3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a11adbe40845d9cb60f71cc3ca2d43f3a78a7b3c

Author: Faith Ekstrand 
Date:   Fri Jan 12 13:30:17 2024 -0600

nvk: Use s instead of set_idx in CmdBindDescriptorSets

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_buffer.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c 
b/src/nouveau/vulkan/nvk_cmd_buffer.c
index b8828b7d350..33bbdf92df0 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.c
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.c
@@ -574,24 +574,24 @@ nvk_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
 
uint32_t next_dyn_offset = 0;
for (uint32_t i = 0; i < descriptorSetCount; ++i) {
-  unsigned set_idx = i + firstSet;
+  unsigned s = i + firstSet;
   VK_FROM_HANDLE(nvk_descriptor_set, set, pDescriptorSets[i]);
   const struct nvk_descriptor_set_layout *set_layout =
- 
vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[set_idx]);
+ vk_to_nvk_descriptor_set_layout(pipeline_layout->set_layouts[s]);
 
-  if (desc->sets[set_idx] != set) {
- desc->root.sets[set_idx] = nvk_descriptor_set_addr(set);
- desc->set_sizes[set_idx] = set->size;
- desc->sets[set_idx] = set;
- desc->sets_dirty |= BITFIELD_BIT(set_idx);
+  if (desc->sets[s] != set) {
+ desc->root.sets[s] = nvk_descriptor_set_addr(set);
+ desc->set_sizes[s] = set->size;
+ desc->sets[s] = set;
+ desc->sets_dirty |= BITFIELD_BIT(s);
 
  /* Binding descriptors invalidates push descriptors */
- desc->push_dirty &= ~BITFIELD_BIT(set_idx);
+ desc->push_dirty &= ~BITFIELD_BIT(s);
   }
 
   if (set_layout->dynamic_buffer_count > 0) {
  const uint32_t dynamic_buffer_start =
-nvk_descriptor_set_layout_dynbuf_start(pipeline_layout, set_idx);
+nvk_descriptor_set_layout_dynbuf_start(pipeline_layout, s);
 
  for (uint32_t j = 0; j < set_layout->dynamic_buffer_count; j++) {
 struct nvk_buffer_address addr = set->dynamic_buffers[j];

Mesa (main): nvk: Return an nvk_cbuf_map from nvk_lower_nir()

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2d5c04ee4aa655bef250b246077e2618c265c421
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d5c04ee4aa655bef250b246077e2618c265c421

Author: Faith Ekstrand 
Date:   Thu Jan  4 16:42:35 2024 -0600

nvk: Return an nvk_cbuf_map from nvk_lower_nir()

There's no need to pass in the whole shader when the only part we're
going to write is the cbuf map.

Part-of: 

---

 src/nouveau/vulkan/nvk_compute_pipeline.c  | 3 ++-
 src/nouveau/vulkan/nvk_graphics_pipeline.c | 3 ++-
 src/nouveau/vulkan/nvk_shader.c| 6 +++---
 src/nouveau/vulkan/nvk_shader.h| 2 +-
 4 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_compute_pipeline.c 
b/src/nouveau/vulkan/nvk_compute_pipeline.c
index b901b8bcb96..bec98c4b3d3 100644
--- a/src/nouveau/vulkan/nvk_compute_pipeline.c
+++ b/src/nouveau/vulkan/nvk_compute_pipeline.c
@@ -214,7 +214,8 @@ nvk_compute_pipeline_create(struct nvk_device *dev,
   if(shader == NULL)
  return vk_error(dev, VK_ERROR_OUT_OF_HOST_MEMORY);
 
-  nvk_lower_nir(dev, nir, , false, pipeline_layout, shader);
+  nvk_lower_nir(dev, nir, , false, pipeline_layout,
+>cbuf_map);
 
   result = nvk_compile_nir(dev, nir, pipeline_flags, , NULL, 
cache, shader);
 
diff --git a/src/nouveau/vulkan/nvk_graphics_pipeline.c 
b/src/nouveau/vulkan/nvk_graphics_pipeline.c
index 9be4786fa25..61b489bb01a 100644
--- a/src/nouveau/vulkan/nvk_graphics_pipeline.c
+++ b/src/nouveau/vulkan/nvk_graphics_pipeline.c
@@ -287,7 +287,8 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
  }
 
  nvk_lower_nir(dev, nir[stage], [stage],
-   state.rp->view_mask != 0, pipeline_layout, shader);
+   state.rp->view_mask != 0, pipeline_layout,
+   >cbuf_map);
 
  result = nvk_compile_nir(dev, nir[stage],
   pipeline_flags, [stage],
diff --git a/src/nouveau/vulkan/nvk_shader.c b/src/nouveau/vulkan/nvk_shader.c
index 14cca62ab17..359b48f3601 100644
--- a/src/nouveau/vulkan/nvk_shader.c
+++ b/src/nouveau/vulkan/nvk_shader.c
@@ -303,7 +303,7 @@ nvk_lower_nir(struct nvk_device *dev, nir_shader *nir,
   const struct vk_pipeline_robustness_state *rs,
   bool is_multiview,
   const struct vk_pipeline_layout *layout,
-  struct nvk_shader *shader)
+  struct nvk_cbuf_map *cbuf_map_out)
 {
struct nvk_physical_device *pdev = nvk_device_physical(dev);
 
@@ -357,13 +357,13 @@ nvk_lower_nir(struct nvk_device *dev, nir_shader *nir,
struct nvk_cbuf_map *cbuf_map = NULL;
if (use_nak(pdev, nir->info.stage) &&
!(pdev->debug_flags & NVK_DEBUG_NO_CBUF)) {
-  cbuf_map = >cbuf_map;
+  cbuf_map = cbuf_map_out;
} else {
   /* Codegen sometimes puts stuff in cbuf 1 and adds 1 to our cbuf indices
* so we can't really rely on it for lowering to cbufs and instead place
* the root descriptors in both cbuf 0 and cbuf 1.
*/
-  shader->cbuf_map = (struct nvk_cbuf_map) {
+  *cbuf_map_out = (struct nvk_cbuf_map) {
  .cbuf_count = 2,
  .cbufs = {
 { .type = NVK_CBUF_TYPE_ROOT_DESC },
diff --git a/src/nouveau/vulkan/nvk_shader.h b/src/nouveau/vulkan/nvk_shader.h
index 867a97c51f2..5bedf488422 100644
--- a/src/nouveau/vulkan/nvk_shader.h
+++ b/src/nouveau/vulkan/nvk_shader.h
@@ -125,7 +125,7 @@ nvk_lower_nir(struct nvk_device *dev, nir_shader *nir,
   const struct vk_pipeline_robustness_state *rs,
   bool is_multiview,
   const struct vk_pipeline_layout *layout,
-  struct nvk_shader *shader);
+  struct nvk_cbuf_map *cbuf_map_out);
 
 VkResult
 nvk_compile_nir(struct nvk_device *dev, nir_shader *nir,

Mesa (main): nvk: Make dynamic cbuf indices relative to the descriptor set

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3197aff4e8ff47708b825f272322e759591d7f79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3197aff4e8ff47708b825f272322e759591d7f79

Author: Faith Ekstrand 
Date:   Fri Jan 12 15:19:06 2024 -0600

nvk: Make dynamic cbuf indices relative to the descriptor set

Part-of: 

---

 src/nouveau/vulkan/nvk_cmd_buffer.c| 7 +--
 src/nouveau/vulkan/nvk_nir_lower_descriptors.c | 7 ++-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/nouveau/vulkan/nvk_cmd_buffer.c 
b/src/nouveau/vulkan/nvk_cmd_buffer.c
index c20917bdb24..24615afb5b5 100644
--- a/src/nouveau/vulkan/nvk_cmd_buffer.c
+++ b/src/nouveau/vulkan/nvk_cmd_buffer.c
@@ -758,9 +758,12 @@ nvk_cmd_buffer_get_cbuf_descriptor(struct nvk_cmd_buffer 
*cmd,
   };
   return true;
 
-   case NVK_CBUF_TYPE_DYNAMIC_UBO:
-  *desc_out = desc->root.dynamic_buffers[cbuf->dynamic_idx];
+   case NVK_CBUF_TYPE_DYNAMIC_UBO: {
+  const uint32_t dyn_start =
+ desc->root.set_dynamic_buffer_start[cbuf->desc_set];
+  *desc_out = desc->root.dynamic_buffers[dyn_start + cbuf->dynamic_idx];
   return true;
+   }
 
case NVK_CBUF_TYPE_UBO_DESC: {
   if (desc->sets[cbuf->desc_set] != NULL)
diff --git a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c 
b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
index 98324ccf2e3..0e57eb2acd9 100644
--- a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
+++ b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c
@@ -291,17 +291,14 @@ ubo_deref_to_cbuf(nir_deref_instr *deref,
}
 
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: {
-  uint8_t dynamic_buffer_index =
- nvk_descriptor_set_layout_dynbuf_start(ctx->layout, set) +
- binding_layout->dynamic_buffer_index + index;
-
   *offset_out = 0;
   *start_out = offset;
   *end_out = offset + range;
 
   return (struct nvk_cbuf) {
  .type = NVK_CBUF_TYPE_DYNAMIC_UBO,
- .dynamic_idx = dynamic_buffer_index,
+ .desc_set = set,
+ .dynamic_idx = binding_layout->dynamic_buffer_index + index,
   };
}
 

Mesa (main): Revert "v3d: show warning on creating a v3d screen on real hw"

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8120360358663af237562a7c81313087a23f8dd6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8120360358663af237562a7c81313087a23f8dd6

Author: Juan A. Suarez Romero 
Date:   Fri Jan 12 23:17:07 2024 +0100

Revert "v3d: show warning on creating a v3d screen on real hw"

There are paths were a v3d screen can be created instead of vc4 screen,
in a real rpi4 hardware. For instance, in the CI itself.

So assuming that it was only possible with the simulator was wrong.

This reverts commit c31be1f4bacde88ccd7177af26cb554c35472573.

Part-of: 

---

 src/gallium/winsys/v3d/drm/meson.build  | 8 
 src/gallium/winsys/v3d/drm/v3d_drm_winsys.c | 4 
 2 files changed, 12 deletions(-)

diff --git a/src/gallium/winsys/v3d/drm/meson.build 
b/src/gallium/winsys/v3d/drm/meson.build
index 258033bbae5..3d3cc5b3f01 100644
--- a/src/gallium/winsys/v3d/drm/meson.build
+++ b/src/gallium/winsys/v3d/drm/meson.build
@@ -18,13 +18,6 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-dep_v3dv3 = dependency('v3dv3', required: false)
-
-v3d_winsys_c_args = []
-if (dep_v3dv3.found())
-  v3d_winsys_c_args += '-DUSE_V3D_SIMULATOR'
-endif
-
 libv3dwinsys = static_library(
   'v3dwinsys',
   files('v3d_drm_winsys.c'),
@@ -32,7 +25,6 @@ libv3dwinsys = static_library(
 inc_src, inc_include,
 inc_gallium, inc_gallium_aux, inc_gallium_drivers,
   ],
-  c_args: [v3d_winsys_c_args],
   gnu_symbol_visibility : 'hidden',
   dependencies : idep_mesautil,
 )
diff --git a/src/gallium/winsys/v3d/drm/v3d_drm_winsys.c 
b/src/gallium/winsys/v3d/drm/v3d_drm_winsys.c
index 7185e0d8d93..0386cde886e 100644
--- a/src/gallium/winsys/v3d/drm/v3d_drm_winsys.c
+++ b/src/gallium/winsys/v3d/drm/v3d_drm_winsys.c
@@ -34,10 +34,6 @@
 struct pipe_screen *
 v3d_drm_screen_create(int fd, const struct pipe_screen_config *config)
 {
-#ifndef USE_V3D_SIMULATOR
-   fprintf (stderr, "Do not manually force v3d driver; hardware uses vc4 to 
create display\n");
-#endif
-
return u_pipe_screen_lookup_or_create(os_dupfd_cloexec(fd), config,
  NULL, v3d_screen_create);
 }

Mesa (main): mesa: Consider mesa format in addition to internal format for mip/cube completeness

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 4cb9c77e8e08507b5c181a480259e42b43dd647e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cb9c77e8e08507b5c181a480259e42b43dd647e

Author: Jesse Natalie 
Date:   Thu Jan 11 15:46:07 2024 -0800

mesa: Consider mesa format in addition to internal format for mip/cube 
completeness

Prior to 06b526de, the mesa format was used for these completeness checks.
That was to address the case where a *different* internal format selected
the *same* mesa format, and the texture shouldn't be considered compatible.
But this didn't address the case where the *same* internal format selected
a *different* mesa format, e.g. because the type passed to the TexImage
API was different.

An old WGL demo app called TexFilter.exe tries to redefine a mipped RGBA16
texture as RGBA8. This incorrect logic caused Mesa to try to copy the RGBA16
data from the smaller mips into the newly created RGBA8 data, because it
thought that the texture was still mip-complete, despite the format changing.

Cc: mesa-stable
Reviewed-By: Mike Blumenkrantz 
Part-of: 

---

 src/mesa/main/texobj.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 20e14ee21ee..5c960c730bf 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -817,7 +817,8 @@ _mesa_test_texobj_completeness( const struct gl_context 
*ctx,
 return;
  }
  if (t->Image[face][baseLevel]->InternalFormat !=
- baseImage->InternalFormat) {
+ baseImage->InternalFormat ||
+ t->Image[face][baseLevel]->TexFormat != baseImage->TexFormat) {
 incomplete(t, BASE, "Cube face format mismatch");
 return;
  }
@@ -876,7 +877,8 @@ _mesa_test_texobj_completeness( const struct gl_context 
*ctx,
   incomplete(t, MIPMAP, "TexImage[%d] is missing", i);
   return;
}
-   if (img->InternalFormat != baseImage->InternalFormat) {
+   if (img->InternalFormat != baseImage->InternalFormat ||
+   img->TexFormat != baseImage->TexFormat) {
   incomplete(t, MIPMAP, "Format[i] != Format[baseLevel]");
   return;
}

Mesa (main): clc: add support for the native spir-v backend

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 75ff6ca470dcceaba317877e636968278a044ac2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75ff6ca470dcceaba317877e636968278a044ac2

Author: Karol Herbst 
Date:   Tue Jan  9 19:49:47 2024 +0100

clc: add support for the native spir-v backend

This allows us to easily test if the LLVM SPIR-V backend is viable to
replace the translator.

Signed-off-by: Karol Herbst 
Part-of: 

---

 src/compiler/clc/clc.h |  1 +
 src/compiler/clc/clc_helpers.cpp   | 45 ++
 .../frontends/rusticl/mesa/compiler/clc/spirv.rs   |  1 +
 3 files changed, 47 insertions(+)

diff --git a/src/compiler/clc/clc.h b/src/compiler/clc/clc.h
index 9d736b16e66..f359fd16892 100644
--- a/src/compiler/clc/clc.h
+++ b/src/compiler/clc/clc.h
@@ -78,6 +78,7 @@ struct clc_compile_args {
/* SPIRV version to target. */
enum clc_spirv_version spirv_version;
struct clc_optional_features features;
+   bool use_llvm_spirv_target;
 
/* Allowed extensions SPIRV extensions the OpenCL->SPIRV translation can
 * enable. A pointer to a NULL terminated array of strings, allow any
diff --git a/src/compiler/clc/clc_helpers.cpp b/src/compiler/clc/clc_helpers.cpp
index 93186b5775a..589feddb114 100644
--- a/src/compiler/clc/clc_helpers.cpp
+++ b/src/compiler/clc/clc_helpers.cpp
@@ -30,8 +30,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -74,9 +77,11 @@ constexpr spv_target_env spirv_target = 
SPV_ENV_UNIVERSAL_1_5;
 constexpr SPIRV::VersionNumber invalid_spirv_trans_version = 
static_cast(0);
 
 using ::llvm::Function;
+using ::llvm::legacy::PassManager;
 using ::llvm::LLVMContext;
 using ::llvm::Module;
 using ::llvm::raw_string_ostream;
+using ::llvm::TargetRegistry;
 using ::clang::driver::Driver;
 
 static void
@@ -1052,6 +1057,46 @@ llvm_mod_to_spirv(std::unique_ptr<::llvm::Module> mod,
spirv_opts.setPreserveOCLKernelArgTypeMetadataThroughString(true);
 #endif
 
+#if LLVM_VERSION_MAJOR >= 17
+   if (args->use_llvm_spirv_target) {
+  const char *triple = args->address_bits == 32 ? "spirv-unknown-unknown" 
: "spirv64-unknown-unknown";
+  std::string error_msg("");
+  auto target = TargetRegistry::lookupTarget(triple, error_msg);
+  if (target) {
+ auto TM = target->createTargetMachine(
+triple, "", "", {}, std::nullopt, std::nullopt,
+#if LLVM_VERSION_MAJOR >= 18
+::llvm::CodeGenOptLevel::None
+#else
+::llvm::CodeGenOpt::None
+#endif
+ );
+
+ auto PM = PassManager();
+ ::llvm::SmallVector buf;
+ auto OS = ::llvm::raw_svector_ostream(buf);
+ TM->addPassesToEmitFile(
+PM, OS, nullptr,
+#if LLVM_VERSION_MAJOR >= 18
+::llvm::CodeGenFileType::ObjectFile
+#else
+::llvm::CGFT_ObjectFile
+#endif
+ );
+
+ PM.run(*mod);
+
+ out_spirv->size = buf.size_in_bytes();
+ out_spirv->data = malloc(out_spirv->size);
+ memcpy(out_spirv->data, buf.data(), out_spirv->size);
+ return 0;
+  } else {
+ clc_error(logger, "LLVM SPIR-V target not found.\n");
+ return -1;
+  }
+   }
+#endif
+
std::ostringstream spv_stream;
if (!::llvm::writeSpirv(mod.get(), spirv_opts, spv_stream, log)) {
   clc_error(logger, "%sTranslation from LLVM IR to SPIR-V failed.\n",
diff --git a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs 
b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs
index e6d8214eaa1..e0fab75afa9 100644
--- a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs
+++ b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs
@@ -143,6 +143,7 @@ impl SPIRVBin {
 num_args: c_args.len() as u32,
 spirv_version: clc_spirv_version::CLC_SPIRV_VERSION_MAX,
 features: features,
+use_llvm_spirv_target: false,
 allowed_spirv_extensions: spirv_extensions.as_ptr(),
 address_bits: address_bits,
 };

Mesa (main): clc: use spirv triple starting with llvm-17

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 22fa315ee0622b73956cebf8375497f3ccb8d456
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22fa315ee0622b73956cebf8375497f3ccb8d456

Author: Karol Herbst 
Date:   Tue Jan  9 19:34:05 2024 +0100

clc: use spirv triple starting with llvm-17

It's supported since a while and shouldn't regress anything.

Signed-off-by: Karol Herbst 
Part-of: 

---

 src/compiler/clc/clc_helpers.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/clc/clc_helpers.cpp b/src/compiler/clc/clc_helpers.cpp
index 49e4f36000b..93186b5775a 100644
--- a/src/compiler/clc/clc_helpers.cpp
+++ b/src/compiler/clc/clc_helpers.cpp
@@ -775,7 +775,11 @@ clc_compile_to_llvm_module(LLVMContext _ctx,
>getDiagnosticOpts())
};
 
+#if LLVM_VERSION_MAJOR >= 17
+   const char *triple = args->address_bits == 32 ? "spirv-unknown-unknown" : 
"spirv64-unknown-unknown";
+#else
const char *triple = args->address_bits == 32 ? "spir-unknown-unknown" : 
"spir64-unknown-unknown";
+#endif
 
std::vector clang_opts = {
   args->source.name,

Mesa (main): anv: Fix PAT entry for userptr in integrated GPUs

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 49fe060b5f39eb673b0c6a8757730386c6ce5570
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49fe060b5f39eb673b0c6a8757730386c6ce5570

Author: José Roberto de Souza 
Date:   Fri Jan 12 08:31:31 2024 -0800

anv: Fix PAT entry for userptr in integrated GPUs

Fixes: 060439bdf0e7 ("anv: Add ANV_BO_ALLOC_IMPORTED")
Signed-off-by: José Roberto de Souza 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 src/intel/vulkan/anv_device.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 97861da01b9..612caa5c553 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -5116,13 +5116,15 @@ const struct intel_device_info_pat_entry *
 anv_device_get_pat_entry(struct anv_device *device,
  enum anv_bo_alloc_flags alloc_flags)
 {
+   if (alloc_flags & ANV_BO_ALLOC_IMPORTED)
+  return >info->pat.cached_coherent;
+
/* PAT indexes has no actual effect in DG2 and DG1, smem caches will always
 * be snopped by GPU and lmem will always be WC.
 * This might change in future discrete platforms.
 */
if (anv_physical_device_has_vram(device->physical)) {
-  if ((alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM) ||
-  (alloc_flags & ANV_BO_ALLOC_IMPORTED))
+  if (alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM)
  return >info->pat.cached_coherent;
   return >info->pat.writecombining;
}

Mesa (main): zink: hook up maint6

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 33282e750452860918149c0ef6e16c795d3607d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33282e750452860918149c0ef6e16c795d3607d8

Author: Mike Blumenkrantz 
Date:   Tue Jan  9 09:03:28 2024 -0500

zink: hook up maint6

Part-of: 

---

 src/gallium/drivers/zink/zink_device_info.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/zink/zink_device_info.py 
b/src/gallium/drivers/zink/zink_device_info.py
index c7d2aa4be4a..c35a700e397 100644
--- a/src/gallium/drivers/zink/zink_device_info.py
+++ b/src/gallium/drivers/zink/zink_device_info.py
@@ -69,6 +69,9 @@ EXTENSIONS = [
 Extension("VK_KHR_maintenance5",
   alias="maint5",
   features=True, properties=True),
+Extension("VK_KHR_maintenance6",
+  alias="maint6",
+  features=True, properties=True),
 Extension("VK_KHR_external_memory"),
 Extension("VK_KHR_external_memory_fd"),
 Extension("VK_KHR_vulkan_memory_model"),

Mesa (main): zink: use maint6 for multi-layer compressed surface creation

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8929257352d127feaaaf764d019b83803b9a325c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8929257352d127feaaaf764d019b83803b9a325c

Author: Mike Blumenkrantz 
Date:   Tue Jan  9 09:03:52 2024 -0500

zink: use maint6 for multi-layer compressed surface creation

this should speed up multi-layer copying

Part-of: 

---

 src/gallium/drivers/zink/zink_surface.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/zink/zink_surface.c 
b/src/gallium/drivers/zink/zink_surface.c
index 16a92624bf5..31a57e85c85 100644
--- a/src/gallium/drivers/zink/zink_surface.c
+++ b/src/gallium/drivers/zink/zink_surface.c
@@ -304,8 +304,11 @@ zink_create_surface(struct pipe_context *pctx,
  If image was created with the 
VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT flag and
  format is a non-compressed format, the levelCount and layerCount 
members of
  subresourceRange must both be 1
+
+ ...but this is allowed with a maintenance6 property
*/
-  if (util_format_is_compressed(pres->format) && templ->u.tex.first_layer 
!= templ->u.tex.last_layer)
+  if (util_format_is_compressed(pres->format) && templ->u.tex.first_layer 
!= templ->u.tex.last_layer &&
+  (!screen->info.have_KHR_maintenance6 || 
!screen->info.maint6_props.blockTexelViewCompatibleMultipleLayers))
  return NULL;
}
 

Mesa (main): zink: use local screen variable in surface creation

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 4ccc91de17014bc5e36ec8b1b4963348ac331b88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ccc91de17014bc5e36ec8b1b4963348ac331b88

Author: Mike Blumenkrantz 
Date:   Tue Jan  9 09:03:10 2024 -0500

zink: use local screen variable in surface creation

no functional changes

Part-of: 

---

 src/gallium/drivers/zink/zink_surface.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/zink/zink_surface.c 
b/src/gallium/drivers/zink/zink_surface.c
index 0bf7ec28e3b..16a92624bf5 100644
--- a/src/gallium/drivers/zink/zink_surface.c
+++ b/src/gallium/drivers/zink/zink_surface.c
@@ -292,6 +292,7 @@ zink_create_surface(struct pipe_context *pctx,
 const struct pipe_surface *templ)
 {
struct zink_resource *res = zink_resource(pres);
+   struct zink_screen *screen = zink_screen(pctx->screen);
bool is_array = templ->u.tex.last_layer != templ->u.tex.first_layer;
bool needs_mutable = false;
enum pipe_texture_target target_2d[] = {PIPE_TEXTURE_2D, 
PIPE_TEXTURE_2D_ARRAY};
@@ -308,16 +309,16 @@ zink_create_surface(struct pipe_context *pctx,
  return NULL;
}
 
-   if (!zink_screen(pctx->screen)->threaded && needs_mutable) {
+   if (!screen->threaded && needs_mutable) {
   /* this is fine without tc */
   needs_mutable = false;
   zink_resource_object_init_mutable(zink_context(pctx), res);
}
 
-   if (!zink_get_format(zink_screen(pctx->screen), templ->format))
+   if (!zink_get_format(screen, templ->format))
   return NULL;
 
-   VkImageViewCreateInfo ivci = create_ivci(zink_screen(pctx->screen), res, 
templ,
+   VkImageViewCreateInfo ivci = create_ivci(screen, res, templ,
 pres->target == PIPE_TEXTURE_3D ? 
target_2d[is_array] : pres->target);
 
struct pipe_surface *psurf = NULL;
@@ -342,7 +343,7 @@ zink_create_surface(struct pipe_context *pctx,
   init_pipe_surface_info(pctx, >base, templ, pres);
}
 
-   if (templ->nr_samples && 
!zink_screen(pctx->screen)->info.have_EXT_multisampled_render_to_single_sampled)
 {
+   if (templ->nr_samples && 
!screen->info.have_EXT_multisampled_render_to_single_sampled) {
   /* transient fb attachment: not cached */
   struct pipe_resource rtempl = *pres;
   rtempl.nr_samples = templ->nr_samples;