Re: [Mesa-dev] [PATCH] clover: restore support for LLVM <= 3.9

[Jan Vesely]

On Tue, 2016-11-15 at 05:32 +0100, Vedran Miletić wrote:
> The commit 8e430ff8b060b4e8e922bae24b3c57837da6ea77 broke 3.9 and older
> versions of LLVM for Clover. This patch restores it and refactors the
> support using Clover compatibility layer for LLVM.
> 
> Signed-off-by: Vedran Miletić 
> ---
>  .../state_trackers/clover/llvm/codegen/bitcode.cpp |  9 ++-
>  src/gallium/state_trackers/clover/llvm/compat.hpp  | 30 
> ++
>  2 files changed, 32 insertions(+), 7 deletions(-)
> 
> diff --git a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp 
> b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> index 5dcc4f8..4b4ae41 100644
> --- a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> +++ b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> @@ -32,6 +32,7 @@
>  ///
>  
>  #include "llvm/codegen.hpp"
> +#include "llvm/compat.hpp"
>  #include "llvm/metadata.hpp"
>  #include "core/error.hpp"
>  #include "util/algorithm.hpp"
> @@ -99,13 +100,7 @@ clover::llvm::parse_module_library(const module , 
> ::llvm::LLVMContext ,
> auto mod = ::llvm::parseBitcodeFile(::llvm::MemoryBufferRef(
>  as_string(m.secs[0].data), " "), 
> ctx);
>  
> -   if (::llvm::Error err = mod.takeError()) {
> -  std::string msg;
> -  ::llvm::handleAllErrors(std::move(err), [&](::llvm::ErrorInfoBase 
> ) {
> - msg = EIB.message();
> - fail(r_log, error(CL_INVALID_PROGRAM), msg.c_str());
> -  });
> -   }
> +   compat::handle_module_error(mod, r_log);
>  
> return std::unique_ptr<::llvm::Module>(std::move(*mod));
>  }
> diff --git a/src/gallium/state_trackers/clover/llvm/compat.hpp 
> b/src/gallium/state_trackers/clover/llvm/compat.hpp
> index a963cff..83b3a74 100644
> --- a/src/gallium/state_trackers/clover/llvm/compat.hpp
> +++ b/src/gallium/state_trackers/clover/llvm/compat.hpp
> @@ -39,6 +39,10 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#if HAVE_LLVM < 0x0400
> +#include 
> +#endif
>  
>  #if HAVE_LLVM >= 0x0307
>  #include 
> @@ -53,6 +57,12 @@
>  #include 
>  #include 
>  
> +#include 
> +
> +namespace llvm {
> +   class Module;
> +}
> +
>  namespace clover {
> namespace llvm {
>namespace compat {
> @@ -158,6 +168,26 @@ namespace clover {
>  #else
>   const auto default_reloc_model = ::llvm::Reloc::Default;
>  #endif
> + inline void
> +#if HAVE_LLVM >= 0x0400
> + 
> handle_module_error(::llvm::Expected> ,
> +#else
> + 
> handle_module_error(::llvm::ErrorOr> ,
> +#endif
> + std::string _log) {

can you merge the ifdef blocks? sharing one line of code is not worth
the hit in readability.

Jan

> +#if HAVE_LLVM >= 0x0400
> +if (::llvm::Error err = mod.takeError()) {
> +   ::llvm::handleAllErrors(std::move(err), 
> [&](::llvm::ErrorInfoBase ) {
> +  fail(r_log, error(CL_INVALID_PROGRAM), 
> EIB.message().c_str());
> +   });
> +}
> +#else
> +if (!mod)
> +   fail(r_log, error(CL_INVALID_PROGRAM), 
> mod.getError().message());
> +#endif
> + }
> +
> +
>}
> }
>  }

-- 
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Re: [Mesa-dev] [PATCH 1/2] anv/format: handle unsupported formats properly

[Iago Toral]

On Mon, 2016-11-14 at 09:29 -0800, Jason Ekstrand wrote:
> On Mon, Nov 14, 2016 at 5:23 AM, Iago Toral Quiroga  m> wrote:
> > According to the spec for vkGetPhysicalDeviceImageFormatProperties:
> > 
> > "If format is not a supported image format, or if the combination
> > of format,
> >  type, tiling, usage, and flags is not supported for images, then
> >  vkGetPhysicalDeviceImageFormatProperties returns
> > VK_ERROR_FORMAT_NOT_SUPPORTED."
> > 
> > Makes the following Vulkan CTS tests report 'Not Supported' instead
> > of crashing:
> > 
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_unorm
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_snorm
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uscaled
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sscaled
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uint
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sint
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_srgb
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_unorm
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_snorm
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uscaled
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sscaled
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uint
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sint
> > dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_srgb
> > dEQP-VK.api.image_clearing.clear_color_image.1d_r4g4_unorm_pack8
> > dEQP-VK.api.image_clearing.clear_color_image.1d_r8_srgb
> > dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8_srgb
> > dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
> > dEQP-
> > VK.api.image_clearing.clear_color_image.1d_b5g5r5a1_unorm_pack16
> > ---
> >  src/intel/vulkan/anv_formats.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/src/intel/vulkan/anv_formats.c
> > b/src/intel/vulkan/anv_formats.c
> > index 7497a38..bca9aeb 100644
> > --- a/src/intel/vulkan/anv_formats.c
> > +++ b/src/intel/vulkan/anv_formats.c
> > @@ -511,6 +511,9 @@ VkResult
> > anv_GetPhysicalDeviceImageFormatProperties(
> >        break;
> >     }
> > 
> > +   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED)
> > +      goto unsupported;
> > +
> Can we move this a bit higher up?  This is an early return so it
> makes sense to return as quickly as we can.
> 

Sorry I pushed this too fast, but yes, you're right that it makes sense
to do this earlier. I'll do the change and talk to Emil to include the
first patch in the next stable release.

Iago

> 
> Reviewed-by: Jason Ekstrand 
>  
> >     /* Our hardware doesn't support 1D compressed textures.
> >      *    From the SKL PRM, RENDER_SURFACE_STATE::SurfaceFormat:
> >      *    * This field cannot be a compressed (BC*, DXT*, FXT*,
> > ETC*, EAC*) format
> > --
> > 2.7.4
> > 
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
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[Mesa-dev] [PATCH] ac/nir/llvm: fix channel in texture gather lowering code.

[Dave Airlie]

From: Dave Airlie 

Just noticed this by inspection, while trying to locate other
CTS failures. Don't think it fixes anything, but it might be
needed once I find the proper fix.
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cb0d9a6..5887125 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1764,7 +1764,7 @@ static LLVMValueRef radv_lower_gather4_integer(struct 
nir_to_llvm_context *ctx,
 
for (c = 0; c < 2; c++) {
half_texel[c] = LLVMBuildExtractElement(ctx->builder, 
size,
-   ctx->i32zero, 
"");
+   
LLVMConstInt(ctx->i32, c, false), "");
half_texel[c] = LLVMBuildUIToFP(ctx->builder, 
half_texel[c], ctx->f32, "");
half_texel[c] = emit_fdiv(ctx, ctx->f32one, 
half_texel[c]);
half_texel[c] = LLVMBuildFMul(ctx->builder, 
half_texel[c],
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] main: return error if asking for GL_TEXTURE_BORDER_COLOR in TEXTURE_2D_MULTISAMPLE{_ARRAY} through TexParameterI{i, ui}v()

[Samuel Iglesias Gonsálvez]

On Mon, 2016-11-14 at 20:05 -0800, Kenneth Graunke wrote:
> On Monday, November 7, 2016 11:49:13 AM PST Samuel Iglesias Gonsálvez
> wrote:
> > OpenGL ES 3.2 says in section 8.10. "TEXTURE PARAMETERS", at the
> > end of
> > the section:
> > 
> > "An INVALID_ENUM error is generated if target is TEXTURE_2D_-
> > MULTISAMPLE or TEXTURE_2D_MULTISAMPLE_ARRAY , and pname is any
> > sampler state from table 21.12."
> > 
> > GL_TEXTURE_BORDER_COLOR is present in that table.
> > 
> > Signed-off-by: Samuel Iglesias Gonsálvez 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98250
> > ---
> >  src/mesa/main/texparam.c | 8 
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
> > index 29eed07..ae96bd8 100644
> > --- a/src/mesa/main/texparam.c
> > +++ b/src/mesa/main/texparam.c
> > @@ -974,6 +974,10 @@ _mesa_texture_parameterIiv(struct gl_context
> > *ctx,
> >  {
> > switch (pname) {
> > case GL_TEXTURE_BORDER_COLOR:
> > +  if (!_mesa_target_allows_setting_sampler_parameters(texObj-
> > >Target)) {
> > + _mesa_error(ctx, GL_INVALID_ENUM,
> > "glTextureParameterIiv(texture)");
> > + return;
> > +  }
> >    FLUSH_VERTICES(ctx, _NEW_TEXTURE);
> >    /* set the integer-valued border color */
> >    COPY_4V(texObj->Sampler.BorderColor.i, params);
> > @@ -992,6 +996,10 @@ _mesa_texture_parameterIuiv(struct gl_context
> > *ctx,
> >  {
> > switch (pname) {
> > case GL_TEXTURE_BORDER_COLOR:
> > +  if (!_mesa_target_allows_setting_sampler_parameters(texObj-
> > >Target)) {
> > + _mesa_error(ctx, GL_INVALID_ENUM,
> > "glTextureParameterIuiv(texture)");
> > + return;
> > +  }
> >    FLUSH_VERTICES(ctx, _NEW_TEXTURE);
> >    /* set the unsigned integer-valued border color */
> >    COPY_4V(texObj->Sampler.BorderColor.ui, params);
> > 
> 
> You need to add this check in _mesa_texture_parameteriv as well.
> 
> - glTexParameterfv: already checks this (confirms we need this) :)
> - glTexParameterIiv: fixed by your patch
> - glTexParameterIuiv: fixed by your patch
> - glTexParameteriv: needs the error check also.
> 
> With that fixed, this is:
> Reviewed-by: Kenneth Graunke 

OK, thanks!

Sam

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[Mesa-dev] [Bug 98606] Compile error in gallium target VA--LLVM undefined referencences

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98606

charlie  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |WORKSFORME

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[Mesa-dev] [Bug 98606] Compile error in gallium target VA--LLVM undefined referencences

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98606

--- Comment #10 from charlie  ---
Solved

I think these are the minimum steps used to fix my bug:
1) delete all installed files (includes and libraries) related to libva,
libvdpau and mesa.
2) compile in the following order: mesa with "./configure --disable-va
--disable-vdpau" then
3) libva
4) libvdpau
5) mesa with "./configure --enable-va --enable-vdpau"

After building mesa I also built the rest of x in the correct order.

I request that the mesa build instructions be updated at
"https://www.x.org/wiki/Development/BuildingX;

Side note for those who may encounter this issue in the future:

After the fix I can now use "vo=vdpau" in mplayer's config file.

You can check or export which video driver would use vdpau acceleration with:
export VDPAU_DRIVER=$(grep -i vdpau /var/log/Xorg.0.log | sed 's/.*: *//')
echo $VDPAU_DRIVER

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Re: [Mesa-dev] [PATCH 02/14] swr: [rasterizer memory] round up when dividing by block sizes

[Ilia Mirkin]

I think you're aware, but I actually have an updated version of this patch
on my branch. Let me know if you want me to send it out.

The issue is that the texture width/height need not be a multiple of the
format's block size. However mip sizes are computed based on that unrounded
size.

On Nov 14, 2016 8:45 PM, "Cherniak, Bruce"  wrote:

> We need to run this through CI for all core users.
>
> > On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> >
> > There's no guarantee that mip width/height will be a multiple of the
> > compressed block size. Make sure to round up when dividing.
> >
> > Signed-off-by: Ilia Mirkin 
> > ---
> >
> > Note - I don't actually need this. An earlier version of my patches
> needed
> > something like this. However since it's a real fix, I figured I'd include
> > it here.
> >
> > .../drivers/swr/rasterizer/memory/TilingFunctions.h   | 15
> ---
> > 1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> > index 0694a99..710bfb3 100644
> > --- a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> > +++ b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> > @@ -276,7 +276,10 @@ INLINE void ComputeLODOffset1D(
> > uint32_t curWidth = baseWidth;
> > // translate mip width from pixels to blocks for block
> compressed formats
> > // @note hAlign is already in blocks for compressed formats so
> no need to convert
> > -if (info.isBC) curWidth /= info.bcWidth;
> > +if (info.isBC)
> > +{
> > +curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> > +}
> >
> > offset = GFX_ALIGN(curWidth, hAlign);
> > for (uint32_t l = 1; l < lod; ++l)
> > @@ -314,7 +317,10 @@ INLINE void ComputeLODOffsetX(
> > uint32_t curWidth = baseWidth;
> > // convert mip width from pixels to blocks for block compressed
> formats
> > // @note hAlign is already in blocks for compressed formats so
> no need to convert
> > -if (info.isBC) curWidth /= info.bcWidth;
> > +if (info.isBC)
> > +{
> > +curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> > +}
> >
> > curWidth = std::max(curWidth >> 1, 1U);
> > curWidth = GFX_ALIGN(curWidth, hAlign);
> > @@ -352,7 +358,10 @@ INLINE void ComputeLODOffsetY(
> >
> > // translate mip height from pixels to blocks for block
> compressed formats
> > // @note VAlign is already in blocks for compressed formats so
> no need to convert
> > -if (info.isBC) mipHeight /= info.bcHeight;
> > +if (info.isBC)
> > +{
> > +mipHeight = GFX_ALIGN(mipHeight, info.bcHeight) /
> info.bcHeight;
> > +}
> >
> > for (uint32_t l = 1; l <= lod; ++l)
> > {
> > --
> > 2.7.3
> >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
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Re: [Mesa-dev] [PATCH 00/14] swr: resource-related (and misc) fixes

[Ilia Mirkin]

Should I push the ones you mark as r-b or wait for a separate go-ahead
based on CI results?

On Nov 14, 2016 8:45 PM, "Cherniak, Bruce"  wrote:

> Reviewing/commenting on each patch individually.  We’re also testing more
> thoroughly in our CI.
>
> In general, your help and interest in OpenSWR is very much appreciated!
>
>
> > On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> >
> > This is a bit of a hodge-podge, but largely related to improving texture
> > resource manipulation - mapping, texturing, rendering, etc. There's a WIP
> > commit at the end which was required to make swr not crash on piglit exit
> > half the time, but I think it needs to be redone in a proper way.
> >
> > The meat is in the "swr: rework resource layout and surface setup"
> commit.
> > This redoes surface layout for swr to match with the rasterizer's
> > expectations. This way we can tell it which array index or LOD to render
> to.
> > This will also be important for layered rendering when GS support comes
> > along. It also paves the way to supporting the swr backend's tiling to
> > improve cache performance.
> >
> > Unfortunately it does mean more overhead for all textures, not just the
> > renderable ones. I thought this was acceptable, as supporting multiple
> > different layout mechanisms seems a little confusing.
> >
> > This series overall fixes ~600 piglit tests. You can see this series (+
> one
> > more commit that's not really ready) at
> >
> > http://github.com/imirkin/mesa/commits/swr
> >
> > I highly recommend testing this in your higher-core/higher-perf
> environments
> > than my desktop SKL (or, *gasp*, SDE on a Core i7-920).
> >
> > Ilia Mirkin (14):
> >  swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formats
> >  swr: [rasterizer memory] round up when dividing by block sizes
> >  swr: [rasterizer memory] fix store tile for 128-bit ymajor tiling
> >  swr: [rasterizer jitter] don't bother quantizing unused channels
> >  swr: add archrast generated files to gitignore
> >  swr: fix texture layout for compressed formats
> >  swr: mark both frag and vert textures read, don't forget about cbs
> >  swr: no support for shader stencil export
> >  swr: mark rgb9_e5 as unrenderable
> >  swr: disable blending for integer formats
> >  swr: rework resource layout and surface setup
> >  swr: remove unnecessary -1 entries in format mapping table
> >  swr: remove formats from mapping table that don't have StoreTile impls
> >  WIP swr: make sure that all rendering is finished on shader destroy
> >
> > src/gallium/drivers/swr/.gitignore |   4 +
> > .../drivers/swr/rasterizer/jitter/blend_jit.cpp|   2 +-
> > .../drivers/swr/rasterizer/memory/LoadTile.h   |   1 +
> > .../drivers/swr/rasterizer/memory/StoreTile.h  |   3 +-
> > .../swr/rasterizer/memory/TilingFunctions.h|  15 +-
> > src/gallium/drivers/swr/swr_context.cpp| 108 --
> > src/gallium/drivers/swr/swr_draw.cpp   |   4 +-
> > src/gallium/drivers/swr/swr_resource.h |   8 +-
> > src/gallium/drivers/swr/swr_screen.cpp | 397
> +
> > src/gallium/drivers/swr/swr_shader.cpp |  28 +-
> > src/gallium/drivers/swr/swr_state.cpp  | 197 ++
> > 11 files changed, 433 insertions(+), 334 deletions(-)
> >
> > --
> > 2.7.3
> >
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>
>
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Re: [Mesa-dev] [PATCH 13/14] swr: remove formats from mapping table that don't have StoreTile impls

[Ilia Mirkin]

All formats are supported by the gallivm texturing logic (except some
compressed ones). Swr backend only needs to know about the format for
rendering, not texturing. Makes sense to me just list the renderable ones
here.

If you want a reminder of which formats could be renderable but aren't, how
about leaving all those in a comment?

Either way, the most important change is to remove all the l/la/i swr
format enums (I.e. make the function return -1) since they only have load,
not store implementations. If you still disagree with the above reasoning,
I'll redo that bit of the series.

On Nov 14, 2016 8:47 PM, "Cherniak, Bruce"  wrote:

> This table lists all supported formats (both renderable and texturable).
>
> swr_texture_layout calls mesa_to_swr_format to convert the PIPE_FORMAT_*
> to the appropriate SWR_FORMAT enum.  Removing these entries would result in
> -1 (unsupported format).  We might need to add a “is_renderable” field to
> the table for its use in swr_is_format_supported, but I believe these
> formats should remain.
>
> Although, it looks like you highlighted another bug, swr_texture_layout
> should return false with an early test for mesa_to_swr_format(fmt), rather
> than continuing on.
>
>
> > On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> >
> > This table exists for the purpose of determining renderable formats.
> > Without a StoreTile implementation, that can't happen.
> >
> > This basically removes rendering support to all L/LA/I formats. They can
> > be re-added when/if StoreTile implementations are added.
> >
> > Signed-off-by: Ilia Mirkin 
> > ---
> > src/gallium/drivers/swr/swr_screen.cpp | 86
> +++---
> > 1 file changed, 48 insertions(+), 38 deletions(-)
> >
> > diff --git a/src/gallium/drivers/swr/swr_screen.cpp
> b/src/gallium/drivers/swr/swr_screen.cpp
> > index 98f5e44..9e80e94 100644
> > --- a/src/gallium/drivers/swr/swr_screen.cpp
> > +++ b/src/gallium/drivers/swr/swr_screen.cpp
> > @@ -427,12 +427,7 @@ mesa_to_swr_format(enum pipe_format format)
> >   {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
> >   {PIPE_FORMAT_B5G6R5_UNORM,   B5G6R5_UNORM},
> >   {PIPE_FORMAT_R10G10B10A2_UNORM,  R10G10B10A2_UNORM},
> > -  {PIPE_FORMAT_L8_UNORM,   L8_UNORM},
> >   {PIPE_FORMAT_A8_UNORM,   A8_UNORM},
> > -  {PIPE_FORMAT_I8_UNORM,   I8_UNORM},
> > -  {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
> > -  {PIPE_FORMAT_L16_UNORM,  L16_UNORM},
> > -  {PIPE_FORMAT_UYVY,   YCRCB_SWAPUVY},
> >   {PIPE_FORMAT_Z16_UNORM,  R16_UNORM}, // z
> >   {PIPE_FORMAT_Z32_FLOAT,  R32_FLOAT}, // z
> >   {PIPE_FORMAT_Z24_UNORM_S8_UINT,  R24_UNORM_X8_TYPELESS}, // z
> > @@ -486,26 +481,11 @@ mesa_to_swr_format(enum pipe_format format)
> >   {PIPE_FORMAT_R16G16B16_FLOAT,R16G16B16_FLOAT},
> >   {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
> >
> > -  {PIPE_FORMAT_L8_SRGB,L8_UNORM_SRGB},
> > -  {PIPE_FORMAT_L8A8_SRGB,  L8A8_UNORM_SRGB},
> >   {PIPE_FORMAT_R8G8B8_SRGB,R8G8B8_UNORM_SRGB},
> >   {PIPE_FORMAT_B8G8R8A8_SRGB,  B8G8R8A8_UNORM_SRGB},
> >   {PIPE_FORMAT_B8G8R8X8_SRGB,  B8G8R8X8_UNORM_SRGB},
> >   {PIPE_FORMAT_R8G8B8A8_SRGB,  R8G8B8A8_UNORM_SRGB},
> >
> > -  {PIPE_FORMAT_DXT1_RGBA,  BC1_UNORM},
> > -  {PIPE_FORMAT_DXT3_RGBA,  BC2_UNORM},
> > -  {PIPE_FORMAT_DXT5_RGBA,  BC3_UNORM},
> > -
> > -  {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
> > -  {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
> > -  {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
> > -
> > -  {PIPE_FORMAT_RGTC1_UNORM,BC4_UNORM},
> > -  {PIPE_FORMAT_RGTC1_SNORM,BC4_SNORM},
> > -  {PIPE_FORMAT_RGTC2_UNORM,BC5_UNORM},
> > -  {PIPE_FORMAT_RGTC2_SNORM,BC5_SNORM},
> > -
> >   {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
> >   {PIPE_FORMAT_R10G10B10A2_USCALED,R10G10B10A2_USCALED},
> >   {PIPE_FORMAT_R11G11B10_FLOAT,R11G11B10_FLOAT},
> > @@ -514,18 +494,9 @@ mesa_to_swr_format(enum pipe_format format)
> >   {PIPE_FORMAT_B10G10R10A2_UNORM,  B10G10R10A2_UNORM},
> >   {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
> >
> > -  {PIPE_FORMAT_L16A16_UNORM,   L16A16_UNORM},
> >   {PIPE_FORMAT_A16_UNORM,  A16_UNORM},
> > -  {PIPE_FORMAT_I16_UNORM,  I16_UNORM},
> > -
> >   {PIPE_FORMAT_A16_FLOAT,  A16_FLOAT},
> > -  {PIPE_FORMAT_L16_FLOAT,  L16_FLOAT},
> > -  {PIPE_FORMAT_L16A16_FLOAT,   L16A16_FLOAT},
> > -  {PIPE_FORMAT_I16_FLOAT,  I16_FLOAT},
> >   {PIPE_FORMAT_A32_FLOAT,  

[Mesa-dev] [PATCH] clover: restore support for LLVM <= 3.9

[Vedran Miletić]

The commit 8e430ff8b060b4e8e922bae24b3c57837da6ea77 broke 3.9 and older
versions of LLVM for Clover. This patch restores it and refactors the
support using Clover compatibility layer for LLVM.

Signed-off-by: Vedran Miletić 
---
 .../state_trackers/clover/llvm/codegen/bitcode.cpp |  9 ++-
 src/gallium/state_trackers/clover/llvm/compat.hpp  | 30 ++
 2 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp 
b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
index 5dcc4f8..4b4ae41 100644
--- a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
+++ b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
@@ -32,6 +32,7 @@
 ///
 
 #include "llvm/codegen.hpp"
+#include "llvm/compat.hpp"
 #include "llvm/metadata.hpp"
 #include "core/error.hpp"
 #include "util/algorithm.hpp"
@@ -99,13 +100,7 @@ clover::llvm::parse_module_library(const module , 
::llvm::LLVMContext ,
auto mod = ::llvm::parseBitcodeFile(::llvm::MemoryBufferRef(
 as_string(m.secs[0].data), " "), ctx);
 
-   if (::llvm::Error err = mod.takeError()) {
-  std::string msg;
-  ::llvm::handleAllErrors(std::move(err), [&](::llvm::ErrorInfoBase ) {
- msg = EIB.message();
- fail(r_log, error(CL_INVALID_PROGRAM), msg.c_str());
-  });
-   }
+   compat::handle_module_error(mod, r_log);
 
return std::unique_ptr<::llvm::Module>(std::move(*mod));
 }
diff --git a/src/gallium/state_trackers/clover/llvm/compat.hpp 
b/src/gallium/state_trackers/clover/llvm/compat.hpp
index a963cff..83b3a74 100644
--- a/src/gallium/state_trackers/clover/llvm/compat.hpp
+++ b/src/gallium/state_trackers/clover/llvm/compat.hpp
@@ -39,6 +39,10 @@
 #include 
 #include 
 #include 
+#include 
+#if HAVE_LLVM < 0x0400
+#include 
+#endif
 
 #if HAVE_LLVM >= 0x0307
 #include 
@@ -53,6 +57,12 @@
 #include 
 #include 
 
+#include 
+
+namespace llvm {
+   class Module;
+}
+
 namespace clover {
namespace llvm {
   namespace compat {
@@ -158,6 +168,26 @@ namespace clover {
 #else
  const auto default_reloc_model = ::llvm::Reloc::Default;
 #endif
+ inline void
+#if HAVE_LLVM >= 0x0400
+ handle_module_error(::llvm::Expected> 
,
+#else
+ handle_module_error(::llvm::ErrorOr> 
,
+#endif
+ std::string _log) {
+#if HAVE_LLVM >= 0x0400
+if (::llvm::Error err = mod.takeError()) {
+   ::llvm::handleAllErrors(std::move(err), 
[&](::llvm::ErrorInfoBase ) {
+  fail(r_log, error(CL_INVALID_PROGRAM), 
EIB.message().c_str());
+   });
+}
+#else
+if (!mod)
+   fail(r_log, error(CL_INVALID_PROGRAM), 
mod.getError().message());
+#endif
+ }
+
+
   }
}
 }
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] main: return error if asking for GL_TEXTURE_BORDER_COLOR in TEXTURE_2D_MULTISAMPLE{_ARRAY} through TexParameterI{i, ui}v()

[Kenneth Graunke]

On Monday, November 7, 2016 11:49:13 AM PST Samuel Iglesias Gonsálvez wrote:
> OpenGL ES 3.2 says in section 8.10. "TEXTURE PARAMETERS", at the end of
> the section:
> 
> "An INVALID_ENUM error is generated if target is TEXTURE_2D_-
> MULTISAMPLE or TEXTURE_2D_MULTISAMPLE_ARRAY , and pname is any
> sampler state from table 21.12."
> 
> GL_TEXTURE_BORDER_COLOR is present in that table.
> 
> Signed-off-by: Samuel Iglesias Gonsálvez 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98250
> ---
>  src/mesa/main/texparam.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
> index 29eed07..ae96bd8 100644
> --- a/src/mesa/main/texparam.c
> +++ b/src/mesa/main/texparam.c
> @@ -974,6 +974,10 @@ _mesa_texture_parameterIiv(struct gl_context *ctx,
>  {
> switch (pname) {
> case GL_TEXTURE_BORDER_COLOR:
> +  if (!_mesa_target_allows_setting_sampler_parameters(texObj->Target)) {
> + _mesa_error(ctx, GL_INVALID_ENUM, "glTextureParameterIiv(texture)");
> + return;
> +  }
>FLUSH_VERTICES(ctx, _NEW_TEXTURE);
>/* set the integer-valued border color */
>COPY_4V(texObj->Sampler.BorderColor.i, params);
> @@ -992,6 +996,10 @@ _mesa_texture_parameterIuiv(struct gl_context *ctx,
>  {
> switch (pname) {
> case GL_TEXTURE_BORDER_COLOR:
> +  if (!_mesa_target_allows_setting_sampler_parameters(texObj->Target)) {
> + _mesa_error(ctx, GL_INVALID_ENUM, 
> "glTextureParameterIuiv(texture)");
> + return;
> +  }
>FLUSH_VERTICES(ctx, _NEW_TEXTURE);
>/* set the unsigned integer-valued border color */
>COPY_4V(texObj->Sampler.BorderColor.ui, params);
> 

You need to add this check in _mesa_texture_parameteriv as well.

- glTexParameterfv: already checks this (confirms we need this) :)
- glTexParameterIiv: fixed by your patch
- glTexParameterIuiv: fixed by your patch
- glTexParameteriv: needs the error check also.

With that fixed, this is:
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 14/14] WIP swr: make sure that all rendering is finished on shader destroy

[Cherniak, Bruce]

This works for now, but totally agree with you, we need work attached to 
fences.  That’s been high on my list.

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Rendering could still be ongoing (or have yet to start) when the shader
> is deleted. There's no refcounting on the shader text, so insert a
> pipeline stall unconditionally when this happens.
> 
> [Note, this commit should instead introduce a way to attach work to
> fences, so that the freeing can be done in the current fence.]
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_state.cpp | 8 
> 1 file changed, 8 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/swr_state.cpp 
> b/src/gallium/drivers/swr/swr_state.cpp
> index 2c7f3be..8aca557 100644
> --- a/src/gallium/drivers/swr/swr_state.cpp
> +++ b/src/gallium/drivers/swr/swr_state.cpp
> @@ -371,6 +371,10 @@ swr_delete_vs_state(struct pipe_context *pipe, void *vs)
> {
>struct swr_vertex_shader *swr_vs = (swr_vertex_shader *)vs;
>FREE((void *)swr_vs->pipe.tokens);
> +   struct swr_screen *screen = swr_screen(pipe->screen);
> +   if (!swr_is_fence_pending(screen->flush_fence))
> +  swr_fence_submit(swr_context(pipe), screen->flush_fence);
> +   swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
>delete swr_vs;
> }
> 
> @@ -407,6 +411,10 @@ swr_delete_fs_state(struct pipe_context *pipe, void *fs)
> {
>struct swr_fragment_shader *swr_fs = (swr_fragment_shader *)fs;
>FREE((void *)swr_fs->pipe.tokens);
> +   struct swr_screen *screen = swr_screen(pipe->screen);
> +   if (!swr_is_fence_pending(screen->flush_fence))
> +  swr_fence_submit(swr_context(pipe), screen->flush_fence);
> +   swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
>delete swr_fs;
> }
> 
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 12/14] swr: remove unnecessary -1 entries in format mapping table

[Cherniak, Bruce]

For book-keeping, to know which formats we have left to support/enable, we’d 
like to leave the -1 entries.  It’s a little clutter, but the sore thumb gets 
the hammer.

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 126 -
> 1 file changed, 126 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
> b/src/gallium/drivers/swr/swr_screen.cpp
> index 73deb03..98f5e44 100644
> --- a/src/gallium/drivers/swr/swr_screen.cpp
> +++ b/src/gallium/drivers/swr/swr_screen.cpp
> @@ -421,11 +421,8 @@ SWR_FORMAT
> mesa_to_swr_format(enum pipe_format format)
> {
>static const std::map mesa2swr = {
> -  {PIPE_FORMAT_NONE,   (SWR_FORMAT)-1},
>   {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
>   {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
> -  {PIPE_FORMAT_A8R8G8B8_UNORM, (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_X8R8G8B8_UNORM, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
>   {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
>   {PIPE_FORMAT_B5G6R5_UNORM,   B5G6R5_UNORM},
> @@ -436,35 +433,18 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
>   {PIPE_FORMAT_L16_UNORM,  L16_UNORM},
>   {PIPE_FORMAT_UYVY,   YCRCB_SWAPUVY},
> -  {PIPE_FORMAT_YUYV,   (SWR_FORMAT)-1},
>   {PIPE_FORMAT_Z16_UNORM,  R16_UNORM}, // z
> -  {PIPE_FORMAT_Z32_UNORM,  (SWR_FORMAT)-1},
>   {PIPE_FORMAT_Z32_FLOAT,  R32_FLOAT}, // z
>   {PIPE_FORMAT_Z24_UNORM_S8_UINT,  R24_UNORM_X8_TYPELESS}, // z
> -  {PIPE_FORMAT_S8_UINT_Z24_UNORM,  (SWR_FORMAT)-1},
>   {PIPE_FORMAT_Z24X8_UNORM,R24_UNORM_X8_TYPELESS}, // z
> -  {PIPE_FORMAT_X8Z24_UNORM,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_S8_UINT,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R64_FLOAT,  (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R64G64_FLOAT,   (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R64G64B64_FLOAT,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R64G64B64A64_FLOAT, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R32_FLOAT,  R32_FLOAT},
>   {PIPE_FORMAT_R32G32_FLOAT,   R32G32_FLOAT},
>   {PIPE_FORMAT_R32G32B32_FLOAT,R32G32B32_FLOAT},
>   {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
> -  {PIPE_FORMAT_R32_UNORM,  (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32_UNORM,   (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32_UNORM,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32A32_UNORM, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R32_USCALED,R32_USCALED},
>   {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
>   {PIPE_FORMAT_R32G32B32_USCALED,  R32G32B32_USCALED},
>   {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
> -  {PIPE_FORMAT_R32_SNORM,  (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32_SNORM,   (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32_SNORM,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32A32_SNORM, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R32_SSCALED,R32_SSCALED},
>   {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
>   {PIPE_FORMAT_R32G32B32_SSCALED,  R32G32B32_SSCALED},
> @@ -489,7 +469,6 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
>   {PIPE_FORMAT_R8G8B8_UNORM,   R8G8B8_UNORM},
>   {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
> -  {PIPE_FORMAT_X8B8G8R8_UNORM, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R8_USCALED, R8_USCALED},
>   {PIPE_FORMAT_R8G8_USCALED,   R8G8_USCALED},
>   {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
> @@ -502,10 +481,6 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_R8G8_SSCALED,   R8G8_SSCALED},
>   {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
>   {PIPE_FORMAT_R8G8B8A8_SSCALED,   R8G8B8A8_SSCALED},
> -  {PIPE_FORMAT_R32_FIXED,  (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32_FIXED,   (SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32_FIXED,(SWR_FORMAT)-1},
> -  {PIPE_FORMAT_R32G32B32A32_FIXED, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R16_FLOAT,  R16_FLOAT},
>   {PIPE_FORMAT_R16G16_FLOAT,   R16G16_FLOAT},
>   {PIPE_FORMAT_R16G16B16_FLOAT,R16G16B16_FLOAT},
> @@ -514,20 +489,14 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_L8_SRGB,L8_UNORM_SRGB},
>   {PIPE_FORMAT_L8A8_SRGB,  L8A8_UNORM_SRGB},
>   {PIPE_FORMAT_R8G8B8_SRGB,R8G8B8_UNORM_SRGB},
> 

Re: [Mesa-dev] [PATCH 11/14] swr: rework resource layout and surface setup

[Cherniak, Bruce]

This one is going to take a bit more testing and internal review before 
adopting.

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> This is a bit of a mega-commit, but unfortunately there's no great way
> to break this up since a lot of different pieces have to match up. Here
> we do the following:
> - change surface layout to match swr's Load/StoreTile expectations
> - fix sampler settings to respect all sampler view parameters
> - fix stencil sampling to read from secondary resource
> - respect pipe surface format, level, and layer settings
> - fix resource map/unmap based on the new layout logic
> - fix resource map/unmap to copy proper parts of stencil values in and
>   out of the matching depth texture
> 
> These fix a massive quantity of piglits, including all the
> tex-miplevel-selection ones.
> 
> Note that the swr native miptree layout isn't extremely space-efficient,
> and we end up using it for all textures, not just the renderable ones. A
> back-of-the-envelope calculation suggests about 10%-25% increased memory
> usage for miptrees, depending on the number of LODs. Single-LOD textures
> should be unaffected.
> 
> There are a handful of regressions as a result of this change:
> - fbo-generatemipmap-formats on compressed textures with irregular
>   sizes fails. The 2+ levels appear as if their offsets were off by a
>   bit. No idea why, despite a lot of staring. I suspect the fact that
>   this test was passing before is pure coincidence as well.
> - Some textureGrad tests, these failures match llvmpipe. (There are
>   debug settings allowing improved gallivm sampling accurancy.)
> - Some layered clearing tests as swr doesn't currently support that. It
>   was getting lucky before because enough other things were broken.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_context.cpp | 103 -
> src/gallium/drivers/swr/swr_draw.cpp|   4 +-
> src/gallium/drivers/swr/swr_resource.h  |   8 +-
> src/gallium/drivers/swr/swr_screen.cpp  | 188 +---
> src/gallium/drivers/swr/swr_shader.cpp  |  28 -
> src/gallium/drivers/swr/swr_state.cpp   | 166 +---
> 6 files changed, 337 insertions(+), 160 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_context.cpp 
> b/src/gallium/drivers/swr/swr_context.cpp
> index 6bc6de4..fc8e74a 100644
> --- a/src/gallium/drivers/swr/swr_context.cpp
> +++ b/src/gallium/drivers/swr/swr_context.cpp
> @@ -139,21 +139,35 @@ swr_transfer_map(struct pipe_context *pipe,
>if (!pt)
>   return NULL;
>pipe_resource_reference(>resource, resource);
> +   pt->usage = (pipe_transfer_usage)usage;
>pt->level = level;
>pt->box = *box;
> -   pt->stride = spr->row_stride[level];
> -   pt->layer_stride = spr->img_stride[level];
> -
> -   /* if we're mapping the depth/stencil, copy in stencil */
> -   if (spr->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT
> -   && spr->has_stencil) {
> -  for (unsigned i = 0; i < spr->alignedWidth * spr->alignedHeight; i++) {
> - spr->swr.pBaseAddress[4 * i + 3] = spr->secondary.pBaseAddress[i];
> -  }
> -   } else if (spr->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
> -  && spr->has_stencil) {
> -  for (unsigned i = 0; i < spr->alignedWidth * spr->alignedHeight; i++) {
> - spr->swr.pBaseAddress[8 * i + 4] = spr->secondary.pBaseAddress[i];
> +   pt->stride = spr->swr.pitch;
> +   pt->layer_stride = spr->swr.qpitch * spr->swr.pitch;
> +
> +   /* if we're mapping the depth/stencil, copy in stencil for the section
> +* being read in
> +*/
> +   if (usage & PIPE_TRANSFER_READ && spr->has_depth && spr->has_stencil) {
> +  size_t zbase, sbase;
> +  for (int z = box->z; z < box->z + box->depth; z++) {
> + zbase = (z * spr->swr.qpitch + box->y) * spr->swr.pitch +
> +spr->mip_offsets[level];
> + sbase = (z * spr->secondary.qpitch + box->y) * spr->secondary.pitch 
> +
> +spr->secondary_mip_offsets[level];
> + for (int y = box->y; y < box->y + box->height; y++) {
> +if (spr->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
> +   for (int x = box->x; x < box->x + box->width; x++)
> +  spr->swr.pBaseAddress[zbase + 4 * x + 3] =
> + spr->secondary.pBaseAddress[sbase + x];
> +} else if (spr->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) 
> {
> +   for (int x = box->x; x < box->x + box->width; x++)
> +  spr->swr.pBaseAddress[zbase + 8 * x + 4] =
> + spr->secondary.pBaseAddress[sbase + x];
> +}
> +zbase += spr->swr.pitch;
> +sbase += spr->secondary.pitch;
> + }
>   }
>}
> 
> @@ -167,23 +181,60 @@ swr_transfer_map(struct pipe_context *pipe,
> }
> 
> static void
> -swr_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer 

Re: [Mesa-dev] [PATCH 13/14] swr: remove formats from mapping table that don't have StoreTile impls

[Cherniak, Bruce]

This table lists all supported formats (both renderable and texturable).

swr_texture_layout calls mesa_to_swr_format to convert the PIPE_FORMAT_* to the 
appropriate SWR_FORMAT enum.  Removing these entries would result in -1 
(unsupported format).  We might need to add a “is_renderable” field to the 
table for its use in swr_is_format_supported, but I believe these formats 
should remain.

Although, it looks like you highlighted another bug, swr_texture_layout should 
return false with an early test for mesa_to_swr_format(fmt), rather than 
continuing on.


> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> This table exists for the purpose of determining renderable formats.
> Without a StoreTile implementation, that can't happen.
> 
> This basically removes rendering support to all L/LA/I formats. They can
> be re-added when/if StoreTile implementations are added.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 86 +++---
> 1 file changed, 48 insertions(+), 38 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
> b/src/gallium/drivers/swr/swr_screen.cpp
> index 98f5e44..9e80e94 100644
> --- a/src/gallium/drivers/swr/swr_screen.cpp
> +++ b/src/gallium/drivers/swr/swr_screen.cpp
> @@ -427,12 +427,7 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
>   {PIPE_FORMAT_B5G6R5_UNORM,   B5G6R5_UNORM},
>   {PIPE_FORMAT_R10G10B10A2_UNORM,  R10G10B10A2_UNORM},
> -  {PIPE_FORMAT_L8_UNORM,   L8_UNORM},
>   {PIPE_FORMAT_A8_UNORM,   A8_UNORM},
> -  {PIPE_FORMAT_I8_UNORM,   I8_UNORM},
> -  {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
> -  {PIPE_FORMAT_L16_UNORM,  L16_UNORM},
> -  {PIPE_FORMAT_UYVY,   YCRCB_SWAPUVY},
>   {PIPE_FORMAT_Z16_UNORM,  R16_UNORM}, // z
>   {PIPE_FORMAT_Z32_FLOAT,  R32_FLOAT}, // z
>   {PIPE_FORMAT_Z24_UNORM_S8_UINT,  R24_UNORM_X8_TYPELESS}, // z
> @@ -486,26 +481,11 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_R16G16B16_FLOAT,R16G16B16_FLOAT},
>   {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
> 
> -  {PIPE_FORMAT_L8_SRGB,L8_UNORM_SRGB},
> -  {PIPE_FORMAT_L8A8_SRGB,  L8A8_UNORM_SRGB},
>   {PIPE_FORMAT_R8G8B8_SRGB,R8G8B8_UNORM_SRGB},
>   {PIPE_FORMAT_B8G8R8A8_SRGB,  B8G8R8A8_UNORM_SRGB},
>   {PIPE_FORMAT_B8G8R8X8_SRGB,  B8G8R8X8_UNORM_SRGB},
>   {PIPE_FORMAT_R8G8B8A8_SRGB,  R8G8B8A8_UNORM_SRGB},
> 
> -  {PIPE_FORMAT_DXT1_RGBA,  BC1_UNORM},
> -  {PIPE_FORMAT_DXT3_RGBA,  BC2_UNORM},
> -  {PIPE_FORMAT_DXT5_RGBA,  BC3_UNORM},
> -
> -  {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
> -  {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
> -  {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
> -
> -  {PIPE_FORMAT_RGTC1_UNORM,BC4_UNORM},
> -  {PIPE_FORMAT_RGTC1_SNORM,BC4_SNORM},
> -  {PIPE_FORMAT_RGTC2_UNORM,BC5_UNORM},
> -  {PIPE_FORMAT_RGTC2_SNORM,BC5_SNORM},
> -
>   {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
>   {PIPE_FORMAT_R10G10B10A2_USCALED,R10G10B10A2_USCALED},
>   {PIPE_FORMAT_R11G11B10_FLOAT,R11G11B10_FLOAT},
> @@ -514,18 +494,9 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_B10G10R10A2_UNORM,  B10G10R10A2_UNORM},
>   {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
> 
> -  {PIPE_FORMAT_L16A16_UNORM,   L16A16_UNORM},
>   {PIPE_FORMAT_A16_UNORM,  A16_UNORM},
> -  {PIPE_FORMAT_I16_UNORM,  I16_UNORM},
> -
>   {PIPE_FORMAT_A16_FLOAT,  A16_FLOAT},
> -  {PIPE_FORMAT_L16_FLOAT,  L16_FLOAT},
> -  {PIPE_FORMAT_L16A16_FLOAT,   L16A16_FLOAT},
> -  {PIPE_FORMAT_I16_FLOAT,  I16_FLOAT},
>   {PIPE_FORMAT_A32_FLOAT,  A32_FLOAT},
> -  {PIPE_FORMAT_L32_FLOAT,  L32_FLOAT},
> -  {PIPE_FORMAT_L32A32_FLOAT,   L32A32_FLOAT},
> -  {PIPE_FORMAT_I32_FLOAT,  I32_FLOAT},
> 
>   {PIPE_FORMAT_R10G10B10A2_SSCALED,R10G10B10A2_SSCALED},
>   {PIPE_FORMAT_R10G10B10A2_SNORM,  R10G10B10A2_SNORM},
> @@ -564,14 +535,6 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
>   {PIPE_FORMAT_R32G32B32A32_SINT,  R32G32B32A32_SINT},
> 
> -  {PIPE_FORMAT_I8_UINT,I8_UINT},
> -  {PIPE_FORMAT_L8_UINT,L8_UINT},
> -  {PIPE_FORMAT_L8A8_UINT,  L8A8_UINT},
> -
> -  {PIPE_FORMAT_I8_SINT,I8_SINT},
> -  {PIPE_FORMAT_L8_SINT,L8_SINT},
> -  

Re: [Mesa-dev] [PATCH 10/14] swr: disable blending for integer formats

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> The EXT_texture_integer test says that blending and alphatest should
> all be disabled. st/mesa takes care of alphatest already.
> 
> Fixes the ext_texture_integer-fbo-blending piglit test.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_state.cpp | 3 +++
> 1 file changed, 3 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/swr_state.cpp 
> b/src/gallium/drivers/swr/swr_state.cpp
> index 526d7e7..783afba 100644
> --- a/src/gallium/drivers/swr/swr_state.cpp
> +++ b/src/gallium/drivers/swr/swr_state.cpp
> @@ -1318,6 +1318,9 @@ swr_update_derived(struct pipe_context *pipe,
>compileState.blendState.logicOpEnable = false;
> }
> 
> +if (info.type[0] == SWR_TYPE_SINT || info.type[0] == 
> SWR_TYPE_UINT)
> +   compileState.blendState.blendEnable = false;
> +
> if (compileState.blendState.blendEnable == false &&
> compileState.blendState.logicOpEnable == false &&
> ctx->depth_stencil->alpha.enabled == 0) {
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 06/14] swr: fix texture layout for compressed formats

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak  

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Fixes the texsubimage piglit and lets the copyteximage one get further.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_context.cpp | 5 +++--
> src/gallium/drivers/swr/swr_screen.cpp  | 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_context.cpp 
> b/src/gallium/drivers/swr/swr_context.cpp
> index cbc60e0..6bc6de4 100644
> --- a/src/gallium/drivers/swr/swr_context.cpp
> +++ b/src/gallium/drivers/swr/swr_context.cpp
> @@ -157,8 +157,9 @@ swr_transfer_map(struct pipe_context *pipe,
>   }
>}
> 
> -   unsigned offset = box->z * pt->layer_stride + box->y * pt->stride
> -  + box->x * util_format_get_blocksize(format);
> +   unsigned offset = box->z * pt->layer_stride +
> +  util_format_get_nblocksy(format, box->y) * pt->stride +
> +  util_format_get_stride(format, box->x);
> 
>*transfer = pt;
> 
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
> b/src/gallium/drivers/swr/swr_screen.cpp
> index fa16edd..16a8bcf 100644
> --- a/src/gallium/drivers/swr/swr_screen.cpp
> +++ b/src/gallium/drivers/swr/swr_screen.cpp
> @@ -796,8 +796,9 @@ swr_texture_layout(struct swr_screen *screen,
>  res->alignedHeight = alignedHeight;
>   }
> 
> -  res->row_stride[level] = alignedWidth * finfo.Bpp;
> -  res->img_stride[level] = res->row_stride[level] * alignedHeight;
> +  res->row_stride[level] = util_format_get_stride(fmt, alignedWidth);
> +  res->img_stride[level] =
> + res->row_stride[level] * util_format_get_nblocksy(fmt, 
> alignedHeight);
>   res->mip_offsets[level] = total_size;
> 
>   if (pt->target == PIPE_TEXTURE_3D)
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 08/14] swr: no support for shader stencil export

[Cherniak, Bruce]

Doesn’t look as though shader stencil export (GL_ARB_shader_stencil_export) 
would be too hard to implement, until then best to disable it.

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
> b/src/gallium/drivers/swr/swr_screen.cpp
> index 16a8bcf..c694457 100644
> --- a/src/gallium/drivers/swr/swr_screen.cpp
> +++ b/src/gallium/drivers/swr/swr_screen.cpp
> @@ -214,7 +214,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap 
> param)
>case PIPE_CAP_PRIMITIVE_RESTART:
>   return 1;
>case PIPE_CAP_SHADER_STENCIL_EXPORT:
> -  return 1;
> +  return 0;
>case PIPE_CAP_TGSI_INSTANCEID:
>case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
>case PIPE_CAP_START_INSTANCE:
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 05/14] swr: add archrast generated files to gitignore

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/.gitignore | 4 
> 1 file changed, 4 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/.gitignore 
> b/src/gallium/drivers/swr/.gitignore
> index 6b4de9e..172f3bf 100644
> --- a/src/gallium/drivers/swr/.gitignore
> +++ b/src/gallium/drivers/swr/.gitignore
> @@ -1,4 +1,8 @@
> swr_context_llvm.h
> +rasterizer/archrast/gen_ar_event.cpp
> +rasterizer/archrast/gen_ar_event.h
> +rasterizer/archrast/gen_ar_eventhandler.h
> +rasterizer/archrast/gen_ar_eventhandlerfile.h
> rasterizer/jitter/builder_gen.cpp
> rasterizer/jitter/builder_gen.h
> rasterizer/jitter/builder_x86.cpp
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 02/14] swr: [rasterizer memory] round up when dividing by block sizes

[Cherniak, Bruce]

We need to run this through CI for all core users.

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> There's no guarantee that mip width/height will be a multiple of the
> compressed block size. Make sure to round up when dividing.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> 
> Note - I don't actually need this. An earlier version of my patches needed
> something like this. However since it's a real fix, I figured I'd include
> it here.
> 
> .../drivers/swr/rasterizer/memory/TilingFunctions.h   | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h 
> b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> index 0694a99..710bfb3 100644
> --- a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> +++ b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
> @@ -276,7 +276,10 @@ INLINE void ComputeLODOffset1D(
> uint32_t curWidth = baseWidth;
> // translate mip width from pixels to blocks for block compressed 
> formats
> // @note hAlign is already in blocks for compressed formats so no 
> need to convert
> -if (info.isBC) curWidth /= info.bcWidth;
> +if (info.isBC)
> +{
> +curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> +}
> 
> offset = GFX_ALIGN(curWidth, hAlign);
> for (uint32_t l = 1; l < lod; ++l)
> @@ -314,7 +317,10 @@ INLINE void ComputeLODOffsetX(
> uint32_t curWidth = baseWidth;
> // convert mip width from pixels to blocks for block compressed 
> formats
> // @note hAlign is already in blocks for compressed formats so no 
> need to convert
> -if (info.isBC) curWidth /= info.bcWidth;
> +if (info.isBC)
> +{
> +curWidth = GFX_ALIGN(curWidth, info.bcWidth) / info.bcWidth;
> +}
> 
> curWidth = std::max(curWidth >> 1, 1U);
> curWidth = GFX_ALIGN(curWidth, hAlign);
> @@ -352,7 +358,10 @@ INLINE void ComputeLODOffsetY(
> 
> // translate mip height from pixels to blocks for block compressed 
> formats
> // @note VAlign is already in blocks for compressed formats so no 
> need to convert
> -if (info.isBC) mipHeight /= info.bcHeight;
> +if (info.isBC)
> +{
> +mipHeight = GFX_ALIGN(mipHeight, info.bcHeight) / info.bcHeight;
> +}
> 
> for (uint32_t l = 1; l <= lod; ++l)
> {
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 09/14] swr: mark rgb9_e5 as unrenderable

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> The support in swr requires shaders to output the components as UINTs.
> This is not how GL or Gallium work, and since this is not a
> required-renderable format, just leave it out.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
> b/src/gallium/drivers/swr/swr_screen.cpp
> index c694457..accd6a2 100644
> --- a/src/gallium/drivers/swr/swr_screen.cpp
> +++ b/src/gallium/drivers/swr/swr_screen.cpp
> @@ -545,7 +545,7 @@ mesa_to_swr_format(enum pipe_format format)
>   {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
>   {PIPE_FORMAT_R10G10B10A2_USCALED,R10G10B10A2_USCALED},
>   {PIPE_FORMAT_R11G11B10_FLOAT,R11G11B10_FLOAT},
> -  {PIPE_FORMAT_R9G9B9E5_FLOAT, R9G9B9E5_SHAREDEXP},
> +  {PIPE_FORMAT_R9G9B9E5_FLOAT, (SWR_FORMAT)-1},
>   {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
>   {PIPE_FORMAT_R1_UNORM,   (SWR_FORMAT)-1},
>   {PIPE_FORMAT_R10G10B10X2_USCALED,R10G10B10X2_USCALED},
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 07/14] swr: mark both frag and vert textures read, don't forget about cbs

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/swr_state.cpp | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/src/gallium/drivers/swr/swr_state.cpp 
> b/src/gallium/drivers/swr/swr_state.cpp
> index 65327f3..526d7e7 100644
> --- a/src/gallium/drivers/swr/swr_state.cpp
> +++ b/src/gallium/drivers/swr/swr_state.cpp
> @@ -674,11 +674,21 @@ swr_update_resource_status(struct pipe_context *pipe,
>}
> 
>/* texture sampler views */
> -   for (uint32_t i = 0; i < PIPE_MAX_SHADER_SAMPLER_VIEWS; i++) {
> -  struct pipe_sampler_view *view =
> - ctx->sampler_views[PIPE_SHADER_FRAGMENT][i];
> -  if (view)
> - swr_resource_read(view->texture);
> +   for (uint32_t j : {PIPE_SHADER_VERTEX, PIPE_SHADER_FRAGMENT}) {
> +  for (uint32_t i = 0; i < ctx->num_sampler_views[j]; i++) {
> + struct pipe_sampler_view *view = ctx->sampler_views[j][i];
> + if (view)
> +swr_resource_read(view->texture);
> +  }
> +   }
> +
> +   /* constant buffers */
> +   for (uint32_t j : {PIPE_SHADER_VERTEX, PIPE_SHADER_FRAGMENT}) {
> +  for (uint32_t i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
> + struct pipe_constant_buffer *cb = >constants[j][i];
> + if (cb->buffer)
> +swr_resource_read(cb->buffer);
> +  }
>}
> }
> 
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 04/14] swr: [rasterizer jitter] don't bother quantizing unused channels

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> In a BGR10X2 or BGR5X1 situation, there's no need to try to quantize the
> X channel - the default will have the proper quantization required.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp 
> b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> index 46ea495..d9c72a9 100644
> --- a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> +++ b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> @@ -220,7 +220,7 @@ struct BlendJit : public Builder
> const SWR_FORMAT_INFO& info = GetFormatInfo(format);
> for (uint32_t c = 0; c < info.numComps; ++c)
> {
> -if (info.bpc[c] <= QUANTIZE_THRESHOLD)
> +if (info.bpc[c] <= QUANTIZE_THRESHOLD && info.type[c] != 
> SWR_TYPE_UNUSED)
> {
> uint32_t swizComp = info.swizzle[c];
> float factor = (float)((1 << info.bpc[c]) - 1);
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 03/14] swr: [rasterizer memory] fix store tile for 128-bit ymajor tiling

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak  

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> Noticed by inspection.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> 
> Entirely untested. Just happened to jump out at me that the two tiling modes
> didn't match, whereas every other instance in this file matches.
> 
> src/gallium/drivers/swr/rasterizer/memory/StoreTile.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h 
> b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> index b89c886..380e6af 100644
> --- a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> +++ b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> @@ -1650,7 +1650,7 @@ struct OptStoreRasterTile< 
> TilingTraits, SrcFormat, Ds
> template
> struct OptStoreRasterTile< TilingTraits, 
> SrcFormat, DstFormat>
> {
> -typedef StoreRasterTile, SrcFormat, 
> DstFormat> GenericStoreTile;
> +typedef StoreRasterTile, 
> SrcFormat, DstFormat> GenericStoreTile;
> 
> static const size_t TILE_Y_COL_WIDTH_BYTES  = 16;
> static const size_t TILE_Y_ROWS = 32;
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 00/14] swr: resource-related (and misc) fixes

[Cherniak, Bruce]

Reviewing/commenting on each patch individually.  We’re also testing more 
thoroughly in our CI.  

In general, your help and interest in OpenSWR is very much appreciated!


> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> This is a bit of a hodge-podge, but largely related to improving texture
> resource manipulation - mapping, texturing, rendering, etc. There's a WIP
> commit at the end which was required to make swr not crash on piglit exit
> half the time, but I think it needs to be redone in a proper way.
> 
> The meat is in the "swr: rework resource layout and surface setup" commit.
> This redoes surface layout for swr to match with the rasterizer's
> expectations. This way we can tell it which array index or LOD to render to.
> This will also be important for layered rendering when GS support comes
> along. It also paves the way to supporting the swr backend's tiling to
> improve cache performance.
> 
> Unfortunately it does mean more overhead for all textures, not just the
> renderable ones. I thought this was acceptable, as supporting multiple
> different layout mechanisms seems a little confusing.
> 
> This series overall fixes ~600 piglit tests. You can see this series (+ one
> more commit that's not really ready) at
> 
> http://github.com/imirkin/mesa/commits/swr
> 
> I highly recommend testing this in your higher-core/higher-perf environments
> than my desktop SKL (or, *gasp*, SDE on a Core i7-920).
> 
> Ilia Mirkin (14):
>  swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formats
>  swr: [rasterizer memory] round up when dividing by block sizes
>  swr: [rasterizer memory] fix store tile for 128-bit ymajor tiling
>  swr: [rasterizer jitter] don't bother quantizing unused channels
>  swr: add archrast generated files to gitignore
>  swr: fix texture layout for compressed formats
>  swr: mark both frag and vert textures read, don't forget about cbs
>  swr: no support for shader stencil export
>  swr: mark rgb9_e5 as unrenderable
>  swr: disable blending for integer formats
>  swr: rework resource layout and surface setup
>  swr: remove unnecessary -1 entries in format mapping table
>  swr: remove formats from mapping table that don't have StoreTile impls
>  WIP swr: make sure that all rendering is finished on shader destroy
> 
> src/gallium/drivers/swr/.gitignore |   4 +
> .../drivers/swr/rasterizer/jitter/blend_jit.cpp|   2 +-
> .../drivers/swr/rasterizer/memory/LoadTile.h   |   1 +
> .../drivers/swr/rasterizer/memory/StoreTile.h  |   3 +-
> .../swr/rasterizer/memory/TilingFunctions.h|  15 +-
> src/gallium/drivers/swr/swr_context.cpp| 108 --
> src/gallium/drivers/swr/swr_draw.cpp   |   4 +-
> src/gallium/drivers/swr/swr_resource.h |   8 +-
> src/gallium/drivers/swr/swr_screen.cpp | 397 +
> src/gallium/drivers/swr/swr_shader.cpp |  28 +-
> src/gallium/drivers/swr/swr_state.cpp  | 197 ++
> 11 files changed, 433 insertions(+), 334 deletions(-)
> 
> -- 
> 2.7.3
> 
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Re: [Mesa-dev] [PATCH 01/14] swr: [rasterizer memory] add support for R32_FLOAT_X8X24 formats

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak  

> On Nov 12, 2016, at 5:00 PM, Ilia Mirkin  wrote:
> 
> This is the format used for the primary surface of a
> PIPE_FORMAT_Z32_FLOAT_S8X24_UINT resource.
> 
> Signed-off-by: Ilia Mirkin 
> ---
> src/gallium/drivers/swr/rasterizer/memory/LoadTile.h  | 1 +
> src/gallium/drivers/swr/rasterizer/memory/StoreTile.h | 1 +
> 2 files changed, 2 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h 
> b/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
> index 858f162..d1cc3ed 100644
> --- a/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
> +++ b/src/gallium/drivers/swr/rasterizer/memory/LoadTile.h
> @@ -347,6 +347,7 @@ static INLINE void 
> InitLoadTileDepthTable(PFN_LOAD_TILES()[NUM_SWR_FORMATS
> memset(table, 0, sizeof(table));
> 
>table[R32_FLOAT]   = 
> LoadMacroTile, R32_FLOAT, R32_FLOAT>::Load;
> +   table[R32_FLOAT_X8X24_TYPELESS]= 
> LoadMacroTile, R32_FLOAT_X8X24_TYPELESS, 
> R32_FLOAT>::Load;
>table[R24_UNORM_X8_TYPELESS]   = 
> LoadMacroTile, R24_UNORM_X8_TYPELESS, 
> R32_FLOAT>::Load;
>table[R16_UNORM]   = 
> LoadMacroTile, R16_UNORM, R32_FLOAT>::Load;
> }
> diff --git a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h 
> b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> index 21ee443..b89c886 100644
> --- a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> +++ b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h
> @@ -1951,6 +1951,7 @@ void InitStoreTilesTableDepth(
> PFN_STORE_TILES()[NumTileModes][ArraySizeT])
> {
>table[TTileMode][R32_FLOAT]  = 
> StoreMacroTile, R32_FLOAT, R32_FLOAT>::Store;
> +   table[TTileMode][R32_FLOAT_X8X24_TYPELESS]   = 
> StoreMacroTile, R32_FLOAT, 
> R32_FLOAT_X8X24_TYPELESS>::Store;
>table[TTileMode][R24_UNORM_X8_TYPELESS]  = 
> StoreMacroTile, R32_FLOAT, 
> R24_UNORM_X8_TYPELESS>::Store;
>table[TTileMode][R16_UNORM]  = 
> StoreMacroTile, R32_FLOAT, R16_UNORM>::Store;
> }
> -- 
> 2.7.3
> 
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[Mesa-dev] [Bug 77662] Fail to render to different faces of depth-stencil cube map

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77662

Nanley Chery  changed:

   What|Removed |Added

Summary|[SNB] fail to render to |Fail to render to different
   |different faces of  |faces of depth-stencil cube
   |depth-stencil cube map  |map

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[Mesa-dev] [Bug 77662] [SNB] fail to render to different faces of depth-stencil cube map

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77662

Nanley Chery  changed:

   What|Removed |Added

Version|10.1|13.0
   Assignee|i...@freedesktop.org |mesa-dev@lists.freedesktop.
   ||org
 QA Contact|intel-3d-bugs@lists.freedes |mesa-dev@lists.freedesktop.
   |ktop.org|org
  Component|Drivers/DRI/i965|Mesa core

--- Comment #3 from Nanley Chery  ---
I've been able to reproduce this with a software rasterizer (via
LIBGL_ALWAYS_SOFTWARE=1) on Mesa 13.

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[Mesa-dev] [PATCH 12/14] i965/vec4: Handle component qualifiers on non-generic varyings.

[Kenneth Graunke]

ARB_enhanced_layouts only requires component qualifier support for
generic varyings, so this is all the vec4 backend knew how to handle.

This patch extends the backend to handle it for all varyings, so we
can use store_output intrinsics with a component set for things like
clip/cull distances.  We may want to use that for other VUE header
fields in the future as well.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_vec4.h  | 10 ++-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp| 11 +--
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp| 83 +--
 src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 18 +++--
 src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp |  4 +-
 5 files changed, 53 insertions(+), 73 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 62c6007..dc69ea9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -113,10 +113,9 @@ public:
/* Regs for vertex results.  Generated at ir_variable visiting time
 * for the ir->location's used.
 */
-   dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
-   dst_reg output_generic_reg[MAX_VARYINGS_INCL_PATCH][4];
-   unsigned output_generic_num_components[MAX_VARYINGS_INCL_PATCH][4];
-   const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
+   dst_reg output_reg[VARYING_SLOT_TESS_MAX][4];
+   unsigned output_num_components[VARYING_SLOT_TESS_MAX][4];
+   const char *output_reg_annotation[VARYING_SLOT_TESS_MAX];
int uniforms;
 
src_reg shader_start_time;
@@ -270,8 +269,7 @@ public:
 
void emit_ndc_computation();
void emit_psiz_and_flags(dst_reg reg);
-   vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
-   void emit_generic_urb_slot(dst_reg reg, int varying, int component);
+   vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
virtual void emit_urb_slot(dst_reg reg, int varying);
 
void emit_shader_time_begin();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index fc4eb3a..0d54907 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -416,14 +416,9 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
*instr)
   src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
 instr->num_components);
 
-  if (varying >= VARYING_SLOT_VAR0) {
- unsigned c = nir_intrinsic_component(instr);
- unsigned v = varying - VARYING_SLOT_VAR0;
- output_generic_reg[v][c] = dst_reg(src);
- output_generic_num_components[v][c] = instr->num_components;
-  } else {
- output_reg[varying] = dst_reg(src);
-  }
+  unsigned c = nir_intrinsic_component(instr);
+  output_reg[varying][c] = dst_reg(src);
+  output_num_components[varying][c] = instr->num_components;
   break;
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 954f147..8c7901f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1154,15 +1154,16 @@ vec4_visitor::gs_end_primitive()
 void
 vec4_visitor::emit_ndc_computation()
 {
-   if (output_reg[VARYING_SLOT_POS].file == BAD_FILE)
+   if (output_reg[VARYING_SLOT_POS][0].file == BAD_FILE)
   return;
 
/* Get the position */
-   src_reg pos = src_reg(output_reg[VARYING_SLOT_POS]);
+   src_reg pos = src_reg(output_reg[VARYING_SLOT_POS][0]);
 
/* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
dst_reg ndc = dst_reg(this, glsl_type::vec4_type);
-   output_reg[BRW_VARYING_SLOT_NDC] = ndc;
+   output_reg[BRW_VARYING_SLOT_NDC][0] = ndc;
+   output_num_components[BRW_VARYING_SLOT_NDC][0] = 4;
 
current_annotation = "NDC";
dst_reg ndc_w = ndc;
@@ -1182,7 +1183,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
 {
if (devinfo->gen < 6 &&
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
-output_reg[VARYING_SLOT_CLIP_DIST0].file != BAD_FILE ||
+output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE ||
 devinfo->has_negative_rhw_bug)) {
   dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
   dst_reg header1_w = header1;
@@ -1191,23 +1192,23 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
   emit(MOV(header1, brw_imm_ud(0u)));
 
   if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
-src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ]);
+src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ][0]);
 
 current_annotation = "Point size";
 emit(MUL(header1_w, psiz, brw_imm_f((float)(1 << 11;
 emit(AND(header1_w, src_reg(header1_w), brw_imm_d(0x7ff << 8)));
   }
 
-  if (output_reg[VARYING_SLOT_CLIP_DIST0].file != BAD_FILE) {
+  if 

[Mesa-dev] [PATCH 03/14] i965: Use shader_info for brw_vue_prog_data::cull_distance_mask.

[Kenneth Graunke]

This also allows us to move it from a GL specific location to a
part of the compiler shared by both GL and Vulkan.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_gs.c| 4 
 src/mesa/drivers/dri/i965/brw_shader.cpp  | 4 
 src/mesa/drivers/dri/i965/brw_tes.c   | 4 
 src/mesa/drivers/dri/i965/brw_vec4.cpp| 4 
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 4 
 src/mesa/drivers/dri/i965/brw_vs.c| 4 
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 0f052d2..c2cc37d 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -135,10 +135,6 @@ brw_codegen_gs_prog(struct brw_context *brw,
 
uint64_t outputs_written = gp->program.info.outputs_written;
 
-   prog_data.base.cull_distance_mask =
-  ((1 << gp->program.CullDistanceArraySize) - 1) <<
-  gp->program.ClipDistanceArraySize;
-
brw_compute_vue_map(devinfo,
_data.base.vue_map, outputs_written,
prog->SeparateShader);
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61bc868..e44a845 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1376,6 +1376,10 @@ brw_compile_tes(const struct brw_compiler *compiler,
   return NULL;
}
 
+   prog_data->base.cull_distance_mask =
+  ((1 << nir->info->cull_distance_array_size) - 1) <<
+  nir->info->clip_distance_array_size;
+
/* URB entry sizes are stored as a multiple of 64 bytes. */
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c 
b/src/mesa/drivers/dri/i965/brw_tes.c
index 6060c76..57f62cb 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -163,10 +163,6 @@ brw_codegen_tes_prog(struct brw_context *brw,
prog_data.base.base.nr_params = param_count;
prog_data.base.base.nr_image_params = tes->NumImages;
 
-   prog_data.base.cull_distance_mask =
-  ((1 << tep->program.CullDistanceArraySize) - 1) <<
-  tep->program.ClipDistanceArraySize;
-
brw_nir_setup_glsl_uniforms(nir, shader_prog, >program,
_data.base.base,
compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 6d487da..4da8f6e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2121,6 +2121,10 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
 
const unsigned *assembly = NULL;
 
+   prog_data->base.cull_distance_mask =
+  ((1 << shader->info->cull_distance_array_size) - 1) <<
+  shader->info->clip_distance_array_size;
+
unsigned nr_attributes = _mesa_bitcount_64(prog_data->inputs_read);
 
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index b2add03..5e2dcc0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -621,6 +621,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void 
*log_data,
brw_nir_lower_vue_outputs(shader, is_scalar);
shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
 
+   prog_data->base.cull_distance_mask =
+  ((1 << shader->info->cull_distance_array_size) - 1) <<
+  shader->info->clip_distance_array_size;
+
prog_data->include_primitive_id =
   (shader->info->system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID)) != 
0;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index 02a88ca..9b17038 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -157,10 +157,6 @@ brw_codegen_vs_prog(struct brw_context *brw,
   prog_data.inputs_read |= VERT_BIT_EDGEFLAG;
}
 
-   prog_data.base.cull_distance_mask =
-  ((1 << vp->program.CullDistanceArraySize) - 1) <<
-  vp->program.ClipDistanceArraySize;
-
brw_compute_vue_map(devinfo,
_data.base.vue_map, outputs_written,
prog ? prog->SeparateShader ||
-- 
2.10.2

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[Mesa-dev] [PATCH 06/14] nir: Add a "compact array" flag and IO lowering code.

[Kenneth Graunke]

Certain built-in arrays, such as gl_ClipDistance[], gl_CullDistance[],
gl_TessLevelInner[], and gl_TessLevelOuter[] are specified as scalar
arrays.  Normal scalar arrays are sparse - each array element usually
occupies a whole vec4 slot.  However, most hardware assumes these
built-in arrays are tightly packed.

The new var->data.compact flag indicates that a scalar array should
be tightly packed, so a float[4] array would take up a single vec4
slot, and a float[8] array would take up two slots.

They are still arrays, not vec4s, however.  nir_lower_io will generate
intrinsics using ARB_enhanced_layouts style component qualifiers.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glsl_to_nir.cpp|  1 +
 src/compiler/nir/nir.h   |  7 +
 src/compiler/nir/nir_gather_info.c   |  9 --
 src/compiler/nir/nir_lower_indirect_derefs.c |  8 +++--
 src/compiler/nir/nir_lower_io.c  | 44 
 src/compiler/nir/nir_print.c |  4 ++-
 6 files changed, 55 insertions(+), 18 deletions(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 6ca760b..ed1c739 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -331,6 +331,7 @@ nir_visitor::visit(ir_variable *ir)
var->data.explicit_index = ir->data.explicit_index;
var->data.explicit_binding = ir->data.explicit_binding;
var->data.has_initializer = ir->data.has_initializer;
+   var->data.compact = false;
var->data.location_frac = ir->data.location_frac;
 
switch (ir->data.depth_layout) {
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 3d46384..0b78242 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -230,6 +230,13 @@ typedef struct nir_variable {
   unsigned location_frac:2;
 
   /**
+   * If true, this variable represents an array of scalars that should
+   * be tightly packed.  In other words, consecutive array elements
+   * should be stored one component apart, rather than one slot apart.
+   */
+  unsigned compact:1;
+
+  /**
* Whether this is a fragment shader output implicitly initialized with
* the previous contents of the specified render target at the
* framebuffer location corresponding to this shader invocation.
diff --git a/src/compiler/nir/nir_gather_info.c 
b/src/compiler/nir/nir_gather_info.c
index 63c8a42..4d07dda 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -94,8 +94,11 @@ mark_whole_variable(nir_shader *shader, nir_variable *var)
var->data.mode == nir_var_shader_in)
   is_vertex_input = true;
 
-   set_io_mask(shader, var, 0,
-   glsl_count_attribute_slots(type, is_vertex_input));
+   const unsigned slots =
+  var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
+: glsl_count_attribute_slots(type, is_vertex_input);
+
+   set_io_mask(shader, var, 0, slots);
 }
 
 static unsigned
@@ -150,7 +153,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var 
*deref)
 * here marking the entire variable as used.
 */
if (!(glsl_type_is_matrix(type) ||
- (glsl_type_is_array(type) &&
+ (glsl_type_is_array(type) && !var->data.compact &&
   (glsl_type_is_numeric(glsl_without_array(type)) ||
glsl_type_is_boolean(glsl_without_array(type)) {
 
diff --git a/src/compiler/nir/nir_lower_indirect_derefs.c 
b/src/compiler/nir/nir_lower_indirect_derefs.c
index 356373e..5c97dc8e 100644
--- a/src/compiler/nir/nir_lower_indirect_derefs.c
+++ b/src/compiler/nir/nir_lower_indirect_derefs.c
@@ -175,8 +175,12 @@ lower_indirect_block(nir_block *block, nir_builder *b,
   if (!deref_has_indirect(intrin->variables[0]))
  continue;
 
-  /* Only lower variables whose mode is in the mask */
-  if (!(modes & intrin->variables[0]->var->data.mode))
+  /* Only lower variables whose mode is in the mask, or compact
+   * array variables.  (We can't handle indirects on tightly packed
+   * scalar arrays, so we need to lower them regardless.)
+   */
+  if (!(modes & intrin->variables[0]->var->data.mode) &&
+  !intrin->variables[0]->var->data.compact)
  continue;
 
   b->cursor = nir_before_instr(>instr);
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index a7e7f14..6628947 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -88,7 +88,8 @@ nir_is_per_vertex_io(nir_variable *var, gl_shader_stage stage)
 static nir_ssa_def *
 get_io_offset(nir_builder *b, nir_deref_var *deref,
   nir_ssa_def **vertex_index,
-  int (*type_size)(const struct glsl_type *))
+  int (*type_size)(const struct glsl_type *),
+  unsigned *component)
 {
nir_deref *tail = >deref;
 
@@ -106,6 +107,19 

[Mesa-dev] [PATCH 10/14] spirv: Silence unsupported capability warnings for Clip/CullDistance.

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke 
---
 src/compiler/spirv/spirv_to_nir.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 9c5d331..5ff09c9 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2443,10 +2443,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
   case SpvCapabilityInterpolationFunction:
   case SpvCapabilityMultiViewport:
   case SpvCapabilitySampleRateShading:
- break;
-
   case SpvCapabilityClipDistance:
   case SpvCapabilityCullDistance:
+ break;
+
   case SpvCapabilityGeometryStreams:
   case SpvCapabilityTessellation:
   case SpvCapabilityTessellationPointSize:
-- 
2.10.2

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[Mesa-dev] [PATCH 13/14] anv: Enable clip and cull distance support.

[Kenneth Graunke]

Everything is now in place, and we appear to pass the tests on Gen7+.

Signed-off-by: Kenneth Graunke 
---
 src/intel/vulkan/anv_device.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 0999fcf..2516fc4 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -439,8 +439,8 @@ void anv_GetPhysicalDeviceFeatures(
   .shaderStorageImageArrayDynamicIndexing   = true,
   .shaderStorageImageReadWithoutFormat  = false,
   .shaderStorageImageWriteWithoutFormat = true,
-  .shaderClipDistance   = false,
-  .shaderCullDistance   = false,
+  .shaderClipDistance   = true,
+  .shaderCullDistance   = true,
   .shaderFloat64= false,
   .shaderInt64  = false,
   .shaderInt16  = false,
@@ -576,9 +576,9 @@ void anv_GetPhysicalDeviceProperties(
   .maxSampleMaskWords   = 1,
   .timestampComputeAndGraphics  = false,
   .timestampPeriod  = time_stamp_base,
-  .maxClipDistances = 0 /* FIXME */,
-  .maxCullDistances = 0 /* FIXME */,
-  .maxCombinedClipAndCullDistances  = 0 /* FIXME */,
+  .maxClipDistances = 8,
+  .maxCullDistances = 8,
+  .maxCombinedClipAndCullDistances  = 8,
   .discreteQueuePriorities  = 1,
   .pointSizeRange   = { 0.125, 255.875 },
   .lineWidthRange   = { 0.0, 7.9921875 },
-- 
2.10.2

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[Mesa-dev] [PATCH 14/14] i965: Use NIR-based clip/cull lowering for OpenGL as well.

[Kenneth Graunke]

The old approach works fine, and this approach isn't necessarily better.
But it at least has the advantage that Vulkan and GL use the same
approach.  I originally wrote it to gain additional testing for the
new paths.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_compiler.c | 1 -
 src/mesa/drivers/dri/i965/brw_nir.c  | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 9387d64..1aa72bc 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -126,7 +126,6 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
   compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
-  compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = true;
 
   bool is_scalar = compiler->scalar_stage[i];
 
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index a93d825..e454180 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -485,6 +485,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, 
nir_shader *nir)
/* Get rid of split copies */
nir = nir_optimize(nir, is_scalar);
 
+   OPT_V(nir_lower_clip_cull_distance_arrays);
+
OPT(nir_remove_dead_variables, nir_var_local);
 
return nir;
-- 
2.10.2

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[Mesa-dev] [PATCH 08/14] anv: Combine ClipDistance and CullDistance arrays.

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke 
---
 src/intel/vulkan/anv_pipeline.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bdc2f01..ab268c6 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -166,6 +166,9 @@ anv_shader_compile_to_nir(struct anv_device *device,
 
nir = brw_preprocess_nir(compiler, nir);
 
+   nir_lower_clip_cull_distance_arrays(nir);
+   nir_validate_shader(nir);
+
nir_shader_gather_info(nir, entry_point->impl);
 
nir_variable_mode indirect_mask = 0;
-- 
2.10.2

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[Mesa-dev] [PATCH 11/14] i965/fs: Handle compact outputs.

[Kenneth Graunke]

We need to calculate the number of vec4 slots correctly.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_fs.h   | 2 +-
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index da01174..6446a61 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -191,7 +191,7 @@ public:
 
void emit_nir_code();
void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
-unsigned *location);
+bool is_compact, unsigned *location);
void nir_setup_outputs();
void nir_setup_uniforms();
void nir_emit_system_values();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index e770502..82e22c2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -55,7 +55,9 @@ fs_visitor::nir_setup_outputs()
   return;
 
nir_foreach_variable(var, >outputs) {
-  const unsigned vec4s = type_size_vec4(var->type);
+  const unsigned vec4s =
+ var->data.compact ? DIV_ROUND_UP(glsl_get_length(var->type), 4)
+   : type_size_vec4(var->type);
   fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_F, 4 * vec4s);
   for (unsigned i = 0; i < vec4s; i++) {
  if (outputs[var->data.driver_location + i].file == BAD_FILE)
-- 
2.10.2

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[Mesa-dev] [PATCH 05/14] nir: Add a C wrapper for glsl_type::is_array_of_arrays().

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke 
---
 src/compiler/nir_types.cpp | 6 ++
 src/compiler/nir_types.h   | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index 5b04e18..cc90efd 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -185,6 +185,12 @@ glsl_type_is_array(const struct glsl_type *type)
 }
 
 bool
+glsl_type_is_array_of_arrays(const struct glsl_type *type)
+{
+   return type->is_array_of_arrays();
+}
+
+bool
 glsl_type_is_struct(const struct glsl_type *type)
 {
return type->is_record() || type->is_interface();
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 57f4708..9088a06 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -108,6 +108,7 @@ bool glsl_type_is_scalar(const struct glsl_type *type);
 bool glsl_type_is_vector_or_scalar(const struct glsl_type *type);
 bool glsl_type_is_matrix(const struct glsl_type *type);
 bool glsl_type_is_array(const struct glsl_type *type);
+bool glsl_type_is_array_of_arrays(const struct glsl_type *type);
 bool glsl_type_is_struct(const struct glsl_type *type);
 bool glsl_type_is_sampler(const struct glsl_type *type);
 bool glsl_type_is_image(const struct glsl_type *type);
-- 
2.10.2

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[Mesa-dev] [PATCH 00/14] anv: clip/cull distance support

[Kenneth Graunke]

Hello,

This series adds support for clip/cull distances in the Intel Vulkan
driver.  It works a little differently than how we did it in OpenGL.

In GL, we have a pass that combines both float[] arrays into a single
vec4[2] variable.  Drivers see a vec4[2] with swizzles and writemasks.
The pass is a bit complicated, but works.

This series retains float[] arrays.  It introduces a new "compact array"
concept.  A nir_variable with the "compact" flag set will be tightly
packed into vec4 slots, with one scalar per component, rather than the
usual sparse packing (one scalar per slot).  In other words, a float[8]
compact array will occupy 2 slots, rather than 8 slots.  nir_lower_io
uses the location field for the array index / 4, and the "component"
field (from ARB_enhanced_layouts) for the array index % 4.

We still need a pass to pack clip/cull distances together into a single
array, rather than two arrays.  It's pretty straightforward.

I'm not sure whether this is a better approach than just converting to
vec4[2] and swizzles/writemasks.  It's pretty simple, and will likely
be reusable for gl_TessLevelInner/Outer[] as well.

The last patch uses the new approach in OpenGL, mostly for testing
purposes.  I ran shader-db statistics for programs using ClipDistance,
and the instruction counts were identical via either method.

--Ken


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[Mesa-dev] [PATCH 07/14] nir: add a pass to compact clip/cull distances.

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke 
---
 src/compiler/Makefile.sources  |   1 +
 src/compiler/nir/nir.h |   1 +
 .../nir/nir_lower_clip_cull_distance_arrays.c  | 187 +
 3 files changed, 189 insertions(+)
 create mode 100644 src/compiler/nir/nir_lower_clip_cull_distance_arrays.c

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 08d93e0..6c331b0 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -202,6 +202,7 @@ NIR_FILES = \
nir/nir_lower_bitmap.c \
nir/nir_lower_clamp_color_outputs.c \
nir/nir_lower_clip.c \
+   nir/nir_lower_clip_cull_distance_arrays.c \
nir/nir_lower_double_ops.c \
nir/nir_lower_double_packing.c \
nir/nir_lower_drawpixels.c \
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 0b78242..f3aadb9 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2441,6 +2441,7 @@ bool nir_lower_idiv(nir_shader *shader);
 
 void nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables);
 void nir_lower_clip_fs(nir_shader *shader, unsigned ucp_enables);
+void nir_lower_clip_cull_distance_arrays(nir_shader *nir);
 
 void nir_lower_two_sided_color(nir_shader *shader);
 
diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c 
b/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c
new file mode 100644
index 000..9f8a7de
--- /dev/null
+++ b/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+
+/**
+ * @file
+ *
+ * This pass combines separate clip and cull distance arrays into a
+ * single array that contains both.  Clip distances come first, then
+ * cull distances.  It also populates nir_shader_info with the size
+ * of the original arrays so the driver knows which are which.
+ */
+
+/**
+ * Get the length of the clip/cull distance array, looking past
+ * any interface block arrays.
+ */
+static unsigned
+get_unwrapped_array_length(nir_variable *var)
+{
+   if (!var)
+  return 0;
+
+   /* Unwrap GS input and TCS input/output interfaces.  We want the
+* underlying clip/cull distance array length, not the per-vertex
+* array length.
+*/
+   const struct glsl_type *type = var->type;
+   if (glsl_type_is_array_of_arrays(type))
+  type = glsl_get_array_element(type);
+
+   return glsl_get_length(type);
+}
+
+/**
+ * Get the type of the combined array (including interface block nesting).
+ */
+static const struct glsl_type *
+get_new_array_type(const struct glsl_type *old_type, unsigned length)
+{
+   const struct glsl_type *type = glsl_array_type(glsl_float_type(), length);
+
+   if (glsl_type_is_array_of_arrays(old_type))
+  type = glsl_array_type(type, glsl_get_length(type));
+
+   return type;
+}
+
+/**
+ * Rewrite any clip/cull distances to refer to the new combined array.
+ */
+static void
+rewrite_references(nir_instr *instr,
+   nir_variable *combined,
+   unsigned cull_offset)
+{
+   if (instr->type != nir_instr_type_intrinsic)
+  return;
+
+   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+
+   /* copy_var needs to be lowered to load/store before calling this pass */
+   assert(intrin->intrinsic != nir_intrinsic_copy_var);
+
+   if (intrin->intrinsic != nir_intrinsic_load_var &&
+   intrin->intrinsic != nir_intrinsic_store_var)
+  return;
+
+   nir_deref_var *var_ref = intrin->variables[0];
+   if (var_ref->var->data.mode != combined->data.mode)
+  return;
+
+   if (var_ref->var->data.location != VARYING_SLOT_CLIP_DIST0 &&
+   var_ref->var->data.location != VARYING_SLOT_CULL_DIST0)
+  return;
+
+   /* Update types along the deref chain 

[Mesa-dev] [PATCH 09/14] anv: Set clip/cull distances fields in packets.

[Kenneth Graunke]

Signed-off-by: Kenneth Graunke 
---
 src/intel/vulkan/anv_private.h| 18 ++
 src/intel/vulkan/gen8_pipeline.c  | 15 ---
 src/intel/vulkan/genX_pipeline_util.h |  5 +
 3 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 30deb02..eef2926 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1445,6 +1445,24 @@ ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
 
+/**
+ * Get the brw_vue_prog_data for the last stage which outputs VUEs.
+ */
+static inline struct brw_vue_prog_data *
+get_last_vue_prog_data(struct anv_pipeline *pipeline)
+{
+   const unsigned pre_clip_stages =
+  pipeline->active_stages & (VK_SHADER_STAGE_FRAGMENT_BIT - 1);
+   const unsigned last_bit = util_last_bit(pre_clip_stages);
+
+   if (last_bit == 0)
+  return NULL;
+
+   struct anv_shader_bin *bin = pipeline->shaders[last_bit - 1];
+
+   return (struct brw_vue_prog_data *) bin->prog_data;
+}
+
 VkResult
 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
   struct anv_pipeline_cache *cache,
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index 6cf55f5..4fad8cd 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -158,10 +158,10 @@ genX(graphics_pipeline_create)(
 gs_prog_data->static_vertex_count >= 0 ?
 gs_prog_data->static_vertex_count : 0;
 
- /* FIXME: mesa sets this based on ctx->Transform.ClipPlanesEnabled:
-  * UserClipDistanceClipTestEnableBitmask_3DSTATE_GS(v)
-  * UserClipDistanceCullTestEnableBitmask(v)
-  */
+ gs.UserClipDistanceClipTestEnableBitmask =
+gs_prog_data->base.clip_distance_mask;
+ gs.UserClipDistanceCullTestEnableBitmask =
+gs_prog_data->base.cull_distance_mask;
 
  gs.VertexURBEntryOutputReadOffset = offset;
  gs.VertexURBEntryOutputLength = length;
@@ -224,9 +224,10 @@ genX(graphics_pipeline_create)(
  vs.VertexURBEntryOutputReadOffset = offset;
  vs.VertexURBEntryOutputLength= length;
 
- /* TODO */
- vs.UserClipDistanceClipTestEnableBitmask = 0;
- vs.UserClipDistanceCullTestEnableBitmask = 0;
+ vs.UserClipDistanceClipTestEnableBitmask =
+vs_prog_data->base.clip_distance_mask;
+ vs.UserClipDistanceCullTestEnableBitmask =
+vs_prog_data->base.cull_distance_mask;
   }
}
 
diff --git a/src/intel/vulkan/genX_pipeline_util.h 
b/src/intel/vulkan/genX_pipeline_util.h
index 129ae94..5bee80c 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -940,6 +940,11 @@ emit_3dstate_clip(struct anv_pipeline *pipeline,
   clip.FrontWinding= vk_to_gen_front_face[rs_info->frontFace];
   clip.CullMode= vk_to_gen_cullmode[rs_info->cullMode];
   clip.ViewportZClipTestEnable = !pipeline->depth_clamp_enable;
+  const struct brw_vue_prog_data *last = get_last_vue_prog_data(pipeline);
+  if (last) {
+ clip.UserClipDistanceClipTestEnableBitmask = last->clip_distance_mask;
+ clip.UserClipDistanceCullTestEnableBitmask = last->cull_distance_mask;
+  }
 #else
   clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
  (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
-- 
2.10.2

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[Mesa-dev] [PATCH 04/14] i965: Store a clip_distance_mask field similar to cull_distance_mask.

[Kenneth Graunke]

This isn't useful for legacy GL, but will be used in Vulkan.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_compiler.h  | 1 +
 src/mesa/drivers/dri/i965/brw_shader.cpp  | 2 ++
 src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 ++
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 2 ++
 4 files changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h 
b/src/mesa/drivers/dri/i965/brw_compiler.h
index c2400f9..65a7478 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -626,6 +626,7 @@ struct brw_vue_prog_data {
GLuint urb_read_length;
GLuint total_grf;
 
+   uint32_t clip_distance_mask;
uint32_t cull_distance_mask;
 
/* Used for calculating urb partitions.  In the VS, this is the size of the
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index e44a845..e367900 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1376,6 +1376,8 @@ brw_compile_tes(const struct brw_compiler *compiler,
   return NULL;
}
 
+   prog_data->base.clip_distance_mask =
+  ((1 << nir->info->clip_distance_array_size) - 1);
prog_data->base.cull_distance_mask =
   ((1 << nir->info->cull_distance_array_size) - 1) <<
   nir->info->clip_distance_array_size;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 4da8f6e..b9e592f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2121,6 +2121,8 @@ brw_compile_vs(const struct brw_compiler *compiler, void 
*log_data,
 
const unsigned *assembly = NULL;
 
+   prog_data->base.clip_distance_mask =
+  ((1 << shader->info->clip_distance_array_size) - 1);
prog_data->base.cull_distance_mask =
   ((1 << shader->info->cull_distance_array_size) - 1) <<
   shader->info->clip_distance_array_size;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 5e2dcc0..900d9d3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -621,6 +621,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void 
*log_data,
brw_nir_lower_vue_outputs(shader, is_scalar);
shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
 
+   prog_data->base.clip_distance_mask =
+  ((1 << shader->info->clip_distance_array_size) - 1);
prog_data->base.cull_distance_mask =
   ((1 << shader->info->cull_distance_array_size) - 1) <<
   shader->info->clip_distance_array_size;
-- 
2.10.2

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[Mesa-dev] [PATCH 02/14] compiler: Store the clip/cull distance array sizes in shader_info.

[Kenneth Graunke]

We switched from a boolean to array lengths in gl_program a while back.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glsl_to_nir.cpp | 4 ++--
 src/compiler/shader_info.h| 7 +--
 src/mesa/program/prog_to_nir.c| 3 ++-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index 096ab4c..6ca760b 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -152,8 +152,8 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
shader->info->num_abos = shader_prog->NumAtomicBuffers;
shader->info->num_ssbos = sh->NumShaderStorageBlocks;
shader->info->num_images = sh->NumImages;
-   shader->info->uses_clip_distance_out =
-  sh->Program->ClipDistanceArraySize != 0;
+   shader->info->clip_distance_array_size = sh->Program->ClipDistanceArraySize;
+   shader->info->cull_distance_array_size = sh->Program->CullDistanceArraySize;
shader->info->separate_shader = shader_prog->SeparateShader;
shader->info->has_transform_feedback_varyings =
   shader_prog->TransformFeedback.NumVarying > 0;
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index b449900..fbc3834 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -65,8 +65,11 @@ typedef struct shader_info {
/* Whether or not this shader ever uses textureGather() */
bool uses_texture_gather;
 
-   /* Whether or not this shader uses the gl_ClipDistance output */
-   bool uses_clip_distance_out;
+   /* The size of the gl_ClipDistance[] array, if declared. */
+   unsigned clip_distance_array_size;
+
+   /* The size of the gl_CullDistance[] array, if declared. */
+   unsigned cull_distance_array_size;
 
/* Whether or not separate shader objects were used */
bool separate_shader;
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 08df05d..3239dd5 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -1052,7 +1052,8 @@ prog_to_nir(const struct gl_program *prog,
s->info->num_ssbos = 0;
s->info->num_images = 0;
s->info->uses_texture_gather = false;
-   s->info->uses_clip_distance_out = false;
+   s->info->clip_distance_array_size = 0;
+   s->info->cull_distance_array_size = 0;
s->info->separate_shader = false;
 
 fail:
-- 
2.10.2

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[Mesa-dev] [PATCH 01/14] i965: Fix GS push inputs with enhanced layouts.

[Kenneth Graunke]

We weren't taking first_component into account when handling GS push
inputs.  We hardly ever push GS inputs, so this was not caught by
existing tests.  When I started using component qualifiers for the
gl_ClipDistance arrays, glsl-1.50-transform-feedback-type-and-size
started catching this.

Cc: "13.0" 
Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index e84e371..e770502 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1984,7 +1984,7 @@ fs_visitor::emit_gs_input_load(const fs_reg ,
   } else {
  for (unsigned i = 0; i < num_components; i++) {
 bld.MOV(offset(dst, bld, i),
-fs_reg(ATTR, imm_offset + i, dst.type));
+fs_reg(ATTR, imm_offset + i + first_component, dst.type));
  }
   }
   return;
-- 
2.10.2

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Re: [Mesa-dev] Compute shader support in LLVMpipe and/or OpenSWR?

[A223 A223]

On Sun, Nov 13, 2016 at 11:58 PM, A223 A223  wrote:
> Hello,
>
> I was curious if there are any near/medium-term plans to add compute
> shader support to the following:
>
> llvmpipe?
> openswr?

CCing Ilia Mirkin, as I feel you may know something about this for
SWR... Thank you.
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Re: [Mesa-dev] GL_ARB_copy_image in OpenSWR?

[A223 A223]

On Mon, Nov 14, 2016 at 11:10 AM, Ilia Mirkin  wrote:
> On Mon, Nov 14, 2016 at 1:53 PM, A223 A223  wrote:
>> On Mon, Nov 14, 2016 at 10:37 AM, Ilia Mirkin  wrote:
>>> My guess is that it can just be flipped on. You can force-enable it
>>> with MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image to see if it works.
>>
>> This does indeed get rid of the error. I'm still getting a white clear
>> color in my OpenGL application, and I'm not sure why -- llvmpipe shows
>> black as expected. Perhaps something odd is happening with the
>> glClear* calls. I'll see if I can track down what's going on.
>
> You may want to try it with my tree at
> https://github.com/imirkin/mesa/commits/swr - get rid of the top 2
> commits though, they're not ready for prime time.
>
> I fixed a ton of issues around rendering and whatnot. Clearing is
> still broken if you have multiple RTs though - it'll only clear the
> first one.

Thanks. I gave that a shot but still get white instead of the expected black.
I see now that we're not actually doing glClear() for this, we're just
rendering a black skybox with glFragColor = rgba 0/0/0/1 in the frag
shader.
The oddity here is that if I draw with a slightly non-black color --
say rgba 0.1/0.1/0.1/1 -- It works as expected and I get a very dark
gray.
Again, works fine on llvmpipe but not on swr. I'll continue looking at
it. Let me know if you have any hunches.
Thanks, Andrew
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Re: [Mesa-dev] GL_ARB_copy_image in OpenSWR?

[A223 A223]

On Mon, Nov 14, 2016 at 10:37 AM, Ilia Mirkin  wrote:
> My guess is that it can just be flipped on. You can force-enable it
> with MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image to see if it works.

This does indeed get rid of the error. I'm still getting a white clear
color in my OpenGL application, and I'm not sure why -- llvmpipe shows
black as expected. Perhaps something odd is happening with the
glClear* calls. I'll see if I can track down what's going on.
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[Mesa-dev] softpipe and PIPE_CAP_MIXED_COLORBUFFER_FORMATS?

[A223 A223]

My application requires PIPE_CAP_MIXED_COLORBUFFER_FORMATS and I
noticed that it is not enabled for softpipe. I hardcoded it to be
turned on and did not notice any ill effects so far.

Is it necessary that PIPE_CAP_MIXED_COLORBUFFER_FORMATS be disabled
for softpipe?
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[Mesa-dev] GL_ARB_copy_image in OpenSWR?

[A223 A223]

Is there any possibility that SWR will see GL_ARB_copy_image support
sometime soon?

Thanks,
Andrew
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[Mesa-dev] Compute shader support in LLVMpipe and/or OpenSWR?

[A223 A223]

Hello,

I was curious if there are any near/medium-term plans to add compute
shader support to the following:

llvmpipe?
openswr?

Thanks!

Andrew
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[Mesa-dev] [PATCH 3/3] swr: mark color clamping as unsupported

[Ilia Mirkin]

There is no functionality in swr to clamp either vertex or frag colors.
This could be added in swr_shader, at which point these could be
re-enabled.

Fixes arb_color_buffer_float-render

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/swr/swr_screen.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
b/src/gallium/drivers/swr/swr_screen.cpp
index e52f8d2..0b1d61d 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -235,8 +235,9 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TEXTURE_BARRIER:
   return 0;
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
-   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: /* draw module */
-   case PIPE_CAP_VERTEX_COLOR_CLAMPED: /* draw module */
+   case PIPE_CAP_VERTEX_COLOR_CLAMPED:
+  return 0;
+   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
   return 1;
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
   return 1;
-- 
2.7.3

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[Mesa-dev] [PATCH 2/3] swr: always enable adding start/base vertex to gl_VertexId

[Ilia Mirkin]

Fixes gl-3.2-basevertex-vertexid

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/swr/swr_state.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/swr/swr_state.cpp 
b/src/gallium/drivers/swr/swr_state.cpp
index 2c7f3be..8038ef5 100644
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -447,6 +447,7 @@ swr_create_vertex_elements_state(struct pipe_context *pipe,
assert(num_elements <= PIPE_MAX_ATTRIBS);
velems = CALLOC_STRUCT(swr_vertex_element_state);
if (velems) {
+  velems->fsState.bVertexIDOffsetEnable = true;
   velems->fsState.numAttribs = num_elements;
   for (unsigned i = 0; i < num_elements; i++) {
  // XXX: we should do this keyed on the VS usage info
-- 
2.7.3

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[Mesa-dev] [PATCH 1/3] swr: add support for upper-left fragcoord position

[Ilia Mirkin]

Fixes glsl-arb-fragment-coord-conventions.

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/swr/swr_shader.cpp | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_shader.cpp 
b/src/gallium/drivers/swr/swr_shader.cpp
index f639df3..e4f9796 100644
--- a/src/gallium/drivers/swr/swr_shader.cpp
+++ b/src/gallium/drivers/swr/swr_shader.cpp
@@ -500,8 +500,14 @@ BuilderSWR::CompileFS(struct swr_context *ctx, 
swr_jit_fs_key )
  inputs[attrib][3] = wrap(VIMMED1(1.0f));
  continue;
   } else if (semantic_name == TGSI_SEMANTIC_POSITION) { // gl_FragCoord
- inputs[attrib][0] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vX, 
PixelPositions_center}, "vX"));
- inputs[attrib][1] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vY, 
PixelPositions_center}, "vY"));
+ if (swr_fs->info.base.properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] 
==
+ TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER) {
+inputs[attrib][0] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vX, 
PixelPositions_center}, "vX"));
+inputs[attrib][1] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vY, 
PixelPositions_center}, "vY"));
+ } else {
+inputs[attrib][0] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vX, 
PixelPositions_UL}, "vX"));
+inputs[attrib][1] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vY, 
PixelPositions_UL}, "vY"));
+ }
  inputs[attrib][2] = wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vZ}, "vZ"));
  inputs[attrib][3] =
 wrap(LOAD(pPS, {0, SWR_PS_CONTEXT_vOneOverW, 
PixelPositions_center}, "vOneOverW"));
-- 
2.7.3

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[Mesa-dev] [PATCH v3] meta/GetTexSubImage: Account for GL_PACK_SKIP_IMAGES on compressed textures

[Kenneth Graunke]

From: Eduardo Lima Mitev 

This option was being ignored when packing compressed 3D and cube textures.

Fixes CTS test (on gen8+):
* GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pixelstore

v2: Drop API checks.
v3 (Ken): Just apply the existing code in more cases.
---
 src/mesa/drivers/common/meta.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

Hey Eduardo,

It looks like the existing code already tries to handle SkipImages - but
we weren't applying it for 3D and cubemap textures.  I found a spec quote
in the narrative for GetTexImage that indicates we need to do it for those
as well.

What do you think of this version?  I preserved your authorship as I wanted
you to get the credit for this bugfix - I just typed it up so that I could
make sure it actually fixed the test, and since I had it typed up, I figured
I'd send it out to save you some time...

 --Ken

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 5ab1e6c..99c85cf 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -3243,8 +3243,20 @@ _mesa_meta_GetTexSubImage(struct gl_context *ctx,
 
   for (slice = 0; slice < depth; slice++) {
  void *dst;
- if (texImage->TexObject->Target == GL_TEXTURE_2D_ARRAY
- || texImage->TexObject->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ /* Section 8.11.4 (Texture Image Queries) of the GL 4.5 spec says:
+  *
+  *"For three-dimensional, two-dimensional array, cube map array,
+  * and cube map textures pixel storage operations are applied as
+  * if the image were two-dimensional, except that the additional
+  * pixel storage state values PACK_IMAGE_HEIGHT and
+  * PACK_SKIP_IMAGES are applied. The correspondence of texels to
+  * memory locations is as defined for TexImage3D in section 8.5."
+  */
+ switch (texImage->TexObject->Target) {
+ case GL_TEXTURE_3D:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY: {
 /* Setup pixel packing.  SkipPixels and SkipRows will be applied
  * in the decompress_texture_image() function's call to
  * glReadPixels but we need to compute the dest slice's address
@@ -3255,9 +3267,11 @@ _mesa_meta_GetTexSubImage(struct gl_context *ctx,
 packing.SkipRows = 0;
 dst = _mesa_image_address3d(, pixels, width, height,
 format, type, slice, 0, 0);
+break;
  }
- else {
+ default:
 dst = pixels;
+break;
  }
  result = decompress_texture_image(ctx, texImage, slice,
xoffset, yoffset, width, height,
-- 
2.10.2

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[Mesa-dev] Stable release process

[Matt Turner]

A long time ago, patch authors were tasked with cherry-picking their
patches to stable branches. Today we Cc
mesa-sta...@lists.freedesktop.org and Emil rebases those patches onto
stable. Cc'ing the list happens even on patches sent for their first
review that are ultimately rejected, creating a lot of noise (and
presumably makes the mailing list less useful).

Initial questions:

Is the mesa-stable@ mailing list useful (other than as a tag in a
committed patch)?

What do "nominated" and "queued" in the stable release candidate
announcements actually mean?

Should driver maintainers cherry-pick patches to stable on their own?

Regardless of the outcome of that question, I think we would the
process would be more transparent and predictable if patches were
incorporated into the branch over time rather than all at once a few
days before the release.
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Re: [Mesa-dev] [PATCH v2 6/8] gallium: Enable swr driver

[Jose Fonseca]

On 10/11/16 17:27, Kyriazis, George wrote:




-Original Message-
From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
Sent: Thursday, November 10, 2016 8:14 AM
To: Kyriazis, George 
Cc: ML mesa-dev 
Subject: Re: [Mesa-dev] [PATCH v2 6/8] gallium: Enable swr driver

"gallium/targets: scons: wire swr support for libgl-gdi/libgl-xlib/osmesa"

... or alike ?


+import SCons.Script.SConscript
+



+if 'swr' in SCons.Script.ARGUMENTS and

SCons.Script.ARGUMENTS['swr']:
With the "move this to top level" suggestion this will read roughly as

if env['swr']:


The command line variables, however (like swr=1) are not part of the 
environment.  Even then, env['swr'] would fail for non-swr builds, since 'swr' 
is not in the env dictionary.  This works for env['llvm'] sincellvm.py 
initially sets it to False.  So, it will still be a 2-level test:   if 'swr' in 
env and env['swr']:, which is not a simplication really.

Is your point to move it to the environment, or to do a one-check test?

Thanks,

George


-Emil

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What you need is this:


diff --git a/common.py b/common.py
index fb0884e..179170b 100644
--- a/common.py
+++ b/common.py
@@ -110,5 +110,6 @@ def AddOptions(opts):
 opts.Add(BoolOption('texture_float',
 'enable floating-point textures and 
renderbuffers',

 'no'))
+opts.Add(BoolOption('swr', 'Build SWR', 'no'))
 if host_platform == 'windows':
 opts.Add('MSVC_VERSION', 'Microsoft Visual C/C++ version')

Then swr should always be part of the environment.


Jose
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Re: [Mesa-dev] [PATCH 08/20] anv/pipeline: Unify 3DSTATE_GS emission

[Timothy Arceri]

On Mon, 2016-11-14 at 08:46 -0800, Jason Ekstrand wrote:
> 
> 
> On Sat, Nov 12, 2016 at 2:54 PM, Timothy Arceri  bora.com> wrote:
> > On Sat, 2016-11-12 at 13:34 -0800, Jason Ekstrand wrote:
> > 
> > I have two questions and two suggestions below. 
> > 
> > With the suggestions addressed and assuming the answer to both
> > questions is yes, Patch 7-8 are:
> > 
> > Reviewed-by: Timothy Arceri 
> > 
> > > ---
> > >  src/intel/vulkan/gen7_pipeline.c  | 48 +--
> > 
> > >  src/intel/vulkan/gen8_pipeline.c  | 62 +--
> > 
> > > --
> > >  src/intel/vulkan/genX_pipeline_util.h | 73
> > > +++
> > >  3 files changed, 75 insertions(+), 108 deletions(-)
> > >
> > > diff --git a/src/intel/vulkan/gen7_pipeline.c
> > > b/src/intel/vulkan/gen7_pipeline.c
> > > index e604c25..52577f5 100644
> > > --- a/src/intel/vulkan/gen7_pipeline.c
> > > +++ b/src/intel/vulkan/gen7_pipeline.c
> > > @@ -105,53 +105,7 @@ genX(graphics_pipeline_create)(
> > >  #endif
> > >  
> > > emit_3dstate_vs(pipeline);
> > > -
> > > -   const struct brw_gs_prog_data *gs_prog_data =
> > > get_gs_prog_data(pipeline);
> > > -
> > > -   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
> > {
> > > -  anv_batch_emit(>batch, GENX(3DSTATE_GS), gs);
> > > -   } else {
> > > -  const struct anv_shader_bin *gs_bin =
> > > - pipeline->shaders[MESA_SHADER_GEOMETRY];
> > > -
> > > -  anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
> > > - gs.KernelStartPointer = gs_bin->kernel.offset;
> > > -
> > > - gs.ScratchSpaceBasePointer = (struct anv_address) {
> > > -.bo = anv_scratch_pool_alloc(device, 
> > > >scratch_pool,
> > > - MESA_SHADER_GEOMETRY,
> > > - gs_prog_data-
> > > >base.base.total_scratch),
> > > -.offset = 0,
> > > - };
> > > - gs.PerThreadScratchSpace  =
> > > scratch_space(_prog_data->base.base);
> > > -
> > > - gs.OutputVertexSize   = gs_prog_data-
> > > >output_vertex_size_hwords * 2 - 1;
> > > - gs.OutputTopology = gs_prog_data-
> > > >output_topology;
> > > - gs.VertexURBEntryReadLength   = gs_prog_data-
> > > >base.urb_read_length;
> > > - gs.IncludeVertexHandles   = gs_prog_data-
> > > >base.include_vue_handles;
> > > -
> > > - gs.DispatchGRFStartRegisterForURBData =
> > > -gs_prog_data->base.base.dispatch_grf_start_reg;
> > > -
> > > - gs.SamplerCount  =
> > get_sampler_count(gs_bin);
> > > - gs.BindingTableEntryCount=
> > > get_binding_table_entry_count(gs_bin);
> > > -
> > > - gs.MaximumNumberofThreads = devinfo->max_gs_threads 
> > -
> > > 1;
> > > - /* This in the next dword on HSW. */
> > > - gs.ControlDataFormat  = gs_prog_data-
> > > >control_data_format;
> > > - gs.ControlDataHeaderSize  = gs_prog_data-
> > > >control_data_header_size_hwords;
> > > - gs.InstanceControl= MAX2(gs_prog_data-
> > > >invocations, 1) - 1;
> > > - gs.DispatchMode   = gs_prog_data-
> > > >base.dispatch_mode;
> > > - gs.StatisticsEnable   = true;
> > > - gs.IncludePrimitiveID = gs_prog_data-
> > > >include_primitive_id;
> > > -# if (GEN_IS_HASWELL)
> > > - gs.ReorderMode= REORDER_TRAILING;
> > 
> > Shouldn't we have changed REORDER_TRAILING to TRAILING in
> > src/intel/genxml/gen75.xml in the previous patch?
> 
> Yeah, I'll do that.
>  
> > > -# else
> > > - gs.ReorderEnable  = true;
> > > -# endif
> > > - gs.FunctionEnable = true;
> > > -  }
> > > -   }
> > > +   emit_3dstate_gs(pipeline);
> > >  
> > > if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
> > {
> > >    anv_batch_emit(>batch, GENX(3DSTATE_SBE), sbe);
> > > diff --git a/src/intel/vulkan/gen8_pipeline.c
> > > b/src/intel/vulkan/gen8_pipeline.c
> > > index 1320a13..5816bd4 100644
> > > --- a/src/intel/vulkan/gen8_pipeline.c
> > > +++ b/src/intel/vulkan/gen8_pipeline.c
> > > @@ -53,9 +53,6 @@ genX(graphics_pipeline_create)(
> > >  {
> > > ANV_FROM_HANDLE(anv_device, device, _device);
> > > ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo-
> > >renderPass);
> > > -   const struct anv_physical_device *physical_device =
> > > -  >instance->physicalDevice;
> > > -   const struct gen_device_info *devinfo = _device-
> > >info;
> > > struct anv_subpass *subpass = >subpasses[pCreateInfo-
> > > >subpass];
> > > struct anv_pipeline *pipeline;
> > > VkResult result;
> > > @@ -112,64 +109,7 @@ genX(graphics_pipeline_create)(
> > >   wm_prog_data ? wm_prog_data->barycentric_interp_modes :
> > 0;
> > > }
> > >  
> > > -   if 

Re: [Mesa-dev] Compute shader support in LLVMpipe and/or OpenSWR?

[Ilia Mirkin]

On Mon, Nov 14, 2016 at 1:48 PM, A223 A223  wrote:
> On Sun, Nov 13, 2016 at 11:58 PM, A223 A223  wrote:
>> Hello,
>>
>> I was curious if there are any near/medium-term plans to add compute
>> shader support to the following:
>>
>> llvmpipe?
>> openswr?
>
> CCing Ilia Mirkin, as I feel you may know something about this for
> SWR... Thank you.

I'm not aware of any plans. The biggest issue is how to properly
support barriers, which means some sort of state execution
suspend/resume is necessary inside the shaders, since a thread group
may be up to 1024-wide.

  -ilia
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Re: [Mesa-dev] GL_ARB_copy_image in OpenSWR?

[Ilia Mirkin]

On Mon, Nov 14, 2016 at 1:53 PM, A223 A223  wrote:
> On Mon, Nov 14, 2016 at 10:37 AM, Ilia Mirkin  wrote:
>> My guess is that it can just be flipped on. You can force-enable it
>> with MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image to see if it works.
>
> This does indeed get rid of the error. I'm still getting a white clear
> color in my OpenGL application, and I'm not sure why -- llvmpipe shows
> black as expected. Perhaps something odd is happening with the
> glClear* calls. I'll see if I can track down what's going on.

You may want to try it with my tree at
https://github.com/imirkin/mesa/commits/swr - get rid of the top 2
commits though, they're not ready for prime time.

I fixed a ton of issues around rendering and whatnot. Clearing is
still broken if you have multiple RTs though - it'll only clear the
first one.

  -ilia
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Re: [Mesa-dev] GL_ARB_copy_image in OpenSWR?

[Ilia Mirkin]

My guess is that it can just be flipped on. You can force-enable it
with MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image to see if it works.

Cheers,

  -ilia


On Mon, Nov 14, 2016 at 1:34 PM, A223 A223  wrote:
> Is there any possibility that SWR will see GL_ARB_copy_image support
> sometime soon?
>
> Thanks,
> Andrew
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Re: [Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 00/20] anv: Unify pipeline setup across gens

[Kristian Høgsberg]

On Sat, Nov 12, 2016 at 1:35 PM Jason Ekstrand  wrote:

> This series started off as me thinking that we should set the correct
> sampler and binding table entry counts because maybe caching those things
> would improve performance.  Then it turned into spring cleaning.  The end
> result is that gen7_pipeline.c, gen8_pipeline.c, and genX_pipeline_util.h
> are all merged into genX_pipeline.c.  Every single packet in pipeline setup
> now has a common path.
>

This looks great, thanks for finally unifying things the way we always
meant to and getting rid of genX_pipeline_util.h.

For the series:

Reviewed-by: Kristian H. Kristensen 


> I still haven't tested the performance of cached sampler states.
>

I'd be interested to hear if you're able to measure anything one way or the
other.

Kristian


>
> Jason Ekstrand (20):
>   anv/pipeline: Set correct binding table and sampler counts
>   anv/pipeline: Get rid of the kernel pointer fields
>   intel/genxml: Make some VS/GS fields consistent across gens
>   anv/pipeline: Stop claiming to support running without a vertex shader
>   anv/pipeline/gen8: Enable VS statistics
>   anv/pipeline: Unify 3DSTATE_VS emission
>   intel/genxml: Make some 3DSTATE_GS fields more consistent
>   anv/pipeline: Unify 3DSTATE_GS emission
>   anv/pipeline: Make emit_3dstate_sbe safe to call without a FS
>   intel/genxml: Make some 3DSTATE_PS fields more consistent
>   anv/pipeline: Unify 3DSTATE_PS emission
>   intel/genxml: Make 3DSTATE_WM more consistent across gens
>   anv/pipeline: Unify 3DSTATE_WM emission
>   anv/pipeline: Move 3DSTATE_PS_EXTRA setup into a helper
>   anv/pipeline: Rework the 3DSTATE_VF_TOPOLOGY helper
>   anv/pipline: Re-order state emission and make it consistent
>   anv/pipeline: Unify graphics_pipeline_create
>   anv/pipeline: Roll genX_pipeline_util.h into genX_pipeline.c
>   anv: Move INTERFACE_DESCRIPTOR_DATA setup to the pipeline
>   anv/pipeline: Use get_scratch_space/address for compute shaders
>
>  src/intel/blorp/blorp_genX_exec.h |   12 +-
>  src/intel/genxml/gen6.xml |   32 +-
>  src/intel/genxml/gen7.xml |   32 +-
>  src/intel/genxml/gen75.xml|   32 +-
>  src/intel/genxml/gen8.xml |8 +-
>  src/intel/genxml/gen9.xml |8 +-
>  src/intel/vulkan/Makefile.sources |5 -
>  src/intel/vulkan/anv_genX.h   |7 -
>  src/intel/vulkan/anv_pipeline.c   |   22 -
>  src/intel/vulkan/anv_private.h|7 +-
>  src/intel/vulkan/gen7_pipeline.c  |  281 ---
>  src/intel/vulkan/gen8_pipeline.c  |  295 ---
>  src/intel/vulkan/genX_cmd_buffer.c|   35 +-
>  src/intel/vulkan/genX_pipeline.c  | 1393
> -
>  src/intel/vulkan/genX_pipeline_util.h |  959 ---
>  15 files changed, 1471 insertions(+), 1657 deletions(-)
>  delete mode 100644 src/intel/vulkan/gen7_pipeline.c
>  delete mode 100644 src/intel/vulkan/gen8_pipeline.c
>  delete mode 100644 src/intel/vulkan/genX_pipeline_util.h
>
> --
> 2.5.0.400.gff86faf
>
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Re: [Mesa-dev] [PATCH 08/14] swr: [rasterizer core/jitter] fix alpha test bug

[Ilia Mirkin]

It seems like this still doesn't quite fix things - have a look at
fbo-mrt-alphatest in piglit. I had assumed this change would do the
trick, but no such luck.

On Wed, Nov 9, 2016 at 10:18 PM, Tim Rowley  wrote:
> Alpha from render target 0 should always be used for alpha test for all
> render targets, according to GL and DX9 specs. Previously we were using
> alpha from the current render target.
> ---
>  src/gallium/drivers/swr/rasterizer/core/backend.h   |  1 +
>  src/gallium/drivers/swr/rasterizer/core/state.h |  6 +-
>  src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp | 10 --
>  3 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.h 
> b/src/gallium/drivers/swr/rasterizer/core/backend.h
> index dc0be90..a7018e0 100644
> --- a/src/gallium/drivers/swr/rasterizer/core/backend.h
> +++ b/src/gallium/drivers/swr/rasterizer/core/backend.h
> @@ -714,6 +714,7 @@ INLINE void OutputMerger(SWR_PS_CONTEXT , 
> uint8_t* ()[SWR_N
>  pBlendState,
>  psContext.shaded[rt],
>  psContext.shaded[1],
> +psContext.shaded[0].w,
>  sample,
>  pColorSample,
>  blendOut,
> diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h 
> b/src/gallium/drivers/swr/rasterizer/core/state.h
> index 5ee12e8..24927cd 100644
> --- a/src/gallium/drivers/swr/rasterizer/core/state.h
> +++ b/src/gallium/drivers/swr/rasterizer/core/state.h
> @@ -805,9 +805,13 @@ typedef void(__cdecl *PFN_CS_FUNC)(HANDLE hPrivateData, 
> SWR_CS_CONTEXT* pCsConte
>  typedef void(__cdecl *PFN_SO_FUNC)(SWR_STREAMOUT_CONTEXT& soContext);
>  typedef void(__cdecl *PFN_PIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT 
> *pContext);
>  typedef void(__cdecl *PFN_CPIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT 
> *pContext);
> -typedef void(__cdecl *PFN_BLEND_JIT_FUNC)(const SWR_BLEND_STATE*, 
> simdvector&, simdvector&, uint32_t, uint8_t*, simdvector&, simdscalari*, 
> simdscalari*);
> +typedef void(__cdecl *PFN_BLEND_JIT_FUNC)(const SWR_BLEND_STATE*,
> +simdvector& vSrc, simdvector& vSrc1, simdscalar& vSrc0Alpha, uint32_t 
> sample,
> +uint8_t* pDst, simdvector& vResult, simdscalari* vOMask, simdscalari* 
> vCoverageMask);
>  typedef simdscalar(*PFN_QUANTIZE_DEPTH)(simdscalar);
>
> +
> +
>  //
>  /// FRONTEND_STATE
>  /
> diff --git a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp 
> b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> index d69d503..43e3d36 100644
> --- a/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> +++ b/src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
> @@ -443,10 +443,13 @@ struct BlendJit : public Builder
>  }
>  }
>
> -void AlphaTest(const BLEND_COMPILE_STATE& state, Value* pBlendState, 
> Value* pAlpha, Value* ppMask)
> +void AlphaTest(const BLEND_COMPILE_STATE& state, Value* pBlendState, 
> Value* ppAlpha, Value* ppMask)
>  {
>  // load uint32_t reference
>  Value* pRef = VBROADCAST(LOAD(pBlendState, { 0, 
> SWR_BLEND_STATE_alphaTestReference }));
> +
> +// load alpha
> +Value* pAlpha = LOAD(ppAlpha);
>
>  Value* pTest = nullptr;
>  if (state.alphaTestFormat == ALPHA_TEST_UNORM8)
> @@ -523,6 +526,7 @@ struct BlendJit : public Builder
>  PointerType::get(Gen_SWR_BLEND_STATE(JM()), 0), // 
> SWR_BLEND_STATE*
>  PointerType::get(mSimdFP32Ty, 0),   // simdvector& 
> src
>  PointerType::get(mSimdFP32Ty, 0),   // simdvector& 
> src1
> +PointerType::get(mSimdFP32Ty, 0),   // src0alpha
>  Type::getInt32Ty(JM()->mContext),   // sampleNum
>  PointerType::get(mSimdFP32Ty, 0),   // uint8_t* pDst
>  PointerType::get(mSimdFP32Ty, 0),   // simdvector& 
> result
> @@ -545,6 +549,8 @@ struct BlendJit : public Builder
>  pSrc->setName("src");
>  Value* pSrc1 = &*argitr++;
>  pSrc1->setName("src1");
> +Value* pSrc0Alpha = &*argitr++;
> +pSrc0Alpha->setName("src0alpha");
>  Value* sampleNum = &*argitr++;
>  sampleNum->setName("sampleNum");
>  Value* pDst = &*argitr++;
> @@ -588,7 +594,7 @@ struct BlendJit : public Builder
>  // alpha test
>  if (state.desc.alphaTestEnable)
>  {
> -AlphaTest(state, pBlendState, src[3], ppMask);
> +AlphaTest(state, pBlendState, pSrc0Alpha, ppMask);
>  }
>
>  // color blend
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH v2] clover: add GetKernelArgInfo (CL 1.2)

[Francisco Jerez]

Serge Martin  writes:

> On Sunday 30 October 2016 16:07:25 Francisco Jerez wrote:
>> Serge Martin  writes:
>> > ---
>> > 
>> >  src/gallium/state_trackers/clover/api/kernel.cpp   | 47
>> >  --
>> >  src/gallium/state_trackers/clover/core/kernel.cpp  |  6 +++
>> >  src/gallium/state_trackers/clover/core/kernel.hpp  |  1 +
>> >  src/gallium/state_trackers/clover/core/module.hpp  | 19 +--
>> >  .../state_trackers/clover/llvm/codegen/common.cpp  | 58
>> >  +- .../state_trackers/clover/llvm/metadata.hpp  
>> >   | 16 ++
>> >  .../state_trackers/clover/tgsi/compiler.cpp|  2 +-
>> >  7 files changed, 141 insertions(+), 8 deletions(-)
>> > 
>> > diff --git a/src/gallium/state_trackers/clover/api/kernel.cpp
>> > b/src/gallium/state_trackers/clover/api/kernel.cpp index 73ba34a..13cfc08
>> > 100644
>> > --- a/src/gallium/state_trackers/clover/api/kernel.cpp
>> > +++ b/src/gallium/state_trackers/clover/api/kernel.cpp
>> > @@ -192,9 +192,50 @@ clGetKernelWorkGroupInfo(cl_kernel d_kern,
>> > cl_device_id d_dev,> 
>> >  CLOVER_API cl_int
>> >  clGetKernelArgInfo(cl_kernel d_kern,
>> >  
>> > cl_uint idx, cl_kernel_arg_info param,
>> > 
>> > -   size_t size, void *r_buf, size_t *r_size) {
>> > -   CLOVER_NOT_SUPPORTED_UNTIL("1.2");
>> > -   return CL_KERNEL_ARG_INFO_NOT_AVAILABLE;
>> > +   size_t size, void *r_buf, size_t *r_size) try {
>> > +   property_buffer buf { r_buf, size, r_size };
>> > +   const auto  = obj(d_kern);
>> > +   const auto args_info = kern.args_info();
>> > +
>> > +   if (args_info.size() == 0)
>> > +  throw error(CL_KERNEL_ARG_INFO_NOT_AVAILABLE);
>> > +
>> > +   if (idx >= args_info.size())
>> > +  throw error(CL_INVALID_ARG_INDEX);
>> > +
>> 
>> I suggest you just handle std::out_of_range like clSetKernelArg does.
>> 
>> > +   const auto  = args_info[idx];
>> > +
>> > +   switch (param) {
>> > +   case CL_KERNEL_ARG_ADDRESS_QUALIFIER:
>> > +  buf.as_scalar() =
>> > + 
>> > info.address_qualifier; +  break;
>> > +
>> > +   case CL_KERNEL_ARG_ACCESS_QUALIFIER:
>> > +  buf.as_scalar() =
>> > + 
>> > info.access_qualifier; +  break;
>> > +
>> > +   case CL_KERNEL_ARG_TYPE_NAME:
>> > +  buf.as_string() = info.type_name;
>> > +  break;
>> > +
>> > +   case CL_KERNEL_ARG_TYPE_QUALIFIER:
>> > +  buf.as_scalar() =
>> > info.type_qualifier;
>> > +  break;
>> > +
>> > +   case CL_KERNEL_ARG_NAME:
>> > +  buf.as_string() = info.arg_name;
>> > +  break;
>> > +
>> > +   default:
>> > +  throw error(CL_INVALID_VALUE);
>> > +   }
>> > +
>> > +   return CL_SUCCESS;
>> > +
>> > +} catch (error ) {
>> > +   return e.get();
>> > 
>> >  }
>> >  
>> >  namespace {
>> > 
>> > diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
>> > b/src/gallium/state_trackers/clover/core/kernel.cpp index
>> > 962f555..18dcd5c 100644
>> > --- a/src/gallium/state_trackers/clover/core/kernel.cpp
>> > +++ b/src/gallium/state_trackers/clover/core/kernel.cpp
>> > @@ -140,6 +140,12 @@ kernel::args() const {
>> > 
>> > return map(derefs(), _args);
>> >  
>> >  }
>> > 
>> > +std::vector
>> > +kernel::args_info() const {
>> > +   const auto  = program().symbols();
>> > +   return find(name_equals(_name), syms).args_info;
>> > +}
>> > +
>> 
>> This method saves literally one line of code in clGetKernelArgInfo.
>> Maybe just open-code it?
>> 
>> >  const module &
>> >  kernel::module(const command_queue ) const {
>> >  
>> > return program().build(q.device()).binary;
>> > 
>> > diff --git a/src/gallium/state_trackers/clover/core/kernel.hpp
>> > b/src/gallium/state_trackers/clover/core/kernel.hpp index
>> > 4ba6ff4..aae51bc 100644
>> > --- a/src/gallium/state_trackers/clover/core/kernel.hpp
>> > +++ b/src/gallium/state_trackers/clover/core/kernel.hpp
>> > @@ -134,6 +134,7 @@ namespace clover {
>> > 
>> >argument_range args();
>> >const_argument_range args() const;
>> > 
>> > +  std::vector args_info() const;
>> > 
>> >const intrusive_ref program;
>> > 
>> > diff --git a/src/gallium/state_trackers/clover/core/module.hpp
>> > b/src/gallium/state_trackers/clover/core/module.hpp index
>> > 5db0548..5ce9492 100644
>> > --- a/src/gallium/state_trackers/clover/core/module.hpp
>> > +++ b/src/gallium/state_trackers/clover/core/module.hpp
>> > @@ -102,16 +102,29 @@ namespace clover {
>> > 
>> >   semantic semantic;
>> >
>> >};
>> > 
>> > +  struct argument_info {
>> > + argument_info() { }
>> > +
>> 
>> If you define a constructor explicitly you should also explicitly
>> initialize all POD members, otherwise their default value will be
>> undefined...
>> 
>> > + uint32_t address_qualifier;
>> 
>> As Vedran pointed out, the computation of this value seems
>> 

Re: [Mesa-dev] [PATCH v2] nvc0/ir: use levelZero flag when the lod is set to 0

[Samuel Pitoiset]

On 11/14/2016 06:53 PM, Ilia Mirkin wrote:

On Mon, Nov 14, 2016 at 12:39 PM, Samuel Pitoiset
 wrote:



On 11/10/2016 03:42 AM, Ilia Mirkin wrote:


Signed-off-by: Ilia Mirkin 
---

v1 -> v2:
  Move to handling this at SSA time. This is a lot more fragile since the
  texture arguments have been reordered already, but it's still easy
enough
  to find the LOD argument.

 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 49
+++---
 .../nouveau/codegen/nv50_ir_lowering_nvc0.h|  1 +
 2 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 68f2b15..68bae08 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -115,6 +115,39 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
i->ftz = true;
 }

+void
+NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
+{
+   if (i->tex.target.isMS())
+  return;
+
+   ImmediateValue lod;
+
+   // The LOD argument comes right after the coordinates (before depth
bias,
+   // offsets, etc).
+   int arg = i->tex.target.getArgCount();
+
+   // SM30+ stores the indirect handle as a separate arg, which comes
before
+   // the LOD.
+   if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET &&
+   i->tex.rIndirectSrc >= 0)
+  arg++;
+   // SM20 stores indirect handle combined with array coordinate
+   if (prog->getTarget()->getChipset() < NVISA_GK104_CHIPSET &&
+   !i->tex.target.isArray() &&
+   i->tex.rIndirectSrc >= 0)



This could be on the same line.


I prefer either all on the same line or 1 per line.


Your call.






+  arg++;
+
+   if (!i->src(arg).getImmediate(lod) || !lod.isInteger(0))
+  return;
+
+   if (i->op == OP_TXL)
+  i->op = OP_TEX;
+   i->tex.levelZero = true;
+   i->moveSources(arg + 1, -1);
+}
+
+



Extra empty line.


Will fix.




 bool
 NVC0LegalizeSSA::visit(Function *fn)
 {
@@ -128,21 +161,25 @@ NVC0LegalizeSSA::visit(BasicBlock *bb)
Instruction *next;
for (Instruction *i = bb->getEntry(); i; i = next) {
   next = i->next;
-  if (i->sType == TYPE_F32) {
- if (prog->getType() != Program::TYPE_COMPUTE)
-handleFTZ(i);
- continue;
-  }
+
+  if (i->sType == TYPE_F32 && prog->getType() !=
Program::TYPE_COMPUTE)
+ handleFTZ(i);
+



Why do you need to change this?


I had to remove the continue, and having

if (a) {
 if (b)
   c;
}

seemed silly.


Okay.

No need to send a v3 for that empty line. :-)

Reviewed-by: Samuel Pitoiset 







   switch (i->op) {
   case OP_DIV:
   case OP_MOD:
- handleDIV(i);
+ if (i->sType != TYPE_F32)
+handleDIV(i);
  break;
   case OP_RCP:
   case OP_RSQ:
  if (i->dType == TYPE_F64)
 handleRCPRSQ(i);
  break;
+  case OP_TXL:
+  case OP_TXF:
+ handleTEXLOD(i->asTex());
+ break;
   default:
  break;
   }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 6f4da8c..d91b6aa 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -35,6 +35,7 @@ private:
void handleDIV(Instruction *); // integer division, modulus
void handleRCPRSQ(Instruction *); // double precision float
recip/rsqrt
void handleFTZ(Instruction *);
+   void handleTEXLOD(TexInstruction *);

 protected:
BuildUtil bld;




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Re: [Mesa-dev] [PATCH v2] nvc0/ir: use levelZero flag when the lod is set to 0

[Ilia Mirkin]

On Mon, Nov 14, 2016 at 12:39 PM, Samuel Pitoiset
 wrote:
>
>
> On 11/10/2016 03:42 AM, Ilia Mirkin wrote:
>>
>> Signed-off-by: Ilia Mirkin 
>> ---
>>
>> v1 -> v2:
>>   Move to handling this at SSA time. This is a lot more fragile since the
>>   texture arguments have been reordered already, but it's still easy
>> enough
>>   to find the LOD argument.
>>
>>  .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 49
>> +++---
>>  .../nouveau/codegen/nv50_ir_lowering_nvc0.h|  1 +
>>  2 files changed, 44 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> index 68f2b15..68bae08 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -115,6 +115,39 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
>> i->ftz = true;
>>  }
>>
>> +void
>> +NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
>> +{
>> +   if (i->tex.target.isMS())
>> +  return;
>> +
>> +   ImmediateValue lod;
>> +
>> +   // The LOD argument comes right after the coordinates (before depth
>> bias,
>> +   // offsets, etc).
>> +   int arg = i->tex.target.getArgCount();
>> +
>> +   // SM30+ stores the indirect handle as a separate arg, which comes
>> before
>> +   // the LOD.
>> +   if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET &&
>> +   i->tex.rIndirectSrc >= 0)
>> +  arg++;
>> +   // SM20 stores indirect handle combined with array coordinate
>> +   if (prog->getTarget()->getChipset() < NVISA_GK104_CHIPSET &&
>> +   !i->tex.target.isArray() &&
>> +   i->tex.rIndirectSrc >= 0)
>
>
> This could be on the same line.

I prefer either all on the same line or 1 per line.

>
>> +  arg++;
>> +
>> +   if (!i->src(arg).getImmediate(lod) || !lod.isInteger(0))
>> +  return;
>> +
>> +   if (i->op == OP_TXL)
>> +  i->op = OP_TEX;
>> +   i->tex.levelZero = true;
>> +   i->moveSources(arg + 1, -1);
>> +}
>> +
>> +
>
>
> Extra empty line.

Will fix.

>
>>  bool
>>  NVC0LegalizeSSA::visit(Function *fn)
>>  {
>> @@ -128,21 +161,25 @@ NVC0LegalizeSSA::visit(BasicBlock *bb)
>> Instruction *next;
>> for (Instruction *i = bb->getEntry(); i; i = next) {
>>next = i->next;
>> -  if (i->sType == TYPE_F32) {
>> - if (prog->getType() != Program::TYPE_COMPUTE)
>> -handleFTZ(i);
>> - continue;
>> -  }
>> +
>> +  if (i->sType == TYPE_F32 && prog->getType() !=
>> Program::TYPE_COMPUTE)
>> + handleFTZ(i);
>> +
>
>
> Why do you need to change this?

I had to remove the continue, and having

if (a) {
 if (b)
   c;
}

seemed silly.

>
>
>>switch (i->op) {
>>case OP_DIV:
>>case OP_MOD:
>> - handleDIV(i);
>> + if (i->sType != TYPE_F32)
>> +handleDIV(i);
>>   break;
>>case OP_RCP:
>>case OP_RSQ:
>>   if (i->dType == TYPE_F64)
>>  handleRCPRSQ(i);
>>   break;
>> +  case OP_TXL:
>> +  case OP_TXF:
>> + handleTEXLOD(i->asTex());
>> + break;
>>default:
>>   break;
>>}
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
>> index 6f4da8c..d91b6aa 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
>> @@ -35,6 +35,7 @@ private:
>> void handleDIV(Instruction *); // integer division, modulus
>> void handleRCPRSQ(Instruction *); // double precision float
>> recip/rsqrt
>> void handleFTZ(Instruction *);
>> +   void handleTEXLOD(TexInstruction *);
>>
>>  protected:
>> BuildUtil bld;
>>
>
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Re: [Mesa-dev] [PATCH] anv: fix multi level clears with VK_REMAINING_MIP_LEVELS

[Nanley Chery]

On Mon, Nov 14, 2016 at 05:26:09PM +, Lionel Landwerlin wrote:
> A commit from the CTS suite on the 1.0-dev branch started using
> VK_REMAINING_MIP_LEVELS, we're not dealing with it properly for clears.
> 
> Fixes:
>dEQP-VK.api.image_clearing.clear_color_image.*
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/anv_blorp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

This patch is
Reviewed-by: Nanley Chery 

> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index b78c21d..d59c1a7 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -803,7 +803,7 @@ void anv_CmdClearColorImage(
>unsigned base_layer = pRanges[r].baseArrayLayer;
>unsigned layer_count = pRanges[r].layerCount;
>  
> -  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
> +  for (unsigned i = 0; i < anv_get_levelCount(image, [r]); i++) {
>   const unsigned level = pRanges[r].baseMipLevel + i;
>   const unsigned level_width = anv_minify(image->extent.width, level);
>   const unsigned level_height = anv_minify(image->extent.height, 
> level);
> @@ -863,7 +863,7 @@ void anv_CmdClearDepthStencilImage(
>unsigned base_layer = pRanges[r].baseArrayLayer;
>unsigned layer_count = pRanges[r].layerCount;
>  
> -  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
> +  for (unsigned i = 0; i < anv_get_levelCount(image, [r]); i++) {
>   const unsigned level = pRanges[r].baseMipLevel + i;
>   const unsigned level_width = anv_minify(image->extent.width, level);
>   const unsigned level_height = anv_minify(image->extent.height, 
> level);
> -- 
> 2.10.2
> 
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Re: [Mesa-dev] [PATCH 1/2] mesa: add NV_image_formats extension support

[Francisco Jerez]

Ilia Mirkin  writes:

> On Mon, Nov 14, 2016 at 6:55 AM, Lionel Landwerlin
>  wrote:
>> On 11/11/16 18:39, Ilia Mirkin wrote:
>>> On Fri, Nov 11, 2016 at 10:40 AM, Lionel Landwerlin  
>>> wrote:
 diff --git a/src/mesa/main/extensions_table.h
 b/src/mesa/main/extensions_table.h
 index 2dbd7da..f58f2ad 100644
 --- a/src/mesa/main/extensions_table.h
 +++ b/src/mesa/main/extensions_table.h
 @@ -315,6 +315,7 @@ EXT(NV_depth_clamp  ,
 ARB_depth_clamp
   EXT(NV_draw_buffers , dummy_true
 ,  x ,  x ,  x , ES2, 2011)
   EXT(NV_fbo_color_attachments, dummy_true
 ,  x ,  x ,  x , ES2, 2010)
   EXT(NV_fog_distance , NV_fog_distance
 , GLL,  x ,  x ,  x , 2001)
 +EXT(NV_image_formats, NV_image_formats
 , GLL, GLC,  x ,  31, 2014)
>>>
>>> This is a GLES-only ext. You want "x" in the GLL and GLC spots.
>>>
>>> Also, is this strictly necessary? I'd recommend dropping the new
>>> boolean and just using ARB_shader_image_load_store here. That would
>>> mean this gets auto-enabled for all ES 3.1-supporting drivers. (Since
>>> there's no new functionality on top of what
>>> ARB_shader_image_load_store requires.)
>>
>>
>> Thanks.
>>
>> Though I'm a bit perplex with what you're proposing.
>> ARB_shader_image_load_store is an OpenGL 3.2 extension, how's that supposed
>> to work with applications using GLES?
>
> It's just a bit in gl_extensions. One that indicates support for the
> features required by that extension. NV_image_formats is a subset of
> ARB_shader_image_load_store functionality, so if a backend supports
> the latter, it'll also support the former. [As an aside, I believe we
> only enable ES 3.1 if gl_extensions.ARB_shader_image_load_store is
> set, so you could ultimately make this into dummy_true - either way's
> good with me.]
>

Agreed, the NV_image_formats bit seems redundant at this point because
ARB_shader_image_load_store provides roughly the same functionality.

> Cheers,
>
>   -ilia
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Re: [Mesa-dev] [PATCH v2] nvc0/ir: use levelZero flag when the lod is set to 0

[Samuel Pitoiset]

On 11/10/2016 03:42 AM, Ilia Mirkin wrote:

Signed-off-by: Ilia Mirkin 
---

v1 -> v2:
  Move to handling this at SSA time. This is a lot more fragile since the
  texture arguments have been reordered already, but it's still easy enough
  to find the LOD argument.

 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 49 +++---
 .../nouveau/codegen/nv50_ir_lowering_nvc0.h|  1 +
 2 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 68f2b15..68bae08 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -115,6 +115,39 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
i->ftz = true;
 }

+void
+NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
+{
+   if (i->tex.target.isMS())
+  return;
+
+   ImmediateValue lod;
+
+   // The LOD argument comes right after the coordinates (before depth bias,
+   // offsets, etc).
+   int arg = i->tex.target.getArgCount();
+
+   // SM30+ stores the indirect handle as a separate arg, which comes before
+   // the LOD.
+   if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET &&
+   i->tex.rIndirectSrc >= 0)
+  arg++;
+   // SM20 stores indirect handle combined with array coordinate
+   if (prog->getTarget()->getChipset() < NVISA_GK104_CHIPSET &&
+   !i->tex.target.isArray() &&
+   i->tex.rIndirectSrc >= 0)


This could be on the same line.


+  arg++;
+
+   if (!i->src(arg).getImmediate(lod) || !lod.isInteger(0))
+  return;
+
+   if (i->op == OP_TXL)
+  i->op = OP_TEX;
+   i->tex.levelZero = true;
+   i->moveSources(arg + 1, -1);
+}
+
+


Extra empty line.


 bool
 NVC0LegalizeSSA::visit(Function *fn)
 {
@@ -128,21 +161,25 @@ NVC0LegalizeSSA::visit(BasicBlock *bb)
Instruction *next;
for (Instruction *i = bb->getEntry(); i; i = next) {
   next = i->next;
-  if (i->sType == TYPE_F32) {
- if (prog->getType() != Program::TYPE_COMPUTE)
-handleFTZ(i);
- continue;
-  }
+
+  if (i->sType == TYPE_F32 && prog->getType() != Program::TYPE_COMPUTE)
+ handleFTZ(i);
+


Why do you need to change this?


   switch (i->op) {
   case OP_DIV:
   case OP_MOD:
- handleDIV(i);
+ if (i->sType != TYPE_F32)
+handleDIV(i);
  break;
   case OP_RCP:
   case OP_RSQ:
  if (i->dType == TYPE_F64)
 handleRCPRSQ(i);
  break;
+  case OP_TXL:
+  case OP_TXF:
+ handleTEXLOD(i->asTex());
+ break;
   default:
  break;
   }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 6f4da8c..d91b6aa 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -35,6 +35,7 @@ private:
void handleDIV(Instruction *); // integer division, modulus
void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
void handleFTZ(Instruction *);
+   void handleTEXLOD(TexInstruction *);

 protected:
BuildUtil bld;


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Re: [Mesa-dev] [PATCH] clover: adapt to new error API since LLVM r286752

[Francisco Jerez]

Jan Vesely  writes:

> On Mon, 2016-11-14 at 12:17 +0100, Vedran Miletić wrote:
>> ---
>>  src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp | 10 --
>>  1 file changed, 8 insertions(+), 2 deletions(-)
>> 
>> diff --git a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp 
>> b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
>> index 8e89a49..5dcc4f8 100644
>> --- a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
>> +++ b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
>> @@ -98,8 +98,14 @@ clover::llvm::parse_module_library(const module , 
>> ::llvm::LLVMContext ,
>> std::string _log) {
>> auto mod = ::llvm::parseBitcodeFile(::llvm::MemoryBufferRef(
>>  as_string(m.secs[0].data), " "), 
>> ctx);
>> -   if (!mod)
>> -  fail(r_log, error(CL_INVALID_PROGRAM), mod.getError().message());
>> +
>> +   if (::llvm::Error err = mod.takeError()) {
>> +  std::string msg;
>
> Any particular reason to keep this outside of the function?
>
Yeah, just drop the definition altogether, no reason to capture the
useless temporary into the closure below.

>> +  ::llvm::handleAllErrors(std::move(err), [&](::llvm::ErrorInfoBase 
>> ) {
>> + msg = EIB.message();
>> + fail(r_log, error(CL_INVALID_PROGRAM), msg.c_str());
>
> This could be EIB.message().c_str(), but that's just bikeshedding.
>
> Jan
>
>> +  });
>> +   }
>>  

Isn't this going to break the build with previous LLVM versions?  Sounds
like you need to define a small wrapper function in llvm/compat.hpp.

>> return std::unique_ptr<::llvm::Module>(std::move(*mod));
>>  }
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[Mesa-dev] [Bug 98595] glsl: ralloc assertion "info->canary == CANARY" failed

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98595

--- Comment #12 from Brian Paul  ---
(In reply to Jonathan Gray from comment #11)
> The proposed fix stops the assertion for me.
> 
> With i965 I now hit a different problem that seems to be unrelated, the
> (OpenBSD) kernel logs
> error: [drm:pid19649:i915_context_is_banned] *ERROR* context hanging too
> fast, declaring banned!
> 
> Running Xorg with softpipe is fine though.

If it's an unrelated issue, please create a new bug report and close this one. 
Thanks.

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Re: [Mesa-dev] [PATCH 1/2] anv/format: handle unsupported formats properly

[Jason Ekstrand]

Also, please Cc stable

On Mon, Nov 14, 2016 at 9:29 AM, Jason Ekstrand 
wrote:

> On Mon, Nov 14, 2016 at 5:23 AM, Iago Toral Quiroga 
> wrote:
>
>> According to the spec for vkGetPhysicalDeviceImageFormatProperties:
>>
>> "If format is not a supported image format, or if the combination of
>> format,
>>  type, tiling, usage, and flags is not supported for images, then
>>  vkGetPhysicalDeviceImageFormatProperties returns
>> VK_ERROR_FORMAT_NOT_SUPPORTED."
>>
>> Makes the following Vulkan CTS tests report 'Not Supported' instead of
>> crashing:
>>
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_unorm
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_snorm
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uscaled
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sscaled
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uint
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sint
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_srgb
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_unorm
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_snorm
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uscaled
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sscaled
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uint
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sint
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_srgb
>> dEQP-VK.api.image_clearing.clear_color_image.1d_r4g4_unorm_pack8
>> dEQP-VK.api.image_clearing.clear_color_image.1d_r8_srgb
>> dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8_srgb
>> dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
>> dEQP-VK.api.image_clearing.clear_color_image.1d_b5g5r5a1_unorm_pack16
>> ---
>>  src/intel/vulkan/anv_formats.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/src/intel/vulkan/anv_formats.c
>> b/src/intel/vulkan/anv_formats.c
>> index 7497a38..bca9aeb 100644
>> --- a/src/intel/vulkan/anv_formats.c
>> +++ b/src/intel/vulkan/anv_formats.c
>> @@ -511,6 +511,9 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties(
>>break;
>> }
>>
>> +   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED)
>> +  goto unsupported;
>> +
>>
>
> Can we move this a bit higher up?  This is an early return so it makes
> sense to return as quickly as we can.
>
> Reviewed-by: Jason Ekstrand 
>
>
>> /* Our hardware doesn't support 1D compressed textures.
>>  *From the SKL PRM, RENDER_SURFACE_STATE::SurfaceFormat:
>>  ** This field cannot be a compressed (BC*, DXT*, FXT*, ETC*,
>> EAC*) format
>> --
>> 2.7.4
>>
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>
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Re: [Mesa-dev] [PATCH] anv: fix multi level clears with VK_REMAINING_MIP_LEVELS

[Jason Ekstrand]

Thanks!

Reviewed-by: Jason Ekstrand 
Cc: "13.0" 

On Mon, Nov 14, 2016 at 9:26 AM, Lionel Landwerlin 
wrote:

> A commit from the CTS suite on the 1.0-dev branch started using
> VK_REMAINING_MIP_LEVELS, we're not dealing with it properly for clears.
>
> Fixes:
>dEQP-VK.api.image_clearing.clear_color_image.*
>
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/anv_blorp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index b78c21d..d59c1a7 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -803,7 +803,7 @@ void anv_CmdClearColorImage(
>unsigned base_layer = pRanges[r].baseArrayLayer;
>unsigned layer_count = pRanges[r].layerCount;
>
> -  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
> +  for (unsigned i = 0; i < anv_get_levelCount(image, [r]);
> i++) {
>   const unsigned level = pRanges[r].baseMipLevel + i;
>   const unsigned level_width = anv_minify(image->extent.width,
> level);
>   const unsigned level_height = anv_minify(image->extent.height,
> level);
> @@ -863,7 +863,7 @@ void anv_CmdClearDepthStencilImage(
>unsigned base_layer = pRanges[r].baseArrayLayer;
>unsigned layer_count = pRanges[r].layerCount;
>
> -  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
> +  for (unsigned i = 0; i < anv_get_levelCount(image, [r]);
> i++) {
>   const unsigned level = pRanges[r].baseMipLevel + i;
>   const unsigned level_width = anv_minify(image->extent.width,
> level);
>   const unsigned level_height = anv_minify(image->extent.height,
> level);
> --
> 2.10.2
>
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Re: [Mesa-dev] [PATCH 2/2] anv/format: support VK_FORMAT_R8G8B8_SRGB

[Jason Ekstrand]

I don't see a problem here

Reviewed-by: Jason Ekstrand 

On Mon, Nov 14, 2016 at 6:10 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> Sounds good too.
>
> Reviewed-by: Lionel Landwerlin 
>
> On 14/11/16 13:23, Iago Toral Quiroga wrote:
>
>> Fixes dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
>> ---
>>   src/intel/vulkan/anv_formats.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/intel/vulkan/anv_formats.c
>> b/src/intel/vulkan/anv_formats.c
>> index bca9aeb..2adde8b 100644
>> --- a/src/intel/vulkan/anv_formats.c
>> +++ b/src/intel/vulkan/anv_formats.c
>> @@ -87,7 +87,7 @@ static const struct anv_format anv_formats[] = {
>>  fmt(VK_FORMAT_R8G8B8_SSCALED,  ISL_FORMAT_R8G8B8_SSCALED),
>>  fmt(VK_FORMAT_R8G8B8_UINT, ISL_FORMAT_R8G8B8_UINT),
>>  fmt(VK_FORMAT_R8G8B8_SINT, ISL_FORMAT_R8G8B8_SINT),
>> -   fmt(VK_FORMAT_R8G8B8_SRGB, ISL_FORMAT_UNSUPPORTED), /*
>> B8G8R8A8_UNORM_SRGB */
>> +   fmt(VK_FORMAT_R8G8B8_SRGB, ISL_FORMAT_R8G8B8_UNORM_SRGB),
>>  fmt(VK_FORMAT_R8G8B8A8_UNORM,  ISL_FORMAT_R8G8B8A8_UNORM),
>>  fmt(VK_FORMAT_R8G8B8A8_SNORM,  ISL_FORMAT_R8G8B8A8_SNORM),
>>  fmt(VK_FORMAT_R8G8B8A8_USCALED,ISL_FORMAT_R8G8B8A8_USCALED),
>>
>
>
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Re: [Mesa-dev] [PATCH 1/2] anv/format: handle unsupported formats properly

[Jason Ekstrand]

On Mon, Nov 14, 2016 at 5:23 AM, Iago Toral Quiroga 
wrote:

> According to the spec for vkGetPhysicalDeviceImageFormatProperties:
>
> "If format is not a supported image format, or if the combination of
> format,
>  type, tiling, usage, and flags is not supported for images, then
>  vkGetPhysicalDeviceImageFormatProperties returns
> VK_ERROR_FORMAT_NOT_SUPPORTED."
>
> Makes the following Vulkan CTS tests report 'Not Supported' instead of
> crashing:
>
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_unorm
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_snorm
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uscaled
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sscaled
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_uint
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_sint
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8_srgb
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_unorm
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_snorm
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uscaled
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sscaled
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_uint
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_sint
> dEQP-VK.api.image_clearing.clear_color_image.1d_b8g8r8a8_srgb
> dEQP-VK.api.image_clearing.clear_color_image.1d_r4g4_unorm_pack8
> dEQP-VK.api.image_clearing.clear_color_image.1d_r8_srgb
> dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8_srgb
> dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
> dEQP-VK.api.image_clearing.clear_color_image.1d_b5g5r5a1_unorm_pack16
> ---
>  src/intel/vulkan/anv_formats.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> index 7497a38..bca9aeb 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -511,6 +511,9 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties(
>break;
> }
>
> +   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED)
> +  goto unsupported;
> +
>

Can we move this a bit higher up?  This is an early return so it makes
sense to return as quickly as we can.

Reviewed-by: Jason Ekstrand 


> /* Our hardware doesn't support 1D compressed textures.
>  *From the SKL PRM, RENDER_SURFACE_STATE::SurfaceFormat:
>  ** This field cannot be a compressed (BC*, DXT*, FXT*, ETC*,
> EAC*) format
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 12/20] intel/genxml: Make 3DSTATE_WM more consistent across gens

[Jason Ekstrand]

On Mon, Nov 14, 2016 at 2:46 AM, Timothy Arceri <
timothy.arc...@collabora.com> wrote:

> On Sat, 2016-11-12 at 13:34 -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/blorp/blorp_genX_exec.h |  4 ++--
> >  src/intel/genxml/gen6.xml | 16 +---
> >  src/intel/genxml/gen7.xml | 16 +---
> >  src/intel/genxml/gen75.xml| 16 +---
> >  src/intel/genxml/gen8.xml |  6 +++---
> >  src/intel/genxml/gen9.xml |  6 +++---
> >  src/intel/vulkan/gen7_pipeline.c  |  2 +-
> >  src/intel/vulkan/gen8_pipeline.c  |  8 
> >  8 files changed, 52 insertions(+), 22 deletions(-)
> >
> > diff --git a/src/intel/blorp/blorp_genX_exec.h
> > b/src/intel/blorp/blorp_genX_exec.h
> > index 4a98371..5921190 100644
> > --- a/src/intel/blorp/blorp_genX_exec.h
> > +++ b/src/intel/blorp/blorp_genX_exec.h
> > @@ -608,7 +608,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
> >   wm.ThreadDispatchEnable = true;
> >
> >if (params->src.enabled)
> > - wm.PixelShaderKillPixel = true;
> > + wm.PixelShaderKillsPixel = true;
> >
> >if (params->dst.surf.samples > 1) {
> >   wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
> > @@ -709,7 +709,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
> >
> >if (params->src.enabled) {
> >   wm.SamplerCount = 1; /* Up to 4 samplers */
> > - wm.PixelShaderKillPixel = true; /* TODO: temporarily smash
> > on */
> > + wm.PixelShaderKillsPixel = true; /* TODO: temporarily smash
> > on */
> >}
> >
> >if (params->dst.surf.samples > 1) {
> > diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
> > index 60e403a..2d19305 100644
> > --- a/src/intel/genxml/gen6.xml
> > +++ b/src/intel/genxml/gen6.xml
> > @@ -1464,12 +1464,22 @@
> >  
> >   > type="uint"/>
> >   > end="183" type="bool"/>
> > - > type="bool"/>
> > + > type="bool"/>
> >   > type="bool"/>
> >   > end="180" type="bool"/>
> >   > type="bool"/>
> > - > end="177" type="uint"/>
> > - > end="175" type="uint"/>
> > + > end="177" type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> > + > end="175" type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> >   > type="bool"/>
> >   > type="bool"/>
> >   > end="169" type="bool"/>
> > diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
> > index 7ac421f..9bb8633 100644
> > --- a/src/intel/genxml/gen7.xml
> > +++ b/src/intel/genxml/gen7.xml
> > @@ -1637,7 +1637,12 @@
> >
> >  
> >  
> > - > end="81" type="uint"/>
> > + > end="81" type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> >   > type="bool"/>
> >   > end="73" type="uint"/>
> >   > type="bool"/>
> > @@ -1907,7 +1912,7 @@
> >   > type="bool"/>
> >   > start="59" end="59" type="bool"/>
> >   > end="58" type="bool"/>
> > - > type="bool"/>
> > + > type="bool"/>
> >   > end="56" type="uint">
> >
> >
> > @@ -1929,7 +1934,12 @@
> >   > type="uint"/>
> >   > end="42" type="bool"/>
> >   > end="41" type="uint"/>
> > - > type="uint"/>
> > + > type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> >   > type="bool"/>
> >   > type="bool"/>
> >   > type="uint">
> > diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> > index 1f8d77a..15c9caa 100644
> > --- a/src/intel/genxml/gen75.xml
> > +++ b/src/intel/genxml/gen75.xml
> > @@ -1892,7 +1892,12 @@
> >
> >  
> >  
> > - > end="81" type="uint"/>
> > + > end="81" type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> >   > type="bool"/>
> >   > type="bool"/>
> >   > end="74" type="bool"/>
> > @@ -2180,7 +2185,7 @@
> >   > type="bool"/>
> >   > start="59" end="59" type="bool"/>
> >   > end="58" type="bool"/>
> > - > type="bool"/>
> > + > type="bool"/>
> >   > end="56" type="uint">
> >
> >
> > @@ -2202,7 +2207,12 @@
> >   > type="uint"/>
> >   > end="42" type="bool"/>
> >   > end="41" type="uint"/>
> > - > type="uint"/>
> > + > type="uint">
> > +  
> > +  
> > +  
> > +  
> > +
> >   > end="37" type="bool"/>
> >   > type="bool"/>
> >   > type="bool"/>
> > diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> > index f4dda4e..3178b1d 100644
> > --- a/src/intel/genxml/gen8.xml
> > +++ b/src/intel/genxml/gen8.xml
> > @@ -2310,9 +2310,9 @@
> >   > start="59" end="59" type="bool"/>
> >   > end="58" type="bool"/>
> >   > type="uint">
> > -  
> > -  
> > -  
> > +  
> > +  
> > +  
> >  
> >   > type="uint">
> >
> > diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> > index 58b41f7..3d44cdb 100644
> > --- a/src/intel/genxml/gen9.xml
> > +++ 

[Mesa-dev] [PATCH] anv: fix multi level clears with VK_REMAINING_MIP_LEVELS

[Lionel Landwerlin]

A commit from the CTS suite on the 1.0-dev branch started using
VK_REMAINING_MIP_LEVELS, we're not dealing with it properly for clears.

Fixes:
   dEQP-VK.api.image_clearing.clear_color_image.*

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_blorp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index b78c21d..d59c1a7 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -803,7 +803,7 @@ void anv_CmdClearColorImage(
   unsigned base_layer = pRanges[r].baseArrayLayer;
   unsigned layer_count = pRanges[r].layerCount;
 
-  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
+  for (unsigned i = 0; i < anv_get_levelCount(image, [r]); i++) {
  const unsigned level = pRanges[r].baseMipLevel + i;
  const unsigned level_width = anv_minify(image->extent.width, level);
  const unsigned level_height = anv_minify(image->extent.height, level);
@@ -863,7 +863,7 @@ void anv_CmdClearDepthStencilImage(
   unsigned base_layer = pRanges[r].baseArrayLayer;
   unsigned layer_count = pRanges[r].layerCount;
 
-  for (unsigned i = 0; i < pRanges[r].levelCount; i++) {
+  for (unsigned i = 0; i < anv_get_levelCount(image, [r]); i++) {
  const unsigned level = pRanges[r].baseMipLevel + i;
  const unsigned level_width = anv_minify(image->extent.width, level);
  const unsigned level_height = anv_minify(image->extent.height, level);
-- 
2.10.2

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Re: [Mesa-dev] [PATCH] util: Fix Clang trivial destructor check.

[Francisco Jerez]

Vinson Lee  writes:

> Check for Clang before GCC.
>
> Clang defines __GNUC__ == 4 and __GNUC_MINOR__ == 2 and matches the GCC
> check but not the GCC version for trivial destructor.
>
> Fixes: 98ab905af0e0 ("mesa: Define introspection macro to determine
> whether a type is trivially destructible.")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98526
> Signed-off-by: Vinson Lee 

Reviewed-by: Francisco Jerez 

> ---
>  src/util/macros.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/util/macros.h b/src/util/macros.h
> index 0563fa59b595..733bf42c 100644
> --- a/src/util/macros.h
> +++ b/src/util/macros.h
> @@ -167,12 +167,12 @@ do {   \
>   * performs no action and all member variables and base classes are
>   * trivially destructible themselves.
>   */
> -#   if defined(__GNUC__)
> -#  if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)))
> +#   if (defined(__clang__) && defined(__has_feature))
> +#  if __has_feature(has_trivial_destructor)
>  # define HAS_TRIVIAL_DESTRUCTOR(T) __has_trivial_destructor(T)
>  #  endif
> -#   elif (defined(__clang__) && defined(__has_feature))
> -#  if __has_feature(has_trivial_destructor)
> +#   elif defined(__GNUC__)
> +#  if ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)))
>  # define HAS_TRIVIAL_DESTRUCTOR(T) __has_trivial_destructor(T)
>  #  endif
>  #   elif defined(_MSC_VER) && !defined(__INTEL_COMPILER)
> -- 
> 2.10.2


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Re: [Mesa-dev] [PATCH 11/20] anv/pipeline: Unify 3DSTATE_PS emission

[Jason Ekstrand]

On Mon, Nov 14, 2016 at 2:35 AM, Timothy Arceri <
timothy.arc...@collabora.com> wrote:

> On Sat, 2016-11-12 at 13:34 -0800, Jason Ekstrand wrote:
>
> In this patch we no longer do:
>
>   ps.RenderTargetResolveEnable = false;
>
> It would be nice to be consistent and either initialise everything or
> just drop all the lines setting things to false/0 and let the memset do
> its job.
>

Yeah... This gets interesting.  I don't really like deleting all
zero-initialized things because it makes it harder to read if zero is an
enum value.  If you want to know "what do we set this to?" then you look
and don't see it, you know it's zero and you don't know what that means.
For instance, the floating point mode, you want to see that it's IEEE but,
unless you know that IEEE is the zero default, you don't know which.  Also,
setting more fields explicitly means it's easier to not forget something;
this was a problem on the past.

On the other hand... The case you mentioned here is one where there is a
field (RenderTargetResolveEnable) that we really don't care about because
we don't support fast-clearing through the regular VkPipeline object.  In
most of these cases, a default value of 0 does exactly what we want so we
don't technically need to set it.  We could set it, but the fields change
from one generation to another so doing so would mean lots of #ifing so
that we can override the default value of 0 with different forms of 0 on
different gens.  It's simpler (and easier to read) to just omit the fields.

In the end, I've taken a "set the important/interesting ones" approach
which I'll be the first to admit is incredibly fuzzy.  However, I think
I've been fairly successful at getting pretty good readability.
Unfortunately, for people who aren't me, it doesn't provide a particularly
good rule-of-thumb.  I'm open to suggestions about how to resolve things in
a non-nasty way.


> > ---
> >  src/intel/vulkan/gen7_pipeline.c  | 57 +--
> > -
> >  src/intel/vulkan/gen8_pipeline.c  | 38 +--
> >  src/intel/vulkan/genX_pipeline_util.h | 70
> > +++
> >  3 files changed, 72 insertions(+), 93 deletions(-)
> >
> > diff --git a/src/intel/vulkan/gen7_pipeline.c
> > b/src/intel/vulkan/gen7_pipeline.c
> > index 40e1d81..dbec828 100644
> > --- a/src/intel/vulkan/gen7_pipeline.c
> > +++ b/src/intel/vulkan/gen7_pipeline.c
> > @@ -107,6 +107,7 @@ genX(graphics_pipeline_create)(
> > emit_3dstate_vs(pipeline);
> > emit_3dstate_gs(pipeline);
> > emit_3dstate_sbe(pipeline);
> > +   emit_3dstate_ps(pipeline);
> >
> > if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
> >anv_batch_emit(>batch, GENX(3DSTATE_WM), wm) {
> > @@ -117,16 +118,7 @@ genX(graphics_pipeline_create)(
> >   wm.EarlyDepthStencilControl= EDSC_NORMAL;
> >   wm.PointRasterizationRule  =
> > RASTRULE_UPPER_RIGHT;
> >}
> > -
> > -  /* Even if no fragments are ever dispatched, the hardware
> > hangs if we
> > -   * don't at least set the maximum number of threads.
> > -   */
> > -  anv_batch_emit(>batch, GENX(3DSTATE_PS), ps) {
> > - ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
> > -  }
> > } else {
> > -  const struct anv_shader_bin *fs_bin =
> > - pipeline->shaders[MESA_SHADER_FRAGMENT];
> >const struct brw_wm_prog_data *wm_prog_data =
> > get_wm_prog_data(pipeline);
> >
> >if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
> > @@ -135,53 +127,6 @@ genX(graphics_pipeline_create)(
> >if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
> >   anv_finishme("primitive_id needs sbe swizzling setup");
> >
> > -  anv_batch_emit(>batch, GENX(3DSTATE_PS), ps) {
> > - ps.KernelStartPointer0   = fs_bin->kernel.offset;
> > - ps.KernelStartPointer1   = 0;
> > - ps.KernelStartPointer2   = fs_bin->kernel.offset +
> > -wm_prog_data-
> > >prog_offset_2;
> > -
> > - ps.ScratchSpaceBasePointer = (struct anv_address) {
> > -.bo = anv_scratch_pool_alloc(device, 
> > >scratch_pool,
> > - MESA_SHADER_FRAGMENT,
> > - wm_prog_data-
> > >base.total_scratch),
> > -.offset = 0,
> > - };
> > - ps.PerThreadScratchSpace =
> > scratch_space(_prog_data->base);
> > -
> > - ps.SamplerCount  =
> > get_sampler_count(fs_bin);
> > - ps.BindingTableEntryCount=
> > get_binding_table_entry_count(fs_bin);
> > -
> > - ps.MaximumNumberofThreads= devinfo->max_wm_threads
> > - 1;
> > - ps.PushConstantEnable= wm_prog_data-
> > >base.nr_params > 0;
> > - ps.AttributeEnable   = wm_prog_data-
> > >num_varying_inputs > 0;
> > - 

[Mesa-dev] [PATCH 06/13] glsl: Remove unneeded check for incompatible primitive types in GS

[Andres Gomez]

The validation of the default in layout qualifier already assures that
we won't have 2 ast_gs_input_layout objects with different primitive
type values. In fact, the validation already assures that we won't
have 2 ast_gs_input_layout objects in the AST tree at all.

The check for an error in the shader has been replaced by an assert.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_to_hir.cpp | 13 +++--
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 9b8678c..c2ce389 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -7935,16 +7935,9 @@ ast_gs_input_layout::hir(exec_list *instructions,
 {
YYLTYPE loc = this->get_location();
 
-   /* If any geometry input layout declaration preceded this one, make sure it
-* was consistent with this one.
-*/
-   if (state->gs_input_prim_type_specified &&
-   state->in_qualifier->prim_type != this->prim_type) {
-  _mesa_glsl_error(, state,
-   "geometry shader input layout does not match"
-   " previous declaration");
-  return NULL;
-   }
+   /* Should have been prevented by the parser. */
+   assert(!state->gs_input_prim_type_specified
+  || state->in_qualifier->prim_type == this->prim_type);
 
/* If any shader inputs occurred before this declaration and specified an
 * array size, make sure the size they specified is consistent with the
-- 
2.9.3

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[Mesa-dev] [PATCH 13/13] Revert "glsl: allow layout qualifier overrides with ARB_shading_language_420pack"

[Andres Gomez]

This reverts commit aaa69c79cd584db4d9c6ea7794e93d29f3d54572.

The commit was erroneous because the ast_layout_expression class is
meant to hold a list used for an after check that all the declared
values for a layout-qualifier-name are consistent.

Therefore, the check for the possibility of duplicated values was
previously fixed to happen much sooner, in the GLSL parser and the
merge of layout qualifiers, and the process_qualifier_constant method
only needs to check that the values are consistent.

By now, those layout-qualifier-name represented as a
ast_layout_expression are "max_vertices", "invocations", "vertices",
"local_size_[x|y|z]" and "xfb_stride".

From page 40 (page 46 of the PDF) of the GLSL 1.50 spec:

  " All geometry shader output layout declarations in a program must
declare the same layout and same value for max_vertices."

From page 44 (page 50 of the PDF) of the GLSL 4.00 spec:

  " If an invocation count is declared, all such declarations must
specify the same count."

From page 47 (page 53 of the PDF) of the GLSL 4.00 spec:

  " All tessellation control shader layout declarations in a program
must specify the same output patch vertex count."

From page 60 (page 66 of the PDF) of the GLSL 4.30 spec:

  " Also, if such a layout qualifier is declared more than once in the
same shader, all those declarations must set the same set of local
work-group sizes and set them to the same values; otherwise a
compile-time error results. If multiple compute shaders attached
to a single program object declare local work-group size, the
declarations must be identical; otherwise a link-time error
results."

From page 73 (page 79 of the PDF) of the GLSL 4.40 spec:

  " While xfb_stride can be declared multiple times for the same
buffer, it is a compile-time or link-time error to have different
values specified for the stride for the same buffer."

Fixes GL44-CTS.enhanced_layouts.xfb_duplicated_stride

Reviewed-by: Timothy Arceri 
Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_type.cpp | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index ce81cdf..c980cfc 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -782,12 +782,7 @@ ast_layout_expression::process_qualifier_constant(struct 
_mesa_glsl_parse_state
  return false;
   }
 
-  /* From section 4.4 "Layout Qualifiers" of the GLSL 4.50 spec:
-   * "When the same layout-qualifier-name occurs multiple times,
-   *  in a single declaration, the last occurrence overrides the
-   *  former occurrence(s)."
-   */
-  if (!state->has_420pack() && !first_pass && *value != 
const_int->value.u[0]) {
+  if (!first_pass && *value != const_int->value.u[0]) {
  YYLTYPE loc = const_expression->get_location();
  _mesa_glsl_error(, state, "%s layout qualifier does not "
  "match previous declaration (%d vs %d)",
-- 
2.9.3

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[Mesa-dev] [PATCH 05/13] glsl: simplifies the merge of the default in layout qualifier

[Andres Gomez]

The merge into the default in layout qualifier duplicates a lot of
code that can be reused from the generic merge method.

Now, we use the generic merge method inside the specific merge for the
default in layout qualifier. The generic merge method has been
completed with some bits that were only present in the merge for the
default in layout qualifier and the specific validation bits have been
moved to the validation method for the default in layout qualifier.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_type.cpp | 165 -
 1 file changed, 81 insertions(+), 84 deletions(-)

diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 803d952..064c63b 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -198,16 +198,20 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
if (q.flags.q.prim_type) {
   if (this->flags.q.prim_type && this->prim_type != q.prim_type) {
  _mesa_glsl_error(loc, state,
-  "conflicting primitive type qualifiers used");
+  "conflicting input primitive %s specified",
+  state->stage == MESA_SHADER_GEOMETRY ?
+  "type" : "mode");
  return false;
   }
+  this->flags.q.prim_type = 1;
   this->prim_type = q.prim_type;
}
 
if (q.flags.q.max_vertices) {
-  if (this->max_vertices && !is_single_layout_merge) {
+  if (this->flags.q.max_vertices && !is_single_layout_merge) {
  this->max_vertices->merge_qualifier(q.max_vertices);
   } else {
+ this->flags.q.max_vertices = 1;
  this->max_vertices = q.max_vertices;
   }
}
@@ -222,9 +226,10 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.invocations) {
-  if (this->invocations && !is_single_layout_merge) {
+  if (this->flags.q.invocations && !is_single_layout_merge) {
  this->invocations->merge_qualifier(q.invocations);
   } else {
+ this->flags.q.invocations = 1;
  this->invocations = q.invocations;
   }
}
@@ -284,9 +289,10 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.vertices) {
-  if (this->vertices && !is_single_layout_merge) {
+  if (this->flags.q.vertices && !is_single_layout_merge) {
  this->vertices->merge_qualifier(q.vertices);
   } else {
+ this->flags.q.vertices = 1;
  this->vertices = q.vertices;
   }
}
@@ -296,6 +302,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  _mesa_glsl_error(loc, state, "conflicting vertex spacing used");
  return false;
   }
+  this->flags.q.vertex_spacing = 1;
   this->vertex_spacing = q.vertex_spacing;
}
 
@@ -304,6 +311,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  _mesa_glsl_error(loc, state, "conflicting ordering used");
  return false;
   }
+  this->flags.q.ordering = 1;
   this->ordering = q.ordering;
}
 
@@ -312,9 +320,13 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  _mesa_glsl_error(loc, state, "conflicting point mode used");
  return false;
   }
+  this->flags.q.point_mode = 1;
   this->point_mode = q.point_mode;
}
 
+   if (q.flags.q.early_fragment_tests)
+  this->flags.q.early_fragment_tests = true;
+
if ((q.flags.i & ubo_mat_mask.flags.i) != 0)
   this->flags.i &= ~ubo_mat_mask.flags.i;
if ((q.flags.i & ubo_layout_mask.flags.i) != 0)
@@ -330,6 +342,9 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
   }
}
 
+   if (q.flags.q.local_size_variable)
+  this->flags.q.local_size_variable = true;
+
this->flags.i |= q.flags.i;
 
if (this->flags.q.in &&
@@ -534,6 +549,45 @@ ast_type_qualifier::validate_in_qualifier(YYLTYPE *loc,
   _mesa_glsl_error(loc, state, "invalid input layout qualifiers used");
}
 
+   /* The checks below are also performed when merging but we want to spit an
+* error against the default global input qualifier as soon as we can, with
+* the closest error location in the shader.
+*/
+
+   /* Input layout qualifiers can be specified multiple
+* times in separate declarations, as long as they match.
+*/
+   if (state->in_qualifier->flags.q.prim_type && this->flags.q.prim_type
+   && state->in_qualifier->prim_type != this->prim_type) {
+  r = false;
+  _mesa_glsl_error(loc, state,
+   "conflicting input primitive %s specified",
+   state->stage == MESA_SHADER_GEOMETRY ?
+   "type" : "mode");
+   }
+
+   if (state->in_qualifier->flags.q.vertex_spacing
+   && this->flags.q.vertex_spacing
+   && state->in_qualifier->vertex_spacing != this->vertex_spacing) {
+  r = false;
+  _mesa_glsl_error(loc, state,
+   "conflicting vertex spacing specified");

[Mesa-dev] [PATCH 09/13] glsl: simplified ast_type_qualifier::merge_into_[in|out]_qualifier API

[Andres Gomez]

Since we modified the way in which multiple repetitions of the same
layout-qualifier-name in a single declaration collapse into the
ast_type_qualifier class, we can simplify the
merge_into_[in|out]_qualifier APIs through removing the create_node
parameter.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |  4 ++--
 src/compiler/glsl/ast_type.cpp   | 13 +
 src/compiler/glsl/glsl_parser.yy |  4 ++--
 3 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 7bbb588..e40387b 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -767,7 +767,7 @@ struct ast_type_qualifier {
 */
bool merge_into_out_qualifier(YYLTYPE *loc,
  _mesa_glsl_parse_state *state,
- ast_node* , bool create_node);
+ ast_node* );
 
/**
 * Validate current qualifier against the global in one.
@@ -780,7 +780,7 @@ struct ast_type_qualifier {
 */
bool merge_into_in_qualifier(YYLTYPE *loc,
 _mesa_glsl_parse_state *state,
-ast_node* , bool create_node);
+ast_node* );
 
bool validate_flags(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 9512f89..9d02b5c6 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -465,7 +465,7 @@ ast_type_qualifier::validate_out_qualifier(YYLTYPE *loc,
 bool
 ast_type_qualifier::merge_into_out_qualifier(YYLTYPE *loc,
  _mesa_glsl_parse_state *state,
- ast_node* , bool create_node)
+ ast_node* )
 {
const bool r = state->out_qualifier->merge_qualifier(loc, state, *this, 
false);
 
@@ -475,8 +475,7 @@ ast_type_qualifier::merge_into_out_qualifier(YYLTYPE *loc,
   state->out_qualifier->flags.q.explicit_stream = 0;
   break;
case MESA_SHADER_TESS_CTRL:
-  if (create_node)
- node = new(state->linalloc) ast_tcs_output_layout(*loc);
+  node = new(state->linalloc) ast_tcs_output_layout(*loc);
   break;
default:
   break;
@@ -610,7 +609,7 @@ ast_type_qualifier::validate_in_qualifier(YYLTYPE *loc,
 bool
 ast_type_qualifier::merge_into_in_qualifier(YYLTYPE *loc,
 _mesa_glsl_parse_state *state,
-ast_node* , bool create_node)
+ast_node* )
 {
bool r = true;
void *lin_ctx = state->linalloc;
@@ -619,8 +618,7 @@ ast_type_qualifier::merge_into_in_qualifier(YYLTYPE *loc,
 * more repeated nodes will be created as we will have the flag set.
 */
if (state->stage == MESA_SHADER_GEOMETRY
-   && this->flags.q.prim_type && !state->in_qualifier->flags.q.prim_type
-   && create_node) {
+   && this->flags.q.prim_type && !state->in_qualifier->flags.q.prim_type) {
   node = new(lin_ctx) ast_gs_input_layout(*loc, this->prim_type);
}
 
@@ -636,8 +634,7 @@ ast_type_qualifier::merge_into_in_qualifier(YYLTYPE *loc,
 * into HIR.
 */
if (state->in_qualifier->flags.q.local_size) {
-  if (create_node)
- node = new(lin_ctx) ast_cs_input_layout(*loc, 
state->in_qualifier->local_size);
+  node = new(lin_ctx) ast_cs_input_layout(*loc, 
state->in_qualifier->local_size);
   state->in_qualifier->flags.q.local_size = 0;
   for (int i = 0; i < 3; i++)
  state->in_qualifier->local_size[i] = NULL;
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 1641cc6..2fc00f1 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -2953,14 +2953,14 @@ layout_defaults:
| layout_in_defaults
{
   $$ = NULL;
-  if (!$1.merge_into_in_qualifier(& @1, state, $$, true)) {
+  if (!$1.merge_into_in_qualifier(& @1, state, $$)) {
  YYERROR;
   }
}
| layout_out_defaults
{
   $$ = NULL;
-  if (!$1.merge_into_out_qualifier(& @1, state, $$, true)) {
+  if (!$1.merge_into_out_qualifier(& @1, state, $$)) {
  YYERROR;
   }
}
-- 
2.9.3

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[Mesa-dev] [PATCH 02/13] glsl: merge layouts into the default one as the last step in interface blocks

[Andres Gomez]

Consider this example:

" #version 150 core
  #extension GL_ARB_shading_language_420pack: require
  #extension GL_ARB_explicit_attrib_location: require

  layout(location=0) out vec4 o;
  layout(binding=2) layout(binding=3, std140) uniform U {
  vec4 a;
  } u[2];"

As there is 2 layout-qualifiers for the uniform U and the binding
layout-qualifier-id is duplicated, the rules set by the
ARB_shading_language_420pack spec state that the rightmost should
prevail.

Our ast_type_qualifier merges with others in a way that if the value
for a layout-qualifier-id is set in both, the object being merged
overwrites the value of the object invoking the merge. Hence, the
merge has to happen from the left layout towards the right one and
this was not happening for interface blocks because we were merging
into the default layout qualifier.

Now, the merge is done from left to right and, as a last step, we
merge into the default layout qualifier if needed, so the values of
the explicit layouts prevail over it.

V2: added a default_layout variable instead of a layout_helper and
make the merge directly over the layout one. Suggested by Timothy.

Reviewed-by: Timothy Arceri 
Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |  9 ++---
 src/compiler/glsl/ast_type.cpp   |  9 +
 src/compiler/glsl/glsl_parser.yy | 24 
 src/compiler/glsl/glsl_parser_extras.cpp | 20 +---
 4 files changed, 40 insertions(+), 22 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 55f9a6c..e7c3aff 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -725,9 +725,6 @@ struct ast_type_qualifier {
 */
glsl_base_type image_base_type;
 
-   /** Flag to know if this represents a default value for a qualifier */
-   bool is_default_qualifier;
-
/**
 * Return true if and only if an interpolation qualifier is present.
 */
@@ -748,6 +745,11 @@ struct ast_type_qualifier {
 */
bool has_auxiliary_storage() const;
 
+   /**
+* Return true if and only if a memory qualifier is present.
+*/
+   bool has_memory() const;
+
bool merge_qualifier(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
 const ast_type_qualifier ,
@@ -1139,6 +1141,7 @@ public:
virtual ir_rvalue *hir(exec_list *instructions,
  struct _mesa_glsl_parse_state *state);
 
+   ast_type_qualifier default_layout;
ast_type_qualifier layout;
const char *block_name;
 
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 478e4a8..48afe09 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -107,6 +107,15 @@ ast_type_qualifier::has_auxiliary_storage() const
   || this->flags.q.patch;
 }
 
+bool ast_type_qualifier::has_memory() const
+{
+   return this->flags.q.coherent
+  || this->flags.q._volatile
+  || this->flags.q.restrict_flag
+  || this->flags.q.read_only
+  || this->flags.q.write_only;
+}
+
 /**
  * This function merges both duplicate identifies within a single layout and
  * multiple layout qualifiers on a single variable declaration. The
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 7d709c7..49574c4 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -838,6 +838,14 @@ declaration:
}
| interface_block
{
+  ast_interface_block *block = (ast_interface_block *) $1;
+  if (block->layout.has_layout() || block->layout.has_memory()) {
+ if (!block->default_layout.merge_qualifier(& @1, state, 
block->layout, false)) {
+YYERROR;
+ }
+  }
+  block->layout = block->default_layout;
+
   $$ = $1;
}
;
@@ -2701,17 +2709,16 @@ interface_block:
{
   ast_interface_block *block = (ast_interface_block *) $2;
 
-  if (!state->has_420pack_or_es31() && block->layout.has_layout() &&
-  !block->layout.is_default_qualifier) {
+  if (!state->has_420pack_or_es31() && block->layout.has_layout()) {
  _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
  YYERROR;
   }
 
-  if (!block->layout.merge_qualifier(& @1, state, $1, false)) {
+  if (!$1.merge_qualifier(& @1, state, block->layout, false)) {
  YYERROR;
   }
 
-  block->layout.is_default_qualifier = false;
+  block->layout = $1;
 
   $$ = block;
}
@@ -2719,14 +2726,15 @@ interface_block:
{
   ast_interface_block *block = (ast_interface_block *)$2;
 
-  if (!block->layout.flags.q.buffer) {
+  if (!block->default_layout.flags.q.buffer) {
 _mesa_glsl_error(& @1, state,
  "memory qualifiers can only be used in the "
  "declaration 

[Mesa-dev] [PATCH 12/13] Revert "glsl: geom shader max_vertices layout must match."

[Andres Gomez]

This reverts commit 4c863993780a11cea6f88fa0682796bee5794042.

The commit was erroneous because the ast_layout_expression class was
created to hold a list of values for a layout-qualifier-name which is
allowed to appear in more than one expression in the same
shader/program but not to hold different values.

In other words, the list is used for an after check that all the
declared values for a layout-qualifier-name are consistent.

Therefore, the values stored must match always, not just for
"max_vertices" or any other eventual layout-qualifier-name.

Reviewed-by: Timothy Arceri 
Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |  3 +--
 src/compiler/glsl/ast_type.cpp   | 17 +++--
 src/compiler/glsl/glsl_parser_extras.cpp |  2 +-
 3 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index d8b425c..afe91ea 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -377,8 +377,7 @@ public:
 
bool process_qualifier_constant(struct _mesa_glsl_parse_state *state,
const char *qual_indentifier,
-   unsigned *value, bool can_be_zero,
-   bool must_match = false);
+   unsigned *value, bool can_be_zero);
 
void merge_qualifier(ast_layout_expression *l_expr)
{
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 01ce641..ce81cdf 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -749,8 +749,7 @@ bool
 ast_layout_expression::process_qualifier_constant(struct 
_mesa_glsl_parse_state *state,
   const char *qual_indentifier,
   unsigned *value,
-  bool can_be_zero,
-  bool must_match)
+  bool can_be_zero)
 {
int min_value = 0;
bool first_pass = true;
@@ -788,14 +787,12 @@ ast_layout_expression::process_qualifier_constant(struct 
_mesa_glsl_parse_state
*  in a single declaration, the last occurrence overrides the
*  former occurrence(s)."
*/
-  if (!first_pass) {
- if ((must_match || !state->has_420pack()) && *value != 
const_int->value.u[0]) {
-YYLTYPE loc = const_expression->get_location();
-_mesa_glsl_error(, state, "%s layout qualifier does not "
- "match previous declaration (%d vs %d)",
- qual_indentifier, *value, const_int->value.i[0]);
-return false;
- }
+  if (!state->has_420pack() && !first_pass && *value != 
const_int->value.u[0]) {
+ YYLTYPE loc = const_expression->get_location();
+ _mesa_glsl_error(, state, "%s layout qualifier does not "
+ "match previous declaration (%d vs %d)",
+  qual_indentifier, *value, const_int->value.i[0]);
+ return false;
   } else {
  first_pass = false;
  *value = const_int->value.u[0];
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index f35a4f0..2ef3d52 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1742,7 +1742,7 @@ set_shader_inout_layout(struct gl_shader *shader,
  unsigned qual_max_vertices;
  if (state->out_qualifier->max_vertices->
process_qualifier_constant(state, "max_vertices",
-  _max_vertices, true, true)) {
+  _max_vertices, true)) {
 
 if (qual_max_vertices > state->Const.MaxGeometryOutputVertices) {
YYLTYPE loc = 
state->out_qualifier->max_vertices->get_location();
-- 
2.9.3

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[Mesa-dev] [PATCH 10/13] glsl: simplified error checking for duplicated layout-qualifiers

[Andres Gomez]

The GLSL parser has been simplified to check for the needed
GL_ARB_shading_language_420pack extension just when merging the
qualifiers in the proper cases.

Reviewed-by: Timothy Arceri 
Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_type.cpp   |  6 ++
 src/compiler/glsl/glsl_parser.yy | 24 
 2 files changed, 6 insertions(+), 24 deletions(-)

diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 9d02b5c6..b50e534 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -201,6 +201,12 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
   return false;
}
 
+   if (is_multiple_layouts_merge && !state->has_420pack_or_es31()) {
+  _mesa_glsl_error(loc, state,
+   "duplicate layout(...) qualifiers");
+  return false;
+   }
+
if (q.flags.q.prim_type) {
   if (this->flags.q.prim_type && this->prim_type != q.prim_type) {
  _mesa_glsl_error(loc, state,
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 2fc00f1..f3c0884 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1883,9 +1883,6 @@ type_qualifier:
* precise qualifiers since these are useful in 
ARB_separate_shader_objects.
* There is no clear spec guidance on this either.
*/
-  if (!state->has_420pack_or_es31() && $2.has_layout())
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
-
   $$ = $1;
   $$.merge_qualifier(& @1, state, $2, false, $2.has_layout());
}
@@ -2709,11 +2706,6 @@ interface_block:
{
   ast_interface_block *block = (ast_interface_block *) $2;
 
-  if (!state->has_420pack_or_es31() && block->layout.has_layout()) {
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
- YYERROR;
-  }
-
   if (!$1.merge_qualifier(& @1, state, block->layout, false,
   block->layout.has_layout())) {
  YYERROR;
@@ -2851,10 +2843,6 @@ layout_uniform_defaults:
layout_qualifier layout_uniform_defaults
{
   $$ = $1;
-  if (!state->has_420pack_or_es31()) {
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
- YYERROR;
-  }
   if (!$$.merge_qualifier(& @1, state, $2, false, true)) {
  YYERROR;
   }
@@ -2866,10 +2854,6 @@ layout_buffer_defaults:
layout_qualifier layout_buffer_defaults
{
   $$ = $1;
-  if (!state->has_420pack_or_es31()) {
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
- YYERROR;
-  }
   if (!$$.merge_qualifier(& @1, state, $2, false, true)) {
  YYERROR;
   }
@@ -2881,10 +2865,6 @@ layout_in_defaults:
layout_qualifier layout_in_defaults
{
   $$ = $1;
-  if (!state->has_420pack_or_es31()) {
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
- YYERROR;
-  }
   if (!$$.merge_qualifier(& @1, state, $2, false, true)) {
  YYERROR;
   }
@@ -2904,10 +2884,6 @@ layout_out_defaults:
layout_qualifier layout_out_defaults
{
   $$ = $1;
-  if (!state->has_420pack_or_es31()) {
- _mesa_glsl_error(&@1, state, "duplicate layout(...) qualifiers");
- YYERROR;
-  }
   if (!$$.merge_qualifier(& @1, state, $2, false, true)) {
  YYERROR;
   }
-- 
2.9.3

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[Mesa-dev] [PATCH 04/13] glsl: Split default in layout qualifier merge

[Andres Gomez]

Currently, the default in layout qualifier merge performs specific
validation and merge.

We want to split out the validation from the merge so they can be done
independently.

Additionally, for simplification, the direction of the validation and
merge is changed so the ast_type_qualifier calling the method is the
one validated and merged against the default in qualifier.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |  16 +++--
 src/compiler/glsl/ast_type.cpp   | 127 ++-
 src/compiler/glsl/glsl_parser.yy |  12 ++--
 3 files changed, 93 insertions(+), 62 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 14936f1..62ccb9d 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -768,10 +768,18 @@ struct ast_type_qualifier {
  _mesa_glsl_parse_state *state,
  ast_node* , bool create_node);
 
-   bool merge_in_qualifier(YYLTYPE *loc,
-   _mesa_glsl_parse_state *state,
-   const ast_type_qualifier ,
-   ast_node* , bool create_node);
+   /**
+* Validate current qualifier against the global in one.
+*/
+   bool validate_in_qualifier(YYLTYPE *loc,
+  _mesa_glsl_parse_state *state);
+
+   /**
+* Merge current qualifier into the global in one.
+*/
+   bool merge_into_in_qualifier(YYLTYPE *loc,
+_mesa_glsl_parse_state *state,
+ast_node* , bool create_node);
 
bool validate_flags(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index aaf7838..803d952 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -461,27 +461,25 @@ ast_type_qualifier::merge_into_out_qualifier(YYLTYPE *loc,
return r;
 }
 
-ast_type_qualifier::merge_in_qualifier(YYLTYPE *loc,
-   _mesa_glsl_parse_state *state,
-   const ast_type_qualifier ,
-   ast_node* , bool create_node)
+bool
+ast_type_qualifier::validate_in_qualifier(YYLTYPE *loc,
+  _mesa_glsl_parse_state *state)
 {
-   void *lin_ctx = state->linalloc;
-   bool create_gs_ast = false;
-   bool create_cs_ast = false;
+   bool r = true;
ast_type_qualifier valid_in_mask;
valid_in_mask.flags.i = 0;
 
switch (state->stage) {
case MESA_SHADER_TESS_EVAL:
-  if (q.flags.q.prim_type) {
+  if (this->flags.q.prim_type) {
  /* Make sure this is a valid input primitive type. */
- switch (q.prim_type) {
+ switch (this->prim_type) {
  case GL_TRIANGLES:
  case GL_QUADS:
  case GL_ISOLINES:
 break;
  default:
+r = false;
 _mesa_glsl_error(loc, state,
  "invalid tessellation evaluation "
  "shader input primitive type");
@@ -495,9 +493,9 @@ ast_type_qualifier::merge_in_qualifier(YYLTYPE *loc,
   valid_in_mask.flags.q.point_mode = 1;
   break;
case MESA_SHADER_GEOMETRY:
-  if (q.flags.q.prim_type) {
+  if (this->flags.q.prim_type) {
  /* Make sure this is a valid input primitive type. */
- switch (q.prim_type) {
+ switch (this->prim_type) {
  case GL_POINTS:
  case GL_LINES:
  case GL_LINES_ADJACENCY:
@@ -505,16 +503,13 @@ ast_type_qualifier::merge_in_qualifier(YYLTYPE *loc,
  case GL_TRIANGLES_ADJACENCY:
 break;
  default:
+r = false;
 _mesa_glsl_error(loc, state,
  "invalid geometry shader input primitive type");
 break;
  }
   }
 
-  create_gs_ast |=
- q.flags.q.prim_type &&
- !state->in_qualifier->flags.q.prim_type;
-
   valid_in_mask.flags.q.prim_type = 1;
   valid_in_mask.flags.q.invocations = 1;
   break;
@@ -522,97 +517,121 @@ ast_type_qualifier::merge_in_qualifier(YYLTYPE *loc,
   valid_in_mask.flags.q.early_fragment_tests = 1;
   break;
case MESA_SHADER_COMPUTE:
-  create_cs_ast |=
- q.flags.q.local_size != 0 &&
- state->in_qualifier->flags.q.local_size == 0;
-
   valid_in_mask.flags.q.local_size = 7;
   valid_in_mask.flags.q.local_size_variable = 1;
   break;
default:
+  r = false;
   _mesa_glsl_error(loc, state,
"input layout qualifiers only valid in "
-   "geometry, fragment and compute shaders");
+   "geometry, tessellation, fragment and compute shaders");
   break;
}
 
/* Generate an error when invalid input layout qualifiers are used. */
-   if ((q.flags.i 

[Mesa-dev] [PATCH 11/13] glsl: push layout-qualifier-name values from variable declarations to global

[Andres Gomez]

After the previous modifications in the merging of the
layout-qualifier-name values, we no longer push the final value in a
declaration to the global values.

This regression happens because we don't call for merging on the
right-most layout qualifier of a declaration which is also the
overriding one in case of multiple appearances.

Now, we add a new method to push these values to the global ones and
we call for this just after all the layout-qualifier collapsing has
happened in a declaration.

This simplifies how this was working in two ways; we make a clear
differentiation of when we are pushing this to the global values since
before it was mixed in the merging call and we only run this once all
the processing for layout-qualifiers in a declaration has happened.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |  6 +
 src/compiler/glsl/ast_type.cpp   | 48 ++--
 src/compiler/glsl/glsl_parser.yy | 27 +-
 3 files changed, 58 insertions(+), 23 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index e40387b..d8b425c 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -782,6 +782,12 @@ struct ast_type_qualifier {
 _mesa_glsl_parse_state *state,
 ast_node* );
 
+   /**
+* Push pending layout qualifiers to the global values.
+*/
+   bool push_to_global(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state);
+
bool validate_flags(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
const ast_type_qualifier _flags,
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index b50e534..01ce641 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -276,29 +276,10 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  }
   }
 
-  if (q.flags.q.explicit_xfb_stride)
+  if (q.flags.q.explicit_xfb_stride) {
+ this->flags.q.xfb_stride = 1;
+ this->flags.q.explicit_xfb_stride = 1;
  this->xfb_stride = q.xfb_stride;
-
-  /* Merge all we xfb_stride qualifiers into the global out */
-  if (q.flags.q.explicit_xfb_stride || this->flags.q.xfb_stride) {
-
- /* Set xfb_stride flag to 0 to avoid adding duplicates every time
-  * there is a merge.
-  */
- this->flags.q.xfb_stride = 0;
-
- unsigned buff_idx;
- if (process_qualifier_constant(state, loc, "xfb_buffer",
-this->xfb_buffer, _idx)) {
-if (state->out_qualifier->out_xfb_stride[buff_idx]
-&& !is_single_layout_merge && !is_multiple_layouts_merge) {
-   state->out_qualifier->out_xfb_stride[buff_idx]->merge_qualifier(
-  new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride));
-} else {
-   state->out_qualifier->out_xfb_stride[buff_idx] =
-  new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride);
-}
- }
   }
}
 
@@ -654,6 +635,29 @@ ast_type_qualifier::merge_into_in_qualifier(YYLTYPE *loc,
return r;
 }
 
+bool
+ast_type_qualifier::push_to_global(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state)
+{
+   if (this->flags.q.xfb_stride) {
+  this->flags.q.xfb_stride = 0;
+
+  unsigned buff_idx;
+  if (process_qualifier_constant(state, loc, "xfb_buffer",
+ this->xfb_buffer, _idx)) {
+ if (state->out_qualifier->out_xfb_stride[buff_idx]) {
+state->out_qualifier->out_xfb_stride[buff_idx]->merge_qualifier(
+   new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride));
+ } else {
+state->out_qualifier->out_xfb_stride[buff_idx] =
+   new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride);
+ }
+  }
+   }
+
+   return true;
+}
+
 /**
  * Check if the current type qualifier has any illegal flags.
  *
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index f3c0884..441ed9d 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -845,7 +845,9 @@ declaration:
  }
   }
   block->layout = block->default_layout;
-
+  if (!block->layout.push_to_global(& @1, state)) {
+ YYERROR;
+  }
   $$ = $1;
}
;
@@ -921,6 +923,9 @@ parameter_declaration:
{
   $$ = $2;
   $$->type->qualifier = $1;
+  if (!$$->type->qualifier.push_to_global(& @1, state)) {
+ YYERROR;
+  }
}
| parameter_qualifier parameter_type_specifier
{
@@ -930,6 +935,9 @@ parameter_declaration:
   $$->type = new(ctx) ast_fully_specified_type();
   $$->type->set_location_range(@1, @2);
   $$->type->qualifier = 

[Mesa-dev] [PATCH v4 00/13] deal with multiple appearances of the same layout-qualifier-name in a single declaration

[Andres Gomez]

In the case of layout-qualifier-names that can appear multiple times
in different declarations of the same shader or, even, the same
program, but that have to consistently hold the same value we are
using the ast_layout_expression class which holds a list to store all
the appearances to be able to check for coherence later.

Until now, we were also holding inside the ast_layout_expression
values of the same layout-qualifier-name that could appear inside a
single layout-qualifier or across multiple layout-qualifiers in a
single declaration.

This was a problem since, inside a declaration, only the last
appearance should be taken into account. As we were not doing this,
the compilation or linking was failing due to different values of the
same layout-qualifier-name in a single declaration when such
layout-qualifier-name had as a constraint to hold the same value
across the same shader or program.

Now, we only hold the last appearanace of a repeated
layout-qualifier-name inside a single declaration.

These following 2 example will help to illustrate the problem:

- " #version 150
#extension GL_ARB_shading_language_420pack: enable
#extension GL_ARB_enhanced_layouts: enable

layout(max_vertices=2, max_vertices=3) out;
layout(max_vertices=3) out;"

- " #version 150
#extension GL_ARB_shading_language_420pack: enable
#extension GL_ARB_enhanced_layouts: enable

layout(max_vertices=2) layout(max_vertices=3) out;
layout(max_vertices=3) out;"

Although different values for "max_vertices" should result in a
compilation error. The above code is valid because max_vertices=2 is
ignored.

The main changes in this v4 series are:
  New patch 3/13.
  New patch 4/13.
  New patch 5/13.
  New patch 6/13.
  New patch 7/13.
  Old patch v3 8/8 is now patch 9/13 to be closer in the log history
with the other related changes.

Fixes:
- GL44-CTS.shading_language_420pack.qualifier_override_layout
- GL44-CTS.enhanced_layouts.xfb_duplicated_stride

Andres Gomez (13):
  glsl: ignore all but the rightmost layout-qualifier-name
  glsl: merge layouts into the default one as the last step in interface
blocks
  glsl: Split default out layout qualifier merge
  glsl: Split default in layout qualifier merge
  glsl: simplifies the merge of the default in layout qualifier
  glsl: Remove unneeded check for incompatible primitive types in GS
  glsl: Add comments for the point mode layout-id-qualifier validation
  glsl: ignore all but the rightmost layout qualifier name from the
rightmost layout qualifier
  glsl: simplified ast_type_qualifier::merge_into_[in|out]_qualifier API
  glsl: simplified error checking for duplicated layout-qualifiers
  glsl: push layout-qualifier-name values from variable declarations to
global
  Revert "glsl: geom shader max_vertices layout must match."
  Revert "glsl: allow layout qualifier overrides with
ARB_shading_language_420pack"

 src/compiler/glsl/ast.h  |  53 +++--
 src/compiler/glsl/ast_to_hir.cpp |  13 +-
 src/compiler/glsl/ast_type.cpp   | 360 ++-
 src/compiler/glsl/glsl_parser.yy | 184 
 src/compiler/glsl/glsl_parser_extras.cpp |  22 +-
 5 files changed, 362 insertions(+), 270 deletions(-)

-- 
2.9.3

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[Mesa-dev] [PATCH 07/13] glsl: Add comments for the point mode layout-id-qualifier validation

[Andres Gomez]

The point mode value in an ast_type_qualifier can only be true if the
flag is already set since this layout-id-qualifier can only be or not
be present in a shader.

Hence, it is useless to check for its value if the flag is already
set. However, for coherence and compatibility with future changes we
do check its value.

Added comments explaining this.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_type.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 064c63b..7c59747 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -315,6 +315,9 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
   this->ordering = q.ordering;
}
 
+   /* Point mode can only be true if set but we check anyway in case there are
+* more options in the future.
+*/
if (q.flags.q.point_mode) {
   if (this->flags.q.point_mode && this->point_mode != q.point_mode) {
  _mesa_glsl_error(loc, state, "conflicting point mode used");
@@ -581,6 +584,9 @@ ast_type_qualifier::validate_in_qualifier(YYLTYPE *loc,
"conflicting ordering specified");
}
 
+   /* Point mode can only be true if set but we check anyway in case there are
+* more options in the future.
+*/
if (state->in_qualifier->flags.q.point_mode && this->flags.q.point_mode
&& state->in_qualifier->point_mode != this->point_mode) {
   r  = false;
-- 
2.9.3

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[Mesa-dev] [PATCH 03/13] glsl: Split default out layout qualifier merge

[Andres Gomez]

Currently, the default out layout qualifier merge performs specific
validation and merge.

We want to split out the validation from the merge so they can be done
independently.

Additionally, for simplification, the direction of the validation and
merge is changed so the ast_type_qualifier calling the method is the
one validated and merged against the default out qualifier.

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  | 16 ++--
 src/compiler/glsl/ast_type.cpp   | 79 +---
 src/compiler/glsl/glsl_parser.yy | 13 +--
 3 files changed, 71 insertions(+), 37 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index e7c3aff..14936f1 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -755,10 +755,18 @@ struct ast_type_qualifier {
 const ast_type_qualifier ,
 bool is_single_layout_merge);
 
-   bool merge_out_qualifier(YYLTYPE *loc,
-   _mesa_glsl_parse_state *state,
-   const ast_type_qualifier ,
-   ast_node* , bool create_node);
+   /**
+* Validate current qualifier against the global out one.
+*/
+   bool validate_out_qualifier(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state);
+
+   /**
+* Merge current qualifier into the global out one.
+*/
+   bool merge_into_out_qualifier(YYLTYPE *loc,
+ _mesa_glsl_parse_state *state,
+ ast_node* , bool create_node);
 
bool merge_in_qualifier(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 48afe09..aaf7838 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -368,33 +368,30 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
 }
 
 bool
-ast_type_qualifier::merge_out_qualifier(YYLTYPE *loc,
-_mesa_glsl_parse_state *state,
-const ast_type_qualifier ,
-ast_node* , bool create_node)
+ast_type_qualifier::validate_out_qualifier(YYLTYPE *loc,
+   _mesa_glsl_parse_state *state)
 {
-   const bool r = this->merge_qualifier(loc, state, q, false);
+   bool r = true;
ast_type_qualifier valid_out_mask;
valid_out_mask.flags.i = 0;
 
-   if (state->stage == MESA_SHADER_GEOMETRY) {
-  if (q.flags.q.prim_type) {
+   switch (state->stage) {
+   case MESA_SHADER_GEOMETRY:
+  if (this->flags.q.prim_type) {
  /* Make sure this is a valid output primitive type. */
- switch (q.prim_type) {
+ switch (this->prim_type) {
  case GL_POINTS:
  case GL_LINE_STRIP:
  case GL_TRIANGLE_STRIP:
 break;
  default:
+r = false;
 _mesa_glsl_error(loc, state, "invalid geometry shader output "
  "primitive type");
 break;
  }
   }
 
-  /* Allow future assigments of global out's stream id value */
-  this->flags.q.explicit_stream = 0;
-
   valid_out_mask.flags.q.stream = 1;
   valid_out_mask.flags.q.explicit_stream = 1;
   valid_out_mask.flags.q.explicit_xfb_buffer = 1;
@@ -403,43 +400,67 @@ ast_type_qualifier::merge_out_qualifier(YYLTYPE *loc,
   valid_out_mask.flags.q.xfb_stride = 1;
   valid_out_mask.flags.q.max_vertices = 1;
   valid_out_mask.flags.q.prim_type = 1;
-   } else if (state->stage == MESA_SHADER_TESS_CTRL) {
-  if (create_node) {
- node = new(state->linalloc) ast_tcs_output_layout(*loc);
-  }
+  break;
+   case MESA_SHADER_TESS_CTRL:
   valid_out_mask.flags.q.vertices = 1;
   valid_out_mask.flags.q.explicit_xfb_buffer = 1;
   valid_out_mask.flags.q.xfb_buffer = 1;
   valid_out_mask.flags.q.explicit_xfb_stride = 1;
   valid_out_mask.flags.q.xfb_stride = 1;
-   } else if (state->stage == MESA_SHADER_TESS_EVAL ||
-  state->stage == MESA_SHADER_VERTEX) {
+  break;
+   case MESA_SHADER_TESS_EVAL:
+   case MESA_SHADER_VERTEX:
   valid_out_mask.flags.q.explicit_xfb_buffer = 1;
   valid_out_mask.flags.q.xfb_buffer = 1;
   valid_out_mask.flags.q.explicit_xfb_stride = 1;
   valid_out_mask.flags.q.xfb_stride = 1;
-   } else if (state->stage == MESA_SHADER_FRAGMENT) {
+  break;
+   case MESA_SHADER_FRAGMENT:
   valid_out_mask.flags.q.blend_support = 1;
-   } else {
-  _mesa_glsl_error(loc, state, "out layout qualifiers only valid in "
-   "geometry, tessellation and vertex shaders");
-  return false;
+  break;
+   default:
+  r = false;
+  _mesa_glsl_error(loc, state,
+   "out layout qualifiers only valid in "
+   

[Mesa-dev] [PATCH 08/13] glsl: ignore all but the rightmost layout qualifier name from the rightmost layout qualifier

[Andres Gomez]

From page 46 (page 52 of the PDF) of the GLSL 4.20 spec:

  " More than one layout qualifier may appear in a single
declaration. If the same layout-qualifier-name occurs in multiple
layout qualifiers for the same declaration, the last one overrides
the former ones."

Consider this example:

  " #version 150
#extension GL_ARB_shading_language_420pack: enable

layout(max_vertices=2) layout(max_vertices=3) out;
layout(max_vertices=3) out;"

Although different values for "max_vertices" results in a compilation
error. The above code is valid because max_vertices=2 is ignored.

Hence, when merging qualifiers in an ast_type_qualifier, we now ignore
new appearances of a same layout-qualifier-name if the new
"is_multiple_layouts_merge" parameter is on, since the GLSL parser
works in this case from right to left.

In addition, any special treatment for the buffer, uniform, in or out
layout defaults has been moved in the GLSL parser to the rule
triggered just after any previous processing/merging on the
layout-qualifiers has happened in a single declaration since it was
run too soon previously.

Fixes GL44-CTS.shading_language_420pack.qualifier_override_layout

Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast.h  |   3 +-
 src/compiler/glsl/ast_type.cpp   |  28 ++---
 src/compiler/glsl/glsl_parser.yy | 130 +++
 3 files changed, 84 insertions(+), 77 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 62ccb9d..7bbb588 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -753,7 +753,8 @@ struct ast_type_qualifier {
bool merge_qualifier(YYLTYPE *loc,
_mesa_glsl_parse_state *state,
 const ast_type_qualifier ,
-bool is_single_layout_merge);
+bool is_single_layout_merge,
+bool is_multiple_layouts_merge = false);
 
/**
 * Validate current qualifier against the global out one.
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 7c59747..9512f89 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -117,15 +117,21 @@ bool ast_type_qualifier::has_memory() const
 }
 
 /**
- * This function merges both duplicate identifies within a single layout and
- * multiple layout qualifiers on a single variable declaration. The
- * is_single_layout_merge param is used differentiate between the two.
+ * This function merges duplicate layout identifiers.
+ *
+ * It deals with duplicates within a single layout qualifier, among multiple
+ * layout qualifiers on a single declaration and on several declarations for
+ * the same variable.
+ *
+ * The is_single_layout_merge and is_multiple_layouts_merge parameters are
+ * used to differentiate among them.
  */
 bool
 ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
 _mesa_glsl_parse_state *state,
 const ast_type_qualifier ,
-bool is_single_layout_merge)
+bool is_single_layout_merge,
+bool is_multiple_layouts_merge)
 {
ast_type_qualifier ubo_mat_mask;
ubo_mat_mask.flags.i = 0;
@@ -208,7 +214,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.max_vertices) {
-  if (this->flags.q.max_vertices && !is_single_layout_merge) {
+  if (this->flags.q.max_vertices
+  && !is_single_layout_merge && !is_multiple_layouts_merge) {
  this->max_vertices->merge_qualifier(q.max_vertices);
   } else {
  this->flags.q.max_vertices = 1;
@@ -226,7 +233,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.invocations) {
-  if (this->flags.q.invocations && !is_single_layout_merge) {
+  if (this->flags.q.invocations
+  && !is_single_layout_merge && !is_multiple_layouts_merge) {
  this->invocations->merge_qualifier(q.invocations);
   } else {
  this->flags.q.invocations = 1;
@@ -277,7 +285,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  if (process_qualifier_constant(state, loc, "xfb_buffer",
 this->xfb_buffer, _idx)) {
 if (state->out_qualifier->out_xfb_stride[buff_idx]
-&& !is_single_layout_merge) {
+&& !is_single_layout_merge && !is_multiple_layouts_merge) {
state->out_qualifier->out_xfb_stride[buff_idx]->merge_qualifier(
   new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride));
 } else {
@@ -289,7 +297,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.vertices) {
-  if (this->flags.q.vertices && !is_single_layout_merge) {
+  if (this->flags.q.vertices
+  && 

[Mesa-dev] [PATCH 01/13] glsl: ignore all but the rightmost layout-qualifier-name

[Andres Gomez]

When a layout contains a duplicated layout-qualifier-name in a single
declaration, only the last occurrence should be taken into account.

From page 59 (page 65 of the PDF) of the GLSL 4.40 spec:

  " More than one layout qualifier may appear in a single
declaration. Additionally, the same layout-qualifier-name can
occur multiple times within a layout qualifier or across multiple
layout qualifiers in the same declaration. When the same
layout-qualifier-name occurs multiple times, in a single
declaration, the last occurrence overrides the former
occurrence(s)."

Consider this example:

  " #version 150
#extension GL_ARB_enhanced_layouts: enable

layout(max_vertices=2, max_vertices=3) out;
layout(max_vertices=3) out;"

Although different values for "max_vertices" results in a compilation
error. The above code is valid because max_vertices=2 is ignored.

When merging qualifiers in an ast_type_qualifier, we now simply ignore
new appearances of a same layout-qualifier-name if the
"is_single_layout_merge" parameter is true, this works because the GLSL
parser processes qualifiers from right to left.

Reviewed-by: Timothy Arceri 
Signed-off-by: Andres Gomez 
---
 src/compiler/glsl/ast_type.cpp | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 2856f18..478e4a8 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -196,7 +196,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.max_vertices) {
-  if (this->max_vertices) {
+  if (this->max_vertices && !is_single_layout_merge) {
  this->max_vertices->merge_qualifier(q.max_vertices);
   } else {
  this->max_vertices = q.max_vertices;
@@ -213,7 +213,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.invocations) {
-  if (this->invocations) {
+  if (this->invocations && !is_single_layout_merge) {
  this->invocations->merge_qualifier(q.invocations);
   } else {
  this->invocations = q.invocations;
@@ -262,7 +262,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
  unsigned buff_idx;
  if (process_qualifier_constant(state, loc, "xfb_buffer",
 this->xfb_buffer, _idx)) {
-if (state->out_qualifier->out_xfb_stride[buff_idx]) {
+if (state->out_qualifier->out_xfb_stride[buff_idx]
+&& !is_single_layout_merge) {
state->out_qualifier->out_xfb_stride[buff_idx]->merge_qualifier(
   new(state->linalloc) ast_layout_expression(*loc, 
this->xfb_stride));
 } else {
@@ -274,7 +275,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
}
 
if (q.flags.q.vertices) {
-  if (this->vertices) {
+  if (this->vertices && !is_single_layout_merge) {
  this->vertices->merge_qualifier(q.vertices);
   } else {
  this->vertices = q.vertices;
@@ -312,7 +313,7 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
 
for (int i = 0; i < 3; i++) {
   if (q.flags.q.local_size & (1 << i)) {
- if (this->local_size[i]) {
+ if (this->local_size[i] && !is_single_layout_merge) {
 this->local_size[i]->merge_qualifier(q.local_size[i]);
  } else {
 this->local_size[i] = q.local_size[i];
-- 
2.9.3

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Re: [Mesa-dev] [PATCH 08/20] anv/pipeline: Unify 3DSTATE_GS emission

[Jason Ekstrand]

On Sat, Nov 12, 2016 at 2:54 PM, Timothy Arceri <
timothy.arc...@collabora.com> wrote:

> On Sat, 2016-11-12 at 13:34 -0800, Jason Ekstrand wrote:
>
> I have two questions and two suggestions below.
>
> With the suggestions addressed and assuming the answer to both
> questions is yes, Patch 7-8 are:
>
> Reviewed-by: Timothy Arceri 
>
> > ---
> >  src/intel/vulkan/gen7_pipeline.c  | 48 +--
> >  src/intel/vulkan/gen8_pipeline.c  | 62 +--
> > --
> >  src/intel/vulkan/genX_pipeline_util.h | 73
> > +++
> >  3 files changed, 75 insertions(+), 108 deletions(-)
> >
> > diff --git a/src/intel/vulkan/gen7_pipeline.c
> > b/src/intel/vulkan/gen7_pipeline.c
> > index e604c25..52577f5 100644
> > --- a/src/intel/vulkan/gen7_pipeline.c
> > +++ b/src/intel/vulkan/gen7_pipeline.c
> > @@ -105,53 +105,7 @@ genX(graphics_pipeline_create)(
> >  #endif
> >
> > emit_3dstate_vs(pipeline);
> > -
> > -   const struct brw_gs_prog_data *gs_prog_data =
> > get_gs_prog_data(pipeline);
> > -
> > -   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
> > -  anv_batch_emit(>batch, GENX(3DSTATE_GS), gs);
> > -   } else {
> > -  const struct anv_shader_bin *gs_bin =
> > - pipeline->shaders[MESA_SHADER_GEOMETRY];
> > -
> > -  anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
> > - gs.KernelStartPointer = gs_bin->kernel.offset;
> > -
> > - gs.ScratchSpaceBasePointer = (struct anv_address) {
> > -.bo = anv_scratch_pool_alloc(device, 
> > >scratch_pool,
> > - MESA_SHADER_GEOMETRY,
> > - gs_prog_data-
> > >base.base.total_scratch),
> > -.offset = 0,
> > - };
> > - gs.PerThreadScratchSpace  =
> > scratch_space(_prog_data->base.base);
> > -
> > - gs.OutputVertexSize   = gs_prog_data-
> > >output_vertex_size_hwords * 2 - 1;
> > - gs.OutputTopology = gs_prog_data-
> > >output_topology;
> > - gs.VertexURBEntryReadLength   = gs_prog_data-
> > >base.urb_read_length;
> > - gs.IncludeVertexHandles   = gs_prog_data-
> > >base.include_vue_handles;
> > -
> > - gs.DispatchGRFStartRegisterForURBData =
> > -gs_prog_data->base.base.dispatch_grf_start_reg;
> > -
> > - gs.SamplerCount  = get_sampler_count(gs_bin);
> > - gs.BindingTableEntryCount=
> > get_binding_table_entry_count(gs_bin);
> > -
> > - gs.MaximumNumberofThreads = devinfo->max_gs_threads -
> > 1;
> > - /* This in the next dword on HSW. */
> > - gs.ControlDataFormat  = gs_prog_data-
> > >control_data_format;
> > - gs.ControlDataHeaderSize  = gs_prog_data-
> > >control_data_header_size_hwords;
> > - gs.InstanceControl= MAX2(gs_prog_data-
> > >invocations, 1) - 1;
> > - gs.DispatchMode   = gs_prog_data-
> > >base.dispatch_mode;
> > - gs.StatisticsEnable   = true;
> > - gs.IncludePrimitiveID = gs_prog_data-
> > >include_primitive_id;
> > -# if (GEN_IS_HASWELL)
> > - gs.ReorderMode= REORDER_TRAILING;
>
> Shouldn't we have changed REORDER_TRAILING to TRAILING in
> src/intel/genxml/gen75.xml in the previous patch?
>

Yeah, I'll do that.


> > -# else
> > - gs.ReorderEnable  = true;
> > -# endif
> > - gs.FunctionEnable = true;
> > -  }
> > -   }
> > +   emit_3dstate_gs(pipeline);
> >
> > if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
> >anv_batch_emit(>batch, GENX(3DSTATE_SBE), sbe);
> > diff --git a/src/intel/vulkan/gen8_pipeline.c
> > b/src/intel/vulkan/gen8_pipeline.c
> > index 1320a13..5816bd4 100644
> > --- a/src/intel/vulkan/gen8_pipeline.c
> > +++ b/src/intel/vulkan/gen8_pipeline.c
> > @@ -53,9 +53,6 @@ genX(graphics_pipeline_create)(
> >  {
> > ANV_FROM_HANDLE(anv_device, device, _device);
> > ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
> > -   const struct anv_physical_device *physical_device =
> > -  >instance->physicalDevice;
> > -   const struct gen_device_info *devinfo = _device->info;
> > struct anv_subpass *subpass = >subpasses[pCreateInfo-
> > >subpass];
> > struct anv_pipeline *pipeline;
> > VkResult result;
> > @@ -112,64 +109,7 @@ genX(graphics_pipeline_create)(
> >   wm_prog_data ? wm_prog_data->barycentric_interp_modes : 0;
> > }
> >
> > -   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
> > -  anv_batch_emit(>batch, GENX(3DSTATE_GS), gs);
> > -   } else {
> > -  const struct brw_gs_prog_data *gs_prog_data =
> > get_gs_prog_data(pipeline);
> > -  const struct anv_shader_bin *gs_bin =
> > - pipeline->shaders[MESA_SHADER_GEOMETRY];
> > -
> > -  uint32_t offset = 1;
> > - 

Re: [Mesa-dev] [PATCH] clover: adapt to new error API since LLVM r286752

[Jan Vesely]

On Mon, 2016-11-14 at 12:17 +0100, Vedran Miletić wrote:
> ---
>  src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp 
> b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> index 8e89a49..5dcc4f8 100644
> --- a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> +++ b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> @@ -98,8 +98,14 @@ clover::llvm::parse_module_library(const module , 
> ::llvm::LLVMContext ,
> std::string _log) {
> auto mod = ::llvm::parseBitcodeFile(::llvm::MemoryBufferRef(
>  as_string(m.secs[0].data), " "), 
> ctx);
> -   if (!mod)
> -  fail(r_log, error(CL_INVALID_PROGRAM), mod.getError().message());
> +
> +   if (::llvm::Error err = mod.takeError()) {
> +  std::string msg;

Any particular reason to keep this outside of the function?

> +  ::llvm::handleAllErrors(std::move(err), [&](::llvm::ErrorInfoBase 
> ) {
> + msg = EIB.message();
> + fail(r_log, error(CL_INVALID_PROGRAM), msg.c_str());

This could be EIB.message().c_str(), but that's just bikeshedding.

Jan

> +  });
> +   }
>  
> return std::unique_ptr<::llvm::Module>(std::move(*mod));
>  }


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Re: [Mesa-dev] [PATCH 1/2] anv/descriptor_set: Write the state offset in the surface state free list.

[Iago Toral]

On Thu, 2016-11-10 at 16:53 -0800, Jason Ekstrand wrote:
> When Kristian reworked descriptor set allocation, somehow he forgot
> to
> actually store the offset in the free list.  Somehow, this completely
> missed CTS testing until now... This fixes all 2744 of the new
> 'dEQP-VK.texture.filtering.* tests in the latest CTS.
> 
> Cc: "12.0 13.0" 
> ---
>  src/intel/vulkan/anv_descriptor_set.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/intel/vulkan/anv_descriptor_set.c
> b/src/intel/vulkan/anv_descriptor_set.c
> index 7d5a78d..52f2df6 100644
> --- a/src/intel/vulkan/anv_descriptor_set.c
> +++ b/src/intel/vulkan/anv_descriptor_set.c
> @@ -489,6 +489,7 @@ anv_descriptor_set_destroy(struct anv_device
> *device,
>    struct surface_state_free_list_entry *entry =
>   set->buffer_views[b].surface_state.map;
>    entry->next = pool->surface_state_free_list;
> +  entry->offset = set->buffer_views[b].surface_state;

This will fail to compile, I think you meant:

entry->offset = set->buffer_views[b].surface_state.offset;

With that change, both patches are:
Reviewed-by: Iago Toral Quiroga 

>    pool->surface_state_free_list = entry;
> }
>  
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Re: [Mesa-dev] [PATCH] clover: adapt to new error API since LLVM r286752

[Vedran Miletić]

On 11/14/2016 04:49 PM, Tom Stellard wrote:
> On Mon, Nov 14, 2016 at 01:44:18PM +0100, Dieter Nützel wrote:
>> Tested-by: Dieter Nützel 
>>
>> Thanks Vedran!
>>
> 
> Pushed, thanks!
> 
> -Tom
> 

Thank you!

Vedran

-- 
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vedran.miletic.net
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Re: [Mesa-dev] [PATCH] clover: adapt to new error API since LLVM r286752

[Tom Stellard]

On Mon, Nov 14, 2016 at 01:44:18PM +0100, Dieter Nützel wrote:
> Tested-by: Dieter Nützel 
> 
> Thanks Vedran!
> 

Pushed, thanks!

-Tom

> Dieter
> 
> Am 14.11.2016 12:17, schrieb Vedran Miletić:
> > ---
> >  src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp | 10 
> > --
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git
> > a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> > b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> > index 8e89a49..5dcc4f8 100644
> > --- a/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> > +++ b/src/gallium/state_trackers/clover/llvm/codegen/bitcode.cpp
> > @@ -98,8 +98,14 @@ clover::llvm::parse_module_library(const module ,
> > ::llvm::LLVMContext ,
> > std::string _log) {
> > auto mod = ::llvm::parseBitcodeFile(::llvm::MemoryBufferRef(
> >  as_string(m.secs[0].data), " 
> > "), ctx);
> > -   if (!mod)
> > -  fail(r_log, error(CL_INVALID_PROGRAM), 
> > mod.getError().message());
> > +
> > +   if (::llvm::Error err = mod.takeError()) {
> > +  std::string msg;
> > +  ::llvm::handleAllErrors(std::move(err), 
> > [&](::llvm::ErrorInfoBase ) {
> > + msg = EIB.message();
> > + fail(r_log, error(CL_INVALID_PROGRAM), msg.c_str());
> > +  });
> > +   }
> > 
> > return std::unique_ptr<::llvm::Module>(std::move(*mod));
> >  }
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Re: [Mesa-dev] EGL/android: pbuffer implementation.

[Emil Velikov]

On 14 November 2016 at 11:49, Liu Zhiquan  wrote:
> mesa android path didn't support pbuffer, so add pbuffer support to
> fix most deqp and cts pbuffer test cases fail;
> add support of front buffer and single buffer config.
>
> Test status: android CTS EGL pbuffer test can run without native crash.
> test:[DEQP,EGL]all deqp pbuffer case passed.
>
> V2: remove duplicate codes.
>
For a second I thought you did not address everything. Information
about the bugs fixed is great, but you want to give a brief summary
about the implementation.
A couple of things that come to mind (although feel free to change/add
your favourite)
 - before double-buffered - now no longer the case.
 - pbuffer is implemented similar to surfaceless/x11 where the [dri]
driver expects a front buffer thus we have to "fake it" in the loader.

> Signed-off-by: Liu Zhiquan 
> Signed-off-by: Kalyan Kondapally 
> ---
>  src/egl/drivers/dri2/egl_dri2.h |   3 +-
>  src/egl/drivers/dri2/platform_android.c | 109 
> 
>  2 files changed, 86 insertions(+), 26 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 3add32e..f3d09dc 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -290,7 +290,8 @@ struct dri2_egl_surface
>  #ifdef HAVE_ANDROID_PLATFORM
> struct ANativeWindow *window;
> struct ANativeWindowBuffer *buffer;
> -   __DRIimage *dri_image;
> +   __DRIimage *dri_image_back;
> +   __DRIimage *dri_image_front;
>
> /* EGL-owned buffers */
> __DRIbuffer   *local_buffers[__DRI_BUFFER_COUNT];
> diff --git a/src/egl/drivers/dri2/platform_android.c 
> b/src/egl/drivers/dri2/platform_android.c
> index ec52a02..760a45c 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -43,6 +43,20 @@
>
>  #define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
>
> +static __DRIimage*
> +alloc_image(struct dri2_egl_display *dri2_dpy,
> +  struct dri2_egl_surface *dri2_surf,
> +  uint32_t format)
> +{
> +   return dri2_dpy->image->createImage(
> +dri2_dpy->dri_screen,
> +dri2_surf->base.Width,
> +dri2_surf->base.Height,
> +format,
Well done with propagating the requested format ! Seems that
platform_surfaceless/wayland/other? have a bug here :-\
Can I interest you in fixing those as follow-up patches ? Note this
request is _not_ a requirement/blocker for this work to land.

Nitpick: can you please inline the function into its only caller or if
you prefer to keep it separate (as-is) rewrap to use the full line.


>  static int
> -get_back_bo(struct dri2_egl_surface *dri2_surf)
> +get_back_bo(struct dri2_egl_display *dri2_dpy, struct dri2_egl_surface 
> *dri2_surf)
>  {
> -   struct dri2_egl_display *dri2_dpy =
> -  dri2_egl_display(dri2_surf->base.Resource.Display);


> +  if (dri2_surf->base.Type == EGL_WINDOW_BIT) {
> + get_back_bo(dri2_dpy, dri2_surf);
> +  }
> +
> +  if (!dri2_surf->dri_image_back) {
Nitpick: please keep get_back_bo() as-is (no extra argument, check
return value) and update it as a follow-up.

With the trivial suggestions, the patch is
Reviewed-by: Emil Velikov 

Thanks
Emil
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Re: [Mesa-dev] [PATCH 1/2] mesa: add NV_image_formats extension support

[Ilia Mirkin]

On Mon, Nov 14, 2016 at 6:55 AM, Lionel Landwerlin
 wrote:
> On 11/11/16 18:39, Ilia Mirkin wrote:
>> On Fri, Nov 11, 2016 at 10:40 AM, Lionel Landwerlin  
>> wrote:
>>> diff --git a/src/mesa/main/extensions_table.h
>>> b/src/mesa/main/extensions_table.h
>>> index 2dbd7da..f58f2ad 100644
>>> --- a/src/mesa/main/extensions_table.h
>>> +++ b/src/mesa/main/extensions_table.h
>>> @@ -315,6 +315,7 @@ EXT(NV_depth_clamp  ,
>>> ARB_depth_clamp
>>>   EXT(NV_draw_buffers , dummy_true
>>> ,  x ,  x ,  x , ES2, 2011)
>>>   EXT(NV_fbo_color_attachments, dummy_true
>>> ,  x ,  x ,  x , ES2, 2010)
>>>   EXT(NV_fog_distance , NV_fog_distance
>>> , GLL,  x ,  x ,  x , 2001)
>>> +EXT(NV_image_formats, NV_image_formats
>>> , GLL, GLC,  x ,  31, 2014)
>>
>> This is a GLES-only ext. You want "x" in the GLL and GLC spots.
>>
>> Also, is this strictly necessary? I'd recommend dropping the new
>> boolean and just using ARB_shader_image_load_store here. That would
>> mean this gets auto-enabled for all ES 3.1-supporting drivers. (Since
>> there's no new functionality on top of what
>> ARB_shader_image_load_store requires.)
>
>
> Thanks.
>
> Though I'm a bit perplex with what you're proposing.
> ARB_shader_image_load_store is an OpenGL 3.2 extension, how's that supposed
> to work with applications using GLES?

It's just a bit in gl_extensions. One that indicates support for the
features required by that extension. NV_image_formats is a subset of
ARB_shader_image_load_store functionality, so if a backend supports
the latter, it'll also support the former. [As an aside, I believe we
only enable ES 3.1 if gl_extensions.ARB_shader_image_load_store is
set, so you could ultimately make this into dummy_true - either way's
good with me.]

Cheers,

  -ilia
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Re: [Mesa-dev] [PATCH 2/2] anv/format: support VK_FORMAT_R8G8B8_SRGB

[Lionel Landwerlin]

Sounds good too.

Reviewed-by: Lionel Landwerlin 

On 14/11/16 13:23, Iago Toral Quiroga wrote:

Fixes dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb
---
  src/intel/vulkan/anv_formats.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index bca9aeb..2adde8b 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -87,7 +87,7 @@ static const struct anv_format anv_formats[] = {
 fmt(VK_FORMAT_R8G8B8_SSCALED,  ISL_FORMAT_R8G8B8_SSCALED),
 fmt(VK_FORMAT_R8G8B8_UINT, ISL_FORMAT_R8G8B8_UINT),
 fmt(VK_FORMAT_R8G8B8_SINT, ISL_FORMAT_R8G8B8_SINT),
-   fmt(VK_FORMAT_R8G8B8_SRGB, ISL_FORMAT_UNSUPPORTED), /* 
B8G8R8A8_UNORM_SRGB */
+   fmt(VK_FORMAT_R8G8B8_SRGB, ISL_FORMAT_R8G8B8_UNORM_SRGB),
 fmt(VK_FORMAT_R8G8B8A8_UNORM,  ISL_FORMAT_R8G8B8A8_UNORM),
 fmt(VK_FORMAT_R8G8B8A8_SNORM,  ISL_FORMAT_R8G8B8A8_SNORM),
 fmt(VK_FORMAT_R8G8B8A8_USCALED,ISL_FORMAT_R8G8B8A8_USCALED),



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