Re: [Mesa-dev] [PATCH] st/mesa: rewrite the primitive restart fallback code
- Original Message - Previously we were mapping/unmapping the index buffer each time we found the restart index in the buffer. This is bad when the restart index is frequently used. Now just map the index buffer once, scan it to produce a list of sub-primitives, unmap the buffer, then draw the sub-primitives. Also, clean up the logic of testing for indexed primitives and calling handle_fallback_primitive_restart(). Don't call it for non-indexed primitives. v2: per Jose, only map the relevant part of the index buffer with pipe_buffer_map_range() Looks good Brian. Before committing, could please just add a comment with the possible improvements (i.e., cache the restart indices when index buffer is not modified between calls, and use triangle strips w/ dummy zero-area triangles as suggested in http://msdn.microsoft.com/en-us/library/windows/desktop/bb206274(v=vs.85).aspx ) for future reference. These are actually nice projects for newbies BTW. Jose ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 43068] New: MESA fails to draw gnome-shell properly | Half of letters are not drawn.
https://bugs.freedesktop.org/show_bug.cgi?id=43068 Bug #: 43068 Summary: MESA fails to draw gnome-shell properly | Half of letters are not drawn. Classification: Unclassified Product: Mesa Version: 7.11 Platform: Other OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Mesa core AssignedTo: mesa-dev@lists.freedesktop.org ReportedBy: kneza...@gmail.com ARCHlinux, freshly installed. After rebooting, half letters aren't getting drawn. Going to gnome-tweak-tool, changing (for example,) text scale from 1.0 to X, then back to 1.0 restores all letters. example photo: http://www.shrani.si/f/2t/GZ/27S3avbw/screenshot-at-2011-11-17.png Anyone knows for a bugfix? -versions- MESA 7.11.1-1 XF86-video-intel 2.16.0-1 LSPCI v3.1.8 uname -a Linux myhost 3.1.1-1-ARCH #1 SMP PREEMPT Fri Nov 11 22:05:37 UTC 2011 i686 Intel(R) Pentium(R) M processor 1500MHz GenuineIntel GNU/Linux [yeah i know i should rather attach files, but browser crashes...] -- LSPCI -- [laptop@myhost ~]$ lspci 00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 00:1d.0 USB controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 03) 00:1d.1 USB controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 03) 00:1d.2 USB controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 03) 00:1d.7 USB controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev 83) 00:1f.0 ISA bridge: Intel Corporation 82801DBM (ICH4-M) LPC Interface Bridge (rev 03) 00:1f.1 IDE interface: Intel Corporation 82801DBM (ICH4-M) IDE Controller (rev 03) 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 03) 00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 03) 00:1f.6 Modem: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller (rev 03) 02:03.0 FireWire (IEEE 1394): Agere Systems FW322/323 (rev 61) 02:05.0 Ethernet controller: Broadcom Corporation BCM4401 100Base-T (rev 01) 02:06.0 Network controller: Intel Corporation PRO/Wireless LAN 2100 3B Mini PCI Adapter (rev 04) 02:09.0 CardBus bridge: Texas Instruments PCI1510 PC card Cardbus Controller -- GLXINFO -- [laptop@myhost ~]$ glxinfo name of display: :0 display: :0 screen: 0 direct rendering: Yes server glx vendor string: SGI server glx version string: 1.4 server glx extensions: GLX_ARB_multisample, GLX_EXT_import_context, GLX_EXT_texture_from_pixmap, GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_MESA_copy_sub_buffer, GLX_OML_swap_method, GLX_SGI_make_current_read, GLX_SGI_swap_control, GLX_SGIS_multisample, GLX_SGIX_fbconfig, GLX_SGIX_pbuffer, GLX_SGIX_visual_select_group, GLX_INTEL_swap_event client glx vendor string: Mesa Project and SGI client glx version string: 1.4 client glx extensions: GLX_ARB_get_proc_address, GLX_ARB_multisample, GLX_EXT_import_context, GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_EXT_framebuffer_sRGB, GLX_MESA_copy_sub_buffer, GLX_MESA_multithread_makecurrent, GLX_MESA_swap_control, GLX_OML_swap_method, GLX_OML_sync_control, GLX_SGI_make_current_read, GLX_SGI_swap_control, GLX_SGI_video_sync, GLX_SGIS_multisample, GLX_SGIX_fbconfig, GLX_SGIX_pbuffer, GLX_SGIX_visual_select_group, GLX_EXT_texture_from_pixmap, GLX_INTEL_swap_event GLX version: 1.4 GLX extensions: GLX_ARB_get_proc_address, GLX_ARB_multisample, GLX_EXT_import_context, GLX_EXT_visual_info, GLX_EXT_visual_rating, GLX_MESA_copy_sub_buffer, GLX_MESA_multithread_makecurrent, GLX_MESA_swap_control, GLX_OML_swap_method, GLX_OML_sync_control, GLX_SGI_make_current_read, GLX_SGI_swap_control, GLX_SGI_video_sync, GLX_SGIS_multisample, GLX_SGIX_fbconfig, GLX_SGIX_pbuffer, GLX_SGIX_visual_select_group, GLX_EXT_texture_from_pixmap OpenGL vendor string: Tungsten Graphics, Inc OpenGL renderer string: Mesa DRI Intel(R) 852GM/855GM x86/MMX/SSE2 OpenGL version string: 1.3 Mesa 7.11.1 OpenGL extensions: GL_ARB_multisample, GL_EXT_abgr, GL_EXT_bgra, GL_EXT_blend_color,
Re: [Mesa-dev] [PATCH 2/2] swrast: fix unmatched span-array-ChanType
On 11/18/2011 12:38 AM, Yuanhan Liu wrote:
texture_combine converts the result rgba to CHAN_TYPE from FLOAT. At the
same time, make sure the span-array-ChanType is changed, too.
Signed-off-by: Yuanhan Liuyuanhan@linux.intel.com
---
src/mesa/swrast/s_texcombine.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/swrast/s_texcombine.c b/src/mesa/swrast/s_texcombine.c
index 0686acd..9f9b7fb 100644
--- a/src/mesa/swrast/s_texcombine.c
+++ b/src/mesa/swrast/s_texcombine.c
@@ -545,6 +545,11 @@ texture_combine( struct gl_context *ctx, GLuint unit,
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][BCOMP], rgba[i][BCOMP]);
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][ACOMP], rgba[i][ACOMP]);
}
+ /*
+* span-array-rgba is coverted to CHAN type by force, so it's a
+* need to make sure the span-array-ChanType is converted, too.
+*/
Maybe rewrite that comment as:
/* The span-array-rgba values are of CHAN type so set
* span-array-ChanType field accordingly.
*/
+ span-array-ChanType = CHAN_TYPE;
end:
for (i = 0; i numArgsRGB || i numArgsA; i++) {
otherwise,
Reviewed-by: Brian Paul bri...@vmware.com
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Re: [Mesa-dev] [PATCH 1/2] swrast: simplify the prototype of function texture_combine
On 11/18/2011 12:38 AM, Yuanhan Liu wrote: Parameter n and rgbaChan are both from structure span, thus using span as paramter to simplify the prototype. Function texture_combine is only used by _swrast_texture_span, so I guess it's safe to do so. This patch is mainly for the next patch. Signed-off-by: Yuanhan Liuyuanhan@linux.intel.com Reviewed-by: Brian Paul bri...@vmware.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/2] Patches to try to fix draw-pixel-with-textures in swrast
On 11/18/2011 12:38 AM, Yuanhan Liu wrote: The two patches tries to fix an issue that happened while calling glDrawPixels with texture enabled. Here I attached a piglit testcase for this issue. Can you resend? I can't detach the attachment and when I save the msg to a text file it's all on one line. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] swrast: fix unmatched span-array-ChanType
On 11/18/2011 08:49 AM, Brian Paul wrote:
On 11/18/2011 12:38 AM, Yuanhan Liu wrote:
texture_combine converts the result rgba to CHAN_TYPE from FLOAT. At the
same time, make sure the span-array-ChanType is changed, too.
Signed-off-by: Yuanhan Liuyuanhan@linux.intel.com
---
src/mesa/swrast/s_texcombine.c | 5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/swrast/s_texcombine.c
b/src/mesa/swrast/s_texcombine.c
index 0686acd..9f9b7fb 100644
--- a/src/mesa/swrast/s_texcombine.c
+++ b/src/mesa/swrast/s_texcombine.c
@@ -545,6 +545,11 @@ texture_combine( struct gl_context *ctx, GLuint
unit,
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][BCOMP], rgba[i][BCOMP]);
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][ACOMP], rgba[i][ACOMP]);
}
+ /*
+ * span-array-rgba is coverted to CHAN type by force, so it's a
+ * need to make sure the span-array-ChanType is converted, too.
+ */
Maybe rewrite that comment as:
/* The span-array-rgba values are of CHAN type so set
* span-array-ChanType field accordingly.
*/
I was about to make the same suggestion.
+ span-array-ChanType = CHAN_TYPE;
end:
for (i = 0; i numArgsRGB || i numArgsA; i++) {
otherwise,
Reviewed-by: Brian Paul bri...@vmware.com
Both patches are also
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
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Re: [Mesa-dev] [PATCH 0/2] Patches to try to fix draw-pixel-with-textures in swrast
On Fri, 18 Nov 2011 15:38:46 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
The two patches tries to fix an issue that happened while calling glDrawPixels
with texture enabled.
Here I attached a piglit testcase for this issue.
git send-email does reasonable things if you supply arguments from 2
separate git format-patch series, instead of putting the patch from the
other series inline here.
--
From c199828cddae5bd0f8e96d586b91be6ad423dbce Mon Sep 17 00:00:00 2001
From: Yuanhan Liu yuanhan@linux.intel.com
Date: Fri, 18 Nov 2011 15:37:33 +0800
Subject: [PATCH] Add a draw-pixel-with-texture testcase
Add a draw-pixel-with-texture testcase to check if sampling is happened
while drawing pixels by glDrawPixels.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
tests/all.tests |1 +
tests/general/CMakeLists.gl.txt |1 +
tests/general/draw-pixel-with-texture.c | 80
+++
3 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644 tests/general/draw-pixel-with-texture.c
diff --git a/tests/all.tests b/tests/all.tests
index 48ce2cb..851db11 100644
--- a/tests/all.tests
+++ b/tests/all.tests
@@ -242,6 +242,7 @@ general['draw-elements-user'] =
PlainExecTest(['draw-elements', '-auto', 'user']
add_plain_test(general, 'draw-elements-vs-inputs')
add_plain_test(general, 'draw-instanced')
add_plain_test(general, 'draw-instanced-divisor')
+add_plain_test(general, 'draw-pixel-with-texture')
add_plain_test(general, 'draw-vertices')
general['draw-vertices-user'] = PlainExecTest(['draw-vertices', '-auto',
'user'])
add_plain_test(general, 'draw-vertices-half-float')
diff --git a/tests/general/CMakeLists.gl.txt b/tests/general/CMakeLists.gl.txt
index 2cfc7be..58cbaa1 100644
--- a/tests/general/CMakeLists.gl.txt
+++ b/tests/general/CMakeLists.gl.txt
@@ -42,6 +42,7 @@ ENDIF (UNIX)
add_executable (draw-elements-vs-inputs draw-elements-vs-inputs.c)
add_executable (draw-instanced draw-instanced.c)
add_executable (draw-instanced-divisor draw-instanced-divisor.c)
+add_executable (draw-pixel-with-texture draw-pixel-with-texture.c)
add_executable (draw-sync draw-sync.c)
add_executable (draw-vertices draw-vertices.c)
add_executable (draw-vertices-half-float draw-vertices-half-float.c)
diff --git a/tests/general/draw-pixel-with-texture.c
b/tests/general/draw-pixel-with-texture.c
new file mode 100644
index 000..c39d35e
--- /dev/null
+++ b/tests/general/draw-pixel-with-texture.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Yuanhan Liu yuanhan@linux.intel.com
+ */
+
+#include piglit-util.h
+
+int piglit_width = 100, piglit_height = 100;
+int piglit_window_mode = GLUT_RGB | GLUT_DOUBLE;
+
+
+enum piglit_result
+piglit_display(void)
+{
+ GLboolean pass = GL_TRUE;
+ GLfloat tex_data[2 * 2 * 4] = {
+ 1, 0, 0, 1, 1, 0, 0, 1,
+ 1, 0, 0, 1, 1, 0, 0, 1,
+ };
+ GLfloat pixels[20 * 20 * 4];
+ GLfloat expected[4] = {0.2, 0, 0, 1};
+ int i;
+
+ glTexImage2D(GL_TEXTURE_2D, 0, GL_RGBA, 2, 2, 0, GL_RGBA, GL_FLOAT,
tex_data);
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
+ glTexEnvi(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_MODULATE);
+
+ glTexCoord2f(0.5, 0.5);
+ glEnable(GL_TEXTURE_2D);
+
+ for (i = 0; i 20 * 20 * 4; i += 4) {
+ pixels[i + 0] = 0.2;
+ pixels[i + 1] = 1;
+ pixels[i + 2] = 0;
+ pixels[i + 3] = 1;
+ }
+
+ glClear(GL_COLOR_BUFFER_BIT);
+
+ glDrawPixels(20, 20, GL_RGBA, GL_FLOAT, pixels);
+
+ /* Here just sample a
[Mesa-dev] [PATCH 1/6] glsl: finish up ARB_conservative_depth
---
src/glsl/ast_to_hir.cpp |7 +--
src/glsl/glsl_lexer.ll |1 +
src/glsl/glsl_parser.yy |9 -
src/glsl/ir_clone.cpp |1 +
4 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index ac090c3..51fec19 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2090,6 +2090,7 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
* The following extension do not allow the deprecated keywords:
*
*GL_AMD_conservative_depth
+*GL_ARB_conservative_depth
*GL_ARB_gpu_shader5
*GL_ARB_separate_shader_objects
*GL_ARB_tesselation_shader
@@ -2122,7 +2123,8 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
+ qual-flags.q.depth_less
+ qual-flags.q.depth_unchanged;
if (depth_layout_count 0
-!state-AMD_conservative_depth_enable) {
+!state-AMD_conservative_depth_enable
+!state-ARB_conservative_depth_enable) {
_mesa_glsl_error(loc, state,
extension GL_AMD_conservative_depth must be enabled
to use depth layout qualifiers);
@@ -2237,7 +2239,8 @@ get_variable_being_redeclared(ir_variable *var,
ast_declaration *decl,
earlier-interpolation = var-interpolation;
/* Layout qualifiers for gl_FragDepth. */
- } else if (state-AMD_conservative_depth_enable
+ } else if ((state-AMD_conservative_depth_enable ||
+ state-ARB_conservative_depth_enable)
strcmp(var-name, gl_FragDepth) == 0
earlier-type == var-type
earlier-mode == var-mode) {
diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll
index 49f3bc8..c7cfedd 100644
--- a/src/glsl/glsl_lexer.ll
+++ b/src/glsl/glsl_lexer.ll
@@ -310,6 +310,7 @@ voidreturn VOID_TOK;
layout {
if ((yyextra-language_version = 140)
|| yyextra-AMD_conservative_depth_enable
+ || yyextra-ARB_conservative_depth_enable
|| yyextra-ARB_explicit_attrib_location_enable
|| yyextra-ARB_fragment_coord_conventions_enable) {
return LAYOUT_TOK;
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index 8363904..71ab039 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1124,7 +1124,9 @@ layout_qualifier_id:
}
/* Layout qualifiers for AMD/ARB_conservative_depth. */
- if (!got_one state-AMD_conservative_depth_enable) {
+ if (!got_one
+ (state-AMD_conservative_depth_enable ||
+ state-ARB_conservative_depth_enable)) {
if (strcmp($1, depth_any) == 0) {
got_one = true;
$$.flags.q.depth_any = 1;
@@ -1141,6 +1143,11 @@ layout_qualifier_id:
if (got_one state-AMD_conservative_depth_warn) {
_mesa_glsl_warning( @1, state,
+ GL_AMD_conservative_depth
+ layout qualifier `%s' is used\n, $1);
+ }
+ if (got_one state-ARB_conservative_depth_warn) {
+_mesa_glsl_warning( @1, state,
GL_ARB_conservative_depth
layout qualifier `%s' is used\n, $1);
}
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index e8ac9fb..c63615c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -51,6 +51,7 @@ ir_variable::clone(void *mem_ctx, struct hash_table *ht) const
var-pixel_center_integer = this-pixel_center_integer;
var-explicit_location = this-explicit_location;
var-has_initializer = this-has_initializer;
+ var-depth_layout = this-depth_layout;
var-num_state_slots = this-num_state_slots;
if (this-state_slots) {
--
1.7.5.4
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[Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
---
src/glsl/linker.cpp| 45
src/mesa/main/mtypes.h |3 ++
src/mesa/program/ir_to_mesa.cpp| 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir = prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
+ switch (var-depth_layout) {
+ case ir_depth_layout_none:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
+return;
+ case ir_depth_layout_any:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
+return;
+ case ir_depth_layout_greater:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
+return;
+ case ir_depth_layout_less:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
+return;
+ case ir_depth_layout_unchanged:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
+return;
+ default:
+assert(0);
+return;
+ }
+ }
+ }
+}
+
+/**
* Validate the resources used by a program versus the implementation limits
*/
static bool
@@ -2177,6 +2221,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
update_array_sizes(prog);
link_assign_uniform_locations(prog);
+ store_fragdepth_layout(prog);
if (!check_resources(ctx, prog))
goto done;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 285ec07..b3427da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2218,6 +2218,9 @@ struct gl_shader_program
/** Post-link transform feedback info. */
struct gl_transform_feedback_info LinkedTransformFeedback;
+ /** Post-link gl_FragDepth layout for ARB_conservative_depth. */
+ enum gl_frag_depth_layout FragDepthLayout;
+
/** Geometry shader state - copied into gl_geometry_program at link time */
struct {
GLint VerticesOut;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 5cee837..5a68fc5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -685,29 +685,6 @@ ir_to_mesa_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
*)this-prog;
- switch (ir-depth_layout) {
- case ir_depth_layout_none:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
-break;
- case ir_depth_layout_any:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
-break;
- case ir_depth_layout_greater:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
-break;
- case ir_depth_layout_less:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
-break;
- case ir_depth_layout_unchanged:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
-break;
- default:
-assert(0);
-break;
- }
}
if (ir-mode == ir_var_uniform strncmp(ir-name, gl_, 3) == 0) {
@@ -3222,6 +3199,12 @@ get_mesa_program(struct gl_context *ctx,
do_set_program_inouts(shader-ir, prog, shader-Type == GL_FRAGMENT_SHADER);
count_resources(prog);
+ /* Set the gl_FragDepth layout. */
+ if (target == GL_FRAGMENT_PROGRAM_ARB) {
+ struct gl_fragment_program *fp = (struct gl_fragment_program *)prog;
+ fp-FragDepthLayout = shader_program-FragDepthLayout;
+ }
+
_mesa_reference_program(ctx, shader-Program, prog);
if ((ctx-Shader.Flags GLSL_NO_OPT) == 0) {
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 0bf6766..929c7af 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1017,29 +1017,6 @@ glsl_to_tgsi_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
[Mesa-dev] [PATCH 3/6] gallium: implement ARB_conservative_depth
This adds a new TGSI property to represent the GLSL layout qualifier in TGSI.
---
src/gallium/auxiliary/tgsi/tgsi_dump.c |1 +
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 16
src/gallium/auxiliary/tgsi/tgsi_ureg.h |5 +
src/gallium/include/pipe/p_shader_tokens.h | 10 +-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 19 +++
5 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index 91bc124..e830aa5 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -174,6 +174,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
FS_COORD_ORIGIN,
FS_COORD_PIXEL_CENTER,
FS_COLOR0_WRITES_ALL_CBUFS,
+ FS_DEPTH_LAYOUT
};
static const char *tgsi_type_names[] =
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index cada435..cac8af3 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -161,6 +161,7 @@ struct ureg_program
unsigned char property_fs_coord_origin; /* = TGSI_FS_COORD_ORIGIN_* */
unsigned char property_fs_coord_pixel_center; /* =
TGSI_FS_COORD_PIXEL_CENTER_* */
unsigned char property_fs_color0_writes_all_cbufs; /* =
TGSI_FS_COLOR0_WRITES_ALL_CBUFS * */
+ unsigned char property_fs_depth_layout; /* TGSI_FS_DEPTH_LAYOUT */
unsigned nr_addrs;
unsigned nr_preds;
@@ -304,6 +305,13 @@ ureg_property_fs_color0_writes_all_cbufs(struct
ureg_program *ureg,
ureg-property_fs_color0_writes_all_cbufs = fs_color0_writes_all_cbufs;
}
+void
+ureg_property_fs_depth_layout(struct ureg_program *ureg,
+ unsigned fs_depth_layout)
+{
+ ureg-property_fs_depth_layout = fs_depth_layout;
+}
+
struct ureg_src
ureg_DECL_fs_input_cyl_centroid(struct ureg_program *ureg,
unsigned semantic_name,
@@ -1389,6 +1397,14 @@ static void emit_decls( struct ureg_program *ureg )
ureg-property_fs_color0_writes_all_cbufs);
}
+ if (ureg-property_fs_depth_layout) {
+ assert(ureg-processor == TGSI_PROCESSOR_FRAGMENT);
+
+ emit_property(ureg,
+TGSI_PROPERTY_FS_DEPTH_LAYOUT,
+ureg-property_fs_depth_layout);
+ }
+
if (ureg-processor == TGSI_PROCESSOR_VERTEX) {
for (i = 0; i UREG_MAX_INPUT; i++) {
if (ureg-vs_inputs[i/32] (1 (i%32))) {
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index 8f5f22e..a70d30f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -157,6 +157,11 @@ void
ureg_property_fs_color0_writes_all_cbufs(struct ureg_program *ureg,
unsigned fs_color0_writes_all_cbufs);
+void
+ureg_property_fs_depth_layout(struct ureg_program *ureg,
+ unsigned fs_depth_layout);
+
+
/***
* Build shader declarations:
*/
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index b04e26d..10cfaf6 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -188,7 +188,8 @@ union tgsi_immediate_data
#define TGSI_PROPERTY_FS_COORD_ORIGIN3
#define TGSI_PROPERTY_FS_COORD_PIXEL_CENTER 4
#define TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS 5
-#define TGSI_PROPERTY_COUNT 6
+#define TGSI_PROPERTY_FS_DEPTH_LAYOUT6
+#define TGSI_PROPERTY_COUNT 7
struct tgsi_property {
unsigned Type : 4; /** TGSI_TOKEN_TYPE_PROPERTY */
@@ -203,6 +204,13 @@ struct tgsi_property {
#define TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER 0
#define TGSI_FS_COORD_PIXEL_CENTER_INTEGER 1
+#define TGSI_FS_DEPTH_LAYOUT_NONE 0
+#define TGSI_FS_DEPTH_LAYOUT_ANY 1
+#define TGSI_FS_DEPTH_LAYOUT_GREATER 2
+#define TGSI_FS_DEPTH_LAYOUT_LESS 3
+#define TGSI_FS_DEPTH_LAYOUT_UNCHANGED4
+
+
struct tgsi_property_data {
unsigned Data;
};
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 929c7af..2a6c433 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4559,6 +4559,25 @@ st_translate_program(
interpMode[i]);
}
+ if (program-shader_program-FragDepthLayout != FRAG_DEPTH_LAYOUT_NONE) {
+ switch (program-shader_program-FragDepthLayout) {
+ case FRAG_DEPTH_LAYOUT_ANY:
+ureg_property_fs_depth_layout(ureg, TGSI_FS_DEPTH_LAYOUT_ANY);
+break;
+ case FRAG_DEPTH_LAYOUT_GREATER:
+ureg_property_fs_depth_layout(ureg, TGSI_FS_DEPTH_LAYOUT_GREATER);
+break;
+ case
[Mesa-dev] [PATCH 4/6] gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionally
Only i965g does not enable GLSL, but that driver has been unmaintained and
bitrotting for quite a while anyway.
---
src/gallium/auxiliary/util/u_caps.c|1 -
src/gallium/docs/source/screen.rst |1 -
src/gallium/drivers/cell/ppu/cell_screen.c |2 -
src/gallium/drivers/i915/i915_screen.c |1 -
src/gallium/drivers/i965/brw_screen.c |2 -
src/gallium/drivers/llvmpipe/lp_screen.c |2 -
src/gallium/drivers/nv50/nv50_screen.c |1 -
src/gallium/drivers/nvc0/nvc0_screen.c |1 -
src/gallium/drivers/nvfx/nvfx_screen.c |2 -
src/gallium/drivers/r300/r300_screen.c | 16 --
src/gallium/drivers/r600/r600_pipe.c |1 -
src/gallium/drivers/softpipe/sp_screen.c |2 -
src/gallium/drivers/svga/svga_screen.c |2 -
src/gallium/include/pipe/p_defines.h |1 -
src/mesa/state_tracker/st_extensions.c | 31 +++
15 files changed, 13 insertions(+), 53 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_caps.c
b/src/gallium/auxiliary/util/u_caps.c
index 75677b2..6230707 100644
--- a/src/gallium/auxiliary/util/u_caps.c
+++ b/src/gallium/auxiliary/util/u_caps.c
@@ -182,7 +182,6 @@ static unsigned caps_dx_11[] = {
/* OpenGL 2.1 */
static unsigned caps_opengl_2_1[] = {
- UTIL_CHECK_CAP(GLSL),
UTIL_CHECK_CAP(OCCLUSION_QUERY),
UTIL_CHECK_CAP(TWO_SIDED_STENCIL),
UTIL_CHECK_CAP(BLEND_EQUATION_SEPARATE),
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 0679240..d2f0f9d 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -26,7 +26,6 @@ The integer capabilities:
normalized coordinates, and mipmaps.
* ``PIPE_CAP_TWO_SIDED_STENCIL``: Whether the stencil test can also affect
back-facing
polygons.
-* ``PIPE_CAP_GLSL``: Deprecated.
* ``PIPE_CAP_DUAL_SOURCE_BLEND``: Whether dual-source blend factors are
supported. See
:ref:`Blend` for more information.
* ``PIPE_CAP_ANISOTROPIC_FILTER``: Whether textures can be filtered
anisotropically.
diff --git a/src/gallium/drivers/cell/ppu/cell_screen.c
b/src/gallium/drivers/cell/ppu/cell_screen.c
index 86acbc7..a4677fd 100644
--- a/src/gallium/drivers/cell/ppu/cell_screen.c
+++ b/src/gallium/drivers/cell/ppu/cell_screen.c
@@ -64,8 +64,6 @@ cell_get_param(struct pipe_screen *screen, enum pipe_cap
param)
return 1;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 1;
- case PIPE_CAP_GLSL:
- return 1;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 0;
case PIPE_CAP_POINT_SPRITE:
diff --git a/src/gallium/drivers/i915/i915_screen.c
b/src/gallium/drivers/i915/i915_screen.c
index 75545f4..9e46afa 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -200,7 +200,6 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap
cap)
return 0;
/* Features we can lie about (boolean caps). */
- case PIPE_CAP_GLSL:
case PIPE_CAP_OCCLUSION_QUERY:
return is-debug.lie ? 1 : 0;
diff --git a/src/gallium/drivers/i965/brw_screen.c
b/src/gallium/drivers/i965/brw_screen.c
index deafd4b..f4abd0f 100644
--- a/src/gallium/drivers/i965/brw_screen.c
+++ b/src/gallium/drivers/i965/brw_screen.c
@@ -160,8 +160,6 @@ brw_get_param(struct pipe_screen *screen, enum pipe_cap
param)
return 1;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 1;
- case PIPE_CAP_GLSL:
- return 0;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 0;
case PIPE_CAP_POINT_SPRITE:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c
b/src/gallium/drivers/llvmpipe/lp_screen.c
index fac13e7..9d77cf8 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -110,8 +110,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum
pipe_cap param)
return 1;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 1;
- case PIPE_CAP_GLSL:
- return 1;
case PIPE_CAP_SM3:
return 1;
case PIPE_CAP_ANISOTROPIC_FILTER:
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 1270c83..278b3ee 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -107,7 +107,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_POINT_SPRITE:
return 1;
- case PIPE_CAP_GLSL:
case PIPE_CAP_SM3:
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index 0da7be4..8b109a9 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -96,7 +96,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_POINT_SPRITE:
return 1;
- case PIPE_CAP_GLSL:
[Mesa-dev] [PATCH 5/6] gallium: expose GLSL 1.3 if PIPE_CAP_SM4 is exposed (new cap)
---
src/gallium/include/pipe/p_defines.h |3 ++-
src/mesa/state_tracker/st_extensions.c |5 +
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 3e55d22..e51132a 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -475,7 +475,8 @@ enum pipe_cap {
PIPE_CAP_MIN_TEXEL_OFFSET = 50,
PIPE_CAP_MAX_TEXEL_OFFSET = 51,
PIPE_CAP_CONDITIONAL_RENDER = 52,
- PIPE_CAP_TEXTURE_BARRIER = 53
+ PIPE_CAP_TEXTURE_BARRIER = 53,
+ PIPE_CAP_SM4 = 54 /* Shader Model 4.0 (roughly equivalent to GLSL 1.3) */
};
/* Shader caps not specific to any single stage */
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 544f0b6..96a1059 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -245,6 +245,11 @@ void st_init_extensions(struct st_context *st)
int i;
ctx-Const.GLSLVersion = 120;
+
+ if (screen-get_param(screen, PIPE_CAP_SM4)) {
+ ctx-Const.GLSLVersion = 130;
+ }
+
_mesa_override_glsl_version(st-ctx);
/*
--
1.7.5.4
___
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[Mesa-dev] [PATCH 6/6] st/mesa: enable ARB(AMD)_convervative_depth if GLSL 1.3 is supported
The spec says GL3 is required, but technically the extension only needs
the 'out' modifier from GLSL 1.3.
---
src/mesa/state_tracker/st_extensions.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 96a1059..ad09c1d 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -248,6 +248,9 @@ void st_init_extensions(struct st_context *st)
if (screen-get_param(screen, PIPE_CAP_SM4)) {
ctx-Const.GLSLVersion = 130;
+
+ /* Extensions that only require GLSL 1.3. */
+ ctx-Extensions.AMD_conservative_depth = GL_TRUE;
}
_mesa_override_glsl_version(st-ctx);
--
1.7.5.4
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[Mesa-dev] ir_swizzle @ 0xe134ae0 specifies a channel not present in the value
Hi there, while trying to play the game Ryzom with latest mesa compiled from git the program terminates with error ir_swizzle @ 0xe134ae0 specifies a channel not present in the value. Switching back to the stable branch mesa-7.11 (haven´t tried mesa-7.11.1) the error is gone. My glxinfo: OpenGL renderer string: Gallium 0.4 on AMD BARTS OpenGL version string: 2.1 Mesa 7.12-devel (git-7e84a64) OpenGL shading language version string: 1.20 Here is the backtrace: Core was generated by `/usr/games/ryzom_client'. Program terminated with signal 6, Aborted. #0 0x7f1c03120405 in *__GI_raise (sig=optimized out) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64 64 ../nptl/sysdeps/unix/sysv/linux/raise.c: Datei oder Verzeichnis nicht gefunden. in ../nptl/sysdeps/unix/sysv/linux/raise.c (gdb) bt #0 0x7f1c03120405 in *__GI_raise (sig=optimized out) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64 #1 0x7f1c03123680 in *__GI_abort () at abort.c:92 #2 0x7f1bfb0423ad in visit_leave (ir=0xdbaf870, this=optimized out) at ir_validate.cpp:465 #3 ir_validate::visit_leave (this=optimized out, ir=0xdbaf870) at ir_validate.cpp:456 #4 0x7f1bfb03c0f0 in ir_expression::accept (this=0xdbaf8e0, v=0x7fff048099a0) at ir_hv_accept.cpp:155 #5 0x7f1bfb03c0f0 in ir_expression::accept (this=0xdbafbd0, v=0x7fff048099a0) at ir_hv_accept.cpp:155 #6 0x7f1bfb03c0f0 in ir_expression::accept (this=0xdbafcf0, v=0x7fff048099a0) at ir_hv_accept.cpp:155 #7 0x7f1bfb03c2e6 in ir_swizzle::accept (this=0xdbafd80, v=0x7fff048099a0) at ir_hv_accept.cpp:244 #8 0x7f1bfb03c2e6 in ir_swizzle::accept (this=0xdbafdf0, v=0x7fff048099a0) at ir_hv_accept.cpp:244 #9 0x7f1bfb03c0f0 in ir_expression::accept (this=0xdbaff20, v=0x7fff048099a0) at ir_hv_accept.cpp:155 #10 0x7f1bfb03c0f0 in ir_expression::accept (this=0xdbb0070, v=0x7fff048099a0) at ir_hv_accept.cpp:155 #11 0x7f1bfb03c4ed in ir_assignment::accept (this=0xdbb0170, v=0x7fff048099a0) at ir_hv_accept.cpp:304 #12 0x7f1bfb03bf88 in visit_list_elements (statement_list=true, l=0xdbbc1c0, v=0x7fff048099a0) at ir_hv_accept.cpp:56 #13 ir_function_signature::accept (this=0xdbbc170, v=0x7fff048099a0) at ir_hv_accept.cpp:129 #14 0x7f1bfb03c044 in visit_list_elements (statement_list=false, l=0xdbbbff0, v=0x7fff048099a0) at ir_hv_accept.cpp:56 #15 ir_function::accept (this=0xdbbbfc0, v=0x7fff048099a0) at ir_hv_accept.cpp:141 #16 0x7f1bfb03bd58 in visit_list_elements (v=0x7fff048099a0, l=optimized out, statement_list=optimized out) at ir_hv_accept.cpp:56 #17 0x7f1bfb042942 in validate_ir_tree (instructions=0xdbbf090) at ir_validate.cpp:621 #18 0x7f1bfafe6533 in create_new_program (key=0x7fff04809b70, ctx=optimized out) at main/ff_fragment_shader.cpp:1472 #19 _mesa_get_fixed_func_fragment_program (ctx=optimized out) at main/ff_fragment_shader.cpp:1540 #20 0x7f1bfaf62890 in update_program (ctx=0x24dd700) at main/state.c:263 #21 _mesa_update_state_locked (ctx=0x24dd700) at main/state.c:676 #22 0x7f1bfaf6393f in _mesa_update_state (ctx=0x24dd700) at main/state.c:709 #23 0x7f1bfaec47b9 in _mesa_valid_to_render (ctx=0x24dd700, where=optimized out) at main/context.c:1723 #24 0x7f1bfb060517 in check_valid_to_render (ctx=0x24dd700, function=optimized out) at main/api_validate.c:105 #25 0x7f1bfb0613b2 in _mesa_validate_DrawElements (ctx=0x24dd700, mode=optimized out, count=1494, type=5123, indices=0x898ff60, basevertex=optimized out) at main/api_validate.c:253 #26 0x7f1bfafb8f42 in vbo_exec_DrawElements (mode=4, count=1494, type=5123, indices=0x898ff60) at vbo/vbo_exec_array.c:1010 #27 0x7f1bfc984381 in NL3D::CDriverGL::renderTriangles(NL3D::CMaterial, unsigned int, unsigned int) () from /usr/lib/nel/libnel_drv_opengl.so ---Type return to continue, or q return to quit--- #28 0x7f1c05a98b27 in NL3D::CMeshMRMSkinnedGeom::renderSkinGroupSpecularRdrPass(NL3D::CMeshMRMSkinnedInstance*, unsigned int) () from /usr/lib/libnel3d.so.0 #29 0x7f1c05c7b5cf in NL3D::CSkeletonModel::renderSkinList(NLMISC::CObjectVectorNL3D::CTransform*, false, float) () from /usr/lib/libnel3d.so.0 #30 0x7f1c05c7ba66 in NL3D::CSkeletonModel::renderSkins() () from /usr/lib/libnel3d.so.0 #31 0x7f1c05c7bc25 in NL3D::CSkeletonModel::traverseRender() () from /usr/lib/libnel3d.so.0 #32 0x7f1c058f3ae1 in NL3D::CRenderTrav::traverse(NL3D::UScene::TRenderPart, bool) () from /usr/lib/libnel3d.so.0 #33 0x7f1c05a64bc2 in NL3D::CScene::renderPart(NL3D::UScene::TRenderPart, bool) () from /usr/lib/libnel3d.so.0 #34 0x7f1c05a667a9 in NL3D::CScene::render(bool) () from /usr/lib/libnel3d.so.0 #35 0x7f1c05bd43ce in NL3D::CSceneUser::render(bool, bool) () from /usr/lib/libnel3d.so.0 #36 0x009fcbe8 in CInterface3DScene::draw() () #37 0x00a6d6f6 in CInterfaceGroup::draw() () #38 0x00bb7388 in CInterfaceManager::drawViews(NL3D::UCamera) ()
Re: [Mesa-dev] [PATCH 5/6] gallium: expose GLSL 1.3 if PIPE_CAP_SM4 is exposed (new cap)
Please disregard this patch and the last one too. GLSL 1.3 in st/mesa
is not as complete and usable as I thought.
Marek
On Fri, Nov 18, 2011 at 8:27 PM, Marek Olšák mar...@gmail.com wrote:
---
src/gallium/include/pipe/p_defines.h | 3 ++-
src/mesa/state_tracker/st_extensions.c | 5 +
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 3e55d22..e51132a 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -475,7 +475,8 @@ enum pipe_cap {
PIPE_CAP_MIN_TEXEL_OFFSET = 50,
PIPE_CAP_MAX_TEXEL_OFFSET = 51,
PIPE_CAP_CONDITIONAL_RENDER = 52,
- PIPE_CAP_TEXTURE_BARRIER = 53
+ PIPE_CAP_TEXTURE_BARRIER = 53,
+ PIPE_CAP_SM4 = 54 /* Shader Model 4.0 (roughly equivalent to GLSL 1.3) */
};
/* Shader caps not specific to any single stage */
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 544f0b6..96a1059 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -245,6 +245,11 @@ void st_init_extensions(struct st_context *st)
int i;
ctx-Const.GLSLVersion = 120;
+
+ if (screen-get_param(screen, PIPE_CAP_SM4)) {
+ ctx-Const.GLSLVersion = 130;
+ }
+
_mesa_override_glsl_version(st-ctx);
/*
--
1.7.5.4
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Re: [Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree
On Thu, 17 Nov 2011 19:58:35 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
Essentially, this patch just globally substitutes `irb-region` with
`irb-mt-region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
In case I get distracted before finishing, patches 1-7 are
Reviewed-by: Eric Anholt e...@anholt.net
---
@@ -1381,9 +1396,12 @@ intel_process_dri2_buffer_with_separate_stencil(struct
intel_context *intel,
buffer_name);
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-hiz_region, region);
+ intel_region_reference(rb-mt-hiz_region, region);
} else {
- intel_region_reference(rb-region, region);
+ rb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);;
}
Leaked old rb-mt here? I don't see this function kicking off with an
intel_miptree_release(rb-mt). Next quoted hunk has the same issue.
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-hiz_region, region);
+ intel_region_reference(rb-mt-hiz_region, region);
} else {
- intel_region_reference(rb-region, region);
+ rb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);;
extra ';'
- intel_region_reference(intel_get_renderbuffer(fb,
BUFFER_DEPTH)-region,
- region);
- intel_region_reference(intel_get_renderbuffer(fb,
BUFFER_STENCIL)-region,
- region);
+ struct intel_mipmap_tree *mt =
+intel_miptree_create_for_region(intel,
+GL_TEXTURE_2D,
+depth_stencil_rb-Base.Format,
+region);
intel_region_release(region);
+ intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-mt,
mt);
+ intel_miptree_reference(intel_get_renderbuffer(fb,
BUFFER_STENCIL)-mt, mt);
Haven't you leaked a mt reference here?
}
irb = intel_renderbuffer(rb);
- intel_region_reference(irb-region, image-region);
+ irb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ image-format,
+ image-region);
+ if (!irb-mt)
+ return;
Leak of existing irb-mt?
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[Mesa-dev] [PATCH] mesa : move bindbuffer{base, range} from transformfeedback.c
BindBuffer* functions are part of tfb extension. They are however
used by others extensions such as uniform buffer object.
This patch moves the BindBuffer* definition to to bufferobj.c
where it acts as a dispatcher calling original tfb function ;
BindBuffer* functions can be used by others extensions, even if
FEATURE_EXT_transform_feedback is not defined.
---
src/mesa/main/api_exec.c |2 +
src/mesa/main/bufferobj.c | 144 +
src/mesa/main/bufferobj.h | 12 +++
src/mesa/main/transformfeedback.c | 109 +---
src/mesa/main/transformfeedback.h |7 --
5 files changed, 159 insertions(+), 115 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index 93214dd..0bbfa8b 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -590,6 +590,8 @@ _mesa_create_exec_table(void)
SET_IsBufferARB(exec, _mesa_IsBufferARB);
SET_MapBufferARB(exec, _mesa_MapBufferARB);
SET_UnmapBufferARB(exec, _mesa_UnmapBufferARB);
+ SET_BindBufferRangeEXT(exec, _mesa_BindBufferRange);
+ SET_BindBufferBaseEXT(exec, _mesa_BindBufferBase);
#endif
/* ARB 29. GL_ARB_occlusion_query */
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 431eafd..0908ce6 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -703,6 +703,150 @@ _mesa_BindBufferARB(GLenum target, GLuint buffer)
bind_buffer_object(ctx, target, buffer);
}
+/**
+ * Helper used by BindBufferRange() and BindBufferBase().
+ */
+void
+bind_buffer_range(struct gl_context *ctx, GLuint index,
+ struct gl_buffer_object *bufObj,
+ GLintptr offset, GLsizeiptr size);
+
+/**
+ * Several extensions declare a BindBufferBase API function,
+ * this one dispatchs call according to target
+ */
+void GLAPIENTRY
+_mesa_BindBufferBase(GLenum target, GLuint index, GLuint buffer)
+{
+
+/**
+ * Declare everything here to avoid declaring inside switch statement
+ */
+#if FEATURE_EXT_transform_feedback
+ struct gl_transform_feedback_object *obj;
+ struct gl_buffer_object *bufObj;
+ GLsizeiptr size;
+#endif
+
+ GET_CURRENT_CONTEXT(ctx);
+ switch (target) {
+#if FEATURE_EXT_transform_feedback
+ case GL_TRANSFORM_FEEDBACK_BUFFER:
+ /**
+ * Specify a buffer object to receive vertex shader results.
+ * As in BindBufferRange, but start at offset = 0.
+ */
+ obj = ctx-TransformFeedback.CurrentObject;
+
+ if (obj-Active) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+glBindBufferBase(transform feedback active));
+return;
+ }
+
+ if (index = ctx-Const.MaxTransformFeedbackSeparateAttribs) {
+_mesa_error(ctx, GL_INVALID_VALUE, glBindBufferBase(index=%d),
index);
+return;
+ }
+
+ bufObj = _mesa_lookup_bufferobj(ctx, buffer);
+ if (!bufObj) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+glBindBufferBase(invalid buffer=%u), buffer);
+return;
+ }
+
+ /* default size is the buffer size rounded down to nearest
+ * multiple of four.
+ */
+ size = bufObj-Size ~0x3;
+
+ bind_buffer_range(ctx, index, bufObj, 0, size);
+ break;
+#endif
+ default:
+ _mesa_error(ctx, GL_INVALID_ENUM, glBindBufferBase(target));
+ break;
+ }
+ return;
+}
+
+extern void
+BindBufferRange_TFB(GLenum target, GLuint index,
+ GLuint buffer, GLintptr offset, GLsizeiptr size);
+
+/**
+ * Several extensions declare a BindBufferRange API function,
+ * this one dispatchs call according to target
+ */
+void GLAPIENTRY
+_mesa_BindBufferRange(GLenum target, GLuint index,
+ GLuint buffer, GLintptr offset, GLsizeiptr size)
+{
+/**
+ * Declare everything here to avoid declaring inside switch statement
+ */
+#if FEATURE_EXT_transform_feedback
+ struct gl_transform_feedback_object *obj;
+ struct gl_buffer_object *bufObj;
+#endif
+
+ GET_CURRENT_CONTEXT(ctx);
+ switch (target) {
+#if FEATURE_EXT_transform_feedback
+ case GL_TRANSFORM_FEEDBACK_BUFFER:
+ /**
+ * Specify a buffer object to receive vertex shader results. Plus,
+ * specify the starting offset to place the results, and max size.
+ */
+ obj = ctx-TransformFeedback.CurrentObject;
+
+ if (obj-Active) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+glBindBufferRange(transform feedback active));
+return;
+ }
+
+ if (index = ctx-Const.MaxTransformFeedbackSeparateAttribs) {
+_mesa_error(ctx, GL_INVALID_VALUE, glBindBufferRange(index=%d),
index);
+return;
+ }
+
+ if ((size = 0) || (size 0x3)) {
+/* must be positive and multiple of four */
+
Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images
On Thu, 17 Nov 2011 19:58:38 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. It's
value, like width and height, varies with miplevel.
Its
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 9398dbd..8c41956 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -947,8 +947,9 @@ intel_framebuffer_renderbuffer(struct gl_context * ctx,
static bool
intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
- struct gl_texture_image *texImage)
+ struct gl_renderbuffer_attachment *att)
{
+ struct gl_texture_image *texImage = _mesa_get_attachment_teximage(att);
struct intel_texture_image *intel_image = intel_texture_image(texImage);
int width, height, depth;
@@ -993,7 +994,8 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
* This will have the region info needed for hardware rendering.
*/
static struct intel_renderbuffer *
-intel_wrap_texture(struct gl_context * ctx, struct gl_texture_image
*texImage)
+intel_wrap_texture(struct gl_context * ctx,
+struct gl_renderbuffer_attachment *att)
{
const GLuint name = ~0; /* not significant, but distinct for debugging
*/
struct intel_renderbuffer *irb;
@@ -1008,7 +1010,7 @@ intel_wrap_texture(struct gl_context * ctx, struct
gl_texture_image *texImage)
_mesa_init_renderbuffer(irb-Base, name);
irb-Base.ClassID = INTEL_RB_CLASS;
- if (!intel_update_wrapper(ctx, irb, texImage)) {
+ if (!intel_update_wrapper(ctx, irb, att)) {
free(irb);
return NULL;
}
@@ -1113,7 +1115,7 @@ intel_render_texture(struct gl_context * ctx,
return;
}
else if (!irb) {
- irb = intel_wrap_texture(ctx, image);
+ irb = intel_wrap_texture(ctx, att);
if (irb) {
/* bind the wrapper to the attachment point */
_mesa_reference_renderbuffer(att-Renderbuffer, irb-Base);
@@ -1125,7 +1127,7 @@ intel_render_texture(struct gl_context * ctx,
}
}
- if (!intel_update_wrapper(ctx, irb, image)) {
+ if (!intel_update_wrapper(ctx, irb, att)) {
_mesa_reference_renderbuffer(att-Renderbuffer, NULL);
_swrast_render_texture(ctx, fb, att);
return;
The changes in this file don't seem to fit in this patch.
- /** Depth of the mipmap at this level: 1 for 1D/2D/CUBE, n for 3D. */
+
+ /**
+* \brief Number of 2D slices in this miplevel.
+*
+* The exact semantics of depth varies according to the texture target:
+*- For GL_TEXTURE_CUBE_MAP, depth is 6.
+*- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It
is
+* identical for all miplevels in the texture.
+*- For GL_TEXTURE_3D, it is the texture's depth at this miplevel.
It's
+* value, like width and height, varies with miplevel.
Its
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index f4c1a68..8dad011 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -140,12 +140,13 @@ intel_tex_map_image_for_swrast(struct intel_context
*intel,
if (mt-target == GL_TEXTURE_3D ||
mt-target == GL_TEXTURE_2D_ARRAY ||
mt-target == GL_TEXTURE_1D_ARRAY) {
- int i;
/* ImageOffsets[] is only used for swrast's fetch_texel_3d, so we can't
* share code with the normal path.
*/
- for (i = 0; i mt-level[level].depth; i++) {
+ assert(face == 0);
+ int depth = mt-level[level].depth;
+ for (int i = 0; i depth; i++) {
intel_miptree_get_image_offset(mt, level, face, i, x, y);
intel_image-base.ImageOffsets[i] = x + y * mt-region-pitch;
}
Not really seeing the point of this hunk (pulling depth out of the loop)
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Re: [Mesa-dev] [PATCH 15/41] intel: Refactor intel_render_texture()
On Thu, 17 Nov 2011 19:58:42 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
This is in preparation for properly implementing glFramebufferTexture*()
for mipmapped depthstencil textures. The FIXME comments deleted by this
patch give a rough explanation of what was broken.
This refactor does the following:
- In intel_update_wrapper() and intel_wrap_texture(), prepare to
replace the 'att' parameter with a miptree.
- Move the call to intel_renderbuffer_set_draw_offsets() from
intel_render_texture() into intel_udpate_wrapper().
Each time I encounter those functions, I dislike their vague names.
(Update which wrapper? What is wrapped? What is the wrapper?). So, while
I was mucking around, I also renamed the functions.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 113
+++-
1 files changed, 81 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 8e4f7a9..a61c74c 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -945,41 +945,54 @@ intel_framebuffer_renderbuffer(struct gl_context * ctx,
intel_draw_buffer(ctx);
}
+/**
+ * NOTE: The 'att' parameter is a kludge that will soon be removed. Its
+ * presence allows us to refactor the wrapping of depthstencil textures that
+ * use separate stencil in two easily manageable steps, rather than in one
+ * large, hairy step. First, refactor the common wrapping code used by all
+ * texture formats. Second, refactor the separate stencil code paths.
+ */
static bool
-intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
- struct gl_renderbuffer_attachment *att)
+intel_renderbuffer_update_wrapper(struct intel_context *intel,
+ struct intel_renderbuffer *irb,
+ struct intel_mipmap_tree *mt,
+ uint32_t level,
+ uint32_t layer,
+ GLenum internal_format,
+ struct gl_renderbuffer_attachment *att)
{
+ struct gl_context *ctx = intel-ctx;
+ struct gl_renderbuffer *rb = irb-Base;
+
+ /* The image variables are a kludge. See the note above for the att
+* parameter.
+*/
struct gl_texture_image *texImage = _mesa_get_attachment_teximage(att);
struct intel_texture_image *intel_image = intel_texture_image(texImage);
- int width, height, depth;
- if (!intel_span_supports_format(texImage-TexFormat)) {
+ irb-Base.Format = ctx-Driver.ChooseTextureFormat(ctx, internal_format,
+ GL_NONE, GL_NONE);
+
+ if (!intel_span_supports_format(rb-Format)) {
This ChooseTextureFormat looks really out of place. I don't know why
you'd be choosing a new format here.
Actually, I can't even figure out where the - lines here, like
intel_span_supports_format(), came from. I don't think I can review
this patch.
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Re: [Mesa-dev] [PATCH] mesa : move bindbuffer{base, range} from transformfeedback.c
On 11/18/2011 01:11 PM, vlj wrote:
BindBuffer* functions are part of tfb extension. They are however
used by others extensions such as uniform buffer object.
This patch moves the BindBuffer* definition to to bufferobj.c
where it acts as a dispatcher calling original tfb function ;
BindBuffer* functions can be used by others extensions, even if
FEATURE_EXT_transform_feedback is not defined.
---
src/mesa/main/api_exec.c |2 +
src/mesa/main/bufferobj.c | 144 +
src/mesa/main/bufferobj.h | 12 +++
src/mesa/main/transformfeedback.c | 109 +---
src/mesa/main/transformfeedback.h |7 --
5 files changed, 159 insertions(+), 115 deletions(-)
diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c
index 93214dd..0bbfa8b 100644
--- a/src/mesa/main/api_exec.c
+++ b/src/mesa/main/api_exec.c
@@ -590,6 +590,8 @@ _mesa_create_exec_table(void)
SET_IsBufferARB(exec, _mesa_IsBufferARB);
SET_MapBufferARB(exec, _mesa_MapBufferARB);
SET_UnmapBufferARB(exec, _mesa_UnmapBufferARB);
+ SET_BindBufferRangeEXT(exec, _mesa_BindBufferRange);
+ SET_BindBufferBaseEXT(exec, _mesa_BindBufferBase);
#endif
/* ARB 29. GL_ARB_occlusion_query */
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 431eafd..0908ce6 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -703,6 +703,150 @@ _mesa_BindBufferARB(GLenum target, GLuint buffer)
bind_buffer_object(ctx, target, buffer);
}
+/**
+ * Helper used by BindBufferRange() and BindBufferBase().
+ */
+void
+bind_buffer_range(struct gl_context *ctx, GLuint index,
+ struct gl_buffer_object *bufObj,
+ GLintptr offset, GLsizeiptr size);
bind_buffer_range() should be moved into bufferobj.c and it should be
static. There's no reason to keep it in transformfeedback.c
+
+/**
+ * Several extensions declare a BindBufferBase API function,
+ * this one dispatchs call according to target
+ */
+void GLAPIENTRY
+_mesa_BindBufferBase(GLenum target, GLuint index, GLuint buffer)
+{
+
+/**
+ * Declare everything here to avoid declaring inside switch statement
+ */
+#if FEATURE_EXT_transform_feedback
+ struct gl_transform_feedback_object *obj;
+ struct gl_buffer_object *bufObj;
+ GLsizeiptr size;
+#endif
Move these xfb-related variables down into the switch case - the only
place they're used.
+
+ GET_CURRENT_CONTEXT(ctx);
+ switch (target) {
+#if FEATURE_EXT_transform_feedback
+ case GL_TRANSFORM_FEEDBACK_BUFFER:
+ /**
+ * Specify a buffer object to receive vertex shader results.
+ * As in BindBufferRange, but start at offset = 0.
+ */
+ obj = ctx-TransformFeedback.CurrentObject;
+
+ if (obj-Active) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+glBindBufferBase(transform feedback active));
+return;
+ }
+
+ if (index= ctx-Const.MaxTransformFeedbackSeparateAttribs) {
+_mesa_error(ctx, GL_INVALID_VALUE, glBindBufferBase(index=%d),
index);
+return;
+ }
+
+ bufObj = _mesa_lookup_bufferobj(ctx, buffer);
+ if (!bufObj) {
+_mesa_error(ctx, GL_INVALID_OPERATION,
+glBindBufferBase(invalid buffer=%u), buffer);
+return;
+ }
The buffer lookup and error check should be after the switch(target)
because it'll be needed for UBO as well.
+ /* default size is the buffer size rounded down to nearest
+ * multiple of four.
+ */
+ size = bufObj-Size ~0x3;
+
+ bind_buffer_range(ctx, index, bufObj, 0, size);
This call should also be placed after the switch.
+ break;
+#endif
+ default:
+ _mesa_error(ctx, GL_INVALID_ENUM, glBindBufferBase(target));
+ break;
+ }
+ return;
+}
+
+extern void
+BindBufferRange_TFB(GLenum target, GLuint index,
+ GLuint buffer, GLintptr offset, GLsizeiptr size);
+
+/**
+ * Several extensions declare a BindBufferRange API function,
+ * this one dispatchs call according to target
+ */
+void GLAPIENTRY
+_mesa_BindBufferRange(GLenum target, GLuint index,
+ GLuint buffer, GLintptr offset, GLsizeiptr size)
+{
+/**
+ * Declare everything here to avoid declaring inside switch statement
+ */
+#if FEATURE_EXT_transform_feedback
+ struct gl_transform_feedback_object *obj;
+ struct gl_buffer_object *bufObj;
+#endif
+
+ GET_CURRENT_CONTEXT(ctx);
+ switch (target) {
+#if FEATURE_EXT_transform_feedback
+ case GL_TRANSFORM_FEEDBACK_BUFFER:
+ /**
+ * Specify a buffer object to receive vertex shader results. Plus,
+ * specify the starting offset to place the results, and max size.
+ */
+ obj = ctx-TransformFeedback.CurrentObject;
+
+ if (obj-Active) {
+
Re: [Mesa-dev] [PATCH 1/6] glsl: finish up ARB_conservative_depth
On 11/18/2011 11:27 AM, Marek Olšák wrote:
This patch also needs to change the _mesa_glsl_supported_extensions
table in glsl_parser_extras.cpp. AMD_conservative_depth is used for
both versions of the extension in the table.
I'm not super convinced that we even need separate enable flags. Both
extensions add the exact same functionality using the exact same layout
qualifiers. It's not a big deal to me either way, though.
---
src/glsl/ast_to_hir.cpp |7 +--
src/glsl/glsl_lexer.ll |1 +
src/glsl/glsl_parser.yy |9 -
src/glsl/ir_clone.cpp |1 +
4 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index ac090c3..51fec19 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2090,6 +2090,7 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
* The following extension do not allow the deprecated keywords:
*
*GL_AMD_conservative_depth
+*GL_ARB_conservative_depth
*GL_ARB_gpu_shader5
*GL_ARB_separate_shader_objects
*GL_ARB_tesselation_shader
@@ -2122,7 +2123,8 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
+ qual-flags.q.depth_less
+ qual-flags.q.depth_unchanged;
if (depth_layout_count 0
- !state-AMD_conservative_depth_enable) {
+ !state-AMD_conservative_depth_enable
+ !state-ARB_conservative_depth_enable) {
_mesa_glsl_error(loc, state,
extension GL_AMD_conservative_depth must be enabled
to use depth layout qualifiers);
This error should be updated too.
extension GL_ARB_conservative_depth or GL_AMD_consevative_depth
must be enabled to use depth layout qualifiers
@@ -2237,7 +2239,8 @@ get_variable_being_redeclared(ir_variable *var,
ast_declaration *decl,
earlier-interpolation = var-interpolation;
/* Layout qualifiers for gl_FragDepth. */
- } else if (state-AMD_conservative_depth_enable
+ } else if ((state-AMD_conservative_depth_enable ||
+ state-ARB_conservative_depth_enable)
strcmp(var-name, gl_FragDepth) == 0
earlier-type == var-type
earlier-mode == var-mode) {
diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll
index 49f3bc8..c7cfedd 100644
--- a/src/glsl/glsl_lexer.ll
+++ b/src/glsl/glsl_lexer.ll
@@ -310,6 +310,7 @@ voidreturn VOID_TOK;
layout{
if ((yyextra-language_version= 140)
|| yyextra-AMD_conservative_depth_enable
+ || yyextra-ARB_conservative_depth_enable
|| yyextra-ARB_explicit_attrib_location_enable
|| yyextra-ARB_fragment_coord_conventions_enable) {
return LAYOUT_TOK;
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index 8363904..71ab039 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1124,7 +1124,9 @@ layout_qualifier_id:
}
/* Layout qualifiers for AMD/ARB_conservative_depth. */
- if (!got_one state-AMD_conservative_depth_enable) {
+ if (!got_one
+ (state-AMD_conservative_depth_enable ||
+ state-ARB_conservative_depth_enable)) {
if (strcmp($1, depth_any) == 0) {
got_one = true;
$$.flags.q.depth_any = 1;
@@ -1141,6 +1143,11 @@ layout_qualifier_id:
if (got_one state-AMD_conservative_depth_warn) {
_mesa_glsl_warning( @1, state,
+ GL_AMD_conservative_depth
+ layout qualifier `%s' is used\n, $1);
+ }
+ if (got_one state-ARB_conservative_depth_warn) {
+_mesa_glsl_warning( @1, state,
GL_ARB_conservative_depth
layout qualifier `%s' is used\n, $1);
}
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index e8ac9fb..c63615c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -51,6 +51,7 @@ ir_variable::clone(void *mem_ctx, struct hash_table *ht) const
var-pixel_center_integer = this-pixel_center_integer;
var-explicit_location = this-explicit_location;
var-has_initializer = this-has_initializer;
+ var-depth_layout = this-depth_layout;
var-num_state_slots = this-num_state_slots;
if (this-state_slots) {
___
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Re: [Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
On 11/18/2011 11:27 AM, Marek Olšák wrote:
---
src/glsl/linker.cpp| 45
src/mesa/main/mtypes.h |3 ++
src/mesa/program/ir_to_mesa.cpp| 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir = prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
It's probably worth explaining why you can't just look up gl_FragDepth
in the symbol table here. I was going to suggest changing to that, but
I managed to convince myself that looping over the IR is correct.
With that small change, this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
+ switch (var-depth_layout) {
+ case ir_depth_layout_none:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
+return;
+ case ir_depth_layout_any:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
+return;
+ case ir_depth_layout_greater:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
+return;
+ case ir_depth_layout_less:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
+return;
+ case ir_depth_layout_unchanged:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
+return;
+ default:
+assert(0);
+return;
+ }
+ }
+ }
+}
+
+/**
* Validate the resources used by a program versus the implementation limits
*/
static bool
@@ -2177,6 +2221,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
update_array_sizes(prog);
link_assign_uniform_locations(prog);
+ store_fragdepth_layout(prog);
if (!check_resources(ctx, prog))
goto done;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 285ec07..b3427da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2218,6 +2218,9 @@ struct gl_shader_program
/** Post-link transform feedback info. */
struct gl_transform_feedback_info LinkedTransformFeedback;
+ /** Post-link gl_FragDepth layout for ARB_conservative_depth. */
+ enum gl_frag_depth_layout FragDepthLayout;
+
/** Geometry shader state - copied into gl_geometry_program at link time */
struct {
GLint VerticesOut;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 5cee837..5a68fc5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -685,29 +685,6 @@ ir_to_mesa_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
*)this-prog;
- switch (ir-depth_layout) {
- case ir_depth_layout_none:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
-break;
- case ir_depth_layout_any:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
-break;
- case ir_depth_layout_greater:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
-break;
- case ir_depth_layout_less:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
-break;
- case ir_depth_layout_unchanged:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
-break;
- default:
-assert(0);
-break;
- }
}
if (ir-mode == ir_var_uniform strncmp(ir-name, gl_, 3) == 0) {
@@ -3222,6 +3199,12 @@ get_mesa_program(struct gl_context *ctx,
do_set_program_inouts(shader-ir, prog, shader-Type ==
GL_FRAGMENT_SHADER);
count_resources(prog);
+ /* Set the gl_FragDepth layout. */
+ if (target == GL_FRAGMENT_PROGRAM_ARB) {
+ struct gl_fragment_program *fp = (struct gl_fragment_program *)prog;
+ fp-FragDepthLayout = shader_program-FragDepthLayout;
+ }
+
_mesa_reference_program(ctx,shader-Program, prog);
if ((ctx-Shader.Flags GLSL_NO_OPT) == 0) {
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 0bf6766..929c7af 100644
---
Re: [Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 12:04 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:35 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
Essentially, this patch just globally substitutes `irb-region` with
`irb-mt-region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
@@ -1381,9 +1396,12 @@
intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
buffer_name);
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-hiz_region, region);
+ intel_region_reference(rb-mt-hiz_region, region);
} else {
- intel_region_reference(rb-region, region);
+ rb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);;
}
Leaked old rb-mt here? I don't see this function kicking off with an
intel_miptree_release(rb-mt). Next quoted hunk has the same issue.
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-hiz_region, region);
+ intel_region_reference(rb-mt-hiz_region, region);
} else {
- intel_region_reference(rb-region, region);
+ rb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);;
extra ';'
- intel_region_reference(intel_get_renderbuffer(fb,
BUFFER_DEPTH)-region,
-region);
- intel_region_reference(intel_get_renderbuffer(fb,
BUFFER_STENCIL)-region,
-region);
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ depth_stencil_rb-Base.Format,
+ region);
intel_region_release(region);
+ intel_miptree_reference(intel_get_renderbuffer(fb, BUFFER_DEPTH)-mt,
mt);
+ intel_miptree_reference(intel_get_renderbuffer(fb,
BUFFER_STENCIL)-mt, mt);
Haven't you leaked a mt reference here?
}
irb = intel_renderbuffer(rb);
- intel_region_reference(irb-region, image-region);
+ irb-mt = intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ image-format,
+ image-region);
+ if (!irb-mt)
+ return;
Leak of existing irb-mt?
Right. My refcounting here is a mess. Expect v2 of this patch in a moment.
-
Chad Versace
chad.vers...@linux.intel.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
iQIcBAEBAgAGBQJOxsS3AAoJEAIvNt057x8ijPEP/3QrgfEIwGvXlcE1z0m8qumn
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Uab1RLPxXisBEqL8vVt0yN/u2+8ATbrICIM1c51bCq2wL35fX7dKBMPscCcARVmJ
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q6SgTCDK3wmEj0Fp6wPO
=e7Px
-END PGP SIGNATURE-
___
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[Mesa-dev] [PATCH] intel: Replace intel_renderbuffer::region with a miptree [v2]
Essentially, this patch just globally substitutes `irb-region` with
`irb-mt-region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
CC: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c| 21 ++-
src/mesa/drivers/dri/i965/brw_vtbl.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 11 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +-
src/mesa/drivers/dri/intel/intel_blit.c | 21 ++-
src/mesa/drivers/dri/intel/intel_buffer_objects.c |8 +-
src/mesa/drivers/dri/intel/intel_buffers.c|9 +-
src/mesa/drivers/dri/intel/intel_context.c| 78 ---
src/mesa/drivers/dri/intel/intel_fbo.c| 151 +++--
src/mesa/drivers/dri/intel/intel_fbo.h|7 +-
src/mesa/drivers/dri/intel/intel_pixel_copy.c |5 +-
src/mesa/drivers/dri/intel/intel_screen.c |3 +-
src/mesa/drivers/dri/intel/intel_span.c |3 +-
src/mesa/drivers/dri/intel/intel_tex_copy.c | 14 ++-
src/mesa/drivers/dri/intel/intel_tex_image.c |6 +-
16 files changed, 203 insertions(+), 140 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 514c990..4119afa 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -33,6 +33,7 @@
#include intel_batchbuffer.h
#include intel_fbo.h
+#include intel_mipmap_tree.h
#include intel_regions.h
#include brw_context.h
@@ -204,9 +205,14 @@ static void emit_depthbuffer(struct brw_context *brw)
/* _NEW_BUFFERS */
struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb,
BUFFER_DEPTH);
struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb,
BUFFER_STENCIL);
- struct intel_region *hiz_region = depth_irb ? depth_irb-hiz_region : NULL;
+ struct intel_region *hiz_region = NULL;
unsigned int len;
+ if (depth_irb
+ depth_irb-mt) {
+ hiz_region = depth_irb-mt-hiz_region;
+ }
+
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
* non-pipelined state that will need the PIPE_CONTROL workaround.
*/
@@ -272,6 +278,8 @@ static void emit_depthbuffer(struct brw_context *brw)
* [DevGT]: This field must be set to the same value (enabled or
* disabled) as Hierarchical Depth Buffer Enable
*/
+ struct intel_region *region = stencil_irb-mt-region;
+
assert(intel-has_separate_stencil);
assert(stencil_irb-Base.Format == MESA_FORMAT_S8);
@@ -283,8 +291,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(BRW_TILEWALK_YMAJOR 26) |
(BRW_SURFACE_2D 29));
OUT_BATCH(0);
- OUT_BATCH(((stencil_irb-region-width - 1) 6) |
-(2 * stencil_irb-region-height - 1) 19);
+ OUT_BATCH(((region-width - 1) 6) |
+(2 * region-height - 1) 19);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -294,7 +302,7 @@ static void emit_depthbuffer(struct brw_context *brw)
ADVANCE_BATCH();
} else {
- struct intel_region *region = depth_irb-region;
+ struct intel_region *region = depth_irb-mt-region;
unsigned int format;
uint32_t tile_x, tile_y, offset;
@@ -379,10 +387,11 @@ static void emit_depthbuffer(struct brw_context *brw)
/* Emit stencil buffer. */
if (stencil_irb) {
+struct intel_region *region = stencil_irb-mt-region;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER 16) | (3 - 2));
-OUT_BATCH(stencil_irb-region-pitch * stencil_irb-region-cpp - 1);
-OUT_RELOC(stencil_irb-region-bo,
+OUT_BATCH(region-pitch * region-cpp - 1);
+OUT_RELOC(region-bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c
b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 7c23faa..9302b27 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -126,7 +126,7 @@ brw_update_draw_buffer(struct intel_context *intel)
/* Check
Re: [Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
On 11/18/2011 12:44 PM, Ian Romanick wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
---
src/glsl/linker.cpp| 45
src/mesa/main/mtypes.h |3 ++
src/mesa/program/ir_to_mesa.cpp| 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx,
struct gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir =
prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
It's probably worth explaining why you can't just look up gl_FragDepth
in the symbol table here. I was going to suggest changing to that, but
I managed to convince myself that looping over the IR is correct.
With that small change, this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Agreed.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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[Mesa-dev] [PATCH] intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
CC: Eric Anholt eric@anholt
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++--
src/mesa/drivers/dri/intel/intel_context.c | 23 +--
src/mesa/drivers/dri/intel/intel_fbo.c | 11 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 19 ++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 22 +-
5 files changed, 50 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 4119afa..17da460 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -209,8 +209,9 @@ static void emit_depthbuffer(struct brw_context *brw)
unsigned int len;
if (depth_irb
- depth_irb-mt) {
- hiz_region = depth_irb-mt-hiz_region;
+ depth_irb-mt
+ depth_irb-mt-hiz_mt) {
+ hiz_region = depth_irb-mt-hiz_mt-region;
}
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 3f55c51..9af21c8 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1357,8 +1357,8 @@ intel_process_dri2_buffer_with_separate_stencil(struct
intel_context *intel,
rb-mt-region-name == buffer-name) ||
(buffer-attachment == __DRI_BUFFER_HIZ
rb-mt
- rb-mt-hiz_region
- rb-mt-hiz_region-name == buffer-name)) {
+ rb-mt-hiz_mt
+ rb-mt-hiz_mt-region-name == buffer-name)) {
return;
}
@@ -1388,10 +1388,10 @@ intel_process_dri2_buffer_with_separate_stencil(struct
intel_context *intel,
}
/* Release the buffer storage now in case we have to return early
-* due to region allocation failure.
+* due to failure to allocate new storage.
*/
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_release(rb-mt-hiz_region);
+ intel_miptree_release(rb-mt-hiz_mt);
} else {
intel_miptree_release(rb-mt);
}
@@ -1407,15 +1407,18 @@ intel_process_dri2_buffer_with_separate_stencil(struct
intel_context *intel,
if (!region)
return;
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);
+ intel_region_release(region);
+
/* Associate buffer with new storage. */
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- rb-mt-hiz_region = region;
+ rb-mt-hiz_mt = mt;
} else {
- rb-mt = intel_miptree_create_for_region(intel,
- GL_TEXTURE_2D,
- rb-Base.Format,
- region);
- intel_region_release(region);
+ rb-mt = mt;
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index a6dc770..545e066 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -63,7 +63,7 @@ intel_framebuffer_has_hiz(struct gl_framebuffer *fb)
struct intel_renderbuffer *rb = NULL;
if (fb)
rb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
- return rb rb-mt rb-mt-hiz_region;
+ return rb rb-mt rb-mt-hiz_mt;
}
struct intel_region*
@@ -705,13 +705,8 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
return false;
if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
-irb-mt-hiz_region = intel_region_alloc(intel-intelScreen,
- I915_TILING_Y,
- cpp,
- rb-Width,
- rb-Height,
- true);
-if (!irb-mt) {
+bool ok = intel_miptree_alloc_hiz(intel, irb-mt);
+if (!ok) {
intel_miptree_release(irb-mt);
return false;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 71fba8d..378e09c 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -261,8 +261,8 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
DBG(%s deleting %p\n, __FUNCTION__, *mt);
intel_region_release(((*mt)-region));
-
Re: [Mesa-dev] [PATCH 4/6] gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionally
On 11/18/2011 11:27 AM, Marek Olšák wrote: Only i965g does not enable GLSL, but that driver has been unmaintained and bitrotting for quite a while anyway. It doesn't even do GLSL? I'm pretty shocked, I figured it at least did that. Is it even worth keeping around in the tree? Seems like it's just creating extra work for you guys, having to update it for Gallium changes...when ultimately, nobody's using it. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/6] glsl: finish up ARB_conservative_depth
On 11/18/2011 11:27 AM, Marek Olšák wrote:
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index e8ac9fb..c63615c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -51,6 +51,7 @@ ir_variable::clone(void *mem_ctx, struct hash_table *ht)
const
var-pixel_center_integer = this-pixel_center_integer;
var-explicit_location = this-explicit_location;
var-has_initializer = this-has_initializer;
+ var-depth_layout = this-depth_layout;
var-num_state_slots = this-num_state_slots;
if (this-state_slots) {
This looks like a useful hunk that we must've missed. It's also fairly
unrelated to the rest of your patch (splitting AMD/ARB enable bits).
I don't think we need to split the AMD/ARB enable bits; it's the exact
same extension with a name change and some rewording of the spec language.
I'd be in favor of pushing this hunk as it's own patch and dropping the
rest. You can have my R-b on such a patch.
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Re: [Mesa-dev] [PATCH 1/6] glsl: finish up ARB_conservative_depth
On Fri, Nov 18, 2011 at 10:14 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index e8ac9fb..c63615c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -51,6 +51,7 @@ ir_variable::clone(void *mem_ctx, struct hash_table *ht)
const
var-pixel_center_integer = this-pixel_center_integer;
var-explicit_location = this-explicit_location;
var-has_initializer = this-has_initializer;
+ var-depth_layout = this-depth_layout;
var-num_state_slots = this-num_state_slots;
if (this-state_slots) {
This looks like a useful hunk that we must've missed. It's also fairly
unrelated to the rest of your patch (splitting AMD/ARB enable bits).
I don't think we need to split the AMD/ARB enable bits; it's the exact
same extension with a name change and some rewording of the spec language.
I'd be in favor of pushing this hunk as it's own patch and dropping the
rest. You can have my R-b on such a patch.
I am not splitting the enables, they were already split. I was only
making both the extensions work. AMD_conservative_depth was broken at
least because of the missing line in the 'clone' function.
ARB_conservative_depth was broken completely (it wasn't even accepted
by the #extension directive). I am not for having separate flags
either, but the cleanup was not meant to be part of the patch. I can
rework it if needed though.
Marek
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Re: [Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
On Fri, Nov 18, 2011 at 9:44 PM, Ian Romanick i...@freedesktop.org wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
---
src/glsl/linker.cpp | 45
src/mesa/main/mtypes.h | 3 ++
src/mesa/program/ir_to_mesa.cpp | 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir = prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
It's probably worth explaining why you can't just look up gl_FragDepth in
the symbol table here. I was going to suggest changing to that, but I
managed to convince myself that looping over the IR is correct.
The reason is I didn't know there is actually any other way to look up
a variable than walking over the IR. You might have been right that I
should have used the look-up you are talking about.
Marek
With that small change, this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
+ switch (var-depth_layout) {
+ case ir_depth_layout_none:
+ prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
+ return;
+ case ir_depth_layout_any:
+ prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
+ return;
+ case ir_depth_layout_greater:
+ prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
+ return;
+ case ir_depth_layout_less:
+ prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
+ return;
+ case ir_depth_layout_unchanged:
+ prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
+ return;
+ default:
+ assert(0);
+ return;
+ }
+ }
+ }
+}
+
+/**
* Validate the resources used by a program versus the implementation
limits
*/
static bool
@@ -2177,6 +2221,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
update_array_sizes(prog);
link_assign_uniform_locations(prog);
+ store_fragdepth_layout(prog);
if (!check_resources(ctx, prog))
goto done;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 285ec07..b3427da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2218,6 +2218,9 @@ struct gl_shader_program
/** Post-link transform feedback info. */
struct gl_transform_feedback_info LinkedTransformFeedback;
+ /** Post-link gl_FragDepth layout for ARB_conservative_depth. */
+ enum gl_frag_depth_layout FragDepthLayout;
+
/** Geometry shader state - copied into gl_geometry_program at link
time */
struct {
GLint VerticesOut;
diff --git a/src/mesa/program/ir_to_mesa.cpp
b/src/mesa/program/ir_to_mesa.cpp
index 5cee837..5a68fc5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -685,29 +685,6 @@ ir_to_mesa_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
*)this-prog;
- switch (ir-depth_layout) {
- case ir_depth_layout_none:
- fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
- break;
- case ir_depth_layout_any:
- fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
- break;
- case ir_depth_layout_greater:
- fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
- break;
- case ir_depth_layout_less:
- fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
- break;
- case ir_depth_layout_unchanged:
- fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
- break;
- default:
- assert(0);
- break;
- }
}
if (ir-mode == ir_var_uniform strncmp(ir-name, gl_, 3) == 0) {
@@ -3222,6 +3199,12 @@ get_mesa_program(struct gl_context *ctx,
do_set_program_inouts(shader-ir, prog, shader-Type ==
GL_FRAGMENT_SHADER);
count_resources(prog);
+ /* Set the gl_FragDepth layout. */
+ if (target == GL_FRAGMENT_PROGRAM_ARB) {
+ struct gl_fragment_program *fp =
Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 12:22 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:38 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. It's
value, like width and height, varies with miplevel.
Its
I'll fix the two It's.
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
The changes in this file don't seem to fit in this patch.
Oops. These hunks are complete mistake. I assume they were introduced by a
rebase.
They will be removed.
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index f4c1a68..8dad011 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -140,12 +140,13 @@ intel_tex_map_image_for_swrast(struct intel_context
*intel,
if (mt-target == GL_TEXTURE_3D ||
mt-target == GL_TEXTURE_2D_ARRAY ||
mt-target == GL_TEXTURE_1D_ARRAY) {
- int i;
/* ImageOffsets[] is only used for swrast's fetch_texel_3d, so we
can't
* share code with the normal path.
*/
- for (i = 0; i mt-level[level].depth; i++) {
+ assert(face == 0);
+ int depth = mt-level[level].depth;
+ for (int i = 0; i depth; i++) {
intel_miptree_get_image_offset(mt, level, face, i, x, y);
intel_image-base.ImageOffsets[i] = x + y * mt-region-pitch;
}
Not really seeing the point of this hunk (pulling depth out of the loop)
This is really a sloppy commit. There is no need for this hunk either.
Other than the spurious hunks, are you ok with this patch?
-
Chad Versace
chad.vers...@linux.intel.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
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km3vrQ9qtCF+IrpCAvQ+SZkv2hU9N2C7ao2W8PRWEHfSVbOUxrJxNMQ+NAp/14XO
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d2DCo2vkxPU3on+IwFH0
=MDMI
-END PGP SIGNATURE-
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[Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images [v2]
From: Chad Versace chad.vers...@linux.intel.com
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace It's with Its.
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
CC: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 17 -
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 44 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 18 +++---
src/mesa/drivers/dri/intel/intel_tex_layout.c |4 +-
src/mesa/drivers/dri/intel/intel_tex_layout.h |3 +-
src/mesa/drivers/dri/intel/intel_tex_validate.c |2 +-
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index d77bf4d..ac6ade6 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -41,8 +41,7 @@
static void
brw_miptree_layout_texture_array(struct intel_context *intel,
-struct intel_mipmap_tree *mt,
-int slices)
+struct intel_mipmap_tree *mt)
{
GLuint align_w;
GLuint align_h;
@@ -58,14 +57,14 @@ brw_miptree_layout_texture_array(struct intel_context
*intel,
if (mt-compressed)
qpitch /= 4;
- i945_miptree_layout_2d(mt, slices);
+ i945_miptree_layout_2d(mt);
for (level = mt-first_level; level = mt-last_level; level++) {
- for (q = 0; q slices; q++) {
+ for (q = 0; q mt-depth0; q++) {
intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
}
}
- mt-total_height = qpitch * slices;
+ mt-total_height = qpitch * mt-depth0;
}
void
@@ -82,7 +81,7 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
* pitch of qpitch rows, where qpitch is defined by the equation given
* in Volume 1 of the BSpec.
*/
-brw_miptree_layout_texture_array(intel, mt, 6);
+brw_miptree_layout_texture_array(intel, mt);
break;
}
/* FALLTHROUGH */
@@ -117,7 +116,7 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
GLint y = 0;
GLint q, j;
-intel_miptree_set_level_info(mt, level, nr_images,
+intel_miptree_set_level_info(mt, level,
0, mt-total_height,
width, height, depth);
@@ -170,11 +169,11 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_1D_ARRAY:
- brw_miptree_layout_texture_array(intel, mt, mt-depth0);
+ brw_miptree_layout_texture_array(intel, mt);
break;
default:
- i945_miptree_layout_2d(mt, 1);
+ i945_miptree_layout_2d(mt);
break;
}
DBG(%s: %dx%dx%d\n, __FUNCTION__,
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 8f10101..8b9bd19 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -82,11 +82,17 @@ intel_miptree_create_internal(struct intel_context *intel,
mt-last_level = last_level;
mt-width0 = width0;
mt-height0 = height0;
- mt-depth0 = depth0;
mt-cpp = compress_byte ? compress_byte :
_mesa_get_format_bytes(mt-format);
mt-compressed = compress_byte ? 1 : 0;
mt-refcount = 1;
+ if (target == GL_TEXTURE_CUBE_MAP) {
+ assert(depth0 == 1);
+ mt-depth0 = 6;
+
Re: [Mesa-dev] ir_swizzle @ 0xe134ae0 specifies a channel not present in the value
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/18/2011 11:48 AM, Theiss, Ingo wrote: Hi there, while trying to play the game Ryzom with latest mesa compiled from git the program terminates with error ir_swizzle @ 0xe134ae0 specifies a channel not present in the value. Switching back to the stable branch mesa-7.11 (haven´t tried mesa-7.11.1) the error is gone. My glxinfo: OpenGL renderer string: Gallium 0.4 on AMD BARTS OpenGL version string: 2.1 Mesa 7.12-devel (git-7e84a64) OpenGL shading language version string: 1.20 Here is the backtrace: Ingo, please file a bug report for this at the Freedesktop Bugzilla. https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa That way we can have a permanent record of the bug and track it more easily. - Chad Versace chad.vers...@linux.intel.com -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJOxtVUAAoJEAIvNt057x8i2twQAK60WNY8hbHLCYAbwVQvwLjb 5xsDhJIOXTattv+lA600w23ToJuEQqpoViM9Ur4C4VQ+c36zifHt7HfUbGSsqADF UAdafWgVGkGFGlQpdf5hAeCpfabDzxEjdzBzte808B70MZP4Ah8Is38MqxcRZZF6 eKhJH0ZbDprHDawIzDNLQxtYeJYDsPkekwdOsgOfXQLFEEMX0FaZxgnxPfs2O9z9 XkNuJ5q20SpCSzs8769gd+jQ2Tn7UmxfaNgTwzWUbNl7nR71TvvgNO/aKzhZNH2Z SmhGKG9Abb5pj5eY6ApNvGn1ScsLXcrGUm69thjldzOaXWrLzBLl7s8cRmK1aqXT 7y/jX2/LfeurIT3lP5DN8ewoDsXC8sNSyyE6iAPeU9AX4jfLCD22Ive+giwTgp40 mh8XxVMYpC5koVZOPbTC5hUe7qYJ2y7WFzKTfi3SLsFFlg6NDi617gpnMO4LEpuM 0cxLux+vvl3y/ZvGd/jphQVOu0Gx1XBr2h0guUnnf0vD5yKfMY4NNpRL1Sl9I3lW dQhL/m+BjyLv4ADXS8JL5QPdQgBdzTqBw9M6D8/11QQyOzFcMjYaDdDSKlySmqC5 OmlpAucJsOHtk7fThyVKLfA+X2b60Zqf7tUfdLdFFCxbDvl9gNwN86/olCeq2JJt FsaXPJP2QUkEXP4bD8zk =s4TQ -END PGP SIGNATURE- ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Allow glTexImage2D with a depth component cube map
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/16/2011 07:56 PM, Anuj Phogat wrote:
From: Anuj Phogat anuj.pho...@gmail.com
Hi,
Here is a patch to allow glTexImage2D and glCopyTexImage2D with depth
component cubemap.
It is listed in mesa work queue with a label CUBE1. I've tested the patch
and output looks visually correct.
Please review the fix and let me know if i'm missing something.
Thanks
Anuj
---
src/mesa/main/teximage.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index acf7187..81f75c8 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1596,7 +1596,7 @@ texture_error_check( struct gl_context *ctx,
/* additional checks for depth textures */
if (_mesa_base_tex_format(ctx, internalFormat) == GL_DEPTH_COMPONENT) {
- /* Only 1D, 2D, rect and array textures supported, not 3D or cubes */
+ /* Only 1D, 2D, rect, array and cube textures are supported, not 3D*/
if (target != GL_TEXTURE_1D
target != GL_PROXY_TEXTURE_1D
target != GL_TEXTURE_2D
@@ -1606,7 +1606,13 @@ texture_error_check( struct gl_context *ctx,
target != GL_TEXTURE_2D_ARRAY
target != GL_PROXY_TEXTURE_2D_ARRAY
target != GL_TEXTURE_RECTANGLE_ARB
- target != GL_PROXY_TEXTURE_RECTANGLE_ARB) {
+ target != GL_PROXY_TEXTURE_RECTANGLE_ARB
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_X
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_X
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_Y
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_Y
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_Z
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_Z) {
if (!isProxy)
_mesa_error(ctx, GL_INVALID_ENUM,
glTexImage(target/internalFormat));
Anuj, the patch looks good, except that the lines are not vertically aligned.
Could you resubmit this with the alignment fixed?
To highlight hard tabs in vim, the magic invocation is `:set list`.
Also, could you share that test with us?
-
Chad Versace
chad.vers...@linux.intel.com
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Re: [Mesa-dev] [PATCH 1/6] glsl: finish up ARB_conservative_depth
On 11/18/2011 01:23 PM, Marek Olšák wrote:
On Fri, Nov 18, 2011 at 10:14 PM, Kenneth Graunke kenn...@whitecape.org
wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index e8ac9fb..c63615c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -51,6 +51,7 @@ ir_variable::clone(void *mem_ctx, struct hash_table *ht)
const
var-pixel_center_integer = this-pixel_center_integer;
var-explicit_location = this-explicit_location;
var-has_initializer = this-has_initializer;
+ var-depth_layout = this-depth_layout;
var-num_state_slots = this-num_state_slots;
if (this-state_slots) {
This looks like a useful hunk that we must've missed. It's also fairly
unrelated to the rest of your patch (splitting AMD/ARB enable bits).
I don't think we need to split the AMD/ARB enable bits; it's the exact
same extension with a name change and some rewording of the spec language.
I'd be in favor of pushing this hunk as it's own patch and dropping the
rest. You can have my R-b on such a patch.
I am not splitting the enables, they were already split. I was only
making both the extensions work. AMD_conservative_depth was broken at
least because of the missing line in the 'clone' function.
ARB_conservative_depth was broken completely (it wasn't even accepted
by the #extension directive). I am not for having separate flags
either, but the cleanup was not meant to be part of the patch. I can
rework it if needed though.
Marek
You're right...sorry for the confusion. Mesa's extensions.c uses a
single AMD_conservative_depth flag, but _mesa_glsl_supported_extensions
has separate AMD/ARB bits. That appears to be required by Paul's table
driven logic.
Now that I've re-examined the code, your patch looks correct. I think
I'd prefer to see two patches---one for the clone fix, and one for the
extension enable bits---but it's not critical.
Sorry I wrote such broken code for this in the first place!
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Re: [Mesa-dev] [PATCH 4/6] gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionally
- Original Message - On 11/18/2011 11:27 AM, Marek Olšák wrote: Only i965g does not enable GLSL, but that driver has been unmaintained and bitrotting for quite a while anyway. It doesn't even do GLSL? I'm pretty shocked, I figured it at least did that. Is it even worth keeping around in the tree? Seems like it's just creating extra work for you guys, having to update it for Gallium changes...when ultimately, nobody's using it. I agree -- this was never finished isn't likely to be either. Keith ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
On 11/18/2011 01:33 PM, Marek Olšák wrote:
On Fri, Nov 18, 2011 at 9:44 PM, Ian Romanicki...@freedesktop.org wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
---
src/glsl/linker.cpp| 45
src/mesa/main/mtypes.h |3 ++
src/mesa/program/ir_to_mesa.cpp| 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir = prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
It's probably worth explaining why you can't just look up gl_FragDepth in
the symbol table here. I was going to suggest changing to that, but I
managed to convince myself that looping over the IR is correct.
The reason is I didn't know there is actually any other way to look up
a variable than walking over the IR. You might have been right that I
should have used the look-up you are talking about.
If gl_FragDepth is not used in the shader, it will be removed from the
IR. However, it won't be removed from the symbol table. I had a couple
patches a month or two ago related to this issue. See 7bbcc0b. I'd
swear that there was another patch around that same time, but I don't
see it.
Marek
With that small change, this patch is
Reviewed-by: Ian Romanickian.d.roman...@intel.com
+ switch (var-depth_layout) {
+ case ir_depth_layout_none:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
+return;
+ case ir_depth_layout_any:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
+return;
+ case ir_depth_layout_greater:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
+return;
+ case ir_depth_layout_less:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
+return;
+ case ir_depth_layout_unchanged:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
+return;
+ default:
+assert(0);
+return;
+ }
+ }
+ }
+}
+
+/**
* Validate the resources used by a program versus the implementation
limits
*/
static bool
@@ -2177,6 +2221,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
update_array_sizes(prog);
link_assign_uniform_locations(prog);
+ store_fragdepth_layout(prog);
if (!check_resources(ctx, prog))
goto done;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 285ec07..b3427da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2218,6 +2218,9 @@ struct gl_shader_program
/** Post-link transform feedback info. */
struct gl_transform_feedback_info LinkedTransformFeedback;
+ /** Post-link gl_FragDepth layout for ARB_conservative_depth. */
+ enum gl_frag_depth_layout FragDepthLayout;
+
/** Geometry shader state - copied into gl_geometry_program at link
time */
struct {
GLint VerticesOut;
diff --git a/src/mesa/program/ir_to_mesa.cpp
b/src/mesa/program/ir_to_mesa.cpp
index 5cee837..5a68fc5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -685,29 +685,6 @@ ir_to_mesa_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
*)this-prog;
- switch (ir-depth_layout) {
- case ir_depth_layout_none:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
-break;
- case ir_depth_layout_any:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
-break;
- case ir_depth_layout_greater:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
-break;
- case ir_depth_layout_less:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
-break;
- case ir_depth_layout_unchanged:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
-break;
- default:
-assert(0);
-break;
- }
}
if (ir-mode == ir_var_uniformstrncmp(ir-name, gl_, 3) == 0) {
@@ -3222,6 +3199,12 @@ get_mesa_program(struct gl_context
Re: [Mesa-dev] [PATCH 2/6] mesa: set the gl_FragDepth layout in the GLSL linker
On 11/18/2011 01:33 PM, Marek Olšák wrote:
On Fri, Nov 18, 2011 at 9:44 PM, Ian Romanicki...@freedesktop.org wrote:
On 11/18/2011 11:27 AM, Marek Olšák wrote:
---
src/glsl/linker.cpp| 45
src/mesa/main/mtypes.h |3 ++
src/mesa/program/ir_to_mesa.cpp| 29 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 23 --
4 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 0ec773d..226aa6f 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1876,6 +1876,50 @@ store_tfeedback_info(struct gl_context *ctx, struct
gl_shader_program *prog,
}
/**
+ * Store the gl_FragDepth layout in the gl_shader_program struct.
+ */
+static void
+store_fragdepth_layout(struct gl_shader_program *prog)
+{
+ if (prog-_LinkedShaders[MESA_SHADER_FRAGMENT] == NULL) {
+ return;
+ }
+
+ struct exec_list *ir = prog-_LinkedShaders[MESA_SHADER_FRAGMENT]-ir;
+
+ foreach_list(node, ir) {
+ ir_variable *const var = ((ir_instruction *) node)-as_variable();
+
+ if (var == NULL || var-mode != ir_var_out) {
+ continue;
+ }
+
+ if (strcmp(var-name, gl_FragDepth) == 0) {
It's probably worth explaining why you can't just look up gl_FragDepth in
the symbol table here. I was going to suggest changing to that, but I
managed to convince myself that looping over the IR is correct.
The reason is I didn't know there is actually any other way to look up
a variable than walking over the IR. You might have been right that I
should have used the look-up you are talking about.
If gl_FragDepth is not used in the shader, it will be removed from the
IR. However, it won't be removed from the symbol table. I had a couple
patches a month or two ago related to this issue. See 7bbcc0b. I'd
swear that there was another patch around that same time, but I don't
see it.
Marek
With that small change, this patch is
Reviewed-by: Ian Romanickian.d.roman...@intel.com
+ switch (var-depth_layout) {
+ case ir_depth_layout_none:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
+return;
+ case ir_depth_layout_any:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
+return;
+ case ir_depth_layout_greater:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
+return;
+ case ir_depth_layout_less:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
+return;
+ case ir_depth_layout_unchanged:
+prog-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
+return;
+ default:
+assert(0);
+return;
+ }
+ }
+ }
+}
+
+/**
* Validate the resources used by a program versus the implementation
limits
*/
static bool
@@ -2177,6 +2221,7 @@ link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
update_array_sizes(prog);
link_assign_uniform_locations(prog);
+ store_fragdepth_layout(prog);
if (!check_resources(ctx, prog))
goto done;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 285ec07..b3427da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2218,6 +2218,9 @@ struct gl_shader_program
/** Post-link transform feedback info. */
struct gl_transform_feedback_info LinkedTransformFeedback;
+ /** Post-link gl_FragDepth layout for ARB_conservative_depth. */
+ enum gl_frag_depth_layout FragDepthLayout;
+
/** Geometry shader state - copied into gl_geometry_program at link
time */
struct {
GLint VerticesOut;
diff --git a/src/mesa/program/ir_to_mesa.cpp
b/src/mesa/program/ir_to_mesa.cpp
index 5cee837..5a68fc5 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -685,29 +685,6 @@ ir_to_mesa_visitor::visit(ir_variable *ir)
fp-OriginUpperLeft = ir-origin_upper_left;
fp-PixelCenterInteger = ir-pixel_center_integer;
-
- } else if (strcmp(ir-name, gl_FragDepth) == 0) {
- struct gl_fragment_program *fp = (struct gl_fragment_program
*)this-prog;
- switch (ir-depth_layout) {
- case ir_depth_layout_none:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_NONE;
-break;
- case ir_depth_layout_any:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_ANY;
-break;
- case ir_depth_layout_greater:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_GREATER;
-break;
- case ir_depth_layout_less:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_LESS;
-break;
- case ir_depth_layout_unchanged:
-fp-FragDepthLayout = FRAG_DEPTH_LAYOUT_UNCHANGED;
-break;
- default:
-assert(0);
-break;
- }
}
if (ir-mode == ir_var_uniformstrncmp(ir-name, gl_, 3) == 0) {
@@ -3222,6 +3199,12 @@ get_mesa_program(struct gl_context
Re: [Mesa-dev] [PATCH 15/41] intel: Refactor intel_render_texture()
On Thu, 17 Nov 2011 19:58:42 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
This is in preparation for properly implementing glFramebufferTexture*()
for mipmapped depthstencil textures. The FIXME comments deleted by this
patch give a rough explanation of what was broken.
This refactor does the following:
- In intel_update_wrapper() and intel_wrap_texture(), prepare to
replace the 'att' parameter with a miptree.
- Move the call to intel_renderbuffer_set_draw_offsets() from
intel_render_texture() into intel_udpate_wrapper().
Each time I encounter those functions, I dislike their vague names.
(Update which wrapper? What is wrapped? What is the wrapper?). So, while
I was mucking around, I also renamed the functions.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 113
+++-
1 files changed, 81 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 8e4f7a9..a61c74c 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -945,41 +945,54 @@ intel_framebuffer_renderbuffer(struct gl_context * ctx,
intel_draw_buffer(ctx);
}
+/**
+ * NOTE: The 'att' parameter is a kludge that will soon be removed. Its
+ * presence allows us to refactor the wrapping of depthstencil textures that
+ * use separate stencil in two easily manageable steps, rather than in one
+ * large, hairy step. First, refactor the common wrapping code used by all
+ * texture formats. Second, refactor the separate stencil code paths.
+ */
static bool
-intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
- struct gl_renderbuffer_attachment *att)
+intel_renderbuffer_update_wrapper(struct intel_context *intel,
+ struct intel_renderbuffer *irb,
+ struct intel_mipmap_tree *mt,
+ uint32_t level,
+ uint32_t layer,
+ GLenum internal_format,
+ struct gl_renderbuffer_attachment *att)
{
+ struct gl_context *ctx = intel-ctx;
+ struct gl_renderbuffer *rb = irb-Base;
+
+ /* The image variables are a kludge. See the note above for the att
+* parameter.
+*/
struct gl_texture_image *texImage = _mesa_get_attachment_teximage(att);
struct intel_texture_image *intel_image = intel_texture_image(texImage);
- int width, height, depth;
- if (!intel_span_supports_format(texImage-TexFormat)) {
+ irb-Base.Format = ctx-Driver.ChooseTextureFormat(ctx, internal_format,
+ GL_NONE, GL_NONE);
+
+ if (!intel_span_supports_format(rb-Format)) {
DBG(Render to texture BAD FORMAT %s\n,
- _mesa_get_format_name(texImage-TexFormat));
+ _mesa_get_format_name(rb-Format));
return false;
} else {
- DBG(Render to texture %s\n,
_mesa_get_format_name(texImage-TexFormat));
+ DBG(Render to texture %s\n, _mesa_get_format_name(rb-Format));
}
- intel_miptree_get_dimensions_for_image(texImage, width, height, depth);
-
- irb-Base.Format = texImage-TexFormat;
- irb-Base.DataType =
intel_mesa_format_to_rb_datatype(texImage-TexFormat);
- irb-Base.InternalFormat = texImage-InternalFormat;
- irb-Base._BaseFormat = _mesa_base_tex_format(ctx,
irb-Base.InternalFormat);
- irb-Base.Width = width;
- irb-Base.Height = height;
+ rb-InternalFormat = internal_format;
+ rb-DataType = intel_mesa_format_to_rb_datatype(rb-Format);
+ rb-_BaseFormat = _mesa_get_format_base_format(rb-Format);
+ rb-Width = mt-level[level].width;
+ rb-Height = mt-level[level].height;
irb-Base.Delete = intel_delete_renderbuffer;
irb-Base.AllocStorage = intel_nop_alloc_storage;
- irb-mt_level = att-TextureLevel;
- if (att-CubeMapFace 0) {
- assert(att-Zoffset == 0);
- irb-mt_layer = att-CubeMapFace;
- } else {
- irb-mt_layer= att-Zoffset;
- }
+ intel_miptree_check_level_layer(mt, level, layer);
+ irb-mt_level = level;
+ irb-mt_layer = layer;
if (intel_image-stencil_rb) {
/* The tex image has packed depth/stencil format, but is using
separate
@@ -1002,29 +1015,46 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
depth_irb = intel_renderbuffer(intel_image-depth_rb);
depth_irb-mt_level = irb-mt_level;
depth_irb-mt_layer = irb-mt_layer;
+ intel_renderbuffer_set_draw_offset(depth_irb);
stencil_irb = intel_renderbuffer(intel_image-stencil_rb);
stencil_irb-mt_level = irb-mt_level;
stencil_irb-mt_layer = irb-mt_layer;
+ intel_renderbuffer_set_draw_offset(stencil_irb);
}
Re: [Mesa-dev] [PATCH] Allow glTexImage2D with a depth component cube map
On 11/16/2011 07:56 PM, Anuj Phogat wrote:
From: Anuj Phogatanuj.pho...@gmail.com
Hi,
Here is a patch to allow glTexImage2D and glCopyTexImage2D with depth component
cubemap.
It is listed in mesa work queue with a label CUBE1. I've tested the patch and
output looks visually correct.
Please review the fix and let me know if i'm missing something.
Thanks
Anuj
---
src/mesa/main/teximage.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index acf7187..81f75c8 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1596,7 +1596,7 @@ texture_error_check( struct gl_context *ctx,
/* additional checks for depth textures */
if (_mesa_base_tex_format(ctx, internalFormat) == GL_DEPTH_COMPONENT) {
- /* Only 1D, 2D, rect and array textures supported, not 3D or cubes */
+ /* Only 1D, 2D, rect, array and cube textures are supported, not 3D*/
if (target != GL_TEXTURE_1D
target != GL_PROXY_TEXTURE_1D
target != GL_TEXTURE_2D
@@ -1606,7 +1606,13 @@ texture_error_check( struct gl_context *ctx,
target != GL_TEXTURE_2D_ARRAY
target != GL_PROXY_TEXTURE_2D_ARRAY
target != GL_TEXTURE_RECTANGLE_ARB
- target != GL_PROXY_TEXTURE_RECTANGLE_ARB) {
+ target != GL_PROXY_TEXTURE_RECTANGLE_ARB
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_X
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_X
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_Y
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_Y
+ target != GL_TEXTURE_CUBE_MAP_POSITIVE_Z
+ target != GL_TEXTURE_CUBE_MAP_NEGATIVE_Z) {
The cubemap targets are only valid in OpenGL 3.0 (or later) or when
GL_EXT_gpu_shader4 is available. Also, GL_PROXY_TEXTURE_CUBE_MAP is
missing.
if (!isProxy)
_mesa_error(ctx, GL_INVALID_ENUM,
glTexImage(target/internalFormat));
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Re: [Mesa-dev] [PATCH 16/41] intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt
On Thu, 17 Nov 2011 19:58:43 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 116 +++--
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 134
+++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 37 +++
src/mesa/drivers/dri/intel/intel_tex.c | 41 +++-
src/mesa/drivers/dri/intel/intel_tex_image.c | 128 --
src/mesa/drivers/dri/intel/intel_tex_obj.h | 30 --
6 files changed, 248 insertions(+), 238 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index a61c74c..7dc0c53 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
#ifdef I915
(void) intel;
if (intel-is_945)
@@ -103,6 +116,23 @@ intel_miptree_create_internal(struct intel_context
*intel,
brw_miptree_layout(intel, mt);
#endif
+ if (intel-has_separate_stencil
+ _mesa_is_depthstencil_format(_mesa_get_format_base_format(format))) {
Shouldn't this be must_have_separate_stencil until patch 39/41?
+ mt-stencil_mt = intel_miptree_create(intel,
+mt-target,
+MESA_FORMAT_S8,
+mt-first_level,
+mt-last_level,
+mt-width0,
+mt-height0,
+mt-depth0,
+true);
+ if (!mt-stencil_mt) {
+ intel_miptree_release(mt);
+ return NULL;
+ }
+ }
+
return mt;
}
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Re: [Mesa-dev] [PATCH 16/41] intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 03:19 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:43 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 116 +++--
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 134
+++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 37 +++
src/mesa/drivers/dri/intel/intel_tex.c | 41 +++-
src/mesa/drivers/dri/intel/intel_tex_image.c | 128 --
src/mesa/drivers/dri/intel/intel_tex_obj.h | 30 --
6 files changed, 248 insertions(+), 238 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index a61c74c..7dc0c53 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
#ifdef I915
(void) intel;
if (intel-is_945)
@@ -103,6 +116,23 @@ intel_miptree_create_internal(struct intel_context
*intel,
brw_miptree_layout(intel, mt);
#endif
+ if (intel-has_separate_stencil
+ _mesa_is_depthstencil_format(_mesa_get_format_base_format(format))) {
Shouldn't this be must_have_separate_stencil until patch 39/41?
You're correct. Thanks for the sharp eye. I'll fix that in the final patch.
-
Chad Versace
chad.vers...@linux.intel.com
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Re: [Mesa-dev] [PATCH 17/41] intel: Replace intel_mipmap_tree::hiz_region with a miptree
On Thu, 17 Nov 2011 19:58:44 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++--
src/mesa/drivers/dri/intel/intel_context.c | 20 ++--
src/mesa/drivers/dri/intel/intel_fbo.c | 11 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 19 ++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 22 +-
5 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 4119afa..17da460 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1394,17 +1394,17 @@
intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
buffer-pitch / buffer-cpp,
buffer-name,
buffer_name);
-
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);
+ intel_region_release(region);
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-mt-hiz_region, region);
+ rb-mt-hiz_mt = mt;
} else {
- rb-mt = intel_miptree_create_for_region(intel,
- GL_TEXTURE_2D,
- rb-Base.Format,
- region);;
+ rb-mt = mt;
}
I don't see who would have already released preexisting rb-mt here.
+bool
+intel_miptree_alloc_hiz(struct intel_context *intel,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt-hiz_mt == NULL);
+ mt-hiz_mt = intel_miptree_create(intel,
+ mt-target,
+ MESA_FORMAT_X8_Z24,
+ mt-first_level,
+ mt-last_level,
+ mt-width0,
+ mt-height0,
+ mt-depth0,
+ true);
+ return mt-hiz_mt != NULL;
+}
We don't get any size reduction on the hiz miptree compared to the real
miptree?
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Re: [Mesa-dev] [PATCH 20/41] intel: Define struct intel_resolve_map
On Thu, 17 Nov 2011 19:58:47 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
This is a map of miptree slices to needed resolves, implemented as
a linked list. A future commit will embed such a list in
intel_mipmap_tree.
If you think I'm crazy to put a list in a miptree, read the Doxygen in
this patch for intel_resolve_map.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/Makefile.sources |1 +
src/mesa/drivers/dri/i965/intel_resolve_map.c |1 +
src/mesa/drivers/dri/intel/intel_resolve_map.c | 95 +++
src/mesa/drivers/dri/intel/intel_resolve_map.h | 99
4 files changed, 196 insertions(+), 0 deletions(-)
create mode 12 src/mesa/drivers/dri/i965/intel_resolve_map.c
create mode 100644 src/mesa/drivers/dri/intel/intel_resolve_map.c
create mode 100644 src/mesa/drivers/dri/intel/intel_resolve_map.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 1b9ca6f..cd6a8f4 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -15,6 +15,7 @@ i965_C_SOURCES := \
intel_fbo.c \
intel_mipmap_tree.c \
intel_regions.c \
+ intel_resolve_map.c \
intel_screen.c \
intel_span.c \
intel_pixel.c \
diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.c
b/src/mesa/drivers/dri/i965/intel_resolve_map.c
new file mode 12
index 000..77e50fb
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_resolve_map.c
@@ -0,0 +1 @@
+../intel/intel_resolve_map.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_resolve_map.c
b/src/mesa/drivers/dri/intel/intel_resolve_map.c
new file mode 100644
index 000..d2af262
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_resolve_map.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include intel_resolve_map.h
+
+#include assert.h
+#include stdlib.h
+
+void
+intel_resolve_map_set(struct intel_resolve_map *head,
+ uint32_t level,
+ uint32_t layer,
+ enum intel_need_resolve need)
+{
+ struct intel_resolve_map **tail = head-next;
+ struct intel_resolve_map *prev = head;
+
+ while (*tail) {
+ if ((*tail)-level == level (*tail)-layer == layer) {
+ assert((*tail)-need == need);
+ return;
+ }
+ prev = *tail;
+ tail = (*tail)-next;
+ }
+
+ *tail = malloc(sizeof(**tail));
+ (*tail)-prev = prev;
+ (*tail)-next = NULL;
+ (*tail)-level = level;
+ (*tail)-layer = layer;
+ (*tail)-need = need;
+}
+
+struct intel_resolve_map*
+intel_resolve_map_get(struct intel_resolve_map *head,
+ uint32_t level,
+ uint32_t layer)
+{
+ struct intel_resolve_map *item = head-next;
+
+ while (item) {
+ if (item-level == level item-layer == layer)
+ break;
+ else
+ item = item-next;
+ }
+
+ return item;
+}
+
+void
+intel_resolve_map_remove(struct intel_resolve_map *elem)
+{
+ if (elem-prev)
+ elem-prev-next = elem-next;
+ if (elem-next)
+ elem-next-prev = elem-prev;
+ free(elem);
+}
+
+void
+intel_resolve_map_clear(struct intel_resolve_map *head)
+{
+ struct intel_resolve_map *next = head-next;
+ struct intel_resolve_map *trash;
+
+ while (next) {
+ trash = next;
+ next = next-next;
+ free(trash);
+ }
+
+ head-next = NULL;
+}
diff --git a/src/mesa/drivers/dri/intel/intel_resolve_map.h
b/src/mesa/drivers/dri/intel/intel_resolve_map.h
new file mode 100644
index 000..d665ecb
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_resolve_map.h
@@ -0,0 +1,99 @@
Re: [Mesa-dev] [PATCH 17/41] intel: Replace intel_mipmap_tree::hiz_region with a miptree
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 03:24 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:44 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++--
src/mesa/drivers/dri/intel/intel_context.c | 20 ++--
src/mesa/drivers/dri/intel/intel_fbo.c | 11 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 19 ++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 22 +-
5 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 4119afa..17da460 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1394,17 +1394,17 @@
intel_process_dri2_buffer_with_separate_stencil(struct intel_context *intel,
buffer-pitch / buffer-cpp,
buffer-name,
buffer_name);
-
+ struct intel_mipmap_tree *mt =
+ intel_miptree_create_for_region(intel,
+ GL_TEXTURE_2D,
+ rb-Base.Format,
+ region);
+ intel_region_release(region);
if (buffer-attachment == __DRI_BUFFER_HIZ) {
- intel_region_reference(rb-mt-hiz_region, region);
+ rb-mt-hiz_mt = mt;
} else {
- rb-mt = intel_miptree_create_for_region(intel,
- GL_TEXTURE_2D,
- rb-Base.Format,
- region);;
+ rb-mt = mt;
}
I don't see who would have already released preexisting rb-mt here.
Fixed that in v2 of this patch, in response to your refcount comments
on the earlier patch.
+bool
+intel_miptree_alloc_hiz(struct intel_context *intel,
+struct intel_mipmap_tree *mt)
+{
+ assert(mt-hiz_mt == NULL);
+ mt-hiz_mt = intel_miptree_create(intel,
+ mt-target,
+ MESA_FORMAT_X8_Z24,
+ mt-first_level,
+ mt-last_level,
+ mt-width0,
+ mt-height0,
+ mt-depth0,
+ true);
+ return mt-hiz_mt != NULL;
+}
We don't get any size reduction on the hiz miptree compared to the real
miptree?
Yes and no.
No, because we always set LOD=0 and manually compute the draw offsets in
the SURFACE_STATE batch. The HiZ and stencil buffers inherit the draw
offset from 3DSTATE_DEPTH_BUFFER, so the HiZ and stencil miptree must have
identical layout to the depth miptree.
To save memory, we could waiver the identical-layout requirement and allocate
a small hiz and stencil miptrees for non-texture renderbuffers, since the draw
offsets will never be used in that case. But let's save that optimization for
a future patch.
Yes, we could allocate small hiz and stencil miptrees if (and that's a big if)
we used the LOD field in SURFACE_STATE. The hardware expects compact miptree
layout in that case.
An additional reason that we may want start using the LOD field is that, when
wrapping a renderbuffer around mipmapped or multi-layer depthstencil textures,
the stencil miptree layout will always be incorrect in the current way we do
things. We should discuss that problem f2f someday.
-
Chad Versace
chad.vers...@linux.intel.com
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Re: [Mesa-dev] [PATCH 10/41] intel: Refactor intel_miptree_copy_teximage()
On 11/17/2011 07:58 PM, Chad Versace wrote:
Extract the body of the inner loop into a new function,
intel_miptree_copy_slice().
This is in preparation for adding support for separate stencil and HiZ to
intel_miptree_copy_teximage(). When copying a slice of a depthstencil
miptree that uses separate stencil, we will also need to copy the
corresponding slice of the stencil miptree. The easiest way to do this
will be to call intel_miptree_copy_slice() recursively. Analogous
reasoning applies to copying a slice of a depth miptree with HiZ.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 122
+---
1 files changed, 66 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 7f9e606..8f10101 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -354,6 +354,69 @@ intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt,
}
}
+static void
+intel_miptree_copy_slice(struct intel_context *intel,
+ struct intel_mipmap_tree *dst_mt,
+ struct intel_mipmap_tree *src_mt,
+ int level,
+ int face,
+ int depth)
+
+{
+ gl_format format = src_mt-format;
+ uint32_t width = src_mt-level[level].width;
+ uint32_t height = src_mt-level[level].height;
+
+ assert(depth src_mt-level[level].depth);
+
+ if (dst_mt-compressed) {
+ uint32_t align_w, align_h;
+ intel_get_texture_alignment_unit(format,
+align_w, align_h);
+ height = ALIGN(height, align_h) / align_h;
+ width = ALIGN(width, align_w);
+ }
This wasn't originally inside the loop; you've effectively moved it
there. Since intel_get_texture_alignment_unit actually does some work
these days, I'm wondering if this could be a performance hit.
At any rate, it doesn't seem necessary...I'd probably just add
height/width function parameters and move this hunk back.
+ uint32_t dst_x, dst_y, src_x, src_y;
+ intel_miptree_get_image_offset(dst_mt, level, face, depth,
+ dst_x, dst_y);
+ intel_miptree_get_image_offset(src_mt, level, face, depth,
+ src_x, src_y);
+
+ DBG(validate blit mt %p %d,%d/%d - mt %p %d,%d/%d (%dx%d)\n,
+ src_mt, src_x, src_y, src_mt-region-pitch * src_mt-region-cpp,
+ dst_mt, dst_x, dst_y, dst_mt-region-pitch * dst_mt-region-cpp,
+ width, height);
+
+ if (!intelEmitCopyBlit(intel,
+ dst_mt-region-cpp,
+ src_mt-region-pitch, src_mt-region-bo,
+ 0, src_mt-region-tiling,
+ dst_mt-region-pitch, dst_mt-region-bo,
+ 0, dst_mt-region-tiling,
+ src_x, src_y,
+ dst_x, dst_y,
+ width, height,
+ GL_COPY)) {
+
+ fallback_debug(miptree validate blit for %s failed\n,
+ _mesa_get_format_name(format));
+ void *dst = intel_region_map(intel, dst_mt-region, GL_MAP_WRITE_BIT);
+ void *src = intel_region_map(intel, src_mt-region, GL_MAP_READ_BIT);
+
+ _mesa_copy_rect(dst,
+ dst_mt-cpp,
+ dst_mt-region-pitch,
+ dst_x, dst_y,
+ width, height,
+ src, src_mt-region-pitch,
+ src_x, src_y);
+
+ intel_region_unmap(intel, dst_mt-region);
+ intel_region_unmap(intel, src_mt-region);
+ }
+}
+
/**
* Copies the image's current data to the given miptree, and associates that
* miptree with the image.
@@ -366,65 +429,12 @@ intel_miptree_copy_teximage(struct intel_context *intel,
struct intel_mipmap_tree *src_mt = intelImage-mt;
int level = intelImage-base.Base.Level;
int face = intelImage-base.Base.Face;
- GLuint width = src_mt-level[level].width;
- GLuint height = src_mt-level[level].height;
GLuint depth = src_mt-level[level].depth;
- int slice;
- void *src, *dst;
-
- if (dst_mt-compressed) {
- unsigned int align_w, align_h;
- intel_get_texture_alignment_unit(intelImage-base.Base.TexFormat,
-align_w, align_h);
- height = ALIGN(height, align_h) / align_h;
- width = ALIGN(width, align_w);
- }
-
- for (slice = 0; slice depth; slice++) {
- unsigned int dst_x, dst_y, src_x, src_y;
-
- intel_miptree_get_image_offset(dst_mt, level, face, slice,
- dst_x, dst_y);
-
- /* Copy potentially with the blitter:
- */
- intel_miptree_get_image_offset(src_mt, level, face, slice,
-
Re: [Mesa-dev] [PATCH 20/41] intel: Define struct intel_resolve_map
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 03:27 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:47 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
This is a map of miptree slices to needed resolves, implemented as
a linked list. A future commit will embed such a list in
intel_mipmap_tree.
If you think I'm crazy to put a list in a miptree, read the Doxygen in
this patch for intel_resolve_map.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/Makefile.sources |1 +
src/mesa/drivers/dri/i965/intel_resolve_map.c |1 +
src/mesa/drivers/dri/intel/intel_resolve_map.c | 95
+++
src/mesa/drivers/dri/intel/intel_resolve_map.h | 99
4 files changed, 196 insertions(+), 0 deletions(-)
create mode 12 src/mesa/drivers/dri/i965/intel_resolve_map.c
create mode 100644 src/mesa/drivers/dri/intel/intel_resolve_map.c
create mode 100644 src/mesa/drivers/dri/intel/intel_resolve_map.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 1b9ca6f..cd6a8f4 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -15,6 +15,7 @@ i965_C_SOURCES := \
intel_fbo.c \
intel_mipmap_tree.c \
intel_regions.c \
+intel_resolve_map.c \
intel_screen.c \
intel_span.c \
intel_pixel.c \
diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.c
b/src/mesa/drivers/dri/i965/intel_resolve_map.c
new file mode 12
index 000..77e50fb
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_resolve_map.c
@@ -0,0 +1 @@
+../intel/intel_resolve_map.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_resolve_map.c
b/src/mesa/drivers/dri/intel/intel_resolve_map.c
new file mode 100644
index 000..d2af262
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_resolve_map.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include intel_resolve_map.h
+
+#include assert.h
+#include stdlib.h
+
+void
+intel_resolve_map_set(struct intel_resolve_map *head,
+ uint32_t level,
+ uint32_t layer,
+ enum intel_need_resolve need)
+{
+ struct intel_resolve_map **tail = head-next;
+ struct intel_resolve_map *prev = head;
+
+ while (*tail) {
+ if ((*tail)-level == level (*tail)-layer == layer) {
+ assert((*tail)-need == need);
+ return;
+ }
+ prev = *tail;
+ tail = (*tail)-next;
+ }
+
+ *tail = malloc(sizeof(**tail));
+ (*tail)-prev = prev;
+ (*tail)-next = NULL;
+ (*tail)-level = level;
+ (*tail)-layer = layer;
+ (*tail)-need = need;
+}
+
+struct intel_resolve_map*
+intel_resolve_map_get(struct intel_resolve_map *head,
+ uint32_t level,
+ uint32_t layer)
+{
+ struct intel_resolve_map *item = head-next;
+
+ while (item) {
+ if (item-level == level item-layer == layer)
+ break;
+ else
+ item = item-next;
+ }
+
+ return item;
+}
+
+void
+intel_resolve_map_remove(struct intel_resolve_map *elem)
+{
+ if (elem-prev)
+ elem-prev-next = elem-next;
+ if (elem-next)
+ elem-next-prev = elem-prev;
+ free(elem);
+}
+
+void
+intel_resolve_map_clear(struct intel_resolve_map *head)
+{
+ struct intel_resolve_map *next = head-next;
+ struct intel_resolve_map *trash;
+
+ while (next) {
+ trash = next;
+ next = next-next;
+ free(trash);
+ }
+
+ head-next = NULL;
+}
diff --git a/src/mesa/drivers/dri/intel/intel_resolve_map.h
b/src/mesa/drivers/dri/intel/intel_resolve_map.h
new file mode 100644
index 000..d665ecb
---
Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images [v2]
On 11/18/2011 01:52 PM, Chad Versace wrote:
[snip]
@@ -335,23 +338,18 @@ intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt,
GLuint level, GLuint face, GLuint depth,
GLuint *x, GLuint *y)
{
- switch (mt-target) {
- case GL_TEXTURE_CUBE_MAP_ARB:
- *x = mt-level[level].slice[face].x_offset;
- *y = mt-level[level].slice[face].y_offset;
- break;
- case GL_TEXTURE_3D:
- case GL_TEXTURE_2D_ARRAY_EXT:
- case GL_TEXTURE_1D_ARRAY_EXT:
- assert(depth mt-level[level].nr_images);
- *x = mt-level[level].slice[depth].x_offset;
- *y = mt-level[level].slice[depth].y_offset;
- break;
- default:
- *x = mt-level[level].slice[0].x_offset;
- *y = mt-level[level].slice[0].y_offset;
- break;
+ int slice;
+
+ if (face 0) {
+ assert(face 6);
+ assert(depth == 0);
+ slice = face;
+ } else {
+ slice = depth;
}
I find the face 0 check confusing. For cube face 0, you're falling
through to the array case and relying the fact that depth == 0 for
cubemaps. Yes, it works, but...bizarre.
You're also relying on depth == 0 for non-cube/non-array cases, but that
seems entirely reasonable to me.
Perhaps just change the (face 0) check to (mt-target ==
GL_TEXTURE_CUBE_MAP)? That seems clear enough.
Technically you could just drop the changes in this function (they're
not necessary), but I do like the cleanup.
+ *x = mt-level[level].slice[slice].x_offset;
+ *y = mt-level[level].slice[slice].y_offset;
}
static void
@@ -429,7 +427,7 @@ intel_miptree_copy_teximage(struct intel_context *intel,
struct intel_mipmap_tree *src_mt = intelImage-mt;
int level = intelImage-base.Base.Level;
int face = intelImage-base.Base.Face;
- GLuint depth = src_mt-level[level].depth;
+ GLuint depth = intelImage-base.Base.Depth;
for (int slice = 0; slice depth; slice++) {
intel_miptree_copy_slice(intel, dst_mt, src_mt, level, face, slice);
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 2cad793..8f024f9 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -69,16 +69,25 @@ struct intel_mipmap_level
GLuint level_y;
GLuint width;
GLuint height;
- /** Depth of the mipmap at this level: 1 for 1D/2D/CUBE, n for 3D. */
+
+ /**
+* \brief Number of 2D slices in this miplevel.
+*
+* The exact semantics of depth varies according to the texture target:
+*- For GL_TEXTURE_CUBE_MAP, depth is 6.
+*- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It
is
+* identical for all miplevels in the texture.
+*- For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
+* value, like width and height, varies with miplevel.
+*- For other texture types, depth is 1.
+*/
GLuint depth;
- /** Number of images at this level: 1 for 1D/2D, 6 for CUBE, depth for 3D
*/
- GLuint nr_images;
/**
* \brief List of 2D images in this mipmap level.
*
* This may be a list of cube faces, array slices in 2D array texture, or
-* layers in a 3D texture. The list's length is \c nr_images.
+* layers in a 3D texture. The list's length is \c depth.
*/
struct intel_mipmap_slice {
/**
@@ -205,7 +214,6 @@ intel_miptree_get_dimensions_for_image(struct
gl_texture_image *image,
void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
GLuint level,
- GLuint nr_images,
GLuint x, GLuint y,
GLuint w, GLuint h, GLuint d);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c
b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 64f4a70..e6324cf 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -50,7 +50,7 @@ intel_get_texture_alignment_unit(gl_format format,
}
}
-void i945_miptree_layout_2d(struct intel_mipmap_tree *mt, int nr_images)
+void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
{
GLuint align_h, align_w;
GLuint level;
@@ -93,7 +93,7 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt,
int nr_images)
for ( level = mt-first_level ; level = mt-last_level ; level++ ) {
GLuint img_height;
- intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
+ intel_miptree_set_level_info(mt, level, x, y, width,
height, depth);
img_height = ALIGN(height, align_h);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h
b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index 257c07c..c6c865d 100644
---
Re: [Mesa-dev] [PATCH 26/41] i965/gen6: Manipulate state batches for HiZ meta-ops
On Thu, 17 Nov 2011 19:58:53 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c |9 -
src/mesa/drivers/dri/i965/gen6_clip_state.c | 17 +
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 22 --
src/mesa/drivers/dri/i965/gen6_sf_state.c | 15 +--
src/mesa/drivers/dri/i965/gen6_wm_state.c | 17 +
5 files changed, 75 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 1571fb7..d2ae087 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -117,10 +117,17 @@ static void brw_set_prim(struct brw_context *brw,
static void gen6_set_prim(struct brw_context *brw,
const struct _mesa_prim *prim)
{
- uint32_t hw_prim = prim_to_hw_prim[prim-mode];
+ uint32_t hw_prim;
DBG(PRIM: %s\n, _mesa_lookup_enum_by_nr(prim-mode));
+ if (brw-hiz.op) {
+ assert(prim-mode == GL_TRIANGLES);
+ hw_prim = _3DPRIM_RECTLIST;
+ } else {
+ hw_prim = prim_to_hw_prim[prim-mode];
+ }
+
if (hw_prim != brw-primitive) {
brw-primitive = hw_prim;
brw-state.dirty.brw |= BRW_NEW_PRIMITIVE;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 72e8687..4eb2012 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -77,10 +77,28 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
}
/* _NEW_DEPTH */
- if (ctx-Depth.Test) {
- ds-ds2.depth_test_enable = 1;
+ if (ctx-Depth.Test || brw-hiz.op) {
ds-ds2.depth_test_func =
intel_translate_compare_func(ctx-Depth.Func);
ds-ds2.depth_write_enable = ctx-Depth.Mask;
+
+ /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
+ * - 7.5.3.1 Depth Buffer Clear
+ * - 7.5.3.2 Depth Buffer Resolve
+ * - 7.5.3.3 Hierarchical Depth Buffer Resolve
+ */
+ switch (brw-hiz.op) {
+ case BRW_HIZ_OP_NONE:
+ case BRW_HIZ_OP_DEPTH_RESOLVE:
+ ds-ds2.depth_test_enable = 1;
+ break;
+ case BRW_HIZ_OP_DEPTH_CLEAR:
+ case BRW_HIZ_OP_HIZ_RESOLVE:
+ ds-ds2.depth_test_enable = 0;
+ break;
+ default:
+ assert(0);
+ break;
+ }
The meta-op should just always set depth test appropriately instead of
adding this hunk, I think. It already does in one case.
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Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images
On Fri, 18 Nov 2011 13:36:25 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 12:22 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:38 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. It's
value, like width and height, varies with miplevel.
Its
I'll fix the two It's.
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
The changes in this file don't seem to fit in this patch.
Oops. These hunks are complete mistake. I assume they were introduced by a
rebase.
They will be removed.
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index f4c1a68..8dad011 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -140,12 +140,13 @@ intel_tex_map_image_for_swrast(struct intel_context
*intel,
if (mt-target == GL_TEXTURE_3D ||
mt-target == GL_TEXTURE_2D_ARRAY ||
mt-target == GL_TEXTURE_1D_ARRAY) {
- int i;
/* ImageOffsets[] is only used for swrast's fetch_texel_3d, so we
can't
* share code with the normal path.
*/
- for (i = 0; i mt-level[level].depth; i++) {
+ assert(face == 0);
+ int depth = mt-level[level].depth;
+ for (int i = 0; i depth; i++) {
intel_miptree_get_image_offset(mt, level, face, i, x, y);
intel_image-base.ImageOffsets[i] = x + y * mt-region-pitch;
}
Not really seeing the point of this hunk (pulling depth out of the loop)
This is really a sloppy commit. There is no need for this hunk either.
Other than the spurious hunks, are you ok with this patch?
Yeah, r-b other than that.
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Re: [Mesa-dev] [PATCH 12/41] intel: Track the miptree layer wrapped by a renderbuffer
On 11/17/2011 07:58 PM, Chad Versace wrote:
Add two fields to intel_renderbuffer:
mt_level
mt_layer
Multiple renderbuffers may simultaneously wrap a single texture and each
provide a different view into that texture. [Consider
glFramebufferTextureLayer()]. The new fields indicate which slice of the
miptree is wrapped by the renderbuffer.
The buffer resolve operations, to be introduced in the future, require
these fields in order to resolve the correct slice in the miptree.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 24
src/mesa/drivers/dri/intel/intel_fbo.h | 17 +
2 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 8c41956..ed58078 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -973,15 +973,39 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
irb-Base.Delete = intel_delete_renderbuffer;
irb-Base.AllocStorage = intel_nop_alloc_storage;
+ irb-mt_level = att-TextureLevel;
+ if (att-CubeMapFace 0) {
+ assert(att-Zoffset == 0);
+ irb-mt_layer = att-CubeMapFace;
+ } else {
+ irb-mt_layer= att-Zoffset;
+ }
Ditto...relying on the unclear property that att-Zoffset == 0 when
att-CubeMapFace == 0. Maybe att-Texture-Target ==
GL_TEXTURE_CUBE_MAP? (Hopefully att-Texture is guaranteed to be !=
NULL...)
+
if (intel_image-stencil_rb) {
/* The tex image has packed depth/stencil format, but is using
separate
* stencil. It shares its embedded depth and stencil renderbuffers
with
* the renderbuffer wrapper.
+ *
+ * FIXME: glFramebufferTexture*() is broken for depthstencil textures
+ * FIXME: with separate stencil. To fix this, we must create a
separate
+ * FIXME: pair of depth/stencil renderbuffers for each attached slice
+ * FIXME: of the miptree.
*/
+ struct intel_renderbuffer *depth_irb;
+ struct intel_renderbuffer *stencil_irb;
+
_mesa_reference_renderbuffer(irb-wrapped_depth,
intel_image-depth_rb);
_mesa_reference_renderbuffer(irb-wrapped_stencil,
intel_image-stencil_rb);
+
+ depth_irb = intel_renderbuffer(intel_image-depth_rb);
+ depth_irb-mt_level = irb-mt_level;
+ depth_irb-mt_layer = irb-mt_layer;
+
+ stencil_irb = intel_renderbuffer(intel_image-stencil_rb);
+ stencil_irb-mt_level = irb-mt_level;
+ stencil_irb-mt_layer = irb-mt_layer;
} else {
intel_miptree_reference(irb-mt, intel_image-mt);
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index 34d2f9a..3a21374 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -52,6 +52,23 @@ struct intel_renderbuffer
GLbitfield map_mode;
/**
+* \name Miptree view
+* \{
+*
+* Multiple renderbuffers may simultaneously wrap a single texture and
each
+* provide a different view into that texture. The fields below indicate
+* which miptree slice is wrapped by this renderbuffer. The fields'
values
+* are consistent with the 'level' and 'layer' parameters of
+* glFramebufferTextureLayer().
+*
+* For renderbuffers not created with glFramebufferTexture*(), mt_level
and
+* mt_layer are 0.
+*/
+ unsigned int mt_level;
+ unsigned int mt_layer;
+ /** \} */
+
+ /**
* \name Packed depth/stencil unwrappers
*
* If the intel_context is using separate stencil and this renderbuffer
has
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Re: [Mesa-dev] [PATCH 10/41] intel: Refactor intel_miptree_copy_teximage()
On 11/18/2011 03:42 PM, Kenneth Graunke wrote:
On 11/17/2011 07:58 PM, Chad Versace wrote:
Extract the body of the inner loop into a new function,
intel_miptree_copy_slice().
This is in preparation for adding support for separate stencil and HiZ to
intel_miptree_copy_teximage(). When copying a slice of a depthstencil
miptree that uses separate stencil, we will also need to copy the
corresponding slice of the stencil miptree. The easiest way to do this
will be to call intel_miptree_copy_slice() recursively. Analogous
reasoning applies to copying a slice of a depth miptree with HiZ.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 122
+---
1 files changed, 66 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 7f9e606..8f10101 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -354,6 +354,69 @@ intel_miptree_get_image_offset(struct intel_mipmap_tree
*mt,
}
}
+static void
+intel_miptree_copy_slice(struct intel_context *intel,
+ struct intel_mipmap_tree *dst_mt,
+ struct intel_mipmap_tree *src_mt,
+ int level,
+ int face,
+ int depth)
+
+{
+ gl_format format = src_mt-format;
+ uint32_t width = src_mt-level[level].width;
+ uint32_t height = src_mt-level[level].height;
+
+ assert(depth src_mt-level[level].depth);
+
+ if (dst_mt-compressed) {
+ uint32_t align_w, align_h;
+ intel_get_texture_alignment_unit(format,
+ align_w, align_h);
+ height = ALIGN(height, align_h) / align_h;
+ width = ALIGN(width, align_w);
+ }
This wasn't originally inside the loop; you've effectively moved it
there. Since intel_get_texture_alignment_unit actually does some work
these days, I'm wondering if this could be a performance hit.
Patch 36/41 Store miptree alignment units in the miptree remove this call
intel_get_texture_alignment_unit(). Does that solve your performance fear?
At any rate, it doesn't seem necessary...I'd probably just add
height/width function parameters and move this hunk back.
It feels really strange to me to pass width and height parameters
into intel_miptree_copy_slice(). I imagine someone in the future
encountering the function and being puzzled: The slice specifier
(level, face, depth) is already passed into intel_miptree_copy_slice().
The width and height are determined by the slice, so why are width and height
also passed? Are we perhaps not copying the entire slice? I'd rather not
make a potentially confusing design choice for the sake of a potential
performance penalty that will be rendered moot in a future commit.
Chad Versace
chad.vers...@linux.intel.com
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Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images [v2]
On Fri, 18 Nov 2011 13:52:32 -0800, a...@anholt.net wrote: From: Chad Versace chad.vers...@linux.intel.com For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and 'depth' fields of intel_mipmap_level were identical. In the exceptional case, nr_images == 6 and depth == 1. It is simple to determine if a texture is a cube or not, so the presence of two fields here was not helpful. Worse, it was confusing. When we eventually implement GL_ARB_texture_cube_map_array, this mess would have become even more confusing. This patch removes 'nr_images' and assigns to 'depth' a consistent meaning: depth is the number of 2D slices at each miplevel. The exact semantics of depth varies according to the texture target: - For GL_TEXTURE_CUBE_MAP, depth is 6. - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is identical for all miplevels in the texture. - For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its value, like width and height, varies with miplevel. - For other texture types, depth is 1. As a consequence, parameters were removed from the following function signatures: intel_miptree_set_level_info Remove 'nr_images'. i945_miptree_layout brw_miptree_layout_texture brw_miptree_layout_texture_array Remove 'slices'. v2: - Replace It's with Its. - Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked in during a rebase. - Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was a little refactor of the for-loop's upper bound. Reviewed-by: Eric Anholt e...@anholt.net pgpolKLWqgNvV.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/41] intel: Refactor intel_miptree_copy_teximage()
On 11/18/2011 04:04 PM, Chad Versace wrote:
On 11/18/2011 03:42 PM, Kenneth Graunke wrote:
On 11/17/2011 07:58 PM, Chad Versace wrote:
Extract the body of the inner loop into a new function,
intel_miptree_copy_slice().
This is in preparation for adding support for separate stencil and HiZ to
intel_miptree_copy_teximage(). When copying a slice of a depthstencil
miptree that uses separate stencil, we will also need to copy the
corresponding slice of the stencil miptree. The easiest way to do this
will be to call intel_miptree_copy_slice() recursively. Analogous
reasoning applies to copying a slice of a depth miptree with HiZ.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 122
+---
1 files changed, 66 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 7f9e606..8f10101 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -354,6 +354,69 @@ intel_miptree_get_image_offset(struct
intel_mipmap_tree *mt,
}
}
+static void
+intel_miptree_copy_slice(struct intel_context *intel,
+struct intel_mipmap_tree *dst_mt,
+struct intel_mipmap_tree *src_mt,
+int level,
+int face,
+int depth)
+
+{
+ gl_format format = src_mt-format;
+ uint32_t width = src_mt-level[level].width;
+ uint32_t height = src_mt-level[level].height;
+
+ assert(depth src_mt-level[level].depth);
+
+ if (dst_mt-compressed) {
+ uint32_t align_w, align_h;
+ intel_get_texture_alignment_unit(format,
+ align_w, align_h);
+ height = ALIGN(height, align_h) / align_h;
+ width = ALIGN(width, align_w);
+ }
This wasn't originally inside the loop; you've effectively moved it
there. Since intel_get_texture_alignment_unit actually does some work
these days, I'm wondering if this could be a performance hit.
Patch 36/41 Store miptree alignment units in the miptree remove this call
intel_get_texture_alignment_unit(). Does that solve your performance fear?
Oh... :) *approval*
For both patches (10 and 36):
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
I definitely like storing the values in the miptree itself.
At any rate, it doesn't seem necessary...I'd probably just add
height/width function parameters and move this hunk back.
It feels really strange to me to pass width and height parameters
into intel_miptree_copy_slice(). I imagine someone in the future
encountering the function and being puzzled: The slice specifier
(level, face, depth) is already passed into intel_miptree_copy_slice().
The width and height are determined by the slice, so why are width and height
also passed? Are we perhaps not copying the entire slice? I'd rather not
make a potentially confusing design choice for the sake of a potential
performance penalty that will be rendered moot in a future commit.
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Re: [Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images [v2]
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 03:55 PM, Kenneth Graunke wrote:
On 11/18/2011 01:52 PM, Chad Versace wrote:
[snip]
@@ -335,23 +338,18 @@ intel_miptree_get_image_offset(struct
intel_mipmap_tree *mt,
GLuint level, GLuint face, GLuint depth,
GLuint *x, GLuint *y)
{
- switch (mt-target) {
- case GL_TEXTURE_CUBE_MAP_ARB:
- *x = mt-level[level].slice[face].x_offset;
- *y = mt-level[level].slice[face].y_offset;
- break;
- case GL_TEXTURE_3D:
- case GL_TEXTURE_2D_ARRAY_EXT:
- case GL_TEXTURE_1D_ARRAY_EXT:
- assert(depth mt-level[level].nr_images);
- *x = mt-level[level].slice[depth].x_offset;
- *y = mt-level[level].slice[depth].y_offset;
- break;
- default:
- *x = mt-level[level].slice[0].x_offset;
- *y = mt-level[level].slice[0].y_offset;
- break;
+ int slice;
+
+ if (face 0) {
+ assert(face 6);
+ assert(depth == 0);
+ slice = face;
+ } else {
+ slice = depth;
}
I find the face 0 check confusing. For cube face 0, you're falling
through to the array case and relying the fact that depth == 0 for
cubemaps. Yes, it works, but...bizarre.
You're also relying on depth == 0 for non-cube/non-array cases, but that
seems entirely reasonable to me.
Perhaps just change the (face 0) check to (mt-target ==
GL_TEXTURE_CUBE_MAP)? That seems clear enough.
If it looks bizarre to you, it will likely look bizarre to others too. I dislike
bizarre code, so I'll change this with your (mt-target = GL_TEXTURE_CUBE_MAP)
suggestion.
Technically you could just drop the changes in this function (they're
not necessary), but I do like the cleanup.
True that it's not really needed. I cleaned it up because it seemed that
the old code did a lot of special-casing for no good reason.
-
Chad Versace
chad.vers...@linux.intel.com
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[Mesa-dev] [PATCH] intel: Kill intel_mipmap_level::nr_images [v3]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace It's with Its.
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v3:
- [kwg] In intel_miptree_get_image_offset(), replace bizarre `face 0`
condition with the more sensible `mt-target == GL_TEXTURE_CUBE_MAP`.
Reviewed-by: Eric Anholt e...@anholt.net
CC: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 17 -
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 45 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 18 +++---
src/mesa/drivers/dri/intel/intel_tex_layout.c |4 +-
src/mesa/drivers/dri/intel/intel_tex_layout.h |3 +-
src/mesa/drivers/dri/intel/intel_tex_validate.c |2 +-
6 files changed, 47 insertions(+), 42 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index d77bf4d..ac6ade6 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -41,8 +41,7 @@
static void
brw_miptree_layout_texture_array(struct intel_context *intel,
-struct intel_mipmap_tree *mt,
-int slices)
+struct intel_mipmap_tree *mt)
{
GLuint align_w;
GLuint align_h;
@@ -58,14 +57,14 @@ brw_miptree_layout_texture_array(struct intel_context
*intel,
if (mt-compressed)
qpitch /= 4;
- i945_miptree_layout_2d(mt, slices);
+ i945_miptree_layout_2d(mt);
for (level = mt-first_level; level = mt-last_level; level++) {
- for (q = 0; q slices; q++) {
+ for (q = 0; q mt-depth0; q++) {
intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
}
}
- mt-total_height = qpitch * slices;
+ mt-total_height = qpitch * mt-depth0;
}
void
@@ -82,7 +81,7 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
* pitch of qpitch rows, where qpitch is defined by the equation given
* in Volume 1 of the BSpec.
*/
-brw_miptree_layout_texture_array(intel, mt, 6);
+brw_miptree_layout_texture_array(intel, mt);
break;
}
/* FALLTHROUGH */
@@ -117,7 +116,7 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
GLint y = 0;
GLint q, j;
-intel_miptree_set_level_info(mt, level, nr_images,
+intel_miptree_set_level_info(mt, level,
0, mt-total_height,
width, height, depth);
@@ -170,11 +169,11 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_1D_ARRAY:
- brw_miptree_layout_texture_array(intel, mt, mt-depth0);
+ brw_miptree_layout_texture_array(intel, mt);
break;
default:
- i945_miptree_layout_2d(mt, 1);
+ i945_miptree_layout_2d(mt);
break;
}
DBG(%s: %dx%dx%d\n, __FUNCTION__,
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 8f10101..bc9469b 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -82,11 +82,17 @@ intel_miptree_create_internal(struct intel_context *intel,
mt-last_level = last_level;
mt-width0 = width0;
mt-height0 = height0;
- mt-depth0 = depth0;
mt-cpp = compress_byte ? compress_byte :
_mesa_get_format_bytes(mt-format);
Re: [Mesa-dev] [PATCH 17/41] intel: Replace intel_mipmap_tree::hiz_region with a miptree
On Fri, 18 Nov 2011 15:41:04 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 11/18/2011 03:24 PM, Eric Anholt wrote:
On Thu, 17 Nov 2011 19:58:44 -0800, Chad Versace
chad.vers...@linux.intel.com wrote:
+bool
+intel_miptree_alloc_hiz(struct intel_context *intel,
+ struct intel_mipmap_tree *mt)
+{
+ assert(mt-hiz_mt == NULL);
+ mt-hiz_mt = intel_miptree_create(intel,
+ mt-target,
+ MESA_FORMAT_X8_Z24,
+ mt-first_level,
+ mt-last_level,
+ mt-width0,
+ mt-height0,
+ mt-depth0,
+ true);
+ return mt-hiz_mt != NULL;
+}
We don't get any size reduction on the hiz miptree compared to the real
miptree?
Yes and no.
No, because we always set LOD=0 and manually compute the draw offsets in
the SURFACE_STATE batch. The HiZ and stencil buffers inherit the draw
offset from 3DSTATE_DEPTH_BUFFER, so the HiZ and stencil miptree must have
identical layout to the depth miptree.
To save memory, we could waiver the identical-layout requirement and allocate
a small hiz and stencil miptrees for non-texture renderbuffers, since the draw
offsets will never be used in that case. But let's save that optimization for
a future patch.
Yes, we could allocate small hiz and stencil miptrees if (and that's a big if)
we used the LOD field in SURFACE_STATE. The hardware expects compact miptree
layout in that case.
Good enough answer for me.
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[Mesa-dev] [PATCH 1/3] mesa: define, use _mesa_is_cube_face() in several places
---
src/mesa/main/fbobject.c| 10 +-
src/mesa/main/texgetimage.c |9 -
src/mesa/main/teximage.c|9 +++--
src/mesa/main/teximage.h| 10 ++
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index f8b148c..5b329f5 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -78,14 +78,6 @@ static struct gl_renderbuffer DummyRenderbuffer;
static struct gl_framebuffer IncompleteFramebuffer;
-static inline GLboolean
-is_cube_face(GLenum target)
-{
- return (target = GL_TEXTURE_CUBE_MAP_POSITIVE_X
- target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z);
-}
-
-
/**
* Is the given FBO a user-created FBO?
*/
@@ -2008,7 +2000,7 @@ framebuffer_texture(struct gl_context *ctx, const char
*caller, GLenum target,
}
else {
err = (texObj-Target == GL_TEXTURE_CUBE_MAP)
-? !is_cube_face(textarget)
+? !_mesa_is_cube_face(textarget)
: (texObj-Target != textarget);
}
}
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index 31d49f2..0650659 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -386,11 +386,10 @@ get_tex_memcpy(struct gl_context *ctx, GLenum format,
GLenum type,
* so we don't have to worry about those.
* XXX more format combinations could be supported here.
*/
- if ((target == GL_TEXTURE_1D ||
-target == GL_TEXTURE_2D ||
-target == GL_TEXTURE_RECTANGLE ||
-(target = GL_TEXTURE_CUBE_MAP_POSITIVE_X
- target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z))) {
+ if (target == GL_TEXTURE_1D ||
+ target == GL_TEXTURE_2D ||
+ target == GL_TEXTURE_RECTANGLE ||
+ _mesa_is_cube_face(target)) {
if ((texImage-TexFormat == MESA_FORMAT_ARGB ||
texImage-TexFormat == MESA_FORMAT_SARGB8)
format == GL_BGRA
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index a84d687..c8ea432 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -522,8 +522,7 @@ _mesa_base_tex_format( struct gl_context *ctx, GLint
internalFormat )
GLuint
_mesa_tex_target_to_face(GLenum target)
{
- if (target = GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
- target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB)
+ if (_mesa_is_cube_face(target))
return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
else
return 0;
@@ -3094,8 +3093,7 @@ compressed_texture_error_check(struct gl_context *ctx,
GLint dimensions,
}
/* For cube map, width must equal height */
- if (target = GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
- target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB width != height) {
+ if (_mesa_is_cube_face(target) width != height) {
*reason = width != height;
return GL_INVALID_VALUE;
}
@@ -3183,8 +3181,7 @@ compressed_subtexture_error_check(struct gl_context *ctx,
GLint dimensions,
return GL_INVALID_ENUM; /*target*/
maxLevels = ctx-Const.MaxCubeTextureLevels;
}
- else if (target = GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
- target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB) {
+ else if (_mesa_is_cube_face(target)) {
if (!ctx-Extensions.ARB_texture_cube_map)
return GL_INVALID_ENUM; /*target*/
maxLevels = ctx-Const.MaxCubeTextureLevels;
diff --git a/src/mesa/main/teximage.h b/src/mesa/main/teximage.h
index fd315be..9cc7d5a 100644
--- a/src/mesa/main/teximage.h
+++ b/src/mesa/main/teximage.h
@@ -36,6 +36,16 @@
#include formats.h
+/** Is the given value one of the 6 cube faces? */
+static inline GLboolean
+_mesa_is_cube_face(GLenum target)
+{
+ return (target = GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB
+ target = GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB);
+}
+
+
+
/** \name Internal functions */
/*@{*/
--
1.7.3.4
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[Mesa-dev] [PATCH 2/3] mesa: make slow_read_rgba_pixels() a void function
The boolean return value was ignored by the caller. --- src/mesa/main/readpix.c |4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c index 86b8753..aa893de 100644 --- a/src/mesa/main/readpix.c +++ b/src/mesa/main/readpix.c @@ -224,7 +224,7 @@ fast_read_rgba_pixels_memcpy( struct gl_context *ctx, return GL_TRUE; } -static GLboolean +static void slow_read_rgba_pixels( struct gl_context *ctx, GLint x, GLint y, GLsizei width, GLsizei height, @@ -263,8 +263,6 @@ slow_read_rgba_pixels( struct gl_context *ctx, } ctx-Driver.UnmapRenderbuffer(ctx, rb); - - return GL_TRUE; } /* -- 1.7.3.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
On Fri, 18 Nov 2011 12:58:43 -0800, Chad Versace chad.vers...@linux.intel.com wrote: This is required to correctly implement HiZ for mipmapped and multi-layered textures. v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were introduced in v2 of commit intel: Replace intel_renderbuffer::region with a miptree [v2] CC: Eric Anholt eric@anholt Signed-off-by: Chad Versace chad.vers...@linux.intel.com Reviewed-by: Eric Anholt e...@anholt.net pgpmzMSSvySHM.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] mesa: handle MapRenderbuffer() failures in glReadPixels
---
src/mesa/main/readpix.c | 45 +
1 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index aa893de..8048a72 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -70,6 +70,11 @@ fast_read_depth_pixels( struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return GL_TRUE; /* don't bother trying the slow path */
+ }
+
dstStride = _mesa_image_row_stride(packing, width, GL_DEPTH_COMPONENT,
type);
dst = (GLubyte *) _mesa_image_address2d(packing, pixels, width, height,
GL_DEPTH_COMPONENT, type, 0, 0);
@@ -126,6 +131,10 @@ read_depth_pixels( struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return;
+ }
/* General case (slower) */
for (j = 0; j height; j++, y++) {
@@ -165,6 +174,10 @@ read_stencil_pixels( struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return;
+ }
/* process image row by row */
for (j = 0; j height; j++) {
@@ -211,6 +224,10 @@ fast_read_rgba_pixels_memcpy( struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return GL_TRUE; /* don't bother trying the slow path */
+ }
texelBytes = _mesa_get_format_bytes(rb-Format);
for (j = 0; j height; j++) {
@@ -248,6 +265,10 @@ slow_read_rgba_pixels( struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return;
+ }
for (j = 0; j height; j++) {
if (_mesa_is_integer_format(format)) {
@@ -325,6 +346,10 @@ fast_read_depth_stencil_pixels(struct gl_context *ctx,
ctx-Driver.MapRenderbuffer(ctx, rb, x, y, width, height, GL_MAP_READ_BIT,
map, stride);
+ if (!map) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return GL_TRUE; /* don't bother trying the slow path */
+ }
for (i = 0; i height; i++) {
_mesa_unpack_uint_24_8_depth_stencil_row(rb-Format, width,
@@ -361,8 +386,18 @@ fast_read_depth_stencil_pixels_separate(struct gl_context
*ctx,
ctx-Driver.MapRenderbuffer(ctx, depthRb, x, y, width, height,
GL_MAP_READ_BIT, depthMap, depthStride);
+ if (!depthMap) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return GL_TRUE; /* don't bother trying the slow path */
+ }
+
ctx-Driver.MapRenderbuffer(ctx, stencilRb, x, y, width, height,
GL_MAP_READ_BIT, stencilMap, stencilStride);
+ if (!stencilMap) {
+ ctx-Driver.UnmapRenderbuffer(ctx, depthRb);
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return GL_TRUE; /* don't bother trying the slow path */
+ }
for (j = 0; j height; j++) {
GLubyte stencilVals[MAX_WIDTH];
@@ -405,10 +440,20 @@ slow_read_depth_stencil_pixels_separate(struct gl_context
*ctx,
*/
ctx-Driver.MapRenderbuffer(ctx, depthRb, x, y, width, height,
GL_MAP_READ_BIT, depthMap, depthStride);
+ if (!depthMap) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return;
+ }
+
if (stencilRb != depthRb) {
ctx-Driver.MapRenderbuffer(ctx, stencilRb, x, y, width, height,
GL_MAP_READ_BIT, stencilMap,
stencilStride);
+ if (!stencilMap) {
+ ctx-Driver.UnmapRenderbuffer(ctx, depthRb);
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, glReadPixels);
+ return;
+ }
}
else {
stencilMap = depthMap;
--
1.7.3.4
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Re: [Mesa-dev] [PATCH] intel: Kill intel_mipmap_level::nr_images [v3]
On 11/18/2011 04:19 PM, Chad Versace wrote: For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and 'depth' fields of intel_mipmap_level were identical. In the exceptional case, nr_images == 6 and depth == 1. It is simple to determine if a texture is a cube or not, so the presence of two fields here was not helpful. Worse, it was confusing. When we eventually implement GL_ARB_texture_cube_map_array, this mess would have become even more confusing. This patch removes 'nr_images' and assigns to 'depth' a consistent meaning: depth is the number of 2D slices at each miplevel. The exact semantics of depth varies according to the texture target: - For GL_TEXTURE_CUBE_MAP, depth is 6. - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is identical for all miplevels in the texture. - For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its value, like width and height, varies with miplevel. - For other texture types, depth is 1. As a consequence, parameters were removed from the following function signatures: intel_miptree_set_level_info Remove 'nr_images'. i945_miptree_layout brw_miptree_layout_texture brw_miptree_layout_texture_array Remove 'slices'. v2: - Replace It's with Its. - Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked in during a rebase. - Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was a little refactor of the for-loop's upper bound. v3: - [kwg] In intel_miptree_get_image_offset(), replace bizarre `face 0` condition with the more sensible `mt-target == GL_TEXTURE_CUBE_MAP`. Great. Thanks Chad. Reviewed-by: Kenneth Graunke kenn...@whitecape.org ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] intel: Track the miptree layer wrapped by a renderbuffer [v2]
Add two fields to intel_renderbuffer:
mt_level
mt_layer
Multiple renderbuffers may simultaneously wrap a single texture and each
provide a different view into that texture. [Consider
glFramebufferTextureLayer()]. The new fields indicate which slice of the
miptree is wrapped by the renderbuffer.
The buffer resolve operations, to be introduced in the future, require
these fields in order to resolve the correct slice in the miptree.
v2:
- [kwg] Replace bizarre condition `CubeMapFace 0` with the more
sensible `Target == GL_TEXTURE_CUBE_MAP`.
CC: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 37 +++
src/mesa/drivers/dri/intel/intel_fbo.h | 17 ++
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 30a42ba..ef74647 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -948,8 +948,9 @@ intel_framebuffer_renderbuffer(struct gl_context * ctx,
static bool
intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb,
-struct gl_texture_image *texImage)
+struct gl_renderbuffer_attachment *att)
{
+ struct gl_texture_image *texImage = _mesa_get_attachment_teximage(att);
struct intel_texture_image *intel_image = intel_texture_image(texImage);
int width, height, depth;
@@ -973,15 +974,40 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
irb-Base.Delete = intel_delete_renderbuffer;
irb-Base.AllocStorage = intel_nop_alloc_storage;
+ irb-mt_level = att-TextureLevel;
+ if (texImage-TexObject-Target == GL_TEXTURE_CUBE_MAP) {
+ assert(att-Zoffset == 0);
+ irb-mt_layer = att-CubeMapFace;
+ } else {
+ assert(att-CubeMapFace == 0);
+ irb-mt_layer= att-Zoffset;
+ }
+
if (intel_image-stencil_rb) {
/* The tex image has packed depth/stencil format, but is using separate
* stencil. It shares its embedded depth and stencil renderbuffers with
* the renderbuffer wrapper.
+ *
+ * FIXME: glFramebufferTexture*() is broken for depthstencil textures
+ * FIXME: with separate stencil. To fix this, we must create a separate
+ * FIXME: pair of depth/stencil renderbuffers for each attached slice
+ * FIXME: of the miptree.
*/
+ struct intel_renderbuffer *depth_irb;
+ struct intel_renderbuffer *stencil_irb;
+
_mesa_reference_renderbuffer(irb-wrapped_depth,
intel_image-depth_rb);
_mesa_reference_renderbuffer(irb-wrapped_stencil,
intel_image-stencil_rb);
+
+ depth_irb = intel_renderbuffer(intel_image-depth_rb);
+ depth_irb-mt_level = irb-mt_level;
+ depth_irb-mt_layer = irb-mt_layer;
+
+ stencil_irb = intel_renderbuffer(intel_image-stencil_rb);
+ stencil_irb-mt_level = irb-mt_level;
+ stencil_irb-mt_layer = irb-mt_layer;
} else {
intel_miptree_reference(irb-mt, intel_image-mt);
}
@@ -994,7 +1020,8 @@ intel_update_wrapper(struct gl_context *ctx, struct
intel_renderbuffer *irb,
* This will have the region info needed for hardware rendering.
*/
static struct intel_renderbuffer *
-intel_wrap_texture(struct gl_context * ctx, struct gl_texture_image *texImage)
+intel_wrap_texture(struct gl_context * ctx,
+ struct gl_renderbuffer_attachment *att)
{
const GLuint name = ~0; /* not significant, but distinct for debugging */
struct intel_renderbuffer *irb;
@@ -1009,7 +1036,7 @@ intel_wrap_texture(struct gl_context * ctx, struct
gl_texture_image *texImage)
_mesa_init_renderbuffer(irb-Base, name);
irb-Base.ClassID = INTEL_RB_CLASS;
- if (!intel_update_wrapper(ctx, irb, texImage)) {
+ if (!intel_update_wrapper(ctx, irb, att)) {
free(irb);
return NULL;
}
@@ -1114,7 +1141,7 @@ intel_render_texture(struct gl_context * ctx,
return;
}
else if (!irb) {
- irb = intel_wrap_texture(ctx, image);
+ irb = intel_wrap_texture(ctx, att);
if (irb) {
/* bind the wrapper to the attachment point */
_mesa_reference_renderbuffer(att-Renderbuffer, irb-Base);
@@ -1126,7 +1153,7 @@ intel_render_texture(struct gl_context * ctx,
}
}
- if (!intel_update_wrapper(ctx, irb, image)) {
+ if (!intel_update_wrapper(ctx, irb, att)) {
_mesa_reference_renderbuffer(att-Renderbuffer, NULL);
_swrast_render_texture(ctx, fb, att);
return;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index 34d2f9a..3a21374 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -52,6
Re: [Mesa-dev] [PATCH] intel: Track the miptree layer wrapped by a renderbuffer [v2]
On 11/18/2011 04:51 PM, Chad Versace wrote: Add two fields to intel_renderbuffer: mt_level mt_layer Multiple renderbuffers may simultaneously wrap a single texture and each provide a different view into that texture. [Consider glFramebufferTextureLayer()]. The new fields indicate which slice of the miptree is wrapped by the renderbuffer. The buffer resolve operations, to be introduced in the future, require these fields in order to resolve the correct slice in the miptree. v2: - [kwg] Replace bizarre condition `CubeMapFace 0` with the more sensible `Target == GL_TEXTURE_CUBE_MAP`. CC: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com Reviewed-by: Kenneth Graunke kenn...@whitecape.org ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] mesa: define, use _mesa_is_cube_face() in several places
On 11/18/2011 04:39 PM, Brian Paul wrote: --- src/mesa/main/fbobject.c| 10 +- src/mesa/main/texgetimage.c |9 - src/mesa/main/teximage.c|9 +++-- src/mesa/main/teximage.h| 10 ++ 4 files changed, 18 insertions(+), 20 deletions(-) For the series: Reviewed-by: Kenneth Graunke kenn...@whitecape.org ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] intel: Replace intel_renderbuffer::region with a miptree [v2]
On Fri, 18 Nov 2011 12:50:36 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
Essentially, this patch just globally substitutes `irb-region` with
`irb-mt-region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
@@ -702,20 +696,21 @@ intel_alloc_renderbuffer_storage(struct gl_context *
ctx, struct gl_renderbuffer
_mesa_reference_renderbuffer(irb-wrapped_stencil, stencil_rb);
} else {
- irb-region = intel_region_alloc(intel-intelScreen, tiling, cpp,
-width, height, true);
- if (!irb-region)
+ irb-mt = intel_miptree_create_for_renderbuffer(intel, rb-Format,
+ tiling, cpp,
+ width, height);
+ if (!irb-mt)
return false;
if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
- irb-hiz_region = intel_region_alloc(intel-intelScreen,
- I915_TILING_Y,
- irb-region-cpp,
- irb-region-width,
- irb-region-height,
- true);
- if (!irb-hiz_region) {
- intel_region_release(irb-region);
+ irb-mt-hiz_region = intel_region_alloc(intel-intelScreen,
+ I915_TILING_Y,
+ cpp,
+ rb-Width,
+ rb-Height,
+ true);
+ if (!irb-mt) {
+ intel_miptree_release(irb-mt);
return false;
I think this was meant to be if (!irb-mt-his_region).
Other than that,
Reviewed-by: Eric Anholt e...@anholt.net
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Re: [Mesa-dev] [PATCH 27/41] i965: Prevent recursive calls to FLUSH_VERTICES
On Thu, 17 Nov 2011 19:58:54 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
To do so, we must resolve all buffers on entering a glBegin/glEnd block.
For the detailed explanation, see the Doxygen comments in this patch.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.c | 73
+++
1 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 9b506a6..4d51e62 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -33,11 +33,23 @@
#include main/imports.h
#include main/macros.h
#include main/simple_list.h
+
+#include vbo/vbo_context.h
+
#include brw_context.h
#include brw_defines.h
#include brw_draw.h
#include brw_state.h
+
+#include gen6_hiz.h
+
+#include intel_fbo.h
+#include intel_mipmap_tree.h
+#include intel_regions.h
#include intel_span.h
+#include intel_tex.h
+#include intel_tex_obj.h
+
#include tnl/t_pipeline.h
#include glsl/ralloc.h
@@ -45,12 +57,73 @@
* Mesa's Driver Functions
***/
+/**
+ * \brief Prepare for entry into glBegin/glEnd block.
+ *
+ * Resolve all buffers before entering a glBegin/glEnd block. This is
+ * necessary to prevent recursive calls to FLUSH_VERTICES.
+ *
+ * Details
+ * ---
+ * When vertices are queued during a glBegin/glEnd block, those vertices must
+ * be drawn before any rendering state changes. To enusure this, Mesa calls
ensure
+ * FLUSH_VERTICES as a prehook to such state changes. Therefore,
+ * FLUSH_VERTICES itself cannot change rendering state without falling into a
+ * recursive trap.
+ *
+ * This precludes meta-ops, namely buffer resolves, from occuring while any
+ * vertices are queued. To prevent that situation, we resolve all buffers on
+ * entering a glBegin/glEnd
+ *
+ * \see brwCleanupExecEnd()
+ */
+static void brwPrepareExecBegin(struct gl_context *ctx)
+{
+ struct brw_context *brw = brw_context(ctx);
+ struct intel_context *intel = brw-intel;
+ struct intel_renderbuffer *draw_irb;
+ struct intel_renderbuffer *read_irb;
+ struct intel_texture_object *tex_obj;
+
+ if (!intel-has_hiz) {
+ /* The context uses no feature that requires buffer resolves. */
+ return;
+ }
+
+ /* Resolve each enabled texture. */
+ for (int i = 0; i ctx-Const.MaxTextureImageUnits; i++) {
+ if (!ctx-Texture.Unit[i]._ReallyEnabled)
+ continue;
+ tex_obj = intel_texture_object(ctx-Texture.Unit[i]._Current);
+ if (!tex_obj || !tex_obj-mt)
+ continue;
+ intel_miptree_all_slices_resolve_hiz(intel, tex_obj-mt);
+ intel_miptree_all_slices_resolve_depth(intel, tex_obj-mt);
+ }
+
+ /* Resolve each attached depth buffer. */
+ draw_irb = intel_get_renderbuffer(ctx-DrawBuffer, BUFFER_DEPTH);
+ read_irb = intel_get_renderbuffer(ctx-ReadBuffer, BUFFER_DEPTH);
+
+ if (draw_irb) {
+ intel_renderbuffer_resolve_hiz(intel, draw_irb);
+ intel_renderbuffer_resolve_depth(intel, draw_irb);
+ }
+
+ if (read_irb != draw_irb read_irb) {
+ intel_renderbuffer_resolve_hiz(intel, read_irb);
+ intel_renderbuffer_resolve_depth(intel, read_irb);
+ }
I find it odd that this is doing a larger set of resolves than the
brw_predraw_resolve_buffers in the next patch. Actually, it seems like
this ought to be just brw_predraw_resolve_buffers, since you're trying
to just get that function's work done before getting any begin/end
vertices queued up, right?
All previous uncommented-by-me patches are r-b.
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Re: [Mesa-dev] [PATCH 32/41] intel: Mark needed resolves when first enabling HiZ on a miptree
On Thu, 17 Nov 2011 19:58:59 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 21 -
1 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 3540997..9ebeefc 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -584,7 +584,26 @@ intel_miptree_alloc_hiz(struct intel_context *intel,
mt-height0,
mt-depth0,
true);
- return mt-hiz_mt != NULL;
+
+ if (!mt-hiz_mt)
+ return false;
+
+ /* Mark that all slices need a HiZ resolve. */
+ struct intel_resolve_map *head = mt-hiz_map;
+ for (int level = mt-first_level; level = mt-last_level; ++level) {
+ for (int layer = 0; layer mt-level[level].depth; ++layer) {
+ head-next = malloc(sizeof(*head-next));
+ head-next-prev = head;
+ head-next-next = NULL;
+ head = head-next;
+
+ head-level = level;
+ head-layer = layer;
+ head-need = INTEL_NEED_HIZ_RESOLVE;
+ }
+ }
I'm not convinced that this patch is required.
If we have just allocated our storage, the contents are undefined. If
someone kicks things off by doing a glClear()-like operation on it, then
the no-resolve-needed initial state would be correct, since the hiz
buffer would get made consistent value at that point. If someone loads
it up with depth image data, that should set a NEED_HIZ_RESOLVE at the
MapTextureImage/MapRenderbuffer time. If someone does rendering that
isn't a clear operation, they've got undefined results outside of where
they drew (as expected), and undefined results where they drew if they
had some non-always/never depth test associated.
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Re: [Mesa-dev] [PATCH 35/41] intel: Enable HiZ for texture renderbuffers
On Thu, 17 Nov 2011 19:59:02 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
When a depth texture is first attached to framebuffer, allocate a HiZ
miptree for it.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 0b6b227..1842925 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -1040,6 +1040,13 @@ intel_renderbuffer_update_wrapper(struct intel_context
*intel,
} else {
intel_miptree_reference(irb-mt, mt);
intel_renderbuffer_set_draw_offset(irb);
+
+ if (mt-hiz_mt == NULL
+ intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
+ intel_miptree_alloc_hiz(intel, mt);
+ if (!mt-hiz_mt)
+return false;
+ }
Aha! Here's the reason you needed that initialize the hiz resolves
patch in intel_miptree_alloc_hiz. Now that one makes sense to me --
previously, intel_miptree_alloc_hiz was only called on uninitialized
storage. We can separate that out later, since it's just optimization.
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Re: [Mesa-dev] [PATCH 26/41] i965/gen6: Manipulate state batches for HiZ meta-ops
On Thu, 17 Nov 2011 19:58:53 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c |9 -
src/mesa/drivers/dri/i965/gen6_clip_state.c | 17 +
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 22 --
src/mesa/drivers/dri/i965/gen6_sf_state.c | 15 +--
src/mesa/drivers/dri/i965/gen6_wm_state.c | 17 +
5 files changed, 75 insertions(+), 5 deletions(-)
+ if (brw-hiz.op) {
+ /* HiZ operations emit a rectangle primitive, which requires clipping
to
+ * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
+ * Section 1.3 3D Primitives Overview:
+ *RECTLIST:
+ *Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
+ *Mode should be set to a value other than CLIPMODE_NORMAL.
+ */
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_CLIP 16 | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ return;
+ }
+
if (!ctx-Transform.DepthClamp)
depth_clamp = GEN6_CLIP_Z_TEST;
This test for brw-hiz.op should have some sort of state flag associated
with it in the brw_tracked_state struct. Otherwise, you have no
guarantee that your upload function will get called. Same goes for
other upload functions touched in this patch.
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Re: [Mesa-dev] [PATCH 37/41] i965: Set vertical alignment in SURFACE_STATE batch
On Thu, 17 Nov 2011 19:59:04 -0800, Chad Versace chad.vers...@linux.intel.com wrote: Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_defines.h |9 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c |8 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) Side note: not necessarily for this series, but gen7 needs the same treatment, right? pgp5Kuyg2sbZC.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] mesa: Make formats.c datatype values match glGetTexLevelParameter return.
The formats.c code's datatype value is what does this value mean, i.e. unorm or snorm or float, and is the return value from the GL_TEXTURE_RED_TYPE class of queries. The depth formats were marked as GL_UNSIGNED_INT, which is what we use for integer, and not what we should be returning from the glGetTexLevelParameter. In texstore, we were inappropriately using it as an argument to _mesa_unpack_depth_span() that was expecting a value like GL_UNSIGNED_INT or GL_UNSIGNED_SHORT. Just hardcode _mesa_unpack_depth_span()'s arguments for now, though it looks like the consumers of that interface would be happier with using MESA_FORMAT. --- src/mesa/main/formats.c | 12 ++-- src/mesa/main/readpix.c |4 ++-- src/mesa/main/texstore.c |7 ++- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index c6febb0..b934bd4 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -414,7 +414,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_Z24_S8, /* Name */ MESA_FORMAT_Z24_S8,/* StrName */ GL_DEPTH_STENCIL,/* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 24, 8, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 4 /* BlockWidth/Height,Bytes */ @@ -423,7 +423,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_S8_Z24, /* Name */ MESA_FORMAT_S8_Z24,/* StrName */ GL_DEPTH_STENCIL,/* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 24, 8, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 4 /* BlockWidth/Height,Bytes */ @@ -432,7 +432,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_Z16, /* Name */ MESA_FORMAT_Z16, /* StrName */ GL_DEPTH_COMPONENT, /* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 16, 0, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 2 /* BlockWidth/Height,Bytes */ @@ -441,7 +441,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_X8_Z24, /* Name */ MESA_FORMAT_X8_Z24,/* StrName */ GL_DEPTH_COMPONENT, /* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 24, 0, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 4 /* BlockWidth/Height,Bytes */ @@ -450,7 +450,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_Z24_X8, /* Name */ MESA_FORMAT_Z24_X8,/* StrName */ GL_DEPTH_COMPONENT, /* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 24, 0, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 4 /* BlockWidth/Height,Bytes */ @@ -459,7 +459,7 @@ static struct gl_format_info format_info[MESA_FORMAT_COUNT] = MESA_FORMAT_Z32, /* Name */ MESA_FORMAT_Z32, /* StrName */ GL_DEPTH_COMPONENT, /* BaseFormat */ - GL_UNSIGNED_INT, /* DataType */ + GL_UNSIGNED_NORMALIZED, /* DataType */ 0, 0, 0, 0, /* Red/Green/Blue/AlphaBits */ 0, 0, 0, 32, 0, /* Lum/Int/Index/Depth/StencilBits */ 1, 1, 4 /* BlockWidth/Height,Bytes */ diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c index 86b8753..a459d33 100644 --- a/src/mesa/main/readpix.c +++ b/src/mesa/main/readpix.c @@ -60,7 +60,7 @@ fast_read_depth_pixels( struct gl_context *ctx, if (packing-SwapBytes) return GL_FALSE; - if (_mesa_get_format_datatype(rb-Format) != GL_UNSIGNED_INT) + if (_mesa_get_format_datatype(rb-Format) != GL_UNSIGNED_NORMALIZED) return GL_FALSE; if (!((type == GL_UNSIGNED_SHORT rb-Format == MESA_FORMAT_Z16) || @@ -358,7 +358,7 @@ fast_read_depth_stencil_pixels_separate(struct gl_context *ctx, GLubyte *depthMap, *stencilMap; int depthStride, stencilStride, i, j; - if (_mesa_get_format_datatype(depthRb-Format) != GL_UNSIGNED_INT) + if
Re: [Mesa-dev] [PATCH 41/41] i965: Document where Piglit test glean/fbo breaks due to HiZ
On Thu, 17 Nov 2011 19:59:08 -0800, Chad Versace chad.vers...@linux.intel.com wrote: I found the line of code that breaks the test, but don't know how to easily fix it. Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_context.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 4d51e62..0021eb5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -97,6 +97,9 @@ static void brwPrepareExecBegin(struct gl_context *ctx) tex_obj = intel_texture_object(ctx-Texture.Unit[i]._Current); if (!tex_obj || !tex_obj-mt) continue; + /* FIXME: The hiz resolve here (not the depth resolve) breaks Piglit + * FIXME: test glean/fbo on gen6. + */ intel_miptree_all_slices_resolve_hiz(intel, tex_obj-mt); intel_miptree_all_slices_resolve_depth(intel, tex_obj-mt); } -- 1.7.7.1 I've made it to the end! At this point, I'm up for a known regression to get this giant series landed. Everything without specific comments is now: Reviewed-by: Eric Anholt e...@anholt.net pgpP94SABRw7i.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] mesa: Don't report types for 0-sized components of textures.
The GL_TEXTURE_WHATEVER_SIZE entrypoints were checking if the
specified base type of the texture allowed that channel to be present
before reporting the size of the channel, so that GL_RGB didn't end up
with an alpha size if the hardware driver had to store it that way.
The GL_TEXTURE_WHATEVER_TYPE entrypoints weren't checking it, so you
would end up with strange responses from the GL involving 0-bit
floating-point alpha components in GL_RGB32F, even though it says
GL_NONE as expected for other 0-sized channels.
Make _TYPE check _BaseFormat the same as _SIZE, which results in
fixing most of the GL_RGB* testcases of gl-3.0-required-sized-formats
pass on i965.
---
src/mesa/main/texparam.c | 115 ++
1 files changed, 65 insertions(+), 50 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 17eac5f..89a8fbb 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -884,6 +884,66 @@ _mesa_TexParameterIuiv(GLenum target, GLenum pname, const
GLuint *params)
}
+static GLboolean
+base_format_has_channel(GLenum base_format, GLenum pname)
+{
+ switch (pname) {
+ case GL_TEXTURE_RED_SIZE:
+ case GL_TEXTURE_RED_TYPE:
+ if (base_format == GL_RED ||
+ base_format == GL_RG ||
+ base_format == GL_RGB ||
+ base_format == GL_RGBA) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_GREEN_SIZE:
+ case GL_TEXTURE_GREEN_TYPE:
+ if (base_format == GL_RG ||
+ base_format == GL_RGB ||
+ base_format == GL_RGBA) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_BLUE_SIZE:
+ case GL_TEXTURE_BLUE_TYPE:
+ if (base_format == GL_RGB ||
+ base_format == GL_RGBA) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_ALPHA_SIZE:
+ case GL_TEXTURE_ALPHA_TYPE:
+ if (base_format == GL_RGBA ||
+ base_format == GL_ALPHA ||
+ base_format == GL_LUMINANCE_ALPHA) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_LUMINANCE_SIZE:
+ case GL_TEXTURE_LUMINANCE_TYPE:
+ if (base_format == GL_LUMINANCE ||
+ base_format == GL_LUMINANCE_ALPHA) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_INTENSITY_SIZE:
+ case GL_TEXTURE_INTENSITY_TYPE:
+ if (base_format == GL_INTENSITY) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ case GL_TEXTURE_DEPTH_SIZE:
+ case GL_TEXTURE_DEPTH_TYPE:
+ if (base_format == GL_DEPTH_STENCIL ||
+ base_format == GL_DEPTH_COMPONENT) {
+return GL_TRUE;
+ }
+ return GL_FALSE;
+ }
+
+ return GL_FALSE;
+}
void GLAPIENTRY
@@ -981,27 +1041,10 @@ _mesa_GetTexLevelParameteriv( GLenum target, GLint level,
*params = img-Border;
break;
case GL_TEXTURE_RED_SIZE:
- if (img-_BaseFormat == GL_RED) {
-*params = _mesa_get_format_bits(texFormat, pname);
- break;
-}
-/* FALLTHROUGH */
case GL_TEXTURE_GREEN_SIZE:
- if (img-_BaseFormat == GL_RG) {
-*params = _mesa_get_format_bits(texFormat, pname);
- break;
-}
-/* FALLTHROUGH */
case GL_TEXTURE_BLUE_SIZE:
- if (img-_BaseFormat == GL_RGB || img-_BaseFormat == GL_RGBA)
-*params = _mesa_get_format_bits(texFormat, pname);
- else
-*params = 0;
- break;
case GL_TEXTURE_ALPHA_SIZE:
- if (img-_BaseFormat == GL_ALPHA ||
- img-_BaseFormat == GL_LUMINANCE_ALPHA ||
- img-_BaseFormat == GL_RGBA)
+ if (base_format_has_channel(img-_BaseFormat, pname))
*params = _mesa_get_format_bits(texFormat, pname);
else
*params = 0;
@@ -1067,46 +1110,18 @@ _mesa_GetTexLevelParameteriv( GLenum target, GLint
level,
/* GL_ARB_texture_float */
case GL_TEXTURE_RED_TYPE_ARB:
- if (!ctx-Extensions.ARB_texture_float)
-goto invalid_pname;
- *params = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE) ?
-_mesa_get_format_datatype(texFormat) : GL_NONE;
- break;
case GL_TEXTURE_GREEN_TYPE_ARB:
- if (!ctx-Extensions.ARB_texture_float)
-goto invalid_pname;
- *params = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE) ?
-_mesa_get_format_datatype(texFormat) : GL_NONE;
- break;
case GL_TEXTURE_BLUE_TYPE_ARB:
- if (!ctx-Extensions.ARB_texture_float)
-goto invalid_pname;
- *params = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE) ?
-_mesa_get_format_datatype(texFormat) : GL_NONE;
- break;
case GL_TEXTURE_ALPHA_TYPE_ARB:
- if (!ctx-Extensions.ARB_texture_float)
-goto invalid_pname;
- *params = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE) ?
-
Re: [Mesa-dev] [PATCH 38/41] i965: Implement the actual tables for texture alignment units.
On Thu, 17 Nov 2011 19:59:05 -0800, Chad Versace chad.vers...@linux.intel.com
wrote:
From: Kenneth Graunke kenn...@whitecape.org
I implemented functions for horizontal/vertical alignment units separately
because I find it easier to read that way...especially with all the
corner-cases.
[chad] Cherry picked from
commit 9babf8ae308223e70f7c867076a5d62f2cd70a32
branch valign
git://git.freedesktop.org/~kayden/mesa.git
[chad] Corrected the vertical alignment calculation by checking for
depthstencil formats.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |3 +-
src/mesa/drivers/dri/intel/intel_tex_layout.c | 101
+++-
src/mesa/drivers/dri/intel/intel_tex_layout.h |7 +-
3 files changed, 105 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 17cf50e..af5d393 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -89,7 +89,8 @@ intel_miptree_create_internal(struct intel_context *intel,
mt-compressed = compress_byte ? 1 : 0;
mt-refcount = 1;
- intel_get_texture_alignment_unit(format, mt-align_w, mt-align_h);
+ intel_get_texture_alignment_unit(intel, format,
+ mt-align_w, mt-align_h);
if (target == GL_TEXTURE_CUBE_MAP) {
assert(depth0 == 1);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c
b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index a428d56..8119d30 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -33,10 +33,105 @@
#include intel_mipmap_tree.h
#include intel_tex_layout.h
#include intel_context.h
+
+#include main/image.h
#include main/macros.h
+static unsigned int
+intel_horizontal_texture_alignment_unit(struct intel_context *intel,
+ gl_format format)
+{
+ /**
+* From the Alignment Unit Size section of various specs, namely:
+* - Gen3 Spec: Memory Data Formats Volume, Section 1.20.1.4
+* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
+* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
+* - BSpec (for Ivybridge and slight variations in separate stencil)
+*
+*
+--+
+* || alignment unit height (i)
|
width
+* | Surface Property
|-|
+* || 915 | 965 | ILK | SNB | IVB
|
+*
+--+
+* | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4
|
+* | BC1-5 compressed format (DXTn/S3TC)| 4 | 4 | 4 | 4 | 4
|
+* | FXT1 compressed format| 8 | 8 | 8 | 8 | 8
|
+* | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8
|
+* | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4
|
+* | Separate Stencil Buffer| N/A | N/A | 8 | 8 | 8
|
+* | All Others | 4 | 4 | 4 | 4 | 4
|
+*
+--+
+*
+* On IVB+, non-special cases can be overridden by setting the
SURFACE_STATE
+* Surface Horizontal Alignment field to VALIGN_4 or VALIGN_8.
+*/
HALIGN
+ if (intel-gen = 6
+ (_mesa_is_depth_format(base_format) ||
+ _mesa_is_depthstencil_format(base_format))) {
+ return 4;
+ }
If we're testing the base_format, we only need to check for
GL_DEPTH_COMPONENT or GL_DEPTH_STENCIL. (those functions are for
internalformats, which might have sizes).
+
+ return 2;
+}
+
void
-intel_get_texture_alignment_unit(gl_format format,
+intel_get_texture_alignment_unit(struct intel_context *intel,
+ gl_format format,
unsigned int *w, unsigned int *h)
{
if (_mesa_is_format_compressed(format)) {
@@ -45,8 +140,8 @@ intel_get_texture_alignment_unit(gl_format format,
*/
_mesa_get_format_block_size(format, w, h);
} else {
- *w = 4;
- *h = 2;
+ *w = intel_horizontal_texture_alignment_unit(intel, format);
+ *h = intel_vertical_texture_alignment_unit(intel, format);
}
}
We have a test for _mesa_is_format_compressed here and in the (static,
called-once) functions above. One of the two should probably be
dropped.
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Re: [Mesa-dev] Problem building current git with osmesa and no gallium
On Tue, Nov 15, 2011 at 9:08 PM, Matthew Cattell mcatt...@spamarrest.com wrote: Brian Paul brianp at vmware.com writes: On 03/10/2011 08:30 PM, tom fogal wrote: Kenneth Graunkekenneth at whitecape.org writes: On Thursday, March 10, 2011 01:17:04 PM Alexander Neundorf wrote: While at it (sorry for newbie questions), do I need gallium (maybe swrast) when I want only osmesa rendering into a software buffer ? I don't think OSMesa requires Gallium, but I've never used it. Kenneth's correct. We build OSMesa all the time without gallium. In this case OSMesa uses the swrast driver/backend/whatnot. The 'xlib' driver also uses this backend. I believe there is a way to build both of these on top of softpipe -- the software/reference gallium implementation -- but my project hasn't jumped on that boat yet. Someday. OSMesa doesn't work with gallium yet. I'd like to do that sometime though. llvmpipe would be much faster than swrast in many cases. -Brian Hi, I've been trying to build mesa with the following combination: osmesa llvm egl gles2 (with and without --with-drivers=fbdev,wayland) For fb only, GLES2, swrast EGL, you may try $ ./configure --disable-opengl --enable-gles2 --enable-gallium-egl \ --with-gallium-drivers=swrast --with-egl-platforms=fbdev If you also need OSMesa, this may work $ ./configure --disable-dri --disable-glx --enable-gles2 --enable-osmesa --enable-gallium-egl \ --with-gallium-drivers=swrast --with-egl-platforms=fbdev I do not really try to build. Some of the options may only available on the master branch. I am puzzled about the terminology but when I got my build to succeed, using a sha1 from 14th July 2011, I tried testing it and found that eglInitialize was failing. This was apparently because it couldn't find the display. I am using and X-less environment and want to render directly to fb0 or to some shared memory, hence the inclusion of osmesa. Am I on the right track here? The combinations of autoconf options seem to change a lot and I can't find much in the way of documentation to see which combinations and options are valid and correct for the particular sha1 I'm using. Can you point me in the right direction? Best Regards, Matthew Cattell ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev -- o...@lunarg.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
