Re: [Openocd-development] Amontec - Out of business?
On Fri, 21 Oct 2011 16:10:51 -0600 Ananda Regmi ananda.re...@sandia.aero wrote: Does anybody here know if Amontec - makers of JTAG Tiny - company went out of business or something? [...] Here's the reason I asked. I bought a JTAG tiny from them like 3-4 weeks ago. The payment went through and I haven't heard back from them. I have tried to send multiple emails and I don't get any response back. If they are indeed out of business, I will have to buy another JTAG dongle. But, if they are still in business, I guess I don't have any other option than to warn people to not to deal with them. Well, I will wait for some of you to respond before I do that. Give them some time. I bought a few JTAG Key's from them in the past. And although they are in the same small country, each delivery took 3 weeks or so. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH] Unused variables
On Thu, 20 Oct 2011 07:18:18 +0200 Peter Stuge pe...@stuge.se wrote: You need an OpenID from somewhere (let me know if you want one from me) You need to register on a web page and pick a username You need to set an HTTP password or upload a public SSH key The above takes not two minutes. If you have no idea what OpenID is, have only a basic understanding of git and want to first understand what you are doing to avoid stupid mistakes, then it takes maybe an hour or two to get up and working. But i have to say, comparing patch submission with gerrit and w/o, i think that gerrit is by far superior to anything i've seen until now. Yes, the first patch takes quite a bit of time. But then it's just like pushing patches to an upstream repo. And resubmitting patches is damn easy and patch managment even more so. That said, i like gerrit, but dont underestimate the first hurdle to get it working. Attila Kinali -- The trouble with you, Shev, is you don't say anything until you've saved up a whole truckload of damned heavy brick arguments and then you dump them all out and never look at the bleeding body mangled beneath the heap -- Tirin, The Dispossessed, U. Le Guin ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] Building OpenOCD for Windows
Moin, Could someone give me a pointer on how to build current git HEAD on windows? None of the howtos on the net i've tried worked. Each and everyone failed at some point with errors that are out of my league (linking errors, libtool errors etc). Alternatively, i wouldnt mind if someone could provide me with a binary. I'd pay with swiss chocolate :-) Attila Kinali -- The trouble with you, Shev, is you don't say anything until you've saved up a whole truckload of damned heavy brick arguments and then you dump them all out and never look at the bleeding body mangled beneath the heap -- Tirin, The Dispossessed, U. Le Guin ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] Change in openocd[master]: Add the SAM3N familly to the chip_details table
Attila Kinali has uploaded a new change for review. Change subject: Add the SAM3N familly to the chip_details table .. Add the SAM3N familly to the chip_details table Change-Id: Ic122d324eacf6e667ed6008ebb84708be944222c Signed-off-by: Attila Kinali att...@kinali.ch --- M src/flash/nor/at91sam3.c 1 file changed, 437 insertions(+), 0 deletions(-) git pull ssh://openocd.zylin.com:29418/openocd refs/changes/29/29/1 -- To view, visit http://openocd.zylin.com/29 To unsubscribe, visit http://openocd.zylin.com/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic122d324eacf6e667ed6008ebb84708be944222c Gerrit-PatchSet: 1 Gerrit-Project: openocd Gerrit-Branch: master Gerrit-Owner: Attila Kinali att...@kinali.ch ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] Atmel SAM3N with OpenOCD 0.5.0 (and git HEAD too)
Moin, On Fri, 7 Oct 2011 23:13:19 +0200 Andreas Fritiofson andreas.fritiof...@gmail.com wrote: Well, what's the problem now? It seems to work? Or at least get through init, since post init is printed now, which it wasn't before. Meh! You're right. I confused myself because i forgot to add a shutdown at the end and waited for openocd to stop ^^' Well, we are now a step further. As OpenOCD doesn't know the SAM3N yet, we had to add those to the table. Patch comes in the next mail. Attila Kinali -- The trouble with you, Shev, is you don't say anything until you've saved up a whole truckload of damned heavy brick arguments and then you dump them all out and never look at the bleeding body mangled beneath the heap -- Tirin, The Dispossessed, U. Le Guin ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] [PATCH] Add the SAM3N familly to the chip_details table
Add the SAM3N familly to the chip_details table.
This has been tested with a SAM3N4C chip. The other values are copied
from the datasheet, but have not been tested.
---
src/flash/nor/at91sam3.c | 437 ++
1 files changed, 437 insertions(+), 0 deletions(-)
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 1fe5f62..24de18c 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -73,6 +73,9 @@
// at91sam3s series (has always one flash bank)
#define FLASH_BANK_BASE_S 0x0040
+// at91sam3n series (has always one flash bank)
+#define FLASH_BANK_BASE_N 0x0040
+
#defineAT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash
Descriptor
#defineAT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
#defineAT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page
and Lock
@@ -832,6 +835,440 @@ static const struct sam3_chip_details all_sam3_details[]
= {
},
},
},
+
+ // Start at91sam3n* series
+ {
+ .chipid_cidr= 0x29540960,
+ .name = at91sam3n4c,
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 24 * 1024,
+ .n_gpnvms = 3,
+ .n_banks= 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via SAMBA (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 16,
+ .sector_size = 16384,
+ .page_size = 256,
+ },
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr= 0x29440960,
+ .name = at91sam3n4b,
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 24 * 1024,
+ .n_gpnvms = 3,
+ .n_banks= 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via SAMBA (rom)
+ // else
+ // boot is via FLASH
+ // Selection is via gpnvm[2]
+ // endif
+ //
+ // NOTE: banks 0 1 switch places
+ // if gpnvm[2] == 0
+ // Bank0 is the boot rom
+ // else
+ // Bank1 is the boot rom
+ // endif
+// .bank[0] = {
+ {
+ {
+ .probed = 0,
+ .pChip = NULL,
+ .pBank = NULL,
+ .bank_number = 0,
+ .base_address = FLASH_BANK_BASE_N,
+ .controller_address = 0x400e0A00,
+ .present = 1,
+ .size_bytes = 256 * 1024,
+ .nsectors = 16,
+ .sector_size = 16384,
+ .page_size = 256,
+ },
+
+// .bank[1] = {
+ {
+ .present = 0,
+ .probed = 0,
+ .bank_number = 1,
+ },
+ },
+ },
+
+ {
+ .chipid_cidr= 0x29340960,
+ .name = at91sam3n4a,
+ .total_flash_size = 256 * 1024,
+ .total_sram_size = 24 * 1024,
+ .n_gpnvms = 3,
+ .n_banks= 1,
+
+ // System boots at address 0x0
+ // gpnvm[1] = selects boot code
+ // if gpnvm[1] == 0
+ // boot is via SAMBA (rom)
+ // else
+
Re: [Openocd-development] Atmel SAM3N with OpenOCD 0.5.0 (and git HEAD too)
On Thu, 6 Oct 2011 23:07:44 +0200 Andreas Fritiofson andreas.fritiof...@gmail.com wrote: That log doesn't show that OpenOCD hangs after accessing flash. The Flash bank access DONE part is wrong, the flash bank has only been set up in OpenOCD, there hasn't been any communication with the target yet. Oops, ok a misinterpretation on my side. It obviously hangs during init, which could mean just about anything. It's impossible to tell without a debug log (-d3). I strippped the script down to what is needed. And get the following output, using current git master/HEAD: ---schnipp--- # src/openocd -f /tmp/armusbocd.script Open On-Chip Debugger 0.6.0-dev-00090-gda8ce5f (2011-10-07-14:09) Licensed under GNU GPL v2 For bug reports, read http://openocd.berlios.de/doc/doxygen/bugs.html Info : only one transport option; autoselect 'jtag' 15 kHz trst_only separate trst_push_pull target created Flash bank access DONE Info : clock speed 15 kHz Info : JTAG tap: sam3n.cpu tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4) Info : sam3n.cpu: hardware has 6 breakpoints, 4 watchpoints post init ---schnapp--- A -d3 output is attached. The bt is this: ---schnipp--- (gdb) bt #0 0xb7fe2424 in __kernel_vsyscall () #1 0xb7f1fc3d in select () from /lib/i386-linux-gnu/i686/cmov/libc.so.6 #2 0xb7fb72be in ?? () from /lib/i386-linux-gnu/libusb-0.1.so.4 #3 0xb7fc1315 in ftdi_read_data () from /usr/lib/i386-linux-gnu/libftdi.so.1 #4 0x08081dc9 in ft2232_read (buf=0xb7e38008 \202\t\017K\003\003\033\002\vK\002\203K\002\001\031\003, size=12, bytes_read=0xb02c) at ft2232.c:575 #5 0x08082098 in ft2232_send_and_recv (first=0xb7d37008, last=0x0) at ft2232.c:844 #6 0x08085691 in ft2232_execute_queue () at ft2232.c:2136 #7 0x08050e5d in interface_jtag_execute_queue () at driver.c:485 #8 0x0804e77f in jtag_execute_queue_noclear () at core.c:835 #9 0x0804e858 in jtag_execute_queue () at core.c:854 #10 0x080ae475 in jtagdp_transaction_endcheck (dap=0x81d03ec) at adi_v5_jtag.c:226 #11 jtag_dp_run (dap=0x81d03ec) at adi_v5_jtag.c:435 #12 0x080e43c7 in cortex_m3_poll (target=0x81cf290) at cortex_m3.c:536 #13 0x08064c82 in target_poll (target=0x81cf290) at target.c:453 #14 0x080658cb in handle_target (priv=0x81b1028) at target.c:1999 #15 handle_target (priv=0x81b1028) at target.c:1916 #16 0x0805c77b in target_call_timer_callback (now=0xb268, cb=0x81d6b38) at target.c:1147 #17 target_call_timer_callbacks_check_time (checktime=1) at target.c:1176 #18 0x08071f4b in server_loop (command_context=0x81b1008) at server.c:433 #19 0x0804b9ac in openocd_thread (cmd_ctx=0x81b1008, argv=0xb464, argc=3) at openocd.c:306 #20 openocd_main (argc=3, argv=0xb464) at openocd.c:339 #21 0x0804b275 in main (argc=3, argv=0xb464) at main.c:42 ---schnapp--- Any help would be appreciated Attila Kinali -- The trouble with you, Shev, is you don't say anything until you've saved up a whole truckload of damned heavy brick arguments and then you dump them all out and never look at the bleeding body mangled beneath the heap -- Tirin, The Dispossessed, U. Le Guin armusbocd.script Description: Binary data armusbocd.out.d3 Description: Binary data ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] Atmel SAM3N with OpenOCD 0.5.0
On Thu, 6 Oct 2011 23:07:44 +0200 Andreas Fritiofson andreas.fritiof...@gmail.com wrote: Other than that I'm not of much use, I haven't worked with any of the targets. Btw: if it would help, i could send you (or anyone else for that matter) one of the SAM3N evaluation boards[1]. Attila Kinali [1] http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4846 -- The trouble with you, Shev, is you don't say anything until you've saved up a whole truckload of damned heavy brick arguments and then you dump them all out and never look at the bleeding body mangled beneath the heap -- Tirin, The Dispossessed, U. Le Guin ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] Atmel SAM3N with OpenOCD 0.5.0
Moin,
Has anyone got a Atmel SAM3N (N, not U) working with OpenOCD?
SAM3U works with OpenOCD 0.5.0, but not with SAM3N.
The device is properly detected, but when accessing the flash, OpenOCD
hangs indefinitely.
See the attached script I use and its output.
If anyone could give me a hint how to get the SAM3N working or how
to debug the problem, i'd appreaciate it.
Attila Kinali
--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
# ***
#
# Customer: AoT
# Project#: 00-00
# Name: AOT_SW Framework
#
# Module: OpenOCD config file template
# State:
# Originator: Gillen
#
# $HeadURL:
svn://192.168.0.100/aot/Software/SIPA/WZU/trunk/sam3_armusbocd_script.template $
# $Revision: 12290 $
# $Date: 2011-09-20 15:32:11 +0200 (Di, 20 Sep 2011) $
#$Author: Gillen $
#
# Developed by Art of Technology AG, 2010
#
#
#
# Version History:
# Version 0.10: Initial version, adapted from OpenOCD templates
# This version is intended for tcl based OpenOCD = version 3.0
#
# For more information about the configuration files, take a
# look at the Open On-Chip Debugger (openocd) documentation.
#
#
# daemon configuration
telnet_port
gdb_port
tcl_port
# debug_level 3
# tell gdb our flash memory map
# and enable flash programming
# gdb_memory_map enable
# gdb_flash_program enable
#
#
# JTAG-Interface, if you want to use an other interface
# you must replace this section here.
#
interface ft2232
ft2232_device_desc Olimex OpenOCD JTAG
ft2232_layout olimex-jtag
ft2232_vid_pid 0x15ba 0x0003
ft2232_latency 5
#
#
# Target section, this example was tested with an
# SIPA/WZU board.
#
# AT91SAM3N starts with 4 MHz RC clock, no speedup foreseen
jtag_khz 15
# use combined on interfaces or targets that can't set TRST/SRST separately
# reset_config trst_and_srst
# reset_config trst_only srst_gates_jtag
# Best setting for SAM3UEK development board
reset_config trst_only
# reset_config trst_pulls_srst
#
# set some important constants
# Set CPU-ID seen over JTAG interface
# Attention: CPU-ID is chip specific
set _CPUTAPID 0x4ba00477
#
jtag newtap sam3n cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
target create sam3n.cpu cortex_m3 -endian little -chain-position sam3n.cpu
echo haha
sam3n.cpu configure -event reset-start {
echo hehe
# Very important, will not run without this delay!
jtag_ntrst_delay 100
echo Configure
# Set Flash timing to 6 wait states (silicon bug)
#mdw 0x400E0A00
# mww 0x400E0A00 0x0600
# set RC clock to 12 MHz,
# mww 0x400E0420 0x00370028
# mww 0x400E0430 0x0001 # Strange: This is MAINCK as source, but does
not work
# Setting readout says: Clock comes from PLLA!
jtag_khz 1000
}
sam3n.cpu configure -event gdb-flash-erase-start {
halt
}
# 8K is plenty, the smallest chip has this much
sam3n.cpu configure -work-area-virt 0 -work-area-phys 0x2000
-work-area-size 8192 -work-area-backup 0
echo Flash bank access
# size is automatically calculated by probing
flash bank sam3.flash at91sam3 0x0040 0 1 1 sam3n.cpu
echo Flash bank access DONE
## target end ###
## procedures ###
# Reset the processor as hard as possible
proc X_ucReset { } {
echo Resetting uC
reset run
# sleep 500
# jtag_reset 1 1
# sleep 500
# jtag_reset 0 0
}
# Report the actual processor status
proc X_ucStatus { state } {
echo CPU-Status($state) = [sam3n.cpu curstate]
}
# Report the JTAG scan line
proc X_JTAG_Info { } {
echo
echo JTAG info
targets
echo END JTAG Info
}
# Report the Flash infos
proc X_Flash_Info { bank } {
if { $bank == 0 } {
echo
echo FLASH BANKS
flash banks
}
echo
echo FLASH INFO BANK $bank
flash info $bank
echo END Flash Info Bank $bank
}
## procedures end ###
echo pre init
init
echo post init
#reset init
echo post init
X_ucStatus 0
reset
X_ucStatus 1
soft_reset_halt
X_ucStatus 2
soft_reset_halt
X_ucStatus 3
echo
echo
