Re: [OpenWrt-Devel] Gigaset SX763
On 13.5.2011. 20:02, Luca Olivetti wrote: Oh, I thought you wanted to dump the flash, not restore it, sorry, I've no suggestion for that. (Actually, if it's based on the danube, it should have a mode in which you can send the code via serial, and this mode doesn't depend on the flash, however I don't know how to activate it). Hi I couldn't find that pin which enebles UART mode, but only that one which enables CFG 05 (SFLASH), but I dunno how sflash mode can be used. On 11.5.2011. 0:38, Luca Olivetti wrote: Al 10/05/11 23:36, En/na Andrej Vlašić ha escrit: Mac address could be read from nvram (both primary and secondary bootloader are modified u-boot), but the eeprom_data is the problem. I dunno how to locate it inside my binary, is there any special hex value which represents that? It should be the data starting at offset 0x7a in your file (0xa5,0x5a), but I could be wrong (I have a chipset using ath9k, so I didn't look at how ath5k works). I see that you also had to change the pci id table to recognize your wifi chip. I'm not sure that's the correct thing to do: in the ar71xx architecture (using ath9k), they're writing some register that modify the pci id, maybe in your file there's also some fixup data? Thanx for the info about wlan, I found out that in original fw, they just added that pci id to madwifi drivers, will see after I manage to get wlan up how to fix that. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 13/05/11 21:13, En/na Andrej Vlašić ha escrit: I'm not sure that's the correct thing to do: in the ar71xx architecture (using ath9k), they're writing some register that modify the pci id, maybe in your file there's also some fixup data? Thanx for the info about wlan, I found out that in original fw, they just added that pci id to madwifi drivers, will see after I manage to get wlan up how to fix that. Ah, ok, maybe that's the correct approach then. In my original firmware (that's not Linux), the id changes automagically from ff1d to 0029 (according to the bootlog), then I found the code in ar71xx to do the fixup. It's possible that there's no such possibility with ath5k. Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
2011/5/9 John Crispin j...@phrozen.org Another question about usb power. Is it possible that on my board USB clock gating is different than one set in current dwc_otg_ifx.c. There it says: // set clock gating writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); On mine board it says: // set clock gating // JR: This means:: USB clock source is special internal clock generated from 36 MHz source set_bit (4, DANUBE_CGU_IFCCR); set_bit (5, DANUBE_CGU_IFCCR); Hi, BIT(4)|BIT(5) == 0x30 ;) however, i will review the driver code later to make sure usb power is setup properly Ok so I looked at that code, and below // set clock gating and there is: // set power writel(readl(DANUBE_PMU_PWDCR) ~0x1, DANUBE_PMU_PWDCR); writel(readl(DANUBE_PMU_PWDCR) ~0x40, DANUBE_PMU_PWDCR); writel(readl(DANUBE_PMU_PWDCR) ~0x8000, DANUBE_PMU_PWDCR); Shouldn't that be: writel(readl(DANUBE_PMU_PWDCR) ~0x1, DANUBE_PMU_PWDCR); writel(readl(DANUBE_PMU_PWDCR) ~0x20, DANUBE_PMU_PWDCR); writel(readl(DANUBE_PMU_PWDCR) ~0x4000, DANUBE_PMU_PWDCR); if the old code was clear_bit (0, DANUBE_PMU_PWDCR); clear_bit (6, DANUBE_PMU_PWDCR); clear_bit (15, DANUBE_PMU_PWDCR); Bye ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 8.5.2011. 0:41, Luca Olivetti wrote: Al 07/05/11 23:23, En/na Andrej Vlašić ha escrit: Also this board doesn't have wlan eeprom, instead it is read by a wlan driver from a file inside fw. If someone has some answers on how to modify current ath5k driver, would like to know. The code in mach-arv45xx.c (arv45xx_register_ath5k) should already take care of that. Bye Ok, gonna leave usb for later, my wireless eeprom is located in a file, and it is 4KB large. I saw that in arv45xx_register_ath5k eeprom_data is read from flash, so I'm thinking that best way to do the same on my board is to insert that eeprom binary directly into source and to read from it. Mac address could be read from nvram (both primary and secondary bootloader are modified u-boot), but the eeprom_data is the problem. I dunno how to locate it inside my binary, is there any special hex value which represents that? Here is that binary if anyone wants to have a look: https://code.google.com/p/sx76x-openwrt-danube/source/browse/trunk/wlan/arteep.bin Thanx ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 10/05/11 23:36, En/na Andrej Vlašić ha escrit: Mac address could be read from nvram (both primary and secondary bootloader are modified u-boot), but the eeprom_data is the problem. I dunno how to locate it inside my binary, is there any special hex value which represents that? It should be the data starting at offset 0x7a in your file (0xa5,0x5a), but I could be wrong (I have a chipset using ath9k, so I didn't look at how ath5k works). Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 11/05/11 00:29, En/na Luca Olivetti ha escrit: Al 10/05/11 23:36, En/na Andrej Vlašić ha escrit: Mac address could be read from nvram (both primary and secondary bootloader are modified u-boot), but the eeprom_data is the problem. I dunno how to locate it inside my binary, is there any special hex value which represents that? It should be the data starting at offset 0x7a in your file (0xa5,0x5a), but I could be wrong (I have a chipset using ath9k, so I didn't look at how ath5k works). I see that you also had to change the pci id table to recognize your wifi chip. I'm not sure that's the correct thing to do: in the ar71xx architecture (using ath9k), they're writing some register that modify the pci id, maybe in your file there's also some fixup data? See https://dev.openwrt.org/browser/trunk/target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.c https://dev.openwrt.org/browser/trunk/target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.h and how I adapted it to the danube (again, for ath9k, not ath5k) http://patchwork.midlink.org/patch/849/ Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 11/05/11 00:38, En/na Luca Olivetti ha escrit: Al 11/05/11 00:29, En/na Luca Olivetti ha escrit: Al 10/05/11 23:36, En/na Andrej Vlašić ha escrit: Mac address could be read from nvram (both primary and secondary bootloader are modified u-boot), but the eeprom_data is the problem. I dunno how to locate it inside my binary, is there any special hex value which represents that? It should be the data starting at offset 0x7a in your file (0xa5,0x5a), but I could be wrong (I have a chipset using ath9k, so I didn't look at how ath5k works). I see that you also had to change the pci id table to recognize your wifi chip. I'm not sure that's the correct thing to do: in the ar71xx architecture (using ath9k), they're writing some register that modify the pci id, maybe in your file there's also some fixup data? That seems to be the case: the file starts with 0x13 0x00 0x8c 0x16 - 168c:0013 which is a correct pci id for the ar5212 Unfortunately I have no idea what you should do with that data See https://dev.openwrt.org/browser/trunk/target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.c https://dev.openwrt.org/browser/trunk/target/linux/ar71xx/files/arch/mips/ar71xx/pci-ath9k-fixup.h and how I adapted it to the danube (again, for ath9k, not ath5k) http://patchwork.midlink.org/patch/849/ Bye ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 11/05/11 00:48, En/na Luca Olivetti ha escrit: That seems to be the case: the file starts with 0x13 0x00 0x8c 0x16 - 168c:0013 which is a correct pci id for the ar5212 And for the ar2414 (the one the sx763 is using), see here: http://linuxwireless.org/en/users/Drivers/ath5k/devices note the pci subsystem 0x2051, and there's a couple of 0x51, 0x20 in your file. Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 09/05/2011 0:31, En/na Luca Olivetti ha escrit: It turns out that the ebu, in the gpio_led structure, uses gpio starting from 32, so defining fake leds using gpios 32-40 I could map all missing leds. Since they're active low, I used lq_register_gpio_ebu(0xff), so they all turn off as soon as the kernel calls lq_register_gpio_ebu (contrary to leds controlled by real gpio, they're lit at power on, the original firmware turns them off very soon). The next question is, how can I control (some of) the leds from an userspace program? Opening the /sys/class/leds/led name/trigger file and alternatively writing none or default-on? Or the same but with the brightness file? Writing a trigger module? (and how since the trigger comes from user space)? Open the gpio directly? (again, how?) Some other way? TIA -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 09/05/11 16:59, Luca Olivetti wrote: Al 09/05/2011 0:31, En/na Luca Olivetti ha escrit: It turns out that the ebu, in the gpio_led structure, uses gpio starting from 32, so defining fake leds using gpios 32-40 I could map all missing leds. Since they're active low, I used lq_register_gpio_ebu(0xff), so they all turn off as soon as the kernel calls lq_register_gpio_ebu (contrary to leds controlled by real gpio, they're lit at power on, the original firmware turns them off very soon). The next question is, how can I control (some of) the leds from an userspace program? Opening the /sys/class/leds/led name/trigger file and alternatively writing none or default-on? Or the same but with the brightness file? Writing a trigger module? (and how since the trigger comes from user space)? Open the gpio directly? (again, how?) Some other way? TIA Hi luca, if it is a gpio cd /sys/class/gpio echo 13 export echo out gpio13/direction echo 0/1 gpio13/brightness for a led in userland echo default-on /sys/class/leds/led name/trigger or in kernel space use the default trigger as shown in this patch https://lists.openwrt.org/pipermail/openwrt-devel/2008-January/001618.html also look at /etc/init.d/led it allows you to setup your leds based on a uci file so ideally you give your leds a default brightness / trigger in the kernel code and then setup the others in userland via uci depending on which works best / makes sense for the specific case ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
2011/5/8 Andrej Vlašić andrej.vlas...@gmail.com I tried 29 again now, and no power, also tried some others, nothing. If someone want's to see here is how power is set in original fw: http://pastebin.com/00vJxdYa http://pastebin.com/00vJxdYa Another question about usb power. Is it possible that on my board USB clock gating is different than one set in current dwc_otg_ifx.c. There it says: // set clock gating writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); On mine board it says: // set clock gating // JR: This means:: USB clock source is special internal clock generated from 36 MHz source set_bit (4, DANUBE_CGU_IFCCR); set_bit (5, DANUBE_CGU_IFCCR); Thanx for any answers ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Another question about usb power. Is it possible that on my board USB clock gating is different than one set in current dwc_otg_ifx.c. There it says: // set clock gating writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); On mine board it says: // set clock gating // JR: This means:: USB clock source is special internal clock generated from 36 MHz source set_bit (4, DANUBE_CGU_IFCCR); set_bit (5, DANUBE_CGU_IFCCR); Hi, BIT(4)|BIT(5) == 0x30 ;) however, i will review the driver code later to make sure usb power is setup properly John ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 09/05/11 20:01, John Crispin wrote:
Another question about usb power.
Is it possible that on my board USB clock gating is different than one set
in current dwc_otg_ifx.c.
There it says:
// set clock gating
writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
On mine board it says:
// set clock gating
// JR: This means:: USB clock source is special internal clock
generated from 36 MHz source
set_bit (4, DANUBE_CGU_IFCCR);
set_bit (5, DANUBE_CGU_IFCCR);
Hi,
BIT(4)|BIT(5) == 0x30 ;)
however, i will review the driver code later to make sure usb power is
setup properly
John
inside
build_dir/linux-lantiq_xway/linux-2.6.37.6/drivers/usb/dwc_otg/dwc_otg_driver.c
you will find this code
static int __devinit
dwc_otg_driver_probe(struct platform_device *_dev)
{
int retval = 0;
dwc_otg_device_t *dwc_otg_device;
int pin = (int)_dev-dev.platform_data;
int32_t snpsid;
struct resource *res;
gusbcfg_data_t usbcfg = {.d32 = 0};
// GPIOs
if(pin = 0)
{
gpio_request(pin, usb_power);
gpio_direction_output(pin, 1);
gpio_set_value(pin, 1);
gpio_export(pin, 0);
}
dev_dbg(_dev-dev, dwc_otg_driver_probe (%p)\n, _dev);
try adding printk(foo %d\n, pin); between the // GPIOs and the if
( and see what the bootlog says
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Re: [OpenWrt-Devel] Gigaset SX763
Al 09/05/11 17:14, En/na John Crispin ha escrit:
The next question is, how can I control (some of) the leds from an
userspace program?
Opening the /sys/class/leds/led name/trigger file and alternatively
writing none or default-on?
Or the same but with the brightness file?
Writing a trigger module? (and how since the trigger comes from user
space)?
Open the gpio directly? (again, how?)
Some other way?
TIA
Hi luca,
if it is a gpio
cd /sys/class/gpio
echo 13 export
echo out gpio13/direction
echo 0/1 gpio13/brightness
for a led in userland echo default-on /sys/class/leds/led name/trigger
or in kernel space use the default trigger as shown in this patch
https://lists.openwrt.org/pipermail/openwrt-devel/2008-January/001618.html
also look at /etc/init.d/led it allows you to setup your leds based on
a uci file
so ideally you give your leds a default brightness / trigger in the
kernel code and then setup the others in userland via uci depending on
which works best / makes sense for the specific case
Well, none of the above ;-)
For almost all the leds there's already a suitable trigger module (be it
network activity, usb, heartbeat, etc., so it's just a matter of enabling it
like you said above, but there are some leds that I'd like to control from
a C application (specifically fxs1, fxs2 and voip),
so I'd like to know if there's an api for it, or I just open, e.g.,
/sys/class/leds/soc:green:fxs1/trigger, and fprintf default-on to turn it
on and none to turn it off (i.e., like the above shell commands but from C).
I just wanted to know if is there a more elegant way.
Note that those 3 leds are controlled by the ebu driver, and I assigned them
to the gpio_led structure, i.e.:
static struct gpio_led
arv7518pw_leds_gpio[] __initdata = {
{ .name = soc:green:power, .gpio = 2, .active_low = 1, },
{ .name = soc:green:adsl, .gpio = 4, .active_low = 1, },
{ .name = soc:green:internet, .gpio = 5, .active_low = 1, },
{ .name = soc:green:wlan, .gpio = 6, .active_low = 1, },
{ .name = soc:red:internet, .gpio = 8, .active_low = 1, },
{ .name = soc:green:usb, .gpio = 19, .active_low = 1, },
{ .name = soc:green:voip, .gpio = 32, .active_low = 1, },
{ .name = soc:green:fxs1, .gpio = 33, .active_low = 1, },
{ .name = soc:green:fxs2, .gpio = 34, .active_low = 1, },
/* no fxo on this board but the led is there, unlabeled */
{ .name = soc:red:fxo, .gpio = 35, .active_low = 1, },
{ .name = soc:yellow:wps, .gpio = 36, .active_low = 1, },
{ .name = soc:red:wps, .gpio = 38, .active_low = 1, },
};
so I'm not sure I can use the /sys/class/gpio method
(the echo xxx /sys/class/leds/yyy/trigger method works, that's how it tested
from userspace).
Bye
--
Luca
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Re: [OpenWrt-Devel] Gigaset SX763
Note that those 3 leds are controlled by the ebu driver, and I assigned them
to the gpio_led structure, i.e.:
static struct gpio_led
arv7518pw_leds_gpio[] __initdata = {
{ .name = soc:green:power, .gpio = 2, .active_low = 1, },
{ .name = soc:green:adsl, .gpio = 4, .active_low = 1, },
{ .name = soc:green:internet, .gpio = 5, .active_low = 1, },
{ .name = soc:green:wlan, .gpio = 6, .active_low = 1, },
{ .name = soc:red:internet, .gpio = 8, .active_low = 1, },
{ .name = soc:green:usb, .gpio = 19, .active_low = 1, },
{ .name = soc:green:voip, .gpio = 32, .active_low = 1, },
{ .name = soc:green:fxs1, .gpio = 33, .active_low = 1, },
{ .name = soc:green:fxs2, .gpio = 34, .active_low = 1, },
/* no fxo on this board but the led is there, unlabeled */
{ .name = soc:red:fxo, .gpio = 35, .active_low = 1, },
{ .name = soc:yellow:wps, .gpio = 36, .active_low = 1, },
{ .name = soc:red:wps, .gpio = 38, .active_low = 1, },
};
so I'm not sure I can use the /sys/class/gpio method
(the echo xxx /sys/class/leds/yyy/trigger method works, that's how it
tested
from userspace).
Bye
sorry, i am not aware of any clean solution fprintf() FTW!
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Re: [OpenWrt-Devel] Gigaset SX763
I'm curious about this box, it looks very interesting as a replacement for my current ADSL modem/router which is one of the last non-Free computer I use daily. Is the ADSL modem working well under OpenWRT? And what about the FXO/FXS ports? Stefan ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
2011/5/9 John Crispin j...@phrozen.org try adding printk(foo %d\n, pin); between the // GPIOs and the if ( and see what the bootlog says ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel This is what it says: dwc_otg: version 2.60a 22-NOV-2006 foo 29 DWC_otg: Using DMA mode dwc_otg dwc_otg.0: DWC OTG Controller dwc_otg dwc_otg.0: new USB bus registered, assigned bus number 1 dwc_otg dwc_otg.0: irq 62, io mem 0xbe101000 DWC_otg: Init: Port Power? op_state=1 DWC_otg: Init: Power Port (0) hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected I also tried some other GPIOs, and none works, but I'm sure that it is 29, because I also found inside router GPL source // P1.13 GPIO29 is EN_USB_PWR on Porta-Danube and there was also something about 13 in that patch I got to power up USB on old ifxmips. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On Sat, May 07, 2011 at 11:23:36PM +0200, Andrej Vlašić wrote:
I'm trying to set up openwrt on this router, it is based on Lantiq Xway
Danube Soc ( PSB50702 E), and manufactured by Sagem(previously by Siemens).
Wiki page is here http://wiki.openwrt.org/toh/gigaset/sx76x
I already managed to boot openwrt on it, but I cannot get USB working,
because there is no power on the port (DISCONNECTED PORT).
It was possible to get power on old ifxmips target by modifying GPIO
addresses in usb_vbus_enable function, but since that is now changed I dunno
how to make it work on a new one. ( I asked that on forums
https://forum.openwrt.org/viewtopic.php?pid=134415#p134415 )
I also looked up at those arcadyan board configs, and some of them have
_EBU addess and _USB pin defined.
I know that on this router usb power is on gpio 29( gpl source says that ),
and that irq at dwc_otg driver in original fw is 54, but I dunno which
address should go to EBU ( if any).
Also this board doesn't have wlan eeprom, instead it is read by a wlan
driver from a file inside fw. If someone has some answers on how to modify
current ath5k driver, would like to know.
I have been trying to set up JTAG on this board, but without success. I
have connected using this device:
http://www.diygadget.com/universal-jtag-adapter-for-routers-modem-fta-and-more.html
The board has standard EJTAG pinout. With urjtag I can dump only part of
flash:
==
jtag cable wiggler ppdev /dev/parport0
Initializing ppdev port /dev/parport0
jtag detect
IR length: 10
Chain length: 2
Device Id: 00011011 (0x0183)
Unknown manufacturer!
Device Id: 00011011 (0x0183)
Unknown manufacturer!
chain.c(149) Part 0 without active instruction
chain.c(200) Part 0 without active instruction
chain.c(149) Part 0 without active instruction
jtag discovery # output attached
jtag include admtek/adm5120/adm5120
jtag part 0
jtag include admtek/adm5120/adm5120
jtag instruction bypass
jtag part 1
jtag include admtek/adm5120/adm5120
jtag initbus ejtag
jtag readmem 0x5002 0x0002 0x0002.bin
==
This is the file from include (modified endian):
==
pc# cat /usr/share/urjtag/admtek/adm5120/adm5120
registerBR 1
registerBSR 1
registerDIR 32
registerEJIMPCODE 32
registerEJADDRESS 32
registerEJDATA 32
registerEJCONTROL 32
registerEJALL 96
registerEJFASTDATA 33
instruction length 5
instruction BYPASS 1 BR
instruction SAMPLE/PRELOAD 00010 BSR
instruction IDCODE 1 DIR
instruction EJTAG_IMPCODE 00011 EJIMPCODE
instruction EJTAG_ADDRESS 01000 EJADDRESS
instruction EJTAG_DATA 01001 EJDATA
instruction EJTAG_CONTROL 01010 EJCONTROL
instruction EJTAG_ALL 01011 EJALL
instruction EJTAGBOOT 01100 BR
instruction NORMALBOOT 01101 BR
instruction EJTAG_FASTDATA 01110 EJFASTDATA
initbus ejtag
endian big
==
But as you can see urjtag detects IR length: 10 and not 5 as set in
the file above. I suspect that is the reason why the output file looks
like this:
==
pc# xxd 0x0002.bin | head -n 20
000: beef 0100 0562 de5b ...b...[
010: 1e52 7ceb b8da 029d ...R..|.
020: 6d8b 88ee 6109 2d91 ..m...a...-.
030: be36 f86b 9154 cf09 ...6...k...T
040: 0cc2 422a a647 17d0 ..B*...G
050: 028f 8e11 59f6 3077 ..Y...0w
060: 458f 25e8 0999 85e9 ..E...%.
070: ee9c 7bb6 f508 44f3 ..{...D.
080: 8532 204c ab11 ...2.. L
090:
0a0:
0b0:
0c0:
0d0:
0e0:
0f0:
100: 3736 ..76
110: 6461 6265 0006 ..da..be
120: 0002 3036 ..06
130: 5f31 335f 6e74 655f .._1..3_..nt..e_
==
On the line 110 should be string danube, but it's not and every second
column is .
Anybody have suggestions how to change config file so it can dump memory
corectly?
Info here:
http://www.dd-wrt.com/phpBB2/viewtopic.php?p=339713 (comcute's post)
Re: [OpenWrt-Devel] Gigaset SX763
Al 10/05/11 00:51, En/na Luka Perkov ha escrit: The board has standard EJTAG pinout. With urjtag I can dump only part of flash: If the board uses the brn bootloader, maybe you can use my quick'n'dirty tool to dump the flash: http://code.google.com/p/brndumper/ Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Hi, I also looked up at those arcadyan board configs, and some of them have _EBU addess and _USB pin defined. I know that on this router usb power is on gpio 29( gpl source says that ) So you'll have to define it for your board in the call to xway_register_dwc (mach-arv45xx.c). if it was 29 on ifxmips/ it will be 29 on lantiq/. only the stp and ebu gpios were mapped to new offsets. the first 32 gpios stayed the same. can oyu make a photograph of the pcb ? after seeing a photo i can tell you if the unit has stp or ebu gpios Also this board doesn't have wlan eeprom, instead it is read by a wlan driver from a file inside fw. If someone has some answers on how to modify current ath5k driver, would like to know. in a file inside the FS or in a sector on the flash ? thanks, John ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 08/05/11 10:48, Luca Olivetti wrote: Al 08/05/11 10:33, En/na John Crispin ha escrit: if it was 29 on ifxmips/ it will be 29 on lantiq/. only the stp and ebu gpios were mapped to new offsets. the first 32 gpios stayed the same. Not related to the original question, but where I could find some documentation on stp/ebu, what they are and how do they work? There are some leds on my router that aren't tied to the normal GPIOs and I'd like to know how to drive them, maybe they are related to this stp/ebu thing? Bye STP - serial to parallel it is a setup where 3 pins are attached to a shift register or cascade thereof. it can go 24 bit deep. the xway socs have a few registers to control this. the actual magic of clocking the data out on the SPI into the shift registers is done by the IP core. the user only defines which led should be on. there is also a magic register to tell the leds to blink at 1 2 4 8 hz. a common chip used fotr this is the 74*595 EBU - external bus unit similar to STP but parallel. the xway has 4 x 16 bit ioport ranges that can be mapped to a special memory location. data written to that location is that physically written to the D0-15 lines on the memory bus. in addition a CS line is toggled. this allows you to use a 8-16bit latch to latch out the data. a common chip used for this is 74*373 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On Sun, May 08, 2011 at 10:33:30AM +0200, John Crispin wrote: I also looked up at those arcadyan board configs, and some of them have _EBU addess and _USB pin defined. I know that on this router usb power is on gpio 29( gpl source says that ) So you'll have to define it for your board in the call to xway_register_dwc (mach-arv45xx.c). if it was 29 on ifxmips/ it will be 29 on lantiq/. only the stp and ebu gpios were mapped to new offsets. the first 32 gpios stayed the same. can oyu make a photograph of the pcb ? after seeing a photo i can tell you if the unit has stp or ebu gpios http://wiki.openwrt.org/_media/toh/gigaset/dsc00453.jpg http://wiki.openwrt.org/_media/toh/gigaset/sam5943.jpg I could make more detailed photos if these are not good enough. Luka ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
on this pic - http://wiki.openwrt.org/_media/toh/gigaset/dsc00453.jpg on the very top, right of where it says PORTA SX76x there is a small chip. can you tell us what is printed on it ? ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On Sun, May 08, 2011 at 12:37:51PM +0200, John Crispin wrote: on this pic - http://wiki.openwrt.org/_media/toh/gigaset/dsc00453.jpg on the very top, right of where it says PORTA SX76x there is a small chip. can you tell us what is printed on it ? HC595AG (inside of circle - ON) PAQ832 Luka ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 08/05/11 15:03, Luka Perkov wrote: On Sun, May 08, 2011 at 12:37:51PM +0200, John Crispin wrote: on this pic - http://wiki.openwrt.org/_media/toh/gigaset/dsc00453.jpg on the very top, right of where it says PORTA SX76x there is a small chip. can you tell us what is printed on it ? HC595AG (inside of circle - ON) PAQ832 Luka ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel ok, thats the shift register, so the board has a STP led interface with 8 bit depth. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 08/05/11 11:13, En/na John Crispin ha escrit: EBU - external bus unit similar to STP but parallel. the xway has 4 x 16 bit ioport ranges that can be mapped to a special memory location. data written to that location is that physically written to the D0-15 lines on the memory bus. in addition a CS line is toggled. this allows you to use a 8-16bit latch to latch out the data. a common chip used for this is 74*373 Thank you for the detailed explanation. I have an LVC373A (octal latch), so it's probably EBU, isn't it? How do I try it? Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 08/05/11 18:29, Luca Olivetti wrote: Al 08/05/11 11:13, En/na John Crispin ha escrit: EBU - external bus unit similar to STP but parallel. the xway has 4 x 16 bit ioport ranges that can be mapped to a special memory location. data written to that location is that physically written to the D0-15 lines on the memory bus. in addition a CS line is toggled. this allows you to use a 8-16bit latch to latch out the data. a common chip used for this is 74*373 Thank you for the detailed explanation. I have an LVC373A (octal latch), so it's probably EBU, isn't it? How do I try it? Bye try this lq_register_gpio_ebu(XYZ); as the latch comes up in a undefined state, the values are random. to work around this, we pass a default value that gets applied. for example if oyu have a 8 bit latch XYZ-0x80 would result in 1 pin high and 7 low ... ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
On 08/05/11 20:16, Andrej Vlašić wrote: Also this board doesn't have wlan eeprom, instead it is read by a wlan driver from a file inside fw. If someone has some answers on how to modify current ath5k driver, would like to know. in a file inside the FS or in a sector on the flash ? Inside a file, which has wlan mac address in it, and it has that atheros AR5001-- Reference Card thing inside. About that usb gpio. I already tried 29 and some others to xway_register_dwc but it stays the same Disconnected port , and no power on it. Do I also need to set lq_pci_data.gpio and lq_pci_data.irq? ( currently I just copied everything from easy50712 mach config and changed partitions and other stuff for my board) Thanx pci is only needed for wifi to work. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 08/05/11 18:45, En/na John Crispin ha escrit: Thank you for the detailed explanation. I have an LVC373A (octal latch), so it's probably EBU, isn't it? How do I try it? Bye try this lq_register_gpio_ebu(XYZ); as the latch comes up in a undefined state, the values are random. to work around this, we pass a default value that gets applied. for example if oyu have a 8 bit latch XYZ-0x80 would result in 1 pin high and 7 low ... It turns out that the ebu, in the gpio_led structure, uses gpio starting from 32, so defining fake leds using gpios 32-40 I could map all missing leds. Since they're active low, I used lq_register_gpio_ebu(0xff), so they all turn off as soon as the kernel calls lq_register_gpio_ebu (contrary to leds controlled by real gpio, they're lit at power on, the original firmware turns them off very soon). Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Gigaset SX763
Al 07/05/11 23:23, En/na Andrej Vlašić ha escrit: I also looked up at those arcadyan board configs, and some of them have _EBU addess and _USB pin defined. I know that on this router usb power is on gpio 29( gpl source says that ) So you'll have to define it for your board in the call to xway_register_dwc (mach-arv45xx.c). Also this board doesn't have wlan eeprom, instead it is read by a wlan driver from a file inside fw. If someone has some answers on how to modify current ath5k driver, would like to know. The code in mach-arv45xx.c (arv45xx_register_ath5k) should already take care of that. Bye -- Luca ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
