Re: [PEDA] footprint clearance checking
Sorry, I have not yet made the move to DXP. Keep in mind that my library components do not have keep-outs defined for any footprints. I've designed them so that Protel's clearance constraint rule ends up using the slik-screen traces as it's guide. So far, in my setup, P99se seems to ignore the component's name #, unless they are on another layer other than the silkscreen. A good method to use this technique to your advantage would be to make a second clearance rule related to silkscreen traces without modifying the current 20 mil default, making sure it deals only with the footprint's keepout layer. Be sure your U shaped component just has no keepout defined you should be able to get stuff inside the 'U'. To really squeeze things in, try the smd stuff in my library. _ Brian Guralnick - Original Message - From: Brad Velander To: 'Protel EDA Forum' Sent: Wednesday, August 11, 2004 11:33 AM Subject: Re: [PEDA] footprint clearance checking Brian, In 2004 or more recent DXP versions, did Altium ever fix the fact that the clearance check includes all reference designators and other attributes within the footprint boundary check? Such that if you had a long attribute string it made the footprint clearance check impossible. Sincerely, Brad Velander PCB Designer Xantrex Technology Inc. (direct) (604) 415-4054 (general) (604) 422-8595 ext. 4054 (fax) (604) 422-1591 -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: August 10, 2004 10:50 PM To: Protel EDA Forum Subject: Re: [PEDA] footprint clearance checking Design it like all of the components in my publicly available library, where the silkscreen defines the outer inner edges of where the component surfaces meet the PCB. Shrink the component-component clearance to 1 mil, or 0 mil. This will allow you place, for example, some caps resistors right up to under some areas of a large PCB mounted RCA jack, but, it will not allow you to place components too close where the silk screen area may touch each other. Note that my library was intentionally designed like this for creating hand-held electronic devices where mounting area may be super constrictive. _ Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] footprint clearance checking
On 01:10 PM 11/08/2004, Dom Bragge said: I have a connector that could be viewed as a large U when placed on the board. If I want to place other components within this U shape (not overlapping the physical connector but within the bounding box) what choices do I have: - permanently enjoying the 20+ clearance errors? (not preferred) - turning off clearance checking? (not preferred) - turning off clearance checking for that one connector whilst in that position (how?)? Dom, Have you got the component clearance check set to Full Check - Full Check does not just use the bounding box for DRC. In P2004 SP1 the Full Check mode now works with on-line DRC, not only batch DRC. Users asked for this capability not long before SP1 was released and it made it in which is nice. I assume you don't have any primitives outside the real boundary of the component, as this will stuff up Full Checks ability to slot components in corners. I regularly put 0603 and 0402 components in the corner of SOT-223 (next to the larger tab) - Full check mode works fine in this case. If you are trying to deliberately overlap components (their primitives overlap) there is a technique that is often discussed on the DXP forum: http://forums.altium.com/cgi-bin/showthread.asp?id=32063list=dxp is a link to the recent discussion - the link is not complete as there is a problem with archiving some emails. I have been asking Altium about this issue for some time now - it does tend to devalue the archive if you can't trust that all posts are archived. The missing follow-up was that the IsComponent part of the rule is not needed as only components can be in a component class. Also, the missing follow-up discussed using rooms (possibly polygonal) and component height rule(s) to control the height of components under the stood off components. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] footprint clearance checking
I have a connector that could be viewed as a large U when placed on the board. If I want to place other components within this U shape (not overlapping the physical connector but within the bounding box) what choices do I have: - permanently enjoying the 20+ clearance errors? (not preferred) - turning off clearance checking? (not preferred) - turning off clearance checking for that one connector whilst in that position (how?)? ( P2004 ) = Dom Bragge CID Snr PCB Designer Sydney, Australia Find local movie times and trailers on Yahoo! Movies. http://au.movies.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] footprint clearance checking
Design it like all of the components in my publicly available library, where the silkscreen defines the outer inner edges of where the component surfaces meet the PCB. Shrink the component-component clearance to 1 mil, or 0 mil. This will allow you place, for example, some caps resistors right up to under some areas of a large PCB mounted RCA jack, but, it will not allow you to place components too close where the silk screen area may touch each other. Note that my library was intentionally designed like this for creating hand-held electronic devices where mounting area may be super constrictive. _ Brian Guralnick - Original Message - From: Dom Bragge To: Protel EDA forum Sent: Tuesday, August 10, 2004 11:10 PM Subject: [PEDA] footprint clearance checking I have a connector that could be viewed as a large U when placed on the board. If I want to place other components within this U shape (not overlapping the physical connector but within the bounding box) what choices do I have: - permanently enjoying the 20+ clearance errors? (not preferred) - turning off clearance checking? (not preferred) - turning off clearance checking for that one connector whilst in that position (how?)? ( P2004 ) = Dom Bragge CID Snr PCB Designer Sydney, Australia Find local movie times and trailers on Yahoo! Movies. http://au.movies.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
