CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Tue May 18 06:42:12 UTC 2021
Modified Files:
src/sys/arch/riscv/include: db_machdep.h
Log Message:
Use #define in this file
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/db_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/db_machdep.h
diff -u src/sys/arch/riscv/include/db_machdep.h:1.4 src/sys/arch/riscv/include/db_machdep.h:1.5
--- src/sys/arch/riscv/include/db_machdep.h:1.4 Tue May 18 06:40:16 2021
+++ src/sys/arch/riscv/include/db_machdep.h Tue May 18 06:42:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.4 2021/05/18 06:40:16 skrll Exp $ */
+/* $NetBSD: db_machdep.h,v 1.5 2021/05/18 06:42:11 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -47,19 +47,19 @@ extern const uint32_t __cpu_Debugger_ins
#define PC_REGS(tf) ((tf)->tf_pc)
-#define PC_ADVANCE(tf) do { \
+#define PC_ADVANCE(tf) do { \
if (db_get_value((tf)->tf_pc, sizeof(uint32_t), false) == BKPT_INST) \
(tf)->tf_pc += BKPT_SIZE; \
} while(0)
/* Similar to PC_ADVANCE(), except only advance on cpu_Debugger()'s bpt */
-#define PC_BREAK_ADVANCE(tf) do {\
+#define PC_BREAK_ADVANCE(tf) do {\
if ((tf)->tf_pc == (register_t) __cpu_Debugger_insn) \
(tf)->tf_pc += BKPT_SIZE; \
} while(0)
#define BKPT_ADDR(addr) (addr) /* breakpoint address */
-#define BKPT_INST 0x00100073
+#define BKPT_INST 0x00100073
#define BKPT_SIZE (sizeof(uint32_t)) /* size of bkpt inst */
#define BKPT_SET(inst, addr) (BKPT_INST)
@@ -70,12 +70,12 @@ extern const uint32_t __cpu_Debugger_ins
* MI ddb can't cope with having two sizes :-(
*/
#if 0
-#define BKPT_INST_2 0x9002
-#define BKPT_SIZE_2 (sizeof(uint16_t))
+#define BKPT_INST_2 0x9002
+#define BKPT_SIZE_2 (sizeof(uint16_t))
#endif
#define IS_BREAKPOINT_TRAP(type, code) ((type) == CAUSE_BREAKPOINT)
-#define IS_WATCHPOINT_TRAP(type, code) (0)
+#define IS_WATCHPOINT_TRAP(type, code) (0)
/*
* Interface to disassembly
@@ -106,9 +106,9 @@ typedef register_t kgdb_reg_t;
/*
* RISCV cpus have no hardware single-step.
*/
-#define SOFTWARE_SSTEP
+#define SOFTWARE_SSTEP
-#define inst_trap_return(ins) ((ins)&0)
+#define inst_trap_return(ins) ((ins)&0)
bool inst_branch(uint32_t inst);
bool inst_call(uint32_t inst);
@@ -127,7 +127,7 @@ void db_resume_others(void);
/*
* We have machine-dependent commands.
*/
-#define DB_MACHINE_COMMANDS
+#define DB_MACHINE_COMMANDS
#endif
#endif /* _RISCV_DB_MACHDEP_H_ */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Tue May 18 06:40:16 UTC 2021 Modified Files: src/sys/arch/riscv/include: db_machdep.h Log Message: Remove argument names from function declaration prototypes. Misc tidyup. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/db_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/db_machdep.h diff -u src/sys/arch/riscv/include/db_machdep.h:1.3 src/sys/arch/riscv/include/db_machdep.h:1.4 --- src/sys/arch/riscv/include/db_machdep.h:1.3 Wed Apr 14 06:32:20 2021 +++ src/sys/arch/riscv/include/db_machdep.h Tue May 18 06:40:16 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: db_machdep.h,v 1.3 2021/04/14 06:32:20 dholland Exp $ */ +/* $NetBSD: db_machdep.h,v 1.4 2021/05/18 06:40:16 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -28,6 +28,7 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ + #ifndef _RISCV_DB_MACHDEP_H_ #define _RISCV_DB_MACHDEP_H_ @@ -57,9 +58,9 @@ extern const uint32_t __cpu_Debugger_ins (tf)->tf_pc += BKPT_SIZE; \ } while(0) -#define BKPT_ADDR(addr) (addr) /* breakpoint address */ -#define BKPT_INST 0x00100073 -#define BKPT_SIZE (sizeof(uint32_t)) /* size of breakpoint inst */ +#define BKPT_ADDR(addr) (addr) /* breakpoint address */ +#define BKPT_INST 0x00100073 +#define BKPT_SIZE (sizeof(uint32_t)) /* size of bkpt inst */ #define BKPT_SET(inst, addr) (BKPT_INST) /* @@ -79,14 +80,14 @@ extern const uint32_t __cpu_Debugger_ins /* * Interface to disassembly */ -db_addr_t db_disasm_insn(uint32_t insn, db_addr_t loc, bool altfmt); +db_addr_t db_disasm_insn(uint32_t, db_addr_t, bool); /* * Entrypoints to DDB for kernel, keyboard drivers, init hook */ void kdb_kbd_trap(db_regs_t *); -int kdb_trap(int type, struct trapframe *); +int kdb_trap(int, struct trapframe *); static inline void db_set_ddb_regs(int type, struct trapframe *tf)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun May 16 09:02:04 UTC 2021 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: s/ENTRY/ENTRY_NP/ in a few places To generate a diff of this commit: cvs rdiff -u -r1.21 -r1.22 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.21 src/sys/arch/riscv/riscv/locore.S:1.22 --- src/sys/arch/riscv/riscv/locore.S:1.21 Sat May 1 07:10:34 2021 +++ src/sys/arch/riscv/riscv/locore.S Sun May 16 09:02:04 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.21 2021/05/01 07:10:34 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.22 2021/05/16 09:02:04 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -479,7 +479,7 @@ END(cpu_exception_handler) // int cpu_set_onfault(struct faultbuf *fb, register_t retval) // -ENTRY(cpu_set_onfault) +ENTRY_NP(cpu_set_onfault) REG_S ra, FB_RA(a0) REG_S s0, FB_S0(a0) REG_S s1, FB_S1(a0) @@ -500,7 +500,7 @@ ENTRY(cpu_set_onfault) ret END(cpu_set_onfault) -ENTRY(setjmp) +ENTRY_NP(setjmp) REG_S ra, FB_RA(a0) REG_S s0, FB_S0(a0) REG_S s1, FB_S1(a0) @@ -519,7 +519,7 @@ ENTRY(setjmp) ret END(setjmp) -ENTRY(longjmp) +ENTRY_NP(longjmp) REG_L ra, FB_RA(a0) REG_L s0, FB_S0(a0) REG_L s1, FB_S1(a0)
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: jmcneill
Date: Wed May 5 12:47:02 UTC 2021
Added Files:
src/sys/arch/riscv/include: loadfile_machdep.h
Log Message:
Add loadfile_machdep.h for riscv
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/include/loadfile_machdep.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/riscv/include/loadfile_machdep.h
diff -u /dev/null src/sys/arch/riscv/include/loadfile_machdep.h:1.1
--- /dev/null Wed May 5 12:47:02 2021
+++ src/sys/arch/riscv/include/loadfile_machdep.h Wed May 5 12:47:02 2021
@@ -0,0 +1,33 @@
+/* $NetBSD: loadfile_machdep.h,v 1.1 2021/05/05 12:47:02 jmcneill Exp $ */
+
+#ifdef _LP64
+#define BOOT_ELF64
+#else
+#define BOOT_ELF32
+#endif
+
+#define LOAD_KERNEL (LOAD_ALL & ~LOAD_TEXTA)
+#define COUNT_KERNEL (COUNT_ALL & ~COUNT_TEXTA)
+
+#define LOADADDR(a) (((u_long)(a)))
+#define ALIGNENTRY(a) ((u_long)(a))
+#define READ(f, b, c) read((f), (void*)LOADADDR(b), (c))
+#define BCOPY(s, d, c) memmove((void*)LOADADDR(d), (void*)(s), (c))
+#define BZERO(d, c) memset((void*)LOADADDR(d), 0, (c))
+#define WARN(a) do { \
+ (void)printf a; \
+ if (errno) \
+ (void)printf(": %s\n", \
+ strerror(errno)); \
+ else \
+ (void)printf("\n"); \
+} while(/* CONSTCOND */0)
+#ifdef PROGRESS_FN
+void PROGRESS_FN(const char *, ...) __printflike(1, 2);
+#define PROGRESS(a) PROGRESS_FN a
+#else
+#define PROGRESS(a) (void)printf a
+#endif
+#define ALLOC(a) alloc(a)
+#define DEALLOC(a, b) dealloc(a, b)
+#define OKMAGIC(a) ((a) == ZMAGIC)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon May 3 20:07:57 UTC 2021 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Sort __HAVE_ #defines. NFCI. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/types.h diff -u src/sys/arch/riscv/include/types.h:1.11 src/sys/arch/riscv/include/types.h:1.12 --- src/sys/arch/riscv/include/types.h:1.11 Sat May 1 06:45:23 2021 +++ src/sys/arch/riscv/include/types.h Mon May 3 20:07:57 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.11 2021/05/01 06:45:23 skrll Exp $ */ +/* $NetBSD: types.h,v 1.12 2021/05/03 20:07:57 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -83,23 +83,25 @@ typedef __int32_t __register_t; #define __SIMPLELOCK_LOCKED 1 #define __SIMPLELOCK_UNLOCKED 0 +#define __HAVE_COMMON___TLS_GET_ADDR +#define __HAVE_COMPAT_NETBSD32 +#define __HAVE_CPU_COUNTER +#define __HAVE_CPU_DATA_FIRST #define __HAVE_FAST_SOFTINTS #define __HAVE_MM_MD_DIRECT_MAPPED_PHYS -#define __HAVE_CPU_COUNTER +//#define __HAVE_NEW_STYLE_BUS_H +#define __HAVE_NO_BUS_DMA #define __HAVE_SYSCALL_INTERN -#define __HAVE_CPU_DATA_FIRST -#define __HAVE___LWP_GETPRIVATE_FAST -#define __HAVE_COMMON___TLS_GET_ADDR #define __HAVE_TLS_VARIANT_I +/* XXX temporary */ +#define __HAVE_UNLOCKED_PMAP +#define __HAVE___LWP_GETPRIVATE_FAST + #ifdef __LP64 #define __HAVE_ATOMIC64_OPS #define __HAVE_CPU_UAREA_ROUTINES #endif -//#define __HAVE_NEW_STYLE_BUS_H -#define __HAVE_NO_BUS_DMA -#define __HAVE_COMPAT_NETBSD32 - //#if defined(_KERNEL) //#define __HAVE_RAS //#endif @@ -109,7 +111,4 @@ typedef __int32_t __register_t; #define PCU_UNIT_COUNT 1 #endif -/* XXX temporary */ -#define __HAVE_UNLOCKED_PMAP - #endif /* _RISCV_TYPES_H_ */
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat May 1 07:41:24 UTC 2021
Modified Files:
src/sys/arch/riscv/include: pmap.h pte.h vmparam.h
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Fixup some pmap / VM related #defines and code
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/pmap.h \
src/sys/arch/riscv/include/vmparam.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/pte.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.8 src/sys/arch/riscv/include/pmap.h:1.9
--- src/sys/arch/riscv/include/pmap.h:1.8 Sun Dec 20 16:38:25 2020
+++ src/sys/arch/riscv/include/pmap.h Sat May 1 07:41:24 2021
@@ -1,11 +1,12 @@
-/* $NetBSD: pmap.h,v 1.8 2020/12/20 16:38:25 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.9 2021/05/01 07:41:24 skrll Exp $ */
/*
- * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
+ * Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
+ * by Matt Thomas (of 3am Software Foundry), Maxime Villard, and
+ * Nick Hudson.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -38,6 +39,7 @@
#if !defined(_MODULE)
+#include
#include
#include
#include
@@ -46,26 +48,35 @@
#include
#include
+#include
#define PMAP_SEGTABSIZE NPTEPG
-
-#define NBSEG (PAGE_SIZE * NPTEPG)
+#define PMAP_PDETABSIZE NPTEPG
#ifdef _LP64
-#define NBXSEG (NBSEG * NSEGPG)
-#define XSEGSHIFT (SEGSHIFT + PGSHIFT - 3)
-#define XSEGOFSET (PTE_PPN1 | SEGOFSET)
-#define SEGSHIFT (PGSHIFT + PGSHIFT - 3)
+#define PTPSHIFT 3
+/* This is SV48. */
+//#define SEGLENGTH + SEGSHIFT + SEGSHIFT */
+
+/* This is SV39. */
+#define XSEGSHIFT (SEGSHIFT + SEGLENGTH)
+#define NBXSEG (1ULL << XSEGSHIFT)
+#define XSEGOFSET (NBXSEG - 1) /* byte offset into xsegment */
+#define XSEGLENGTH (PGSHIFT - 3)
+#define NXSEGPG (1 << XSEGLENGTH)
#else
-#define SEGSHIFT (PGSHIFT + PGSHIFT - 2)
+#define PTPSHIFT 2
+#define XSEGSHIFT SEGLENGTH
#endif
-#define SEGOFSET (PTE_PPN0|PAGE_MASK)
+#define SEGLENGTH (PGSHIFT - PTPSHIFT)
+#define SEGSHIFT (SEGLENGTH + PGSHIFT)
+#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
+#define SEGOFSET (NBSEG - 1) /* byte offset into segment */
#define KERNEL_PID 0
#define PMAP_HWPAGEWALKER 1
-#define PMAP_TLB_NUM_PIDS 256
#define PMAP_TLB_MAX 1
#ifdef _LP64
#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
@@ -74,6 +85,8 @@
#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)0xdeadbeef)
#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)0xdeadbeef)
#endif
+#define PMAP_TLB_NUM_PIDS (__SHIFTOUT_MASK(SATP_ASID) + 1)
+#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
#define PMAP_TLB_FLUSH_ASID_ON_RESET false
#define pmap_phys_address(x) (x)
@@ -120,9 +133,9 @@ paddr_t pmap_md_direct_mapped_vaddr_to_p
vaddr_t pmap_md_direct_map_paddr(paddr_t);
void pmap_md_init(void);
bool pmap_md_tlb_check_entry(void *, vaddr_t, tlb_asid_t, pt_entry_t);
-voidpmap_md_page_syncicache(struct vm_page_md *, const kcpuset_t *);
-void pmap_md_pdetab_activate(struct pmap *);
+void pmap_md_xtab_activate(struct pmap *, struct lwp *);
+void pmap_md_xtab_deactivate(struct pmap *);
void pmap_md_pdetab_init(struct pmap *);
bool pmap_md_ok_to_steal_p(const uvm_physseg_t, size_t);
@@ -131,6 +144,9 @@ extern vaddr_t pmap_direct_end;
#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa))
#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - pmap_direct_base)
+#define MEGAPAGE_TRUNC(x) ((x) & ~SEGOFSET)
+#define MEGAPAGE_ROUND(x) MEGAPAGE_TRUNC((x) + SEGOFSET)
+
#ifdef __PMAP_PRIVATE
static inline void
pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *kc)
@@ -150,7 +166,6 @@ pmap_md_vca_add(struct vm_page_md *mdpg,
static inline void
pmap_md_vca_remove(struct vm_page_md *mdpg, vaddr_t va)
{
-
}
static inline void
@@ -164,20 +179,6 @@ pmap_md_tlb_asid_max(void)
return PMAP_TLB_NUM_PIDS - 1;
}
-static inline void
-pmap_md_xtab_activate(struct pmap *pm, struct lwp *l)
-{
-
- /* nothing */
-}
-
-static inline void
-pmap_md_xtab_deactivate(struct pmap *pm)
-{
-
- /* nothing */
-}
-
#endif /* __PMAP_PRIVATE */
#endif /* _KERNEL */
Index: src/sys/arch/riscv/include/vmparam.h
diff -u src/sys/arch/riscv/include/vmparam.h:1.8 src/sys/arch/riscv/include/vmparam.h:1.9
--- src/sys/arch/riscv/include/vmparam.h:1.8 Fri Feb 26 02:18:29 2021
+++ src/sys/arch/riscv/include/vmparam.h Sat May 1 07:41:24 2021
@@ -1,11 +1,11 @@
-/* $NetBSD: vmparam.h,v 1.8
CVS commit: src/sys/arch/riscv/conf
Module Name:src
Committed By: skrll
Date: Sat May 1 07:13:21 UTC 2021
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv kern.ldscript
Log Message:
Fixup kernel linking and provide a linker script with standard sections
and symbols
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/Makefile.riscv
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/kern.ldscript
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.6 src/sys/arch/riscv/conf/Makefile.riscv:1.7
--- src/sys/arch/riscv/conf/Makefile.riscv:1.6 Sat Mar 14 16:12:15 2020
+++ src/sys/arch/riscv/conf/Makefile.riscv Sat May 1 07:13:21 2021
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.riscv,v 1.6 2020/03/14 16:12:15 skrll Exp $
+# $NetBSD: Makefile.riscv,v 1.7 2021/05/01 07:13:21 skrll Exp $
# Makefile for NetBSD
#
@@ -74,11 +74,17 @@ TEXTADDR?= 0xFFC0
TEXTADDR?= 0xC0001000
.endif
KERNLDSCRIPT?= ${RISCV}/conf/kern.ldscript
-LINKFORMAT+= -T ${KERNLDSCRIPT}
EXTRA_LINKFLAGS= ${LDOPTS} --relax
LINKFLAGS_NORMAL= -X
STRIPFLAGS= -g -X
+# Set the physical load address (aka LMA) to the address that OpenSBI's
+# fw_jump jumps to. This allows us to load the kernel with the -kernel flag
+# in QEMU without having to embed it inside BBL or OpenSBI's fw_payload first.
+#
+KERNEL_PHYS?= 0x8020
+EXTRA_LINKFLAGS+= --defsym='KERNEL_PHYS=${KERNEL_PHYS}'
+
##
## (6) port specific target dependencies
##
Index: src/sys/arch/riscv/conf/kern.ldscript
diff -u src/sys/arch/riscv/conf/kern.ldscript:1.7 src/sys/arch/riscv/conf/kern.ldscript:1.8
--- src/sys/arch/riscv/conf/kern.ldscript:1.7 Wed Nov 4 07:09:45 2020
+++ src/sys/arch/riscv/conf/kern.ldscript Sat May 1 07:13:21 2021
@@ -1,4 +1,6 @@
-/* $NetBSD: kern.ldscript,v 1.7 2020/11/04 07:09:45 skrll Exp $ */
+/* $NetBSD: kern.ldscript,v 1.8 2021/05/01 07:13:21 skrll Exp $ */
+
+#include "assym.h"
OUTPUT_ARCH(riscv)
ENTRY(start)
@@ -8,8 +10,10 @@ __LARGE_PAGE_SIZE = 0x20 ;
SECTIONS
{
- .text : AT (ADDR(.text) & 0x0fff)
+
+ .text : AT (KERNEL_PHYS)
{
+ PROVIDE(__kernel_text = .);
*(.text)
*(.text.*)
*(.stub)
@@ -19,7 +23,7 @@ SECTIONS
. = ALIGN(__LARGE_PAGE_SIZE);
- __rodata_start = . ;
+ PROVIDE(__rodata_start = .);
.rodata :
{
*(.rodata)
@@ -28,17 +32,36 @@ SECTIONS
*(.srodata.*)
}
+ PROVIDE(_etext = .);
+ PROVIDE(etext = .);
. = ALIGN(__LARGE_PAGE_SIZE);
- __data_start = . ;
.data :
{
+ PROVIDE(__data_start = .);
*(.data)
+ }
+
+ . = ALIGN(COHERENCY_UNIT);
+ .data.cacheline_aligned :
+ {
+ *(.data.cacheline_aligned)
+ }
+ . = ALIGN(COHERENCY_UNIT);
+ .data.read_mostly :
+ {
+ *(.data.read_mostly)
+ }
+ . = ALIGN(COHERENCY_UNIT);
+
+ .sdata :
+ {
+ __global_pointer$ = . + 0x800;
*(.sdata)
*(.sdata.*)
}
- _edata = . ;
- PROVIDE (edata = .) ;
+ _edata = .;
+ PROVIDE (edata = .);
__bss_start = .;
.bss :
@@ -50,14 +73,13 @@ SECTIONS
*(COMMON)
. = ALIGN(__LARGE_PAGE_SIZE);
}
-
+ _bss_end__ = . ;
+ __bss_end__ = . ;
. = ALIGN(__PAGE_SIZE);
- /* End of the kernel image */
- __kernel_end = . ;
-
- _end = . ;
- PROVIDE (end = .) ;
+ __end__ = . ;
+ _end = .;
+ PROVIDE(end = .);
.note.netbsd.ident :
{
KEEP(*(.note.netbsd.ident));
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat May 1 07:11:12 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: autoconf.c
Log Message:
Enable interrupts at the end of cpu_configure
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/autoconf.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/autoconf.c
diff -u src/sys/arch/riscv/riscv/autoconf.c:1.2 src/sys/arch/riscv/riscv/autoconf.c:1.3
--- src/sys/arch/riscv/riscv/autoconf.c:1.2 Wed Nov 4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/autoconf.c Sat May 1 07:11:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.2 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: autoconf.c,v 1.3 2021/05/01 07:11:12 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: autoconf.c,v 1.2 2020/11/04 07:09:46 skrll Exp $");
+__RCSID("$NetBSD: autoconf.c,v 1.3 2021/05/01 07:11:12 skrll Exp $");
#include
#include
@@ -47,6 +47,8 @@ cpu_configure(void)
if (config_rootfound("mainbus", NULL) == NULL)
panic("no mainbus found");
+
+ spl0();
}
void
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat May 1 07:10:34 UTC 2021 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Quick hack to make this link To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.20 src/sys/arch/riscv/riscv/locore.S:1.21 --- src/sys/arch/riscv/riscv/locore.S:1.20 Sun Nov 8 10:08:28 2020 +++ src/sys/arch/riscv/riscv/locore.S Sat May 1 07:10:34 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.20 2020/11/08 10:08:28 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.21 2021/05/01 07:10:34 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -120,8 +120,7 @@ ENTRY_NP(start) #endif // We should have a VM so let's start using our real addresses - lui t0, %hi(.Lmmu_on) // load hi part of absolute address - jr t0, %lo(.Lmmu_on) // jump to absolute address + PTR_LA t0, .Lmmu_on .Lmmu_on: // MMU is on!
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat May 1 07:09:55 UTC 2021
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Provide riscvreg_satp_{read,write}
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.12 src/sys/arch/riscv/include/sysreg.h:1.13
--- src/sys/arch/riscv/include/sysreg.h:1.12 Sat May 1 07:09:04 2021
+++ src/sys/arch/riscv/include/sysreg.h Sat May 1 07:09:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.12 2021/05/01 07:09:04 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.13 2021/05/01 07:09:55 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,6 +36,8 @@
#include
#endif
+#include
+
#define FCSR_FMASK 0 // no exception bits
#define FCSR_FRM __BITS(7,5)
#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
@@ -262,6 +264,20 @@ riscvreg_cycle_read(void)
#define SATP_PPN __BITS(21,0)
#endif
+static inline uintptr_t
+riscvreg_satp_read(void)
+{
+ uintptr_t satp;
+ __asm __volatile("csrr %0, satp" : "=r" (satp));
+ return satp;
+}
+
+static inline void
+riscvreg_satp_write(uintptr_t satp)
+{
+ __asm __volatile("csrw satp, %0" :: "r" (satp));
+}
+
static inline uint32_t
riscvreg_asid_read(void)
{
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 1 07:09:04 UTC 2021 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Indent the FCSR_FRM value #defines To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.11 src/sys/arch/riscv/include/sysreg.h:1.12 --- src/sys/arch/riscv/include/sysreg.h:1.11 Wed Dec 16 19:49:04 2020 +++ src/sys/arch/riscv/include/sysreg.h Sat May 1 07:09:04 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.11 2020/12/16 19:49:04 christos Exp $ */ +/* $NetBSD: sysreg.h,v 1.12 2021/05/01 07:09:04 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -38,12 +38,12 @@ #define FCSR_FMASK 0 // no exception bits #define FCSR_FRM __BITS(7,5) -#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even -#define FCSR_FRM_RTZ 0b001 // Round Towards Zero -#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) -#define FCSR_FRM_RUP 0b011 // Round UP (+infinity) -#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude -#define FCSR_FRM_DYN 0b111 // Dynamic rounding +#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even +#define FCSR_FRM_RTZ 0b001 // Round Towards Zero +#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity) +#define FCSR_FRM_RUP 0b011 // Round UP (+infinity) +#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude +#define FCSR_FRM_DYN 0b111 // Dynamic rounding #define FCSR_FFLAGS __BITS(4,0) // Sticky bits #define FCSR_NV __BIT(4) // iNValid operation #define FCSR_DZ __BIT(3) // Divide by Zero
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 1 07:06:54 UTC 2021 Modified Files: src/sys/arch/riscv/include: param.h Log Message: Bump MSGBUFSIZE (if not defined) Provide COHERENCY_UNIT and CACHE_LINE_SIZE Also provide MAXCPUS To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/param.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/param.h diff -u src/sys/arch/riscv/include/param.h:1.3 src/sys/arch/riscv/include/param.h:1.4 --- src/sys/arch/riscv/include/param.h:1.3 Sat Jun 1 12:42:28 2019 +++ src/sys/arch/riscv/include/param.h Sat May 1 07:06:54 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: param.h,v 1.3 2019/06/01 12:42:28 maxv Exp $ */ +/* $NetBSD: param.h,v 1.4 2021/05/01 07:06:54 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -88,6 +88,15 @@ #define MCLBYTES (1 << MCLSHIFT) /* size of a m_buf cluster */ +#ifndef MSGBUFSIZE +#define MSGBUFSIZE 65536 /* default message buffer size */ +#endif + +#define COHERENCY_UNIT 64 +#define CACHE_LINE_SIZE 64 + +#define MAXCPUS 32 + #ifdef _KERNEL void delay(unsigned long); #define DELAY(x) delay(x)
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 1 07:05:07 UTC 2021 Modified Files: src/sys/arch/riscv/include: asm.h Log Message: Provide __CONCAT, __STRING and ___CONCAT To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/asm.h diff -u src/sys/arch/riscv/include/asm.h:1.5 src/sys/arch/riscv/include/asm.h:1.6 --- src/sys/arch/riscv/include/asm.h:1.5 Fri Apr 17 14:19:44 2020 +++ src/sys/arch/riscv/include/asm.h Sat May 1 07:05:07 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.5 2020/04/17 14:19:44 joerg Exp $ */ +/* $NetBSD: asm.h,v 1.6 2021/05/01 07:05:07 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -34,6 +34,11 @@ #define _C_LABEL(x) x +#define __CONCAT(x,y) x ## y +#define __STRING(x) #x + +#define ___CONCAT(x,y) __CONCAT(x,y) + /* * Define -pg profile entry code. * Must always be noreorder, must never use a macro instruction
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat May 1 06:53:09 UTC 2021
Modified Files:
src/sys/arch/riscv/include: locore.h
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
Sprinkle #ifdef FPE for now
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/locore.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/locore.h
diff -u src/sys/arch/riscv/include/locore.h:1.7 src/sys/arch/riscv/include/locore.h:1.8
--- src/sys/arch/riscv/include/locore.h:1.7 Wed Nov 4 07:09:45 2020
+++ src/sys/arch/riscv/include/locore.h Sat May 1 06:53:08 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.7 2020/11/04 07:09:45 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.8 2021/05/01 06:53:08 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -118,7 +118,10 @@ struct mainbus_attach_args {
#ifdef _KERNEL
extern int cpu_printfataltraps;
+
+#ifdef FPE
extern const pcu_ops_t pcu_fpu_ops;
+#endif
static inline vaddr_t
stack_align(vaddr_t sp)
@@ -135,31 +138,43 @@ userret(struct lwp *l)
static inline void
fpu_load(void)
{
+#ifdef FPE
pcu_load(_fpu_ops);
+#endif
}
static inline void
fpu_save(lwp_t *l)
{
+#ifdef FPE
pcu_save(_fpu_ops, l);
+#endif
}
static inline void
fpu_discard(lwp_t *l)
{
+#ifdef FPE
pcu_discard(_fpu_ops, l, false);
+#endif
}
static inline void
fpu_replace(lwp_t *l)
{
+#ifdef FPE
pcu_discard(_fpu_ops, l, true);
+#endif
}
static inline bool
fpu_valid_p(lwp_t *l)
{
+#ifdef FPE
return pcu_valid_p(_fpu_ops, l);
+#else
+ return false;
+#endif
}
void __syncicache(const void *, size_t);
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.13 src/sys/arch/riscv/riscv/riscv_machdep.c:1.14
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.13 Wed Nov 4 20:05:47 2020
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Sat May 1 06:53:08 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.14 2021/05/01 06:53:08 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_modular.h"
-__RCSID("$NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.14 2021/05/01 06:53:08 skrll Exp $");
#include
#include
@@ -65,7 +65,9 @@ struct cpu_info cpu_info_store = {
};
const pcu_ops_t * const pcu_ops_md_defs[PCU_UNIT_COUNT] = {
+#ifdef FPE
[PCU_FPU] = _fpu_ops,
+#endif
};
void
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat May 1 06:48:51 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/db_disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_disasm.c
diff -u src/sys/arch/riscv/riscv/db_disasm.c:1.6 src/sys/arch/riscv/riscv/db_disasm.c:1.7
--- src/sys/arch/riscv/riscv/db_disasm.c:1.6 Tue Apr 20 10:15:34 2021
+++ src/sys/arch/riscv/riscv/db_disasm.c Sat May 1 06:48:51 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_disasm.c,v 1.6 2021/04/20 10:15:34 skrll Exp $ */
+/* $NetBSD: db_disasm.c,v 1.7 2021/05/01 06:48:51 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: db_disasm.c,v 1.6 2021/04/20 10:15:34 skrll Exp $");
+__RCSID("$NetBSD: db_disasm.c,v 1.7 2021/05/01 06:48:51 skrll Exp $");
#include
#include
@@ -97,7 +97,7 @@ db_print_addr(db_addr_t loc)
* size. I've used the #defines for that to conditionalize it, on the
* grounds that ddb is disassembling itself so the build machine
* version is the target machine version. This is not true for crash
- * necessarily but I don't think
+ * necessarily but I don't think
*/
#define COMBINE(op, q) (((op) << 2) | (q))
@@ -153,7 +153,7 @@ db_disasm_16(db_addr_t loc, uint32_t ins
rd = INSN16_RS2x(insn);
#if __riscv_xlen < 128
imm = INSN16_IMM_CL_D(insn);
- db_printf("c.fld f%d, %d(%s)\n", rd, (int32_t)imm,
+ db_printf("c.fld f%d, %d(%s)\n", rd, (int32_t)imm,
riscv_registers[rs1]);
#else
imm = INSN16_IMM_CL_Q(insn);
@@ -173,7 +173,7 @@ db_disasm_16(db_addr_t loc, uint32_t ins
rd = INSN16_RS2x(insn);
#if __riscv_xlen == 32
imm = INSN16_IMM_CL_W(insn);
- db_printf("c.flw f%d, %d(%s)\n", rd, (int32_t)imm,
+ db_printf("c.flw f%d, %d(%s)\n", rd, (int32_t)imm,
riscv_registers[rs1]);
#else
imm = INSN16_IMM_CL_D(insn);
@@ -186,7 +186,7 @@ db_disasm_16(db_addr_t loc, uint32_t ins
rs2 = INSN16_RS2x(insn);
#if __riscv_xlen < 128
imm = INSN16_IMM_CS_D(insn);
- db_printf("c.fsd f%d, %d(%s)\n", rs2, (int32_t)imm,
+ db_printf("c.fsd f%d, %d(%s)\n", rs2, (int32_t)imm,
riscv_registers[rs1]);
#else
imm = INSN16_IMM_CS_Q(insn);
@@ -206,7 +206,7 @@ db_disasm_16(db_addr_t loc, uint32_t ins
rs2 = INSN16_RS2x(insn);
#if __riscv_xlen == 32
imm = INSN16_IMM_CS_W(insn);
- db_printf("c.fsw f%d, %d(%s)\n", rs2, (int32_t)imm,
+ db_printf("c.fsw f%d, %d(%s)\n", rs2, (int32_t)imm,
riscv_registers[rs1]);
#else
imm = INSN16_IMM_CS_D(insn);
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat May 1 06:45:23 UTC 2021 Modified Files: src/sys/arch/riscv/include: types.h Log Message: Make paddr_t/psize_t __uint64_t for both 32 and 64 bit ports To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/types.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/types.h diff -u src/sys/arch/riscv/include/types.h:1.10 src/sys/arch/riscv/include/types.h:1.11 --- src/sys/arch/riscv/include/types.h:1.10 Thu Apr 1 04:35:47 2021 +++ src/sys/arch/riscv/include/types.h Sat May 1 06:45:23 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: types.h,v 1.10 2021/04/01 04:35:47 simonb Exp $ */ +/* $NetBSD: types.h,v 1.11 2021/05/01 06:45:23 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -37,13 +37,15 @@ #include #if defined(_KERNEL) || defined(_KMEMUSER) || defined(_KERNTYPES) || defined(_STANDALONE) -typedef __UINTPTR_TYPE__ paddr_t; -typedef __UINTPTR_TYPE__ psize_t; + +typedef __uint64_t paddr_t; +typedef __uint64_t psize_t; +#define PRIxPADDR PRIx64 +#define PRIxPSIZE PRIx64 +#define PRIuPSIZE PRIu64 + typedef __UINTPTR_TYPE__ vaddr_t; typedef __UINTPTR_TYPE__ vsize_t; -#define PRIxPADDR PRIxPTR -#define PRIxPSIZE PRIxPTR -#define PRIuPSIZE PRIuPTR #define PRIxVADDR PRIxPTR #define PRIxVSIZE PRIxPTR #define PRIuVSIZE PRIuPTR
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Apr 20 10:15:34 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/db_disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_disasm.c
diff -u src/sys/arch/riscv/riscv/db_disasm.c:1.5 src/sys/arch/riscv/riscv/db_disasm.c:1.6
--- src/sys/arch/riscv/riscv/db_disasm.c:1.5 Tue Apr 20 10:01:37 2021
+++ src/sys/arch/riscv/riscv/db_disasm.c Tue Apr 20 10:15:34 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_disasm.c,v 1.5 2021/04/20 10:01:37 skrll Exp $ */
+/* $NetBSD: db_disasm.c,v 1.6 2021/04/20 10:15:34 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: db_disasm.c,v 1.5 2021/04/20 10:01:37 skrll Exp $");
+__RCSID("$NetBSD: db_disasm.c,v 1.6 2021/04/20 10:15:34 skrll Exp $");
#include
#include
@@ -114,8 +114,7 @@ db_print_addr(db_addr_t loc)
* 32 to 64 for RV64. (And bail on RV128 since it's not clear what
* the C type sizes are going to be there anyway...)
*/
-static
-unsigned long
+static unsigned long
maybe_signext64(uint32_t x)
{
#if __riscv_xlen == 32
@@ -130,8 +129,7 @@ maybe_signext64(uint32_t x)
#endif
}
-static
-int
+static int
db_disasm_16(db_addr_t loc, uint32_t insn, bool altfmt)
{
/* note: insn needs to be uint32_t for immediate computations */
@@ -221,16 +219,13 @@ db_disasm_16(db_addr_t loc, uint32_t ins
imm = INSN16_IMM_CI_K(insn);
if (rd == 0 && imm == 0) {
db_printf("c.nop\n");
- }
- else if (rd == 0 && imm != 0) {
+ } else if (rd == 0 && imm != 0) {
/* undefined hint */
return EINVAL;
- }
- else if (rd != 0 && imm == 0) {
+ } else if (rd != 0 && imm == 0) {
/* undefined hint */
return EINVAL;
- }
- else {
+ } else {
db_printf("c.addi %s, %s, 0x%lx\n",
riscv_registers[rd],
riscv_registers[rd],
@@ -420,11 +415,9 @@ db_disasm_16(db_addr_t loc, uint32_t ins
case Q2MISC_JR_MV:
if (rs1 == 0) {
return EINVAL;
- }
- else if (rs2 == 0) {
+ } else if (rs2 == 0) {
db_printf("c.jr %s\n", riscv_registers[rs1]);
- }
- else {
+ } else {
db_printf("c.mv %s, %s\n",
riscv_registers[rs1],
riscv_registers[rs2]);
@@ -433,14 +426,11 @@ db_disasm_16(db_addr_t loc, uint32_t ins
case Q2MISC_EBREAK_JALR_ADD:
if (rs1 == 0 && rs2 == 0) {
db_printf("c.ebreak\n");
- }
- else if (rs2 == 0) {
+ } else if (rs2 == 0) {
db_printf("c.jalr %s\n", riscv_registers[rs1]);
- }
- else if (rs1 == 0) {
+ } else if (rs1 == 0) {
return EINVAL;
- }
- else {
+ } else {
db_printf("c.add %s, %s, %s\n",
riscv_registers[rs1],
riscv_registers[rs1],
@@ -836,8 +826,7 @@ static const struct riscv_disasm32_entry
[OPCODE_X80] = { .fmt = FMT_ASSERT },
};
-static
-const struct riscv_disasm_insn *
+static const struct riscv_disasm_insn *
riscv_disasm_match(const struct riscv_disasm_insn *table, unsigned num,
uint32_t insn, uint32_t imm)
{
@@ -978,8 +967,7 @@ riscv_disasm_match(const struct riscv_di
return NULL;
}
-static
-void
+static void
db_print_riscv_fencebits(unsigned bits)
{
if (bits == 0) {
@@ -994,8 +982,7 @@ db_print_riscv_fencebits(unsigned bits)
}
}
-static
-void
+static void
db_print_riscv_reg(unsigned reg, bool isfreg)
{
if (isfreg) {
@@ -1006,8 +993,7 @@ db_print_riscv_reg(unsigned reg, bool is
}
}
-static
-const char *
+static const char *
riscv_int_size(unsigned fpsize)
{
switch (fpsize) {
@@ -1022,8 +1008,7 @@ riscv_int_size(unsigned fpsize)
}
}
-static
-const char *
+static const char *
riscv_fp_size(unsigned fpsize)
{
switch (fpsize) {
@@ -1037,8 +1022,8 @@ riscv_fp_size(unsigned fpsize)
}
}
-static
-bool larger_f_i(unsigned sz1, unsigned sz2)
+static bool
+larger_f_i(unsigned sz1, unsigned sz2)
{
switch (sz1) {
case OPFP_S:
@@ -1071,8 +1056,8 @@ bool larger_f_i(unsigned sz1, unsigned s
return false;
}
-static
-bool larger_f_f(unsigned sz1, unsigned sz2)
+static bool
+larger_f_f(unsigned sz1, unsigned sz2)
{
switch (sz1) {
case OPFP_S:
@@ -1102,8 +1087,7 @@ bool larger_f_f(unsigned sz1, unsigned s
return false;
}
-static
-void
+static void
db_print_riscv_fpround(const char *sep, unsigned round)
{
switch (round) {
@@ -1122,8 +1106,7 @@ db_print_riscv_fpround(const char *sep,
}
-static
-void
+static void
db_print_riscv_insnname(uint32_t insn, const struct riscv_disasm_insn *info)
{
db_printf("%s", info->name);
@@ -1171,8 +1154,7 @@ db_print_riscv_insnname(uint32_t insn, c
}
}
-static
-int
+static int
db_disasm_32(db_addr_t loc, uint32_t insn, bool altfmt)
{
unsigned opcode;
@@ -1217,8 +1199,7 @@ db_disasm_32(db_addr_t loc, uint32_t ins
db_printf("%s0x%x, ", sep,
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Apr 20 10:01:37 UTC 2021
Modified Files:
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
compile fixes
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_disasm.c
diff -u src/sys/arch/riscv/riscv/db_disasm.c:1.4 src/sys/arch/riscv/riscv/db_disasm.c:1.5
--- src/sys/arch/riscv/riscv/db_disasm.c:1.4 Mon Apr 19 07:55:59 2021
+++ src/sys/arch/riscv/riscv/db_disasm.c Tue Apr 20 10:01:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_disasm.c,v 1.4 2021/04/19 07:55:59 dholland Exp $ */
+/* $NetBSD: db_disasm.c,v 1.5 2021/04/20 10:01:37 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: db_disasm.c,v 1.4 2021/04/19 07:55:59 dholland Exp $");
+__RCSID("$NetBSD: db_disasm.c,v 1.5 2021/04/20 10:01:37 skrll Exp $");
#include
#include
@@ -1015,6 +1015,10 @@ riscv_int_size(unsigned fpsize)
case OPFP_WU: return ".wu";
case OPFP_L: return ".l";
case OPFP_LU: return ".lu";
+ default:
+ /* matching should prevent it coming here */
+ KASSERT(0);
+ return ".?";
}
}
@@ -1400,7 +1404,7 @@ db_disasm_32(db_addr_t loc, uint32_t ins
db_print_riscv_reg(INSN_RS2(insn),
info->printflags & RS2_FREG);
- db_printf(", ", sep);
+ db_printf("%s", sep);
db_printf("%d(", (int32_t)imm);
db_print_riscv_reg(INSN_RS1(insn),
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: dholland
Date: Mon Apr 19 07:55:59 UTC 2021
Modified Files:
src/sys/arch/riscv/include: insn.h
src/sys/arch/riscv/riscv: db_disasm.c
Log Message:
Make the riscv disassembler work, as best as I can test from amd64 userspace.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/insn.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/db_disasm.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/insn.h
diff -u src/sys/arch/riscv/include/insn.h:1.3 src/sys/arch/riscv/include/insn.h:1.4
--- src/sys/arch/riscv/include/insn.h:1.3 Wed Apr 14 06:32:20 2021
+++ src/sys/arch/riscv/include/insn.h Mon Apr 19 07:55:59 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: insn.h,v 1.3 2021/04/14 06:32:20 dholland Exp $ */
+/* $NetBSD: insn.h,v 1.4 2021/04/19 07:55:59 dholland Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -241,16 +241,16 @@ union riscv_insn {
* Quadrant 1 goes FUNCT3 -> FUNCT2a -> FUNCT3b,
* Quadrant 2 goes FUNCT3 -> FUNCT1b.
*/
-#define INSN16_FUNCT3(insn) (((insn) && 0xe000) >> 13)
-#define INSN16_FUNCT2a(insn) (((insn) && 0x0c00) >> 10)
-#define INSN16_FUNCT1b(insn) (((insn) && 0x1000) >> 12)
-#define INSN16_FUNCT2b(insn) (((insn) && 0x0060) >> 5)
+#define INSN16_FUNCT3(insn) (((insn) & 0xe000) >> 13)
+#define INSN16_FUNCT2a(insn) (((insn) & 0x0c00) >> 10)
+#define INSN16_FUNCT1b(insn) (((insn) & 0x1000) >> 12)
+#define INSN16_FUNCT2b(insn) (((insn) & 0x0060) >> 5)
#define INSN16_FUNCT3c(insn) \
((INSN16_FUNCT1b(insn) << 2) | INSN16_FUNCT2b(insn))
/* full-size register fields */
#define INSN16_RS1(insn) (((insn) & 0x0f80) >> 7) /* bits 7-11 */
-#define INSN16_RS2(insn) (((insn) & 0x007c) >> 7) /* bits 2-6 */
+#define INSN16_RS2(insn) (((insn) & 0x007c) >> 2) /* bits 2-6 */
/* small register fields, for registers 8-15 */
#define INSN16_RS1x(insn) insn) & 0x0380) >> 7) + 8) /* bits 7-9 */
@@ -422,6 +422,12 @@ union riscv_insn {
#define OPFP_D 0b01
#define OPFP_Q 0b11
+// in some instructions they're an integer operand size instead
+#define OPFP_W 0b00
+#define OPFP_WU 0b01
+#define OPFP_L 0b10
+#define OPFP_LU 0b11
+
// primary is AMO (0b01011, 11), top 5 bits
// (bottom two bits are ACQUIRE and RELEASE flags respectively)
// funct3 gives the operand size
@@ -644,7 +650,7 @@ union riscv_insn {
#define OPCODE16_Q0 0b00 /* quadrant 0 */
#define OPCODE16_Q1 0b01 /* quadrant 1 */
-#define OPCODE16_Q2 0b11 /* quadrant 2 */
+#define OPCODE16_Q2 0b10 /* quadrant 2 */
/* quadrant 0 */
#define Q0_ADDI4SPN 0b000
Index: src/sys/arch/riscv/riscv/db_disasm.c
diff -u src/sys/arch/riscv/riscv/db_disasm.c:1.3 src/sys/arch/riscv/riscv/db_disasm.c:1.4
--- src/sys/arch/riscv/riscv/db_disasm.c:1.3 Wed Apr 14 06:32:20 2021
+++ src/sys/arch/riscv/riscv/db_disasm.c Mon Apr 19 07:55:59 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_disasm.c,v 1.3 2021/04/14 06:32:20 dholland Exp $ */
+/* $NetBSD: db_disasm.c,v 1.4 2021/04/19 07:55:59 dholland Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include
-__RCSID("$NetBSD: db_disasm.c,v 1.3 2021/04/14 06:32:20 dholland Exp $");
+__RCSID("$NetBSD: db_disasm.c,v 1.4 2021/04/19 07:55:59 dholland Exp $");
#include
#include
@@ -65,6 +65,11 @@ db_print_addr(db_addr_t loc)
db_sym_t sym;
const char *symname;
+/* hack for testing since the test program is ASLR'd */
+#ifndef _KERNEL
+ loc &= 0xfff;
+#endif
+
diff = INT_MAX;
symname = NULL;
sym = db_search_symbol(loc, DB_STGY_ANY, );
@@ -101,6 +106,30 @@ db_print_addr(db_addr_t loc)
#define IN_Q1(op) COMBINE(op, OPCODE16_Q1)
#define IN_Q2(op) COMBINE(op, OPCODE16_Q2)
+/*
+ * All the 16-bit immediate bit-wrangling is done in uint32_t, which
+ * is sufficient, but on RV64 the resulting values should be printed
+ * as 64-bit. Continuing the assumption that we're disassembling for
+ * the size we're built on, do nothing for RV32 and sign-extend from
+ * 32 to 64 for RV64. (And bail on RV128 since it's not clear what
+ * the C type sizes are going to be there anyway...)
+ */
+static
+unsigned long
+maybe_signext64(uint32_t x)
+{
+#if __riscv_xlen == 32
+ return x;
+#elif __riscv_xlen == 64
+ uint64_t xx;
+
+ xx = ((x & 0x8000) ? 0x : 0) | x;
+ return xx;
+#else
+#error Oops.
+#endif
+}
+
static
int
db_disasm_16(db_addr_t loc, uint32_t insn, bool altfmt)
@@ -110,10 +139,15 @@ db_disasm_16(db_addr_t loc, uint32_t ins
uint32_t imm;
unsigned rd, rs1, rs2;
+ //warnx("toot 0x%x", insn);
switch (COMBINE(INSN16_FUNCT3(insn), INSN16_QUADRANT(insn))) {
case IN_Q0(Q0_ADDI4SPN):
rd = INSN16_RS2x(insn);
imm = INSN16_IMM_CIW(insn);
+ if (imm == 0) {
+ /* reserved (all bits 0 -> invalid) */
+ return EINVAL;
+ }
db_printf("c.addi4spn %s, 0x%x\n", riscv_registers[rd], imm);
break;
case
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: dholland
Date: Wed Apr 14 06:32:20 UTC 2021
Modified Files:
src/sys/arch/riscv/include: db_machdep.h insn.h
src/sys/arch/riscv/riscv: db_disasm.c db_machdep.c
Log Message:
Add a ddb disassembler for riscv.
builds, but not really tested yet.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/db_machdep.h \
src/sys/arch/riscv/include/insn.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/db_disasm.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/db_machdep.h
diff -u src/sys/arch/riscv/include/db_machdep.h:1.2 src/sys/arch/riscv/include/db_machdep.h:1.3
--- src/sys/arch/riscv/include/db_machdep.h:1.2 Mon Nov 6 03:47:48 2017
+++ src/sys/arch/riscv/include/db_machdep.h Wed Apr 14 06:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.h,v 1.2 2017/11/06 03:47:48 christos Exp $ */
+/* $NetBSD: db_machdep.h,v 1.3 2021/04/14 06:32:20 dholland Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -62,6 +62,17 @@ extern const uint32_t __cpu_Debugger_ins
#define BKPT_SIZE (sizeof(uint32_t)) /* size of breakpoint inst */
#define BKPT_SET(inst, addr) (BKPT_INST)
+/*
+ * XXX with the C extension there's also a 16-bit-wide breakpoint
+ * instruction, the idea being that you use it when inserting a
+ * breakpoint into a stream of 16-bit instructions, but it looks like
+ * MI ddb can't cope with having two sizes :-(
+ */
+#if 0
+#define BKPT_INST_2 0x9002
+#define BKPT_SIZE_2 (sizeof(uint16_t))
+#endif
+
#define IS_BREAKPOINT_TRAP(type, code) ((type) == CAUSE_BREAKPOINT)
#define IS_WATCHPOINT_TRAP(type, code) (0)
Index: src/sys/arch/riscv/include/insn.h
diff -u src/sys/arch/riscv/include/insn.h:1.2 src/sys/arch/riscv/include/insn.h:1.3
--- src/sys/arch/riscv/include/insn.h:1.2 Wed Nov 4 07:09:45 2020
+++ src/sys/arch/riscv/include/insn.h Wed Apr 14 06:32:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: insn.h,v 1.2 2020/11/04 07:09:45 skrll Exp $ */
+/* $NetBSD: insn.h,v 1.3 2021/04/14 06:32:20 dholland Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,8 +32,14 @@
#ifndef _RISCV_INSN_H_
#define _RISCV_INSN_H_
+/*
+ * I have corrected and updated this, but it's the wrong way to do it.
+ * It's still used by ddb_machdep.c but that code should be fixed to
+ * use the newer stuff below. - dholland
+ */
union riscv_insn {
uint32_t val;
+ /* register ops */
struct {
unsigned int r_opcode : 7;
unsigned int r_rd : 5;
@@ -42,14 +48,26 @@ union riscv_insn {
unsigned int r_rs2 : 5;
unsigned int r_funct7 : 7;
} type_r;
+ /* 32-bit shifts */
+ struct {
+ unsigned int rs32_opcode : 7;
+ unsigned int rs32_rd : 5;
+ unsigned int rs32_funct3 : 3;
+ unsigned int rs32_rs1 : 5;
+ unsigned int rs32_shamt : 5;
+ unsigned int rs32_funct7 : 7;
+ } type_rs32;
+ /* 64-bit shifts */
struct {
- unsigned int rs_opcode : 7;
- unsigned int rs_rd : 5;
- unsigned int rs_funct3 : 3;
- unsigned int rs_rs1 : 5;
- unsigned int rs_shmat : 6;
- unsigned int rs_funct6 : 6;
- } type_rs;
+ unsigned int rs64_opcode : 7;
+ unsigned int rs64_rd : 5;
+ unsigned int rs64_funct3 : 3;
+ unsigned int rs64_rs1 : 5;
+ unsigned int rs64_shamt : 6;
+ unsigned int rs64_zero : 1;
+ unsigned int rs64_funct5 : 5;
+ } type_rs64;
+ /* atomics */
struct {
unsigned int ra_opcode : 7;
unsigned int ra_rd : 5;
@@ -58,17 +76,29 @@ union riscv_insn {
unsigned int ra_rs2 : 5;
unsigned int ra_rl : 1;
unsigned int ra_aq : 1;
- unsigned int ra_funct5 : 6;
+ unsigned int ra_funct5 : 5;
} type_ra;
+ /* certain fpu ops */
struct {
unsigned int rf_opcode : 7;
unsigned int rf_rd : 5;
unsigned int rf_rm : 3;
unsigned int rf_rs1 : 5;
unsigned int rf_rs2 : 5;
- unsigned int rf_funct2 : 2;
- unsigned int rf_rs3 : 5;
+ unsigned int rf_size : 2;
+ unsigned int rf_funct5 : 5;
} type_rf;
+ /* other fpu ops */
+ struct {
+ unsigned int rf4_opcode : 7;
+ unsigned int rf4_rd : 5;
+ unsigned int rf4_rm : 3;
+ unsigned int rf4_rs1 : 5;
+ unsigned int rf4_rs2 : 5;
+ unsigned int rf4_size : 2;
+ unsigned int rf4_rs3 : 5;
+ } type_rf4;
+ /* immediates */
struct {
unsigned int i_opcode : 7;
unsigned int i_rd : 5;
@@ -76,6 +106,7 @@ union riscv_insn {
unsigned int i_rs1 : 5;
signed int i_imm11to0 : 12;
} type_i;
+ /* stores */
struct {
unsigned int s_opcode : 7;
unsigned int s_imm4_to_0 : 5;
@@ -84,33 +115,241 @@ union riscv_insn {
unsigned int s_rs2 : 5;
signed int s_imm11_to_5 : 7;
} type_s;
+ /* branches */
struct {
- unsigned int sb_opcode : 7;
- unsigned int sb_imm11 : 1;
- unsigned int sb_imm4to1 : 4;
- unsigned int sb_funct3 : 3;
- unsigned int sb_rs1 : 5;
- unsigned int sb_rs2 : 5;
- unsigned int sb_imm10to5 : 6;
- signed int sb_imm12 : 1;
- } type_sb;
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sun Nov 15 08:09:56 UTC 2020 Modified Files: src/sys/arch/riscv/include: pmap.h Log Message: This file is #define To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/pmap.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pmap.h diff -u src/sys/arch/riscv/include/pmap.h:1.6 src/sys/arch/riscv/include/pmap.h:1.7 --- src/sys/arch/riscv/include/pmap.h:1.6 Mon Aug 10 06:53:11 2020 +++ src/sys/arch/riscv/include/pmap.h Sun Nov 15 08:09:56 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pmap.h,v 1.6 2020/08/10 06:53:11 skrll Exp $ */ +/* $NetBSD: pmap.h,v 1.7 2020/11/15 08:09:56 skrll Exp $ */ /* * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc. @@ -47,7 +47,7 @@ #include -#define PMAP_SEGTABSIZE NPTEPG +#define PMAP_SEGTABSIZE NPTEPG #define NBSEG (PAGE_SIZE * NPTEPG)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sat Nov 14 13:05:14 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Improve dump_trapframe output layout and fix printing of s6/s7
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.13 src/sys/arch/riscv/riscv/trap.c:1.14
--- src/sys/arch/riscv/riscv/trap.c:1.13 Wed Nov 4 20:04:01 2020
+++ src/sys/arch/riscv/riscv/trap.c Sat Nov 14 13:05:14 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.13 2020/11/04 20:04:01 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.14 2020/11/14 13:05:14 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.13 2020/11/04 20:04:01 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.14 2020/11/14 13:05:14 skrll Exp $");
#include
#include
@@ -167,32 +167,32 @@ dump_trapframe(const struct trapframe *t
&& causenames[tf->tf_cause] != NULL)
causestr = causenames[tf->tf_cause];
(*pr)("Trapframe @ %p "
- "(cause=%d (%s), status=%#x, pc=%#16"PRIxREGISTER
- ", va=%#"PRIxREGISTER"):\n",
+ "(cause=%d (%s), status=%#x, pc=%#18" PRIxREGISTER
+ ", va=%#" PRIxREGISTER "):\n",
tf, tf->tf_cause, causestr, tf->tf_sr, tf->tf_pc, tf->tf_tval);
- (*pr)("ra=%#16"PRIxREGISTER", sp=%#16"PRIxREGISTER
- ", gp=%#16"PRIxREGISTER", tp=%#16"PRIxREGISTER"\n",
+ (*pr)("ra =%#18" PRIxREGISTER ", sp =%#18" PRIxREGISTER
+ ", gp =%#18" PRIxREGISTER ", tp =%#18" PRIxREGISTER "\n",
tf->tf_ra, tf->tf_sp, tf->tf_gp, tf->tf_tp);
- (*pr)("s0=%#16"PRIxREGISTER", s1=%#16"PRIxREGISTER
- ", s2=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n",
+ (*pr)("s0 =%#18" PRIxREGISTER ", s1 =%#18" PRIxREGISTER
+ ", s2 =%#18" PRIxREGISTER ", s3 =%#18" PRIxREGISTER "\n",
tf->tf_s0, tf->tf_s1, tf->tf_s2, tf->tf_s3);
- (*pr)("s4=%#16"PRIxREGISTER", s5=%#16"PRIxREGISTER
- ", s5=%#16"PRIxREGISTER", s3=%#16"PRIxREGISTER"\n",
- tf->tf_s4, tf->tf_s5, tf->tf_s2, tf->tf_s3);
- (*pr)("s8=%#16"PRIxREGISTER", s9=%#16"PRIxREGISTER
- ", s10=%#16"PRIxREGISTER", s11=%#16"PRIxREGISTER"\n",
+ (*pr)("s4 =%#18" PRIxREGISTER ", s5 =%#18" PRIxREGISTER
+ ", s6 =%#18" PRIxREGISTER ", s7 =%#18" PRIxREGISTER "\n",
+ tf->tf_s4, tf->tf_s5, tf->tf_s6, tf->tf_s7);
+ (*pr)("s8 =%#18" PRIxREGISTER ", s9 =%#18" PRIxREGISTER
+ ", s10=%#18" PRIxREGISTER ", s11=%#18" PRIxREGISTER "\n",
tf->tf_s8, tf->tf_s9, tf->tf_s10, tf->tf_s11);
- (*pr)("a0=%#16"PRIxREGISTER", a1=%#16"PRIxREGISTER
- ", a2=%#16"PRIxREGISTER", a3=%#16"PRIxREGISTER"\n",
+ (*pr)("a0 =%#18" PRIxREGISTER ", a1 =%#18" PRIxREGISTER
+ ", a2 =%#18" PRIxREGISTER ", a3 =%#18" PRIxREGISTER "\n",
tf->tf_a0, tf->tf_a1, tf->tf_a2, tf->tf_a3);
- (*pr)("a4=%#16"PRIxREGISTER", a5=%#16"PRIxREGISTER
- ", a5=%#16"PRIxREGISTER", a7=%#16"PRIxREGISTER"\n",
+ (*pr)("a4 =%#18" PRIxREGISTER ", a5 =%#18" PRIxREGISTER
+ ", a5 =%#18" PRIxREGISTER ", a7 =%#18" PRIxREGISTER "\n",
tf->tf_a4, tf->tf_a5, tf->tf_a6, tf->tf_a7);
- (*pr)("t0=%#16"PRIxREGISTER", t1=%#16"PRIxREGISTER
- ", t2=%#16"PRIxREGISTER", t3=%#16"PRIxREGISTER"\n",
+ (*pr)("t0 =%#18" PRIxREGISTER ", t1 =%#18" PRIxREGISTER
+ ", t2 =%#18" PRIxREGISTER ", t3 =%#18" PRIxREGISTER "\n",
tf->tf_t0, tf->tf_t1, tf->tf_t2, tf->tf_t3);
- (*pr)("t4=%#16"PRIxREGISTER", t5=%#16"PRIxREGISTER
- ", t6=%#16"PRIxREGISTER"\n",
+ (*pr)("t4 =%#18" PRIxREGISTER ", t5 =%#18" PRIxREGISTER
+ ", t6 =%#18" PRIxREGISTER "\n",
tf->tf_t4, tf->tf_t5, tf->tf_t6);
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Tue Nov 10 06:58:46 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: spl.S
Log Message:
Revamp to the point it builds, but needs more work
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/spl.S
diff -u src/sys/arch/riscv/riscv/spl.S:1.4 src/sys/arch/riscv/riscv/spl.S:1.5
--- src/sys/arch/riscv/riscv/spl.S:1.4 Wed Nov 4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/spl.S Tue Nov 10 06:58:46 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: spl.S,v 1.4 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: spl.S,v 1.5 2020/11/10 06:58:46 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,41 +32,40 @@
#include
#include "assym.h"
-__RCSID("$NetBSD: spl.S,v 1.4 2020/11/04 07:09:46 skrll Exp $")
+__RCSID("$NetBSD: spl.S,v 1.5 2020/11/10 06:58:46 skrll Exp $")
+#if notyet
.data
- .globl _C_LABEL(ipl_sr_map)
- .type _C_LABEL(ipl_sr_map), @object
+ .globl _C_LABEL(ipl_si_map)
+ .type _C_LABEL(ipl_si_map), @object
.p2align INT_SCALESHIFT
-_C_LABEL(ipl_sr_map):
- .word 0 /* IPL_NONE */
- .word 0 /* IPL_SOFTCLOCK */
- .word 0 /* IPL_SOFTBIO */
- .word 0 /* IPL_SOFTNET */
- .word 0 /* IPL_SOFTSERIAL */
- .word SR_IM /* IPL_VM */
- .word SR_IM /* IPL_SCHED */
- .word SR_IM /* IPL_DDB */
- .word SR_IM /* IPL_HIGH */
+_C_LABEL(ipl_si_map):
+ .word 0 /* IPL_NONE */
+ .word 0 /* IPL_SOFTCLOCK */
+ .word 0 /* IPL_SOFTBIO */
+ .word 0 /* IPL_SOFTNET */
+ .word 0 /* IPL_SOFTSERIAL */
+ .word SI_EXTERAL/* IPL_VM */
+ .word SI_EXTERNAL | SI_TIMER /* IPL_SCHED */
+ .word SI_EXTERNAL | SI_SOFTWARE | SI_TIMER /* IPL_HIGH */
+#endif
ENTRY_NP(splx)
// a0 = new lower IPL
+ csrci sstatus, SR_SIE // disable interrupts
PTR_L a3, L_CPU(tp) // get curcpu()
INT_L t0, CI_CPL(a3) // get current IPL
beq a0, t0, 2f
-.L_splset:
+
// a0 = new ipl
- PTR_LA t0, ipl_sr_map
- slli a1, a0, 2 // make integer index
- add t0, t0, a1 // index into table
- INT_L t0, (t0) // get new mask bits to clear
- li t2, SR_IM // get mask bits
- xor t0, t0, t2 // invert mask bits
- csrc sstatus, t2 // block everything
INT_S a0, CI_CPL(a3) // change IPL
beqz t0, 2f
- csrs sstatus, t0 // unmask appropriate bits
-2: INT_L t4, CI_SOFTINTS(a3) // get softint mask
+
+ //call riscv_do_pending_irqs
+2:
+ csrsi sstatus, SR_SIE // enable interrupts
+
+ INT_L t4, CI_SOFTINTS(a3) // get softint mask
srl t4, t4, a0 // see what softints are pending.
beqz t4, 3f // none, just return
// there are softints that need to be delivered, so instead of
@@ -74,79 +73,82 @@ ENTRY_NP(splx)
// will do a tailcall back to splx and then we can return (if there
// are no pending softints).
tail _C_LABEL(softint_deliver)
-3: ret// return (or do softints)
+3:
+ ret// return (or do softints)
END(splx)
#if IPL_NONE != 0
#error IPL_NONE is not 0
#endif
ENTRY_NP(spl0)
+ csrci sstatus, SR_SIE // disable interrupts
PTR_L a3, L_CPU(tp) // get curcpu()
- li t0, SR_IM|SR_EI // load SR_IM|EI
- csrci sstatus, SR_EI // disable interrupts
INT_S zero, CI_CPL(a3) // set current IPL to IPL_NONE
- csrs sstatus, t0 // unmask all & enable interrupts
+
+ //call riscv_do_pending_irqs
+
+ csrsi sstatus, SR_SIE // enable interrupts
// spl0() is only called rarely so the overhead of always calling
// softint_deliver is minimal.
tail _C_LABEL(softint_deliver)
END(spl0)
ENTRY_NP(splhigh)
+ csrci sstatus, SR_SIE // disable interrupts
PTR_L a3, L_CPU(tp) // get curcpu()
- INT_L a0, CI_CPL(a3) // get current IPL
- li t1, SR_IM // load SR_IM
+ INT_L a0, CI_CPL(a3) // get current IPL for return value
li t0, IPL_HIGH //
- csrc sstatus, t1 // mask all interrupts
INT_S t0, CI_CPL(a3) // set it to IPL_HIGH
+ // interrupts remain disabled???
ret
END(splhigh)
+
ENTRY_NP(splsoftclock)
- li a0, IPL_SOFTCLOCK
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_SOFTCLOCK
+ j _splraise
END(splsoftclock)
ENTRY_NP(splsoftbio)
- li a0, IPL_SOFTBIO
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_SOFTBIO
+ j _splraise
END(splsoftbio)
ENTRY_NP(splsoftnet)
- li a0, IPL_SOFTNET
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_SOFTNET
+ j _splraise
END(splsoftnet)
ENTRY_NP(splsoftserial)
- li a0, IPL_SOFTSERIAL
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_SOFTSERIAL
+ j _splraise
END(splsoftserial)
ENTRY_NP(splvm)
- li a0, IPL_VM
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_VM
+ j _splraise
END(splvm)
ENTRY_NP(splsched)
- li a0, IPL_SCHED
- PTR_L a3, L_CPU(tp) // get curcpu()
- j .L_splset
+ li t0, IPL_SCHED
+ j _splraise
END(splsched)
ENTRY_NP(splddb)
- li a0, IPL_DDB
- PTR_L a3, L_CPU(tp) // get
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Nov 8 10:08:28 UTC 2020 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix register usage To generate a diff of this commit: cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.19 src/sys/arch/riscv/riscv/locore.S:1.20 --- src/sys/arch/riscv/riscv/locore.S:1.19 Sun Nov 8 08:12:17 2020 +++ src/sys/arch/riscv/riscv/locore.S Sun Nov 8 10:08:28 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.19 2020/11/08 08:12:17 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.20 2020/11/08 10:08:28 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -60,7 +60,7 @@ ENTRY_NP(start) add s1, s1, s10 // PAGE_SIZE addi s1, s1, -1 // -1 == PAGE_MASK - neg a1, a0 // -PAGE_SIZE + neg a1, s10 // -PAGE_SIZE and s1, s1, a1 // s1 is page aligned end of kernel // s1 = uarea add s2, s1, s9 // s2 = first PDE page
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Nov 8 08:12:17 UTC 2020 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix a typo To generate a diff of this commit: cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.18 src/sys/arch/riscv/riscv/locore.S:1.19 --- src/sys/arch/riscv/riscv/locore.S:1.18 Sun Nov 8 08:11:15 2020 +++ src/sys/arch/riscv/riscv/locore.S Sun Nov 8 08:12:17 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.18 2020/11/08 08:11:15 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.19 2020/11/08 08:12:17 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -67,7 +67,7 @@ ENTRY_NP(start) #ifdef _LP64 add s3, s2, s10 // s3 = second PDE page (RV64 only) #else - mv s3, 22 + mv s3, s2 #endif add s4, s3, s10 // s4 = first kernel PTE page add s5, s1, s9 // s5 = kernel_end
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Nov 8 08:11:15 UTC 2020 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Remove unnecessary local labels To generate a diff of this commit: cvs rdiff -u -r1.17 -r1.18 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.17 src/sys/arch/riscv/riscv/locore.S:1.18 --- src/sys/arch/riscv/riscv/locore.S:1.17 Sun Nov 8 08:07:43 2020 +++ src/sys/arch/riscv/riscv/locore.S Sun Nov 8 08:11:15 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.17 2020/11/08 08:07:43 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.18 2020/11/08 08:11:15 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -77,7 +77,7 @@ ENTRY_NP(start) // As a temporary hack, word 0 contains the amount of memory in MB INT_L a7, (zero) // load memory size slli a7, a7, (20-PGSHIFT) // convert MB to pages -.L01: PTR_LA t0, physmem + PTR_LA t0, physmem INT_S a7, (t0) // store it in physmem li t4, PTE_V | PTE_SX | PTE_SW | PTE_SR | PTE_G @@ -440,7 +440,7 @@ _C_LABEL(exception_userexit): j exception_kernexit trap_syscall: -.L0: PTR_LA ra, exception_userexit + PTR_LA ra, exception_userexit PTR_L t0, L_PROC(tp) // get proc struct PTR_L t0, P_MD_SYSCALL(t0) // get syscall address from proc jr t0 // and jump to it
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sun Nov 8 08:07:43 UTC 2020 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Use correct instruction to load address of exception_userexit into RA To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.16 src/sys/arch/riscv/riscv/locore.S:1.17 --- src/sys/arch/riscv/riscv/locore.S:1.16 Wed Nov 4 20:05:47 2020 +++ src/sys/arch/riscv/riscv/locore.S Sun Nov 8 08:07:43 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.16 2020/11/04 20:05:47 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.17 2020/11/08 08:07:43 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -440,7 +440,7 @@ _C_LABEL(exception_userexit): j exception_kernexit trap_syscall: -.L0: PTR_L ra, exception_userexit +.L0: PTR_LA ra, exception_userexit PTR_L t0, L_PROC(tp) // get proc struct PTR_L t0, P_MD_SYSCALL(t0) // get syscall address from proc jr t0 // and jump to it
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sat Nov 7 14:48:46 UTC 2020 Modified Files: src/sys/arch/riscv/include: vmparam.h Log Message: Use lower case for hex constants To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/vmparam.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/vmparam.h diff -u src/sys/arch/riscv/include/vmparam.h:1.6 src/sys/arch/riscv/include/vmparam.h:1.7 --- src/sys/arch/riscv/include/vmparam.h:1.6 Tue Oct 6 13:42:03 2020 +++ src/sys/arch/riscv/include/vmparam.h Sat Nov 7 14:48:45 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: vmparam.h,v 1.6 2020/10/06 13:42:03 christos Exp $ */ +/* $NetBSD: vmparam.h,v 1.7 2020/11/07 14:48:45 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -106,12 +106,12 @@ #define VM_MIN_ADDRESS ((vaddr_t)0x) #ifdef _LP64 /* Sv39 */ #define VM_MAXUSER_ADDRESS ((vaddr_t)0x0040 - 16 * PAGE_SIZE) -#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0xFFC0) -#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xFFD0) /* MIN + 64GB */ +#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0xffc0) +#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xffd0) /* MIN + 64GB */ #else /* Sv32 */ -#define VM_MAXUSER_ADDRESS ((vaddr_t)-0x7fff-1)/* 0x8000 */ -#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)-0x7fff-1)/* 0x8000 */ -#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x4000) /* 0xC000 */ +#define VM_MAXUSER_ADDRESS ((vaddr_t)-0x7fff-1)/* 0x8000 */ +#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)-0x7fff-1)/* 0x8000 */ +#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x4000) /* 0xc000 */ #endif #define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS #define VM_MAXUSER_ADDRESS32 ((vaddr_t)(1UL << 31))/* 0x8000 */
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:48:17 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.7 src/sys/arch/riscv/include/reg.h:1.8
--- src/sys/arch/riscv/include/reg.h:1.7 Sat Nov 7 10:47:35 2020
+++ src/sys/arch/riscv/include/reg.h Sat Nov 7 10:48:17 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.7 2020/11/07 10:47:35 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.8 2020/11/07 10:48:17 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -108,8 +108,8 @@ struct reg32 { // synced with register_t
*/
#ifndef _BSD_FPREG_T_
union __fpreg {
- __uint64_t u_u64;
- double u_d;
+ __uint64_t u_u64;
+ double u_d;
};
#define _BSD_FPREG_T_ union __fpreg
#endif
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:47:35 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Indent and annotate FP registers much like the general registers
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.6 src/sys/arch/riscv/include/reg.h:1.7
--- src/sys/arch/riscv/include/reg.h:1.6 Sat Nov 7 10:43:47 2020
+++ src/sys/arch/riscv/include/reg.h Sat Nov 7 10:47:35 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.6 2020/11/07 10:43:47 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.7 2020/11/07 10:47:35 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -95,13 +95,13 @@ struct reg32 { // synced with register_t
#define _X_T5 _XREG(30)
#define _X_T6 _XREG(31)
-// f0-f7 = ft0-ft7 (FP temporaries)
+// f0 - f7 = ft0 - ft7 (FP temporaries) Caller
// following layout is similar to integer registers above
-// f8-f9 = fs0-fs1 (FP saved registers)
-// f10-f11 = fa0-fa1 (FP arguments/return values)
-// f12-f17 = fa2-fa7 (FP arguments)
-// f18-f27 = fs2-fa11 (FP saved registers)
-// f28-f31 = ft8-ft11 (FP temporaries)
+// f8 - f9 = fs0 - fs1 (FP saved registers) Callee
+// f10 - f11 = fa0 - fa1 (FP arguments/return values) Caller
+// f12 - f17 = fa2 - fa7 (FP arguments) Caller
+// f18 - f27 = fs2 - fa11 (FP saved registers) Callee
+// f28 - f31 = ft8 - ft11 (FP temporaries) Caller
/*
* This fragment is common to and
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Sat Nov 7 10:43:47 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Note if a register is Caller / Callee saved
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.5 src/sys/arch/riscv/include/reg.h:1.6
--- src/sys/arch/riscv/include/reg.h:1.5 Wed Nov 4 07:41:34 2020
+++ src/sys/arch/riscv/include/reg.h Sat Nov 7 10:43:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.5 2020/11/04 07:41:34 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.6 2020/11/07 10:43:47 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -33,17 +33,17 @@
#define _RISCV_REG_H_
// x0 = 0
-// x1 = ra (return address)
-// x2 = sp (stack pointer)
+// x1 = ra (return address) Caller
+// x2 = sp (stack pointer) Callee
// x3 = gp (global pointer)
// x4 = tp (thread pointer)
-// x5 - x7 = t0 - t2 (temporary)
-// x8 = s0/fp (saved register / frame pointer)
-// x9 = s1 (saved register)
-// x10 - x11 = a0 - a1 (arguments/return values)
-// x12 - x17 = a2 - a7 (arguments)
-// x18 - x27 = s2 - s11 (saved registers)
-// x28 - x31 = t3 - r6 (temporaries)
+// x5 - x7 = t0 - t2 (temporary) Caller
+// x8 = s0/fp (saved register / frame pointer) Callee
+// x9 = s1 (saved register) Callee
+// x10 - x11 = a0 - a1 (arguments/return values) Caller
+// x12 - x17 = a2 - a7 (arguments) Caller
+// x18 - x27 = s2 - s11 (saved registers) Callee
+// x28 - x31 = t3 - r6 (temporaries) Caller
struct reg { // synced with register_t in
#ifdef _LP64
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Wed Nov 4 20:05:47 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
src/sys/arch/riscv/riscv: genassym.cf locore.S riscv_machdep.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/genassym.cf
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.9 src/sys/arch/riscv/include/sysreg.h:1.10
--- src/sys/arch/riscv/include/sysreg.h:1.9 Wed Nov 4 06:56:56 2020
+++ src/sys/arch/riscv/include/sysreg.h Wed Nov 4 20:05:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.9 2020/11/04 06:56:56 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.10 2020/11/04 20:05:47 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -167,12 +167,12 @@ riscvreg_fcsr_write_frm(uint32_t __new)
#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
#ifdef _LP64
-#define SR_USER (SR_UIE | SR_U64 | SR_S64 | SR_IM)
-#define SR_USER32 (SR_USER & ~SR_U64)
-#define SR_KERNEL (SR_S | SR_UIE | SR_U64 | SR_S64)
+#define SR_USER (SR_UIE)
+#define SR_USER32 (SR_USER)
+#define SR_KERNEL (SR_SIE | SR_UIE)
#else
-#define SR_USER (SR_UIE||SR_IM)
-#define SR_KERNEL (SR_S|SR_UIE)
+#define SR_USER (SR_UIE)
+#define SR_KERNEL (SR_SIE | SR_UIE)
#endif
static inline uint32_t
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.9 src/sys/arch/riscv/riscv/genassym.cf:1.10
--- src/sys/arch/riscv/riscv/genassym.cf:1.9 Wed Nov 4 07:51:08 2020
+++ src/sys/arch/riscv/riscv/genassym.cf Wed Nov 4 20:05:47 2020
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.9 2020/11/04 07:51:08 skrll Exp $
+# $NetBSD: genassym.cf,v 1.10 2020/11/04 20:05:47 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -62,6 +62,14 @@ define SR_SIE SR_SIE
define CAUSE_SYSCALL CAUSE_SYSCALL
+ifdef _LP64
+define SATP_MODE_MASK SATP_MODE
+define SATP_MODE_SV39 __SHIFTIN(SATP_MODE_SV39, SATP_MODE)
+define SATP_MODE_SV48 __SHIFTIN(SATP_MODE_SV48, SATP_MODE)
+else
+define SATP_MODE_SV32 __SHIFTIN(SATP_MODE_SV32, SATP_MODE)
+endif
+
define IPL_HIGH IPL_HIGH
define IPL_DDB IPL_DDB
define IPL_SCHED IPL_SCHED
@@ -108,7 +116,7 @@ define TF_T6 offsetof(struct trapframe,
define TF_GP offsetof(struct trapframe, tf_reg[_X_GP])
define TF_PC offsetof(struct trapframe, tf_pc)
define TF_CAUSE offsetof(struct trapframe, tf_cause)
-define TF_TVA L offsetof(struct trapframe, tf_tval)
+define TF_TVAL offsetof(struct trapframe, tf_tval)
define TF_SR offsetof(struct trapframe, tf_sr)
define L_CPU offsetof(struct lwp, l_cpu)
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.15 src/sys/arch/riscv/riscv/locore.S:1.16
--- src/sys/arch/riscv/riscv/locore.S:1.15 Wed Nov 4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/locore.S Wed Nov 4 20:05:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.15 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.16 2020/11/04 20:05:47 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -39,15 +39,6 @@ ENTRY_NP(start)
// We get loaded and starting running at or near 0, not where we
// should be. We need to construct an initial PDETAB
-#ifdef _LP64
- li t0, SR_U64|SR_S64
- li t1, SR_IM|SR_SIE
- csrs sstatus, t0
-#else
- li t1, SR_IM|SR_U64|SR_S64|SR_EI
-#endif
- csrc sstatus, t1
-
li s11, VM_MAX_KERNEL_ADDRESS
li s10, PAGE_SIZE
li s9, USPACE
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.12 src/sys/arch/riscv/riscv/riscv_machdep.c:1.13
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.12 Wed Nov 4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Wed Nov 4 20:05:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.12 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $ */
/*-
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_modular.h"
-__RCSID("$NetBSD: riscv_machdep.c,v 1.12 2020/11/04 07:09:46 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $");
#include
#include
@@ -124,7 +124,9 @@ md_child_return(struct lwp *l)
tf->tf_a0 = 0;
tf->tf_a1 = 1;
+#ifdef FPE
tf->tf_sr &= ~SR_EF; /* Disable FP as we can't be them. */
+#endif
}
void
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Wed Nov 4 20:04:01 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c vm_machdep.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/trap.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/vm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.12 src/sys/arch/riscv/riscv/trap.c:1.13
--- src/sys/arch/riscv/riscv/trap.c:1.12 Wed Nov 4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/trap.c Wed Nov 4 20:04:01 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.12 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.13 2020/11/04 20:04:01 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.12 2020/11/04 07:09:46 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.13 2020/11/04 20:04:01 skrll Exp $");
#include
#include
@@ -372,7 +372,7 @@ cpu_trap(struct trapframe *tf, register_
{
const u_int fault_mask = 1U << cause;
const intptr_t addr = tval;
- const bool usertrap_p = (status & SR_PS) == 0;
+ const bool usertrap_p = (status & SR_SPP) == 0;
bool ok = true;
ksiginfo_t ksi;
Index: src/sys/arch/riscv/riscv/vm_machdep.c
diff -u src/sys/arch/riscv/riscv/vm_machdep.c:1.3 src/sys/arch/riscv/riscv/vm_machdep.c:1.4
--- src/sys/arch/riscv/riscv/vm_machdep.c:1.3 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/riscv/vm_machdep.c Wed Nov 4 20:04:01 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: vm_machdep.c,v 1.3 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: vm_machdep.c,v 1.4 2020/11/04 20:04:01 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.3 2020/03/14 16:12:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vm_machdep.c,v 1.4 2020/11/04 20:04:01 skrll Exp $");
#define _PMAP_PRIVATE
@@ -91,7 +91,9 @@ cpu_lwp_fork(struct lwp *l1, struct lwp
vaddr_t ua2 = uvm_lwp_getuarea(l2);
tf = (struct trapframe *)(ua2 + USPACE) - 1;
*tf = *l1->l_md.md_utf;
+#ifdef FPE
tf->tf_sr &= ~SR_EF; /* floating point must be disabled */
+#endif
/* If specified, set a different user stack for a child. */
if (stack != NULL) {
@@ -114,12 +116,8 @@ cpu_lwp_fork(struct lwp *l1, struct lwp
tf->tf_s0 = (intptr_t)func; /* S0 */
tf->tf_s1 = (intptr_t)arg; /* S1 */
tf->tf_ra = (intptr_t)cpu_lwp_trampoline; /* RA */
- l2->l_md.md_ktf = tf; /* SP */
- KASSERT(tf->tf_sr & SR_S);
-#ifdef _LP64
- KASSERT(tf->tf_sr & SR_S64);
-#endif
- KASSERT(tf->tf_sr & SR_EI);
+ l2->l_md.md_ktf = tf;/* SP */
+ KASSERT(tf->tf_sr & SR_SIE);
}
/*
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:51:09 UTC 2020
Modified Files:
src/sys/arch/riscv/include: frame.h
src/sys/arch/riscv/riscv: genassym.cf
Log Message:
Fix some of the previous - I must have compile tested the wrong tree
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/frame.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/genassym.cf
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/frame.h
diff -u src/sys/arch/riscv/include/frame.h:1.3 src/sys/arch/riscv/include/frame.h:1.4
--- src/sys/arch/riscv/include/frame.h:1.3 Wed Nov 4 06:56:56 2020
+++ src/sys/arch/riscv/include/frame.h Wed Nov 4 07:51:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.3 2020/11/04 06:56:56 skrll Exp $ */
+/* $NetBSD: frame.h,v 1.4 2020/11/04 07:51:08 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,9 +36,9 @@
struct trapframe {
struct reg tf_regs __aligned(8);
- register_t tf_stval; // supervisor trap value
- register_t tf_sepc; // supervisor exception program counter
- register_t tf_scause; // supervisor cause register
+ register_t tf_tval; // supervisor trap value
+ register_t tf_pc; // supervisor exception program counter
+ register_t tf_cause; // supervisor cause register
register_t tf_sr; // supervisor status register
#define tf_reg tf_regs.r_reg
#define tf_a0 tf_reg[_X_A0]
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.8 src/sys/arch/riscv/riscv/genassym.cf:1.9
--- src/sys/arch/riscv/riscv/genassym.cf:1.8 Wed Nov 4 06:56:56 2020
+++ src/sys/arch/riscv/riscv/genassym.cf Wed Nov 4 07:51:08 2020
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.8 2020/11/04 06:56:56 skrll Exp $
+# $NetBSD: genassym.cf,v 1.9 2020/11/04 07:51:08 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -107,8 +107,8 @@ define TF_T5 offsetof(struct trapframe,
define TF_T6 offsetof(struct trapframe, tf_reg[_X_T6])
define TF_GP offsetof(struct trapframe, tf_reg[_X_GP])
define TF_PC offsetof(struct trapframe, tf_pc)
-define TF_SCAUSE offsetof(struct trapframe, tf_scause)
-define TF_STVAL offsetof(struct trapframe, tf_stval)
+define TF_CAUSE offsetof(struct trapframe, tf_cause)
+define TF_TVA L offsetof(struct trapframe, tf_tval)
define TF_SR offsetof(struct trapframe, tf_sr)
define L_CPU offsetof(struct lwp, l_cpu)
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:41:34 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
whitespace in comments
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.4 src/sys/arch/riscv/include/reg.h:1.5
--- src/sys/arch/riscv/include/reg.h:1.4 Wed Nov 4 07:40:15 2020
+++ src/sys/arch/riscv/include/reg.h Wed Nov 4 07:41:34 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.4 2020/11/04 07:40:15 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.5 2020/11/04 07:41:34 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -32,18 +32,18 @@
#ifndef _RISCV_REG_H_
#define _RISCV_REG_H_
-// x0 = 0
-// x1 = ra (return address)
-// x2 = sp (stack pointer)
-// x3 = gp (global pointer)
-// x4 = tp (thread pointer)
-// x5-x7 = t0-t2 (temporary)
-// x8 = s0/fp (saved register / frame pointer)
-// x9 = s1 (saved register)
-// x10-x11 = a0-a1 (arguments/return values)
-// x12-x17 = a2-a7 (arguments)
-// x18-x27 = s2-s11 (saved registers)
-// x28-x31 = t3-r6 (temporaries)
+// x0 = 0
+// x1 = ra (return address)
+// x2 = sp (stack pointer)
+// x3 = gp (global pointer)
+// x4 = tp (thread pointer)
+// x5 - x7 = t0 - t2 (temporary)
+// x8 = s0/fp (saved register / frame pointer)
+// x9 = s1 (saved register)
+// x10 - x11 = a0 - a1 (arguments/return values)
+// x12 - x17 = a2 - a7 (arguments)
+// x18 - x27 = s2 - s11 (saved registers)
+// x28 - x31 = t3 - r6 (temporaries)
struct reg { // synced with register_t in
#ifdef _LP64
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:40:15 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.3 src/sys/arch/riscv/include/reg.h:1.4
--- src/sys/arch/riscv/include/reg.h:1.3 Wed Nov 4 06:24:44 2020
+++ src/sys/arch/riscv/include/reg.h Wed Nov 4 07:40:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.3 2020/11/04 06:24:44 skrll Exp $ */
+/* $NetBSD: reg.h,v 1.4 2020/11/04 07:40:15 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -42,7 +42,7 @@
// x9 = s1 (saved register)
// x10-x11 = a0-a1 (arguments/return values)
// x12-x17 = a2-a7 (arguments)
-// x18-r27 = s2-s11 (saved registers)
+// x18-x27 = s2-s11 (saved registers)
// x28-x31 = t3-r6 (temporaries)
struct reg { // synced with register_t in
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Wed Nov 4 07:09:46 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: kern.ldscript
src/sys/arch/riscv/htif: htif.c htif_cons.c htif_disk.c htif_var.h
src/sys/arch/riscv/include: insn.h locore.h
src/sys/arch/riscv/riscv: autoconf.c clock_machdep.c core_machdep.c
cpu_mainbus.c cpu_subr.c db_disasm.c db_machdep.c db_trace.c
exec_machdep.c fixup.c kobj_machdep.c locore.S mainbus.c
netbsd32_machdep.c process_machdep.c procfs_machdep.c
riscv_machdep.c sig_machdep.c softint_machdep.c spl.S stubs.c
sys_machdep.c trap.c
Log Message:
RCSID and whitespace police...
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/kern.ldscript
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/htif/htif.c \
src/sys/arch/riscv/htif/htif_cons.c src/sys/arch/riscv/htif/htif_disk.c \
src/sys/arch/riscv/htif/htif_var.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/insn.h
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/locore.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/autoconf.c \
src/sys/arch/riscv/riscv/cpu_mainbus.c \
src/sys/arch/riscv/riscv/cpu_subr.c src/sys/arch/riscv/riscv/db_disasm.c \
src/sys/arch/riscv/riscv/db_trace.c \
src/sys/arch/riscv/riscv/exec_machdep.c src/sys/arch/riscv/riscv/fixup.c \
src/sys/arch/riscv/riscv/mainbus.c \
src/sys/arch/riscv/riscv/softint_machdep.c \
src/sys/arch/riscv/riscv/stubs.c src/sys/arch/riscv/riscv/sys_machdep.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/clock_machdep.c \
src/sys/arch/riscv/riscv/procfs_machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/core_machdep.c \
src/sys/arch/riscv/riscv/netbsd32_machdep.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/db_machdep.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/kobj_machdep.c \
src/sys/arch/riscv/riscv/process_machdep.c \
src/sys/arch/riscv/riscv/sig_machdep.c src/sys/arch/riscv/riscv/spl.S
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/riscv/riscv_machdep.c \
src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/kern.ldscript
diff -u src/sys/arch/riscv/conf/kern.ldscript:1.6 src/sys/arch/riscv/conf/kern.ldscript:1.7
--- src/sys/arch/riscv/conf/kern.ldscript:1.6 Sun Jun 16 07:42:52 2019
+++ src/sys/arch/riscv/conf/kern.ldscript Wed Nov 4 07:09:45 2020
@@ -1,3 +1,5 @@
+/* $NetBSD: kern.ldscript,v 1.7 2020/11/04 07:09:45 skrll Exp $ */
+
OUTPUT_ARCH(riscv)
ENTRY(start)
Index: src/sys/arch/riscv/htif/htif.c
diff -u src/sys/arch/riscv/htif/htif.c:1.1 src/sys/arch/riscv/htif/htif.c:1.2
--- src/sys/arch/riscv/htif/htif.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/htif/htif.c Wed Nov 4 07:09:45 2020
@@ -1,3 +1,5 @@
+/* $NetBSD: htif.c,v 1.2 2020/11/04 07:09:45 skrll Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +31,7 @@
#include
-__RCSID("$NetBSD: htif.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__RCSID("$NetBSD: htif.c,v 1.2 2020/11/04 07:09:45 skrll Exp $");
#include
#include
Index: src/sys/arch/riscv/htif/htif_cons.c
diff -u src/sys/arch/riscv/htif/htif_cons.c:1.1 src/sys/arch/riscv/htif/htif_cons.c:1.2
--- src/sys/arch/riscv/htif/htif_cons.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/htif/htif_cons.c Wed Nov 4 07:09:45 2020
@@ -1,3 +1,5 @@
+/* $NetBSD: htif_cons.c,v 1.2 2020/11/04 07:09:45 skrll Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +31,7 @@
#include
-__RCSID("$NetBSD: htif_cons.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__RCSID("$NetBSD: htif_cons.c,v 1.2 2020/11/04 07:09:45 skrll Exp $");
#include
#include
Index: src/sys/arch/riscv/htif/htif_disk.c
diff -u src/sys/arch/riscv/htif/htif_disk.c:1.1 src/sys/arch/riscv/htif/htif_disk.c:1.2
--- src/sys/arch/riscv/htif/htif_disk.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/htif/htif_disk.c Wed Nov 4 07:09:45 2020
@@ -1,3 +1,5 @@
+/* $NetBSD: htif_disk.c,v 1.2 2020/11/04 07:09:45 skrll Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +31,7 @@
#include
-__RCSID("$NetBSD: htif_disk.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__RCSID("$NetBSD: htif_disk.c,v 1.2 2020/11/04 07:09:45 skrll Exp $");
#include
#include
Index: src/sys/arch/riscv/htif/htif_var.h
diff -u src/sys/arch/riscv/htif/htif_var.h:1.1 src/sys/arch/riscv/htif/htif_var.h:1.2
--- src/sys/arch/riscv/htif/htif_var.h:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/htif/htif_var.h Wed Nov 4 07:09:45 2020
@@ -1,4 +1,5 @@
-/* $NetBSD: htif_var.h,v 1.1 2015/03/28 16:13:56 matt Exp $ */
+/* $NetBSD: htif_var.h,v 1.2 2020/11/04
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Wed Nov 4 06:56:56 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: GENERIC files.riscv
src/sys/arch/riscv/include: frame.h locore.h sysreg.h
src/sys/arch/riscv/riscv: core_machdep.c db_machdep.c genassym.cf
locore.S trap.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/frame.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/locore.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/core_machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_machdep.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/genassym.cf
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/GENERIC
diff -u src/sys/arch/riscv/conf/GENERIC:1.10 src/sys/arch/riscv/conf/GENERIC:1.11
--- src/sys/arch/riscv/conf/GENERIC:1.10 Sat Jun 1 12:42:27 2019
+++ src/sys/arch/riscv/conf/GENERIC Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.10 2019/06/01 12:42:27 maxv Exp $
+# $NetBSD: GENERIC,v 1.11 2020/11/04 06:56:56 skrll Exp $
#
# GENERIC machine description file
#
@@ -22,12 +22,12 @@ include "arch/riscv/conf/std.riscv64"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.10 $"
+#ident "GENERIC-$Revision: 1.11 $"
maxusers 64 # estimated number of users
# Standard system options
-
+#options FPE # Floating-point extension support
options NTP # NTP phase/frequency locked loop
options KTRACE # system call tracing via ktrace(1)
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.6 src/sys/arch/riscv/conf/files.riscv:1.7
--- src/sys/arch/riscv/conf/files.riscv:1.6 Wed Oct 21 13:31:51 2020
+++ src/sys/arch/riscv/conf/files.riscv Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.6 2020/10/21 13:31:51 christos Exp $
+# $NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
#
maxpartitions 16
@@ -14,7 +14,7 @@ file arch/riscv/riscv/cpu_subr.c
file arch/riscv/riscv/db_disasm.c ddb
file arch/riscv/riscv/db_trace.c ddb
file arch/riscv/riscv/fixup.c
-file arch/riscv/riscv/fpu.c
+file arch/riscv/riscv/fpu.c fpe
file arch/riscv/riscv/ipifuncs.c multiprocessor
file arch/riscv/riscv/stubs.c
file arch/riscv/riscv/syscall.c # syscall handler
Index: src/sys/arch/riscv/include/frame.h
diff -u src/sys/arch/riscv/include/frame.h:1.2 src/sys/arch/riscv/include/frame.h:1.3
--- src/sys/arch/riscv/include/frame.h:1.2 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/frame.h Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.2 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: frame.h,v 1.3 2020/11/04 06:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,10 +36,10 @@
struct trapframe {
struct reg tf_regs __aligned(8);
- register_t tf_badvaddr;
- register_t tf_pc;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register_t tf_stval; // supervisor trap value
+ register_t tf_sepc; // supervisor exception program counter
+ register_t tf_scause; // supervisor cause register
+ register_t tf_sr; // supervisor status register
#define tf_reg tf_regs.r_reg
#define tf_a0 tf_reg[_X_A0]
#define tf_t0 tf_reg[_X_T0]
Index: src/sys/arch/riscv/include/locore.h
diff -u src/sys/arch/riscv/include/locore.h:1.5 src/sys/arch/riscv/include/locore.h:1.6
--- src/sys/arch/riscv/include/locore.h:1.5 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/locore.h Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.6 2020/11/04 06:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,9 +39,9 @@
struct trapframe {
struct reg tf_regs;
- register_t tf_badaddr;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register_t tf_tval;
+ register_t tf_cause;
+ register_t tf_sr;
#define tf_reg tf_regs.r_reg
#define tf_pc tf_regs.r_pc
#define tf_ra tf_reg[_X_RA]
@@ -80,9 +80,9 @@ struct trapframe {
// For COMPAT_NETBSD32 coredumps
struct trapframe32 {
struct reg32 tf_regs;
- register32_t tf_badaddr;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register32_t tf_tval;
+ register32_t tf_cause;
+ register32_t tf_sr;
};
#define FB_A0 0
@@ -105,7 +105,7 @@ struct trapframe32 {
struct
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Wed Nov 4 06:24:44 UTC 2020
Modified Files:
src/sys/arch/riscv/include: reg.h
Log Message:
Remove incorrect comment
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/reg.h
diff -u src/sys/arch/riscv/include/reg.h:1.2 src/sys/arch/riscv/include/reg.h:1.3
--- src/sys/arch/riscv/include/reg.h:1.2 Fri Mar 27 06:57:21 2015
+++ src/sys/arch/riscv/include/reg.h Wed Nov 4 06:24:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: reg.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */
+/* $NetBSD: reg.h,v 1.3 2020/11/04 06:24:44 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -44,7 +44,6 @@
// x12-x17 = a2-a7 (arguments)
// x18-r27 = s2-s11 (saved registers)
// x28-x31 = t3-r6 (temporaries)
-// x26-x30 = t0-t4 (temporary)
struct reg { // synced with register_t in
#ifdef _LP64
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Nov 2 08:37:59 UTC 2020 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Add SATP_MODE values To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.7 src/sys/arch/riscv/include/sysreg.h:1.8 --- src/sys/arch/riscv/include/sysreg.h:1.7 Mon Nov 2 08:36:54 2020 +++ src/sys/arch/riscv/include/sysreg.h Mon Nov 2 08:37:59 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.7 2020/11/02 08:36:54 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.8 2020/11/02 08:37:59 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -198,10 +198,13 @@ riscvreg_cycle_read(void) #ifdef _LP64 #define SATP_MODE __BITS(63,60) +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 #define SATP_ASID __BITS(59,44) #define SATP_PPN __BITS(43,0) #else #define SATP_MODE __BIT(31) +#define SATP_MODE_SV32 1 #define SATP_ASID __BITS(30,22) #define SATP_PPN __BITS(21,0) #endif
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Mon Nov 2 08:36:54 UTC 2020 Modified Files: src/sys/arch/riscv/include: sysreg.h Log Message: Whitespace To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/include/sysreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/sysreg.h diff -u src/sys/arch/riscv/include/sysreg.h:1.6 src/sys/arch/riscv/include/sysreg.h:1.7 --- src/sys/arch/riscv/include/sysreg.h:1.6 Sun Nov 1 21:09:48 2020 +++ src/sys/arch/riscv/include/sysreg.h Mon Nov 2 08:36:54 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: sysreg.h,v 1.6 2020/11/01 21:09:48 skrll Exp $ */ +/* $NetBSD: sysreg.h,v 1.7 2020/11/02 08:36:54 skrll Exp $ */ /* * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -197,13 +197,13 @@ riscvreg_cycle_read(void) } #ifdef _LP64 -#define SATP_MODE __BITS(63,60) -#define SATP_ASID __BITS(59,44) -#define SATP_PPN __BITS(43,0) +#define SATP_MODE __BITS(63,60) +#define SATP_ASID __BITS(59,44) +#define SATP_PPN __BITS(43,0) #else -#define SATP_MODE __BIT(31) -#define SATP_ASID __BITS(30,22) -#define SATP_PPN __BITS(21,0) +#define SATP_MODE __BIT(31) +#define SATP_ASID __BITS(30,22) +#define SATP_PPN __BITS(21,0) #endif static inline uint32_t
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:09:48 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
src/sys/arch/riscv/riscv: trap.c
Log Message:
Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.5 src/sys/arch/riscv/include/sysreg.h:1.6
--- src/sys/arch/riscv/include/sysreg.h:1.5 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/sysreg.h Sun Nov 1 21:09:48 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.6 2020/11/01 21:09:48 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -155,18 +155,24 @@ riscvreg_status_set(uint32_t __mask)
}
// Cause register
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
+#define CAUSE_FETCH_MISALIGNED 0
+#define CAUSE_FETCH_ACCESS 1
#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_MISALIGNED_LOAD 4
-#define CAUSE_FAULT_LOAD 5
-#define CAUSE_MISALIGNED_STORE 6
-#define CAUSE_FAULT_STORE 7
+#define CAUSE_BREAKPOINT 3
+#define CAUSE_LOAD_MISALIGNED 4
+#define CAUSE_LOAD_ACCESS 5
+#define CAUSE_STORE_MISALIGNED 6
+#define CAUSE_STORE_ACCESS 7
#define CAUSE_SYSCALL 8
-#define CAUSE_BREAKPOINT 9
-#define CAUSE_FP_DISABLED 10
-#define CAUSE_ACCELERATOR_DISABLED 12
+#define CAUSE_USER_ECALL 8
+#define CAUSE_SUPERVISOR_ECALL 9
+/* 10 is reserved */
+#define CAUSE_MACHINE_ECALL 11
+#define CAUSE_FETCH_PAGE_FAULT 12
+#define CAUSE_LOAD_PAGE_FAULT 13
+/* 14 is Reserved */
+#define CAUSE_STORE_PAGE_FAULT 15
+/* >= 16 is reserved */
static inline uint64_t
riscvreg_cycle_read(void)
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.9 src/sys/arch/riscv/riscv/trap.c:1.10
--- src/sys/arch/riscv/riscv/trap.c:1.9 Sun Nov 1 21:06:22 2020
+++ src/sys/arch/riscv/riscv/trap.c Sun Nov 1 21:09:48 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.9 2020/11/01 21:06:22 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.10 2020/11/01 21:09:48 skrll Exp $");
#include
#include
@@ -46,27 +46,24 @@ __RCSID("$NetBSD: trap.c,v 1.9 2020/11/0
#include
-#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_PRIVILEGED_INSTRUCTION) \
-|__BIT(CAUSE_ILLEGAL_INSTRUCTION))
+#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_ILLEGAL_INSTRUCTION))
-#define FAULT_TRAP_MASK (__BIT(CAUSE_FAULT_FETCH) \
-|__BIT(CAUSE_FAULT_LOAD) \
-|__BIT(CAUSE_FAULT_STORE))
-
-#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_MISALIGNED_FETCH) \
-|__BIT(CAUSE_MISALIGNED_LOAD) \
-|__BIT(CAUSE_MISALIGNED_STORE))
+#define FAULT_TRAP_MASK (__BIT(CAUSE_FETCH_ACCESS) \
+|__BIT(CAUSE_LOAD_ACCESS) \
+|__BIT(CAUSE_STORE_ACCESS))
+
+#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_FETCH_MISALIGNED) \
+|__BIT(CAUSE_LOAD_MISALIGNED) \
+|__BIT(CAUSE_STORE_MISALIGNED))
static const char * const causenames[] = {
- [CAUSE_MISALIGNED_FETCH] = "misaligned fetch",
- [CAUSE_MISALIGNED_LOAD] = "misaligned load",
- [CAUSE_MISALIGNED_STORE] = "misaligned store",
- [CAUSE_FAULT_FETCH] = "fetch",
- [CAUSE_FAULT_LOAD] = "load",
- [CAUSE_FAULT_STORE] = "store",
- [CAUSE_FP_DISABLED] = "fp disabled",
+ [CAUSE_FETCH_MISALIGNED] = "misaligned fetch",
+ [CAUSE_LOAD_MISALIGNED] = "misaligned load",
+ [CAUSE_STORE_MISALIGNED] = "misaligned store",
+ [CAUSE_FETCH_ACCESS] = "fetch",
+ [CAUSE_LOAD_ACCESS] = "load",
+ [CAUSE_STORE_ACCESS] = "store",
[CAUSE_ILLEGAL_INSTRUCTION] = "illegal instruction",
- [CAUSE_PRIVILEGED_INSTRUCTION] = "privileged instruction",
[CAUSE_BREAKPOINT] = "breakpoint",
};
@@ -220,11 +217,11 @@ cpu_trapsignal(struct trapframe *tf, ksi
static inline vm_prot_t
get_faulttype(register_t cause)
{
- if (cause == CAUSE_FAULT_LOAD)
+ if (cause == CAUSE_LOAD_ACCESS)
return VM_PROT_READ;
- if (cause == CAUSE_FAULT_STORE)
+ if (cause == CAUSE_STORE_ACCESS)
return VM_PROT_READ | VM_PROT_WRITE;
- KASSERT(cause == CAUSE_FAULT_FETCH);
+ KASSERT(cause == CAUSE_FETCH_ACCESS);
return VM_PROT_READ | VM_PROT_EXECUTE;
}
@@ -256,12 +253,12 @@ trap_pagefault_fixup(struct trapframe *t
attr |= VM_PAGEMD_REFERENCED;
}
#if 0 /* XXX Outdated */
- if (cause == CAUSE_FAULT_STORE) {
+ if (cause == CAUSE_STORE_ACCESS) {
if ((npte & PTE_NW) != 0) {
npte &= ~PTE_NW;
attr |= VM_PAGEMD_MODIFIED;
}
- } else if (cause == CAUSE_FAULT_FETCH) {
+ } else if (cause == CAUSE_FETCH_ACCESS) {
if ((npte & PTE_NX) != 0) {
npte &= ~PTE_NX;
attr |= VM_PAGEMD_EXECPAGE;
@@ -349,9 +346,8 @@ static bool
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:06:22 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Remove unused variable
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.8 src/sys/arch/riscv/riscv/trap.c:1.9
--- src/sys/arch/riscv/riscv/trap.c:1.8 Sun Nov 1 20:56:24 2020
+++ src/sys/arch/riscv/riscv/trap.c Sun Nov 1 21:06:22 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.8 2020/11/01 20:56:24 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.9 2020/11/01 21:06:22 skrll Exp $");
#include
#include
@@ -422,7 +422,6 @@ cpu_trap(struct trapframe *tf, register_
void
cpu_ast(struct trapframe *tf)
{
- struct cpu_info * const ci = curcpu();
atomic_swap_uint(>l_md.md_astpending, 0);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Nov 1 21:01:49 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: clock_machdep.c
Log Message:
Don't shadow 'hz'
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/clock_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/clock_machdep.c
diff -u src/sys/arch/riscv/riscv/clock_machdep.c:1.1 src/sys/arch/riscv/riscv/clock_machdep.c:1.2
--- src/sys/arch/riscv/riscv/clock_machdep.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/riscv/clock_machdep.c Sun Nov 1 21:01:49 2020
@@ -29,7 +29,7 @@
#include
-__RCSID("$NetBSD: clock_machdep.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__RCSID("$NetBSD: clock_machdep.c,v 1.2 2020/11/01 21:01:49 skrll Exp $");
#include
#include
@@ -40,6 +40,6 @@ cpu_initclocks(void)
}
void
-setstatclockrate(int hz)
+setstatclockrate(int newhz)
{
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Sun Nov 1 20:56:24 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Typo in a trap name
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.7 src/sys/arch/riscv/riscv/trap.c:1.8
--- src/sys/arch/riscv/riscv/trap.c:1.7 Tue Jun 30 16:20:02 2020
+++ src/sys/arch/riscv/riscv/trap.c Sun Nov 1 20:56:24 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.7 2020/06/30 16:20:02 maxv Exp $");
+__RCSID("$NetBSD: trap.c,v 1.8 2020/11/01 20:56:24 skrll Exp $");
#include
#include
@@ -59,7 +59,7 @@ __RCSID("$NetBSD: trap.c,v 1.7 2020/06/3
static const char * const causenames[] = {
[CAUSE_MISALIGNED_FETCH] = "misaligned fetch",
- [CAUSE_MISALIGNED_LOAD] = "mialigned load",
+ [CAUSE_MISALIGNED_LOAD] = "misaligned load",
[CAUSE_MISALIGNED_STORE] = "misaligned store",
[CAUSE_FAULT_FETCH] = "fetch",
[CAUSE_FAULT_LOAD] = "load",
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: skrll Date: Sun Nov 1 19:47:46 UTC 2020 Modified Files: src/sys/arch/riscv/include: pte.h Log Message: Comments from zmcgrew@ To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/pte.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/pte.h diff -u src/sys/arch/riscv/include/pte.h:1.4 src/sys/arch/riscv/include/pte.h:1.5 --- src/sys/arch/riscv/include/pte.h:1.4 Sat Mar 14 16:12:16 2020 +++ src/sys/arch/riscv/include/pte.h Sun Nov 1 19:47:46 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: pte.h,v 1.4 2020/03/14 16:12:16 skrll Exp $ */ +/* $NetBSD: pte.h,v 1.5 2020/11/01 19:47:46 skrll Exp $ */ /* * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc. @@ -59,14 +59,15 @@ typedef __uint32_t pd_entry_t; #define PTE_WIRED __BIT(8) /* Hardware PTE bits. */ -#define PTE_D __BIT(7) -#define PTE_A __BIT(6) -#define PTE_G __BIT(5) -#define PTE_U __BIT(4) -#define PTE_X __BIT(3) -#define PTE_W __BIT(2) -#define PTE_R __BIT(1) -#define PTE_V __BIT(0) +// These are hardware defined bits +#define PTE_D __BIT(7) // Dirty +#define PTE_A __BIT(6) // Accessed +#define PTE_G __BIT(5) // Global +#define PTE_U __BIT(4) // User +#define PTE_X __BIT(3) // eXecute +#define PTE_W __BIT(2) // Write +#define PTE_R __BIT(1) // Read +#define PTE_V __BIT(0) // Valid #define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT) #define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: skrll Date: Sat Oct 31 15:18:09 UTC 2020 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Use the 'mv' pseudo-instruction instead of the 'move' equivalent as 'mv' is mentioned in the ISA documentation and it's used elsewhere. That is, let's use 'mv' everywhere for consistency. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.12 src/sys/arch/riscv/riscv/locore.S:1.13 --- src/sys/arch/riscv/riscv/locore.S:1.12 Sat Mar 14 16:12:16 2020 +++ src/sys/arch/riscv/riscv/locore.S Sat Oct 31 15:18:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.12 2020/03/14 16:12:16 skrll Exp $ */ +/* $NetBSD: locore.S,v 1.13 2020/10/31 15:18:09 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -75,7 +75,7 @@ ENTRY_NP(start) #ifdef _LP64 add s3, s2, s10 // s3 = second PDE page (RV64 only) #else - move s3, 22 + mv s3, 22 #endif add s4, s3, s10 // s4 = first kernel PTE page add s5, s1, s9 // s5 = kernel_end @@ -187,7 +187,7 @@ ENTRY_NP(cpu_switchto) csrrci t0, sstatus, SR_EI // # disable interrupts - move tp, a1 // # put the new lwp in thread pointer + mv tp, a1 // # put the new lwp in thread pointer PTR_L t1, L_CPU(tp) // # get curcpu PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp @@ -221,10 +221,10 @@ ENTRY_NP(cpu_switchto) END(cpu_switchto) ENTRY_NP(cpu_lwp_trampoline) - move a1, tp // get new lwp + mv a1, tp // get new lwp call _C_LABEL(lwp_startup) // call lwp startup - move a0, s1 // get saved arg + mv a0, s1 // get saved arg jalr s0 // call saved func // If the saved func returns, we are returning to user land. @@ -271,8 +271,8 @@ ENTRY_NP(cpu_fast_switchto) csrr t4, sstatus // get status register (for intr state) REG_S t4, TF_SR(sp) // save it - move s0, tp // remember curlwp - move s1, sp // remember kernel stack + mv s0, tp // remember curlwp + mv s1, sp // remember kernel stack #if 0 csrrci t0, sstatus, SR_EI // disable interrupts @@ -280,7 +280,7 @@ ENTRY_NP(cpu_fast_switchto) PTR_L t1, L_CPU(tp) // get curcpu() PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp - move tp, a0 // set thread pointer to newlwp + mv tp, a0 // set thread pointer to newlwp PTR_S tp, CI_CURLWP(t1) // update curlwp PTR_L sp, L_MD_KTF(tp) // switch to its stack #if 0 @@ -291,12 +291,12 @@ ENTRY_NP(cpu_fast_switchto) csrrci t0, sstatus, SR_EI // disable interrupts #endif PTR_L t1, L_CPU(tp) // get curcpu() again - move tp, s0 // return to pinned lwp + mv tp, s0 // return to pinned lwp PTR_S tp, CI_CURLWP(t1) // restore curlwp #if 0 csrw sstatus, t0 // reeanble interrupts #endif - move sp, s1 // restore stack pointer + mv sp, s1 // restore stack pointer REG_L ra, (TF_RA + CALLFRAME_RA)(sp) // get return address REG_L s0, TF_S0(sp) // restore register we used @@ -365,7 +365,7 @@ ENTRY_NP(cpu_exception_handler) REG_S t6, TF_T6(sp) // save t6 // Now we get the - move a0, sp // trapframe pointer + mv a0, sp // trapframe pointer csrr a1, sepc // get execption pc csrr a2, sstatus // get status csrr a3, scause // get cause @@ -480,7 +480,7 @@ intr_usersave: REG_S s11, TF_S11(sp) // only save from userland PTR_LA ra, exception_userexit trap_doast: - move a0, sp // only argument is trapframe + mv a0, sp // only argument is trapframe tail _C_LABEL(cpu_ast) intr_user: @@ -555,7 +555,7 @@ ENTRY(longjmp) REG_L s10, FB_S10(a0) REG_L s11, FB_S11(a0) REG_L sp, FB_SP(a0) - move a0, a1 + mv a0, a1 ret END(longjmp)
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: skrll
Date: Mon Aug 10 06:53:11 UTC 2020
Modified Files:
src/sys/arch/riscv/include: pmap.h
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.5 src/sys/arch/riscv/include/pmap.h:1.6
--- src/sys/arch/riscv/include/pmap.h:1.5 Fri Aug 7 07:19:45 2020
+++ src/sys/arch/riscv/include/pmap.h Mon Aug 10 06:53:11 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.5 2020/08/07 07:19:45 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.6 2020/08/10 06:53:11 skrll Exp $ */
/*
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -111,15 +111,15 @@ struct pmap_md {
void pmap_bootstrap(void);
struct vm_page *
-pmap_md_alloc_poolpage(int flags);
-vaddr_t pmap_md_map_poolpage(paddr_t, vsize_t);
-voidpmap_md_unmap_poolpage(vaddr_t, vsize_t);
-boolpmap_md_direct_mapped_vaddr_p(vaddr_t);
-boolpmap_md_io_vaddr_p(vaddr_t);
-paddr_t pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t);
-vaddr_t pmap_md_direct_map_paddr(paddr_t);
-voidpmap_md_init(void);
-boolpmap_md_tlb_check_entry(void *, vaddr_t, tlb_asid_t, pt_entry_t);
+ pmap_md_alloc_poolpage(int flags);
+vaddr_t pmap_md_map_poolpage(paddr_t, vsize_t);
+void pmap_md_unmap_poolpage(vaddr_t, vsize_t);
+bool pmap_md_direct_mapped_vaddr_p(vaddr_t);
+bool pmap_md_io_vaddr_p(vaddr_t);
+paddr_t pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t);
+vaddr_t pmap_md_direct_map_paddr(paddr_t);
+void pmap_md_init(void);
+bool pmap_md_tlb_check_entry(void *, vaddr_t, tlb_asid_t, pt_entry_t);
//voidpmap_md_page_syncicache(struct vm_page *, const kcpuset_t *);
void pmap_md_pdetab_activate(struct pmap *);
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: skrll
Date: Mon Apr 6 20:26:17 UTC 2020
Modified Files:
src/sys/arch/riscv/riscv: trap.c
Log Message:
Whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.5 src/sys/arch/riscv/riscv/trap.c:1.6
--- src/sys/arch/riscv/riscv/trap.c:1.5 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/riscv/trap.c Mon Apr 6 20:26:16 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.5 2020/03/14 16:12:16 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.6 2020/04/06 20:26:16 skrll Exp $");
#include
#include
@@ -293,7 +293,7 @@ trap_pagefault_fixup(struct trapframe *t
pmap_tlb_update_addr(pmap, addr, npte, 0);
if (attr & VM_PAGEMD_EXECPAGE)
- pmap_md_page_syncicache(pg, curcpu()->ci_data.cpu_kcpuset);
+ pmap_md_page_syncicache(pg, curcpu()->ci_data.cpu_kcpuset);
return true;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: christos
Date: Sat Apr 4 21:13:20 UTC 2020
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
silence lint.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/byte_swap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/byte_swap.h
diff -u src/sys/arch/riscv/include/byte_swap.h:1.4 src/sys/arch/riscv/include/byte_swap.h:1.5
--- src/sys/arch/riscv/include/byte_swap.h:1.4 Mon Apr 15 10:03:32 2019
+++ src/sys/arch/riscv/include/byte_swap.h Sat Apr 4 17:13:20 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: byte_swap.h,v 1.4 2019/04/15 14:03:32 maya Exp $ */
+/* $NetBSD: byte_swap.h,v 1.5 2020/04/04 21:13:20 christos Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -88,7 +88,7 @@ __byte_swap_u32_variable(uint32_t v)
static __inline uint16_t
__byte_swap_u16_variable(uint16_t v)
{
-
+ /*LINTED*/
return (uint16_t)((v >> 8) | (v << 8));
}
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: skrll
Date: Sat Mar 14 16:12:16 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv majors.riscv
src/sys/arch/riscv/include: asm.h elf_machdep.h fenv.h frame.h ieeefp.h
locore.h mcontext.h pte.h sysreg.h types.h
src/sys/arch/riscv/riscv: db_machdep.c kobj_machdep.c locore.S
netbsd32_machdep.c pmap_machdep.c process_machdep.c
procfs_machdep.c riscv_machdep.c sig_machdep.c spl.S syscall.c
trap.c vm_machdep.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/Makefile.riscv
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/conf/majors.riscv
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/asm.h \
src/sys/arch/riscv/include/pte.h
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/include/elf_machdep.h \
src/sys/arch/riscv/include/types.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/fenv.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/frame.h \
src/sys/arch/riscv/include/ieeefp.h
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/locore.h \
src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/mcontext.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/db_machdep.c \
src/sys/arch/riscv/riscv/netbsd32_machdep.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/kobj_machdep.c \
src/sys/arch/riscv/riscv/process_machdep.c \
src/sys/arch/riscv/riscv/sig_machdep.c src/sys/arch/riscv/riscv/spl.S \
src/sys/arch/riscv/riscv/vm_machdep.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/pmap_machdep.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/procfs_machdep.c \
src/sys/arch/riscv/riscv/syscall.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/riscv_machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.5 src/sys/arch/riscv/conf/Makefile.riscv:1.6
--- src/sys/arch/riscv/conf/Makefile.riscv:1.5 Sun Jun 16 07:42:52 2019
+++ src/sys/arch/riscv/conf/Makefile.riscv Sat Mar 14 16:12:15 2020
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.riscv,v 1.5 2019/06/16 07:42:52 maxv Exp $
+# $NetBSD: Makefile.riscv,v 1.6 2020/03/14 16:12:15 skrll Exp $
# Makefile for NetBSD
#
@@ -99,7 +99,7 @@ RAMDISKDIR!=cd ${NETBSDSRCDIR}/distr
.if defined(NEED_MDSETIMAGE) && ${NEED_MDSETIMAGE} != "no" \
&& defined(RAMDISKDIR) && exists(${RAMDISKDIR}/ramdisk.fs)
-SYSTEM_DEP+=${RAMDISKDIR}/ramdisk.fs
+SYSTEM_DEP+=${RAMDISKDIR}/ramdisk.fs
SYSTEM_LD_TAIL_EXTRA+=; \
echo ${TOOL_MDSETIMAGE} -s $@ ${RAMDISKDIR}/ramdisk.fs; \
${TOOL_MDSETIMAGE} -s $@ ${RAMDISKDIR}/ramdisk.fs
Index: src/sys/arch/riscv/conf/majors.riscv
diff -u src/sys/arch/riscv/conf/majors.riscv:1.7 src/sys/arch/riscv/conf/majors.riscv:1.8
--- src/sys/arch/riscv/conf/majors.riscv:1.7 Mon Jan 28 02:29:00 2019
+++ src/sys/arch/riscv/conf/majors.riscv Sat Mar 14 16:12:15 2020
@@ -1,4 +1,4 @@
-# $NetBSD: majors.riscv,v 1.7 2019/01/28 02:29:00 dholland Exp $
+# $NetBSD: majors.riscv,v 1.8 2020/03/14 16:12:15 skrll Exp $
#
# Device majors for riscv
#
@@ -32,7 +32,7 @@ device-major kttcp char 71 kttcp
#device-major aucom char 73 aucom
# Majors up to 143 are reserved for machine-dependent drivers.
-# New machine-independent driver majors are assigned in
+# New machine-independent driver majors are assigned in
# sys/conf/majors.
include "conf/majors.ws"
Index: src/sys/arch/riscv/include/asm.h
diff -u src/sys/arch/riscv/include/asm.h:1.3 src/sys/arch/riscv/include/asm.h:1.4
--- src/sys/arch/riscv/include/asm.h:1.3 Sat Apr 13 12:41:36 2019
+++ src/sys/arch/riscv/include/asm.h Sat Mar 14 16:12:16 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.3 2019/04/13 12:41:36 maya Exp $ */
+/* $NetBSD: asm.h,v 1.4 2020/03/14 16:12:16 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -49,7 +49,7 @@
REG_L ra, CALLFRAME_RA(sp);\
REG_L a0, CALLFRAME_S0(sp);\
addi sp, sp, CALLFRAME_SIZ;\
- .set pop;
+ .set pop;
#ifdef GPROF
#define _PROF_PROLOGUE _KERN_MCOUNT
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.3 src/sys/arch/riscv/include/pte.h:1.4
--- src/sys/arch/riscv/include/pte.h:1.3 Sun Jun 16 07:42:52 2019
+++ src/sys/arch/riscv/include/pte.h Sat Mar 14 16:12:16 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.3 2019/06/16 07:42:52 maxv Exp $ */
+/* $NetBSD: pte.h,v 1.4 2020/03/14 16:12:16 skrll Exp $ */
/*
* Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -125,8 +125,8 @@ pte_wire_entry(pt_entry_t pte)
{
return pte | PTE_WIRED;
}
-
-static inline pt_entry_t
+
+static inline pt_entry_t
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: mrg Date: Wed Apr 17 11:01:19 UTC 2019 Modified Files: src/sys/arch/riscv/include: int_fmtio.h Log Message: fix for riscv32. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/int_fmtio.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/int_fmtio.h diff -u src/sys/arch/riscv/include/int_fmtio.h:1.3 src/sys/arch/riscv/include/int_fmtio.h:1.4 --- src/sys/arch/riscv/include/int_fmtio.h:1.3 Tue Apr 16 07:08:52 2019 +++ src/sys/arch/riscv/include/int_fmtio.h Wed Apr 17 11:01:19 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: int_fmtio.h,v 1.3 2019/04/16 07:08:52 maya Exp $ */ +/* $NetBSD: int_fmtio.h,v 1.4 2019/04/17 11:01:19 mrg Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -53,11 +53,13 @@ #define PRIdLEAST32 "d" /* int_least32_t */ #ifdef _LP64 #define PRIdLEAST64 "ld" /* int_least64_t */ +#define PRIdFAST8 "d" /* int_fast8_t */ +#define PRIdFAST16 "d" /* int_fast16_t */ #else #define PRIdLEAST64 "lld" /* int_least64_t */ -#endif #define PRIdFAST8 "hhd" /* int_fast8_t */ #define PRIdFAST16 "hd" /* int_fast16_t */ +#endif #define PRIdFAST32 "d" /* int_fast32_t */ #ifdef _LP64 #define PRIdFAST64 "ld" /* int_fast64_t */ @@ -81,11 +83,13 @@ #define PRIiLEAST32 "i" /* int_least32_t */ #ifdef _LP64 #define PRIiLEAST64 "li" /* int_least64_t */ +#define PRIiFAST8 "i" /* int_fast8_t */ +#define PRIiFAST16 "i" /* int_fast16_t */ #else #define PRIiLEAST64 "lli" /* int_least64_t */ -#endif #define PRIiFAST8 "hhi" /* int_fast8_t */ #define PRIiFAST16 "hi" /* int_fast16_t */ +#endif #define PRIiFAST32 "i" /* int_fast32_t */ #ifdef _LP64 #define PRIiFAST64 "li" /* int_fast64_t */ @@ -111,11 +115,13 @@ #define PRIoLEAST32 "ho" /* uint_least32_t */ #ifdef _LP64 #define PRIoLEAST64 "lo" /* uint_least64_t */ +#define PRIoFAST8 "o" /* uint_fast8_t */ +#define PRIoFAST16 "o" /* uint_fast16_t */ #else #define PRIoLEAST64 "llo" /* uint_least64_t */ -#endif #define PRIoFAST8 "hho" /* uint_fast8_t */ #define PRIoFAST16 "ho" /* uint_fast16_t */ +#endif #define PRIoFAST32 "o" /* uint_fast32_t */ #ifdef _LP64 #define PRIoFAST64 "lo" /* uint_fast64_t */ @@ -139,11 +145,13 @@ #define PRIuLEAST32 "u" /* uint_least32_t */ #ifdef _LP64 #define PRIuLEAST64 "lu" /* uint_least64_t */ +#define PRIuFAST8 "u" /* uint_fast8_t */ +#define PRIuFAST16 "u" /* uint_fast16_t */ #else #define PRIuLEAST64 "llu" /* uint_least64_t */ -#endif #define PRIuFAST8 "hhu" /* uint_fast8_t */ #define PRIuFAST16 "hu" /* uint_fast16_t */ +#endif #define PRIuFAST32 "u" /* uint_fast32_t */ #ifdef _LP64 #define PRIuFAST64 "lu" /* uint_fast64_t */ @@ -167,11 +175,13 @@ #define PRIxLEAST32 "x" /* uint_least32_t */ #ifdef _LP64 #define PRIxLEAST64 "lx" /* uint_least64_t */ +#define PRIxFAST8 "x" /* uint_fast8_t */ +#define PRIxFAST16 "x" /* uint_fast16_t */ #else #define PRIxLEAST64 "llx" /* uint_least64_t */ +#define PRIxFAST8 "hhx" /* uint_fast8_t */ +#define PRIxFAST16 "hx" /* uint_fast16_t */ #endif -#define PRIxFAST8 "x" /* uint_fast8_t */ -#define PRIxFAST16 "x" /* uint_fast16_t */ #define PRIxFAST32 "x" /* uint_fast32_t */ #ifdef _LP64 #define PRIxFAST64 "lx" /* uint_fast64_t */ @@ -195,11 +205,13 @@ #define PRIXLEAST32 "X" /* uint_least32_t */ #ifdef _LP64 #define PRIXLEAST64 "lX" /* uint_least64_t */ +#define PRIXFAST8 "X" /* uint_fast8_t */ +#define PRIXFAST16 "X" /* uint_fast16_t */ #else #define PRIXLEAST64 "llX" /* uint_least64_t */ +#define PRIXFAST8 "hhX" /* uint_fast8_t */ +#define PRIXFAST16 "hX" /* uint_fast16_t */ #endif -#define PRIXFAST8 "X" /* uint_fast8_t */ -#define PRIXFAST16 "X" /* uint_fast16_t */ #define PRIXFAST32 "X" /* uint_fast32_t */ #ifdef _LP64 #define PRIXFAST64 "lX" /* uint_fast64_t */ @@ -225,11 +237,13 @@ #define SCNdLEAST32 "d" /* int_least32_t */ #ifdef _LP64 #define SCNdLEAST64 "ld" /* int_least64_t */ +#define SCNdFAST8 "d" /* int_fast8_t */ +#define SCNdFAST16 "d" /* int_fast16_t */ #else #define SCNdLEAST64 "lld" /* int_least64_t */ +#define SCNdFAST8 "hhd" /* int_fast8_t */ +#define SCNdFAST16 "hd" /* int_fast16_t */ #endif -#define SCNdFAST8 "d" /* int_fast8_t */ -#define SCNdFAST16 "d" /* int_fast16_t */ #define SCNdFAST32 "d" /* int_fast32_t */ #ifdef _LP64 #define SCNdFAST64 "ld" /* int_fast64_t */ @@ -253,11 +267,13 @@ #define SCNiLEAST32 "i" /* int_least32_t */ #ifdef _LP64 #define SCNiLEAST64 "li" /* int_least64_t */ +#define SCNiFAST8 "i" /* int_fast8_t */ +#define SCNiFAST16 "i" /* int_fast16_t */ #else #define SCNiLEAST64 "lli" /* int_least64_t */ +#define SCNiFAST8 "hhi" /* int_fast8_t */ +#define SCNiFAST16 "hi" /* int_fast16_t */ #endif -#define SCNiFAST8 "i" /* int_fast8_t */ -#define SCNiFAST16 "i" /* int_fast16_t */ #define SCNiFAST32 "i" /* int_fast32_t */ #ifdef _LP64 #define
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: maya Date: Tue Apr 16 07:40:03 UTC 2019 Modified Files: src/sys/arch/riscv/include: math.h Log Message: RISC-V ELF psABI says ILP32 also defaults to 128bit long double. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/math.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/math.h diff -u src/sys/arch/riscv/include/math.h:1.2 src/sys/arch/riscv/include/math.h:1.3 --- src/sys/arch/riscv/include/math.h:1.2 Sat Apr 13 15:57:31 2019 +++ src/sys/arch/riscv/include/math.h Tue Apr 16 07:40:02 2019 @@ -1,7 +1,4 @@ -/* $NetBSD: math.h,v 1.2 2019/04/13 15:57:31 maya Exp $ */ +/* $NetBSD: math.h,v 1.3 2019/04/16 07:40:02 maya Exp $ */ #define __HAVE_NANF - -#if defined(_LP64) || defined(_KERNEL) #define __HAVE_LONG_DOUBLE 128 -#endif
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: maya Date: Tue Apr 16 07:08:52 UTC 2019 Modified Files: src/sys/arch/riscv/include: int_fmtio.h Log Message: We're now using gcc netbsd-stdint.h instead of our own definitions, so match those with the format types XXX wrong for 32bit. XXX unclear if changing the fast types was the right call To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/int_fmtio.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/int_fmtio.h diff -u src/sys/arch/riscv/include/int_fmtio.h:1.2 src/sys/arch/riscv/include/int_fmtio.h:1.3 --- src/sys/arch/riscv/include/int_fmtio.h:1.2 Sat Apr 13 15:56:18 2019 +++ src/sys/arch/riscv/include/int_fmtio.h Tue Apr 16 07:08:52 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: int_fmtio.h,v 1.2 2019/04/13 15:56:18 maya Exp $ */ +/* $NetBSD: int_fmtio.h,v 1.3 2019/04/16 07:08:52 maya Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -101,7 +101,11 @@ #define PRIo8 "hho" /* uint8_t */ #define PRIo16 "ho" /* uint16_t */ #define PRIo32 "o" /* uint32_t */ +#ifdef _LP64 +#define PRIo64 "lo" /* uint64_t */ +#else #define PRIo64 "llo" /* uint64_t */ +#endif #define PRIoLEAST8 "o" /* uint_least8_t */ #define PRIoLEAST16 "hho" /* uint_least16_t */ #define PRIoLEAST32 "ho" /* uint_least32_t */ @@ -224,8 +228,8 @@ #else #define SCNdLEAST64 "lld" /* int_least64_t */ #endif -#define SCNdFAST8 "hhd" /* int_fast8_t */ -#define SCNdFAST16 "hd" /* int_fast16_t */ +#define SCNdFAST8 "d" /* int_fast8_t */ +#define SCNdFAST16 "d" /* int_fast16_t */ #define SCNdFAST32 "d" /* int_fast32_t */ #ifdef _LP64 #define SCNdFAST64 "ld" /* int_fast64_t */ @@ -252,8 +256,8 @@ #else #define SCNiLEAST64 "lli" /* int_least64_t */ #endif -#define SCNiFAST8 "hhi" /* int_fast8_t */ -#define SCNiFAST16 "hi" /* int_fast16_t */ +#define SCNiFAST8 "i" /* int_fast8_t */ +#define SCNiFAST16 "i" /* int_fast16_t */ #define SCNiFAST32 "i" /* int_fast32_t */ #ifdef _LP64 #define SCNiFAST64 "li" /* int_fast64_t */ @@ -282,8 +286,8 @@ #else #define SCNoLEAST64 "llo" /* uint_least64_t */ #endif -#define SCNoFAST8 "hho" /* uint_fast8_t */ -#define SCNoFAST16 "ho" /* uint_fast16_t */ +#define SCNoFAST8 "o" /* uint_fast8_t */ +#define SCNoFAST16 "o" /* uint_fast16_t */ #define SCNoFAST32 "o" /* uint_fast32_t */ #ifdef _LP64 #define SCNoFAST64 "lo" /* uint_fast64_t */ @@ -310,8 +314,8 @@ #else #define SCNuLEAST64 "llu" /* uint_least64_t */ #endif -#define SCNuFAST8 "hhu" /* uint_fast8_t */ -#define SCNuFAST16 "hu" /* uint_fast16_t */ +#define SCNuFAST8 "u" /* uint_fast8_t */ +#define SCNuFAST16 "u" /* uint_fast16_t */ #define SCNuFAST32 "u" /* uint_fast32_t */ #ifdef _LP64 #define SCNuFAST64 "lu" /* uint_fast64_t */ @@ -338,8 +342,8 @@ #else #define SCNxLEAST64 "llx" /* uint_least64_t */ #endif -#define SCNxFAST8 "hhx" /* uint_fast8_t */ -#define SCNxFAST16 "hx" /* uint_fast16_t */ +#define SCNxFAST8 "x" /* uint_fast8_t */ +#define SCNxFAST16 "x" /* uint_fast16_t */ #define SCNxFAST32 "x" /* uint_fast32_t */ #ifdef _LP64 #define SCNxFAST64 "lx" /* uint_fast64_t */
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: maya
Date: Mon Apr 15 14:03:32 UTC 2019
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Avoid -Wconversion warnings
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/byte_swap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/byte_swap.h
diff -u src/sys/arch/riscv/include/byte_swap.h:1.3 src/sys/arch/riscv/include/byte_swap.h:1.4
--- src/sys/arch/riscv/include/byte_swap.h:1.3 Tue Oct 28 20:25:36 2014
+++ src/sys/arch/riscv/include/byte_swap.h Mon Apr 15 14:03:32 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: byte_swap.h,v 1.3 2014/10/28 20:25:36 dennis Exp $ */
+/* $NetBSD: byte_swap.h,v 1.4 2019/04/15 14:03:32 maya Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -88,10 +88,8 @@ __byte_swap_u32_variable(uint32_t v)
static __inline uint16_t
__byte_swap_u16_variable(uint16_t v)
{
- v &= 0x;
- v = (v >> 8) | (v << 8);
- return v;
+ return (uint16_t)((v >> 8) | (v << 8));
}
__END_DECLS
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: maya Date: Sat Apr 13 15:57:31 UTC 2019 Modified Files: src/sys/arch/riscv/include: ieee.h math.h Log Message: Our current configuration is that long double is 128bit, so reflect that in the relevant headers. Taken from sparc64. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/ieee.h \ src/sys/arch/riscv/include/math.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/ieee.h diff -u src/sys/arch/riscv/include/ieee.h:1.1 src/sys/arch/riscv/include/ieee.h:1.2 --- src/sys/arch/riscv/include/ieee.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/ieee.h Sat Apr 13 15:57:31 2019 @@ -1,3 +1,4 @@ -/* $NetBSD: ieee.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: ieee.h,v 1.2 2019/04/13 15:57:31 maya Exp $ */ +#include /* for #define __HAVE_LONG_DOUBLE 128 */ #include Index: src/sys/arch/riscv/include/math.h diff -u src/sys/arch/riscv/include/math.h:1.1 src/sys/arch/riscv/include/math.h:1.2 --- src/sys/arch/riscv/include/math.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/math.h Sat Apr 13 15:57:31 2019 @@ -1,3 +1,7 @@ -/* $NetBSD: math.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: math.h,v 1.2 2019/04/13 15:57:31 maya Exp $ */ #define __HAVE_NANF + +#if defined(_LP64) || defined(_KERNEL) +#define __HAVE_LONG_DOUBLE 128 +#endif
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: maya Date: Sat Apr 13 15:56:18 UTC 2019 Modified Files: src/sys/arch/riscv/include: int_fmtio.h Log Message: Provide defines for the 64bit case. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/int_fmtio.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/int_fmtio.h diff -u src/sys/arch/riscv/include/int_fmtio.h:1.1 src/sys/arch/riscv/include/int_fmtio.h:1.2 --- src/sys/arch/riscv/include/int_fmtio.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/int_fmtio.h Sat Apr 13 15:56:18 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: int_fmtio.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: int_fmtio.h,v 1.2 2019/04/13 15:56:18 maya Exp $ */ /*- * Copyright (c) 2001 The NetBSD Foundation, Inc. @@ -43,31 +43,57 @@ #define PRId8 "hhd" /* int8_t */ #define PRId16 "hd" /* int16_t */ #define PRId32 "d" /* int32_t */ +#ifdef _LP64 +#define PRId64 "ld" /* int64_t */ +#else #define PRId64 "lld" /* int64_t */ +#endif #define PRIdLEAST8 "hhd" /* int_least8_t */ #define PRIdLEAST16 "hd" /* int_least16_t */ #define PRIdLEAST32 "d" /* int_least32_t */ +#ifdef _LP64 +#define PRIdLEAST64 "ld" /* int_least64_t */ +#else #define PRIdLEAST64 "lld" /* int_least64_t */ +#endif #define PRIdFAST8 "hhd" /* int_fast8_t */ #define PRIdFAST16 "hd" /* int_fast16_t */ #define PRIdFAST32 "d" /* int_fast32_t */ +#ifdef _LP64 +#define PRIdFAST64 "ld" /* int_fast64_t */ +#define PRIdMAX "ld" /* intmax_t */ +#else #define PRIdFAST64 "lld" /* int_fast64_t */ #define PRIdMAX "lld" /* intmax_t */ +#endif #define PRIdPTR "ld" /* intptr_t */ #define PRIi8 "hhi" /* int8_t */ #define PRIi16 "hi" /* int16_t */ #define PRIi32 "i" /* int32_t */ +#ifdef _LP64 +#define PRIi64 "li" /* int64_t */ +#else #define PRIi64 "lli" /* int64_t */ +#endif #define PRIiLEAST8 "hhi" /* int_least8_t */ #define PRIiLEAST16 "hi" /* int_least16_t */ #define PRIiLEAST32 "i" /* int_least32_t */ +#ifdef _LP64 +#define PRIiLEAST64 "li" /* int_least64_t */ +#else #define PRIiLEAST64 "lli" /* int_least64_t */ +#endif #define PRIiFAST8 "hhi" /* int_fast8_t */ #define PRIiFAST16 "hi" /* int_fast16_t */ #define PRIiFAST32 "i" /* int_fast32_t */ +#ifdef _LP64 +#define PRIiFAST64 "li" /* int_fast64_t */ +#define PRIiMAX "li" /* intmax_t */ +#else #define PRIiFAST64 "lli" /* int_fast64_t */ #define PRIiMAX "lli" /* intmax_t */ +#endif #define PRIiPTR "li" /* intptr_t */ /* fprintf macros for unsigned integers */ @@ -79,57 +105,105 @@ #define PRIoLEAST8 "o" /* uint_least8_t */ #define PRIoLEAST16 "hho" /* uint_least16_t */ #define PRIoLEAST32 "ho" /* uint_least32_t */ +#ifdef _LP64 +#define PRIoLEAST64 "lo" /* uint_least64_t */ +#else #define PRIoLEAST64 "llo" /* uint_least64_t */ +#endif #define PRIoFAST8 "hho" /* uint_fast8_t */ #define PRIoFAST16 "ho" /* uint_fast16_t */ #define PRIoFAST32 "o" /* uint_fast32_t */ +#ifdef _LP64 +#define PRIoFAST64 "lo" /* uint_fast64_t */ +#define PRIoMAX "lo" /* uintmax_t */ +#else #define PRIoFAST64 "llo" /* uint_fast64_t */ #define PRIoMAX "llo" /* uintmax_t */ +#endif #define PRIoPTR "lo" /* uintptr_t */ #define PRIu8 "hhu" /* uint8_t */ #define PRIu16 "hu" /* uint16_t */ #define PRIu32 "u" /* uint32_t */ +#ifdef _LP64 +#define PRIu64 "lu" /* uint64_t */ +#else #define PRIu64 "llu" /* uint64_t */ +#endif #define PRIuLEAST8 "hhu" /* uint_least8_t */ #define PRIuLEAST16 "hu" /* uint_least16_t */ #define PRIuLEAST32 "u" /* uint_least32_t */ +#ifdef _LP64 +#define PRIuLEAST64 "lu" /* uint_least64_t */ +#else #define PRIuLEAST64 "llu" /* uint_least64_t */ +#endif #define PRIuFAST8 "hhu" /* uint_fast8_t */ #define PRIuFAST16 "hu" /* uint_fast16_t */ #define PRIuFAST32 "u" /* uint_fast32_t */ +#ifdef _LP64 +#define PRIuFAST64 "lu" /* uint_fast64_t */ +#define PRIuMAX "lu" /* uintmax_t */ +#else #define PRIuFAST64 "llu" /* uint_fast64_t */ #define PRIuMAX "llu" /* uintmax_t */ +#endif #define PRIuPTR "lu" /* uintptr_t */ #define PRIx8 "hhx" /* uint8_t */ #define PRIx16 "hx" /* uint16_t */ #define PRIx32 "x" /* uint32_t */ +#ifdef _LP64 +#define PRIx64 "lx" /* uint64_t */ +#else #define PRIx64 "llx" /* uint64_t */ +#endif #define PRIxLEAST8 "x" /* uint_least8_t */ #define PRIxLEAST16 "x" /* uint_least16_t */ #define PRIxLEAST32 "x" /* uint_least32_t */ +#ifdef _LP64 +#define PRIxLEAST64 "lx" /* uint_least64_t */ +#else #define PRIxLEAST64 "llx" /* uint_least64_t */ +#endif #define PRIxFAST8 "x" /* uint_fast8_t */ #define PRIxFAST16 "x" /* uint_fast16_t */ #define PRIxFAST32 "x" /* uint_fast32_t */ +#ifdef _LP64 +#define PRIxFAST64 "lx" /* uint_fast64_t */ +#define PRIxMAX "lx" /* uintmax_t */ +#else #define PRIxFAST64 "llx" /* uint_fast64_t */ #define PRIxMAX "llx" /* uintmax_t */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: maya Date: Sat Apr 13 12:41:37 UTC 2019 Modified Files: src/sys/arch/riscv/include: asm.h Log Message: Handle changes since the gcc riscv toolchain was upstreamed To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/asm.h diff -u src/sys/arch/riscv/include/asm.h:1.2 src/sys/arch/riscv/include/asm.h:1.3 --- src/sys/arch/riscv/include/asm.h:1.2 Fri Mar 27 06:57:21 2015 +++ src/sys/arch/riscv/include/asm.h Sat Apr 13 12:41:36 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */ +/* $NetBSD: asm.h,v 1.3 2019/04/13 12:41:36 maya Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -58,7 +58,7 @@ #endif #ifdef __PIC__ -#define PLT(x) x##@ +#define PLT(x) x##@plt #else #define PLT(x) x #endif
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: kamil
Date: Thu Apr 11 11:23:52 UTC 2019
Modified Files:
src/sys/arch/riscv/include: locore.h
Log Message:
Fix a typo in a comment
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/locore.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/locore.h
diff -u src/sys/arch/riscv/include/locore.h:1.3 src/sys/arch/riscv/include/locore.h:1.4
--- src/sys/arch/riscv/include/locore.h:1.3 Thu Mar 16 16:13:21 2017
+++ src/sys/arch/riscv/include/locore.h Thu Apr 11 11:23:51 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.3 2017/03/16 16:13:21 chs Exp $ */
+/* $NetBSD: locore.h,v 1.4 2019/04/11 11:23:51 kamil Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -77,7 +77,7 @@ struct trapframe {
#define tf_t6 tf_reg[_X_T6]
};
-// For COMPAT_NETBDS32 coredumps
+// For COMPAT_NETBSD32 coredumps
struct trapframe32 {
struct reg32 tf_regs;
register32_t tf_badaddr;
CVS commit: src/sys/arch/riscv/conf
Module Name:src Committed By: dholland Date: Sun Jan 27 18:00:06 UTC 2019 Modified Files: src/sys/arch/riscv/conf: majors.riscv Log Message: This may have been cutpasted from evbmips, but we don't need to say so. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/conf/majors.riscv Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/conf/majors.riscv diff -u src/sys/arch/riscv/conf/majors.riscv:1.5 src/sys/arch/riscv/conf/majors.riscv:1.6 --- src/sys/arch/riscv/conf/majors.riscv:1.5 Sun Jan 27 17:59:23 2019 +++ src/sys/arch/riscv/conf/majors.riscv Sun Jan 27 18:00:06 2019 @@ -1,6 +1,6 @@ -# $NetBSD: majors.riscv,v 1.5 2019/01/27 17:59:23 dholland Exp $ +# $NetBSD: majors.riscv,v 1.6 2019/01/27 18:00:06 dholland Exp $ # -# Device majors for evbmips +# Device majors for riscv # device-major tun char 7 tun
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: christos
Date: Mon Apr 23 15:40:33 UTC 2018
Modified Files:
src/sys/arch/riscv/riscv: db_machdep.c
Log Message:
PR/53206: David Binderman: fix array bounds comparison in KASSERT.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/db_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/db_machdep.c
diff -u src/sys/arch/riscv/riscv/db_machdep.c:1.1 src/sys/arch/riscv/riscv/db_machdep.c:1.2
--- src/sys/arch/riscv/riscv/db_machdep.c:1.1 Sat Mar 28 12:13:56 2015
+++ src/sys/arch/riscv/riscv/db_machdep.c Mon Apr 23 11:40:33 2018
@@ -29,7 +29,7 @@
#include
-__RCSID("$NetBSD: db_machdep.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__RCSID("$NetBSD: db_machdep.c,v 1.2 2018/04/23 15:40:33 christos Exp $");
#include
@@ -86,7 +86,7 @@ int
db_rw_ddbreg(const struct db_variable *vp, db_expr_t *valp, int rw)
{
struct trapframe * const tf = curcpu()->ci_ddb_regs;
- KASSERT(db_regs <= vp && vp < db_regs);
+ KASSERT(db_regs <= vp && vp < db_regs + __arraycount(db_regs));
const uintptr_t addr = (uintptr_t)tf + (uintptr_t)vp->valuep;
if (vp->modif != NULL && vp->modif[0] == 'i') {
if (rw == DB_VAR_GET) {
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: maya Date: Mon Feb 5 10:41:12 UTC 2018 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix tyop To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.6 src/sys/arch/riscv/riscv/locore.S:1.7 --- src/sys/arch/riscv/riscv/locore.S:1.6 Mon Dec 5 07:24:16 2016 +++ src/sys/arch/riscv/riscv/locore.S Mon Feb 5 10:41:12 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.6 2016/12/05 07:24:16 kamil Exp $ */ +/* $NetBSD: locore.S,v 1.7 2018/02/05 10:41:12 maya Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -190,7 +190,7 @@ ENTRY_NP(cpu_switchto) REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer REG_L t4, TF_SR(sp) // # fetch status register - csrw sstatus, t4 // # restore it (and interrutps?) + csrw sstatus, t4 // # restore it (and interrupts?) REG_L s0, TF_S0(sp) // restore callee saved REG_L s1, TF_S1(sp) // restore callee saved @@ -281,7 +281,7 @@ ENTRY_NP(cpu_fast_switchto) PTR_S tp, CI_CURLWP(t1) // update curlwp PTR_L sp, L_MD_KTF(tp) // switch to its stack #if 0 - csrw sstatus, t0 // reeanble interrupts + csrw sstatus, t0 // reenable interrupts #endif call _C_LABEL(softint_dispatch) #if 0
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: kamil Date: Mon Dec 5 07:24:16 UTC 2016 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix cpu_switchto(9) prototype in a comment To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.5 src/sys/arch/riscv/riscv/locore.S:1.6 --- src/sys/arch/riscv/riscv/locore.S:1.5 Tue Mar 31 11:53:13 2015 +++ src/sys/arch/riscv/riscv/locore.S Mon Dec 5 07:24:16 2016 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.5 2015/03/31 11:53:13 matt Exp $ */ +/* $NetBSD: locore.S,v 1.6 2016/12/05 07:24:16 kamil Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -156,7 +156,7 @@ ENTRY_NP(start) END(start) // -// struct lwp *cpu_switch(struct lwp *oldl, struct lwp *newl, bool returning); +// struct lwp *cpu_switchto(struct lwp *oldl, struct lwp *newl, bool returning); // ENTRY_NP(cpu_switchto) addi sp, sp, -TF_LEN // allocate trapframe
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Fri Jun 26 14:20:11 UTC 2015
Modified Files:
src/sys/arch/riscv/include: lock.h
Log Message:
Fix cp error.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/lock.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/lock.h
diff -u src/sys/arch/riscv/include/lock.h:1.2 src/sys/arch/riscv/include/lock.h:1.3
--- src/sys/arch/riscv/include/lock.h:1.2 Sun Mar 29 09:43:26 2015
+++ src/sys/arch/riscv/include/lock.h Fri Jun 26 14:20:11 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: lock.h,v 1.2 2015/03/29 09:43:26 matt Exp $ */
+/* $NetBSD: lock.h,v 1.3 2015/06/26 14:20:11 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -88,7 +88,7 @@ __cpu_simple_lock(__cpu_simple_lock_t *_
static __inline int __unused
__cpu_simple_lock_try(__cpu_simple_lock_t *__ptr)
{
- return __atomic_exchange_n(__ptr, __SIMPLELOCK_LOCKED, __ATOMIC_ACQUIRE) == __SIMPLELOCK_LOCKED;
+ return __atomic_exchange_n(__ptr, __SIMPLELOCK_LOCKED, __ATOMIC_ACQUIRE) == __SIMPLELOCK_UNLOCKED;
}
static __inline void __unused
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: matt Date: Thu May 28 02:19:05 UTC 2015 Modified Files: src/sys/arch/riscv/include: elf_machdep.h Log Message: add ELF64_MACHDEP_ID To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/elf_machdep.h diff -u src/sys/arch/riscv/include/elf_machdep.h:1.4 src/sys/arch/riscv/include/elf_machdep.h:1.5 --- src/sys/arch/riscv/include/elf_machdep.h:1.4 Wed Apr 1 21:59:01 2015 +++ src/sys/arch/riscv/include/elf_machdep.h Thu May 28 02:19:05 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.4 2015/04/01 21:59:01 matt Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.5 2015/05/28 02:19:05 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -33,6 +33,7 @@ #define _RISCV_ELF_MACHDEP_H_ #define ELF32_MACHDEP_ID EM_RISCV +#define ELF64_MACHDEP_ID EM_RISCV #define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB #define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Wed Apr 1 21:55:03 UTC 2015
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
_KMEMUSER only needs struct cpu_info
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.3 src/sys/arch/riscv/include/cpu.h:1.4
--- src/sys/arch/riscv/include/cpu.h:1.3 Tue Mar 31 01:11:41 2015
+++ src/sys/arch/riscv/include/cpu.h Wed Apr 1 21:55:03 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.3 2015/03/31 01:11:41 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.4 2015/04/01 21:55:03 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -33,6 +33,7 @@
#define _RISCV_CPU_H_
#if defined(_KERNEL) || defined(_KMEMUSER)
+
struct clockframe {
uintptr_t cf_pc;
uint32_t cf_sr;
@@ -79,6 +80,10 @@ struct cpu_info {
struct evcnt ci_ev_fpu_reenables;
};
+#endif /* _KERNEL || _KMEMUSER */
+
+#ifdef _KERNEL
+
extern struct cpu_info cpu_info_store;
// This is also in sys/lwp.h
@@ -141,6 +146,6 @@ cpu_idle(void)
{
}
-#endif /* _KERNEL || _KMEMUSER */
+#endif /* _KERNEL */
#endif /* _RISCV_CPU_H_ */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: matt Date: Wed Apr 1 21:55:33 UTC 2015 Modified Files: src/sys/arch/riscv/include: mcontext.h Log Message: Add _REG_S0 To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/mcontext.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/mcontext.h diff -u src/sys/arch/riscv/include/mcontext.h:1.3 src/sys/arch/riscv/include/mcontext.h:1.4 --- src/sys/arch/riscv/include/mcontext.h:1.3 Fri Mar 27 06:57:21 2015 +++ src/sys/arch/riscv/include/mcontext.h Wed Apr 1 21:55:33 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: mcontext.h,v 1.3 2015/03/27 06:57:21 matt Exp $ */ +/* $NetBSD: mcontext.h,v 1.4 2015/04/01 21:55:33 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -91,6 +91,7 @@ typedef _BSD_FPREG_T_ __fregset_t[_NFREG #define _REG_SP _REG_X2 #define _REG_GP _REG_X3 #define _REG_TP _REG_X4 +#define _REG_S0 _REG_X8 #define _REG_RV _REG_X10 #define _REG_A0 _REG_X10
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: matt Date: Wed Apr 1 21:59:01 UTC 2015 Modified Files: src/sys/arch/riscv/include: elf_machdep.h Log Message: Add two new relocs for compressed branches. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/elf_machdep.h diff -u src/sys/arch/riscv/include/elf_machdep.h:1.3 src/sys/arch/riscv/include/elf_machdep.h:1.4 --- src/sys/arch/riscv/include/elf_machdep.h:1.3 Fri Mar 27 23:26:14 2015 +++ src/sys/arch/riscv/include/elf_machdep.h Wed Apr 1 21:59:01 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.3 2015/03/27 23:26:14 matt Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.4 2015/04/01 21:59:01 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -97,6 +97,8 @@ #define R_RISCV_GNU_VTINHERIT 41 // A 0x #define R_RISCV_GNU_VTENTRY 42 #define R_RISCV_ALIGN 43 +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 /* These are aliases we can use R_TYPESZ */ #define R_RISCV_ADDR32 R_RISCV_32
CVS commit: src/sys/arch/riscv
Module Name:src
Committed By: matt
Date: Tue Mar 31 06:47:47 UTC 2015
Modified Files:
src/sys/arch/riscv/include: proc.h
src/sys/arch/riscv/riscv: genassym.cf locore.S
Log Message:
Optimize the exception handle a little bit more.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/proc.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/genassym.cf \
src/sys/arch/riscv/riscv/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/proc.h
diff -u src/sys/arch/riscv/include/proc.h:1.2 src/sys/arch/riscv/include/proc.h:1.3
--- src/sys/arch/riscv/include/proc.h:1.2 Tue Mar 31 01:12:29 2015
+++ src/sys/arch/riscv/include/proc.h Tue Mar 31 06:47:47 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.2 2015/03/31 01:12:29 matt Exp $ */
+/* $NetBSD: proc.h,v 1.3 2015/03/31 06:47:47 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,7 +46,7 @@ struct mdlwp {
struct trapframe *md_utf; /* trapframe from userspace */
struct trapframe *md_ktf; /* trapframe from userspace */
struct faultbuf *md_onfault; /* registers to store on fault */
- register_t md_tp; /* for locore.S */
+ register_t md_usp; /* for locore.S */
vaddr_t md_ss_addr; /* single step address for ptrace */
int md_ss_instr; /* single step instruction for ptrace */
volatile int md_astpending; /* AST pending on return to userland */
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.2 src/sys/arch/riscv/riscv/genassym.cf:1.3
--- src/sys/arch/riscv/riscv/genassym.cf:1.2 Tue Mar 31 01:12:47 2015
+++ src/sys/arch/riscv/riscv/genassym.cf Tue Mar 31 06:47:47 2015
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.2 2015/03/31 01:12:47 matt Exp $
+# $NetBSD: genassym.cf,v 1.3 2015/03/31 06:47:47 matt Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -114,7 +114,7 @@ define L_CPU offsetof(struct lwp, l_cpu
define L_CTXSWTCH offsetof(struct lwp, l_ctxswtch)
define L_MD_ASTPENDING offsetof(struct lwp, l_md.md_astpending)
define L_MD_ONFAULT offsetof(struct lwp, l_md.md_onfault)
-define L_MD_TP offsetof(struct lwp, l_md.md_tp)
+define L_MD_USP offsetof(struct lwp, l_md.md_usp)
define L_MD_UTF offsetof(struct lwp, l_md.md_utf)
define L_MD_KTF offsetof(struct lwp, l_md.md_ktf)
define L_PCB offsetof(struct lwp, l_addr)
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.2 src/sys/arch/riscv/riscv/locore.S:1.3
--- src/sys/arch/riscv/riscv/locore.S:1.2 Tue Mar 31 01:30:50 2015
+++ src/sys/arch/riscv/riscv/locore.S Tue Mar 31 06:47:47 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.2 2015/03/31 01:30:50 matt Exp $ */
+/* $NetBSD: locore.S,v 1.3 2015/03/31 06:47:47 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -306,8 +306,8 @@ END(cpu_fast_switchto)
// RISCV only has a simple exception handler handles both synchronous traps
// and interrupts.
ENTRY_NP(cpu_exception_handler)
- csrrw sp, sscratch, sp // swap scratch and stack pointer
- beqz sp, .Lexception_kernel // sp == 0, already on kernel stack
+ csrrw tp, sscratch, tp // swap scratch and thread pointer
+ beqz tp, .Lexception_kernel // tp == 0, already on kernel stack
//
// The execption happened while user code was executing. We need to
// get the pointer to the user trapframe from the LWP md area. Then we
@@ -315,14 +315,14 @@ ENTRY_NP(cpu_exception_handler)
// into tp. We also save the saved SP into the trapframe.
// Upon entry on an exception from user, sscratch will contain curlwp.
//
- REG_S tp, L_MD_TP(sp) // save thread pointer temporarily
- mv tp, sp // put curlwp in thread pointer
+ REG_S sp, L_MD_USP(tp) // save user stack pointer temporarily
PTR_L sp, L_MD_UTF(sp) // trapframe pointer loaded
REG_S t1, TF_T1(sp) // save t1
- csrrw t1, sscratch, zero // save saved stack pointer with 0
- REG_S t1, TF_SP(sp) // save stack pointer
- REG_S t1, L_MD_TP(tp) // get thread pointer from temp store
+ REG_S t1, L_MD_USP(tp) // get user stack pointer
REG_L t1, TF_SP(sp) // save thread pointer in trapframe
+ csrrw t1, sscratch, zero // swap saved thread pointer with 0
+ REG_L t1, TF_TP(sp) // save thread pointer in trapframe
+ li t1, 0 // indicate user exception
j .Lexception_common
//
@@ -333,11 +333,13 @@ ENTRY_NP(cpu_exception_handler)
// trapframe for use by the exception exiting code.
//
.Lexception_kernel:
- csrrw sp, sscratch, zero // get back our stack pointer
+ csrrw tp, sscratch, zero // get back our thread pointer
addi sp, sp, -TF_LEN // allocate stack frame
REG_S t1, TF_T1(sp) // save t1
addi t1, sp, TF_LEN
REG_S t1, TF_SP(sp) // save SP
+ li t1, 1 // indicate kernel exception
+
.Lexception_common:
// Now we save all the temporary registers into the trapframe since
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: matt Date: Tue Mar 31 11:48:10 UTC 2015 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Fix botch on putting user stack pointer into trapframe. To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.3 src/sys/arch/riscv/riscv/locore.S:1.4 --- src/sys/arch/riscv/riscv/locore.S:1.3 Tue Mar 31 06:47:47 2015 +++ src/sys/arch/riscv/riscv/locore.S Tue Mar 31 11:48:10 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.3 2015/03/31 06:47:47 matt Exp $ */ +/* $NetBSD: locore.S,v 1.4 2015/03/31 11:48:10 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -318,8 +318,8 @@ ENTRY_NP(cpu_exception_handler) REG_S sp, L_MD_USP(tp) // save user stack pointer temporarily PTR_L sp, L_MD_UTF(sp) // trapframe pointer loaded REG_S t1, TF_T1(sp) // save t1 - REG_S t1, L_MD_USP(tp) // get user stack pointer - REG_L t1, TF_SP(sp) // save thread pointer in trapframe + REG_L t1, L_MD_USP(tp) // get user stack pointer + REG_S t1, TF_SP(sp) // save thread pointer in trapframe csrrw t1, sscratch, zero // swap saved thread pointer with 0 REG_L t1, TF_TP(sp) // save thread pointer in trapframe li t1, 0 // indicate user exception
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: matt Date: Tue Mar 31 11:53:14 UTC 2015 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Accept the one instruction penalty and just use PTR_LA instead of doing the relocs ourselves. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.4 src/sys/arch/riscv/riscv/locore.S:1.5 --- src/sys/arch/riscv/riscv/locore.S:1.4 Tue Mar 31 11:48:10 2015 +++ src/sys/arch/riscv/riscv/locore.S Tue Mar 31 11:53:13 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.4 2015/03/31 11:48:10 matt Exp $ */ +/* $NetBSD: locore.S,v 1.5 2015/03/31 11:53:13 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -78,10 +78,10 @@ ENTRY_NP(start) call memset // zero through kernel_end // As a temporary hack, word 0 contains the amount of memory in MB - INT_L a7, (zero) // load memory size - slli a7, a7, (20-PGSHIFT) // convert MB to pages -.L01: auipc t0, %pcrel_hi(physmem) - INT_S a7, %pcrel_lo(.L01)(t0) // store it in physmem + INT_L a7, (zero) // load memory size + slli a7, a7, (20-PGSHIFT) // convert MB to pages +.L01: PTR_LA t0, physmem + INT_S a7, (t0) // store it in physmem li t4, PTE_V | PTE_SX | PTE_SW | PTE_SR | PTE_G #ifdef _LP64
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:14:02 UTC 2015
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
No more fatc (replaced by sfence.vm instruction).
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.2 src/sys/arch/riscv/include/sysreg.h:1.3
--- src/sys/arch/riscv/include/sysreg.h:1.2 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/include/sysreg.h Tue Mar 31 01:14:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.2 2015/03/28 16:13:56 matt Exp $ */
+/* $NetBSD: sysreg.h,v 1.3 2015/03/31 01:14:02 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -217,14 +217,4 @@ riscvreg_asid_write(uint32_t __asid)
__asm __volatile(csrw\tsasid, %0 :: r(__asid));
}
-#if 0
-static inline uintptr_t
-riscvreg_fatc_read(void)
-{
- uint32_t __fatc;
- __asm __volatile(csrr\t%0, fatc : =r(__fatc));
- return __fatc;
-}
-#endif
-
#endif /* _RISCV_SYSREG_H_ */
CVS commit: src/sys/arch/riscv/conf
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:05:52 UTC 2015
Modified Files:
src/sys/arch/riscv/conf: Makefile.riscv
Log Message:
Use -mcmodel=medany to get PICish code.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/conf/Makefile.riscv
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/Makefile.riscv
diff -u src/sys/arch/riscv/conf/Makefile.riscv:1.1 src/sys/arch/riscv/conf/Makefile.riscv:1.2
--- src/sys/arch/riscv/conf/Makefile.riscv:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/conf/Makefile.riscv Tue Mar 31 01:05:52 2015
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.riscv,v 1.1 2015/03/28 16:13:56 matt Exp $
+# $NetBSD: Makefile.riscv,v 1.2 2015/03/31 01:05:52 matt Exp $
# Makefile for NetBSD
#
@@ -38,7 +38,8 @@ GENASSYM_CONF= ${RISCV}/riscv/genassym.c
## Note: -ffixed-?? must be kept in sync with cpu.h.
##
CPPFLAGS+= -D${MACHINE}
-CFLAGS+= -fPIC -Wa,-fno-pic -msoft-float
+CFLAGS+= -mcmodel=medany
+CFLAGS+= -msoft-float
.if !defined(LP64) || ${LP64} == no
CFLAGS+= -m32
AFLAGS+= -m32
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: matt Date: Tue Mar 31 01:30:50 UTC 2015 Modified Files: src/sys/arch/riscv/riscv: locore.S Log Message: Since there is only scratch system register for use on exception, come up with a new scheme for its use. Use PTR_LA, INT_S/INT_L, etc. Disable interrupts when returning from exceptions. Use L_CPU(tp) to get the curcpu pointer. When the cpu gets an exception from kernel mode, the sscratch register will be 0 and curlwp will be in the tp register. When the cpu gets an exception from user mode, the sscratch register will be a pointer to the current lwp. When an exception happends, the sp is atomically swapped with the sscratch register. If the sp is zero, the exception was a kernel exception and the kernel exception path is taken: sp and sscratch are swapped again so sscratch is zero again and then a trapframe is allocated from the kernel stack. The t1 register is saved and then the pre-trapframe sp is written to the trapframe. If sp was non-zero, the exception was from user mode. The tp register is temporarily saved in L_MD_TP(sp) and sp is moved tp. tp now contains a pointer to the current lwp. A pointer to the user trapframe is loaded from L_MD_UTF(tp). Then t1 is saved in the trapframe so it can be used. The old sp is fetched from sscratch while sscratch is zeroed (indicated kernel mode). The old sp is saved in the trapframe. Upon exiting the exception, if the exception is returning to user mode, the contents of tp is written to sscratch. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/locore.S diff -u src/sys/arch/riscv/riscv/locore.S:1.1 src/sys/arch/riscv/riscv/locore.S:1.2 --- src/sys/arch/riscv/riscv/locore.S:1.1 Sat Mar 28 16:13:56 2015 +++ src/sys/arch/riscv/riscv/locore.S Tue Mar 31 01:30:50 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.S,v 1.1 2015/03/28 16:13:56 matt Exp $ */ +/* $NetBSD: locore.S,v 1.2 2015/03/31 01:30:50 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -78,10 +78,10 @@ ENTRY_NP(start) call memset // zero through kernel_end // As a temporary hack, word 0 contains the amount of memory in MB - lw a7, (zero) // load memory size + INT_L a7, (zero) // load memory size slli a7, a7, (20-PGSHIFT) // convert MB to pages - auipc t0, %pcrel_hi(physmem) - sw a7, %pcrel_lo(physmem)(t0) // store it in physmem +.L01: auipc t0, %pcrel_hi(physmem) + INT_S a7, %pcrel_lo(.L01)(t0) // store it in physmem li t4, PTE_V | PTE_SX | PTE_SW | PTE_SR | PTE_G #ifdef _LP64 @@ -115,11 +115,11 @@ ENTRY_NP(start) // // Fill in the PDEs to direct map memory. // -1: REG_S t4, 0(s3) // store PDE +.Lfill: REG_S t4, 0(s3) // store PDE add t4, t4, t3 // advance PA in PDE to next segment add s3, s3, SZREG // advance to next PDE slot addi a7, a7, -1 // count down segment - bgtz a6, 1b // loop if more + bgtz a6, .Lfill // loop if more csrw sptbr, s1 // set the page table base li t0, SR_VM @@ -131,8 +131,7 @@ ENTRY_NP(start) .Lmmu_on: // MMU is on! - PTR_LA a0, _C_LABEL(cpu_info_store) - csrw sscratch, a0 // curcpu() in sscratch + csrw sscratch, zero // zero in sscratch to mark kernel PTR_LA tp, _C_LABEL(lwp0) // put curlwp in tp @@ -151,8 +150,8 @@ ENTRY_NP(start) // Now we should ready to start initializing the kernel. PTR_LA a0, _C_LABEL(start) // kernel_start add a1, s5, s11 // kernel_end - PTR_LA ra, _C_LABEL(main) // return to main - tail _C_LABEL(init_riscv) // do MD startup + call _C_LABEL(init_riscv) // do MD startup + tail _C_LABEL(main) // and transfer to main // not reached END(start) @@ -162,7 +161,7 @@ END(start) ENTRY_NP(cpu_switchto) addi sp, sp, -TF_LEN // allocate trapframe - beqz a0, 1f // can skip saving oldl state? + beqz a0, .Lswitchto_newlwp // can skip saving oldl state? REG_S ra, TF_RA(sp) // save return address REG_S s0, TF_S0(sp) // save callee saved address @@ -181,17 +180,17 @@ ENTRY_NP(cpu_switchto) REG_S t4, TF_SR(sp) // save it REG_S sp, L_MD_KTF(a0) // record trapframe pointer -1: - csrrci t0, sstatus, SR_EI // disable interrupts +.Lswitchto_newlwp: + csrrci t0, sstatus, SR_EI // # disable interrupts - move tp, a1 // put the new lwp in thread pointer + move tp, a1 // # put the new lwp in thread pointer - csrr t1, sscratch // get curcpu - PTR_S tp, CI_CURLWP(t1) // update curcpu with the new curlwp + PTR_L t1, L_CPU(tp) // # get curcpu + PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp - REG_L sp, L_MD_KTF(tp) // load its kernel stack pointer - REG_L t4, TF_SR(sp) // fetch status register - csrw sstatus, t4 // restore it (and
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: matt Date: Tue Mar 31 01:15:26 UTC 2015 Modified Files: src/sys/arch/riscv/riscv: spl.S Log Message: Get curcpu() from L_CPU(tp) To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/spl.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/spl.S diff -u src/sys/arch/riscv/riscv/spl.S:1.1 src/sys/arch/riscv/riscv/spl.S:1.2 --- src/sys/arch/riscv/riscv/spl.S:1.1 Sat Mar 28 16:13:56 2015 +++ src/sys/arch/riscv/riscv/spl.S Tue Mar 31 01:15:26 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: spl.S,v 1.1 2015/03/28 16:13:56 matt Exp $ */ +/* $NetBSD: spl.S,v 1.2 2015/03/31 01:15:26 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. * All rights reserved. @@ -31,7 +31,7 @@ #include machine/asm.h #include assym.h -__RCSID($NetBSD: spl.S,v 1.1 2015/03/28 16:13:56 matt Exp $) +__RCSID($NetBSD: spl.S,v 1.2 2015/03/31 01:15:26 matt Exp $) .data .globl _C_LABEL(ipl_sr_map) @@ -50,22 +50,22 @@ _C_LABEL(ipl_sr_map): ENTRY_NP(splx) // a0 = new lower IPL - csrr a3, sscratch // get curcpu() - lw t0, CI_CPL(a3) // get current IPL + PTR_L a3, L_CPU(tp) // get curcpu() + INT_L t0, CI_CPL(a3) // get current IPL beq a0, t0, 2f .L_splset: // a0 = new ipl - la t0, ipl_sr_map + PTR_LA t0, ipl_sr_map slli a1, a0, 2 // make integer index add t0, t0, a1 // index into table - lw t0, (t0) // get new mask bits to clear + INT_L t0, (t0) // get new mask bits to clear li t2, SR_IM // get mask bits xor t0, t0, t2 // invert mask bits csrc sstatus, t2 // block everything - sw a0, CI_CPL(a3) // change IPL + INT_S a0, CI_CPL(a3) // change IPL beqz t0, 2f csrs sstatus, t0 // unmask appropriate bits -2: lw t4, CI_SOFTINTS(a3) // get softint mask +2: INT_L t4, CI_SOFTINTS(a3) // get softint mask srl t4, t4, a0 // see what softints are pending. beqz t4, 3f // none, just return // there are softints that need to be delivered, so instead of @@ -80,10 +80,10 @@ END(splx) #error IPL_NONE is not 0 #endif ENTRY_NP(spl0) - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() li t0, SR_IM|SR_EI // load SR_IM|EI csrci sstatus, SR_EI // disable interrupts - sw zero, CI_CPL(a3) // set current IPL to IPL_NONE + INT_S zero, CI_CPL(a3) // set current IPL to IPL_NONE csrs sstatus, t0 // unmask all enable interrupts // spl0() is only called rarely so the overhead of always calling // softint_deliver is minimal. @@ -91,61 +91,61 @@ ENTRY_NP(spl0) END(spl0) ENTRY_NP(splhigh) - csrr a3, sscratch // get curcpu() - lw a0, CI_CPL(a3) // get current IPL + PTR_L a3, L_CPU(tp) // get curcpu() + INT_L a0, CI_CPL(a3) // get current IPL li t1, SR_IM // load SR_IM li t0, IPL_HIGH // csrc sstatus, t1 // mask all interrupts - sw t0, CI_CPL(a3) // set it to IPL_HIGH + INT_S t0, CI_CPL(a3) // set it to IPL_HIGH ret END(splhigh) ENTRY_NP(splsoftclock) li a0, IPL_SOFTCLOCK - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splsoftclock) ENTRY_NP(splsoftbio) li a0, IPL_SOFTBIO - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splsoftbio) ENTRY_NP(splsoftnet) li a0, IPL_SOFTNET - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splsoftnet) ENTRY_NP(splsoftserial) li a0, IPL_SOFTSERIAL - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splsoftserial) ENTRY_NP(splvm) li a0, IPL_VM - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splvm) ENTRY_NP(splsched) li a0, IPL_SCHED - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splsched) ENTRY_NP(splddb) li a0, IPL_DDB - csrr a3, sscratch // get curcpu() + PTR_L a3, L_CPU(tp) // get curcpu() j .L_splset END(splddb) ENTRY_NP(splraise) mv t0, a0 // need a0 for return value - csrr a3, sscratch // get curcpu() - lw a0, CI_CPL(a3) // get current IPL + PTR_L a3, L_CPU(tp) // get curcpu() + INT_L a0, CI_CPL(a3) // get current IPL bgt t0, a0, .L_splset // set if new IPL is higher ret END(splraise)
CVS commit: src/sys/arch/riscv/riscv
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:14:57 UTC 2015
Modified Files:
src/sys/arch/riscv/riscv: pmap_machdep.c
Log Message:
Use sfence.vm instruction and change ptbr cse to sptbr csr
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/pmap_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.1 src/sys/arch/riscv/riscv/pmap_machdep.c:1.2
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Tue Mar 31 01:14:57 2015
@@ -31,7 +31,7 @@
#include sys/cdefs.h
-__RCSID($NetBSD: pmap_machdep.c,v 1.1 2015/03/28 16:13:56 matt Exp $);
+__RCSID($NetBSD: pmap_machdep.c,v 1.2 2015/03/31 01:14:57 matt Exp $);
#include sys/param.h
@@ -144,7 +144,7 @@ pmap_md_tlb_check_entry(void *ctx, vaddr
void
pmap_md_pdetab_activate(struct pmap *pmap)
{
- __asm(csrw\tptbr, %0 :: r(pmap-pm_md.md_ptbr));
+ __asm(csrw\tsptbr, %0 :: r(pmap-pm_md.md_ptbr));
}
void
@@ -176,18 +176,18 @@ voidtlb_invalidate_globals(void);
void
tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
{
- (void) riscvreg_fatc_read();
+ __asm __volatile(sfence.vm ::: memory);
}
void
tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
{
- (void) riscvreg_fatc_read();
+ __asm __volatile(sfence.vm ::: memory);
}
bool
tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
{
- (void) riscvreg_fatc_read();
+ __asm __volatile(sfence.vm ::: memory);
return false;
}
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: matt Date: Tue Mar 31 01:12:47 UTC 2015 Modified Files: src/sys/arch/riscv/riscv: genassym.cf Log Message: Add L_MD_TP To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/genassym.cf Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/genassym.cf diff -u src/sys/arch/riscv/riscv/genassym.cf:1.1 src/sys/arch/riscv/riscv/genassym.cf:1.2 --- src/sys/arch/riscv/riscv/genassym.cf:1.1 Sat Mar 28 16:13:56 2015 +++ src/sys/arch/riscv/riscv/genassym.cf Tue Mar 31 01:12:47 2015 @@ -1,4 +1,4 @@ -# $NetBSD: genassym.cf,v 1.1 2015/03/28 16:13:56 matt Exp $ +# $NetBSD: genassym.cf,v 1.2 2015/03/31 01:12:47 matt Exp $ #- # Copyright (c) 2014 The NetBSD Foundation, Inc. # All rights reserved. @@ -114,6 +114,7 @@ define L_CPU offsetof(struct lwp, l_cpu define L_CTXSWTCH offsetof(struct lwp, l_ctxswtch) define L_MD_ASTPENDING offsetof(struct lwp, l_md.md_astpending) define L_MD_ONFAULT offsetof(struct lwp, l_md.md_onfault) +define L_MD_TP offsetof(struct lwp, l_md.md_tp) define L_MD_UTF offsetof(struct lwp, l_md.md_utf) define L_MD_KTF offsetof(struct lwp, l_md.md_ktf) define L_PCB offsetof(struct lwp, l_addr)
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:12:30 UTC 2015
Modified Files:
src/sys/arch/riscv/include: proc.h
Log Message:
Add a md_tp member to mdlwp so that the exception handler can temporarily
store the user's thread pointer before saving it in the trapframe.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/proc.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/proc.h
diff -u src/sys/arch/riscv/include/proc.h:1.1 src/sys/arch/riscv/include/proc.h:1.2
--- src/sys/arch/riscv/include/proc.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/proc.h Tue Mar 31 01:12:29 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: proc.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: proc.h,v 1.2 2015/03/31 01:12:29 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,6 +46,7 @@ struct mdlwp {
struct trapframe *md_utf; /* trapframe from userspace */
struct trapframe *md_ktf; /* trapframe from userspace */
struct faultbuf *md_onfault; /* registers to store on fault */
+ register_t md_tp; /* for locore.S */
vaddr_t md_ss_addr; /* single step address for ptrace */
int md_ss_instr; /* single step instruction for ptrace */
volatile int md_astpending; /* AST pending on return to userland */
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Tue Mar 31 01:11:42 UTC 2015
Modified Files:
src/sys/arch/riscv/include: cpu.h
Log Message:
Define curcpu() as lwp_getcpu(curlwp) since curlwp is always in the tp
(thread pointer) register.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/cpu.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu.h
diff -u src/sys/arch/riscv/include/cpu.h:1.2 src/sys/arch/riscv/include/cpu.h:1.3
--- src/sys/arch/riscv/include/cpu.h:1.2 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/include/cpu.h Tue Mar 31 01:11:41 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.2 2015/03/28 16:13:56 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.3 2015/03/31 01:11:41 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -81,16 +81,13 @@ struct cpu_info {
extern struct cpu_info cpu_info_store;
+// This is also in sys/lwp.h
+struct lwp;
+static inline struct cpu_info *lwp_getcpu(struct lwp *);
+
register struct lwp *riscv_curlwp __asm(tp);
#define curlwp riscv_curlwp
-
-static inline struct cpu_info *
-curcpu(void)
-{
- struct cpu_info *ci;
- __asm(csrr\t%0, sscratch : =r(ci));
- return ci;
-}
+#define curcpu() lwp_getcpu(curlwp)
static inline cpuid_t
cpu_number(void)
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: matt
Date: Sun Mar 29 09:43:26 UTC 2015
Modified Files:
src/sys/arch/riscv/include: lock.h
Log Message:
Use C11 atomic builtins instead of __asm.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/lock.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/lock.h
diff -u src/sys/arch/riscv/include/lock.h:1.1 src/sys/arch/riscv/include/lock.h:1.2
--- src/sys/arch/riscv/include/lock.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/lock.h Sun Mar 29 09:43:26 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: lock.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: lock.h,v 1.2 2015/03/29 09:43:26 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -50,75 +50,51 @@ __SIMPLELOCK_UNLOCKED_P(__cpu_simple_loc
static __inline void
__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
{
-#if 0
- __atomic_clear(__ptr, __ATOMIC_RELAXED);
-#else
+#if 1
*__ptr = __SIMPLELOCK_UNLOCKED;
+#else
+ __atomic_store_n(__ptr, __SIMPLELOCK_UNLOCKED, __ATOMIC_RELAXED);
#endif
}
static __inline void
__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
{
-#if 0
- (void)__atomic_test_and_set(__ptr, __ATOMIC_RELAXED);
-#else
+#if 1
*__ptr = __SIMPLELOCK_LOCKED;
+#else
+ __atomic_store_n(__ptr, __SIMPLELOCK_LOCKED, __ATOMIC_RELAXED);
#endif
}
static __inline void __unused
__cpu_simple_lock_init(__cpu_simple_lock_t *__ptr)
{
-#if 0
- __atomic_clear(__ptr, __ATOMIC_RELAXED);
-#else
+#if 1
*__ptr = __SIMPLELOCK_UNLOCKED;
+#else
+ __atomic_store_n(__ptr, __SIMPLELOCK_UNLOCKED, __ATOMIC_RELAXED);
#endif
}
static __inline void __unused
__cpu_simple_lock(__cpu_simple_lock_t *__ptr)
{
-#if 0
- while (__atomic_test_and_set(__ptr, __ATOMIC_ACQUIRE)) {
+ while (__atomic_exchange_n(__ptr, __SIMPLELOCK_LOCKED, __ATOMIC_ACQUIRE) == __SIMPLELOCK_LOCKED) {
/* do nothing */
}
-#else
- int __tmp;
- __asm(
- \n 1:
- \n\t amoswap.w.aq %[__tmp], %[__newval], 0(%[__ptr])
- \n\t bnez %[__tmp], 1b
- : [__tmp] =r (__tmp)
- : [__newval] r (__SIMPLELOCK_LOCKED),
- [__ptr] r (__ptr));
-#endif
}
static __inline int __unused
__cpu_simple_lock_try(__cpu_simple_lock_t *__ptr)
{
-#if 0
- return !__atomic_test_and_set(__ptr, __ATOMIC_ACQUIRE);
-#else
- int __oldval;
- __asm( amoswap.w.aq\t%[__oldval], %[__newval], 0(%[__ptr])
- : [__oldval] =r (__oldval)
- : [__newval] r (__SIMPLELOCK_LOCKED),
- [__ptr] r (__ptr));
- return __oldval == __SIMPLELOCK_UNLOCKED;
-#endif
+ return __atomic_exchange_n(__ptr, __SIMPLELOCK_LOCKED, __ATOMIC_ACQUIRE) == __SIMPLELOCK_LOCKED;
}
static __inline void __unused
__cpu_simple_unlock(__cpu_simple_lock_t *__ptr)
{
-#if 0
- __atomic_clear(__ptr, __ATOMIC_RELEASE);
-#else
- __asm(amoswap.w.rl\tx0, x0, 0(%[__ptr]) :: [__ptr] r (__ptr));
-#endif
+ __atomic_store_n(__ptr, __SIMPLELOCK_UNLOCKED, __ATOMIC_RELEASE);
}
#endif /* _RISCV_LOCK_H_ */
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: matt Date: Fri Mar 27 06:57:21 UTC 2015 Modified Files: src/sys/arch/riscv/include: asm.h elf_machdep.h mcontext.h reg.h setjmp.h Log Message: Switch to new ABI (return values now in a0/a1; v0/v1 are no more) To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/asm.h \ src/sys/arch/riscv/include/elf_machdep.h src/sys/arch/riscv/include/reg.h \ src/sys/arch/riscv/include/setjmp.h cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/mcontext.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/asm.h diff -u src/sys/arch/riscv/include/asm.h:1.1 src/sys/arch/riscv/include/asm.h:1.2 --- src/sys/arch/riscv/include/asm.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/asm.h Fri Mar 27 06:57:21 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: asm.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -119,9 +119,9 @@ #define RCSID(name) __RCSID(name) #if defined(_LP64) -#define SZREG 4 -#else #define SZREG 8 +#else +#define SZREG 4 #endif #define ALSK 15 /* stack alignment */ Index: src/sys/arch/riscv/include/elf_machdep.h diff -u src/sys/arch/riscv/include/elf_machdep.h:1.1 src/sys/arch/riscv/include/elf_machdep.h:1.2 --- src/sys/arch/riscv/include/elf_machdep.h:1.1 Fri Sep 19 17:36:26 2014 +++ src/sys/arch/riscv/include/elf_machdep.h Fri Mar 27 06:57:21 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -56,59 +56,55 @@ /* Processor specific relocation types */ #define R_RISCV_NONE 0 -#define R_RISCV_32 2 // A -#define R_RISCV_REL32 3 // A 0x -#define R_RISCV_JAL 4 // A 0xff -#define R_RISCV_HI20 5 // A 0x -#define R_RISCV_LO12_I 6 // (A 16) 0x -#define R_RISCV_LO12_S 7 // (S + A - P) 2 -#define R_RISCV_PCREL_LO12_I 8 -#define R_RISCV_PCREL_LO12_S 9 -#define R_RISCV_BRANCH 10 // (A - P) 0x -#define R_RISCV_CALL 11 // (A - P) 0xff -#define R_RISCV_PCREL_HI20 12 -#define R_RISCV_CALL_PLT 13 -#define R_RISCV_64 18 -#define R_RISCV_GOT_HI20 22 -#define R_RISCV_GOT_LO12 23 -#define R_RISCV_COPY 24 -#define R_RISCV_JMP_SLOT 25 -/* TLS relocations. */ -#define R_RISCV_TLS_IE_HI20 29 -#define R_RISCV_TLS_IE_LO12 30 -#define R_RISCV_TLS_IE_ADD 31 -#define R_RISCV_TLS_IE_LO12_I 32 -#define R_RISCV_TLS_IE_LO12_S 33 -#define R_RISCV_TPREL_HI20 34 -#define R_RISCV_TLREL_LO12_I 35 -#define R_RISCV_TLREL_LO12_S 36 -#define R_RISCV_TLREL_ADD 37 - -#define R_RISCV_TLS_DTPMOD32 38 -#define R_RISCV_TLS_DTPREL32 39 -#define R_RISCV_TLS_DTPMOD64 40 -#define R_RISCV_TLS_DTPREL64 41 -#define R_RISCV_TLS_DTPREL_HI16 44 -#define R_RISCV_TLS_DTPREL_LO16 45 -#define R_RISCV_TLS_PCREL_LO12 50 -#define R_RISCV_TLS_GOT_HI20 51 -#define R_RISCV_TLS_GOT_LO20 52 -#define R_RISCV_TLS_GD_HI20 53 -#define R_RISCV_TLS_GD_LO20 54 - -#define R_RISCV_GLOB_DAT 57 -#define R_RISCV_ADD32 58 -#define R_RISCV_SUB32 59 -#define R_RISCV_ADD64 60 -#define R_RISCV_SUB64 61 +#define R_RISCV_32 1 // A +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPREL32 7 +#define R_RISCV_TLS_DTPMOD64 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_DTPREL64 11 + +/* The rest are not used by the dynamic linker */ +#define R_RISCV_BRANCH 16 // (A - P) 0x +#define R_RISCV_JAL 17 // A 0xff +#define R_RISCV_CALL 18 // (A - P) 0xff +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 // A 0x +#define R_RISCV_LO12_I 27 // (A 16) 0x +#define R_RISCV_LO12_S 28 // (S + A - P) 2 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TLREL_LO12_I 30 +#define R_RISCV_TLREL_LO12_S 31 +#define R_RISCV_TLREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GNU_VTINHERIT 41 // A 0x +#define R_RISCV_GNU_VTENTRY 42 +#define R_RISCV_ALIGN 43 + #define R_TYPE(name) R_RISCV_ ## name +#if ELFSIZE == 32 +#define R_TLS_TYPE(name) R_RISCV_ ## name ## 32 +#else #define R_TLS_TYPE(name) R_RISCV_ ## name ## 64 - -#define DT_RISCV_LOCAL_GOTNO (DT_LOPROC + 0) -#define DT_RISCV_SYMTABNO (DT_LOPROC + 1) -#define DT_RISCV_GOTSYM (DT_LOPROC + 2) -#define DT_RISCV_PLTGOT (DT_LOPROC + 3) +#endif #ifdef _KERNEL #ifdef
CVS commit: src/sys/arch/riscv/include
Module Name:src Committed By: matt Date: Fri Mar 27 23:26:14 UTC 2015 Modified Files: src/sys/arch/riscv/include: elf_machdep.h Log Message: Fix one error and make life for ld.elf_so a little easier. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/elf_machdep.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/include/elf_machdep.h diff -u src/sys/arch/riscv/include/elf_machdep.h:1.2 src/sys/arch/riscv/include/elf_machdep.h:1.3 --- src/sys/arch/riscv/include/elf_machdep.h:1.2 Fri Mar 27 06:57:21 2015 +++ src/sys/arch/riscv/include/elf_machdep.h Fri Mar 27 23:26:14 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: elf_machdep.h,v 1.2 2015/03/27 06:57:21 matt Exp $ */ +/* $NetBSD: elf_machdep.h,v 1.3 2015/03/27 23:26:14 matt Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -66,7 +66,7 @@ #define R_RISCV_TLS_DTPMOD64 8 #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 -#define R_RISCV_TLS_DTPREL64 11 +#define R_RISCV_TLS_TPREL64 11 /* The rest are not used by the dynamic linker */ #define R_RISCV_BRANCH 16 // (A - P) 0x @@ -98,12 +98,15 @@ #define R_RISCV_GNU_VTENTRY 42 #define R_RISCV_ALIGN 43 +/* These are aliases we can use R_TYPESZ */ +#define R_RISCV_ADDR32 R_RISCV_32 +#define R_RISCV_ADDR64 R_RISCV_64 #define R_TYPE(name) R_RISCV_ ## name #if ELFSIZE == 32 -#define R_TLS_TYPE(name) R_RISCV_ ## name ## 32 +#define R_TYPESZ(name) R_RISCV_ ## name ## 32 #else -#define R_TLS_TYPE(name) R_RISCV_ ## name ## 64 +#define R_TYPESZ(name) R_RISCV_ ## name ## 64 #endif #ifdef _KERNEL
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: dennis
Date: Tue Oct 28 19:46:18 UTC 2014
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Correct 32 and 64 bit byte swap inlines.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/byte_swap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/byte_swap.h
diff -u src/sys/arch/riscv/include/byte_swap.h:1.1 src/sys/arch/riscv/include/byte_swap.h:1.2
--- src/sys/arch/riscv/include/byte_swap.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/byte_swap.h Tue Oct 28 19:46:18 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: byte_swap.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: byte_swap.h,v 1.2 2014/10/28 19:46:18 dennis Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -63,9 +63,9 @@ static __inline uint64_t
__byte_swap_u64_variable(uint64_t v)
{
v = ((v 0x00ff) (56 - 0)) | ((v (56 - 0)) 0x00ff)
- | ((v 0xff00) (48 - 8)) | ((v (48 - 8)) 0xff00)
- | ((v 0x00ff) (40 - 16)) | ((v (40 - 16)) 0x00ff)
- | ((v 0xff00) (32 - 24)) | ((v (32 - 24)) 0xff00);
+ | ((v 0xff00) (48 - 8)) | ((v (48 - 8)) 0xff00)
+ | ((v 0x00ff) (40 - 16)) | ((v (40 - 16)) 0x00ff)
+ | ((v 0xff00) (32 - 24)) | ((v (32 - 24)) 0xff00);
return v;
}
@@ -75,7 +75,7 @@ static __inline uint32_t
__byte_swap_u32_variable(uint32_t v)
{
v = ((v 0x00ff) (24 - 0)) | ((v (24 - 0)) 0x00ff)
- | ((v 0xff00) (16 - 8)) | ((v (16 - 8)) 0xff00);
+ | ((v 0xff00) (16 - 8)) | ((v (16 - 8)) 0xff00);
return v;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: dennis
Date: Tue Oct 28 20:25:36 UTC 2014
Modified Files:
src/sys/arch/riscv/include: byte_swap.h
Log Message:
Shave an instruction from the generated code for the 32 bit byte
swap inline. Prune 5 or 9 instructions (depending on what you count)
from the 64 bit byte swap inline.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/byte_swap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/byte_swap.h
diff -u src/sys/arch/riscv/include/byte_swap.h:1.2 src/sys/arch/riscv/include/byte_swap.h:1.3
--- src/sys/arch/riscv/include/byte_swap.h:1.2 Tue Oct 28 19:46:18 2014
+++ src/sys/arch/riscv/include/byte_swap.h Tue Oct 28 20:25:36 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: byte_swap.h,v 1.2 2014/10/28 19:46:18 dennis Exp $ */
+/* $NetBSD: byte_swap.h,v 1.3 2014/10/28 20:25:36 dennis Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -62,10 +62,12 @@ __BEGIN_DECLS
static __inline uint64_t
__byte_swap_u64_variable(uint64_t v)
{
- v = ((v 0x00ff) (56 - 0)) | ((v (56 - 0)) 0x00ff)
- | ((v 0xff00) (48 - 8)) | ((v (48 - 8)) 0xff00)
- | ((v 0x00ff) (40 - 16)) | ((v (40 - 16)) 0x00ff)
- | ((v 0xff00) (32 - 24)) | ((v (32 - 24)) 0xff00);
+ const uint64_t m1 = 0xull;
+ const uint64_t m0 = 0x00ff00ff00ff00ffull;
+
+ v = (v 32) | (v 32);
+ v = ((v 16) m1) | ((v m1) 16);
+ v = ((v 8) m0) | ((v m0) 8);
return v;
}
@@ -74,8 +76,10 @@ __byte_swap_u64_variable(uint64_t v)
static __inline uint32_t
__byte_swap_u32_variable(uint32_t v)
{
- v = ((v 0x00ff) (24 - 0)) | ((v (24 - 0)) 0x00ff)
- | ((v 0xff00) (16 - 8)) | ((v (16 - 8)) 0xff00);
+ const uint32_t m = 0xff00ff;
+
+ v = (v 16) | (v 16);
+ v = ((v 8) m) | ((v m) 8);
return v;
}
CVS commit: src/sys/arch/riscv/include
Module Name:src
Committed By: dennis
Date: Fri Oct 24 01:08:07 UTC 2014
Modified Files:
src/sys/arch/riscv/include: mcontext.h
Log Message:
Fix a typo: the PC is likely in _REG_PC
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/mcontext.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/mcontext.h
diff -u src/sys/arch/riscv/include/mcontext.h:1.1 src/sys/arch/riscv/include/mcontext.h:1.2
--- src/sys/arch/riscv/include/mcontext.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/mcontext.h Fri Oct 24 01:08:07 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: mcontext.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: mcontext.h,v 1.2 2014/10/24 01:08:07 dennis Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -117,7 +117,7 @@ typedef struct {
#define _UC_TLSBASE 0x0008 /* see sys/ucontext.h */
#define _UC_MACHINE_SP(uc) ((uc)-uc_mcontext.__gregs[_REG_SP])
-#define _UC_MACHINE_PC(uc) ((uc)-uc_mcontext.__gregs[_REG_LR])
+#define _UC_MACHINE_PC(uc) ((uc)-uc_mcontext.__gregs[_REG_PC])
#define _UC_MACHINE_INTRV(uc) ((uc)-uc_mcontext.__gregs[_REG_RV])
#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
