Re: [time-nuts] Divide by five
In message 54614a56.4010...@rubidium.dyndns.org, Magnus Danielson writes: There used to be an academic paper on timing.com's home-page about their clock-ensemble algorithm called something like Advances in Time-Scale Algorithms. PTTI 24, Sam Steins work: http://tycho.usno.navy.mil/ptti/1992papers/Vol%2024_28.pdf There you go... I've long toyed with the idea of building ensemble clock, but never got around to it. I did some experiments based on that timing.com paper, but didn't really have enough clocks for it to be worthwhile, and the cooling in my lap couldn't cope with me turning so much kit on at the same time during summer. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi On Nov 12, 2014, at 5:24 PM, Poul-Henning Kamp p...@phk.freebsd.dk wrote: In message 54614a56.4010...@rubidium.dyndns.org, Magnus Danielson writes: There used to be an academic paper on timing.com's home-page about their clock-ensemble algorithm called something like Advances in Time-Scale Algorithms. PTTI 24, Sam Steins work: http://tycho.usno.navy.mil/ptti/1992papers/Vol%2024_28.pdf There are a raft of papers from the 60’s and 70’s talking about the paper clocks and their initial efforts to turn them into software versions of the paper tables. There you go... I've long toyed with the idea of building ensemble clock, but never got around to it. I did some experiments based on that timing.com paper, but didn't really have enough clocks for it to be worthwhile, and the cooling in my lap couldn't cope with me turning so much kit on at the same time during summer. It has occurred to me that running 100 Rubidiums at 15W each might get the electric meter spinning a bit fast. It’s also not really very clear how to test the result without building two or three of them. Keeping three batches of 100 Rb’s from talking to each other on a thermal basis might be even more difficult than the basic issues around a 4.5KW load plus cooling 24 hours a day. Lots to think about. Bob -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Poul-Henning, On 11/09/2014 09:44 PM, Poul-Henning Kamp wrote: In message CABbxVHtommjwSWq1i=oH-u1S=G6P=xu8e0yzekadg-vchgk...@mail.gmail.com , Chris Albertson writes: NTP does not pick the best clock. NTP finds the subset of clocks that track each other. NTP does indeed find the best clock from the subset of clocks which pass its sanity check, and then it uses only that one. There are several problems with that, and as we speak I'm developing a new algorithm which at least so far, gives much superior performance. You can read my musings about this here: http://phk.freebsd.dk/time/20141107.html My goal is to release the new NTP client before X-mas. Just as you point out, there is no easy way around the fact that delays may be asymmetric. When one analyzes the problem, the actual time-error and delays in both directions cannot be solved with the two measurements one do, three unknowns and two equations. The sum of the observations, forming the Round-Trip-Time, is however the only value we can trust, and worst case asymmetry will be that of the RTT, regardless of statistical distribution. Using RTT as a worst-case estimator is thus enough if you don't know better, and using RTT as a simple stability estimator isn't all that bad for a simple system. The NTP scatter-plot wedge is another way to present it, and finding the tip of that wedge is really about finding the min-value of delay in each direction prior to doing the two-way time-transfer equations. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
In message 546070b3.1010...@rubidium.dyndns.org, Magnus Danielson writes: The NTP scatter-plot wedge is another way to present it, and finding the tip of that wedge is really about finding the min-value of delay in each direction prior to doing the two-way time-transfer equations. The important part about the wedge diagram is that the wedge is not filled out. With a very large probability only one of the two packets is impacted by extra delays. The current NTP filter totally fails to exploit this fact and performs quite a bit worse because of it: A median filter is really not a suitable way to handle that situation. But steering back to the original topic again: You really should not look at NTP for clock-ensemble or clock-steering examples, the challenges NTP copes with, are nothing like the challenges you have with a bunch of local high-quality frequencies. There used to be an academic paper on timing.com's home-page about their clock-ensemble algorithm called something like Advances in Time-Scale Algorithms. It's not super detailed but it was certainly a much better place to start than NTP source or documentation -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
Hi On Nov 10, 2014, at 1:59 AM, Poul-Henning Kamp p...@phk.freebsd.dk wrote: In message 4cdc0090-dd4b-4380-acc1-40a80d3bc...@n1k.org, Bob Camp writes: Hi Here’s what I’m saying: The NTP algorithm as it is written and as it is implemented results in an output clock that does *not* improve when a number of very good clocks are being used [...] The crucial word here is good clocks. A good clock in NTP is nearby and because it is nearby, the chances of several of them overlapping is usually not high enough for any clock combining to happen. Yes, in normal NTP land it’s not in any way worth worrying about. The NTP algorithms were built for 10-100msec packet delays, not low microsecond packet delays. NTP is designed to do something very different. Bob -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Nov 10, 2014, at 2:49 AM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 11/09/2014 07:11 PM, Bob Camp wrote: Hi On Nov 9, 2014, at 11:18 AM, Chris Albertson albertson.ch...@gmail.com wrote: On Sat, Nov 8, 2014 at 11:13 PM, Neil Schroeder gign...@gmail.com wrote: At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NTP does this but on a MUCH lower frequency and longer time scale. But I think NTP's general method could apply. NTP will accept any number of reference clocks. (Yes sone people run NTP using just one GPS receiver as a reference but best practice is to use five references.) NTP compares the set of ref. clocks with each other and first tries to find the subset of clocks that track each other, assuming the outliers are wrong. It continuously checks this and maintains a set of true tickers. From these it computes a consensus time using a weighted average of the true clocks. The weights are based on the jitter and other quality measuring statistics. Using this method reference clocks can be taken on and off line without need to re-start NTP. That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. The aim is to remove false-tickers and then build the best ensemble of the remaining sources and weigh them according to stability. It seems this goal is not very well met in practice, but the theory foundation is pretty good. The intent of NTP is great. The implementation is targeted at the real NTP world. A set of good clocks that all are equally good simply is not what happens in the real NTP world. They don’t address it because it does not happen often enough to matter. Bob Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Poul-Henning, On 11/10/2014 09:16 AM, Poul-Henning Kamp wrote: In message 546070b3.1010...@rubidium.dyndns.org, Magnus Danielson writes: The NTP scatter-plot wedge is another way to present it, and finding the tip of that wedge is really about finding the min-value of delay in each direction prior to doing the two-way time-transfer equations. The important part about the wedge diagram is that the wedge is not filled out. With a very large probability only one of the two packets is impacted by extra delays. The current NTP filter totally fails to exploit this fact and performs quite a bit worse because of it: A median filter is really not a suitable way to handle that situation. Completely agree. Also, NTP uses far too few packets to get any meaningful statistics on the edges of the wedge, which is to say the minimum value in either direction. Also, long-term averaging makes the TE part draw towards zero, so if there is a sufficiently long run with high asymmetric delay, the node tracks in the precieved offset error and thus asymmetric delay will affect the time of the node. But steering back to the original topic again: You really should not look at NTP for clock-ensemble or clock-steering examples, the challenges NTP copes with, are nothing like the challenges you have with a bunch of local high-quality frequencies. Fully agree. In fact, missing this point is part of the problem that NTP has. There used to be an academic paper on timing.com's home-page about their clock-ensemble algorithm called something like Advances in Time-Scale Algorithms. PTTI 24, Sam Steins work: http://tycho.usno.navy.mil/ptti/1992papers/Vol%2024_28.pdf It's not super detailed but it was certainly a much better place to start than NTP source or documentation I think the simplest case is that of Dave Allan and friends put down in the NBS Monograph 140, chapter 9: http://tf.boulder.nist.gov/general/pdf/194.pdf They have even thrown in the Fortran code that they used. I think it originally ran on a PDP-7 or something. You do want to read the 9.3 part, as it is the runner-up to the 9.4 part which gets dirty into how to do it. I think that will give a first concrete starting-point, and there is more development in both NBS/NIST, USNO etc. (see NIST and USNO PTTI archives). I've long toyed with the idea of building ensemble clock, but never got around to it. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
On 11/09/2014 10:54 PM, Chris Albertson wrote: On Sun, Nov 9, 2014 at 12:45 PM, Bob Camp kb...@n1k.org wrote: Hi The main point is that NTP picks *one* source from among it’s batch of inputs and uses that. The ADEV of the output can be no better than the ADEV of the output. The statement above is not correct. NTP does not select just one clock. The statement below is correct and is what NTP actually does. If you look at the output from ntpstat you might think NTP selects one clock but internally it's not going that. The display is misleading. In the case of an ensemble of clocks combined with a better approach the ADEV of the output can be better than the ADEV of the best clock in the group. It's best to read this http://www.eecis.udel.edu/~mills/ntp/html/warp.html In simple terms it searches for consensus range of time where all the error bars of the various clock overlap and then eliminate clocks who d't agree with the consensus. Of those still in it figures out and kind of weighted average. I think you could do the same thing. First find the set of 10MHz oscillators who are in phase with each other to within some statistical limit and then you compute the weighted average phase Maybe start with Clock Select Algorithm. Free-running oscillators won't be agreeing on phase. As they have different independent frequency that we observe without steering, they won't agree on phase. NTP on the other hand assumes that the sources is sources of UTC, and thus have one way or another been coordinated with that unifying phase, then and only then it makes sense to compare the phase of the individual sources, but it's not really independent clocks. What you can do is to have a set of free-running oscillators, use them to build a ensemble paper-clock average, which when weighing them against the stability of the ensemble clock the individual stability will expose itself, and that ensemble clock will have some weighted frequency, and the individual clocks offset from that average frequency would be known, and momentary phases and prediction of those phases into the future can be done, and well deviations from that gives new info. However, the average frequency won't be a true frequency, and if the clocks is way to similar, there will be considerable common mode effect from the environment, but it will be some improved stability in there. If you compare it to some outside clock, long-term frequency and phase adjustments can be done to align it up to some time-scale, and that source would also give a measure of the ensemble stability and precision. This is similar to how EAL is a ensemble-clock out of about 450 atomic clocks, and that a few of them is considered phase-accurate is used to correct into the TAI clock. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi On Nov 10, 2014, at 6:33 PM, Magnus Danielson mag...@rubidium.se wrote: Bob, On 11/10/2014 01:17 PM, Bob Camp wrote: On Nov 10, 2014, at 2:49 AM, Magnus Danielson mag...@rubidium.dyndns.org wrote: On 11/09/2014 07:11 PM, Bob Camp wrote: Hi That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. The aim is to remove false-tickers and then build the best ensemble of the remaining sources and weigh them according to stability. It seems this goal is not very well met in practice, but the theory foundation is pretty good. The intent of NTP is great. The implementation is targeted at the real NTP world. A set of good clocks that all are equally good simply is not what happens in the real NTP world. They don’t address it because it does not happen often enough to matter. Who said equally good? Rather, they are sufficiently near each other so that some weighted average can be formed. My original example that started this whole sub sub thread … I was trying very hard to keep things simple. Bob However, some of the issues is in getting close enough. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
What you can do is to have a set of free-running oscillators, use them to build a ensemble paper-clock average, which when weighing them against the stability of the ensemble clock the individual stability will expose itself, and that ensemble clock will have some weighted frequency, and the individual clocks offset from that average frequency would be known, and momentary phases and prediction of those phases into the future can be done, and well deviations from that gives new info. I like the term paper clock. I assume it means an oscillator that does not physically exist but if it did would have the minimum weighted difference relative to the set of physical clocks when measured over some time span. Your final ensemble time then would be the output of any oscillator plus a data stream that gives difference between it and the paper clock. Of course the controller would select a good oscillator and try and discipline it well but there will still be an error. This is like what a GPS does when it outputs a sawtooth function. The GPS does it's best to put the PPS at theocracy time. It can't get it perfect but it can determine the error -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Go on - actually stepping or mixing then filtering the output? Or numerically deriving an offset? I am well on my way to en ensemble of sources - and my plan has always been to build a diverse set of circuits and attempt to capture the best of each. I just wasn't sure the best approach. At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NS On Sat, Nov 8, 2014 at 6:35 PM, Bob Camp kb...@n1k.org wrote: Hi One of the more interesting uses for something like a Cyclone V would be a front end board to drive a KS-24361 from an ensemble of sources. That’s what David Allan’s original idea was when he started the whole software empire that turned into the Z3801 and all the rest. Bob On Nov 8, 2014, at 8:36 PM, Bert Kehren via time-nuts time-nuts@febo.com wrote: We do most our projects with Altera G/A. The biggest benefit is that if something does not work on first pass changing the G/A logic is much faster, less costly than a new board layout. Bert Kehren In a message dated 11/8/2014 6:17:29 P.M. Eastern Standard Time, kb...@n1k.org writes: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy any hardware. All the design tools are schematic entry capable and free on the web. There’s not a big speed bump when you start using them (like say needing to go learn VHDL…). Once you get using them, the CPLD's are quite handy for a wide range of projects, way beyond a simple divide by 5. Their bigger cousins (the FPGA’s) aren’t that much more (under $35) and they will do a LOT, especially in the newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob On Nov 8, 2014, at 5:58 PM, cfo xne...@luna.dyndns.dk wrote: On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote: can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF I'd suggest ALTERA parts , but only because they are the cheapest boards on *bay , XILINX boards are 2 x the Altera price on *Bay. An EPM240 CPLD Board $9 (240 cells let you do quite a lot) http://tinyurl.com/qcusb69 There's also an EPM-570 Board , but the price is almost the same as the below FPGA , and then the FPGA is the thing to get. A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value for the money http://tinyurl.com/pd326ct An ALTERA Programmer $6 http://tinyurl.com/po2qhq2 The only caveat is that they are NOT 5v tolerant , they can do 3v3 or less. ALTERA has the free QuartusII WEB Edition , and it works fine under both Windows Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based under the hood) I am a VHDL beginner , and completed this (free) course s few month back Course http://tinyurl.com/per8lm5 Forum http://tinyurl.com/pw3b9bv I have just did a divide by 5 with the EP2C5T144 FPGA board , using one of the PLL's. I did use so few resources, that it reported 0% of the 4608 Cells utilized, and 1 of 2 PLL's used. *** SNIP * Fitter StatusSuccessful - Sat Nov 8 23:11:59 2014 Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Namediv5pll Top-level Entity Namediv5pll FamilyCyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements0 / 4,608 ( 0 % ) Total combinational functions0 / 4,608 ( 0 % ) Dedicated logic registers0 / 4,608 ( 0 % ) Total registers 0 Total pins6 / 89 ( 7 % ) Total virtual pins0 Total memory bits0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs1 / 2 ( 50 % ) *** SNIP * Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress boards are ALTERA Boards , so i have both tools installed on my linux machine. If you don't feel like learning VHDL or Verilog , you can do the layout in Schematic. ALTERA QuartusII does have an extensive 74xx lib built in the schematic engine. See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration. http://tinyurl.com/ntdkcst Be sure to get these versions of the tools , as both have upgraded their tools , and the new tools doesn't support the older (cheaper chips). Altera QuartusII : Version 13.0sp1 (13.1+ doesn't
Re: [time-nuts] Divide by five
Hi The reason for the KS-2461 box on the end is to make things easy(er). Trying to get all the crossovers done and working into 1 ms / 1 KHz is beyond what I’m willing to do on this project. Here’s my thought: Take the Lucent box and let it do it’s thing out to 100 or (more likely) 1000 seconds. It will play with it’s filters independent of what ever you feed it. Take the 10 MHz out of a source and womp it up with the PLL in the Cyclone. Net result is a clock at 100 MHz. Divide all of your various sources down to 1 pps if they aren’t already 1 pps. Clock in the time of arrival of each pps to within 10 ns. (if you want to do a TDC on each one, 10 ps). Feed all the data to a computer of some sort. Process it and then talk back to the Cyclone. Generate a pps out of the Cyclone modulo 10 ns. Play with the sawtooth correction part of the GPS string to get the pps to 1 ns or less. Yes, this is only one way to do it. There are others with or without an FPGA. The reason I like this approach is that just about anything can be used as a source. Since it’s an anything / everything sort of setup. The “PC will need to do some fairly heavy lifting. You might keep a M0 Arm fairly busy for a few hundred ms. Each source gets modeled and frequency offset is removed. Each measurement is weighted through your filter to give it the right impact on the total. Some sources will be there mainly for long term, others for short term. The output is simply the “next” pps location. The computer generates a fake GPS string to make the KS-2461 box happy and tells the FPGA where to put the PPS. Since you have a 1 second delay inherent in this, it’s not going to do you much good at one (or probably 10) seconds. That’s why you need some sort of fairly good “filter box” on the output. Other ways to do it (still with the Cyclone): Forget about the fancy ex-GPSDO and just lock up an OCXO on the output. You still need a (probably 100 second) (probably digital) loop. Forget about all the pps stuff, just mix them down like in a DMTD. That will take some external “stuff” to filter the mixer outputs. Partially gut the ex-GPSDO and build it all in one box. Use what you need on the GPSDO board and forget the rest. Lots of choices. So, how good *could* it be? You will have the roughly 2x10^-12 ADEV from the KS-2461 out to 100 or 1000 seconds. At 100 seconds 1x10^-12 would be 0.1 ns. 100 samples dithered at 10 ns should get you there. If your sources are good enough (and the filter works ok- it might not) your output will go down as Tau from there based on resolution. It could be: 1x10^-13 at 1,000 sec 1x10^-14 at 10,000 sec 1x10^-15 at 100,000 sec It will not hit those numbers because your input sources won’t be that good. It also will depend a bit on the filter software in the GPSDO doing it’s thing. How good could it be? Say you have telco Rb’s that are in the 3x10^-13 range at 10,000 seconds. Hook up 9 of them and if sqrt(N) works, you are at 1x10^-13. Grab 100 of them and …. Say you have OCXO’s that are in the 2x10^-12 range at 1,000 seconds and cost $10 each. Spend the price of a “fell off the truck” dead Cs standard ($1K) and you are at 2x10^-13. Toss in a GPSDO (or just a GPS) and you can have good long term numbers on top of what ever your local stuff does. Is this a bit nutty - sure. Bob On Nov 9, 2014, at 2:13 AM, Neil Schroeder gign...@gmail.com wrote: Go on - actually stepping or mixing then filtering the output? Or numerically deriving an offset? I am well on my way to en ensemble of sources - and my plan has always been to build a diverse set of circuits and attempt to capture the best of each. I just wasn't sure the best approach. At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NS On Sat, Nov 8, 2014 at 6:35 PM, Bob Camp kb...@n1k.org wrote: Hi One of the more interesting uses for something like a Cyclone V would be a front end board to drive a KS-24361 from an ensemble of sources. That’s what David Allan’s original idea was when he started the whole software empire that turned into the Z3801 and all the rest. Bob On Nov 8, 2014, at 8:36 PM, Bert Kehren via time-nuts time-nuts@febo.com wrote: We do most our projects with Altera G/A. The biggest benefit is that if something does not work on first pass changing the G/A logic is much faster, less costly than a new board layout. Bert Kehren In a message dated 11/8/2014 6:17:29 P.M. Eastern Standard Time, kb...@n1k.org writes: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy
Re: [time-nuts] Divide by five
On Sat, Nov 8, 2014 at 11:13 PM, Neil Schroeder gign...@gmail.com wrote: At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NTP does this but on a MUCH lower frequency and longer time scale. But I think NTP's general method could apply. NTP will accept any number of reference clocks. (Yes sone people run NTP using just one GPS receiver as a reference but best practice is to use five references.) NTP compares the set of ref. clocks with each other and first tries to find the subset of clocks that track each other, assuming the outliers are wrong. It continuously checks this and maintains a set of true tickers. From these it computes a consensus time using a weighted average of the true clocks. The weights are based on the jitter and other quality measuring statistics. Using this method reference clocks can be taken on and off line without need to re-start NTP. You could do the same thing with a set of local oscillators.Divide each down to 1PPS then every second you compare their phases. Keep statistics on drift and standard deviation relative to your consensus phase. You then discipline an OCXO (or several OCXOs) to output that consensus. Like NTP you might accept reference from any number of GPSes or Rb or other standards. You controller might pick the best OCXO in real time as the output. I figure the first generation where we are now, where we build a GPSDO using just one GPS and one OCXO and next generation would use multiples of each. There is not a lot of fancy electronics required. Just some phase comparators that can run once per second. The once pre second data rate is so slow that ANY $5 micro controller could keep up with even a dozen reference clocks. I'd likely us one of the ARM based Arduinos because they are easy enough to program that the barrier to entry is low enough others might be able to contribute. (Think about this if you want to make your design public. If the technology is exotic,no one but you will contribute to further development.) If you like those FPGA boards then you can usually synthesize a CPU and run the controller code on that. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi On Nov 9, 2014, at 11:18 AM, Chris Albertson albertson.ch...@gmail.com wrote: On Sat, Nov 8, 2014 at 11:13 PM, Neil Schroeder gign...@gmail.com wrote: At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NTP does this but on a MUCH lower frequency and longer time scale. But I think NTP's general method could apply. NTP will accept any number of reference clocks. (Yes sone people run NTP using just one GPS receiver as a reference but best practice is to use five references.) NTP compares the set of ref. clocks with each other and first tries to find the subset of clocks that track each other, assuming the outliers are wrong. It continuously checks this and maintains a set of true tickers. From these it computes a consensus time using a weighted average of the true clocks. The weights are based on the jitter and other quality measuring statistics. Using this method reference clocks can be taken on and off line without need to re-start NTP. That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. You could do the same thing with a set of local oscillators.Divide each down to 1PPS then every second you compare their phases. Keep statistics on drift and standard deviation relative to your consensus phase. You then discipline an OCXO (or several OCXOs) to output that consensus. Like NTP you might accept reference from any number of GPSes or Rb or other standards. You controller might pick the best OCXO in real time as the output. I figure the first generation where we are now, where we build a GPSDO using just one GPS and one OCXO and next generation would use multiples of each. You *do* need a way to do this with pretty high precision. The 10 ns number I tossed around earlier is sort of an upper bound. The closer you get to 0.1 ns, the better things might get. There is not a lot of fancy electronics required. Just some phase comparators that can run once per second. The once pre second data rate is so slow that ANY $5 micro controller could keep up with even a dozen reference clocks. I'd likely us one of the ARM based Arduinos because they are easy enough to program that the barrier to entry is low enough others might be able to contribute. (Think about this if you want to make your design public. If the technology is exotic,no one but you will contribute to further development.) If you like those FPGA boards then you can usually synthesize a CPU and run the controller code on that. I would very much avoid an FPGA based CPU. You likely will need to add both flash and ram to the FPGA. Once you are done, you have a $30 gizmo that replaces a $1 chip. You also have a tool chain for your code that is far from “low barrier to entry”. It’s a great solution for something like video processing that needs TONS of bandwidth. We are very much on the other end of that stick. Bob -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Sun, Nov 9, 2014 at 1:11 PM, Bob Camp kb...@n1k.org wrote: NTP's aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. By default NTP makes a paper clock from all acceptable sources (up to some maximum) to discipline a/the/its system clock. One source is special -- The mitigation rules select from among the survivors a *system peer* from which a set of system statistics can be inherited and passed along to dependent clients, if any -- but not for the discipline process. Unfortunately peer can be a bit confusing in this context so I prefer source. This is not to say that the NTP paper clock algorithm is particularly good or suitable for other purposes and the code may be simplified because the assumption is a relatively small (10) number of survivors. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Sun, Nov 9, 2014 at 10:11 AM, Bob Camp kb...@n1k.org wrote: That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. No, not pick one as best. NTP does not pick the best clock. NTP finds the subset of clocks that track each other. Clocks are allowed to enter and leave this set. NTP then computes a weighted average of the clocks in the set. Pretty much what you said you wanted. These two algorithms are used. Conceptually that are run one after the other but actually they run together in a loop forever 1) clock selection http://www.eecis.udel.edu/~mills/ntp/html/select.html 2) clock cluster http://www.eecis.udel.edu/~mills/ntp/html/cluster.html You would not want to use this exact algorithm but something like it. I think the basic idea is simple: Reference clocks should tend to cluster around correct behavior. In other words our set of reference clocks is not biased. I don't think there is any way to detect bias unless you add more reference clocks. I would very much avoid an FPGA based CPU. You likely will need to add both flash and ram to the FPGA. Once you are done, you have a $30 gizmo that replaces a $1 chip. You also have a tool chain for your code that is far from “low barrier to entry”. It’s a great solution for something like video processing that needs TONS of bandwidth. We are very much on the other end of that stick. I agree. Unless the whole this is FPGA based and you have enough free gates. Otherwise it is not good to use something so complex to simulate a $2 part. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
Hi The main point is that NTP picks *one* source from among it’s batch of inputs and uses that. The ADEV of the output can be no better than the ADEV of the output. In the case of an ensemble of clocks combined with a better approach the ADEV of the output can be better than the ADEV of the best clock in the group. No this not an idea I came up with at all. It’s what’s been done by people like NIST and BIH for many decades. It also is the idea behind David Allan’s original Smart Clock stuff. I’d just like to try in in the basement … Two examples: NTP has three clocks that are half way around the world with flaky paths, two clocks that are in your local area on the internet, and one or two GPS clocks on the local LAN. It needs to figure out that one on the LAN is the best bet. Once it does so, it does it’s best to lock on to that clock and use it. We have a group of (say) 16 Rb’s that all are equally good at (say) 4x10^-13 at 1,000 seconds. None of them are really any better or worse than the rest. Our math needs to figure out how to take that group and get 1x10^-13 at 1,000 seconds. It can’t do that by just picking one out of the group and locking to that. (NTP goes a bit crazy when presented with many very good / equally good clocks …) David Allan has a number of papers on how you *can* indeed get results from a group that are better than any one member of the group. Bob On Nov 9, 2014, at 2:51 PM, Paul tic-...@bodosom.net wrote: On Sun, Nov 9, 2014 at 1:11 PM, Bob Camp kb...@n1k.org wrote: NTP's aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. By default NTP makes a paper clock from all acceptable sources (up to some maximum) to discipline a/the/its system clock. One source is special -- The mitigation rules select from among the survivors a *system peer* from which a set of system statistics can be inherited and passed along to dependent clients, if any -- but not for the discipline process. Unfortunately peer can be a bit confusing in this context so I prefer source. This is not to say that the NTP paper clock algorithm is particularly good or suitable for other purposes and the code may be simplified because the assumption is a relatively small (10) number of survivors. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi On Nov 9, 2014, at 3:31 PM, Chris Albertson albertson.ch...@gmail.com wrote: On Sun, Nov 9, 2014 at 10:11 AM, Bob Camp kb...@n1k.org wrote: That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. No, not pick one as best. NTP does not pick the best clock. NTP finds the subset of clocks that track each other. Clocks are allowed to enter and leave this set. NTP then computes a weighted average of the clocks in the set. Pretty much what you said you wanted. These two algorithms are used. Conceptually that are run one after the other but actually they run together in a loop forever 1) clock selection http://www.eecis.udel.edu/~mills/ntp/html/select.html 2) clock cluster http://www.eecis.udel.edu/~mills/ntp/html/cluster.html The clock that’s in the middle of the cluster is the one that is “best” and gets flagged as such. Bob You would not want to use this exact algorithm but something like it. I think the basic idea is simple: Reference clocks should tend to cluster around correct behavior. In other words our set of reference clocks is not biased. I don't think there is any way to detect bias unless you add more reference clocks. I would very much avoid an FPGA based CPU. You likely will need to add both flash and ram to the FPGA. Once you are done, you have a $30 gizmo that replaces a $1 chip. You also have a tool chain for your code that is far from “low barrier to entry”. It’s a great solution for something like video processing that needs TONS of bandwidth. We are very much on the other end of that stick. I agree. Unless the whole this is FPGA based and you have enough free gates. Otherwise it is not good to use something so complex to simulate a $2 part. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
In message CABbxVHtommjwSWq1i=oH-u1S=G6P=xu8e0yzekadg-vchgk...@mail.gmail.com , Chris Albertson writes: NTP does not pick the best clock. NTP finds the subset of clocks that track each other. NTP does indeed find the best clock from the subset of clocks which pass its sanity check, and then it uses only that one. There are several problems with that, and as we speak I'm developing a new algorithm which at least so far, gives much superior performance. You can read my musings about this here: http://phk.freebsd.dk/time/20141107.html My goal is to release the new NTP client before X-mas. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Sun, Nov 9, 2014 at 3:44 PM, Poul-Henning Kamp p...@phk.freebsd.dk wrote: NTP does indeed find the best clock from the subset of clocks which pass its sanity check, and then it uses only that one. Normally I wouldn't question your NTP assertions but I suspect a great many people believe NTPv4 Algorithms Specification or the 18-Jul-2012 document on Mitigation Rules. From http://www.eecis.udel.edu/~mills/ntp/html/prefer.html#miti 2. Combine Algorithm The clock combine algorithm uses the survivor list to produce a weighted average of both offset and jitter. Absent other considerations discussed later, the *combined offset* is used to discipline the system clock, while the *combined jitter* is augmented with other components to produce the system jitter statistic inherited by dependent clients, if any. The clock combine algorithm uses a weight factor for each survivor equal to the reciprocal of the root distance. This is normalized so that the sum of the reciprocals is equal to unity. This design favors the survivors at the smallest root distance and thus the smallest maximum error. Or more succintly (from a Mills ppt) Θ=combine(θj) where Theta is the (estimated) system clock offset and the theta_j are the survivor offsets. You're saying these documents affirming clock combining are wrong? Or have I gone terribly astray? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
On Sun, Nov 9, 2014 at 3:45 PM, Bob Camp kb...@n1k.org wrote: The main point is that NTP picks *one* source Not according to the documentation (since at least 2005). I'll admit to not having read the code for the primary algorithms. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
On Sun, Nov 9, 2014 at 12:45 PM, Bob Camp kb...@n1k.org wrote: Hi The main point is that NTP picks *one* source from among it’s batch of inputs and uses that. The ADEV of the output can be no better than the ADEV of the output. The statement above is not correct. NTP does not select just one clock. The statement below is correct and is what NTP actually does. If you look at the output from ntpstat you might think NTP selects one clock but internally it's not going that. The display is misleading. In the case of an ensemble of clocks combined with a better approach the ADEV of the output can be better than the ADEV of the best clock in the group. It's best to read this http://www.eecis.udel.edu/~mills/ntp/html/warp.html In simple terms it searches for consensus range of time where all the error bars of the various clock overlap and then eliminate clocks who d't agree with the consensus. Of those still in it figures out and kind of weighted average. I think you could do the same thing. First find the set of 10MHz oscillators who are in phase with each other to within some statistical limit and then you compute the weighted average phase Maybe start with Clock Select Algorithm. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
HI What is going on is that people are confusing the estimation process that is used by the selection process (which does look at a lot of stuff) and how that is described. They are then making the leap to the locking process, which is something else altogether. It’s easy to see that this is what’s going on by looking at the performance of an NTP implementation. If you give it multiple good clocks, the output is no better than one of the clocks in the group. In certain cases, with equally good / very good clocks, the selection process falls apart and the output actually degrades compared to the best clock in the group due to “best clock” selection changes. That’s not any sort of fault in NTP, you are giving it a situation that (by it’s rules) it really does not matter which one it picks. Any pick will result in an output that it considers to be “good enough”. Bob On Nov 9, 2014, at 4:54 PM, Chris Albertson albertson.ch...@gmail.com wrote: On Sun, Nov 9, 2014 at 12:45 PM, Bob Camp kb...@n1k.org wrote: Hi The main point is that NTP picks *one* source from among it’s batch of inputs and uses that. The ADEV of the output can be no better than the ADEV of the output. The statement above is not correct. NTP does not select just one clock. The statement below is correct and is what NTP actually does. If you look at the output from ntpstat you might think NTP selects one clock but internally it's not going that. The display is misleading. In the case of an ensemble of clocks combined with a better approach the ADEV of the output can be better than the ADEV of the best clock in the group. It's best to read this http://www.eecis.udel.edu/~mills/ntp/html/warp.html In simple terms it searches for consensus range of time where all the error bars of the various clock overlap and then eliminate clocks who d't agree with the consensus. Of those still in it figures out and kind of weighted average. I think you could do the same thing. First find the set of 10MHz oscillators who are in phase with each other to within some statistical limit and then you compute the weighted average phase Maybe start with Clock Select Algorithm. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
In message CAKyJ6kbZ5bzSoxB4vxRb3=9NJTiz70jzk9TOcmuizZ1Xv=b...@mail.gmail.com , Paul writes: You're saying these documents affirming clock combining are wrong? Or have I gone terribly astray? I'm saying that with NTP there is plenty of room between theory and practice :-) -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
NTP does not pick the best clock. NTP finds the subset of clocks that track each other. NTP does indeed find the best clock from the subset of clocks which pass its sanity check, and then it uses only that one. There are several problems with that, and as we speak I'm developing a new algorithm which at least so far, gives much superior performance. You can read my musings about this here: http://phk.freebsd.dk/time/20141107.html My goal is to release the new NTP client before X-mas. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 Hi, Looking forward to testing the new NTP implementations! Many years ago I was bitten by a setup where ntpd did not exclude a falseticker. A normal PC (P2-450MHz) running linux (2.4.20ish-kernel with ppskit-patches) was set up with 4 or 5 good internet ntp-servers as reference. Two GPS-receivers were attached locally and configured as refclocks. One Trimble with external event input (driver29) and a Rockwell Jupiter with 1pps (hardpps) (driver31). By mistake I disconnected the Jupiter antenna cable. After about day (day and night, 24h), the clock had drifted ca 180ms. Even though all clocks but the Jupiter was agreeing within 1ms of true time. The clock followed the 1PPS of the drifting Jupiter oscillator, never minding the other sources. This could be since the jupiter 1pps, was configured as hardpps using the kerneldriver, instead of letting ntpd using the pps in softpps(?)-mode. Nevertheless I was a bit surprised that the computer continued to serve time claiming to be a S1-server, even if both local refclock and a number of external S1-servers said time was false. I dont know if recent ntpd and operating system versions still have this problem. Poul-Henning, for the updated server with local refclock, have you elaborated over 1) supporting multiple 1PPS-sources on the same server? 2) supporting a stable frequency source? (say a ocxo or rb, that are divided down to 1pps, 10pps or 1pp(minute), but the pulse is only stable not aligned to a utc-second transition, and have a small frequency offset.) -- Björn ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
kb...@n1k.org said: What is going on is that people are confusing the estimation process that is used by the selection process (which does look at a lot of stuff) and how that is described. ... In this context, it's important to remember that there are 2 parameters associated with the goodness of clocks. The first is the error. The second is the error bars. For NTP, the error bars are often huge and often differ wildly between clocks. I don't know how that translates into getting the best out of a batch of Rbs. NTP has another trick worth adding to the collection. For things like PPS processing, it collects a batch of samples, then discards roughly 1/3 of them as outliers. That helps keep an occasional bad sample from biasing the result. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
On Sun, Nov 9, 2014 at 5:22 PM, Bob Camp kb...@n1k.org wrote: What is going on is that people are confusing the estimation process that is used by the selection process (which does look at a lot of stuff) and how that is described. They are then making the leap to the locking process, which is something else altogether. Have you read the referenced documentation? It quite clearly describes five major components: - Clock Filter Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/filter.html - Clock Select Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/select.html - Clock Cluster Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/cluster.html - Mitigation Rules and the prefer Keyword [viz. Clock Combining Algorithm] http://www.eecis.udel.edu/%7Emills/ntp/html/prefer.html - Clock Discipline Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/discipline.html Admittedly saying Mitigation Rules and the prefer Keyword rather than saying Combining Algorithm could lead one astray but there is a step between Cluster and Discipline. As noted earlier this bit: designate one of them as the *system peer* does not mean one clocks offset is used to discipline the client system clock. It's easy to see that this is what's going on by looking at the performance of an NTP implementation. I'm not sure what you mean here but root distance degradation dictates that no Stratum N+1 clock can be better than its upstream Stratum N servers. In certain cases, with equally good / very good clocks, the selection process falls apart and the output actually degrades compared to the best clock in the group due to best clock selection changes. Do you mean this? In practice, with fast LANs and modern computers, the correctness interval can be quite small, especially when the candidates are multiple reference clocks. In such cases the intersection interval might be empty, due to insignificant differences in the reference clock offsets. or clock-hopping? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
Hi Here’s what I’m saying: The NTP algorithm as it is written and as it is implemented results in an output clock that does *not* improve when a number of very good clocks are being used and the output is compared to the input. In that case and that case alone, the system simply does what one of the clocks is doing. That’s the case that matters when you are looking at a bunch of similar Rb’s. Bob On Nov 9, 2014, at 6:06 PM, Paul tic-...@bodosom.net wrote: On Sun, Nov 9, 2014 at 5:22 PM, Bob Camp kb...@n1k.org wrote: What is going on is that people are confusing the estimation process that is used by the selection process (which does look at a lot of stuff) and how that is described. They are then making the leap to the locking process, which is something else altogether. Have you read the referenced documentation? It quite clearly describes five major components: - Clock Filter Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/filter.html - Clock Select Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/select.html - Clock Cluster Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/cluster.html - Mitigation Rules and the prefer Keyword [viz. Clock Combining Algorithm] http://www.eecis.udel.edu/%7Emills/ntp/html/prefer.html - Clock Discipline Algorithm http://www.eecis.udel.edu/%7Emills/ntp/html/discipline.html Admittedly saying Mitigation Rules and the prefer Keyword rather than saying Combining Algorithm could lead one astray but there is a step between Cluster and Discipline. As noted earlier this bit: designate one of them as the *system peer* does not mean one clocks offset is used to discipline the client system clock. It's easy to see that this is what's going on by looking at the performance of an NTP implementation. I'm not sure what you mean here but root distance degradation dictates that no Stratum N+1 clock can be better than its upstream Stratum N servers. In certain cases, with equally good / very good clocks, the selection process falls apart and the output actually degrades compared to the best clock in the group due to best clock selection changes. Do you mean this? In practice, with fast LANs and modern computers, the correctness interval can be quite small, especially when the candidates are multiple reference clocks. In such cases the intersection interval might be empty, due to insignificant differences in the reference clock offsets. or clock-hopping? ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five -Ensemble
On Sun, Nov 9, 2014 at 6:18 PM, Bob Camp kb...@n1k.org wrote:
The NTP algorithm as it is written and as it is implemented results in an
output clock that does *not* improve when a number of very good clocks are
being used and the output is compared to the input. In that case and that
case alone, the system simply does what one of the clocks is doing. That's
the case that matters when you are looking at a bunch of similar Rb's.
I would naively compare input to output like this using ntpq (values in ms)
--
On a local S2 server, (estimated) system clock offset from UTC:
offset=-0.004554
Average offset from the system peer (which does happen to have the
smallest offset among all servers): offset=-0.019
The best view would likely come from turning on debugging. Viz the DPRINTF
below from ntp_proto in the 476 dev release:
/*
* Mitigation rules of the game. We have the pick of the
* litter in typesystem if any survivors are left. If
* there is a prefer peer, use its offset and jitter.
* Otherwise, use the combined offset and jitter of all kitters.
*/
if (typesystem != NULL) {
if (sys_prefer == NULL) {
typesystem-new_status = CTL_PST_SEL_SYSPEER;
clock_combine(peers, sys_survivors, speer);
} else {
typesystem = sys_prefer;
sys_clockhop = 0;
typesystem-new_status = CTL_PST_SEL_SYSPEER;
sys_offset = typesystem-offset;
sys_jitter = typesystem-jitter;
}
DPRINTF(1, (select: combine offset %.9f jitter %.9f\n,
sys_offset, sys_jitter));
and clock_combine while simple is not empty:
clock_combine(
peer_select * peers, /* survivor list */
int npeers, /* number of survivors */
int syspeer /* index of sys.peer */
)
{
int i;
double x, y, z, w;
y = z = w = 0;
for (i = 0; i npeers; i++) {
x = 1. / peers[i].synch;
y += x;
z += x * peers[i].peer-offset;
w += x * DIFF(peers[i].peer-offset,
peers[syspeer].peer-offset);
}
sys_offset = z / y;
sys_jitter = SQRT(w / y + SQUARE(peers[syspeer].seljit));
}
As I said before I'm certainly not arguing that the technique in
clock_combine() has any specific fitness or suitability for any purpose but
it certainly looks like it does what's documented modulo prefer.
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Re: [time-nuts] Divide by five -Ensemble
In message 4cdc0090-dd4b-4380-acc1-40a80d3bc...@n1k.org, Bob Camp writes: Hi Here’s what I’m saying: The NTP algorithm as it is written and as it is implemented results in an output clock that does *not* improve when a number of very good clocks are being used [...] The crucial word here is good clocks. A good clock in NTP is nearby and because it is nearby, the chances of several of them overlapping is usually not high enough for any clock combining to happen. The NTP algorithms were built for 10-100msec packet delays, not low microsecond packet delays. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi, On 11/09/2014 11:40 PM, Poul-Henning Kamp wrote: In message CAKyJ6kbZ5bzSoxB4vxRb3=9NJTiz70jzk9TOcmuizZ1Xv=b...@mail.gmail.com , Paul writes: You're saying these documents affirming clock combining are wrong? Or have I gone terribly astray? I'm saying that with NTP there is plenty of room between theory and practice :-) When you follow the breadcrum trace to the paper for control algorithm theory, the ADEV intercept point is traceable to a different concept with different noise-behavior, in which the method worked, where as re-applying it to the noises of packet networks may not be the best of methods. With all the theory available, it just doesn't necessarily apply to the reality. BTW, the ADEV intercept-point was done not by Dave Mills, but he refer to a paper by Judah Levine. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On 11/09/2014 05:18 PM, Chris Albertson wrote: On Sat, Nov 8, 2014 at 11:13 PM, Neil Schroeder gign...@gmail.com wrote: At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NTP does this but on a MUCH lower frequency and longer time scale. But I think NTP's general method could apply. NTP will accept any number of reference clocks. (Yes sone people run NTP using just one GPS receiver as a reference but best practice is to use five references.) NTP compares the set of ref. clocks with each other and first tries to find the subset of clocks that track each other, assuming the outliers are wrong. It continuously checks this and maintains a set of true tickers. From these it computes a consensus time using a weighted average of the true clocks. The weights are based on the jitter and other quality measuring statistics. Using this method reference clocks can be taken on and off line without need to re-start NTP. You could do the same thing with a set of local oscillators.Divide each down to 1PPS then every second you compare their phases. Keep statistics on drift and standard deviation relative to your consensus phase. You then discipline an OCXO (or several OCXOs) to output that consensus. Like NTP you might accept reference from any number of GPSes or Rb or other standards. You controller might pick the best OCXO in real time as the output. I figure the first generation where we are now, where we build a GPSDO using just one GPS and one OCXO and next generation would use multiples of each. There is not a lot of fancy electronics required. Just some phase comparators that can run once per second. The once pre second data rate is so slow that ANY $5 micro controller could keep up with even a dozen reference clocks. I'd likely us one of the ARM based Arduinos because they are easy enough to program that the barrier to entry is low enough others might be able to contribute. (Think about this if you want to make your design public. If the technology is exotic,no one but you will contribute to further development.) If you like those FPGA boards then you can usually synthesize a CPU and run the controller code on that. The NIST ensemble-processing is run on a pair of old 386 machines, or at least was when I did the tour in 2012. They operate redundantly and process for 40 s every 12 min, which is enough for the atomic clocks involved. They then steer the clock synthesis for the various time-scales they maintain. The NTP steering has a similar approach and origin. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On 11/09/2014 07:11 PM, Bob Camp wrote: Hi On Nov 9, 2014, at 11:18 AM, Chris Albertson albertson.ch...@gmail.com wrote: On Sat, Nov 8, 2014 at 11:13 PM, Neil Schroeder gign...@gmail.com wrote: At one point I was considering phase locking all of them together - but again that seemed less than straightforward. You can do it PLL back to back, but is there a way to have a loop that contains multiple clocks? I would think the telephone game would apply. NTP does this but on a MUCH lower frequency and longer time scale. But I think NTP's general method could apply. NTP will accept any number of reference clocks. (Yes sone people run NTP using just one GPS receiver as a reference but best practice is to use five references.) NTP compares the set of ref. clocks with each other and first tries to find the subset of clocks that track each other, assuming the outliers are wrong. It continuously checks this and maintains a set of true tickers. From these it computes a consensus time using a weighted average of the true clocks. The weights are based on the jitter and other quality measuring statistics. Using this method reference clocks can be taken on and off line without need to re-start NTP. That may (or may not) give you the best ADEV on the output. My guess is that the filtering algorithm will need to be a bit more complex. NTP’s aim is mainly to throw out bad clocks and pick one as best. We would more likely want to combine the outputs and use all of the good clocks we have. The idea is to improve on the ADEV of the *best* source you have available. The aim is to remove false-tickers and then build the best ensemble of the remaining sources and weigh them according to stability. It seems this goal is not very well met in practice, but the theory foundation is pretty good. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
The 74F161 is only rated at 90MHz over temp (TI) and 120MHz or 100MHz (unclear) at 25C and then only as typical without any max freq being indicated at all in the datasheet (Fairchild). So thats pretty much a no-go for any commercial product even at 'only' 100MHz.. Again for a one-off it may work, but not for a production unit that has to be guaranteed.. For a divide by 10 it would work if there is a 74AC74 type prescaler.. Bye, Said On Nov 7, 2014, at 21:19, Bob Bownes bow...@gmail.com wrote: I'm surprised no one has suggested 74F161 or other F series. Power hungry, but rated to in excess of 100mhz, some vendors as high as 120mhz, at ordinary temps. I will have to look, but I might have a tube or two of them in the basement. I know I have most of the other 74F. On Nov 7, 2014, at 23:20, Said Jackson via time-nuts time-nuts@febo.com wrote: Joe, This puppy can go to 166MHz over temp and has standard 100 mil pin spacing if you put it into a socket: ATF16V8C I have not used PALs since 1992 but I used to be extremely fond of the 16R8 and 22V10 types back then. This is a 16V8 that will do your divider in no time: http://www.digikey.com/product-detail/en/ATF16V8C-5JX/ATF16V8C-5JX-ND/1027054 Best of all its available and only ~$3.. Said Sent From iPhone On Nov 7, 2014, at 19:37, Joseph Gray jg...@zianet.com wrote: Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. Joe Gray W5JG On Fri, Nov 7, 2014 at 4:45 PM, Alex Pummer a...@pcscons.com wrote: check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/ 74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Sorry if I hijack the thread... On Sat, Nov 8, 2014 at 5:20 AM, Said Jackson via time-nuts time-nuts@febo.com wrote: Joe, This puppy can go to 166MHz over temp and has standard 100 mil pin spacing if you put it into a socket: ATF16V8C I have not used PALs since 1992 but I used to be extremely fond of the 16R8 and 22V10 types back then. This is a 16V8 that will do your divider in no time: http://www.digikey.com/product-detail/en/ATF16V8C-5JX/ATF16V8C-5JX-ND/1027054 can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
The 74F161 is only rated at 90MHz over temp (TI) and 120MHz or 100MHz (unclear) at 25C and then only as typical without any max freq being indicated at all in the datasheet (Fairchild). That's just the count frequency. If you want to divide by 5, you have to do something like use the terminal count output to load it with 15-5. Unfortunately, the PE (Parallel load Enable) is active low while the TC (Terminal Count) signal is active high so you have to add an inverter. Even without the inverter, the clock-out and setup times are way too long. Clock to out for TC is 10 ns. (typical from Fairchild data sheet) Setup for PE is 11 ns. (Min at 25C, 5V) The PAL suggestion was an interesting one. Does anybody have software and/or a programming setup that still works? Modern CPLDs or FPGAs would probably work. You can probably get one on a small board. Not quite a DIP, but might fit. Ahhh. A big DIP. :) http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,798Prod=CMOD -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Am 08.11.2014 um 09:46 schrieb Said Jackson via time-nuts: The x163 seems to be in better supply than the '161. For example: http://www.nxp.com/documents/data_sheet/74LVC163.pdf At 3.0 - 3.6V 150 MHz guaranteed, 200 MHz typ. I have done a fanout board for the Xilinx Coolrunner XC2C64 to 100 mil square pads. The small chip in the Background is the core voltage regulator, The plug fits to the Xilinx USB configuration cable. Enough to create 1pps from 100 MHz. https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink The other small boards are 100 MHz Crystek CVHD-950 locked to 10 MHz using LVC163 Doubler 100 MHz --- 200 MHz 13dBm in - 13 dBm out using 2*BF862 push/push grounded gate Doubler 200 MHz - 400 MHz 13 dBm in 13 dBm out, HSMS-282F, SAW Filter on 400 MHz, ERA-4 amplifier All are week-enders, Layout printed on Laser printer to foil, presensitized FR-4 0.5mm from Bungard, home etched. The bottom side ist ground only. I can use these snippets in my Altium Designer to combine them to larger projects; the modules keep their layout and need only to be handled as a block. I have collected quite a block library over the years. :-) regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Joe wrote: Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. If by breadboards you mean plug-in breadboards, AC logic often does not play well with them. It wants a real ground plane and very short leads. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
I would very, very, very much enjoy perusing that library, if you'd be as kind ;-) Particularly just a few basics for the Xilinx. I also have a few CVHD-950s In need of some parenting! On Saturday, November 8, 2014, Gerhard Hoffmann dk...@arcor.de wrote: Am 08.11.2014 um 09:46 schrieb Said Jackson via time-nuts: The x163 seems to be in better supply than the '161. For example: http://www.nxp.com/documents/data_sheet/74LVC163.pdf At 3.0 - 3.6V 150 MHz guaranteed, 200 MHz typ. I have done a fanout board for the Xilinx Coolrunner XC2C64 to 100 mil square pads. The small chip in the Background is the core voltage regulator, The plug fits to the Xilinx USB configuration cable. Enough to create 1pps from 100 MHz. https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETY myPJy0liipFm0?feat=directlink The other small boards are 100 MHz Crystek CVHD-950 locked to 10 MHz using LVC163 Doubler 100 MHz --- 200 MHz 13dBm in - 13 dBm out using 2*BF862 push/push grounded gate Doubler 200 MHz - 400 MHz 13 dBm in 13 dBm out, HSMS-282F, SAW Filter on 400 MHz, ERA-4 amplifier All are week-enders, Layout printed on Laser printer to foil, presensitized FR-4 0.5mm from Bungard, home etched. The bottom side ist ground only. I can use these snippets in my Altium Designer to combine them to larger projects; the modules keep their layout and need only to be handled as a block. I have collected quite a block library over the years. :-) regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hal, That means in a divide by 5 you cant even get close to 125MHz even if the 74lvc163 is rated at 200MHz count frequency. Very good point. I used to use ABEL with DataIO programmers back in the day, Abel is now licensed by Lattice and I think they still support the old 16V8 and 22V10 types. It is available as freeware from lattice and generates standard Jedec files. No idea what programmer to use nowadays though, nowadays I use Lattice PLDs with JTAG programmer. Those PLDs can count at 200MHz easily (Lattice 4032 for example). Bye, Said Sent From iPhone On Nov 8, 2014, at 1:34, Hal Murray hmur...@megapathdsl.net wrote: The 74F161 is only rated at 90MHz over temp (TI) and 120MHz or 100MHz (unclear) at 25C and then only as typical without any max freq being indicated at all in the datasheet (Fairchild). That's just the count frequency. If you want to divide by 5, you have to do something like use the terminal count output to load it with 15-5. Unfortunately, the PE (Parallel load Enable) is active low while the TC (Terminal Count) signal is active high so you have to add an inverter. Even without the inverter, the clock-out and setup times are way too long. Clock to out for TC is 10 ns. (typical from Fairchild data sheet) Setup for PE is 11 ns. (Min at 25C, 5V) The PAL suggestion was an interesting one. Does anybody have software and/or a programming setup that still works? Modern CPLDs or FPGAs would probably work. You can probably get one on a small board. Not quite a DIP, but might fit. Ahhh. A big DIP. :) http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,798Prod=CMOD -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Francesco, If you can handle tqfp packages then the Lattice parts are a worthy PAL replacement. The LC4032V clocks at up to 400MHz with 2.5ns delay, and that part at slower speed costs down to only $1.43 at mouser. Its a simple architecture with deterministic timing, kind of like a Super-PAL at half the price. I only miss an internal PLL to generate the = 400MHz clock from a slow external clock input. You can program it in my beloved ABEL instead if the dreaded CUPL.. Lattice sells a cheap USB programmer for these. Bye, Said Sent From iPhone On Nov 8, 2014, at 0:58, Francesco Messineo francesco.messi...@gmail.com wrote: Sorry if I hijack the thread... On Sat, Nov 8, 2014 at 5:20 AM, Said Jackson via time-nuts time-nuts@febo.com wrote: Joe, This puppy can go to 166MHz over temp and has standard 100 mil pin spacing if you put it into a socket: ATF16V8C I have not used PALs since 1992 but I used to be extremely fond of the 16R8 and 22V10 types back then. This is a 16V8 that will do your divider in no time: http://www.digikey.com/product-detail/en/ATF16V8C-5JX/ATF16V8C-5JX-ND/1027054 can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Potato Semi's world heardquaters http://goo.gl/P7vqMT -pete On Sat, Nov 8, 2014 at 9:36 AM, paul swed paulsw...@gmail.com wrote: Heavens never heard of potato semi. Pretty interesting. Though if you use the soic to dip boards won't that mess up the top end signalling? It gets tricky at high speeds Regards Paul WB8TSL On Fri, Nov 7, 2014 at 5:43 PM, cdel...@juno.com wrote: You could use a SOIC to DIP adaptor board with a couple logic and FF elements in the Potato Chip Family. See: http://www.potatosemi.com/ Cheers, Corby ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Am 08.11.2014 um 18:36 schrieb paul swed: Heavens never heard of potato semi. Pretty interesting. If it cannot drive at least 100 Ohm without running out of speed then it's not for me. :-) Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Am 08.11.2014 um 18:21 schrieb Robert Darby: As a dumb question does $15 for this item : XC9572XL CPLD development board v1b http://www.seeedstudio.com/depot/XC9572XL-CPLD-development-board-v1b-p-799.html make any sense? It's 5V tolerant and has 5ns pin to pin logic. JTAG or bus pirate programming. Probably yes, but I have never used the XC95 family. The Coolrunners use very little power, can do 250 MHz and store their own configuration. Wierd enough, their Flipflops can switch on both the rising AND the falling edge. I have revitalized my HiLO All-11 programmer from the times when PALs/GALS and Eproms were great. Its software now runs in a virtual XP machine under Linux Mint / VMware with an USB to serial cable made by HAMA. Gerhard BTW, this is the 10/100MHz -- 1pps-generator in the 2C64: (I have removed some debug outputs, hopefully I did not mess it up) -- -- Company: Hoffmann RF DSP -- Create Date:09:09:37 08/08/2012 -- Module Name:pps1_generator - Behavioral -- Target Devices: X2c64A-5VQ44 -- Additional Comments: Free firmware under BSD license -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity pps1_generator is Port( clk : in STD_LOGIC; RunAt100MHz : in STD_LOGIC; pps1_out: out STD_LOGIC ); end pps1_generator; architecture Behavioral of pps1_generator is signal tctr : integer range 0 to ; signal pw_ctr : integer range 0 to 19; signal cycle_done : boolean; signal pw_done: boolean; function bool2sl(b : boolean) return std_logic is begin if b then return '1'; else return '0'; end if; end function bool2sl; begin u_div : process(clk) is begin if rising_edge(clk) then cycle_done = (tctr = 0); -- pipeline the comparator if cycle_done then if RunAt100MHz = '1' then tctr = 1 - 2; -- divide by 100 Meg else tctr = 1000 - 2; -- divide by 10 Meg end if; else tctr = tctr - 1; end if; end if; -- rising_edge() end process u_div; -- produce the standard 20 usec pulsewidth u_pulsewidth : process(clk) is begin if rising_edge(clk) then if cycle_done then if RunAt100MHz = '1' then pw_ctr = 1999; else pw_ctr = 199; end if; elsif pw_ctr /= 0 then pw_ctr = pw_ctr - 1; end if; pps1_out = bool2sl(pw_ctr /= 0); end if; -- rising_edge() end process u_pulsewidth; end Behavioral; ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
You can program it in my beloved ABEL instead if the dreaded CUPL.. Lattice sells a cheap USB programmer for these. Are they usable in a non-Windows environment? -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
When I first discoverd the parts, that was the brick wall. They pretty much can't drive anything. I was going to look at some line drivers I had for a fast 4 Gbs setup but discovered I could not find them. -pete On Sat, Nov 8, 2014 at 9:50 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 08.11.2014 um 18:36 schrieb paul swed: Heavens never heard of potato semi. Pretty interesting. If it cannot drive at least 100 Ohm without running out of speed then it's not for me. :-) Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote: can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF I'd suggest ALTERA parts , but only because they are the cheapest boards on *bay , XILINX boards are 2 x the Altera price on *Bay. An EPM240 CPLD Board $9 (240 cells let you do quite a lot) http://tinyurl.com/qcusb69 There's also an EPM-570 Board , but the price is almost the same as the below FPGA , and then the FPGA is the thing to get. A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value for the money http://tinyurl.com/pd326ct An ALTERA Programmer $6 http://tinyurl.com/po2qhq2 The only caveat is that they are NOT 5v tolerant , they can do 3v3 or less. ALTERA has the free QuartusII WEB Edition , and it works fine under both Windows Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based under the hood) I am a VHDL beginner , and completed this (free) course s few month back Course http://tinyurl.com/per8lm5 Forum http://tinyurl.com/pw3b9bv I have just did a divide by 5 with the EP2C5T144 FPGA board , using one of the PLL's. I did use so few resources, that it reported 0% of the 4608 Cells utilized, and 1 of 2 PLL's used. *** SNIP * Fitter Status Successful - Sat Nov 8 23:11:59 2014 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name div5pll Top-level Entity Name div5pll Family Cyclone II Device EP2C5T144C8 Timing Models Final Total logic elements0 / 4,608 ( 0 % ) Total combinational functions 0 / 4,608 ( 0 % ) Dedicated logic registers 0 / 4,608 ( 0 % ) Total registers 0 Total pins 6 / 89 ( 7 % ) Total virtual pins 0 Total memory bits 0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements 0 / 26 ( 0 % ) Total PLLs 1 / 2 ( 50 % ) *** SNIP * Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress boards are ALTERA Boards , so i have both tools installed on my linux machine. If you don't feel like learning VHDL or Verilog , you can do the layout in Schematic. ALTERA QuartusII does have an extensive 74xx lib built in the schematic engine. See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration. http://tinyurl.com/ntdkcst Be sure to get these versions of the tools , as both have upgraded their tools , and the new tools doesn't support the older (cheaper chips). Altera QuartusII : Version 13.0sp1 (13.1+ doesn't suport the old CPLD's) Xilinx ISE: Version 14.7(Vivado doesn't support the old stuff) I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD , and MUCH more in the FPGA. The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in the FPGA. As seen below. *** SNIP *** Flow Status Successful - Sat Nov 8 23:56:46 2014 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name lesson10d Top-level Entity Name lesson10d Family Cyclone II Device EP2C5T144C8 Timing Models Final Total logic elements39 / 4,608 ( 1 % ) Total combinational functions 39 / 4,608 ( 1 % ) Dedicated logic registers 31 / 4,608 ( 1 % ) Total registers 31 Total pins 3 / 89 ( 3 % ) Total virtual pins 0 Total memory bits 0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements 0 / 26 ( 0 % ) Total PLLs 0 / 2 ( 0 % ) *** SNIP *** CFO - Denmark -- E-mail:xne...@luna.dyndns.dk ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy any hardware. All the design tools are schematic entry capable and free on the web. There’s not a big speed bump when you start using them (like say needing to go learn VHDL…). Once you get using them, the CPLD's are quite handy for a wide range of projects, way beyond a simple divide by 5. Their bigger cousins (the FPGA’s) aren’t that much more (under $35) and they will do a LOT, especially in the newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob On Nov 8, 2014, at 5:58 PM, cfo xne...@luna.dyndns.dk wrote: On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote: can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF I'd suggest ALTERA parts , but only because they are the cheapest boards on *bay , XILINX boards are 2 x the Altera price on *Bay. An EPM240 CPLD Board $9 (240 cells let you do quite a lot) http://tinyurl.com/qcusb69 There's also an EPM-570 Board , but the price is almost the same as the below FPGA , and then the FPGA is the thing to get. A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value for the money http://tinyurl.com/pd326ct An ALTERA Programmer $6 http://tinyurl.com/po2qhq2 The only caveat is that they are NOT 5v tolerant , they can do 3v3 or less. ALTERA has the free QuartusII WEB Edition , and it works fine under both Windows Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based under the hood) I am a VHDL beginner , and completed this (free) course s few month back Course http://tinyurl.com/per8lm5 Forum http://tinyurl.com/pw3b9bv I have just did a divide by 5 with the EP2C5T144 FPGA board , using one of the PLL's. I did use so few resources, that it reported 0% of the 4608 Cells utilized, and 1 of 2 PLL's used. *** SNIP * Fitter Status Successful - Sat Nov 8 23:11:59 2014 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name div5pll Top-level Entity Name div5pll FamilyCyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements 0 / 4,608 ( 0 % ) Total combinational functions 0 / 4,608 ( 0 % ) Dedicated logic registers 0 / 4,608 ( 0 % ) Total registers 0 Total pins6 / 89 ( 7 % ) Total virtual pins0 Total memory bits 0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs1 / 2 ( 50 % ) *** SNIP * Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress boards are ALTERA Boards , so i have both tools installed on my linux machine. If you don't feel like learning VHDL or Verilog , you can do the layout in Schematic. ALTERA QuartusII does have an extensive 74xx lib built in the schematic engine. See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration. http://tinyurl.com/ntdkcst Be sure to get these versions of the tools , as both have upgraded their tools , and the new tools doesn't support the older (cheaper chips). Altera QuartusII : Version 13.0sp1 (13.1+ doesn't suport the old CPLD's) Xilinx ISE : Version 14.7(Vivado doesn't support the old stuff) I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD , and MUCH more in the FPGA. The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in the FPGA. As seen below. *** SNIP *** Flow Status Successful - Sat Nov 8 23:56:46 2014 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name lesson10d Top-level Entity Name lesson10d FamilyCyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements 39 / 4,608 ( 1 % ) Total combinational functions 39 / 4,608 ( 1 % ) Dedicated logic registers 31 / 4,608 ( 1 % ) Total registers 31 Total pins3 / 89 ( 3 % ) Total virtual pins0 Total memory bits 0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs0 / 2 ( 0 % ) *** SNIP *** CFO - Denmark -- E-mail:xne...@luna.dyndns.dk ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
Re: [time-nuts] Divide by five
It seems that Mr. Richard of Potato Semiconductor has issued a patent: http://www.google.com/patents/US7102380 On Sat, Nov 8, 2014 at 6:48 PM, Pete Lancashire p...@petelancashire.com wrote: Potato Semi's world heardquaters http://goo.gl/P7vqMT -pete On Sat, Nov 8, 2014 at 9:36 AM, paul swed paulsw...@gmail.com wrote: Heavens never heard of potato semi. Pretty interesting. Though if you use the soic to dip boards won't that mess up the top end signalling? It gets tricky at high speeds Regards Paul WB8TSL On Fri, Nov 7, 2014 at 5:43 PM, cdel...@juno.com wrote: You could use a SOIC to DIP adaptor board with a couple logic and FF elements in the Potato Chip Family. See: http://www.potatosemi.com/ Cheers, Corby ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Sat, 08 Nov 2014 18:17:09 -0500, Bob Camp wrote: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. SNIP The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob Bob Hmmm ... I didn't know the CycloneII had a Min of 20Mhz. Is that in some doc you can point me to ? Well it seems to be 11Mhz for the CycloneII ... (Bummer from a T-Nut perspective) http://tinyurl.com/opvng2y I just tried to do a 10 = 100Mhz PLL in the EP2C5T144C8 , using the MegaWizzard , and there were no errors or warnings. Strange if the Min input is 11Mhz Anyways , thanx for enlighten me Bob. CFO ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi On Nov 8, 2014, at 7:14 PM, cfo xne...@luna.dyndns.dk wrote: On Sat, 08 Nov 2014 18:17:09 -0500, Bob Camp wrote: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. SNIP The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob Bob Hmmm ... I didn't know the CycloneII had a Min of 20Mhz. Is that in some doc you can point me to ? Well it seems to be 11Mhz for the CycloneII ... (Bummer from a T-Nut perspective) http://tinyurl.com/opvng2y I just tried to do a 10 = 100Mhz PLL in the EP2C5T144C8 , using the MegaWizzard , and there were no errors or warnings. Strange if the Min input is 11Mhz Back when they were new, I think the limit was higher than that. I suspect the simple answer is “does not work reliably at 10 MHz over all voltages and temperatures”. I haven’t done a Cyclone II design in many years. It’s been almost that long since I looked at a Cy II spec sheet. Bob Anyways , thanx for enlighten me Bob. CFO ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
We do most our projects with Altera G/A. The biggest benefit is that if something does not work on first pass changing the G/A logic is much faster, less costly than a new board layout. Bert Kehren In a message dated 11/8/2014 6:17:29 P.M. Eastern Standard Time, kb...@n1k.org writes: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy any hardware. All the design tools are schematic entry capable and free on the web. There’s not a big speed bump when you start using them (like say needing to go learn VHDL…). Once you get using them, the CPLD's are quite handy for a wide range of projects, way beyond a simple divide by 5. Their bigger cousins (the FPGA’s) aren’t that much more (under $35) and they will do a LOT, especially in the newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob On Nov 8, 2014, at 5:58 PM, cfo xne...@luna.dyndns.dk wrote: On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote: can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF I'd suggest ALTERA parts , but only because they are the cheapest boards on *bay , XILINX boards are 2 x the Altera price on *Bay. An EPM240 CPLD Board $9 (240 cells let you do quite a lot) http://tinyurl.com/qcusb69 There's also an EPM-570 Board , but the price is almost the same as the below FPGA , and then the FPGA is the thing to get. A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value for the money http://tinyurl.com/pd326ct An ALTERA Programmer $6 http://tinyurl.com/po2qhq2 The only caveat is that they are NOT 5v tolerant , they can do 3v3 or less. ALTERA has the free QuartusII WEB Edition , and it works fine under both Windows Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based under the hood) I am a VHDL beginner , and completed this (free) course s few month back Course http://tinyurl.com/per8lm5 Forum http://tinyurl.com/pw3b9bv I have just did a divide by 5 with the EP2C5T144 FPGA board , using one of the PLL's. I did use so few resources, that it reported 0% of the 4608 Cells utilized, and 1 of 2 PLL's used. *** SNIP * Fitter StatusSuccessful - Sat Nov 8 23:11:59 2014 Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Namediv5pll Top-level Entity Namediv5pll FamilyCyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements0 / 4,608 ( 0 % ) Total combinational functions0 / 4,608 ( 0 % ) Dedicated logic registers0 / 4,608 ( 0 % ) Total registers 0 Total pins6 / 89 ( 7 % ) Total virtual pins0 Total memory bits0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs1 / 2 ( 50 % ) *** SNIP * Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress boards are ALTERA Boards , so i have both tools installed on my linux machine. If you don't feel like learning VHDL or Verilog , you can do the layout in Schematic. ALTERA QuartusII does have an extensive 74xx lib built in the schematic engine. See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration. http://tinyurl.com/ntdkcst Be sure to get these versions of the tools , as both have upgraded their tools , and the new tools doesn't support the older (cheaper chips). Altera QuartusII : Version 13.0sp1 (13.1+ doesn't suport the old CPLD's) Xilinx ISE : Version 14.7 (Vivado doesn't support the old stuff) I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD , and MUCH more in the FPGA. The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in the FPGA. As seen below. *** SNIP *** Flow StatusSuccessful - Sat Nov 8 23:56:46 2014 Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Namelesson10d Top-level Entity Namelesson10d Family Cyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements39 / 4,608 ( 1 % ) Total combinational functions39 / 4,608 ( 1 % ) Dedicated logic registers31 / 4,608 ( 1 % ) Total registers31 Total pins3 / 89 ( 3 % ) Total virtual pins0 Total memory bits0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs0 / 2 ( 0 % ) *** SNIP *** CFO - Denmark -- E-mail:xne...@luna.dyndns.dk
Re: [time-nuts] Divide by five
Hi One of the more interesting uses for something like a Cyclone V would be a front end board to drive a KS-24361 from an ensemble of sources. That’s what David Allan’s original idea was when he started the whole software empire that turned into the Z3801 and all the rest. Bob On Nov 8, 2014, at 8:36 PM, Bert Kehren via time-nuts time-nuts@febo.com wrote: We do most our projects with Altera G/A. The biggest benefit is that if something does not work on first pass changing the G/A logic is much faster, less costly than a new board layout. Bert Kehren In a message dated 11/8/2014 6:17:29 P.M. Eastern Standard Time, kb...@n1k.org writes: Hi I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy any hardware. All the design tools are schematic entry capable and free on the web. There’s not a big speed bump when you start using them (like say needing to go learn VHDL…). Once you get using them, the CPLD's are quite handy for a wide range of projects, way beyond a simple divide by 5. Their bigger cousins (the FPGA’s) aren’t that much more (under $35) and they will do a LOT, especially in the newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible. Bob On Nov 8, 2014, at 5:58 PM, cfo xne...@luna.dyndns.dk wrote: On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote: can anyone suggest a (cheap if possible) programmer and software for these modern PLD? Thanks and best regards Frank IZ8DWF I'd suggest ALTERA parts , but only because they are the cheapest boards on *bay , XILINX boards are 2 x the Altera price on *Bay. An EPM240 CPLD Board $9 (240 cells let you do quite a lot) http://tinyurl.com/qcusb69 There's also an EPM-570 Board , but the price is almost the same as the below FPGA , and then the FPGA is the thing to get. A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value for the money http://tinyurl.com/pd326ct An ALTERA Programmer $6 http://tinyurl.com/po2qhq2 The only caveat is that they are NOT 5v tolerant , they can do 3v3 or less. ALTERA has the free QuartusII WEB Edition , and it works fine under both Windows Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based under the hood) I am a VHDL beginner , and completed this (free) course s few month back Course http://tinyurl.com/per8lm5 Forum http://tinyurl.com/pw3b9bv I have just did a divide by 5 with the EP2C5T144 FPGA board , using one of the PLL's. I did use so few resources, that it reported 0% of the 4608 Cells utilized, and 1 of 2 PLL's used. *** SNIP * Fitter StatusSuccessful - Sat Nov 8 23:11:59 2014 Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Namediv5pll Top-level Entity Namediv5pll FamilyCyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements0 / 4,608 ( 0 % ) Total combinational functions0 / 4,608 ( 0 % ) Dedicated logic registers0 / 4,608 ( 0 % ) Total registers 0 Total pins6 / 89 ( 7 % ) Total virtual pins0 Total memory bits0 / 119,808 ( 0 % ) Embedded Multiplier 9-bit elements0 / 26 ( 0 % ) Total PLLs1 / 2 ( 50 % ) *** SNIP * Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress boards are ALTERA Boards , so i have both tools installed on my linux machine. If you don't feel like learning VHDL or Verilog , you can do the layout in Schematic. ALTERA QuartusII does have an extensive 74xx lib built in the schematic engine. See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration. http://tinyurl.com/ntdkcst Be sure to get these versions of the tools , as both have upgraded their tools , and the new tools doesn't support the older (cheaper chips). Altera QuartusII : Version 13.0sp1 (13.1+ doesn't suport the old CPLD's) Xilinx ISE : Version 14.7 (Vivado doesn't support the old stuff) I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD , and MUCH more in the FPGA. The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in the FPGA. As seen below. *** SNIP *** Flow StatusSuccessful - Sat Nov 8 23:56:46 2014 Quartus II 64-Bit Version13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Namelesson10d Top-level Entity Namelesson10d Family Cyclone II DeviceEP2C5T144C8 Timing Models Final Total logic elements39 / 4,608 ( 1 % ) Total
[time-nuts] Divide by five
I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Ring counter, made out of Potato Semiconductor PO74G74A's? Except those don't come in DIP as far as I know. But consider that the spacing on a SOIC is just the same as spacing on a TO-92. I know that ECL dividers/prescalers e.g. 11C90 used to come in DIP but I only see SMD ECL now. e.g. MC10EP139. Tim N3QE On Fri, Nov 7, 2014 at 4:12 PM, Joseph Gray jg...@zianet.com wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On Fri, Nov 7, 2014 at 1:12 PM, Joseph Gray jg...@zianet.com wrote: Can anyone recommend a chip that is fast enough and comes in DIP? Some SMDs are easy to solder by hand. Others such as ball grid array is impossible. An easy SMD prototype board can be made by sawing the edge connectors off some old RAM memory or PCI boards and gluing down a parallel row of them. Dead bug style works well with SMD also. We are going to have to get used to working with these. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Divide by five
You could use a SOIC to DIP adaptor board with a couple logic and FF elements in the Potato Chip Family. See: http://www.potatosemi.com/ Cheers, Corby ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi: I have some info on working with SMD parts at: http://www.prc68.com/I/SMT.shtml The key thing is to get parts with a reasonable pitch, 0.1 is a standard DIP pitch. 0.050 (1.27 or 1.25 mm) is half DIP and is easy to do with a fine tip soldering iron and small dia. solder that I normally use for other stuff. The use of a stereo zoom microscope or a magnifying glass/light or 3.25 diopter reading glasses is a big help. On eBay there are many surface mount surfboard that allow you to mount a SMT and then treat it like a SIP so you can use prototyping boards. Another option is to make a ring counter out of transistors. http://www.prc68.com/I/comp.shtml#Lamp The beauty is that each transistor is toggling at 2/N of the clock frequency. Mail_Attachment -- Have Fun, Brooke Clarke http://www.PRC68.com http://www.end2partygovernment.com/2012Issues.html http://www.prc68.com/I/DietNutrition.html Chris Albertson wrote: On Fri, Nov 7, 2014 at 1:12 PM, Joseph Gray jg...@zianet.com wrote: Can anyone recommend a chip that is fast enough and comes in DIP? Some SMDs are easy to solder by hand. Others such as ball grid array is impossible. An easy SMD prototype board can be made by sawing the edge connectors off some old RAM memory or PCI boards and gluing down a parallel row of them. Dead bug style works well with SMD also. We are going to have to get used to working with these. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi The days of DIP parts are drawing to a close. Most of the DIP’s are now surplus and stocked by odd places here and here. The risk with many places (even major names) is that the part you get isn’t what you think it is. It may be a re-labeled something else pulled off a board in China with a blowtorch. I think that in a lot of ways, you are better off with something in one of the larger SMD packages than a surplus / questionable DIP. The other half of the equation at higher frequencies is good layout. That sort of forces you in the direction of a pc board. Custom boards are now so crazy cheap that doing them for a one off makes sense. Bob On Nov 7, 2014, at 4:12 PM, Joseph Gray jg...@zianet.com wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
On the topic of SMD/SMT surfboards - has anyone seen one that has pad areas designed for crystals or oscillators?Most of the pads are for resistors, and that might be fine for a crystal in the strictest sense - just the crystal no resonator - but I have 4, 6, and 8 pad guys here that just aren't spaced right for that. If nobody has, will break out Eagle and make an attempt to create one. NS On Fri, Nov 7, 2014 at 3:32 PM, Brooke Clarke bro...@pacific.net wrote: Hi: I have some info on working with SMD parts at: http://www.prc68.com/I/SMT.shtml The key thing is to get parts with a reasonable pitch, 0.1 is a standard DIP pitch. 0.050 (1.27 or 1.25 mm) is half DIP and is easy to do with a fine tip soldering iron and small dia. solder that I normally use for other stuff. The use of a stereo zoom microscope or a magnifying glass/light or 3.25 diopter reading glasses is a big help. On eBay there are many surface mount surfboard that allow you to mount a SMT and then treat it like a SIP so you can use prototyping boards. Another option is to make a ring counter out of transistors. http://www.prc68.com/I/comp.shtml#Lamp The beauty is that each transistor is toggling at 2/N of the clock frequency. Mail_Attachment -- Have Fun, Brooke Clarke http://www.PRC68.com http://www.end2partygovernment.com/2012Issues.html http://www.prc68.com/I/DietNutrition.html Chris Albertson wrote: On Fri, Nov 7, 2014 at 1:12 PM, Joseph Gray jg...@zianet.com wrote: Can anyone recommend a chip that is fast enough and comes in DIP? Some SMDs are easy to solder by hand. Others such as ball grid array is impossible. An easy SMD prototype board can be made by sawing the edge connectors off some old RAM memory or PCI boards and gluing down a parallel row of them. Dead bug style works well with SMD also. We are going to have to get used to working with these. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
As far as I'm concerned there are no more DIP parts. However, let's not give up yet. Although I am not a high volume manufacturer, I found a nice way around it. First, forget about prototyping by hand. That ship has left. So, I use OrCAD/Cadence (CIS/PCB Editor) from the start in order to create a proper project. This includes circuit and board. OrCAD is fantastic in that you can have revisions, simulation, etc, etc... Then I use http://pcb123.com/ to make myself a protoboard (or 4). Pretty cheap for that volume. ~$50 Then to mount the components, I use http://www.pnconline.com/ I can usually make 2-4 protoboards for ~$200-300 with all the components. Depends on count. OK, so not exactly old school but I have a very nice prototype. OrCad also does amazing simulations on diff pairs, and other cool things. Ultimately, by thinking of these things ahead of time and doing the design right I end up saving considerable time. On the prototypes, there is usually a few extra SMD pots but that's ok. Let's face it. DIPs are done. This is the way now and we might as well get used to it. Anyone here who needs help with OrCad, just ask. I am sure there are a few experts here as well. Thanks for listening, -George, N2FGX On 11/07/2014 07:37 PM, Bob Camp wrote: Hi The days of DIP parts are drawing to a close. Most of the DIP’s are now surplus and stocked by odd places here and here. The risk with many places (even major names) is that the part you get isn’t what you think it is. It may be a re-labeled something else pulled off a board in China with a blowtorch. I think that in a lot of ways, you are better off with something in one of the larger SMD packages than a surplus / questionable DIP. The other half of the equation at higher frequencies is good layout. That sort of forces you in the direction of a pc board. Custom boards are now so crazy cheap that doing them for a one off makes sense. Bob On Nov 7, 2014, at 4:12 PM, Joseph Gray jg...@zianet.com wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
I do a lot of work with SMD parts and would be happy to solder up and SOIC-16 version of the 74AC161, such as this one: http://www.digikey.com/product-search/en?pv633=35k=74AC161mnonly=0newproducts=0ColumnSort=0page=1stock=1quantity=0ptm=0fid=0pageSize=25 onto a dip break out board, such as this one: https://www.adafruit.com/products/1207 Or, if you need something more complex, I do a lot of PCB design using OSH Park https://www.oshpark.com and I'd be happy to whip up a simple PCB for you. It takes a few weeks to turn around a board, but it's a very economical service ($5 a square inch for three copies.) Wayne On Fri, Nov 7, 2014 at 1:12 PM, Joseph Gray jg...@zianet.com wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Hi If it’s a synthesizer and you can play with divide’s a bit - there are a number of divide by 10 preschoolers out there. They are not in DIP’s, but the packages are not that crazy. They also are rated to much higher frequencies. You would not have any issues with “almost works” at 125 MHz. Bob On Nov 7, 2014, at 4:12 PM, Joseph Gray jg...@zianet.com wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. Joe Gray W5JG On Fri, Nov 7, 2014 at 4:45 PM, Alex Pummer a...@pcscons.com wrote: check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/ 74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
That part is limited to 95MHz over temp. Not suitable for commercial designs, but probably works just fine for a one-off.. Sent From iPhone On Nov 7, 2014, at 19:37, Joseph Gray jg...@zianet.com wrote: Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. Joe Gray W5JG On Fri, Nov 7, 2014 at 4:45 PM, Alex Pummer a...@pcscons.com wrote: check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/ 74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
Joe, This puppy can go to 166MHz over temp and has standard 100 mil pin spacing if you put it into a socket: ATF16V8C I have not used PALs since 1992 but I used to be extremely fond of the 16R8 and 22V10 types back then. This is a 16V8 that will do your divider in no time: http://www.digikey.com/product-detail/en/ATF16V8C-5JX/ATF16V8C-5JX-ND/1027054 Best of all its available and only ~$3.. Said Sent From iPhone On Nov 7, 2014, at 19:37, Joseph Gray jg...@zianet.com wrote: Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. Joe Gray W5JG On Fri, Nov 7, 2014 at 4:45 PM, Alex Pummer a...@pcscons.com wrote: check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/ 74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divide by five
I'm surprised no one has suggested 74F161 or other F series. Power hungry, but rated to in excess of 100mhz, some vendors as high as 120mhz, at ordinary temps. I will have to look, but I might have a tube or two of them in the basement. I know I have most of the other 74F. On Nov 7, 2014, at 23:20, Said Jackson via time-nuts time-nuts@febo.com wrote: Joe, This puppy can go to 166MHz over temp and has standard 100 mil pin spacing if you put it into a socket: ATF16V8C I have not used PALs since 1992 but I used to be extremely fond of the 16R8 and 22V10 types back then. This is a 16V8 that will do your divider in no time: http://www.digikey.com/product-detail/en/ATF16V8C-5JX/ATF16V8C-5JX-ND/1027054 Best of all its available and only ~$3.. Said Sent From iPhone On Nov 7, 2014, at 19:37, Joseph Gray jg...@zianet.com wrote: Looks like I can get the 74AC161 in DIP from Mouser. Thanks to everyone for the suggestions. I still like DIP for prototyping on breadboards. Joe Gray W5JG On Fri, Nov 7, 2014 at 4:45 PM, Alex Pummer a...@pcscons.com wrote: check if you could get a 74AC161, which could be connected to divide by 5 at 125 MHz see here http://ecee.colorado.edu/~mcleod/pdfs/IADE/references/ 74AC161.pdf to be sure to work at 125MHz run with 5,5 to 6V... 73 Alex On 11/7/2014 1:12 PM, Joseph Gray wrote: I need to divide a 125 Mhz clock by five. I have looked on Mouser and every chip I find is either obsolete or in SMT. Can anyone recommend a chip that is fast enough and comes in DIP? Joe Gray W5JG ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
