Re: [time-nuts] OCXO PLL gains?

[Bob kb8tq]

Hi

Not a clue, my copy is 40 years old :)

Bob

> On Feb 8, 2019, at 9:19 AM, Adrian Godwin  wrote:
> 
> On Fri, Feb 1, 2019 at 8:09 PM Bob kb8tq  wrote:
> 
>> Gardner:
>> 
>> https://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633
>> >> 
>> 
>> is an oldie but goodie in this area.
>> 
>> 
> The current (3rd) edition of this text is fairly expensive but 1st and 2nd
> editions are incredibly cheap. They are, after all, nearly 40 years old.
> What extra topics are included in the 2005 edition ?
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Re: [time-nuts] OCXO PLL gains?

[Adrian Godwin]

On Fri, Feb 1, 2019 at 8:09 PM Bob kb8tq  wrote:

> Gardner:
>
> https://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633
>  >
>
> is an oldie but goodie in this area.
>
>
The current (3rd) edition of this text is fairly expensive but 1st and 2nd
editions are incredibly cheap. They are, after all, nearly 40 years old.
What extra topics are included in the 2005 edition ?
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Re: [time-nuts] OCXO PLL gains?

[Bob kb8tq]

Hi

The bumps you are seeing are likely due to some sort of filtering in the EFC 
input
to the oscillator you are trying to lock up. 100 Hz is not all that uncommon 
for a filter
cap rolling off noise on the EFC line. Indeed it can be from other things, it’s 
just a guess….

Bob

> On Feb 4, 2019, at 10:44 AM, Anders Wallin  
> wrote:
> 
> I played around with this today, recording 5 minute runs: freerunning, P/10
> gain, P gain, 10x P gain (where P is some unknown value...)
> I then added either a 1M/100n or 500k/100n integrator which really only
> shows in the TDEV-plot, not in the PN-plot.
> https://photos.app.goo.gl/V9xL5MkVsL6RLRXJ7
> 
> maybe "P/10, with integrator" is the best one so far? Seems any increase in
> P-gain always creates an ugly PN-bump?
> Increasing the I-gain is maybe the next thing to try, either with a shorter
> RC-constant, or by increasing the I-weight in the summing op-amp..
> Didn't have time to read the references much - so this is mostly trial and
> error for now...
> 
> Anders
> 
> On Sun, Feb 3, 2019 at 7:01 PM Tom Van Baak  wrote:
> 
>> Bert,
>> 
>> That looks like a very nice board. Thanks for posting. Let us know how to
>> obtain one; as board, kit or product.
>> 
>> /tvb
>> 
>> N.B. The original posting was aol / html. It has been reformatted below to
>> work with the time-nuts server.
>> 
>> 
>> - Original Message -
>> From: ew
>> To: time-nuts@lists.febo.com
>> Cc: j.koe...@bluewin.ch
>> Sent: Sunday, February 03, 2019 5:26 AM
>> Subject: Re: [time-nuts] OCXO PLL gains?
>> 
>> There is a need for clean up loops across time-nuts applications. Right
>> now Corby has one to test  clean up for a HP 5065A and a HP 5061B. How ever
>> there is room for improvement.
>> 
>> In my simple mind there may be an answer for most applications and enough
>> brains among time nuts to define and develop a loop. Many of the telecom
>> GPSDO's use frequency to correct for time, FE5680 a candidate even other
>> Rb's depending what you have and try to accomplish. Morion MV89A, HP10811,
>> Austron 1150, FRK, M100, FTS1200, M1000, OSA8600 all candidates for the
>> other side.
>> 
>> I recently did two OCXO boards one based on many time nuts inputs. Did not
>> find some one to pick up the designs and make it available. I than decided
>> to post Gerber files and based on off list questions and comments boards
>> have been made.
>> 
>> I propose something similar. Our experts come up with an answer, I do a
>> board and add it to my next order, projects are waiting to be ordered after
>> the Chinese holiday. As always Corby will along with Juerg get the first
>> boards and once passed Corby's test I will release information. I do make
>> layout mistakes and I do not want mistakes out there. Cause confusion with
>> corrected boards.
>> 
>> I keep looking at Microsemi 4145C datasheet and I am convinced with the
>> time nuts brains out there one could get close. There is a digital loop
>> between an the HP5071A and a OSA8600 and an analog loop between 8600 and a
>> Wenzel Super Low Noise OCXO. Not now, walk before we run, but the brains
>> and parts are out there.
>> 
>> Bert Kehren
>> 
>> Attached a picture of our first board, we now have later versions, one
>> based on Wenzel 600 sec. design and one similar to the dither filter used
>> in the HP GPSDO. We are not experts.
>> 
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>> 
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Re: [time-nuts] OCXO PLL gains?

[Rice, Hugh (IPH Writing Systems)]

> The 5061 had an analog double integrator using a $100 op amp.
> Maybe Hugh Rice can speak about that. You have to have the 2nd
> integrator to prevent a ramping error term from turning into a
> frequency offset instead of getting integrated out.

I never studied the control loop design on the 5061A/B.  It worked just fine, 
so I didn’t dig into it.
I’ll mention the $100 op-amp more in another story in the future, but it wasn’t 
nearly as exotic as it looks.
I recall it being a hybrid circuit monstrosity – a whole bunch of discrete 
components all potted in blue plastic, and about 2” x 2” in size.
My guess is that it was a high performance device, during the transition days 
from making op-amp with discrete parts on PCAs
(like the 5060A did in the 1960s), to fully integrated op-amps in the 1980s.   
An awkward teen-ager of electronics from the early 1970s, so to speak.

Modern IC op-amps probably could replace it just fine.   Our 
super-technician/engineer on the production engineering team, Dave Montgomery,
used to say we should replace it with and “Op-07”, his favorite high-end 
op-amp.   It costs $.45 each now, if you buy 1000.

Hugh



From: time-nuts  On Behalf Of Richard (Rick) 
Karlquist
Sent: Sunday, February 3, 2019 8:41 AM
To: Magnus Danielson ; Discussion of precise time and 
frequency measurement 
Subject: Re: [time-nuts] OCXO PLL gains?



On 2/2/2019 3:06 PM, Magnus Danielson wrote:

>>   We also used a double integrator
>> on the 5071A cesium standard, but cesium loops are NOT PLL's.
>
> Indeed, double-integrator in FLL is a separate class of problems.
>
> Didn't know it had double-integrator.
>
> Cheers,
> Magnus

The 5061 had an analog double integrator using a $100 op amp.
Maybe Hugh Rice can speak about that. You have to have the 2nd
integrator to prevent a ramping error term from turning into a
frequency offset instead of getting integrated out.

Rick

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Re: [time-nuts] OCXO PLL gains?

[Magnus Danielson]

Hi Rick,

On 2019-02-02 17:49, Richard (Rick) Karlquist wrote:

On 2/1/2019 3:22 PM, Magnus Danielson wrote:


The Gardner book is the one book I recommend. Few books has core 
knowledge so well compressed. If one only gets one book, this would 
be the one I would recommend.


Cheers,
Magnus



I'm glad someone mentioned this classic.  45 years ago, this
was my first training in PLLs.  In the first 10 or 20 pages,
I learned just about all I needed to know about designing PLL's.
Design for a natural frequency around 1% of the sampling rate,
set damping factor to at least 1, and I was off and
running.

Exactly. If I would have to settle with only one PLL book, the Gardner 
book is it for sure. It may not be the best one for all people to start 
with, but they should mature up to it pretty quickly after the Best book 
if that is where they start.

As far as PN "bumps" are concerned:  they are generally unavoidable,
but you want keep them from being very peaky.  You either need to
reduce loop bandwidth or reduce extraneous poles in the tuning
voltage path.

Well, if your damping factor is too low, you will have a more 
prodominant peak due to the resonance. With a well-damped system, the 
noises add on top of each other at the cross-over and well, you can only 
do so much on a second degree system.

You can easily build a SPICE model where voltage represents phase
and simulate the loop, both open and closed.  The open loop
response should have one and only one dominant pole.  That is
what gives you a stable loop without a lot of peaking.

Gardner has an interesting chapter on 3rd order PLL's utilizing
double integrators.  Unless you are tracking out doppler shift
on a moving signal source, you should never need double integrators.

Indeed. The improved slopes may be a reason to raise the level thought.


We used a double integrator on the oven control loop on the HP1938A
OCXO.  It was tricky to get it working correctly, due to
a phenomenon known as "wind up".
The danger is that it is no longer stable for all settings, so that can 
catch you badly.

  We also used a double integrator
on the 5071A cesium standard, but cesium loops are NOT PLL's.


Indeed, double-integrator in FLL is a separate class of problems.

Didn't know it had double-integrator.

Cheers,
Magnus



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Re: [time-nuts] OCXO PLL gains?

[Richard (Rick) Karlquist]

On 2/2/2019 3:06 PM, Magnus Danielson wrote:


  We also used a double integrator
on the 5071A cesium standard, but cesium loops are NOT PLL's.


Indeed, double-integrator in FLL is a separate class of problems.

Didn't know it had double-integrator.

Cheers,
Magnus


The 5061 had an analog double integrator using a $100 op amp.
Maybe Hugh Rice can speak about that.  You have to have the 2nd
integrator to prevent a ramping error term from turning into a
frequency offset instead of getting integrated out.

Rick

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Re: [time-nuts] OCXO PLL gains?

[Richard (Rick) Karlquist]

On 2/1/2019 3:22 PM, Magnus Danielson wrote:


The Gardner book is the one book I recommend. Few books has core 
knowledge so well compressed. If one only gets one book, this would be 
the one I would recommend.


Cheers,
Magnus



I'm glad someone mentioned this classic.  45 years ago, this
was my first training in PLLs.  In the first 10 or 20 pages,
I learned just about all I needed to know about designing PLL's.
Design for a natural frequency around 1% of the sampling rate,
set damping factor to at least 1, and I was off and
running.

As far as PN "bumps" are concerned:  they are generally unavoidable,
but you want keep them from being very peaky.  You either need to
reduce loop bandwidth or reduce extraneous poles in the tuning
voltage path.

You can easily build a SPICE model where voltage represents phase
and simulate the loop, both open and closed.  The open loop
response should have one and only one dominant pole.  That is
what gives you a stable loop without a lot of peaking.

Gardner has an interesting chapter on 3rd order PLL's utilizing
double integrators.  Unless you are tracking out doppler shift
on a moving signal source, you should never need double integrators.

We used a double integrator on the oven control loop on the HP1938A
OCXO.  It was tricky to get it working correctly, due to
a phenomenon known as "wind up".  We also used a double integrator
on the 5071A cesium standard, but cesium loops are NOT PLL's.

Rick

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Re: [time-nuts] OCXO PLL gains?

[Dana Whitlow]

I learned a useful rule of thumb design procedure for 2nd degree PLLs some
time ago
(I'll speak in the context of using an inverting op-amp in the loop
gain/filter stage):

Step 1: Short the capacitor in the opamp's FB loop, then set the resistor
so that
the PLL has the desired loop bandwidth.  This is the gain part of the
adjustment.

2. Then set the capacitor value so that its reactance at the frequency of
the loop BW
is about 1/5th the resistance that you set in step 1.  This is the damping
setting step.

3. Then examine the overall loop behavior for its damping behavior.  If
there are no
"hidden poles" somewhere, the above should yield pretty good results right
off that
bat, but a little tweaking is always fair game if you want.

However, there *are* often "hidden rolloffs" (poles) somewhere, and damping
behavior will be degraded.  Such poles are most likely to arise in two
areas-
the VCO itself, or the opamp you're using.  Be sure that the opamp's gain-
bandwidth is much larger than required, said requirement being the product
of the gain being called for in the opamp stage and the desired PLL
bandwidth.
And VCOs always introduce hidden poles into the loop, which are not usually
well documented in the oscillator's specsheet (if at all).

But with luck you won't run into either problem area for the low loop
bandwidths
typically desired in oscillator-cleanup PLL applications.

Dana  K8YUM





On Fri, Feb 1, 2019 at 11:04 PM Magnus Danielson  wrote:

> Hej Anders,
>
> On 2019-02-01 19:11, Anders Wallin wrote:
> > Hi all, is there are rule-of-thumb or simple paper/presentation of how to
> > choose PLL-gains?
> >
> > I have a phase-detector that gives out a slope of roughly 1 V/rad,
> followed
> > by an op-amp circuit with proportional, integral, and double-integral
> gains
> > summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
> > ppm pull-range, from datasheet).
> >
> > So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
> > 'bump' somewhere between 10 and 100 Hz offset from the carrier.
> > I tried the integrator with a time-constant of 1/16Hz using R 100k  C
> 100n,
> > but it wouldn't lock.
> > The thinking was to put the integrator time-constant about where the
> > free-running ADEV turns upwards from a 1/tau slope.
> >
> > So far I didn't enable the double-integrator - not sure if it's worth the
> > trouble or not..
>
> OK, I can give you a more in-depth overview, but I just crash this quickly.
>
> Now, let's assume you have a pure phase-detector (such as a mixer), a
> PI-regulator and an oscillator.
>
> This represents a second-degree PLL, which has two key properties:
> natural frequency and damping factor.
>
> The natural frequency depends on the loop bandwidth as it goes though
> the integrator path and the I factor.
>
> The I factor is proportional to the natural frequency in square.
>
> The damping factor depents on the balance between the I and P factors,
> in fact the P factor is proportional to the natural frequency and
> damping factor multiplied.
>
> I've derived the formulas multiple times here on time-nuts, but if you
> need further details, please let me know. Happy to discuss off-list.
>
> The loop-gain, as it goes through the integrator path, will decide the
> bandwidh of the PLL and thus the time-constants of the PLL.
>
> The loop-gain, as it goes through the proportional path, decides the
> damping factor and hence the bump of the PLL.
>
> In general, you want to make sure your damping constant is high enough
> and thus avoid the bump, and then dimension the filter bandwidth to
> bring the best balance between the reference oscillators phase-noise and
> the locked oscillators phase-noise. Essentially you overlay the
> phase-plots of reference and locked oscillator, and where they cross you
> put your cross-over bandwidth, as the PLL will low-pass filtet the
> reference oscillator phase-noise and high-pass filter the
> locked-oscillator phase-noise. The resonance due to lack of damping will
> exagerate the response at the cross-over frequency.
>
> Uhm, this may sound a bit uncoherently, but it all fits together if you
> play around.
>
> For the double-integration path, you need to be careful as the
> root-locus does not guarantee a stable system, as the complex pole-pair
> can move over to the right-hand side and hence severely unstable.
>
> I can make a few recommended readings. The TI application note
> referenced isn't bad, but there is a few books to look at. The TI
> app-note does however cover some of the field the following references
> miss out on.
>
> The Best book may be a good crash-coarse, but ends up not being good at
> teach the basics. It may be good for crashing into the field of PLLs,
> and for some things it's a very handy reference, but for others... not
> so much.
>
> The Gardner book is the one book I recommend. Few books has core
> knowledge so well compressed. If one only gets one book, this would be
> the one I 

Re: [time-nuts] OCXO PLL gains?

[Magnus Danielson]

Hej Anders,

On 2019-02-01 19:11, Anders Wallin wrote:

Hi all, is there are rule-of-thumb or simple paper/presentation of how to
choose PLL-gains?

I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
by an op-amp circuit with proportional, integral, and double-integral gains
summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
ppm pull-range, from datasheet).

So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
'bump' somewhere between 10 and 100 Hz offset from the carrier.
I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
but it wouldn't lock.
The thinking was to put the integrator time-constant about where the
free-running ADEV turns upwards from a 1/tau slope.

So far I didn't enable the double-integrator - not sure if it's worth the
trouble or not..


OK, I can give you a more in-depth overview, but I just crash this quickly.

Now, let's assume you have a pure phase-detector (such as a mixer), a 
PI-regulator and an oscillator.


This represents a second-degree PLL, which has two key properties: 
natural frequency and damping factor.


The natural frequency depends on the loop bandwidth as it goes though 
the integrator path and the I factor.


The I factor is proportional to the natural frequency in square.

The damping factor depents on the balance between the I and P factors, 
in fact the P factor is proportional to the natural frequency and 
damping factor multiplied.


I've derived the formulas multiple times here on time-nuts, but if you 
need further details, please let me know. Happy to discuss off-list.


The loop-gain, as it goes through the integrator path, will decide the 
bandwidh of the PLL and thus the time-constants of the PLL.


The loop-gain, as it goes through the proportional path, decides the 
damping factor and hence the bump of the PLL.


In general, you want to make sure your damping constant is high enough 
and thus avoid the bump, and then dimension the filter bandwidth to 
bring the best balance between the reference oscillators phase-noise and 
the locked oscillators phase-noise. Essentially you overlay the 
phase-plots of reference and locked oscillator, and where they cross you 
put your cross-over bandwidth, as the PLL will low-pass filtet the 
reference oscillator phase-noise and high-pass filter the 
locked-oscillator phase-noise. The resonance due to lack of damping will 
exagerate the response at the cross-over frequency.


Uhm, this may sound a bit uncoherently, but it all fits together if you 
play around.


For the double-integration path, you need to be careful as the 
root-locus does not guarantee a stable system, as the complex pole-pair 
can move over to the right-hand side and hence severely unstable.


I can make a few recommended readings. The TI application note 
referenced isn't bad, but there is a few books to look at. The TI 
app-note does however cover some of the field the following references 
miss out on.


The Best book may be a good crash-coarse, but ends up not being good at 
teach the basics. It may be good for crashing into the field of PLLs, 
and for some things it's a very handy reference, but for others... not 
so much.


The Gardner book is the one book I recommend. Few books has core 
knowledge so well compressed. If one only gets one book, this would be 
the one I would recommend.


The Wolaver book is really a great complementary book. Great on it's own 
merrits.


I end up using all three to cover enough aspects of the field. I should 
probably be using the TI app-note a little more.


Let's talk about your specific problem and I will help you more.

Cheers,
Magnus


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Re: [time-nuts] OCXO PLL gains?

[Bob kb8tq]

Hi

I’m sure there is a closed form solution somewhere out there that includes 
noise. It is 
more common to do it with simulation by one method or another. You normally 
have a 
lot going on in a PLL. 

Simple answer is - less gain = less bandwidth.  If what you have is too wide, 
cut it down. 
If you have too much of a peak with just P, check for lag in the circuit. It is 
very normal 
to have 3db of noise peaking.  

It’s generally best to run through a gain / stability calculation once you go 
to P-I. It will 
not help much with the noise side of things but it will help with getting the 
loop to lock. 
It will also give you a good idea of how much gain peaking you may have with a 
given 
configuration. There are a ton of app notes and text books out there on that 
side of it. 
Gardner:

https://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633 


is an oldie but goodie in this area. 

Bob

> On Feb 1, 2019, at 1:11 PM, Anders Wallin  wrote:
> 
> Hi all, is there are rule-of-thumb or simple paper/presentation of how to
> choose PLL-gains?
> 
> I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
> by an op-amp circuit with proportional, integral, and double-integral gains
> summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
> ppm pull-range, from datasheet).
> 
> So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
> 'bump' somewhere between 10 and 100 Hz offset from the carrier.
> I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
> but it wouldn't lock.
> The thinking was to put the integrator time-constant about where the
> free-running ADEV turns upwards from a 1/tau slope.
> 
> So far I didn't enable the double-integrator - not sure if it's worth the
> trouble or not..
> 
> thanks,
> Anders
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Re: [time-nuts] OCXO PLL gains?

[Alex Pummer]

Hi Anders

look that

https://www.analog.com/media/ru/training-seminars/tutorials/MT-086.pdf

73

KJ6UHN Alex


On 2/1/2019 10:11 AM, Anders Wallin wrote:

Hi all, is there are rule-of-thumb or simple paper/presentation of how to
choose PLL-gains?

I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
by an op-amp circuit with proportional, integral, and double-integral gains
summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
ppm pull-range, from datasheet).

So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
'bump' somewhere between 10 and 100 Hz offset from the carrier.
I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
but it wouldn't lock.
The thinking was to put the integrator time-constant about where the
free-running ADEV turns upwards from a 1/tau slope.

So far I didn't enable the double-integrator - not sure if it's worth the
trouble or not..

thanks,
Anders
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Re: [time-nuts] OCXO PLL gains?

[jimlux]

On 2/1/19 10:11 AM, Anders Wallin wrote:

Hi all, is there are rule-of-thumb or simple paper/presentation of how to
choose PLL-gains?

I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
by an op-amp circuit with proportional, integral, and double-integral gains
summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
ppm pull-range, from datasheet).

So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
'bump' somewhere between 10 and 100 Hz offset from the carrier.
I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
but it wouldn't lock.
The thinking was to put the integrator time-constant about where the
free-running ADEV turns upwards from a 1/tau slope.

So far I didn't enable the double-integrator - not sure if it's worth the
trouble or not..





Dean Banerjee's book probably has the answer -

http://www.ti.com/tool/PLL_BOOK

Excellent cookbook

The simulators on TI and AD website also work well for trying different 
things.

I don't know if the web-simulators do ADEV, though.


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[time-nuts] OCXO PLL gains?

[Anders Wallin]

Hi all, is there are rule-of-thumb or simple paper/presentation of how to
choose PLL-gains?

I have a phase-detector that gives out a slope of roughly 1 V/rad, followed
by an op-amp circuit with proportional, integral, and double-integral gains
summed into one voltage [0, 3.3V] on the tune-pine of the OCXO ( +/- 0.6
ppm pull-range, from datasheet).

So far it locks with only P-gain, but the phase-noise (and ADEV) shows a
'bump' somewhere between 10 and 100 Hz offset from the carrier.
I tried the integrator with a time-constant of 1/16Hz using R 100k  C 100n,
but it wouldn't lock.
The thinking was to put the integrator time-constant about where the
free-running ADEV turns upwards from a 1/tau slope.

So far I didn't enable the double-integrator - not sure if it's worth the
trouble or not..

thanks,
Anders
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