Re: [U-Boot] [PATCH v4 10/12] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to
800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
---
Changes v2:
- enable fan on odroid U3
Changes v3:
- odroid.c: clean up board name related code
- odroid.c: remove static from set_board_type()
- odroid.c: add implementation of functions: get_dfu_alt_*
- odroid.c: include misc.h
Changes v4:
odroid.c: dfu_get_alt_boot: add call get_boot_mode()
---
board/samsung/odroid/Makefile | 8 +
board/samsung/odroid/odroid.c | 466
++
board/samsung/odroid/setup.h | 227
3 files changed, 701 insertions(+)
create mode 100644 board/samsung/odroid/Makefile
create mode 100644 board/samsung/odroid/odroid.c
create mode 100644 board/samsung/odroid/setup.h
diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak p.marc...@samsung.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y:= odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 000..28706af
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+#include asm/arch/cpu.h
+#include power/pmic.h
+#include power/max77686_pmic.h
+#include errno.h
+#include usb.h
+#include usb/s3c_udc.h
+#include samsung/misc.h
+#include setup.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+ ODROID_TYPE_U3,
+ ODROID_TYPE_X2,
+};
+
+void set_board_type(void)
+{
+ int val;
+
+ /* Check GPC1 pin 2 */
+ gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
+ gpio_direction_input(EXYNOS4X12_GPIO_C12);
+
+ /* XCL205 - needs some latch time */
+ mdelay(10);
+
+ /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+ val = gpio_get_value(EXYNOS4X12_GPIO_C12);
+ if (val)
val is unnecessary. int val can be removed.
if (gpio_get_value(EXYNS4x12_GPIO_C12))
+ gd-board_type = ODROID_TYPE_X2;
+ else
+ gd-board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_name(void)
+{
+ const char *board_name = odroid;
Is there other approach or general method for getting board name?
+
+ return board_name;
+}
+
+const char *get_board_type(void)
+{
+ const char *board_type[] = {u3, x2};
+
+ return board_type[gd-board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void)
+{
+ return getenv(dfu_alt_system);
+}
+
+char *get_dfu_alt_boot(void)
+{
+ char *alt_boot = NULL;
+
+ switch (get_boot_mode()) {
+ case BOOT_MODE_MMC:
+ alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+ break;
+ default:
+ alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+ break;
+ }
+
+ if (!alt_boot)
+ return NULL;
Is it need? alt_boot is set to CONFIG_DFU_ALT_BOOT_EMMC by default, isn't?
CONFIG_DFU_ALT_BOOT_EMMC is 0?
+
+ setenv(dfu_alt_boot, alt_boot);
+
+ return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+ /*
+ * CMU_CPU clocks src to MPLL
+ * Bit values: 0 ; 1
+ * MUX_APLL_SEL:FIN_PLL ; FOUT_APLL
+ * MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
+ * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+ * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+ */
+ clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |
+ MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
+ set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
+ MUX_MPLL_USER_SEL_C(1);
0x1 or 1? you can use it consistency. MUX_APLL_SEL(1) or MUX_APLL_SEL(0x1).
+
+ clrsetbits_le32(clk-src_cpu, clr_src_cpu,
Re: [U-Boot] [PATCH v4 04/12] board:samsung: check the boot device and init the right mmc driver.
Hello Jaehoon,
On 07/04/2014 07:45 AM, Jaehoon Chung wrote:
Hi, Przemyslaw.
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to 0 in the most config cases.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes V3:
- separate two changes into two commits
Changes V4:
- board.c: add functions: init_mmc() and init_dwmmc()
- board_mmc_init(): call get_boot_mode()
---
board/samsung/common/board.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..4d3f216 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+static int init_mmc(void)
+{
+#ifdef CONFIG_SDHCI
+ return exynos_mmc_init(gd-fdt_blob);
+#else
+ return 0;
+#endif
+}
+
+static int init_dwmmc(void)
{
- int ret;
#ifdef CONFIG_DWMMC
- /* dwmmc initializattion for available channels */
- ret = exynos_dwmmc_init(gd-fdt_blob);
- if (ret)
- debug(dwmmc init failed\n);
+ return exynos_dwmmc_init(gd-fdt_blob);
+#else
+ return 0;
#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ if (get_boot_mode() == BOOT_MODE_MMC) {
+ ret = init_mmc();
+ ret |= init_dwmmc();
+ } else {
+ ret = init_dwmmc();
+ ret |= init_mmc();
+ }
Well, i have some confusion for this.
Did you consider the case like init_dwmmc() is succeed and init_mmc() is failed?
it's hard to control the error for both.
Best Regards,
Jaehoon Chung
In our vendor init code, the value returned by this function has no
significant meaning since there is no implementation of function
cpu_mmc_init().
So checking this error is just for a debug purposes:
# if (ret)
# debug(mmc init failed\n);
and the returned value:
mmc | dwmmc - ret
0 | 1 - 1
1 | 0 - 1
1 | 1 - 1
0 | 0 - 0
So we have an error message on any error.
-#ifdef CONFIG_SDHCI
- /* mmc initializattion for available channels */
- ret = exynos_mmc_init(gd-fdt_blob);
if (ret)
debug(mmc init failed\n);
-#endif
+
return ret;
}
#endif
Thank you,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH v4 08/12] samsung: board: enable support of multiple board types
On 07/04/2014 07:49 AM, Jaehoon Chung wrote:
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This change adds declaration of functions:
- set_board_type() - called at checkboard()
- get_board_type() - called at checkboard()
- get_board_name()
For supporting multiple board types in a one config - it is welcome
to display the current board model. This is what get_board_type()
should return.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
Changes v3:
- change the commit order
- include/samsung/misc.h: add new functions declaration
- update a commit message
Changes v4:
- checkboard(): remove redundant variable
---
board/samsung/common/board.c | 12 +---
include/samsung/misc.h | 5 +
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index a46e87b..3e27130 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -280,11 +280,17 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
- const char *board_name;
+ const char *board_info;
Is there a reason that it's renaming?
Best Regards,
Jaehoon Chung
Yes, I think that the board_info is more suitable as a common for name
and type.
- board_name = fdt_getprop(gd-fdt_blob, 0, model, NULL);
- printf(Board: %s\n, board_name ? board_name : unknown);
+ board_info = fdt_getprop(gd-fdt_blob, 0, model, NULL);
+ printf(Board: %s\n, board_info ? board_info : unknown);
+#ifdef CONFIG_BOARD_TYPES
+ set_board_type();
+ board_info = get_board_type();
+
+ printf(Model: %s\n, board_info ? board_info : unknown);
+#endif
return 0;
}
#endif
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index e82bf32..cc41997 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -33,5 +33,10 @@ char *get_dfu_alt_system(void);
char *get_dfu_alt_boot(void);
void set_dfu_alt_info(void);
#endif
+#ifdef CONFIG_BOARD_TYPES
+void set_board_type(void);
+const char *get_board_type(void);
+const char *get_board_name(void);
+#endif
#endif /* __SAMSUNG_MISC_COMMON_H__ */
Thanks,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH v4 10/12] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
On 07/04/2014 08:07 AM, Jaehoon Chung wrote:
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
---
Changes v2:
- enable fan on odroid U3
Changes v3:
- odroid.c: clean up board name related code
- odroid.c: remove static from set_board_type()
- odroid.c: add implementation of functions: get_dfu_alt_*
- odroid.c: include misc.h
Changes v4:
odroid.c: dfu_get_alt_boot: add call get_boot_mode()
---
board/samsung/odroid/Makefile | 8 +
board/samsung/odroid/odroid.c | 466 ++
board/samsung/odroid/setup.h | 227
3 files changed, 701 insertions(+)
create mode 100644 board/samsung/odroid/Makefile
create mode 100644 board/samsung/odroid/odroid.c
create mode 100644 board/samsung/odroid/setup.h
diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak p.marc...@samsung.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 000..28706af
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+#include asm/arch/cpu.h
+#include power/pmic.h
+#include power/max77686_pmic.h
+#include errno.h
+#include usb.h
+#include usb/s3c_udc.h
+#include samsung/misc.h
+#include setup.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+ ODROID_TYPE_U3,
+ ODROID_TYPE_X2,
+};
+
+void set_board_type(void)
+{
+ int val;
+
+ /* Check GPC1 pin 2 */
+ gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
+ gpio_direction_input(EXYNOS4X12_GPIO_C12);
+
+ /* XCL205 - needs some latch time */
+ mdelay(10);
+
+ /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+ val = gpio_get_value(EXYNOS4X12_GPIO_C12);
+ if (val)
val is unnecessary. int val can be removed.
if (gpio_get_value(EXYNS4x12_GPIO_C12))
ok
+ gd-board_type = ODROID_TYPE_X2;
+ else
+ gd-board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_name(void)
+{
+ const char *board_name = odroid;
Is there other approach or general method for getting board name?
Actually, the board name is the same as CONFIG_SYS_BOARD, but we are
going to have only one binary for Exynos 4 boards in the future - so
such function is welcome. We can also put this into the dts file.
+
+ return board_name;
+}
+
+const char *get_board_type(void)
+{
+ const char *board_type[] = {u3, x2};
+
+ return board_type[gd-board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void)
+{
+ return getenv(dfu_alt_system);
+}
+
+char *get_dfu_alt_boot(void)
+{
+ char *alt_boot = NULL;
+
+ switch (get_boot_mode()) {
+ case BOOT_MODE_MMC:
+ alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+ break;
+ default:
+ alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+ break;
+ }
+
+ if (!alt_boot)
+ return NULL;
Is it need? alt_boot is set to CONFIG_DFU_ALT_BOOT_EMMC by default, isn't?
CONFIG_DFU_ALT_BOOT_EMMC is 0?
Oops, right. I must fix that.
+
+ setenv(dfu_alt_boot, alt_boot);
+
+ return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+ /*
+* CMU_CPU clocks src to MPLL
+* Bit values: 0 ; 1
+* MUX_APLL_SEL:FIN_PLL ; FOUT_APLL
+* MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
+* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+ */
+ clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |
+ MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
+
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi Benoît, On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau benoit.thebaudeau@gmail.com wrote: Hi Albert, On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Helmut, On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger helmut.rai...@hale.at wrote: Hi, On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: )Dear Helmut Raiger, On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. It does, thanks -- but I fail to see any SPL code built for TT-01. You're getting SPL issues with another target, right? Helmut seems to be working on a custom TT-01 variant (or just with a specific hardware configuration using dip switches, or jumpers, etc.) using the i.MX31 NAND internal boot rather than the mainline boot source. No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Ok, I think I'm getting it, but actually you don't need PIC (your code won't run at arbitrary locations), you need VMAs vs LMAs (your code will run partly at one location, partly at another, but will be loaded at only one of these locations). Therefore, we should be able to manage this in the linker script, by basically defining two output sections: the first one with a VMA and LMA equal to 0xB800 both, and which would contain the 'copier' code; and the second one with a VMA equal to CONFIG_SPL_TEXT_BASE (so that it links properly for running at that address) and a LMA equal to 0xB80 (so that it gets lumped with the first section in the less-than-2K ELF file produced by the linker. (actually we'd have several output sections with VMA==LMA, but it does not affect the core of the idea.) Does it make sense to you? It makes sense to me. That should work, but it'd be better to avoid adding a custom linker script. A simple fix in vectors.S would be preferable if possible. Also, the __image_copy_start stuff should be taken care of with such a change. I do not intend to have this in a custom linker script; I want this to be in the common ARM SPL linker script (I hope it is what Helmut's TT-01 changes use) -- I also want to get rid of all custom linker scripts in the ARM par of U-Boot, but I could not get this done for 2014.07. BTW, I see that you skipped arch/arm/cpu/arm1136/u-boot-spl.lds in commit 41623c91 (addition of *(.vectors)). Was it intentional? Not that I can remember: I did modify the arm1136 start.S, so te linker scripts should have followed. It silently changes woodburn_sd because the fallback exception vectors no longer exist. This should not cause a build error because the _start symbol is duplicated in this linker script. The board may also boot correctly with this, but the default vectors can be useful in some cases, especially for debugging exceptions. Can you post a patch today? I'll pull it in a PR I'll do today before COB. Cordialement, Benoît Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARMv8 spin-table patches
Hi, Apologies for the late reply. On Fri, Jun 27, 2014 at 05:44:05PM +0100, Tom Rini wrote: On Fri, Jun 27, 2014 at 09:11:39AM -0700, York Sun wrote: Dear Albert, Wolfgang, Tom, I have seen some patches for PSCI. We don't have PSCI enabled on Freescale ARMv8 SoCs. Will spin-table patches be acceptable? Baring some technical reasons why no, you can't do that, yes, lets see the patches :) I'd point out that it's decidedly sub-optimal as spin-table provides no provision for CPU hotplug (which for Linux will affect kexec and other features relying on CPU hotplug support). Additionally, spin-table has the unfortunate property of allowing the firmware to throw an unbound number of CPUs into the kernel at once (when they share a cpu-release-addr), where they can spend a lot of time spinning pointlessly (executing kernel code from memory and possibly fetching it into I-caches) depending on the number of events a CPU happens to generate at runtime. Linux will continue to support spin-table, but it's far preferable to use PSCI. Another possibility raised was trying to fix spin-table to provide provisions for CPU hotplug, but I've not had the time to look into this in great detail. A while ago there were some PSCI patches for (32-bit) ARM [1]... Thanks, Mark. [1] https://git.kernel.org/cgit/linux/kernel/git/maz/u-boot.git/log/?h=wip/psci-v4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: fix the ARCH Timer frequency setting.
On 07/04/2014 04:43 AM, Xiubo Li-B47053 wrote: Subject: Re: [PATCH 1/4] ARM: fix the ARCH Timer frequency setting. On 07/03/2014 12:51 PM, Xiubo Li wrote: For some SoCs, the CONFIG_SYS_CLK_FREQ maybe won't equal the ARCH Timer's frequency. Can you give an example? In LS1021A-QDS/TWR, the CONFIG_SYS_CLK_FREQ is 100Mhz and the ARCH timer's Frequency will be 12.5Mhz... Here using the CONFIG_TIMER_CLK_FREQ instead if the ARCH Timer's frequency need to config here. Signed-off-by: Xiubo Li li.xi...@freescale.com --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6f90988..e9766c0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -147,11 +147,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ Aren't you breaking the boards which rely on CONFIG_SYS_CLK_FREQ ? I hadn't found any board is using this in the upstreamed tree, or may I miss something ? If there exist some, and I will redefined it for them here. In ARMv7, what could I find is that only vexpress_ca15_tc2 board has enabled the CONFIG_ARMV7_VIRT without defining it. Yes, this board defines CONFIG_ARMV7_VIRT. In order for this board to work after your changes you need to define CONFIG_TIMER_CLK_FREQ. Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mpc85xx/t104x: Enable L2 and CPC cache when resume
From: Tang Yuantian yuantian.t...@freescale.com
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
based on u-boot-mpc85xx.
there are some warning in exsiting code, so they are in this patch.
I like to address it if needed in following patch.
arch/powerpc/cpu/mpc85xx/cpu_init.c | 163 +++-
arch/powerpc/include/asm/cache.h| 6 ++
arch/powerpc/lib/board.c| 5 ++
3 files changed, 98 insertions(+), 76 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 78316a6..55f0bc7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#ifdef CONFIG_SYS_FSL_CPC
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
-static void disable_cpc_sram(void)
+void disable_cpc_sram(void)
{
int i;
@@ -251,7 +251,7 @@ static void enable_tdm_law(void)
}
#endif
-static void enable_cpc(void)
+void enable_cpc(void)
{
int i;
u32 size = 0;
@@ -306,6 +306,7 @@ static void invalidate_cpc(void)
#else
#define enable_cpc()
#define invalidate_cpc()
+#define disable_cpc_sram()
#endif /* CONFIG_SYS_FSL_CPC */
/*
@@ -545,88 +546,15 @@ int enable_cluster_l2(void)
/*
* Initialize L2 as cache.
- *
- * The newer 8548, etc, parts have twice as much cache, but
- * use the same bit-encoding as the older 8555, etc, parts.
- *
*/
-int cpu_init_r(void)
+int l2cache_init(void)
{
__maybe_unused u32 svr = get_svr();
-#ifdef CONFIG_SYS_LBC_LCRR
- fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
-#endif
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem
*)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
-#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) defined(CONFIG_MP)
- extern int spin_table_compat;
- const char *spin;
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
-#endif
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
- defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
- /*
-* CPU22 and NMG_CPU_A011 share the same workaround.
-* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
-* fixed in 2.0. NMG_CPU_A011 is activated by default and can
-* be disabled by hwconfig with syntax:
-*
-* fsl_cpu_a011:disable
-*/
- extern int enable_cpu_a011_workaround;
-#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
- enable_cpu_a011_workaround = (SVR_MAJ(svr) 3);
-#else
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
- int n, res;
-
- n = getenv_f(hwconfig, buffer, sizeof(buffer));
- if (n 0)
- buf = buffer;
-
- res = hwconfig_arg_cmp_f(fsl_cpu_a011, disable, buf);
- if (res 0)
- enable_cpu_a011_workaround = 0;
- else {
- if (n = HWCONFIG_BUFFER_SIZE) {
- printf(fsl_cpu_a011 was not found. hwconfig variable
- may be too long\n);
- }
- enable_cpu_a011_workaround =
- (SVR_SOC_VER(svr) == SVR_P4080 SVR_MAJ(svr) 3) ||
- (SVR_SOC_VER(svr) != SVR_P4080 SVR_MAJ(svr) 2);
- }
-#endif
- if (enable_cpu_a011_workaround) {
- flush_dcache();
- mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
- sync();
- }
-#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
- /*
-* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
-* in write shadow mode. Checking DCWS before setting SPR 976.
-*/
- if (mfspr(L1CSR2) L1CSR2_DCWS)
- mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x8000));
-#endif
-
-#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) defined(CONFIG_MP)
- spin = getenv(spin_table_compat);
- if (spin (*spin == 'n'))
- spin_table_compat = 0;
- else
- spin_table_compat = 1;
-#endif
puts (L2:);
@@ -751,6 +679,89 @@ skip_l2:
puts(disabled\n);
#endif
+ return 0;
+}
+
+/*
+ *
+ * The newer 8548, etc, parts have twice as much cache, but
+ * use the same bit-encoding as the older 8555, etc, parts.
+ *
+ */
+int cpu_init_r(void)
+{
+ __maybe_unused u32 svr = get_svr();
+#ifdef
[U-Boot] [PATCH 6/6] git-mailrc: add me as the maintainer of UniPhier SoCs
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- doc/git-mailrc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/git-mailrc b/doc/git-mailrc index e53c888..77f66f9 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -26,6 +26,7 @@ alias lukma Lukasz Majewski l.majew...@samsung.com alias macpaulMacpaul Lin macp...@andestech.com alias marex Marek Vasut ma...@denx.de alias monstr Michal Simek mon...@monstr.eu +alias masahiro Masahiro Yamada yamad...@jp.panasonic.com alias panto Pantelis Antoniou pa...@antoniou-consulting.com alias prafulla Prafulla Wadaskar prafu...@marvell.com alias prom Minkyu Kang mk7.k...@samsung.com @@ -59,6 +60,7 @@ alias samsunguboot, prom alias tegra uboot, sjg, Tom Warren twar...@nvidia.com, Stephen Warren swar...@nvidia.com alias tegra2 tegra alias ti uboot, trini +alias uniphier uboot, masahiro alias avr32 uboot, abiessmann -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] arm: uniphier: add UniPhier config headers
Configuration headers for Panasonic UniPhier series: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- include/configs/ph1_ld4.h | 64 + include/configs/ph1_pro4.h| 66 + include/configs/ph1_sld8.h| 64 + include/configs/uniphier-common.h | 275 ++ 4 files changed, 469 insertions(+) create mode 100644 include/configs/ph1_ld4.h create mode 100644 include/configs/ph1_pro4.h create mode 100644 include/configs/ph1_sld8.h create mode 100644 include/configs/uniphier-common.h diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h new file mode 100644 index 000..50c2f8e --- /dev/null +++ b/include/configs/ph1_ld4.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada yamad...@jp.panasonic.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable CONFIG_UNIPHIER_SERIAL + * On-board UART: enable CONFIG_SYS_NS16550_SERIAL + */ +#if 0 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK36864000 + +#define CONFIG_SMC911X + +/*--- + * Board Type + *--*/ +#define CONFIG_PH1_LD4 + +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +#define CONFIG_DDR_FREQ 1600 + +/* + * Memory Size Mapping + */ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x8000 +#define CONFIG_SDRAM0_SIZE 0x1000 +#define CONFIG_SDRAM1_BASE 0x9000 +#define CONFIG_SDRAM1_SIZE 0x1000 + +#define CONFIG_SPL_TEXT_BASE 0x4 + +#include uniphier-common.h + +#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h new file mode 100644 index 000..6633f7a --- /dev/null +++ b/include/configs/ph1_pro4.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada yamad...@jp.panasonic.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable CONFIG_UNIPHIER_SERIAL + * On-board UART: enable CONFIG_SYS_NS16550_SERIAL + */ +#if 0 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK73728000 + +#define CONFIG_SMC911X + +/*--- + * Board Type + *--*/ +#define CONFIG_PH1_PRO4 + +#define CONFIG_DDR_NUM_CH0 2 +#define CONFIG_DDR_NUM_CH1 2 + +#define CONFIG_DDR_FREQ 1600 + +#define CONFIG_UNIPHIER_SMP + +/* + * Memory Size Mapping + */ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x8000 +#define CONFIG_SDRAM0_SIZE 0x2000 +#define CONFIG_SDRAM1_BASE 0xa000 +#define CONFIG_SDRAM1_SIZE 0x2000 + +#define CONFIG_SPL_TEXT_BASE 0x10 + +#include uniphier-common.h + +#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h new file mode 100644 index 000..5130adf --- /dev/null +++ b/include/configs/ph1_sld8.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada yamad...@jp.panasonic.com + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable
[U-Boot] [PATCH 2/6] serial: add UniPhier serial driver
The driver for on-chip UART used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
drivers/serial/Makefile | 1 +
drivers/serial/serial.c | 2 +
drivers/serial/serial_uniphier.c | 206 +++
3 files changed, 209 insertions(+)
create mode 100644 drivers/serial/serial_uniphier.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 571c18f..385b2f9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
+obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index fd61a5e..9a05bef 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);
serial_initfunc(arm_dcc_initialize);
serial_initfunc(mxs_auart_initialize);
serial_initfunc(arc_serial_initialize);
+serial_initfunc(uniphier_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@@ -250,6 +251,7 @@ void serial_initialize(void)
arm_dcc_initialize();
mxs_auart_initialize();
arc_serial_initialize();
+ uniphier_serial_initialize();
serial_assign(default_serial_console()-name);
}
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
new file mode 100644
index 000..82c754c
--- /dev/null
+++ b/drivers/serial/serial_uniphier.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ * Author: Masahiro Yamada yamad...@jp.panasonic.com
+ *
+ * Based on serial_ns16550.c
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. r...@flyingpig.com.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include serial.h
+
+#define UART_REG(x)\
+ u8 x; \
+ u8 postpad_##x[3];
+
+/*
+ * Note: Register map is slightly different from that of 16550.
+ */
+struct uniphier_serial {
+ UART_REG(rbr); /* 0x00 */
+ UART_REG(ier); /* 0x04 */
+ UART_REG(iir); /* 0x08 */
+ UART_REG(fcr); /* 0x0c */
+ u8 mcr; /* 0x10 */
+ u8 lcr;
+ u16 __postpad;
+ UART_REG(lsr); /* 0x14 */
+ UART_REG(msr); /* 0x18 */
+ u32 __none1;
+ u32 __none2;
+ u16 dlr;
+ u16 __postpad2;
+};
+
+#define thr rbr
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_WLS_8 0x03/* 8 bit character length */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR0x01/* Data ready */
+#define UART_LSR_THRE 0x20/* Xmit holding register empty */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_serial_init(struct uniphier_serial *port)
+{
+ writeb(UART_LCR_WLS_8, port-lcr);
+
+#define MODE_X_DIV 16
+
+ /* Compute divisor value. Normally, we should simply return:
+* CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd-baudrate
+* but we need to round that value by adding 0.5.
+* Rounding is especially important at high baud rates.
+*/
+ writew((CONFIG_SYS_UNIPHIER_UART_CLK + (gd-baudrate *
+ (MODE_X_DIV / 2))) / (MODE_X_DIV * gd-baudrate), port-dlr);
+}
+
+static void uniphier_serial_setbrg(struct uniphier_serial *port)
+{
+ uniphier_serial_init(port);
+}
+
+static int uniphier_serial_tstc(struct uniphier_serial *port)
+{
+ return (readb(port-lsr) UART_LSR_DR) != 0;
+}
+
+static int uniphier_serial_getc(struct uniphier_serial *port)
+{
+ while (!uniphier_serial_tstc(port))
+ ;
+
+ return readb(port-rbr);
+}
+
+static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+{
+ if (c == '\n')
+ uniphier_serial_putc(port, '\r');
+
+ while (!(readb(port-lsr) UART_LSR_THRE))
+ ;
+
+ writeb(c, port-thr);
+}
+
+static struct uniphier_serial *serial_ports[4] = {
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
+ (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
+ (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
+ (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
+ (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
+#else
+ NULL,
+#endif
+};
+
+/* Multi serial device functions */
+#define
[U-Boot] [PATCH 5/6] arm: uniphier: add board entries to boards.cfg
Add board entries for Panasonic UniPhier family: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- boards.cfg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/boards.cfg b/boards.cfg index 8e2db82..cfe4498 100644 --- a/boards.cfg +++ b/boards.cfg @@ -376,6 +376,9 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poir...@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href- - +Active arm armv7 uniphier- none ph1_ld4 - Masahiro Yamada yamad...@jp.panasonic.com +Active arm armv7 uniphier- none ph1_pro4 - Masahiro Yamada yamad...@jp.panasonic.com +Active arm armv7 uniphier- none ph1_sld8 - Masahiro Yamada yamad...@jp.panasonic.com Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang b18...@freescale.com Active arm armv7 zynqxilinx zynq zynq_microzed - Michal Simek mon...@monstr.eu:Jagannadha Sutradharudu Teki jaga...@xilinx.com Active arm armv7 zynqxilinx zynq zynq_zc70x- Michal Simek mon...@monstr.eu:Jagannadha Sutradharudu Teki jaga...@xilinx.com -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] nand: denali: add Denali NAND driver for SPL
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Chin Liang See cl...@altera.com
Cc: Scott Wood scottw...@freescale.com
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/denali_spl.c | 201 ++
2 files changed, 202 insertions(+)
create mode 100644 drivers/mtd/nand/denali_spl.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f298f84..052c285 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_NAND_DOCG4) += docg4.o
else # minimal SPL drivers
+obj-$(CONFIG_NAND_DENALI) += denali_spl.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
new file mode 100644
index 000..6eed079
--- /dev/null
+++ b/drivers/mtd/nand/denali_spl.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include denali.h
+
+#define SPARE_ACCESS 0x41
+#define MAIN_ACCESS0x42
+
+#define BANK(x) ((x) 24)
+
+static void __iomem *denali_flash_mem =
+ (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+static void __iomem *denali_flash_reg =
+ (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+static const int flash_bank;
+static uint8_t page_buffer[NAND_MAX_PAGESIZE];
+static int page_size, oob_size, pages_per_block;
+
+static void index_addr(uint32_t address, uint32_t data)
+{
+ writel(address, denali_flash_mem + INDEX_CTRL_REG);
+ writel(data, denali_flash_mem + INDEX_DATA_REG);
+}
+
+static int wait_for_irq(uint32_t irq_mask)
+{
+ unsigned long timeout = 100;
+ uint32_t intr_status;
+
+ do {
+ intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
+
+ if (intr_status INTR_STATUS__ECC_UNCOR_ERR) {
+ debug(Uncorrected ECC detected\n);
+ return -EIO;
+ }
+
+ if (intr_status irq_mask)
+ break;
+
+ udelay(1);
+ timeout--;
+ } while (timeout);
+
+ if (!timeout) {
+ debug(Timeout with interrupt status %08x\n, intr_status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void read_data_from_flash_mem(uint8_t *buf, int len)
+{
+ int i;
+ uint32_t *buf32;
+
+ /* transfer the data from the flash */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i len / 4; i++)
+ *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
+}
+
+int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
+{
+ uint32_t addr, cmd;
+ static uint32_t page_count = 1;
+
+ writel(ecc_en, denali_flash_reg + ECC_ENABLE);
+
+ /* clear all bits of intr_status. */
+ writel(0x, denali_flash_reg + INTR_STATUS(flash_bank));
+
+ addr = BANK(flash_bank) | page;
+
+ /* setup the acccess type */
+ cmd = MODE_10 | addr;
+ index_addr(cmd, access_type);
+
+ /* setup the pipeline command */
+ index_addr(cmd, 0x2000 | page_count);
+
+ cmd = MODE_01 | addr;
+ writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
+
+ return wait_for_irq(INTR_STATUS__LOAD_COMP);
+}
+
+static int nand_read_oob(void *buf, int page)
+{
+ int ret;
+
+ ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
+ if (ret 0)
+ return ret;
+
+ read_data_from_flash_mem(buf, oob_size);
+
+ return 0;
+}
+
+static int nand_read_page(void *buf, int page)
+{
+ int ret;
+
+ ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
+ if (ret 0)
+ return ret;
+
+ read_data_from_flash_mem(buf, page_size);
+
+ return 0;
+}
+
+static int nand_block_isbad(int block)
+{
+ int ret;
+
+ ret = nand_read_oob(page_buffer, block * pages_per_block);
+ if (ret 0)
+ return ret;
+
+ return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+ /* access to main area */
+ writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
+
+ page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
+ oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
+ pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ int block, page,
[U-Boot] [PATCH 0/6] Add support for Panasonic UniPhier SoCs/boards
UniPhier is the SoC family developed by Panasonic Corporation, based on ARM Cortex-A9. This patch set adds its SoC/board support code with some drivers. This series depends on the Denali NAND driver patch: http://patchwork.ozlabs.org/patch/357717/ It must be applied first. Masahiro Yamada (6): nand: denali: add Denali NAND driver for SPL serial: add UniPhier serial driver arm: uniphier: add UniPhier SoC suppurt code arm: uniphier: add UniPhier config headers arm: uniphier: add board entries to boards.cfg git-mailrc: add me as the maintainer of UniPhier SoCs arch/arm/cpu/armv7/uniphier/Makefile | 23 + arch/arm/cpu/armv7/uniphier/board_common.c | 32 + arch/arm/cpu/armv7/uniphier/board_late_init.c | 37 + arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 +++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 + arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 ++ arch/arm/cpu/armv7/uniphier/dram_init.c| 37 + arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 arch/arm/cpu/armv7/uniphier/lowlevel_init.S| 159 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c| 42 + arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c|1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c |1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 + arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c| 168 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c| 75 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c| 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c|1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c |1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c |1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c| 201 .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c |1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c| 51 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c |1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c| 10 + arch/arm/cpu/armv7/uniphier/reset.c| 29 + arch/arm/cpu/armv7/uniphier/smp.S | 54 + arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 arch/arm/cpu/armv7/uniphier/timer.c| 39 + arch/arm/include/asm/arch-uniphier/arm-mpcore.h| 46 + arch/arm/include/asm/arch-uniphier/bcu-regs.h | 29 + arch/arm/include/asm/arch-uniphier/board.h | 35 + arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 ++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 107 ++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 arch/arm/include/asm/arch-uniphier/ssc-regs.h | 65 ++ boards.cfg |3 + doc/git-mailrc |2 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/denali_spl.c | 201 drivers/serial/Makefile|1 + drivers/serial/serial.c|2 + drivers/serial/serial_uniphier.c | 206 include/configs/ph1_ld4.h | 64 ++ include/configs/ph1_pro4.h | 66 ++ include/configs/ph1_sld8.h | 64 ++ include/configs/uniphier-common.h | 275 + 69 files changed, 4802 insertions(+) create mode 100644 arch/arm/cpu/armv7/uniphier/Makefile create mode 100644
Re: [U-Boot] [PATCH v4 04/12] board:samsung: check the boot device and init the right mmc driver.
Hi, Przemyslaw.
On 07/04/2014 05:07 PM, Przemyslaw Marczak wrote:
Hello Jaehoon,
On 07/04/2014 07:45 AM, Jaehoon Chung wrote:
Hi, Przemyslaw.
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to 0 in the most config cases.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes V3:
- separate two changes into two commits
Changes V4:
- board.c: add functions: init_mmc() and init_dwmmc()
- board_mmc_init(): call get_boot_mode()
---
board/samsung/common/board.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..4d3f216 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+static int init_mmc(void)
+{
+#ifdef CONFIG_SDHCI
+return exynos_mmc_init(gd-fdt_blob);
+#else
+return 0;
+#endif
+}
+
+static int init_dwmmc(void)
{
-int ret;
#ifdef CONFIG_DWMMC
-/* dwmmc initializattion for available channels */
-ret = exynos_dwmmc_init(gd-fdt_blob);
-if (ret)
-debug(dwmmc init failed\n);
+return exynos_dwmmc_init(gd-fdt_blob);
+#else
+return 0;
#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+int ret;
+
+if (get_boot_mode() == BOOT_MODE_MMC) {
+ret = init_mmc();
+ret |= init_dwmmc();
+} else {
+ret = init_dwmmc();
+ret |= init_mmc();
+}
Well, i have some confusion for this.
Did you consider the case like init_dwmmc() is succeed and init_mmc() is
failed?
it's hard to control the error for both.
Best Regards,
Jaehoon Chung
In our vendor init code, the value returned by this function has no
significant meaning since there is no implementation of function
cpu_mmc_init().
Ok..then ret value is used to just debug display, right?
Best Regards,
Jaehoon Chung
So checking this error is just for a debug purposes:
# if (ret)
#debug(mmc init failed\n);
and the returned value:
mmc | dwmmc - ret
0 | 1 - 1
1 | 0 - 1
1 | 1 - 1
0 | 0 - 0
So we have an error message on any error.
-#ifdef CONFIG_SDHCI
-/* mmc initializattion for available channels */
-ret = exynos_mmc_init(gd-fdt_blob);
if (ret)
debug(mmc init failed\n);
-#endif
+
return ret;
}
#endif
Thank you,
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH v4 10/12] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
On 07/04/2014 05:08 PM, Przemyslaw Marczak wrote:
On 07/04/2014 08:07 AM, Jaehoon Chung wrote:
On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to
800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Tom Rini tr...@ti.com
---
Changes v2:
- enable fan on odroid U3
Changes v3:
- odroid.c: clean up board name related code
- odroid.c: remove static from set_board_type()
- odroid.c: add implementation of functions: get_dfu_alt_*
- odroid.c: include misc.h
Changes v4:
odroid.c: dfu_get_alt_boot: add call get_boot_mode()
---
board/samsung/odroid/Makefile | 8 +
board/samsung/odroid/odroid.c | 466
++
board/samsung/odroid/setup.h | 227
3 files changed, 701 insertions(+)
create mode 100644 board/samsung/odroid/Makefile
create mode 100644 board/samsung/odroid/odroid.c
create mode 100644 board/samsung/odroid/setup.h
diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak p.marc...@samsung.com
+#
+# SPDX-License-Identifier:GPL-2.0+
+#
+
+obj-y:= odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 000..28706af
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak p.marc...@samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/pinmux.h
+#include asm/arch/power.h
+#include asm/arch/clock.h
+#include asm/arch/gpio.h
+#include asm/gpio.h
+#include asm/arch/cpu.h
+#include power/pmic.h
+#include power/max77686_pmic.h
+#include errno.h
+#include usb.h
+#include usb/s3c_udc.h
+#include samsung/misc.h
+#include setup.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+ODROID_TYPE_U3,
+ODROID_TYPE_X2,
+};
+
+void set_board_type(void)
+{
+int val;
+
+/* Check GPC1 pin 2 */
+gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
+gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
+gpio_direction_input(EXYNOS4X12_GPIO_C12);
+
+/* XCL205 - needs some latch time */
+mdelay(10);
+
+/* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+val = gpio_get_value(EXYNOS4X12_GPIO_C12);
+if (val)
val is unnecessary. int val can be removed.
if (gpio_get_value(EXYNS4x12_GPIO_C12))
ok
+gd-board_type = ODROID_TYPE_X2;
+else
+gd-board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_name(void)
+{
+const char *board_name = odroid;
Is there other approach or general method for getting board name?
Actually, the board name is the same as CONFIG_SYS_BOARD, but we are going to
have only one binary for Exynos 4 boards in the future - so such function is
welcome. We can also put this into the dts file.
In future...Then using dt-file would be better than this. :)
Best Regards,
Jaehoon Chung
+
+return board_name;
+}
+
+const char *get_board_type(void)
+{
+const char *board_type[] = {u3, x2};
+
+return board_type[gd-board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void)
+{
+return getenv(dfu_alt_system);
+}
+
+char *get_dfu_alt_boot(void)
+{
+char *alt_boot = NULL;
+
+switch (get_boot_mode()) {
+case BOOT_MODE_MMC:
+alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+break;
+default:
+alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+break;
+}
+
+if (!alt_boot)
+return NULL;
Is it need? alt_boot is set to CONFIG_DFU_ALT_BOOT_EMMC by default, isn't?
CONFIG_DFU_ALT_BOOT_EMMC is 0?
Oops, right. I must fix that.
+
+setenv(dfu_alt_boot, alt_boot);
+
+return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+samsung_get_base_clock();
+
+/*
+ * CMU_CPU clocks src to MPLL
+ * Bit values: 0 ; 1
+ * MUX_APLL_SEL:FIN_PLL ; FOUT_APLL
+ * MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
+ * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+ * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+*/
+clr_src_cpu =
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi all, (I hope gmail formats this mail according to the mailing list requirements, my apologies if it doesn't) On 4 July 2014 10:50, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Benoît, On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau benoit.thebaudeau@gmail.com wrote: Hi Albert, It makes sense to me. That should work, but it'd be better to avoid adding a custom linker script. A simple fix in vectors.S would be preferable if possible. Also, the __image_copy_start stuff should be taken care of with such a change. I do not intend to have this in a custom linker script; I want this to be in the common ARM SPL linker script (I hope it is what Helmut's TT-01 changes use) -- I also want to get rid of all custom linker scripts in the ARM par of U-Boot, but I could not get this done for 2014.07. I have access to i.MX31 board (PDK) and can definitely help testing any patch to this problem. However, I won't be able to do any verification until beginning of August. Regards, Magnus Lilja ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] ARM: LS1021A: enable ARMv7 virt support for LS1021A A7
On 07/04/2014 04:48 AM, Xiubo Li-B47053 wrote: diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d639a6f..f090971 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -18,6 +18,15 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_SOC_BIG_ENDIAN +#define CONFIG_DCFG_CCSR_SCRATCHRW10x01ee0200 +#define CONFIG_DCFG_CCSR_BRR 0x01ee00e4 Why are you hardcoding the register addresses in this file? I saw that all registers are defined in: arch/arm/include/asm/arch-ls102xa/config.h. Why are these special? No special, and I'll follow your advice. +#define CONFIG_SMP_PEN_ADDRCONFIG_DCFG_CCSR_SCRATCHRW1 +#define CONFIG_ARM_GIC_BASE_ADDRESS0x0140 Why do you need the GIC base address? Can't this be read from CBAR? I'm not very sure, I have tried, but failed, I will do some research later. What is not working? Is the address returned by CBAR wrong? Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] Add LS1021A-QDS/TWR Non-secure and HYP support.
On 07/04/2014 04:31 AM, Xiubo Li-B47053 wrote: This patch series depends on the following patch: [U-Boot,v4,03/10] ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe But we have HYP enabled. In this case why are the series dependent on this patch? Well, if the HYP is enabled, the host OS will use the Physical timer, and these CNTVOFFs could be cleared in kernel too. When and where to clear them is better ? In uboot or in kernel when needed? If HYP mode is available CNTVOFF is cleared in Linux. What I am trying to say is that it will work also without the patch you mentioned. Diana ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 1/3] mtd: nand: davinci: add opportunity to write keystone U-boot image
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.
The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.
The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.
Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/mtd/nand/davinci_nand.c | 196
include/configs/k2hk_evm.h | 4 +-
2 files changed, 199 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 5d42509..a079b1e 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -305,6 +305,189 @@ static struct nand_ecclayout
nand_davinci_4bit_layout_oobfirst = {
#endif
};
+#if defined CONFIG_KEYSTONE_RBL_NAND
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
+static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
+ .eccbytes = 40,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ },
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+ .eccbytes = 80,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
+ 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ {.offset = 64, .length = 6, },
+ {.offset = 80, .length = 6, },
+ {.offset = 96, .length = 6, },
+ {.offset = 112, .length = 6, },
+ },
+#endif
+};
+
+#ifdef CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE 11
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE 12
+#endif
+
+/**
+ * nand_davinci_write_page - write one page
+ * @mtd: MTD device structure
+ * @chip: NAND chip descriptor
+ * @buf: the data to write
+ * @oob_required: must write chip-oob_poi to OOB
+ * @page: page number to write
+ * @cached: cached programming
+ * @raw: use _raw version of write_page
+ */
+static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip
*chip,
+ const uint8_t *buf, int oob_required,
+ int page, int cached, int raw)
+{
+ int status;
+ int ret = 0;
+ struct nand_ecclayout *saved_ecc_layout;
+
+ /* save current ECC layout and assign Keystone RBL ECC layout */
+ if (page CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
+ saved_ecc_layout = chip-ecc.layout;
+ chip-ecc.layout = nand_keystone_rbl_4bit_layout_oobfirst;
+ mtd-oobavail = chip-ecc.layout-oobavail;
+ }
+
+ chip-cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+ if (unlikely(raw))
+ status = chip-ecc.write_page_raw(mtd, chip, buf, oob_required);
+ else
+ status = chip-ecc.write_page(mtd, chip, buf, oob_required);
+
+ if (status 0) {
+ ret = status;
+ goto err;
+ }
+
+ chip-cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip-waitfunc(mtd, chip);
+
+ /*
+* See if operation failed and additional status checks are
+* available.
+*/
+ if ((status NAND_STATUS_FAIL) (chip-errstat))
+ status = chip-errstat(mtd, chip, FL_WRITING, status, page);
+
+
[U-Boot] [U-boot] [Patch v2 0/3] Add support for NAND U-boot image upgrade
This series adds opportunity to write U-boot image on AEMIF NAND device using standard nand u-boot commands. Also added script to automate this process. This series is logical continue of [U-boot] [Patch v3 0/3] keystone: nand: add additional nand ecclayout series (http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/189378). For more informations see: http://www.ti.com/lit/ug/spruhj3/spruhj3.pdf Based on u-boot-ti.git master v2..v1: k2hk_evm: add script to automate NAND flash process - include NAND boot under the section Supported boot modes: in README Ivan Khoronzhuk (3): mtd: nand: davinci: add opportunity to write keystone U-boot image keystone: add support for NAND gpheader image k2hk_evm: add script to automate NAND flash process Makefile| 6 ++ board/ti/k2hk_evm/README| 28 +- drivers/mtd/nand/davinci_nand.c | 196 include/configs/k2hk_evm.h | 8 +- 4 files changed, 235 insertions(+), 3 deletions(-) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-boot] [Patch v2 3/3] k2hk_evm: add script to automate NAND flash process
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
board/ti/k2hk_evm/README | 28 +++-
include/configs/k2hk_evm.h | 4 +++-
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README
index bfeb05b..7426b8d 100644
--- a/board/ti/k2hk_evm/README
+++ b/board/ti/k2hk_evm/README
@@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h
Supported boot modes:
- SPI NOR boot
+ - AEMIF NAND boot
Supported image formats:-
- u-boot.bin: for loading and running u-boot.bin through Texas instruments
code composure studio (CCS)
- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
Build instructions:
===
@@ -55,6 +57,10 @@ To build u-boot-spi.gph
make k2hk_evm_config
make u-boot-spi.gph
+To build u-boot-nand.gph
+ make k2hk_evm_config
+ make u-boot-nand.gph
+
Load and Run U-Boot on K2HK EVM using CCS
=
@@ -115,8 +121,28 @@ instructions:-
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x8700
setenv filesize size in hex of u-boot-spi.gph rounded to hex 0x1
- run burn_uboot
+ run burn_uboot_spi
Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to SPI Little Endian Boot mode as per instruction at
http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+==
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run - Suspend from top level menu
+ CortexA15_1 (Free Running)
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x8700
+ through CCS as described in step 2 of Load and Run U-Boot on K2HK EVM
+ using CCS, but using address 0x8700.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv filesize size in hex of u-boot-nand.gph rounded to hex 0x1
+ run burn_uboot_nand
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to ARM NAND Boot mode as per instruction at
+ http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 3f87741..63e0249 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -221,8 +221,10 @@
get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0 \
get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0 \
get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0 \
- burn_uboot=sf probe; sf erase 0 0x10; \
+ burn_uboot_spi=sf probe; sf erase 0 0x10; \
sf write ${addr_uboot} 0 ${filesize}\0\
+ burn_uboot_nand=nand erase 0 0x10;\
+ nand write ${addr_uboot} 0 ${filesize}\0 \
args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0 \
args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs \
root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0 \
--
1.8.3.2
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[U-Boot] [U-boot] [Patch v2 2/3] keystone: add support for NAND gpheader image
Add support for NAND gpheader image. TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the nand u-boot image. So add zeros at the end of the nand gph image. Acked-by: Murali Karicheri m-kariche...@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com --- Makefile | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Makefile b/Makefile index 966fd14..76a712e 100644 --- a/Makefile +++ b/Makefile @@ -937,6 +937,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot +u-boot-nand.gph: u-boot.bin FORCE + $(call if_changed,mkimage) + @dd if=/dev/zero bs=8 count=1 2/dev/null $@ + ifneq ($(CONFIG_SUNXI),) OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v1 2/4] armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Hi York,
I spotted a couple of generic issues below. Most of these are issues
with the existing code that you happen to be moving around, rather than
with the new code this patch introduces.
There are a couple of gotchas around secondary startup that are painful
with the bootwrapper for arm64 at present, and I think that we can avoid
them by construction for U-Boot. More on that below.
On Fri, Jun 27, 2014 at 05:54:08PM +0100, York Sun wrote:
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. If a single
release address is needed, defining macro CONFIG_FSL_SMP_RELEASE_ALL
will use the CPU_RELEASE_ADDR. Spin table and the boot page is reserved
in device tree so OS won't overwrite.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Arnab Basu arnab.b...@freescale.com
---
This set depends on this bundle
http://patchwork.ozlabs.org/bundle/yorksun/armv8_fsl-lsch3/
arch/arm/cpu/armv8/fsl-lsch3/Makefile |2 +
arch/arm/cpu/armv8/fsl-lsch3/cpu.c| 13 ++
arch/arm/cpu/armv8/fsl-lsch3/cpu.h|1 +
arch/arm/cpu/armv8/fsl-lsch3/fdt.c| 56 +++
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 119 +++---
arch/arm/cpu/armv8/fsl-lsch3/mp.c | 171
+
arch/arm/cpu/armv8/fsl-lsch3/mp.h | 36 +
arch/arm/cpu/armv8/transition.S | 63 +---
arch/arm/include/asm/arch-fsl-lsch3/config.h |3 +-
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 35 +
arch/arm/include/asm/macro.h | 81 ++
arch/arm/lib/gic_64.S | 10 +-
common/board_f.c |2 +-
13 files changed, 502 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c
create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h
[...]
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
new file mode 100644
index 000..cd34e16
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include libfdt.h
+#include fdt_support.h
+#include mp.h
+
+#ifdef CONFIG_MP
+void ft_fixup_cpu(void *blob)
+{
+ int off;
+ __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
+ u64 *reg;
+ u64 val;
+
+ off = fdt_node_offset_by_prop_value(blob, -1, device_type, cpu,
4);
+ while (off != -FDT_ERR_NOTFOUND) {
+ reg = (u64 *)fdt_getprop(blob, off, reg, 0);
+ if (reg) {
+ val = spin_tbl_addr;
+#ifndef CONFIG_FSL_SMP_RELEASE_ALL
+ val += id_to_core(fdt64_to_cpu(*reg)) *
SIZE_BOOT_ENTRY;
In Linux we read /cpus/#address-cells to determine the size of a
CPU's reg property (and have dts where this is 1 cell). Will the above
work for that?
+#endif
+ val = cpu_to_fdt64(val);
+ fdt_setprop_string(blob, off, enable-method,
+ spin-table);
+ fdt_setprop(blob, off, cpu-release-addr,
+ val, sizeof(val));
+ } else {
+ puts(cpu NULL\n);
+ }
+ off = fdt_node_offset_by_prop_value(blob, off, device_type,
+ cpu, 4);
+ }
+ /*
+* Boot page and spin table can be reserved here if not done staticlly
+* in device tree.
+*
+* fdt_add_mem_rsv(blob, bootpg,
+* *((u64 *)(__secondary_boot_page_size)));
+* If defined CONFIG_FSL_SMP_RELEASE_ALL, the release address should
+* also be reserved.
+*/
I think that this reservation should _always_ be added by U-Boot unless
specifically overridden.
A problem I had with the arm64 bootwrapper when adding PSCI support and
now (as I am moving stuff about) was that the DTS in the kernel tree had
a memreserve out-of-sync with what the wrapper actually needed. While I
can add a new reservation, I can't remove any in case they are for
something else, so I end up protecting too much, wasting memory.
Given that the reservation is to protect data which U-Boot is in control
of choosing the address for, I think the only sane thing to do is for
U-Boot to always add the reservation.
That way U-Boot can change and existing DTBs will just work. We won't
end up protecting too much or too little.
[...]
@@ -119,3 +107,94 @@ ENTRY(lowlevel_init)
mov lr, x29 /* Restore
Re: [U-Boot] [PATCH] kirkwood: define empty CONFIG_MVGBE_PORTS by default
-Original Message-
From: Luka Perkov [mailto:l...@openwrt.org]
Sent: 02 July 2014 05:48
To: u-boot@lists.denx.de
Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
Subject: [PATCH] kirkwood: define empty
CONFIG_MVGBE_PORTS by default
Each board with defines it's own set of values. If we
do not define
CONFIG_MVGBE_PORTS we will hit following error:
mvgbe.c: In function 'mvgbe_initialize':
mvgbe.c:700:34: error: 'CONFIG_MVGBE_PORTS' undeclared
(first use in this function)
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
This patch fixes above described problem.
Signed-off-by: Luka Perkov l...@openwrt.org
CC: Prafulla Wadaskar prafu...@marvell.com
CC: Stefan Roese s...@denx.de
---
drivers/net/mvgbe.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 0cd06b6..d558f59 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -35,6 +35,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_MVGBE_PORTS
+# define CONFIG_MVGBE_PORTS {0, 0}
+#endif
+
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers
*)MVGBE0_BASE)-smi)
This is generic to network driver, to be picked up by net custodian..
+Joe
Acked-by: Prafulla Wadaskar prafu...@marvell.com
Regards...
Prafulla . . .
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Re: [U-Boot] [PATCH] kirkwood: ib62x0: add CONFIG_SYS_GENERIC_BOARD define
-Original Message- From: Luka Perkov [mailto:l...@openwrt.org] Sent: 02 July 2014 05:48 To: u-boot@lists.denx.de Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese Subject: [PATCH] kirkwood: ib62x0: add CONFIG_SYS_GENERIC_BOARD define Signed-off-by: Luka Perkov l...@openwrt.org CC: Prafulla Wadaskar prafu...@marvell.com CC: Stefan Roese s...@denx.de --- include/configs/ib62x0.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 186fd35..cd38577 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -9,6 +9,8 @@ #ifndef _CONFIG_IB62x0_H #define _CONFIG_IB62x0_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- Acked-By: Prafulla Wadaskar prafu...@marvell.com Will be pulled latter. Regards... Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] kirkwood: cosmetic: style fixes in kwbimage.cfg files
-Original Message- From: Luka Perkov [mailto:l...@openwrt.org] Sent: 02 July 2014 05:47 To: u-boot@lists.denx.de Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese Subject: [PATCH] kirkwood: cosmetic: style fixes in kwbimage.cfg files When diffing through the various kwbimage.cfg files only show relevant changes. Signed-off-by: Luka Perkov l...@openwrt.org CC: Prafulla Wadaskar prafu...@marvell.com CC: Stefan Roese s...@denx.de --- board/iomega/iconnect/kwbimage.cfg | 4 ++-- board/raidsonic/ib62x0/kwbimage.cfg | 22 +++-- - 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg index 3c63a03..f4260fa 100644 --- a/board/iomega/iconnect/kwbimage.cfg +++ b/board/iomega/iconnect/kwbimage.cfg @@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, @@ -87,7 +87,7 @@ DATA 0xffd0141c 0x0c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery +# bit11-9: 0x6, auto-precharge write recovery # bit12:0x0, PD must be zero # bit31-13: 0x0, required diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg index 596071f..ec00c15 100644 --- a/board/raidsonic/ib62x0/kwbimage.cfg +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -11,7 +11,7 @@ # # Boot Media configurations -BOOT_FROMnand# change from nand to uart if building UART image +BOOT_FROMnand NAND_ECC_MODEdefault NAND_PAGE_SIZE 0x0800 @@ -21,12 +21,12 @@ NAND_PAGE_SIZE0x0800 # Configure RGMII-0 interface pad voltage to 1.8V DATA 0xffd100e0 0x1b1b1b9b -#Dram initalization for SINGLE x16 CL=5 @ 400MHz +# Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xffd01400 0x43000c30 # DDR Configuration register # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) # bit23-14: 0x0, -# bit24:0x1, enable exit self refresh mode on DDR access -# bit25:0x1, required +# bit24:0x1, enable exit self refresh mode on DDR access +# bit25:0x1, required # bit29-26: 0x0, # bit31-30: 0x1, @@ -64,10 +64,10 @@ DATA 0xffd01410 0x000c# DDR Address Control # bit3-2: 11, Cs0size (1Gb) # bit5-4: 00, Cs1width (x8) # bit7-6: 11, Cs1size (1Gb) -# bit9-8: 00, Cs2width (nonexistent -# bit11-10: 00, Cs2size (nonexistent -# bit13-12: 00, Cs3width (nonexistent -# bit15-14: 00, Cs3size (nonexistent +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) # bit16:0, Cs0AddrSel # bit17:0, Cs1AddrSel # bit18:0, Cs2AddrSel @@ -88,7 +88,7 @@ DATA 0xffd0141c 0x0c52 # DDR Mode # bit6-4: 0x4, CL=5 # bit7: 0x0, TestMode=0 normal # bit8: 0x0, DLL reset=0 normal -# bit11-9: 0x6, auto-precharge write recovery +# bit11-9: 0x6, auto-precharge write recovery # bit12:0x0, PD must be zero # bit31-13: 0x0, required @@ -148,8 +148,8 @@ DATA 0xffd0149c 0xe803# CPU ODT Control DATA 0xffd01480 0x0001 # DDR Initialization Control # bit0: 0x1, enable DDR init upon this register write -DATA 0xFFD20134 0x # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x # L2 RAM Timing 1 Register +DATA 0xffd20134 0x # L2 RAM Timing 0 Register +DATA 0xffd20138 0x # L2 RAM Timing 1 Register # End of Header extension DATA 0x0 0x0 -- Acked-By: Prafulla Wadaskar prafu...@marvell.com Will be pulled latter. Regards... Prafulla . . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 1/9] exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-exynos/system.h |1 +
board/samsung/common/board.c | 15 +++
drivers/video/exynos_fb.c | 17 +
include/configs/exynos5250-dt.h |2 --
include/configs/s5pc210_universal.h |3 ---
include/configs/trats.h |3 ---
include/configs/trats2.h |3 ---
7 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 7e2057c..4968d3d 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -39,5 +39,6 @@ struct exynos5_sysreg {
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
+int exynos_lcd_early_init(const void *blob);
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 9dc7c83..1f6f0a0 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -20,6 +20,7 @@
#include asm/arch/mmc.h
#include asm/arch/pinmux.h
#include asm/arch/power.h
+#include asm/arch/system.h
#include power/pmic.h
#include asm/arch/sromc.h
#include lcd.h
@@ -148,6 +149,20 @@ int board_early_init_f(void)
board_i2c_init(gd-fdt_blob);
#endif
+#if defined(CONFIG_OF_CONTROL) defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd-fdt_blob);
+ if (err) {
+ debug(LCD early init failed\n);
+ return err;
+ }
+#endif
+
return exynos_early_init_f();
}
#endif
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index e1e0d80..bc478a9 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-/*
- * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
- * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
- * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
- * is called. So, we are forced to statically assign it.
- */
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
- .vl_col = LCD_XRES,
- .vl_row = LCD_YRES,
- .vl_bpix = LCD_COLOR16,
+ /* Insert a value here so that we don't end up in the BSS
+* Reference: drivers/video/tegra.c
+*/
+ .vl_col = -1,
};
#endif
@@ -141,7 +136,7 @@ static void lcd_panel_on(vidinfo_t *vid)
}
#ifdef CONFIG_OF_CONTROL
-int exynos_fimd_parse_dt(const void *blob)
+int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
@@ -286,8 +281,6 @@ void lcd_ctrl_init(void *lcdbase)
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
- if (exynos_fimd_parse_dt(gd-fdt_blob))
- debug(Can't get proper panel info\n);
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(panel_info);
#endif
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 74e72a5..c24984b 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -61,8 +61,6 @@
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
-#define LCD_XRES 2560
-#define LCD_YRES 1600
#define LCD_BPPLCD_COLOR16
#endif
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index eb046cd..20985da 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -247,7 +247,4 @@ int universal_spi_read(void);
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 480
-#define LCD_YRES 800
-
#endif /* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 90f1962..35c1feb 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -261,7 +261,4 @@
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
-#define LCD_XRES 720
-#define
[U-Boot] [PATCH V3 0/9] peach_pit: Add support for FIMD, DP and parade chip
Patchset V1: https://www.mail-archive.com/u-boot@lists.denx.de/msg140596.html Patchset V2: https://www.mail-archive.com/u-boot@lists.denx.de/msg141203.html Changes from V1: [PATCH V2 3/10] : Don't mix cpu_is and proid_isas per Minkyu's suggestion. Also, incorporate Simon's suggestion of not using else. [PATCH V2 4/10] : For FIMD SYSMMU DT, use same compatible string as kernel. [TEST_ONLY V2 6/10]: Make this patch TEST_ONLY Changes from V2: [PATCH V3 5/9] : Use SPDX tags to define the license for the file: parade.c Removed TEST_ONLY patches. Ajay Kumar (8): [PATCH V3 1/9] exynos_fb: Remove usage of static defines [PATCH V3 2/9] arm: exynos: Add RPLL for Exynos5420 [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH V3 6/9] ARM: exynos: Add missing declaration for gpio_direction_input [PATCH V3 7/9] exynos5420: add callbacks needed for exynos_fb driver [PATCH V3 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip [PATCH V3 9/9] CONFIGS: peach-pit: Enable display for peach_pit board Vadim Bendebury (1): [PATCH V3 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge arch/arm/cpu/armv7/exynos/clock.c | 83 - arch/arm/cpu/armv7/exynos/clock_init.h |3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 ++ arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +- arch/arm/dts/exynos5420-peach-pit.dts | 30 arch/arm/dts/exynos54xx.dtsi | 10 ++ arch/arm/include/asm/arch-exynos/clk.h |1 + arch/arm/include/asm/arch-exynos/gpio.h|1 + arch/arm/include/asm/arch-exynos/system.h |4 + board/samsung/common/board.c | 15 ++ board/samsung/smdk5420/smdk5420.c | 129 +- doc/device-tree-bindings/video/exynos-fb.txt |6 + drivers/video/Makefile |1 + drivers/video/exynos_fb.c | 17 +- drivers/video/exynos_fimd.c| 43 + drivers/video/parade.c | 220 include/configs/exynos5250-dt.h|2 - include/configs/peach-pit.h| 10 ++ include/configs/s5pc210_universal.h|3 - include/configs/trats.h|3 - include/configs/trats2.h |3 - include/fdtdec.h |2 + lib/fdtdec.c |2 + 23 files changed, 492 insertions(+), 111 deletions(-) create mode 100644 drivers/video/parade.c -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 2/9] arm: exynos: Add RPLL for Exynos5420
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/exynos/clock_init.h |3 +++
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +
2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h
b/arch/arm/cpu/armv7/exynos/clock_init.h
index a875d0b..fce502f 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init.h
+++ b/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -75,6 +75,9 @@ struct mem_timings {
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
+ unsigned rpll_mdiv;
+ unsigned rpll_pdiv;
+ unsigned rpll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index 1d6977f..b6a9bc1 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -179,6 +179,10 @@ struct mem_timings mem_timings[] = {
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
+ /* RPLL @70.5Mhz */
+ .rpll_mdiv = 0x5E,
+ .rpll_pdiv = 0x2,
+ .rpll_sdiv = 0x4,
.direct_cmd_msr = {
0x00020018, 0x0003, 0x00010046, 0x0d70,
@@ -800,6 +804,7 @@ static void exynos5420_system_clock_init(void)
writel(mem-ipll_pdiv * PLL_LOCK_FACTOR, clk-ipll_lock);
writel(mem-spll_pdiv * PLL_LOCK_FACTOR, clk-spll_lock);
writel(mem-kpll_pdiv * PLL_LOCK_FACTOR, clk-kpll_lock);
+ writel(mem-rpll_pdiv * PLL_X_LOCK_FACTOR, clk-rpll_lock);
setbits_le32(clk-src_cpu, MUX_HPM_SEL_MASK);
@@ -898,6 +903,14 @@ static void exynos5420_system_clock_init(void)
while ((readl(clk-spll_con0) PLL_LOCKED) == 0)
;
+ /* Set RPLL */
+ writel(RPLL_CON2_VAL, clk-rpll_con2);
+ writel(RPLL_CON1_VAL, clk-rpll_con1);
+ val = set_pll(mem-rpll_mdiv, mem-rpll_pdiv, mem-rpll_sdiv);
+ writel(val, clk-rpll_con0);
+ while ((readl(clk-rpll_con0) PLL_LOCKED) == 0)
+ ;
+
writel(CLK_DIV_CDREX0_VAL, clk-div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, clk-div_cdrex1);
--
1.7.9.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 3/9] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/exynos/clock.c | 83 +++--
arch/arm/cpu/armv7/exynos/exynos5_setup.h |2 +-
arch/arm/include/asm/arch-exynos/clk.h|1 +
3 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 400d134..c8be39b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
r = readl(clk-rpll_con0);
k = readl(clk-rpll_con1);
break;
+ case SPLL:
+ r = readl(clk-spll_con0);
+ break;
default:
printf(Unsupported PLL (%d)\n, pllreg);
return 0;
@@ -1027,6 +1031,40 @@ static unsigned long exynos5_get_lcd_clk(void)
return pclk;
}
+static unsigned long exynos5420_get_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ sel = readl(clk-src_disp10);
+ sel = (1 4);
+
+ if (sel)
+ sclk = get_pll_clk(SPLL);
+ else
+ sclk = get_pll_clk(RPLL);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ ratio = readl(clk-div_disp10);
+ ratio = ratio 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
@@ -1131,6 +1169,33 @@ void exynos5_set_lcd_clk(void)
clrsetbits_le32(clk-div_disp1_0, 0xf, 0x0);
}
+void exynos5420_set_lcd_clk(void)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned int cfg;
+
+ /*
+* CLK_SRC_DISP10
+* FIMD1_SEL [4]
+* 0: SCLK_RPLL
+* 1: SCLK_SPLL
+*/
+ cfg = readl(clk-src_disp10);
+ cfg = ~(0x1 4);
+ cfg |= (0 4);
+ writel(cfg, clk-src_disp10);
+
+ /*
+* CLK_DIV_DISP10
+* FIMD1_RATIO [3:0]
+*/
+ cfg = readl(clk-div_disp10);
+ cfg = ~(0xf 0);
+ cfg |= (0 0);
+ writel(cfg, clk-div_disp10);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
@@ -1602,16 +1667,24 @@ unsigned long get_lcd_clk(void)
{
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
- else
- return exynos5_get_lcd_clk();
+ else {
+ if (proid_is_exynos5420())
+ return exynos5420_get_lcd_clk();
+ else
+ return exynos5_get_lcd_clk();
+ }
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
- else
- exynos5_set_lcd_clk();
+ else {
+ if (proid_is_exynos5250())
+ exynos5_set_lcd_clk();
+ if (proid_is_exynos5420())
+ exynos5420_set_lcd_clk();
+ }
}
void set_mipi_clk(void)
diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 3242093..2eea48a 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -783,7 +783,7 @@
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x
#define CLK_SRC_TOP4_VAL 0x0111
-#define CLK_SRC_TOP5_VAL 0x1100
+#define CLK_SRC_TOP5_VAL 0x1101
#define CLK_SRC_TOP6_VAL 0x0111
#define CLK_SRC_TOP7_VAL 0x00022200
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index ffbc07e..db24dc0 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -15,6 +15,7 @@
#define VPLL 4
#define BPLL 5
#define RPLL 6
+#define SPLL 7
#define MASK_PRE_RATIO(x) (0xff ((x 4) + 8))
#define MASK_RATIO(x) (0xf (x 4))
--
[U-Boot] [PATCH V3 4/9] video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
on state by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/dts/exynos54xx.dtsi | 10 ++
doc/device-tree-bindings/video/exynos-fb.txt |6
drivers/video/exynos_fimd.c | 43 ++
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
5 files changed, 61 insertions(+)
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index b9f8e0b..c21d798 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -113,6 +113,16 @@
status = disabled;
};
+ fimdm0_sysmmu@0x1464 {
+ compatible = samsung,sysmmu-v3.3;
+ reg = 0x1464 0x100;
+ };
+
+ fimdm1_sysmmu@0x1468 {
+ compatible = samsung,sysmmu-v3.3;
+ reg = 0x1468 0x100;
+ };
+
fimd@1440 {
/* sysmmu is not used in U-Boot */
samsung,disable-sysmmu;
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt
b/doc/device-tree-bindings/video/exynos-fb.txt
index bb7441c..dc4e44f 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -55,6 +55,12 @@ Board(panel specific):
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
+ samsung,disable-sysmmu: Define this if you want to disable FIMD sysmmu.
+ (needed for Exynos5420 and newer versions)
+ Add the required FIMD sysmmu nodes to be
+ disabled with compatible string
+ samsung,sysmmu-v3.3, with a reg property
+ holding the register address of FIMD sysmmu.
Example:
SOC specific part:
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index cebbba7..f67fa81 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,6 +251,45 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, fimd_ctrl-winshmap);
}
+#ifdef CONFIG_OF_CONTROL
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+ u32 *sysmmufimd;
+ unsigned int node;
+ int node_list[2];
+ int count;
+ int i;
+
+ count = fdtdec_find_aliases_for_id(gd-fdt_blob, fimd,
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+ for (i = 0; i count; i++) {
+ node = node_list[i];
+ if (node = 0) {
+ debug(Can't get device node for fimd sysmmu\n);
+ return;
+ }
+
+ sysmmufimd = (u32 *)fdtdec_get_addr(gd-fdt_blob, node, reg);
+ if (!sysmmufimd) {
+ debug(Can't get base address for sysmmu fimdm0);
+ return;
+ }
+
+ writel(0x0, sysmmufimd);
+ }
+}
+#endif
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
@@ -268,6 +307,10 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
node, reg);
if (fimd_ctrl == NULL)
debug(Can't get the FIMD base address\n);
+
+ if (fdtdec_get_bool(gd-fdt_blob, node, samsung,disable-sysmmu))
+ exynos_fimd_disable_sysmmu();
+
#else
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index a7e6ee7..a583d68 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -94,6 +94,7 @@ enum fdt_compat_id {
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
+ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index aaa6620..64d2398 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -68,6 +68,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SANDBOX_LCD_SDL, sandbox,lcd-sdl),
COMPAT(TI_TPS65090,
[U-Boot] [PATCH V3 5/9] video: Add driver for Parade PS8625 dP to LVDS bridge
From: Vadim Bendebury vben...@chromium.org
The initialization table comes from the Illustration of I2C command
for initialing PS8625 document supplied by Parade.
Signed-off-by: Vadim Bendebury vben...@chromium.org
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
drivers/video/Makefile |1 +
drivers/video/parade.c | 220
include/fdtdec.h |1 +
lib/fdtdec.c |1 +
4 files changed, 223 insertions(+)
create mode 100644 drivers/video/parade.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..8618590 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
+obj-$(CONFIG_VIDEO_PARADE) += parade.o
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
new file mode 100644
index 000..0f543f6
--- /dev/null
+++ b/drivers/video/parade.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This file is a driver for Parade dP-LVDS bridges. The original submission
+ * is for the ps8625 chip.
+ */
+#include config.h
+#include common.h
+#include i2c.h
+#include fdtdec.h
+
+/*
+ * Initialization of the chip is a process of writing certaing values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, only address offset is
+ * stored in the table below.
+ */
+/**
+ * struct reg_data() - data for a parade register write
+ *
+ * @addr_offoffset from the i2c base address for parade
+ * @reg_addrregister address to write
+ * @value value to be written
+ */
+struct reg_data {
+ uint8_t addr_off;
+ uint8_t reg;
+ uint8_t value;
+} _packed;
+
+#define END_OF_TABLE 0xff /* Ficticious offset */
+
+static const struct reg_data parade_values[] = {
+ {0x02, 0xa1, 0x01}, /* HPD low */
+/*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ {0x04, 0x14, 0x01},
+/*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ {0x04, 0xe3, 0x20},
+ {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
+/*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ {0x04, 0x8a, 0x0c},
+ {0x04, 0x89, 0x08}, /* [3] RFD always on */
+/*
+ * CTN lock in/out:
+ * 2ppm/8ppm. Lock out 2
+ * times.
+ */
+ {0x04, 0x71, 0x2d},
+/*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ {0x04, 0x7d, 0x07},
+ {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
+ {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
+/*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ {0x04, 0xc0, 0x12},
+ {0x04, 0xc1, 0x92}, /* Gitune=-37% */
+ {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
+ {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
+/*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ {0x04, 0x00, 0xb0},
+/*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ {0x04, 0x15, 0x40},
+/* EQ Training State Machine Setting */
+ {0x04, 0x54, 0x10}, /* RCO calibration start */
+/* [4:0] MAX_LANE_COUNT set to one lane */
+ {0x01, 0x02, 0x81},
+/* [4:0] LANE_COUNT_SET set to one lane */
+ {0x01, 0x21, 0x81},
+ {0x00, 0x52, 0x20},
+ {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
+ {0x00, 0x62, 0x41},
+/* Counter number, add 1ms counter delay */
+ {0x00, 0xf6, 0x01},
+/*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ {0x00, 0x77, 0x06},
+/*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ {0x00, 0x4c, 0x04},
+/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ {0x01, 0xc0, 0x00},
+ {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
+ {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
+/*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ {0x01, 0xc3, 0x44},
+ {0x01, 0xc4, 0x32}, /* DPCD404 */
+ {0x01, 0xc5, 0x53},
[U-Boot] [PATCH V3 6/9] ARM: exynos: Add missing declaration for gpio_direction_input
This patch adds missing declaration for gpio_direction_input
function, thereby helps in resolving compilation warnings.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index be5113f..8fb5c23 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1504,6 +1504,7 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
+int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
--
1.7.9.5
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[U-Boot] [PATCH V3 7/9] exynos5420: add callbacks needed for exynos_fb driver
Add initialization code for peach_pit panel, parade bridge chip,
and backlight.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/arm/include/asm/arch-exynos/system.h |3 +
board/samsung/smdk5420/smdk5420.c | 129 +++--
2 files changed, 50 insertions(+), 82 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/system.h
b/arch/arm/include/asm/arch-exynos/system.h
index 4968d3d..320763f 100644
--- a/arch/arm/include/asm/arch-exynos/system.h
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -41,4 +41,7 @@ void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);
+/* Initialize the Parade dP-LVDS bridge if present */
+int parade_init(const void *blob);
+
#endif /* _EXYNOS4_SYSTEM_H */
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 183c522..270ee83 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -10,11 +10,14 @@
#include i2c.h
#include lcd.h
#include spi.h
+#include errno.h
#include asm/arch/board.h
#include asm/arch/cpu.h
#include asm/arch/gpio.h
#include asm/arch/pinmux.h
+#include asm/arch/system.h
#include asm/arch/dp_info.h
+#include power/tps65090_pmic.h
DECLARE_GLOBAL_DATA_PTR;
@@ -40,95 +43,57 @@ int exynos_init(void)
}
#ifdef CONFIG_LCD
-void cfg_lcd_gpio(void)
+static int has_edp_bridge(void)
{
- /* For Backlight */
- gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+ int node;
+
+ node = fdtdec_next_compatible(gd-fdt_blob, 0, COMPAT_PARADE_PS8625);
- /* LCD power on */
- gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
- gpio_set_value(EXYNOS5420_GPIO_X15, 1);
+ /* No node for bridge in device tree. */
+ if (node = 0)
+ return 0;
- /* Set Hotplug detect for DP */
- gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
+ /* Default is with bridge ic */
+ return 1;
}
-vidinfo_t panel_info = {
- .vl_freq= 60,
- .vl_col = 2560,
- .vl_row = 1600,
- .vl_width = 2560,
- .vl_height = 1600,
- .vl_clkp= CONFIG_SYS_LOW,
- .vl_hsp = CONFIG_SYS_LOW,
- .vl_vsp = CONFIG_SYS_LOW,
- .vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle on LCD */
-
- /* wDP panel timing infomation */
- .vl_hspw= 32,
- .vl_hbpd= 80,
- .vl_hfpd= 48,
-
- .vl_vspw= 6,
- .vl_vbpd= 37,
- .vl_vfpd= 3,
- .vl_cmd_allow_len = 0xf,
-
- .win_id = 3,
- .cfg_gpio = cfg_lcd_gpio,
- .backlight_on = NULL,
- .lcd_power_on = NULL,
- .reset_lcd = NULL,
- .dual_lcd_enabled = 0,
-
- .init_delay = 0,
- .power_on_delay = 0,
- .reset_delay= 0,
- .interface_mode = FIMD_RGB_INTERFACE,
- .dp_enabled = 1,
-};
-
-static struct edp_device_info edp_info = {
- .disp_info = {
- .h_res = 2560,
- .h_sync_width = 32,
- .h_back_porch = 80,
- .h_front_porch = 48,
- .v_res = 1600,
- .v_sync_width = 6,
- .v_back_porch = 37,
- .v_front_porch = 3,
- .v_sync_rate = 60,
- },
- .lt_info = {
- .lt_status = DP_LT_NONE,
- },
- .video_info = {
- .master_mode = 0,
- .bist_mode = DP_DISABLE,
- .bist_pattern = NO_PATTERN,
- .h_sync_polarity = 0,
- .v_sync_polarity = 0,
- .interlaced = 0,
- .color_space = COLOR_RGB,
- .dynamic_range = VESA,
- .ycbcr_coeff = COLOR_YCBCR601,
- .color_depth = COLOR_8,
- },
-};
-
-static struct exynos_dp_platform_data dp_platform_data = {
- .phy_enable = set_dp_phy_ctrl,
- .edp_dev_info = edp_info,
-};
-
-void init_panel_info(vidinfo_t *vid)
+void exynos_lcd_power_on(void)
{
- vid-rgb_mode = MODE_RGB_P;
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret 0) {
+ printf(%s: tps65090_init() failed\n, __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar...@samsung.com): Use device tree */
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26,
[U-Boot] [PATCH V3 9/9] CONFIGS: peach-pit: Enable display for peach_pit board
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar ajaykumar...@samsung.com --- include/configs/peach-pit.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 76b8d7a..88c093f 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -22,4 +22,14 @@ #define CONFIG_SYS_PROMPT Peach # #define CONFIG_IDENT_STRING for Peach +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + #endif /* __CONFIG_PEACH_PIT_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 8/9] ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5420-peach-pit.dts | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts
b/arch/arm/dts/exynos5420-peach-pit.dts
index 8d148af..3ed70a8 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -63,6 +63,11 @@
reg = 0x20;
compatible = maxim,max98090-codec;
};
+
+ edp-lvds-bridge@48 {
+ compatible = parade,ps8625;
+ reg = 0x48;
+ };
};
sound@383 {
@@ -124,4 +129,29 @@
xhci@1240 {
samsung,vbus-gpio = gpio 0x41 0; /* H01 */
};
+
+ fimd@1440 {
+ samsung,vl-freq = 60;
+ samsung,vl-col = 1366;
+ samsung,vl-row = 768;
+ samsung,vl-width = 1366;
+ samsung,vl-height = 768;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = 4;
+
+ samsung,vl-hspw = 32;
+ samsung,vl-hbpd = 40;
+ samsung,vl-hfpd = 40;
+ samsung,vl-vspw = 6;
+ samsung,vl-vbpd = 10;
+ samsung,vl-vfpd = 12;
+ samsung,vl-cmd-allow-len = 0xf;
+
+ samsung,winid = 3;
+ samsung,interface-mode = 1;
+ samsung,dp-enabled = 1;
+ samsung,dual-lcd-enabled = 0;
+ };
};
--
1.7.9.5
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Re: [U-Boot] [PATCH 1/5] AHCI: Increase link timeout to 200ms
On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote: In 73545f75b66d ahci: wait longer for link I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Karsten Merker mer...@debian.org Is there no way to poll for this condition instead of using an ever-growing timeout? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] nand: denali: add Denali NAND driver for SPL
On Friday, July 04, 2014 at 12:19:13 PM, Masahiro Yamada wrote:
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Chin Liang See cl...@altera.com
Cc: Scott Wood scottw...@freescale.com
[...]
+static void read_data_from_flash_mem(uint8_t *buf, int len)
+{
+ int i;
+ uint32_t *buf32;
+
+ /* transfer the data from the flash */
+ buf32 = (uint32_t *)buf;
+ for (i = 0; i len / 4; i++)
+ *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
+}
+
+int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
+{
+ uint32_t addr, cmd;
+ static uint32_t page_count = 1;
+
+ writel(ecc_en, denali_flash_reg + ECC_ENABLE);
+
+ /* clear all bits of intr_status. */
+ writel(0x, denali_flash_reg + INTR_STATUS(flash_bank));
+
+ addr = BANK(flash_bank) | page;
+
+ /* setup the acccess type */
+ cmd = MODE_10 | addr;
+ index_addr(cmd, access_type);
+
+ /* setup the pipeline command */
+ index_addr(cmd, 0x2000 | page_count);
Magic value 0x2000 should be fixed here.
+ cmd = MODE_01 | addr;
+ writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
Somehow, eventually, this should be migrated to struct based register access
instead of such offset computation. If you feel like doing it, that'd be nice
;-)
+ return wait_for_irq(INTR_STATUS__LOAD_COMP);
+}
[...]
Thanks!
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Re: [U-Boot] [PATCH 2/6] serial: add UniPhier serial driver
On Friday, July 04, 2014 at 12:19:14 PM, Masahiro Yamada wrote:
The driver for on-chip UART used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
[...]
+static void uniphier_serial_init(struct uniphier_serial *port)
+{
+ writeb(UART_LCR_WLS_8, port-lcr);
+
+#define MODE_X_DIV 16
You can use just const unsigned here instead of #define.
+
+ /* Compute divisor value. Normally, we should simply return:
+ * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd-baudrate
+ * but we need to round that value by adding 0.5.
+ * Rounding is especially important at high baud rates.
+ */
+ writew((CONFIG_SYS_UNIPHIER_UART_CLK + (gd-baudrate *
+ (MODE_X_DIV / 2))) / (MODE_X_DIV * gd-baudrate), port-dlr);
+}
+
+static void uniphier_serial_setbrg(struct uniphier_serial *port)
+{
+ uniphier_serial_init(port);
+}
+
+static int uniphier_serial_tstc(struct uniphier_serial *port)
+{
+ return (readb(port-lsr) UART_LSR_DR) != 0;
+}
+
+static int uniphier_serial_getc(struct uniphier_serial *port)
+{
+ while (!uniphier_serial_tstc(port))
+ ;
+
+ return readb(port-rbr);
+}
+
+static void uniphier_serial_putc(struct uniphier_serial *port, const char
c) +{
+ if (c == '\n')
+ uniphier_serial_putc(port, '\r');
+
+ while (!(readb(port-lsr) UART_LSR_THRE))
+ ;
I think in this function, you can avoid such completely unbounded loop.
[...]
Best regard,
Marek Vasut
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Re: [U-Boot] [PATCH 2/5] board_r: run scsi init() on ARM too
On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote: This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch). Does this break bisectability ? I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware) - omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used). While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Simon Glass s...@chromium.org Make sure to check no ARM boards call scsi_init() from their board files. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] board_r: run scsi init() on ARM too
On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote: On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote: This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch). Does this break bisectability ? Not if this patch goes in first. I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware) - omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used). While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Simon Glass s...@chromium.org Make sure to check no ARM boards call scsi_init() from their board files. I grepped around and couldn't find any. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] AHCI: Increase link timeout to 200ms
On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote: On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote: In 73545f75b66d ahci: wait longer for link I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Karsten Merker mer...@debian.org Is there no way to poll for this condition instead of using an ever-growing timeout? This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] board_r: run scsi init() on ARM too
On Friday, July 04, 2014 at 05:25:10 PM, Ian Campbell wrote: On Fri, 2014-07-04 at 16:59 +0200, Marek Vasut wrote: On Saturday, May 31, 2014 at 06:36:12 PM, Ian Campbell wrote: This has been disabled for ARM in initr_scsi since that function was introduced. However it works fine for me on Cubieboard and Cubietruck (with the upcoming AHCI glue patch). Does this break bisectability ? Not if this patch goes in first. I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI: - highbank worked fine (on midway hardware) - omap5_uevm built OK and I confirmed using objdump that things were as expected (i.e. the default weak scsi_init nop was used). While there remove the mismatched comment from the #endif (omitting the comment seems to be the prevailing style in this file) and add a missing return to initr_doc which I happened to spot while editing. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Simon Glass s...@chromium.org Make sure to check no ARM boards call scsi_init() from their board files. I grepped around and couldn't find any. OK, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] AHCI: Increase link timeout to 200ms
On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote: On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote: On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote: In 73545f75b66d ahci: wait longer for link I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Karsten Merker mer...@debian.org Is there no way to poll for this condition instead of using an ever-growing timeout? This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one. And if the device is never ready, then we will wait 200mS for nothing ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] AHCI: Increase link timeout to 200ms
On Fri, 2014-07-04 at 17:44 +0200, Marek Vasut wrote: On Friday, July 04, 2014 at 05:26:40 PM, Ian Campbell wrote: On Fri, 2014-07-04 at 16:58 +0200, Marek Vasut wrote: On Saturday, May 31, 2014 at 06:36:11 PM, Ian Campbell wrote: In 73545f75b66d ahci: wait longer for link I increased the timeout to 40ms based on the observed behaviour of a WD disk on a Cubietruck. Since then Karsten Merker and myself have both observed timeouts with HGST disks (Karsten on Cubietruck, me on Cubieboard2). Increasing the timeout to ~175ms fixes this, so go to 200ms for a bit of headroom. Signed-off-by: Ian Campbell i...@hellion.org.uk Cc: Karsten Merker mer...@debian.org Is there no way to poll for this condition instead of using an ever-growing timeout? This timeout is the maximum time to poll for. If the device is ready sooner (likely) then we'll notice that and carry one. And if the device is never ready, then we will wait 200mS for nothing ? If you've typed scsi scan, yes. Does u-boot have any mechanisms to do anything else though? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4: DNS320 support 0/4] Add a new kirkwook board
Add a new kirkwook board dns-320.
This is a rebase of an old patch set from Jamie Lentin.
Source is available here:
http://jamie.lentin.co.uk/devices/dlink-dns325/
Please apply
Changelog:
[V2] Use git option -M
[V3] Fix a mismerge in boards.cfg
[V4] Rebase.
Cc: Prafulla Wadaskar prafu...@marvell.com
Cc: Jamie Lentin j...@lentin.co.uk
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Jamie Lentin (4):
kirkwood: Rename dns325 to dnskw
kirkwood: Add support for the D-Link DNS-320
kirkwood: Set unused SD pins back to GPIO for DNS-320 DNS-325
kirkwood: Shorten DNS-325 IDENT_STRING to match DNS-320
board/d-link/dns325/dns325.h | 32 ---
board/d-link/{dns325 = dnskw}/Makefile| 2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 30 +++---
board/d-link/dnskw/dnskw.h | 42 +
.../kwbimage.cfg = dnskw/kwbimage.dns320.cfg} | 103 -
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} | 0
boards.cfg | 3 +-
include/configs/{dns325.h = dnskw.h} | 23 -
8 files changed, 138 insertions(+), 97 deletions(-)
delete mode 100644 board/d-link/dns325/dns325.h
rename board/d-link/{dns325 = dnskw}/Makefile (93%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (84%)
create mode 100644 board/d-link/dnskw/dnskw.h
copy board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns320.cfg} (67%)
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
rename include/configs/{dns325.h = dnskw.h} (86%)
--
2.0.0
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[U-Boot] [PATCH 1/4] kirkwood: Rename dns325 to dnskw
From: Jamie Lentin j...@lentin.co.uk
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
---
board/d-link/{dns325 = dnskw}/Makefile| 2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 10 -
board/d-link/{dns325/dns325.h = dnskw/dnskw.h}| 24 +-
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} | 0
boards.cfg | 2 +-
include/configs/{dns325.h = dnskw.h} | 11 +++---
6 files changed, 29 insertions(+), 20 deletions(-)
rename board/d-link/{dns325 = dnskw}/Makefile (93%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (93%)
rename board/d-link/{dns325/dns325.h = dnskw/dnskw.h} (52%)
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
rename include/configs/{dns325.h = dnskw.h} (94%)
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dnskw/Makefile
similarity index 93%
rename from board/d-link/dns325/Makefile
rename to board/d-link/dnskw/Makefile
index b8a5ea1..85cebf7 100644
--- a/board/d-link/dns325/Makefile
+++ b/board/d-link/dnskw/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := dns325.o
+obj-y := dnskw.o
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dnskw/dnskw.c
similarity index 93%
rename from board/d-link/dns325/dns325.c
rename to board/d-link/dnskw/dnskw.c
index ff70e94..22b0ffb 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dnskw/dnskw.c
@@ -17,15 +17,15 @@
#include asm/arch/kirkwood.h
#include asm/arch/mpp.h
#include asm/arch/gpio.h
-#include dns325.h
+#include dnskw.h
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* Gpio configuration */
- kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
- DNS325_OE_LOW, DNS325_OE_HIGH);
+ kw_config_gpio(DNSKW_OE_VAL_LOW, DNSKW_OE_VAL_HIGH,
+ DNSKW_OE_LOW, DNSKW_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
@@ -83,9 +83,9 @@ int board_early_init_f(void)
};
kirkwood_mpp_conf(kwmpp_config, NULL);
- kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
+ kw_gpio_set_blink(DNSKW_GPIO_LED_POWER , 1);
- kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+ kw_gpio_set_value(DNSKW_GPIO_SATA0_EN , 1);
return 0;
}
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dnskw/dnskw.h
similarity index 52%
rename from board/d-link/dns325/dns325.h
rename to board/d-link/dnskw/dnskw.h
index f7b25f2..8d2e2b1 100644
--- a/board/d-link/dns325/dns325.h
+++ b/board/d-link/dnskw/dnskw.h
@@ -10,18 +10,22 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#ifndef __DNS325_H
-#define __DNS325_H
+#ifndef __DNSKW_H
+#define __DNSKW_H
/* GPIO configuration */
-#define DNS325_OE_LOW 0x
-#define DNS325_OE_HIGH 0x00039604
-#define DNS325_OE_VAL_LOW 0x3800 /* disable leds */
-#define DNS325_OE_VAL_HIGH 0x0800 /* disable leds */
+#define DNSKW_OE_LOW 0x
+#define DNSKW_OE_HIGH 0x00039604
-#define DNS325_GPIO_LED_POWER 26
-#define DNS325_GPIO_SATA0_EN 39
-#define DNS325_GPIO_SATA1_EN 40
+#define DNSKW_GPIO_LED_POWER 26
+#define DNSKW_GPIO_SATA0_EN39
+#define DNSKW_GPIO_SATA1_EN40
+
+/* DNS-325 specific configuration */
+#ifdef CONFIG_BOARD_IS_DNS325
+#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */
+#define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */
+#endif /* CONFIG_BOARD_IS_DNS325 */
/* PHY related */
#define MV88E1116_MAC_CTRL_REG 21
@@ -29,4 +33,4 @@
#define MV88E1116_RGMII_TXTM_CTRL (1 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 5)
-#endif /* __DNS325_H */
+#endif /* __DNSKW_H */
diff --git a/board/d-link/dns325/kwbimage.cfg
b/board/d-link/dnskw/kwbimage.dns325.cfg
similarity index 100%
rename from board/d-link/dns325/kwbimage.cfg
rename to board/d-link/dnskw/kwbimage.dns325.cfg
diff --git a/boards.cfg b/boards.cfg
index 8e2db82..5259b27 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -163,7 +163,7 @@ Active arm arm926ejs davinci omicron
calimain
Active arm arm926ejs kirkwoodbuffalo lsxl
lschlv2 lsxl:LSCHLV2
Michael Walle mich...@walle.cc
Active arm arm926ejs kirkwoodbuffalo lsxl
lsxhl lsxl:LSXHL
[U-Boot] [PATCH 4/4] kirkwood: Shorten DNS-325 IDENT_STRING to match DNS-320
From: Jamie Lentin j...@lentin.co.uk You should already know you're using a D-link device. Signed-off-by: Jamie Lentin j...@lentin.co.uk --- include/configs/dnskw.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h index e55fdc4..7058873 100644 --- a/include/configs/dnskw.h +++ b/include/configs/dnskw.h @@ -19,7 +19,7 @@ #ifdef CONFIG_BOARD_IS_DNS325 #define MACH_TYPE_DNS325 3800 #define CONFIG_MACH_TYPE MACH_TYPE_DNS325 -#define CONFIG_IDENT_STRING\nD-Link DNS-325 +#define CONFIG_IDENT_STRING\nDNS-325 #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.dns325.cfg -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] kirkwood: Add support for the D-Link DNS-320
From: Jamie Lentin j...@lentin.co.uk Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more information on this NAS, see:- http://jamie.lentin.co.uk/devices/dlink-dns320 http://dns323.kood.org/dns-320 http://sharecenter.dlink.com/products/DNS-320 Changes since V1: * Shorten CONFIG_IDENT_STRING [Prafulla Wadaskar] Changes since V2: * Correct a mismerge conflict Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net Cc: ste...@herbrechtsmeier.net --- board/d-link/dnskw/dnskw.c | 8 +- board/d-link/dnskw/dnskw.h | 6 + board/d-link/dnskw/kwbimage.dns320.cfg | 207 + boards.cfg | 1 + include/configs/dnskw.h| 10 ++ 5 files changed, 228 insertions(+), 4 deletions(-) create mode 100644 board/d-link/dnskw/kwbimage.dns320.cfg diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c index 22b0ffb..a9fa9a2 100644 --- a/board/d-link/dnskw/dnskw.c +++ b/board/d-link/dnskw/dnskw.c @@ -42,8 +42,8 @@ int board_early_init_f(void) MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, + MPP13_UART1_TXD,/* Custom ...*/ + MPP14_UART1_RXD,/* ... controller */ MPP15_SD_D1, MPP16_SD_D2, MPP17_SD_D3, @@ -58,13 +58,13 @@ int board_early_init_f(void) MPP26_GPIO, /* power led */ MPP27_GPIO, /* sata0(right) error led */ MPP28_GPIO, /* sata1(left) error led */ - MPP29_GPIO, /* usb error led */ + MPP29_GPIO, /* usb error led (dns-325) */ MPP30_GPIO, MPP31_GPIO, MPP32_GPIO, MPP33_GPIO, MPP34_GPIO, /* power key */ - MPP35_GPIO, + MPP35_GPIO, /* usb error led (dns-320) */ MPP36_GPIO, MPP37_GPIO, MPP38_GPIO, diff --git a/board/d-link/dnskw/dnskw.h b/board/d-link/dnskw/dnskw.h index 8d2e2b1..f87f02c 100644 --- a/board/d-link/dnskw/dnskw.h +++ b/board/d-link/dnskw/dnskw.h @@ -27,6 +27,12 @@ #define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */ #endif /* CONFIG_BOARD_IS_DNS325 */ +/* DNS-320 specific configuration */ +#ifdef CONFIG_BOARD_IS_DNS320 +#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */ +#define DNSKW_OE_VAL_HIGH 0x0808 /* disable leds */ +#endif /* CONFIG_BOARD_IS_DNS320 */ + /* PHY related */ #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG22 diff --git a/board/d-link/dnskw/kwbimage.dns320.cfg b/board/d-link/dnskw/kwbimage.dns320.cfg new file mode 100644 index 000..b515bf2 --- /dev/null +++ b/board/d-link/dnskw/kwbimage.dns320.cfg @@ -0,0 +1,207 @@ +# +# Copyright (C) 2012 +# Jamie Lentin j...@lentin.co.uk +# +# Based on dns325 support: +# Copyright (C) 2011 +# Stefan Herbrechtsmeier ste...@code.herbrechtsmeier.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0x618 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24:1, enable exit self refresh mode on DDR access +# bit25:1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit3-0: 0 required +# bit4: 0, addr/cmd in smame cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use
[U-Boot] [PATCH 3/4] kirkwood: Set unused SD pins back to GPIO for DNS-320 DNS-325
From: Jamie Lentin j...@lentin.co.uk Neither device makes any use of the SD reader functionalty, so as suggested by Stefan Herbrechtsmeier, set the pins to GPIO instead to make this more obvious. Label MPP10 MPP11's use whilst here. Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net Cc: ste...@herbrechtsmeier.net --- board/d-link/dnskw/dnskw.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c index a9fa9a2..90cb92e 100644 --- a/board/d-link/dnskw/dnskw.c +++ b/board/d-link/dnskw/dnskw.c @@ -39,14 +39,14 @@ int board_early_init_f(void) MPP7_GPO, MPP8_TW_SDA, MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, + MPP10_UART0_TXD,/* 5 pin ...*/ + MPP11_UART0_RXD,/* ... console header */ + MPP12_GPO, MPP13_UART1_TXD,/* Custom ...*/ MPP14_UART1_RXD,/* ... controller */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, MPP18_NF_IO0, MPP19_NF_IO1, MPP20_SATA1_ACTn, /* sata1(left) status led */ -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v9 1/5] Added 64-bit MMIO accessors for ARMv8
Hi York,
On Mon, 23 Jun 2014 15:15:52 -0700, York Sun york...@freescale.com
wrote:
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v9: no change
v8: no change
v7: no change
v6: no change
v5: no change
v4: no change
v3: no change
arch/arm/include/asm/io.h |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6a1f05a..95528dd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -70,10 +70,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short
*)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getq(a) (*(volatile unsigned long long
*)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) =
(v))
extern inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
@@ -123,10 +125,12 @@ extern inline void __raw_readsl(unsigned long addr,
void *data, int longlen)
#define __raw_writeb(v,a)__arch_putb(v,a)
#define __raw_writew(v,a)__arch_putw(v,a)
#define __raw_writel(v,a)__arch_putl(v,a)
+#define __raw_writeq(v,a)__arch_putq(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
+#define __raw_readq(a) __arch_getq(a)
/*
* TODO: The kernel offers some more advanced versions of barriers, it might
@@ -139,10 +143,12 @@ extern inline void __raw_readsl(unsigned long addr,
void *data, int longlen)
#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
/*
* The compiler seems to be incapable of optimising constants
@@ -168,9 +174,11 @@ extern inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
#define out_arch(type,endian,a,v)__raw_write##type(cpu_to_##endian(v),a)
#define in_arch(type,endian,a)
endian##_to_cpu(__raw_read##type(a))
+#define out_le64(a,v)out_arch(q,le64,a,v)
#define out_le32(a,v)out_arch(l,le32,a,v)
#define out_le16(a,v)out_arch(w,le16,a,v)
+#define in_le64(a) in_arch(q,le64,a)
#define in_le32(a) in_arch(l,le32,a)
#define in_le16(a) in_arch(w,le16,a)
Series applied to u-boot-arm/master (with a slight manual fix to
boards.cfg in 1/5), thanks!
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH] ARM: cache_v7: use __weak
Hi Tom, On Mon, 23 Jun 2014 16:15:51 -0400, Tom Rini tr...@ti.com wrote: On Mon, Jun 23, 2014 at 10:07:04PM +0200, Jeroen Hofstee wrote: This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud albert.u.b...@aribaud.net Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Been on my TODO list for a long time, thanks! Reviewed-by: Tom Rini tr...@ti.com +/* Stub implementations for outer cache operations */ Extra space. Albert assuming you're OK can you just fix it up when you take it? Ok -- pulling this one in as a bugfix (though I don't see the warning with the toolchain I am using). Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: cache_v7: use __weak
Hi Jeroen,
On Mon, 23 Jun 2014 22:07:04 +0200, Jeroen Hofstee
jer...@myspectrum.nl wrote:
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
---
arch/arm/cpu/armv7/cache_v7.c | 45
+++
arch/arm/include/asm/cache.h | 3 +++
arch/arm/lib/cache-cp15.c | 9 ++---
arch/arm/lib/cache.c | 13 +++--
4 files changed, 15 insertions(+), 55 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index bc5fc42..a2c4032 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -354,41 +354,10 @@ void invalidate_icache_all(void)
}
#endif
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
- __attribute__((weak, alias(__v7_outer_cache_enable)));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
- __attribute__((weak, alias(__v7_outer_cache_disable)));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
- __attribute__((weak, alias(__v7_outer_cache_flush_all)));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
- __attribute__((weak, alias(__v7_outer_cache_inval_all)));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
- __attribute__((weak, alias(__v7_outer_cache_flush_range)));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
- __attribute__((weak, alias(__v7_outer_cache_inval_range)));
+/* Stub implementations for outer cache operations */
+__weak void v7_outer_cache_enable(void) {}
+__weak void v7_outer_cache_disable(void) {}
+__weak void v7_outer_cache_flush_all(void) {}
+__weak void v7_outer_cache_inval_all(void) {}
+__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
+__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index ddebbc8..a836e9f 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -29,6 +29,9 @@ void l2_cache_enable(void);
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
void dram_bank_mmu_setup(int bank);
#endif
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 8642010..5fdfdbf 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -14,11 +14,9 @@
DECLARE_GLOBAL_DATA_PTR;
-void __arm_init_before_mmu(void)
+__weak void arm_init_before_mmu(void)
{
}
-void arm_init_before_mmu(void)
- __attribute__((weak, alias(__arm_init_before_mmu)));
__weak void arm_init_domains(void)
{
@@ -44,14 +42,11 @@ void set_section_dcache(int section, enum dcache_option
option)
page_table[section] = value;
}
-void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug(%s: Warning: not implemented\n, __func__);
}
-void mmu_page_table_flush(unsigned long start, unsigned long stop)
- __attribute__((weak, alias(__mmu_page_table_flush)));
-
void mmu_set_region_dcache_behaviour(u32 start, int size,
enum dcache_option option)
{
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 4f6b9f0..4e597a4 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -9,7 +9,7 @@
#include common.h
-void __flush_cache(unsigned long start, unsigned long size)
+__weak void flush_cache(unsigned long start, unsigned long size)
{
#if defined(CONFIG_ARM1136)
@@ -31,28 +31,21 @@ void __flush_cache(unsigned long start, unsigned long
size)
#endif /* CONFIG_ARM926EJS */
return;
}
-void flush_cache(unsigned long start, unsigned long size)
- __attribute__((weak, alias(__flush_cache)));
/*
* Default implementation:
* do a range flush for the entire range
*/
-void __flush_dcache_all(void)
+__weak void flush_dcache_all(void)
{
flush_cache(0, ~0);
}
-void flush_dcache_all(void)
- __attribute__((weak, alias(__flush_dcache_all)));
-
/*
* Default implementation of enable_caches()
* Real implementation should be in platform code
*/
-void __enable_caches(void)
+__weak void enable_caches(void)
{
puts(WARNING: Caches not enabled\n);
}
-void enable_caches(void)
- __attribute__((weak, alias(__enable_caches)));
Re: [U-Boot] [PATCH] ARM: kirkwood: fix cpu info for 6282 device id
-Original Message-
From: Luka Perkov [mailto:l...@openwrt.org]
Sent: 02 July 2014 05:48
To: u-boot@lists.denx.de
Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
Subject: [PATCH] ARM: kirkwood: fix cpu info for 6282
device id
Signed-off-by: Luka Perkov l...@openwrt.org
CC: Prafulla Wadaskar prafu...@marvell.com
CC: Stefan Roese s...@denx.de
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index da80240..312d2b2 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -252,7 +252,7 @@ static void kw_sysrst_check(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char *rev;
+ char *rev = ??;
u16 devid = (readl(KW_REG_PCIE_DEVID) 16)
0x;
u8 revid = readl(KW_REG_PCIE_REVID) 0xff;
@@ -263,7 +263,13 @@ int print_cpuinfo(void)
switch (revid) {
case 0:
- rev = Z0;
+ if (devid == 0x6281)
+ rev = Z0;
+ else if (devid == 0x6282)
+ rev = A0;
+ break;
+ case 1:
+ rev = A1;
break;
case 2:
rev = A0;
@@ -272,7 +278,6 @@ int print_cpuinfo(void)
rev = A1;
break;
default:
- rev = ??;
break;
}
Acked-By: Prafulla Wadaskar prafu...@marvell.com
Will be pulled latter.
Regards...
Prafulla . . .
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Re: [U-Boot] [PATCH 1/4] kirkwood: Rename dns325 to dnskw
Hi Bastien, On Fri, 4 Jul 2014 19:01:47 +0200, Bastien ROUCARIÈS roucaries.bast...@gmail.com wrote: From: Jamie Lentin j...@lentin.co.uk So we can re-use DNS-325 configuration for the DNS-320 without things getting confusing, rename all common parts from dns325 to dnskw, and use a config option to configure DNS-325 specifics. Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net --- For this patch and the rest of the series: the v4 tag is missing from the individual patch subject. Maybe you should consider using patman (see tools/patman/README), which automates a lot of patch series submission things like version tags or history. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] kirkwood: Add support for the D-Link DNS-320
Hi Bastien,
On Fri, 4 Jul 2014 19:01:48 +0200, Bastien ROUCARIÈS
roucaries.bast...@gmail.com wrote:
From: Jamie Lentin j...@lentin.co.uk
Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more
information on this NAS, see:-
http://jamie.lentin.co.uk/devices/dlink-dns320
http://dns323.kood.org/dns-320
http://sharecenter.dlink.com/products/DNS-320
Changes since V1:
* Shorten CONFIG_IDENT_STRING [Prafulla Wadaskar]
Changes since V2:
* Correct a mismerge conflict
Changlog must not appear in commit message. It must appear after the
commit message delimiter ('---' below).
Also: maybe URLs for the board should be put in a README.dns-320 file
uder the doc/ directory, so that people interested in the board can
find it with a simple grep, rather than finding them by chance in a
commit message.
Amicalement,
--
Albert.
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[U-Boot] [PATCH v1 0/7] TI: armv7: add parallel NAND support
This patch series adds support for parallel NAND devices support connected via GPMC chip-select on various boards belonging to AM33xx and OMAPx platforms. This series also moves some board specific CONFIG_NAND_xx from generic files to individual files. Tested using: ./MAKEALL -s am33xx -s omap3 -s oamp4 -s omap5 works fine except for am335x_boneblack_vboot build breaks for am335x_boneblack_vboot for un-related reasons u-boot/scripts/dtc-version.sh: line 17: dtc: command not found Pekon Gupta (7): TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h board/ti/am335x: add support for beaglebone NAND cape arm: lib: continue board_init_r even if valid flash device is not detected board/ti/am335x: add support for beaglebone NOR Cape board/ti/am335x: update configs for parallel NAND board/ti/am43xx: add support for parallel NAND board/ti/dra7xx: add support for parallel NAND arch/arm/lib/board.c | 7 +- board/ti/am335x/mux.c | 149 ++--- board/ti/am43xx/board.c| 1 + board/ti/am43xx/mux.c | 42 +++ board/ti/dra7xx/mux_data.h | 30 boards.cfg | 4 +- doc/README.nand| 12 +++ include/configs/am335x_evm.h | 64 +--- include/configs/am43xx_evm.h | 70 + include/configs/cm_t335.h | 10 +++ include/configs/dra7xx_evm.h | 58 ++- include/configs/omap3_beagle.h | 6 ++ include/configs/omap3_igep00x0.h | 9 +++ include/configs/omap3_overo.h | 8 ++ include/configs/omap3_zoom1.h | 7 ++ include/configs/pengwyn.h | 7 ++ include/configs/ti_am335x_common.h | 4 - include/configs/ti_armv7_common.h | 9 --- 18 files changed, 369 insertions(+), 128 deletions(-) -- 1.8.5.1.163.gd7aced9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/7] arm: lib: continue board_init_r even if valid flash device is not detected
Most platforms have fall-back boot sources, if their primary boot fails.
This patch allows board_init to continue scanning through other secondary boot
sources like NAND, MMC, etc if valid FLASH device is not detected.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/lib/board.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 76adaf3..413ee60 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -460,10 +460,6 @@ void board_init_f(ulong bootflag)
memcpy(id, (void *)gd, sizeof(gd_t));
}
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = *** failed ***\n;
-#endif
-
/*
* Tell if it's OK to load the environment early in boot.
*
@@ -574,8 +570,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
print_size(flash_size, \n);
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
- puts(failed);
- hang();
+ puts(unable to detect valid flash device\n);
}
#endif
--
1.8.5.1.163.gd7aced9
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[U-Boot] [PATCH v1 1/7] TI: armv7: move board specific NAND configs out from ti_armv7_common.h and ti_am335x_common.h
This patch moves some board specific NAND configs: - FROM: generic config files like 'ti_armv7_common.h' and 'ti_am335x_common.h' - TO: individual board config files using these configs. So that each board can independently set the value as per its design. Following configs are affected in this patch: CONFIG_NAND_OMAP_GPMC: refer doc/README.nand CONFIG_NAND_OMAP_ELM: refer doc/README.nand CONFIG_SPL_NAND_AM33XX_BCH: refer doc/README.nand CONFIG_SYS_NAND_U_BOOT_OFFS: refer doc/README.nand CONFIG_CMD_SPL_NAND_OFS: refer doc/README.falcon CONFIG_SYS_NAND_SPL_KERNEL_OFFS: refer doc/README.falcon CONFIG_CMD_SPL_WRITE_SIZE: refer doc/README.falcon This patch also updates documentation for few of above NAND configs. Signed-off-by: Pekon Gupta pe...@ti.com --- doc/README.nand| 12 include/configs/am335x_evm.h | 7 +++ include/configs/cm_t335.h | 10 ++ include/configs/omap3_beagle.h | 6 ++ include/configs/omap3_igep00x0.h | 9 + include/configs/omap3_overo.h | 8 include/configs/omap3_zoom1.h | 7 +++ include/configs/pengwyn.h | 7 +++ include/configs/ti_am335x_common.h | 4 include/configs/ti_armv7_common.h | 9 - 10 files changed, 66 insertions(+), 13 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 70cf768..e29188f 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -89,6 +89,10 @@ Commands: Configuration Options: + CONFIG_SYS_NAND_U_BOOT_OFFS + NAND Offset from where SPL will read u-boot image. This is the starting + address of u-boot MTD partition in NAND. + CONFIG_CMD_NAND Enables NAND support and commmands. @@ -226,6 +230,14 @@ Platform specific options detection. However ECC calculation on such plaforms would still be done by GPMC controller. + CONFIG_SPL_NAND_AM33XX_BCH + Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based +hardware ECC correction. This is useful for platforms which have ELM + hardware engine and use NAND boot mode. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling +SPL-NAND driver with software ECC correction support. + CONFIG_NAND_OMAP_ECCSCHEME On OMAP platforms, this CONFIG specifies NAND ECC scheme. It can take following values: diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a48b386..57a6cab 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -233,6 +233,8 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM +#define CONFIG_SPL_NAND_AM33XX_BCH +/* NAND: device related configs */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) @@ -254,6 +256,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS0x8 +#ifdef CONFIG_SPL_OS_BOOT + #define CONFIG_CMD_SPL_NAND_OFS 0x0008 /* os parameters */ + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x0020 /* kernel offset */ + #define CONFIG_CMD_SPL_WRITE_SIZE0x2000 +#endif #endif #endif diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 4d1dd28..70b6e90 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -150,6 +150,16 @@ #define CONFIG_ENV_OFFSET 0x30 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 10) /* 128 KiB */ #define CONFIG_SYS_NAND_ONFI_DETECTION +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SPL_NAND_AM33XX_BCH /* SPL-NAND driver with ELM support */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT + #define CONFIG_CMD_SPL_NAND_OFS 0x40 /* un-assigned: (using dtb) */ + #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x50 + #define CONFIG_CMD_SPL_WRITE_SIZE0x2000 +#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank 5) + _pin) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c023483..7878765 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -126,6 +126,12 @@ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS0x24 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x28 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #define
[U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]
* How to boot from NAND using Memory Expander + NAND Cape ? *
- Important: As BOOTSEL values are sampled only at POR, so after changing any
setting on SW2 (DIP switch), disconnect and reconnect all board power supply
(including mini-USB console port) to POR the beaglebone.
- Selection of ECC scheme
for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
for NAND cape(b), ROM code expects BCH16_HW ecc-scheme
- Selction of boot modes can be controlled via DIP switch(SW2) present on
Memory Expander cape.
SW2[SWITCH_BOOT] == OFF follow default boot order MMC- SPI - UART - USB
SW2[SWITCH_BOOT] == ON boot mode selected via DIP switch(SW2)
So to flash NAND, first boot via MMC or other sources and then switch to
SW2[SWITCH_BOOT]=ON to boot from NAND Cape.
- For NAND boot following switch settings need to be followed
SW2[ 1] = OFF (SYSBOOT[ 0]==1: NAND boot mode selected )
SW2[ 2] = OFF (SYSBOOT[ 1]==1: -- do -- )
SW2[ 3] = ON (SYSBOOT[ 2]==0: -- do -- )
SW2[ 4] = ON (SYSBOOT[ 3]==0: -- do -- )
SW2[ 5] = OFF (SYSBOOT[ 4]==1: -- do -- )
SW2[ 6] = OFF (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
SW2[ 7] = ON (SYSBOOT[ 9]==0: ECC done by ROM )
SW2[ 8] = ON (SYSBOOT[10]==0: Non Muxed device )
SW2[ 9] = ON (SYSBOOT[11]==0:-- do -- )
[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2]
http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
board/ti/am335x/mux.c | 58 +--
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index b2bfda5..439da4b 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -171,25 +171,36 @@ static struct module_pin_mux mii1_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0),(MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+
[U-Boot] [PATCH v1 5/7] board/ti/am335x: update configs for parallel NAND
This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various
configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)
Signed-off-by: Pekon Gupta pe...@ti.com
---
include/configs/am335x_evm.h | 61 ++--
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 57a6cab..4f8ed2f 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -61,7 +61,7 @@
${optargs} \
root=${nandroot} \
rootfstype=${nandrootfstype}\0 \
- nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0 \
+ nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0 \
nandrootfstype=ubifs rootwait=1\0 \
nandboot=echo Booting from nand ...; \
run nandargs; \
@@ -229,18 +229,23 @@
#define CONFIG_SPL_NET_VCI_STRING AM335x U-Boot SPL
#define CONFIG_SPL_LDSCRIPT$(CPUDIR)/am33xx/u-boot-spl.lds
+#endif
+/* NAND support */
#ifdef CONFIG_NAND
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_NAND_OMAP_ELM
-#define CONFIG_SPL_NAND_AM33XX_BCH
/* NAND: device related configs */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
-CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
@@ -252,17 +257,30 @@
#define CONFIG_SYS_NAND_ECCSIZE512
#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS0x8
+#define MTDIDS_DEFAULT nand0=nand.0
+#define MTDPARTS_DEFAULT mtdparts=nand.0: \
+ 128k(NAND.SPL), \
+ 128k(NAND.SPL.backup1), \
+ 128k(NAND.SPL.backup2), \
+ 128k(NAND.SPL.backup3), \
+ 256k(NAND.u-boot-spl-os), \
+ 1m(NAND.u-boot), \
+ 128k(NAND.u-boot-env), \
+ 128k(NAND.u-boot-env.backup1), \
+ 8m(NAND.kernel), \
+ -(NAND.rootfs)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS0x000c
+#define CONFIG_ENV_OFFSET 0x001c
+#define CONFIG_ENV_OFFSET_REDUND 0x001e
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS 0x0008 /* os parameters */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x0020 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE0x2000
#endif
-#endif
-#endif
+#endif /* !CONFIG_NAND */
/*
* For NOR boot, we must set this to the start of where NOR is mapped
@@ -419,23 +437,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
-/* NAND support */
-#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
-#if !defined(CONFIG_SPI_BOOT) !defined(CONFIG_NOR_BOOT)
-#define MTDIDS_DEFAULT nand0=omap2-nand.0
-#define MTDPARTS_DEFAULT mtdparts=omap2-nand.0:128k(SPL), \
- 128k(SPL.backup1), \
- 128k(SPL.backup2), \
- 128k(SPL.backup3),1792k(u-boot), \
- 128k(u-boot-spl-os), \
- 128k(u-boot-env),5m(kernel),-(rootfs)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x26 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 10) /* 128 KiB */
-#endif
-#endif
-
/*
* NOR Size = 16 MiB
* Number of Sectors/Blocks = 128
--
1.8.5.1.163.gd7aced9
___
U-Boot mailing list
[U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape
This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
so only one of them can be enabled at a time from board profile configs.
[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
Signed-off-by: Pekon Gupta pe...@ti.com
---
board/ti/am335x/mux.c | 95 +++
1 file changed, 35 insertions(+), 60 deletions(-)
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 439da4b..f6a9b29 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
{-1},
};
-#endif
-#if defined(CONFIG_NOR) !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
static struct module_pin_mux bone_norcape_pin_mux[] = {
- {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
- {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
- {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
- {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
- {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
- {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
- {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
- {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
- {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
- {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
- {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
- {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
- {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
- {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
- {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A14 */
- {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A15 */
- {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A16 */
- {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A17 */
- {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A18 */
- {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},/* NOR_A19 */
- {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
- {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
- {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
- {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
- {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
- {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
- {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
- {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
- {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
- {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
- {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
- {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
- {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
- {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
- {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
- {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
-
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /*
NOR_ADVN_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/*
NOR_BE0N_CLE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_WEN */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD0 */
+ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD1 */
+ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD2 */
+ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD3 */
+ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD4 */
+ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD5 */
+ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD6 */
+ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD7 */
+ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD8 */
+ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE},
[U-Boot] [PATCH v1 6/7] board/ti/am43xx: add support for parallel NAND
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
SPI2_CS0 == 0: NAND (default)
SPI2_CS0 == 1: eMMC
am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
Signed-off-by: Pekon Gupta pe...@ti.com
---
board/ti/am43xx/board.c | 1 +
board/ti/am43xx/mux.c| 42 ++
boards.cfg | 2 +-
include/configs/am43xx_evm.h | 70
4 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 054a452..2c3a290 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -487,6 +487,7 @@ void sdram_init(void)
int board_init(void)
{
gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
return 0;
}
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 50967e1..172adcd 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -73,6 +73,36 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
{-1},
};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0),(MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+ {-1},
+};
+#else
static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
@@ -82,6 +112,7 @@ static struct module_pin_mux qspi_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
{-1},
};
+#endif
void enable_uart0_pin_mux(void)
{
@@ -97,12 +128,23 @@ void enable_board_pin_mux(void)
if (board_is_gpevm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#endif
} else if (board_is_sk()) {
configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ pr_err(NAND flash is not present on this board\n);
+#else
configure_module_pin_mux(qspi_pin_mux);
+#endif
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_NAND)
+
[U-Boot] [PATCH v1 7/7] board/ti/dra7xx: add support for parallel NAND
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select present on DRA7xx EVM.
On this board, GPMC_WPN and NAND_BOOTn are controlled by DIP switch,
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Pekon Gupta pe...@ti.com
---
board/ti/dra7xx/mux_data.h | 30 +++
boards.cfg | 2 +-
include/configs/dra7xx_evm.h | 58 +++-
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 38de9d5..697e9e4 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -51,6 +51,35 @@ const struct pad_conf_entry core_padconf_array_essential[] =
{
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+#ifdef CONFIG_NAND
+ /* NAND / NOR pin-mux */
+ {GPMC_AD0 , M0 | IEN | PDIS}, /* AD0 */
+ {GPMC_AD1 , M0 | IEN | PDIS}, /* AD1 */
+ {GPMC_AD2 , M0 | IEN | PDIS}, /* AD2 */
+ {GPMC_AD3 , M0 | IEN | PDIS}, /* AD3 */
+ {GPMC_AD4 , M0 | IEN | PDIS}, /* AD4 */
+ {GPMC_AD5 , M0 | IEN | PDIS}, /* AD5 */
+ {GPMC_AD6 , M0 | IEN | PDIS}, /* AD6 */
+ {GPMC_AD7 , M0 | IEN | PDIS}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {GPMC_AD8 , M0 | IEN | PDIS}, /* AD8 */
+ {GPMC_AD9 , M0 | IEN | PDIS}, /* AD9 */
+ {GPMC_AD10, M0 | IEN | PDIS}, /* AD10 */
+ {GPMC_AD11, M0 | IEN | PDIS}, /* AD11 */
+ {GPMC_AD12, M0 | IEN | PDIS}, /* AD12 */
+ {GPMC_AD13, M0 | IEN | PDIS}, /* AD13 */
+ {GPMC_AD14, M0 | IEN | PDIS}, /* AD14 */
+ {GPMC_AD15, M0 | IEN | PDIS}, /* AD15 */
+#endif
+ {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* chip-select */
+ {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* Addr latch */
+ {GPMC_OEN_REN, M0 | IDIS | PEN | PTD}, /* Read enable */
+ {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* Write enable_n */
+ {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* Byte/Column En */
+ {GPMC_WAIT0,M0 | IEN | PEN | PTU}, /* Wait/Ready */
+ /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+ /* QSPI pin-mux */
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
@@ -61,6 +90,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
{GPMC_CS2, (IEN | PTU | PDIS | M1)},/* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)},/* QSPI1_CS1*/
+#endif /* CONFIG_NAND */
{USB2_DRVVBUS, (M0 | IEN | FSC) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/boards.cfg b/boards.cfg
index 52aeb7f..1cc0e94 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -361,7 +361,7 @@ Active arm armv7 omap4 gumstix
duovero
Active arm armv7 omap4 ti panda
omap4_panda -
Sricharan R r.sricha...@ti.com
Active arm armv7 omap4 ti sdp4430
omap4_sdp4430 -
Sricharan R r.sricha...@ti.com
Active arm armv7 omap5 compulabcm_t54
cm_t54-
Dmitry Lifshitz lifsh...@compulab.co.il
-Active arm armv7 omap5 ti dra7xx
dra7xx_evmdra7xx_evm:CONS_INDEX=1
Lokesh Vutla lokeshvu...@ti.com
+Active arm armv7 omap5 ti dra7xx
dra7xx_evmdra7xx_evm:CONS_INDEX=1,NAND
Lokesh Vutla lokeshvu...@ti.com
Active arm armv7 omap5 ti dra7xx
dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT
Lokesh Vutla lokeshvu...@ti.com
Active arm armv7 omap5 ti dra7xx
dra7xx_evm_uart3
dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT
Re: [U-Boot] [PATCH] ARM: kirkwood: fix cpu info for 6282 device id
Hi Prafulla,
On Fri, 4 Jul 2014 11:43:48 -0700, Prafulla Wadaskar
prafu...@marvell.com wrote:
-Original Message-
From: Luka Perkov [mailto:l...@openwrt.org]
Sent: 02 July 2014 05:48
To: u-boot@lists.denx.de
Cc: l...@openwrt.org; Prafulla Wadaskar; Stefan Roese
Subject: [PATCH] ARM: kirkwood: fix cpu info for 6282
device id
Signed-off-by: Luka Perkov l...@openwrt.org
CC: Prafulla Wadaskar prafu...@marvell.com
CC: Stefan Roese s...@denx.de
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index da80240..312d2b2 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -252,7 +252,7 @@ static void kw_sysrst_check(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char *rev;
+ char *rev = ??;
u16 devid = (readl(KW_REG_PCIE_DEVID) 16)
0x;
u8 revid = readl(KW_REG_PCIE_REVID) 0xff;
@@ -263,7 +263,13 @@ int print_cpuinfo(void)
switch (revid) {
case 0:
- rev = Z0;
+ if (devid == 0x6281)
+ rev = Z0;
+ else if (devid == 0x6282)
+ rev = A0;
+ break;
+ case 1:
+ rev = A1;
break;
case 2:
rev = A0;
@@ -272,7 +278,6 @@ int print_cpuinfo(void)
rev = A1;
break;
default:
- rev = ??;
break;
}
Acked-By: Prafulla Wadaskar prafu...@marvell.com
Will be pulled latter.
Prafulla, just a note in case you intend to send a PR for 2014.07: I'll
be unavailable for U-Boot work from Monday july 7th to Tuesday july 22nd
inclusive, so meanwhile, a Marvell PR for 2014.07 would have to be sent
to Tom Rini.
Regards...
Prafulla . . .
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Hi Albert, On Mon, 9 Jun 2014 10:11:28 +0200, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Anthony, On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice tony.fel...@timesys.com wrote: Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Is this just a compliance fix, or a bug fix? Ping. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5: 0/5] Add a new kirkwook board
Add a new kirkwook board dns-320.
This is a rebase of an old patch set from Jamie Lentin.
Source is available here:
http://jamie.lentin.co.uk/devices/dlink-dns325/
Please apply
Changelog:
[V2] Use git option -M
[V3] Fix a mismerge in boards.cfg
[V4] Rebase.
[V5] Add documentation
Cc: Prafulla Wadaskar prafu...@marvell.com
Cc: Jamie Lentin j...@lentin.co.uk
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Bastien ROUCARIÈS (1):
Add documentation for dns-32{0,5}
Jamie Lentin (4):
kirkwood: Rename dns325 to dnskw
kirkwood: Add support for the D-Link DNS-320
kirkwood: Set unused SD pins back to GPIO for DNS-320 DNS-325
kirkwood: Shorten DNS-325 IDENT_STRING to match DNS-320
board/d-link/dns325/dns325.h | 32 ---
board/d-link/{dns325 = dnskw}/Makefile| 2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 30 +++---
board/d-link/dnskw/dnskw.h | 42 +
.../kwbimage.cfg = dnskw/kwbimage.dns320.cfg} | 103 -
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} | 0
boards.cfg | 3 +-
doc/README.dnskw | 25 +
include/configs/{dns325.h = dnskw.h} | 23 -
9 files changed, 163 insertions(+), 97 deletions(-)
delete mode 100644 board/d-link/dns325/dns325.h
rename board/d-link/{dns325 = dnskw}/Makefile (93%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (84%)
create mode 100644 board/d-link/dnskw/dnskw.h
copy board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns320.cfg} (67%)
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
create mode 100644 doc/README.dnskw
rename include/configs/{dns325.h = dnskw.h} (86%)
--
2.0.0
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[U-Boot] [PATCH V5: 1/5] kirkwood: Rename dns325 to dnskw
From: Jamie Lentin j...@lentin.co.uk
So we can re-use DNS-325 configuration for the DNS-320 without things getting
confusing, rename all common parts from dns325 to dnskw, and use a config
option to configure DNS-325 specifics.
Signed-off-by: Jamie Lentin j...@lentin.co.uk
Cc: prafu...@marvell.com
Cc: albert.u.b...@aribaud.net
---
board/d-link/{dns325 = dnskw}/Makefile| 2 +-
board/d-link/{dns325/dns325.c = dnskw/dnskw.c}| 10 -
board/d-link/{dns325/dns325.h = dnskw/dnskw.h}| 24 +-
.../kwbimage.cfg = dnskw/kwbimage.dns325.cfg} | 0
boards.cfg | 2 +-
include/configs/{dns325.h = dnskw.h} | 11 +++---
6 files changed, 29 insertions(+), 20 deletions(-)
rename board/d-link/{dns325 = dnskw}/Makefile (93%)
rename board/d-link/{dns325/dns325.c = dnskw/dnskw.c} (93%)
rename board/d-link/{dns325/dns325.h = dnskw/dnskw.h} (52%)
rename board/d-link/{dns325/kwbimage.cfg = dnskw/kwbimage.dns325.cfg} (100%)
rename include/configs/{dns325.h = dnskw.h} (94%)
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dnskw/Makefile
similarity index 93%
rename from board/d-link/dns325/Makefile
rename to board/d-link/dnskw/Makefile
index b8a5ea1..85cebf7 100644
--- a/board/d-link/dns325/Makefile
+++ b/board/d-link/dnskw/Makefile
@@ -10,4 +10,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := dns325.o
+obj-y := dnskw.o
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dnskw/dnskw.c
similarity index 93%
rename from board/d-link/dns325/dns325.c
rename to board/d-link/dnskw/dnskw.c
index ff70e94..22b0ffb 100644
--- a/board/d-link/dns325/dns325.c
+++ b/board/d-link/dnskw/dnskw.c
@@ -17,15 +17,15 @@
#include asm/arch/kirkwood.h
#include asm/arch/mpp.h
#include asm/arch/gpio.h
-#include dns325.h
+#include dnskw.h
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* Gpio configuration */
- kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
- DNS325_OE_LOW, DNS325_OE_HIGH);
+ kw_config_gpio(DNSKW_OE_VAL_LOW, DNSKW_OE_VAL_HIGH,
+ DNSKW_OE_LOW, DNSKW_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
@@ -83,9 +83,9 @@ int board_early_init_f(void)
};
kirkwood_mpp_conf(kwmpp_config, NULL);
- kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
+ kw_gpio_set_blink(DNSKW_GPIO_LED_POWER , 1);
- kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+ kw_gpio_set_value(DNSKW_GPIO_SATA0_EN , 1);
return 0;
}
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dnskw/dnskw.h
similarity index 52%
rename from board/d-link/dns325/dns325.h
rename to board/d-link/dnskw/dnskw.h
index f7b25f2..8d2e2b1 100644
--- a/board/d-link/dns325/dns325.h
+++ b/board/d-link/dnskw/dnskw.h
@@ -10,18 +10,22 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#ifndef __DNS325_H
-#define __DNS325_H
+#ifndef __DNSKW_H
+#define __DNSKW_H
/* GPIO configuration */
-#define DNS325_OE_LOW 0x
-#define DNS325_OE_HIGH 0x00039604
-#define DNS325_OE_VAL_LOW 0x3800 /* disable leds */
-#define DNS325_OE_VAL_HIGH 0x0800 /* disable leds */
+#define DNSKW_OE_LOW 0x
+#define DNSKW_OE_HIGH 0x00039604
-#define DNS325_GPIO_LED_POWER 26
-#define DNS325_GPIO_SATA0_EN 39
-#define DNS325_GPIO_SATA1_EN 40
+#define DNSKW_GPIO_LED_POWER 26
+#define DNSKW_GPIO_SATA0_EN39
+#define DNSKW_GPIO_SATA1_EN40
+
+/* DNS-325 specific configuration */
+#ifdef CONFIG_BOARD_IS_DNS325
+#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */
+#define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */
+#endif /* CONFIG_BOARD_IS_DNS325 */
/* PHY related */
#define MV88E1116_MAC_CTRL_REG 21
@@ -29,4 +33,4 @@
#define MV88E1116_RGMII_TXTM_CTRL (1 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 5)
-#endif /* __DNS325_H */
+#endif /* __DNSKW_H */
diff --git a/board/d-link/dns325/kwbimage.cfg
b/board/d-link/dnskw/kwbimage.dns325.cfg
similarity index 100%
rename from board/d-link/dns325/kwbimage.cfg
rename to board/d-link/dnskw/kwbimage.dns325.cfg
diff --git a/boards.cfg b/boards.cfg
index 8e2db82..5259b27 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -163,7 +163,7 @@ Active arm arm926ejs davinci omicron
calimain
Active arm arm926ejs kirkwoodbuffalo lsxl
lschlv2 lsxl:LSCHLV2
Michael Walle mich...@walle.cc
Active arm arm926ejs kirkwoodbuffalo lsxl
lsxhl lsxl:LSXHL
[U-Boot] [PATCH V5: 3/5] kirkwood: Set unused SD pins back to GPIO for DNS-320 DNS-325
From: Jamie Lentin j...@lentin.co.uk Neither device makes any use of the SD reader functionalty, so as suggested by Stefan Herbrechtsmeier, set the pins to GPIO instead to make this more obvious. Label MPP10 MPP11's use whilst here. Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net Cc: ste...@herbrechtsmeier.net --- board/d-link/dnskw/dnskw.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c index a9fa9a2..90cb92e 100644 --- a/board/d-link/dnskw/dnskw.c +++ b/board/d-link/dnskw/dnskw.c @@ -39,14 +39,14 @@ int board_early_init_f(void) MPP7_GPO, MPP8_TW_SDA, MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, + MPP10_UART0_TXD,/* 5 pin ...*/ + MPP11_UART0_RXD,/* ... console header */ + MPP12_GPO, MPP13_UART1_TXD,/* Custom ...*/ MPP14_UART1_RXD,/* ... controller */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, MPP18_NF_IO0, MPP19_NF_IO1, MPP20_SATA1_ACTn, /* sata1(left) status led */ -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5: 2/5] kirkwood: Add support for the D-Link DNS-320
From: Jamie Lentin j...@lentin.co.uk Extend dnskw to support the D-Link DNS-320 ShareCenter NAS also. For more information on this NAS, see:- http://jamie.lentin.co.uk/devices/dlink-dns320 http://dns323.kood.org/dns-320 http://sharecenter.dlink.com/products/DNS-320 Signed-off-by: Jamie Lentin j...@lentin.co.uk Cc: prafu...@marvell.com Cc: albert.u.b...@aribaud.net Cc: ste...@herbrechtsmeier.net --- Changes since V1: * Shorten CONFIG_IDENT_STRING [Prafulla Wadaskar] Changes since V2: * Correct a mismerge conflict board/d-link/dnskw/dnskw.c | 8 +- board/d-link/dnskw/dnskw.h | 6 + board/d-link/dnskw/kwbimage.dns320.cfg | 207 + boards.cfg | 1 + include/configs/dnskw.h| 10 ++ 5 files changed, 228 insertions(+), 4 deletions(-) create mode 100644 board/d-link/dnskw/kwbimage.dns320.cfg diff --git a/board/d-link/dnskw/dnskw.c b/board/d-link/dnskw/dnskw.c index 22b0ffb..a9fa9a2 100644 --- a/board/d-link/dnskw/dnskw.c +++ b/board/d-link/dnskw/dnskw.c @@ -42,8 +42,8 @@ int board_early_init_f(void) MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, + MPP13_UART1_TXD,/* Custom ...*/ + MPP14_UART1_RXD,/* ... controller */ MPP15_SD_D1, MPP16_SD_D2, MPP17_SD_D3, @@ -58,13 +58,13 @@ int board_early_init_f(void) MPP26_GPIO, /* power led */ MPP27_GPIO, /* sata0(right) error led */ MPP28_GPIO, /* sata1(left) error led */ - MPP29_GPIO, /* usb error led */ + MPP29_GPIO, /* usb error led (dns-325) */ MPP30_GPIO, MPP31_GPIO, MPP32_GPIO, MPP33_GPIO, MPP34_GPIO, /* power key */ - MPP35_GPIO, + MPP35_GPIO, /* usb error led (dns-320) */ MPP36_GPIO, MPP37_GPIO, MPP38_GPIO, diff --git a/board/d-link/dnskw/dnskw.h b/board/d-link/dnskw/dnskw.h index 8d2e2b1..f87f02c 100644 --- a/board/d-link/dnskw/dnskw.h +++ b/board/d-link/dnskw/dnskw.h @@ -27,6 +27,12 @@ #define DNSKW_OE_VAL_HIGH 0x0800 /* disable leds */ #endif /* CONFIG_BOARD_IS_DNS325 */ +/* DNS-320 specific configuration */ +#ifdef CONFIG_BOARD_IS_DNS320 +#define DNSKW_OE_VAL_LOW 0x3800 /* disable leds */ +#define DNSKW_OE_VAL_HIGH 0x0808 /* disable leds */ +#endif /* CONFIG_BOARD_IS_DNS320 */ + /* PHY related */ #define MV88E1116_MAC_CTRL_REG 21 #define MV88E1116_PGADR_REG22 diff --git a/board/d-link/dnskw/kwbimage.dns320.cfg b/board/d-link/dnskw/kwbimage.dns320.cfg new file mode 100644 index 000..b515bf2 --- /dev/null +++ b/board/d-link/dnskw/kwbimage.dns320.cfg @@ -0,0 +1,207 @@ +# +# Copyright (C) 2012 +# Jamie Lentin j...@lentin.co.uk +# +# Based on dns325 support: +# Copyright (C) 2011 +# Stefan Herbrechtsmeier ste...@code.herbrechtsmeier.net +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=3 @ 200MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0x618 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24:1, enable exit self refresh mode on DDR access +# bit25:1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit3-0: 0 required +# bit4: 0, addr/cmd in smame cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use
[U-Boot] [PATCH V5: 4/5] kirkwood: Shorten DNS-325 IDENT_STRING to match DNS-320
From: Jamie Lentin j...@lentin.co.uk You should already know you're using a D-link device. Signed-off-by: Jamie Lentin j...@lentin.co.uk --- include/configs/dnskw.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/dnskw.h b/include/configs/dnskw.h index e55fdc4..7058873 100644 --- a/include/configs/dnskw.h +++ b/include/configs/dnskw.h @@ -19,7 +19,7 @@ #ifdef CONFIG_BOARD_IS_DNS325 #define MACH_TYPE_DNS325 3800 #define CONFIG_MACH_TYPE MACH_TYPE_DNS325 -#define CONFIG_IDENT_STRING\nD-Link DNS-325 +#define CONFIG_IDENT_STRING\nDNS-325 #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.dns325.cfg -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V5: 5/5] Add documentation for dns-32{0,5}
Add documentation for dns-320 dns-325 kirkwood box. This documentation include harware description, and link to external documentation. Signed-off-by: Bastien ROUCARIÈS roucaries.bast...@gmail.com --- doc/README.dnskw | 25 + 1 file changed, 25 insertions(+) create mode 100644 doc/README.dnskw diff --git a/doc/README.dnskw b/doc/README.dnskw new file mode 100644 index 000..f9aaadc --- /dev/null +++ b/doc/README.dnskw @@ -0,0 +1,25 @@ +Overview + + +The DNS-kw are a low cost NAS based on Marvell SOC 88F6281-A1 aka kirkwood. +They are two supported NAS: +- dns 320 +- dns 325 + +Hardware + + + DNS-320DNS-325 +SoCMarvell 88F6281-A1 @800Mhz Marvell 88F6281-A1 @1200Mhz +RAM2xSEC K4T51083QG-HCE6:64Mx8 @333 CL5 (128MB total) 2xSEC K4T1G084QF-HCF7:128Mx8 @400 CL6 (256MB total) +Flash SAMSUNG 146 K9F1G08U0D SCB0 (128MB total) SAMSUNG 946 K9F1G08U0B PCB0 (128MB total) +PHY Marvell 88E1116R-NNC1 Marvell 88E1116R-NNC1 +PMUWeltrend WT69P803 Holtek HT48C06E + + +More information + + + http://jamie.lentin.co.uk/devices/dlink-dns320 + http://dns323.kood.org/dns-320 + http://sharecenter.dlink.com/products/DNS-320 -- 2.0.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] enbw_cmc, da850evm_direct_nor, and calimain vectors table misaligned (was: [PATCH] arm: fix a build error with CONFIG_USE_IRQ)
Hi Christian, On Wed, 2 Jul 2014 15:45:17 +0200, Christian Riesch christian.rie...@omicron.at wrote: Hello Albert, On Wed, Jun 18, 2014 at 2:55 PM, Christian Riesch christian.rie...@omicron.at wrote: Am I missing something here? What would be the preferred solution to make the board working again? Any comments on this? What shall we do to get the boards working again? Sorry for the delay. My opinion is that for these boards, there should actually be *no* exception vectors at the start of the image, since it would never serve any purpose anyway unless as you suggest we copy the vectors table from the image to the actual vectors table location (or set the VBAR to the image vector table location for those targets which allow it). (and I don't think this is limited to the three boards discussed here. IOW, the current exception/interrupt system in ARM U-Boot is FUBAR.) As far as fixing the boards, Masahiro had posted a series where one patch fixed the issue. I NAKed the submission for several reasons; I had expected a followup (v3) which I failed to ping for. MAsahiro: do you have a v3 ready? Thanks, Christian Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: sdhci: Fixed timeout for sdhci_send_command()
Tested-by: Steve Rae s...@broadcom.com
(does resolve the issue on our board!)
On 14-06-27 02:37 AM, Pantelis Antoniou wrote:
Hi Eli,
On Jun 12, 2014, at 12:41 PM, Eli Billauer wrote:
The current wait loop just reads the status 1 times, which makes the
actual timeout period platform-dependent. The udelay() call within the loop
makes the new timeout ~100 ms.
Signed-off-by: Eli Billauer eli.billa...@gmail.com
---
drivers/mmc/sdhci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 3125d13..80f3a91 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -226,6 +226,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
break;
if (--retry == 0)
break;
+ udelay(10);
} while ((stat mask) != mask);
if (retry == 0) {
--
1.7.2.3
Looking at the linux sources is no good, cause linux is interrupt driven.
This delay is used because the driver is not interrupt driven, so you have
to wait until the interrupt indication is delivered.
The only reference to interrupt latency I found is related to tuning and is
set to 50ms which I supposed is very pessimistic.
I think a timeout of 100ms would be fine.
Regards
-- Pantelis
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Re: [U-Boot] SPL broken on i.mx31 platforms
Hi Albert, On Fri, Jul 4, 2014 at 10:50 AM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau benoit.thebaudeau@gmail.com wrote: On Thu, Jul 3, 2014 at 3:35 PM, Albert ARIBAUD albert.u.b...@aribaud.net wrote: On Thu, 03 Jul 2014 10:19:39 +0200, Helmut Raiger helmut.rai...@hale.at wrote: On 07/03/2014 01:20 AM, Benoît Thébaudeau wrote: On Wed, Jul 2, 2014 at 9:04 AM, Helmut Raiger helmut.rai...@hale.at wrote: the commit 41623c91 breaks the SPL on i.mx31 platforms. Here, you are talking about mx31pdk, right? Actually im talking TT-01, but it has no contributed NAND boot code (which I was working on), but it should hit mx31pdk in the same way. This should answer Albert's question about the board. It does, thanks -- but I fail to see any SPL code built for TT-01. You're getting SPL issues with another target, right? Helmut seems to be working on a custom TT-01 variant (or just with a specific hardware configuration using dip switches, or jumpers, etc.) using the i.MX31 NAND internal boot rather than the mainline boot source. No, it will only be a minor change, I think, but I thought there might have been an additional intention behind the change to position dependent code. One could link the first part to 0xB800 (the original position of the SPL when loaded by the IPL) and the part after the relocation to CONFIG_SPL_TEXT_BASE. Actually, the ROM bootloader first copies the first NAND page to 0xB800. Then, the SPL placed here but linked at CONFIG_SPL_TEXT_BASE copies itself to CONFIG_SPL_TEXT_BASE in order to free the NFC buffer so that it can be used by the SPL. There is no relocation going on at this stage, but only a copy, and the SPL code size is limited to 2 kiB. Then, the SPL does its NAND load job towards CONFIG_SYS_TEXT_BASE and starts executing the non-SPL binary, which then relocates itself according to the heap size, etc. Ok, I think I'm getting it, but actually you don't need PIC (your code won't run at arbitrary locations), you need VMAs vs LMAs (your code will run partly at one location, partly at another, but will be loaded at only one of these locations). Therefore, we should be able to manage this in the linker script, by basically defining two output sections: the first one with a VMA and LMA equal to 0xB800 both, and which would contain the 'copier' code; and the second one with a VMA equal to CONFIG_SPL_TEXT_BASE (so that it links properly for running at that address) and a LMA equal to 0xB80 (so that it gets lumped with the first section in the less-than-2K ELF file produced by the linker. (actually we'd have several output sections with VMA==LMA, but it does not affect the core of the idea.) Does it make sense to you? It makes sense to me. That should work, but it'd be better to avoid adding a custom linker script. A simple fix in vectors.S would be preferable if possible. Also, the __image_copy_start stuff should be taken care of with such a change. I do not intend to have this in a custom linker script; I want this to be in the common ARM SPL linker script (I hope it is what Helmut's TT-01 changes use) -- I also want to get rid of all custom linker scripts in the ARM par of U-Boot, but I could not get this done for 2014.07. Looks good. BTW, I see that you skipped arch/arm/cpu/arm1136/u-boot-spl.lds in commit 41623c91 (addition of *(.vectors)). Was it intentional? Not that I can remember: I did modify the arm1136 start.S, so te linker scripts should have followed. OK. There seems to be the same issue for board/ait/cam_enc_4xx/u-boot-spl.lds . All the ARM arch and ARM boards linker scripts should probably be rechecked. It silently changes woodburn_sd because the fallback exception vectors no longer exist. This should not cause a build error because the _start symbol is duplicated in this linker script. The board may also boot correctly with this, but the default vectors can be useful in some cases, especially for debugging exceptions. Can you post a patch today? I'll pull it in a PR I'll do today before COB. Sorry, I can't before next week at best. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: Fix armv8 compilation error
Hi Darwin, On Mon, 9 Jun 2014 13:25:52 -0700, Darwin Rambo dra...@broadcom.com wrote: From: Shaibal.Dutta shaibal.du...@broadcom.com Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta shaibal.du...@broadcom.com Signed-off-by: Darwin Rambo dra...@broadcom.com Reviewed-by: Darwin Rambo dra...@broadcom.com --- I don't get any such error. Which board and which compiler does it appear for? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPL broken on i.mx31 platforms
Hi Magnus, On Fri, Jul 4, 2014 at 12:42 PM, Magnus Lilja lilja.mag...@gmail.com wrote: Hi all, (I hope gmail formats this mail according to the mailing list requirements, my apologies if it doesn't) I think that HTML is forbidden. You can switch Gmail to plain text mode with the More options down arrow in the lower right corner of the composing frame. On 4 July 2014 10:50, Albert ARIBAUD albert.u.b...@aribaud.net wrote: Hi Benoît, On Thu, 3 Jul 2014 22:58:56 +0200, Benoît Thébaudeau benoit.thebaudeau@gmail.com wrote: Hi Albert, It makes sense to me. That should work, but it'd be better to avoid adding a custom linker script. A simple fix in vectors.S would be preferable if possible. Also, the __image_copy_start stuff should be taken care of with such a change. I do not intend to have this in a custom linker script; I want this to be in the common ARM SPL linker script (I hope it is what Helmut's TT-01 changes use) -- I also want to get rid of all custom linker scripts in the ARM par of U-Boot, but I could not get this done for 2014.07. I have access to i.MX31 board (PDK) and can definitely help testing any patch to this problem. Thanks, that will help. The first things to test will be: - confirm the issue on mx31pdk with mainline, - confirm that reverting commit 41623c91 on top of mainline is sufficient to fix the issue, - test from mainline whether removing the two _reset lines in vectors.S and adding b reset or bl reset right after _start: (still in vectors.S) fixes the issue or improves things in any way. However, I won't be able to do any verification until beginning of August. No problem. Maybe Helmut will make some progress in the meantime. Regards, Benoît ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] gpio: spear_gpio: Fix gpio_set_value() implementation
Hi Axel,
On Mon, 16 Sep 2013 08:35:41 +0800, Axel Lin axel@ingics.com
wrote:
In current gpio_set_value() implementation, it always sets the gpio control
bit
no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
This patch fixes this bug.
The address bus is used as a mask on read/write operations, so that
independent
software drivers can set their GPIO bits without affecting any other pins in a
single write operation. Thus we don't need a read-modify-write to update the
register.
Signed-off-by: Axel Lin axel@ingics.com
Acked-by: Stefan Roese s...@denx.de
Reviewed-by: Vipin Kumar vipin.ku...@st.com
Reviewed-by: Michael Trimarchi mich...@amarulasolutions.com
---
v2: Update commit log to explain why a read-modify-write is not necessary
for clearing specific GPIO bit.
Also added Michael Trimarchi's reviewed-by tag since he does review the
patch and said the patch is fine.
drivers/gpio/spear_gpio.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index 367b670..6fb4117 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -36,7 +36,10 @@ int gpio_set_value(unsigned gpio, int value)
{
struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
- writel(1 gpio, regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1 gpio, regs-gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0, regs-gpiodata[DATA_REG_ADDR(gpio)]);
return 0;
}
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH v5 2/2] socfpga: Adding DesignWare watchdog support
Hi Chin, On Tue, 10 Jun 2014 01:11:04 -0500, Chin Liang See cl...@altera.com wrote: To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See cl...@altera.com Cc: Anatolij Gustschin ag...@denx.de Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Heiko Schocher h...@denx.de Cc: Tom Rini tr...@ti.com --- Changes for v5 - Updated to latest code branch Changes for v4 - Updated to latest code branch Changes for v3 - Split to 2 series patch Changes for v2 - Enable this driver at socfpga_cyclone5 board --- .../include/asm/arch-socfpga/socfpga_base_addrs.h |1 + include/configs/socfpga_cyclone5.h | 14 ++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046..f2ecbbd 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,6 +11,7 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd0 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0254249..34291c7 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -206,6 +206,17 @@ #define CONFIG_ENV_IS_NOWHERE /* + * L4 Watchdog + */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS2000 +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +/* Clocks source frequency to watchdog timer */ +#define CONFIG_DW_WDT_CLOCK_KHZ 25000 + + +/* * SPL Second Program Loader aka Initial Software */ @@ -237,4 +248,7 @@ /* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT +/* Support for watchdog */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + #endif /* __CONFIG_H */ Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] watchdog/denali: Adding DesignWare watchdog driver support
Hi Chin,
On Tue, 10 Jun 2014 01:10:21 -0500, Chin Liang See cl...@altera.com
wrote:
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
---
Changes for v5
- Updated to latest code branch
Changes for v4
- Added static for local function
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
drivers/watchdog/Makefile |1 +
drivers/watchdog/designware_wdt.c | 74
+
2 files changed, 75 insertions(+)
create mode 100644 drivers/watchdog/designware_wdt.c
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 06ced10..0276a10 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
+obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
diff --git a/drivers/watchdog/designware_wdt.c
b/drivers/watchdog/designware_wdt.c
new file mode 100644
index 000..e788e1b
--- /dev/null
+++ b/drivers/watchdog/designware_wdt.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include asm/utils.h
+
+#define DW_WDT_CR0x00
+#define DW_WDT_TORR 0x04
+#define DW_WDT_CRR 0x0C
+
+#define DW_WDT_CR_EN_OFFSET 0x00
+#define DW_WDT_CR_RMOD_OFFSET0x01
+#define DW_WDT_CR_RMOD_VAL 0x00
+#define DW_WDT_CRR_RESTART_VAL 0x76
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int designware_wdt_settimeout(unsigned int timeout)
+{
+ signed int i;
+
+ /* calculate the timeout range value */
+ i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
+ if (i 15)
+ i = 15;
+ if (i 0)
+ i = 0;
+
+ writel((i | (i 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
+ return 0;
+}
+
+static void designware_wdt_enable(void)
+{
+ writel(((DW_WDT_CR_RMOD_VAL DW_WDT_CR_RMOD_OFFSET) |
+ (0x1 DW_WDT_CR_EN_OFFSET)),
+ (CONFIG_DW_WDT_BASE + DW_WDT_CR));
+}
+
+static unsigned int designware_wdt_is_enabled(void)
+{
+ unsigned long val;
+ val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
+ return val 0x1;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ if (designware_wdt_is_enabled())
+ /* restart the watchdog counter */
+ writel(DW_WDT_CRR_RESTART_VAL,
+(CONFIG_DW_WDT_BASE + DW_WDT_CRR));
+}
+
+void hw_watchdog_init(void)
+{
+ /* reset to disable the watchdog */
+ hw_watchdog_reset();
+ /* set timer in miliseconds */
+ designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS);
+ /* enable the watchdog */
+ designware_wdt_enable();
+ /* reset the watchdog */
+ hw_watchdog_reset();
+}
+#endif
Applied to u-boot-arm/master, thanks!
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH v8] socfpga: Adding Scan Manager driver
Hi Chin,
On Tue, 10 Jun 2014 01:17:42 -0500, Chin Liang See cl...@altera.com
wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v8
- Updated to latest code branch
Changes for v7
- Enhance the function scan_chain_engine_is_idle
Changes for v6
- Fixed various coding style issue
Changes for v5
- Removal of additional blank line
- Added comment for magic number
Changes for v4
- avoid code duplication by add goto error
- include underscore to variables name
Changes for v3
- merge the handoff file and driver into single patch
Changes for v2
- rebase with latest v2014.01-rc1
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++
arch/arm/cpu/armv7/socfpga/spl.c |4 +
arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++
.../include/asm/arch-socfpga/socfpga_base_addrs.h |1 +
board/altera/socfpga/iocsr_config.c| 657
board/altera/socfpga/iocsr_config.h| 17 +
include/configs/socfpga_cyclone5.h |1 +
8 files changed, 980 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c
create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h
create mode 100644 board/altera/socfpga/iocsr_config.c
create mode 100644 board/altera/socfpga/iocsr_config.h
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile
b/arch/arm/cpu/armv7/socfpga/Makefile
index cbe1d40..eb33f2c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
obj-y:= lowlevel_init.o
obj-y+= misc.o timer.o reset_manager.o system_manager.o
clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/scan_manager.c
b/arch/arm/cpu/armv7/socfpga/scan_manager.c
new file mode 100644
index 000..a820b1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/scan_manager.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/freeze_controller.h
+#include asm/arch/scan_manager.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+ (void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+ uint32_t scanmgr_status;
+
+ scanmgr_status = readl(scan_manager_base-stat);
+
+ /* Poll the engine until the scan engine is inactive */
+ while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+ (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) 0)) {
+ max_iter--;
+ if (max_iter 0)
+ scanmgr_status = readl(scan_manager_base-stat);
+ else
+ return 0;
+ }
+ return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+ uint32_t io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
+{
+ uint16_t tdi_tdo_header;
+ uint32_t io_program_iter;
+ uint32_t io_scan_chain_data_residual;
+ uint32_t residual;
+ uint32_t i;
+ uint32_t index = 0;
+
+ /*
+ * De-assert reinit if the IO scan chain is intended for HIO. In
+ * this, its the chain 3.
+ */
+ if (io_scan_chain_id == 3)
+ clrbits_le32(freeze_controller_base-hioctrl,
+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+ /*
+ * Check if the scan chain engine is inactive and the
+ * WFIFO is empty before enabling the IO scan chain
+ */
+ if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+ return 1;
+
+ /*
+ * Enable IO Scan chain based on scan chain id
+ * Note: only one chain can be enabled at a time
+ */
+ setbits_le32(scan_manager_base-en, 1 io_scan_chain_id);
+
+ /*
+ * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+ * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+ */
+ io_program_iter =
Re: [U-Boot] [PATCH] arm: Fix armv8 compilation error
Albert, I don't think that there is any code currently submitted that triggers this error. (it is hidden inside inline functions...) However, you could add one line of code 'anywhere' to test this: test_and_set_bit(1, (volatile void *)0x12345678); Thanks, Steve PS. - using: gcc-linaro-aarch64-linux-gnu-4.8-2014.01_linux/bin/aarch64-linux-gnu- - and:./MAKEALL -a aarch64 On 14-07-04 02:41 PM, Albert ARIBAUD wrote: Hi Darwin, On Mon, 9 Jun 2014 13:25:52 -0700, Darwin Rambo dra...@broadcom.com wrote: From: Shaibal.Dutta shaibal.du...@broadcom.com Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta shaibal.du...@broadcom.com Signed-off-by: Darwin Rambo dra...@broadcom.com Reviewed-by: Darwin Rambo dra...@broadcom.com --- I don't get any such error. Which board and which compiler does it appear for? Amicalement, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-arm/master
Hello, The following changes since commit fe8b3212b7938861eacdefe6115810303a96f9cc: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-07-02 16:38:02 -0400) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 4009bed4694892716d280fcb088899b566c5c986: Reformat boards.cfg (2014-07-05 00:36:57 +0200) Albert ARIBAUD (1): Reformat boards.cfg Axel Lin (1): gpio: spear_gpio: Fix gpio_set_value() implementation Chin Liang See (3): watchdog/denali: Adding DesignWare watchdog driver support socfpga: Adding DesignWare watchdog support socfpga: Adding Scan Manager driver Darwin Rambo (1): arm: Add support for semihosting for armv8 fastmodel targets. J. German Rivera (2): Added 64-bit MMIO accessors for ARMv8 armv8/fsl-lsch3: Add support to load and start MC Firmware Jeroen Hofstee (1): ARM: cache_v7: use __weak Sergey Kostanbaev (1): arm: ep9315: Return back Cirrus Logic EDB9315A board support York Sun (3): ARMv8: Adjust MMU setup ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support README | 27 + arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S| 463 - arch/arm/cpu/armv7/cache_v7.c | 45 ++-- arch/arm/cpu/armv7/socfpga/Makefile| 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/cpu/armv8/cache_v8.c | 57 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 9 ++ arch/arm/cpu/armv8/fsl-lsch3/README| 10 ++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 436 + arch/arm/cpu/armv8/fsl-lsch3/cpu.h | 7 ++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S| 65 +++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 176 ++ arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 ++ arch/arm/include/asm/arch-ep93xx/ep93xx.h | 85 +++ arch/arm/include/asm/arch-fsl-lsch3/clock.h | 23 arch/arm/include/asm/arch-fsl-lsch3/config.h | 65 +++ arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 ++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 116 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 +++ arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++ arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h | 2 + arch/arm/include/asm/armv8/mmu.h | 24 arch/arm/include/asm/cache.h | 3 + arch/arm/include/asm/config.h | 4 + arch/arm/include/asm/io.h | 8 ++ arch/arm/include/asm/semihosting.h | 21 arch/arm/include/asm/system.h | 2 + arch/arm/lib/Makefile | 1 + arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/cache.c | 13 +-- arch/arm/lib/semihosting.c | 233 +++ board/altera/socfpga/iocsr_config.c| 657 ++ board/altera/socfpga/iocsr_config.h| 17 +++ board/armltd/vexpress64/vexpress64.c | 101 - board/cirrus/edb93xx/Makefile | 11 ++ board/cirrus/edb93xx/edb93xx.c | 382 board/cirrus/edb93xx/u-boot.lds| 115 board/freescale/ls2085a/Makefile | 8 ++ board/freescale/ls2085a/README | 16 +++ board/freescale/ls2085a/ddr.c | 175 ++ board/freescale/ls2085a/ddr.h | 57 ++ board/freescale/ls2085a/ls2085a.c | 100 + boards.cfg | 17 ++- doc/README.semihosting | 54 + drivers/gpio/spear_gpio.c | 5 +- drivers/i2c/mxc_i2c.c | 5 + drivers/net/Makefile | 1 + drivers/net/fsl_mc/Makefile
Re: [U-Boot] Pull request: u-boot-arm/master
On Sat, Jul 05, 2014 at 12:57:22AM +0200, Albert ARIBAUD wrote: Hello, The following changes since commit fe8b3212b7938861eacdefe6115810303a96f9cc: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-07-02 16:38:02 -0400) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 4009bed4694892716d280fcb088899b566c5c986: Reformat boards.cfg (2014-07-05 00:36:57 +0200) Albert ARIBAUD (1): Reformat boards.cfg Axel Lin (1): gpio: spear_gpio: Fix gpio_set_value() implementation Chin Liang See (3): watchdog/denali: Adding DesignWare watchdog driver support socfpga: Adding DesignWare watchdog support socfpga: Adding Scan Manager driver Darwin Rambo (1): arm: Add support for semihosting for armv8 fastmodel targets. J. German Rivera (2): Added 64-bit MMIO accessors for ARMv8 armv8/fsl-lsch3: Add support to load and start MC Firmware Jeroen Hofstee (1): ARM: cache_v7: use __weak Sergey Kostanbaev (1): arm: ep9315: Return back Cirrus Logic EDB9315A board support York Sun (3): ARMv8: Adjust MMU setup ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support README | 27 + arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S| 463 - arch/arm/cpu/armv7/cache_v7.c | 45 ++-- arch/arm/cpu/armv7/socfpga/Makefile| 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 209 +++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/cpu/armv8/cache_v8.c | 57 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 9 ++ arch/arm/cpu/armv8/fsl-lsch3/README| 10 ++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 436 + arch/arm/cpu/armv8/fsl-lsch3/cpu.h | 7 ++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S| 65 +++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 176 ++ arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 ++ arch/arm/include/asm/arch-ep93xx/ep93xx.h | 85 +++ arch/arm/include/asm/arch-fsl-lsch3/clock.h | 23 arch/arm/include/asm/arch-fsl-lsch3/config.h | 65 +++ arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 ++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 116 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 +++ arch/arm/include/asm/arch-socfpga/scan_manager.h | 90 +++ arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h | 2 + arch/arm/include/asm/armv8/mmu.h | 24 arch/arm/include/asm/cache.h | 3 + arch/arm/include/asm/config.h | 4 + arch/arm/include/asm/io.h | 8 ++ arch/arm/include/asm/semihosting.h | 21 arch/arm/include/asm/system.h | 2 + arch/arm/lib/Makefile | 1 + arch/arm/lib/cache-cp15.c | 9 +- arch/arm/lib/cache.c | 13 +-- arch/arm/lib/semihosting.c | 233 +++ board/altera/socfpga/iocsr_config.c| 657 ++ board/altera/socfpga/iocsr_config.h| 17 +++ board/armltd/vexpress64/vexpress64.c | 101 - board/cirrus/edb93xx/Makefile | 11 ++ board/cirrus/edb93xx/edb93xx.c | 382 board/cirrus/edb93xx/u-boot.lds| 115 board/freescale/ls2085a/Makefile | 8 ++ board/freescale/ls2085a/README | 16 +++ board/freescale/ls2085a/ddr.c | 175 ++ board/freescale/ls2085a/ddr.h | 57 ++ board/freescale/ls2085a/ls2085a.c | 100 + boards.cfg | 17 ++- doc/README.semihosting | 54 + drivers/gpio/spear_gpio.c |
