[U-Boot] [PATCH v2 13/19] ARM: dts: rockchip: prefer u-boot, dm-pre-reloc rather than u-boot, dm-spl

[Paweł Jarosz]

rk3xxx.dtsi is used by rk3188 and rk3066. rk3188 uses alocated data in spl but 
rk3066 needs it in tpl.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 arch/arm/dts/rk3xxx.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi
index 6d9e36d..d1c205b 100644
--- a/arch/arm/dts/rk3xxx.dtsi
+++ b/arch/arm/dts/rk3xxx.dtsi
@@ -135,7 +135,7 @@
};
 
noc: syscon@10128000 {
-   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
compatible = "rockchip,rk3188-noc", "syscon";
reg = <0x10128000 0x2000>;
};
@@ -218,13 +218,13 @@
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
reg = <0x20004000 0x100>;
-   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
};
 
grf: grf@20008000 {
compatible = "syscon";
reg = <0x20008000 0x200>;
-   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
};
 
dmc: dmc@2002 {
@@ -238,7 +238,7 @@
   0x2004 0x294>;
clocks = < PCLK_DDRUPCTL>, < PCLK_PUBL>;
clock-names = "pclk_ddrupctl", "pclk_publ";
-   u-boot,dm-spl;
+   u-boot,dm-pre-reloc;
};
 
i2c0: i2c@2002d000 {
-- 
2.7.4

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[U-Boot] [PATCH v2 15/19] mmc: dw_mmc: rockchip: add support for rk3066 sdmmc

[Paweł Jarosz]

This patch enables support for the Rockchip RK3066 SD/MMC controller, which is 
based on Designware IP. The device supports SD, SDIO, MMC and eMMC.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- dropped OF_PLATDATA

 drivers/mmc/rockchip_dw_mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index e7fcf89..a879fcd 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -160,6 +160,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
 
 static const struct udevice_id rockchip_dwmmc_ids[] = {
{ .compatible = "rockchip,rk3288-dw-mshc" },
+   { .compatible = "rockchip,rk2928-dw-mshc" },
{ }
 };
 
-- 
2.7.4

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[U-Boot] [PATCH v2 14/19] mmc: dw_mmc: support transfer mode autodetection

[Paweł Jarosz]

dw_mmc supports two transfer modes in u-boot: idma and fifo.
This patch adds autodetection of transfer mode and eliminates setting this in 
host config struct

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 drivers/mmc/dw_mmc.c | 8 
 include/dwmmc.h  | 4 
 2 files changed, 12 insertions(+)

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 700f764..2cc4d67 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -428,6 +428,7 @@ static int dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
struct dwmci_host *host = mmc->priv;
+   uint32_t use_dma;
 
if (host->board_init)
host->board_init(host);
@@ -439,6 +440,13 @@ static int dwmci_init(struct mmc *mmc)
return -EIO;
}
 
+   use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON));
+   if (use_dma == DMA_INTERFACE_IDMA) {
+   host->fifo_mode = 0;
+   } else {
+   host->fifo_mode = 1;
+   }
+
/* Enumerate at 400KHz */
dwmci_setup_bus(host, mmc->cfg->f_min);
 
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 4dda009..269536d 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -115,6 +115,10 @@
 #define RX_WMARK_SHIFT 16
 #define RX_WMARK_MASK  (0xfff << RX_WMARK_SHIFT)
 
+/* HCON Register */
+#define DMA_INTERFACE_IDMA (0x0)
+#define SDMMC_GET_TRANS_MODE(x)(((x)>>16) & 0x3)
+
 #define DWMCI_IDMAC_OWN(1 << 31)
 #define DWMCI_IDMAC_CH (1 << 4)
 #define DWMCI_IDMAC_FS (1 << 3)
-- 
2.7.4

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[U-Boot] [PATCH v2 12/19] rockchip: board: rk3066: convert board_usb_init to live tree functions

[Paweł Jarosz]

Use live tree functions to fill dwc2_plat_otg_data structure in board_usb_init.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 arch/arm/mach-rockchip/rk3066-board.c | 52 +--
 1 file changed, 7 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3066-board.c 
b/arch/arm/mach-rockchip/rk3066-board.c
index 8fa06a2..2b96eb2 100644
--- a/arch/arm/mach-rockchip/rk3066-board.c
+++ b/arch/arm/mach-rockchip/rk3066-board.c
@@ -90,55 +90,17 @@ static struct dwc2_plat_otg_data rk3066_otg_data = {
 
 int board_usb_init(int index, enum usb_init_type init)
 {
-   int node, phy_node;
-   const char *mode;
-   bool matched = false;
-   const void *blob = gd->fdt_blob;
-   u32 grf_phy_offset;
-
-   /* find the usb_otg node */
-   node = fdt_node_offset_by_compatible(blob, -1,
-   "rockchip,rk3066-usb");
-
-   while (node > 0) {
-   mode = fdt_getprop(blob, node, "dr_mode", NULL);
-   if (mode && strcmp(mode, "otg") == 0) {
-   matched = true;
-   break;
-   }
-
-   node = fdt_node_offset_by_compatible(blob, node,
-   "rockchip,rk3066-usb");
-   }
-   if (!matched) {
-   debug("Not found usb_otg device\n");
-   return -ENODEV;
-   }
-   rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+   ofnode otg_node;
+   u32 reg;
 
-   node = fdtdec_lookup_phandle(blob, node, "phys");
-   if (node <= 0) {
-   debug("Not found usb phy device\n");
+   otg_node = ofnode_path("/usb@1018");
+   if (!ofnode_valid(otg_node)) {
+   debug("Not found usb otg device\n");
return -ENODEV;
}
 
-   phy_node = fdt_parent_offset(blob, node);
-   if (phy_node <= 0) {
-   debug("Not found usb phy device\n");
-   return -ENODEV;
-   }
-
-   rk3066_otg_data.phy_of_node = phy_node;
-   grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-   node = fdt_node_offset_by_compatible(blob, -1,
-   "rockchip,rk3066-grf");
-   if (node <= 0) {
-   debug("Not found grf device\n");
-   return -ENODEV;
-   }
-   rk3066_otg_data.regs_phy = grf_phy_offset +
-   fdtdec_get_addr(blob, node, "reg");
+   ofnode_read_u32(otg_node, "reg", );
+   rk3066_otg_data.regs_otg = reg;
 
return dwc2_udc_probe(_otg_data);
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 18/19] dfu: fix spl build

[Paweł Jarosz]

In current state dfu depends on cmd/mtdparts.c which isn't build in SPL.
This patch resolves it by cutting out unwanted code in SPL build.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 drivers/dfu/dfu_nand.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index 6dc9ff7..a196233 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -192,8 +192,9 @@ unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu)
 int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s)
 {
char *st;
+#ifndef CONFIG_SPL_BUILD
int ret, dev, part;
-
+#endif
dfu->data.nand.ubi = 0;
dfu->dev_type = DFU_DEV_NAND;
st = strsep(, " ");
@@ -203,6 +204,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char 
*devstr, char *s)
s++;
dfu->data.nand.size = simple_strtoul(s, , 16);
} else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) {
+#ifndef CONFIG_SPL_BUILD
char mtd_id[32];
struct mtd_device *mtd_dev;
u8 part_num;
@@ -220,6 +222,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char 
*devstr, char *s)
mtdparts_init();
 
ret = find_dev_and_part(mtd_id, _dev, _num, );
+
if (ret != 0) {
printf("Could not locate '%s'\n", mtd_id);
return -1;
@@ -229,6 +232,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char 
*devstr, char *s)
dfu->data.nand.size = pi->size;
if (!strcmp(st, "partubi"))
dfu->data.nand.ubi = 1;
+#endif
} else {
printf("%s: Memory layout (%s) not supported!\n", __func__, st);
return -1;
-- 
2.7.4

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[U-Boot] [PATCH v2 19/19] mtd: nand: spl: allow build nand_bbt, nand_ids and nand_util

[Paweł Jarosz]

This patch allows building of nand_bbt, nand_ids, nand_util for nand drivers 
that need it.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 drivers/mtd/nand/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 0659253..9062c2e 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -18,6 +18,9 @@ obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
 obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
 obj-$(CONFIG_SPL_NAND_INIT) += nand.o
+obj-$(CONFIG_SPL_NAND_BBT) += nand_bbt.o
+obj-$(CONFIG_SPL_NAND_IDS) += nand_ids.o
+obj-$(CONFIG_SPL_NAND_UTIL) += nand_util.o
 ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
 obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
 endif
-- 
2.7.4

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[U-Boot] [PATCH v2 16/19] armv7: support rk3066 early back to bootrom in vector.S

[Paweł Jarosz]

Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
executes it. Then waits for back to bootrom and loads another 32KB to sram
which also executes. Sdram initialisation code needs to be in one of these two
steps. Then bootloader loads another ~200KB of data at offset 0x6000
and jumps to it.

32KB of data is a little low for tpl + spl part and ~200KB data is to low for
u-boot part(for example to boot from mmc you need to disable usb support.

My solution to size problem is to move sdram initialisation code to tpl stage,
move spl part to third stage(reading 200KB data) and add support for loading
u-boot by spl from ext2/4, fat partitions.

But moving sdram initialisation code to tpl increases size of tpl above 1KB
(first boot stage). Solution to this is to add code which will be below 1KB
offset in tpl binary and do back to bootrom at very beginning of the tpl
execution.

Adding this few lines of code here meets these conditions.

Signed-off-by: Paweł Jarosz 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- moved to vector.S

 arch/arm/include/asm/arch-rockchip/boot0.h | 14 ++
 arch/arm/lib/vectors.S | 18 +-
 configs/mk808_defconfig|  1 +
 3 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h 
b/arch/arm/include/asm/arch-rockchip/boot0.h
index 72d264b..4179448 100644
--- a/arch/arm/include/asm/arch-rockchip/boot0.h
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -5,6 +5,19 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
+#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
+   ldr r3, =0x10080900
+   ldr r0, [r3]
+   cmp r0, #1
+   movne   r0, #1
+   strne   r0, [r3]
+   beq out_of_bootrom
+   bx  lr
+out_of_bootrom:
+   mov r0, #0
+   str r0, [r3]
+#endif
+
 /*
  * Execution starts on the instruction following this 4-byte header
  * (containing the magic 'RK33').
@@ -26,6 +39,7 @@
 */
b reset  /* may be overwritten --- should be 'nop' or a 'b reset' */
 #endif
+
b reset
 
 #if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 1019091..e3c18da 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -47,6 +47,15 @@
 
 _start:
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include 
+#endif
+
 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word   CONFIG_SYS_DV_NOR_BOOT_CFG
 #endif
@@ -60,15 +69,6 @@ _start:
ldr pc, _irq
ldr pc, _fiq
 
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
-/*
- * Various SoCs need something special and SoC-specific up front in
- * order to boot, allow them to set that in their boot0.h file and then
- * use it here.
- */
-#include 
-#endif
-
 /*
  *
  *
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index ab67e4f..bf4af82 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -13,6 +13,7 @@ CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 CONFIG_SYS_NS16550=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_BOOTDELAY=1
 CONFIG_CONSOLE_MUX=y
 CONFIG_DISPLAY_BOARDINFO=y
-- 
2.7.4

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[U-Boot] [PATCH v2 17/19] rockchip: sysreset: deduplicate rk3066 and rk3188 sysreset drivers

[Paweł Jarosz]

Sysreset drivers for rk3066 and rk3188 contain common elements which can be 
reused.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 .../include/asm/arch-rockchip/sysreset_common.h| 20 +++
 arch/arm/mach-rockchip/Makefile|  3 ++
 arch/arm/mach-rockchip/sysreset-common.c   | 39 ++
 drivers/sysreset/sysreset_rk3066.c | 34 ++-
 drivers/sysreset/sysreset_rk3188.c | 35 ++-
 5 files changed, 84 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/sysreset_common.h
 create mode 100644 arch/arm/mach-rockchip/sysreset-common.c

diff --git a/arch/arm/include/asm/arch-rockchip/sysreset_common.h 
b/arch/arm/include/asm/arch-rockchip/sysreset_common.h
new file mode 100644
index 000..c7e1fc0
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sysreset_common.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_SYSRESET_COMMON_H
+#define _ASM_ARCH_SYSRESET_COMMON_H
+
+struct rockchip_sysreset_data {
+   void *grf_soc_con0;
+   uint32_t noc_remap_mask;
+   void *cru_mode_con;
+   void *cru_glb_srst_snd_value;
+   void *cru_glb_srst_fst_value;
+};
+
+int rockchip_sysreset_request(struct rockchip_sysreset_data *data,
+ enum sysreset_t type);
+#endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index ae878ef..b58a9c4 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,6 +11,9 @@
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 
+obj-$(CONFIG_ROCKCHIP_RK3066) += sysreset-common.o
+obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset-common.o
+
 obj-tpl-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
diff --git a/arch/arm/mach-rockchip/sysreset-common.c 
b/arch/arm/mach-rockchip/sysreset-common.c
new file mode 100644
index 000..41e76e3
--- /dev/null
+++ b/arch/arm/mach-rockchip/sysreset-common.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int rockchip_sysreset_request(struct rockchip_sysreset_data *data,
+ enum sysreset_t type)
+{
+   switch (type) {
+   case SYSRESET_WARM:
+   /*
+* warm-reset keeps the remap value,
+* so make sure it's disabled.
+*/
+   rk_clrsetreg(data->grf_soc_con0,
+   data->noc_remap_mask, 0);
+
+   rk_clrreg(data->cru_mode_con, 0x);
+   writel(0xeca8, data->cru_glb_srst_snd_value);
+   break;
+   case SYSRESET_COLD:
+   rk_clrreg(data->cru_mode_con, 0x);
+   writel(0xfdb9, data->cru_glb_srst_fst_value);
+   break;
+   default:
+   return -EPROTONOSUPPORT;
+   }
+
+   return -EINPROGRESS;
+}
diff --git a/drivers/sysreset/sysreset_rk3066.c 
b/drivers/sysreset/sysreset_rk3066.c
index b5dcb9a..f82b3dd 100644
--- a/drivers/sysreset/sysreset_rk3066.c
+++ b/drivers/sysreset/sysreset_rk3066.c
@@ -14,40 +14,28 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
struct rk3066_cru *cru = rockchip_get_cru();
-   struct rk3066_grf *grf;
+   struct rk3066_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   struct rockchip_sysreset_data data = {
+   .grf_soc_con0 = >soc_con0,
+   .noc_remap_mask = NOC_REMAP_MASK,
+   .cru_mode_con = >cru_mode_con,
+   .cru_glb_srst_snd_value = >cru_glb_srst_snd_value,
+   .cru_glb_srst_fst_value = >cru_glb_srst_fst_value
+   };
 
if (IS_ERR(cru))
return PTR_ERR(cru);
 
-   switch (type) {
-   case SYSRESET_WARM:
-   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-   if (IS_ERR(grf))
-   return -EPROTONOSUPPORT;
-   /*
-* warm-reset keeps the remap value,
-* so make sure it's disabled.
-*/
-   rk_clrsetreg(>soc_con0,
-   NOC_REMAP_MASK, 0 << NOC_REMAP_SHIFT);
-
-   rk_clrreg(>cru_mode_con, 0x);
-   writel(0xeca8, >cru_glb_srst_snd_value);
-   break;
-   case SYSRESET_COLD:
-   rk_clrreg(>cru_mode_con, 0x);
-   

[U-Boot] [PATCH v2 11/19] rockchip: mkimage: add support for rockchip nand boot image

[Paweł Jarosz]

The Rockchip boot ROM requires a particular file format for booting from NAND:

* It starts with 512-byte, rc4 encoded header and is aligned to nand page size

* Then first 2KB of first stage loader (tpl) aligned to nand page size
* n empty pages

* second 2KB of first stage loader (tpl) aligned to nand page size
* n empty pages

* ...

* first 2KB of second stage loader (spl) aligned to nand page size
* n empty pages

* second 2KB of first stage loader (spl) aligned to nand page size
* n empty pages

* ...

Size of spl and tpl must be aligned to 2KB.

example usage for nand with page size 16384 and one empty page in iteration:

# mkimage -n rk3066 -T rknand -d 
./u-boot/tpl/u-boot-tpl.bin:./u-boot/spl/u-boot-spl.bin -X 16384,1 out

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 common/image.c|   1 +
 include/image.h   |   1 +
 tools/Makefile|   2 +-
 tools/imagetool.h |   1 +
 tools/mkimage.c   |   8 ++-
 tools/rkcommon.c  |  10 ++--
 tools/rkcommon.h  |  10 +++-
 tools/rknand.c| 156 ++
 tools/rksd.c  |   2 +-
 tools/rkspi.c |   2 +-
 10 files changed, 183 insertions(+), 10 deletions(-)
 create mode 100644 tools/rknand.c

diff --git a/common/image.c b/common/image.c
index 0f88984..1d677bc 100644
--- a/common/image.c
+++ b/common/image.c
@@ -167,6 +167,7 @@ static const table_entry_t uimage_type[] = {
{   IH_TYPE_FPGA,   "fpga",   "FPGA Image" },
{   IH_TYPE_TEE,"tee","Trusted Execution 
Environment Image",},
{   IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" 
},
+   {   IH_TYPE_RKNAND, "rknand", "Rockchip NAND Boot Image" },
{   -1, "",   "",   },
 };
 
diff --git a/include/image.h b/include/image.h
index c6f1513..7d90f36 100644
--- a/include/image.h
+++ b/include/image.h
@@ -269,6 +269,7 @@ enum {
IH_TYPE_VYBRIDIMAGE,/* VYBRID .vyb Image */
IH_TYPE_TEE,/* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT,   /* Firmware Image with HABv4 IVT */
+   IH_TYPE_RKNAND, /* Rockchip NAND Boot Image */
 
IH_TYPE_COUNT,  /* Number of image types */
 };
diff --git a/tools/Makefile b/tools/Makefile
index 0743677..52858bc 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -79,7 +79,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
 
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rknand.o rksd.o rkspi.o
 
 # common objs for dumpimage and mkimage
 dumpimage-mkimage-objs := aisimage.o \
diff --git a/tools/imagetool.h b/tools/imagetool.h
index a8d5054..0b2a707 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -77,6 +77,7 @@ struct image_tool_params {
bool quiet; /* Don't output text in normal operation */
unsigned int external_offset;   /* Add padding to external data */
const char *engine_id;  /* Engine to use for signing */
+   char *extraparams;  /* Extra parameters for img creation (-X) */
 };
 
 /*
diff --git a/tools/mkimage.c b/tools/mkimage.c
index 28ff35e..ffc91d2 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -144,7 +144,7 @@ static void process_args(int argc, char **argv)
int opt;
 
while ((opt = getopt(argc, argv,
-"a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qsT:vVx")) 
!= -1) {
+
"a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:N:p:O:rR:qsT:vVxX:")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, , 16);
@@ -279,6 +279,9 @@ static void process_args(int argc, char **argv)
case 'x':
params.xflag++;
break;
+   case 'X':
+   params.extraparams = optarg;
+   break;
default:
usage("Invalid option");
}
@@ -416,7 +419,8 @@ int main(int argc, char **argv)
exit (retval);
}
 
-   if ((params.type != IH_TYPE_MULTI) && (params.type != IH_TYPE_SCRIPT)) {
+   if ((params.type != IH_TYPE_MULTI) && (params.type != IH_TYPE_SCRIPT) &&
+   (params.type != IH_TYPE_RKNAND)) {
dfd = open(params.datafile, O_RDONLY | O_BINARY);
if (dfd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 04e8272..a2f2160 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -73,6 +73,7 @@ struct spl_info {
 
 static struct spl_info spl_infos[] = {
{ "rk3036", "RK30", 0x1000, 

[U-Boot] [PATCH v2 10/19] mtd: nand: add the rockchip nand controller driver

[Paweł Jarosz]

Add basic Rockchip nand driver.

Driver in current state has 16, 24, 40, 60 per 1024B BCH/ECC ability and 8 bit 
asynchronous flash interface support. Other features will come later.

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 drivers/mtd/nand/Kconfig |   6 +
 drivers/mtd/nand/Makefile|   1 +
 drivers/mtd/nand/rockchip_nand.c | 660 +++
 include/fdtdec.h |   1 +
 lib/fdtdec.c |   1 +
 5 files changed, 669 insertions(+)
 create mode 100644 drivers/mtd/nand/rockchip_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3508c62..57a870d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -66,6 +66,12 @@ config NAND_PXA3XX
  This enables the driver for the NAND flash device found on
  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
 
+config NAND_ROCKCHIP
+   bool "Support for NAND on Rockchip SoCs"
+   select SYS_NAND_SELF_INIT
+   ---help---
+   Enable support for Rockchip nand.
+
 config NAND_SUNXI
bool "Support for NAND on Allwinner SoCs"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index c3d4a99..0659253 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
 obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
+obj-$(CONFIG_NAND_ROCKCHIP) += rockchip_nand.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/rockchip_nand.c b/drivers/mtd/nand/rockchip_nand.c
new file mode 100644
index 000..c997c43
--- /dev/null
+++ b/drivers/mtd/nand/rockchip_nand.c
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2017 Yifeng Zhao 
+ * Copyright (c) 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NANDC_V6_BOOTROM_ECC   24
+#defineNANDC_V6_NUM_BANKS  8
+#define NANDC_V6_DEF_TIMEOUT   2
+#define NANDC_V6_READ  0
+#define NANDC_V6_WRITE 1
+
+#defineNANDC_REG_V6_FMCTL  0x00
+#defineNANDC_REG_V6_FMWAIT 0x04
+#defineNANDC_REG_V6_FLCTL  0x08
+#defineNANDC_REG_V6_BCHCTL 0x0c
+#defineNANDC_REG_V6_DMA_CFG0x10
+#defineNANDC_REG_V6_DMA_BUF0   0x14
+#defineNANDC_REG_V6_DMA_BUF1   0x18
+#defineNANDC_REG_V6_DMA_ST 0x1C
+#defineNANDC_REG_V6_BCHST  0x20
+#defineNANDC_REG_V6_RANDMZ 0x150
+#defineNANDC_REG_V6_VER0x160
+#defineNANDC_REG_V6_INTEN  0x16C
+#defineNANDC_REG_V6_INTCLR 0x170
+#defineNANDC_REG_V6_INTST  0x174
+#defineNANDC_REG_V6_SPARE0 0x200
+#defineNANDC_REG_V6_SPARE1 0x230
+#defineNANDC_REG_V6_BANK0  0x800
+#defineNANDC_REG_V6_SRAM0  0x1000
+#defineNANDC_REG_V6_SRAM_SIZE  0x400
+
+#define NANDC_REG_V6_DATA  0x00
+#define NANDC_REG_V6_ADDR  0x04
+#define NANDC_REG_V6_CMD   0x08
+
+/* FMCTL */
+#define NANDC_V6_FM_WP BIT(8)
+#define NANDC_V6_FM_CE_SEL_M   0xFF
+#define NANDC_V6_FM_CE_SEL(x)  (1 << (x))
+#define NANDC_V6_FM_FREADY BIT(9)
+
+/* FLCTL */
+#define NANDC_V6_FL_RSTBIT(0)
+#define NANDC_V6_FL_DIR_S  0x1
+#define NANDC_V6_FL_XFER_START BIT(2)
+#define NANDC_V6_FL_XFER_ENBIT(3)
+#define NANDC_V6_FL_ST_BUF_S   0x4
+#define NANDC_V6_FL_XFER_COUNT BIT(5)
+#define NANDC_V6_FL_ACORRECT   BIT(10)
+#define NANDC_V6_FL_XFER_READY BIT(20)
+
+/* BCHCTL */
+#define NAND_V6_BCH_REGION_S   0x5
+#define NAND_V6_BCH_REGION_M   0x7 
+
+/* BCHST */
+#define NANDC_V6_BCH0_ST_ERR   BIT(2)
+#define NANDC_V6_BCH1_ST_ERR   BIT(15)
+#define NANDC_V6_ECC_ERR_CNT0(x) x & (0x1F << 3)) >> 3) \
+   | ((x & (1 << 27)) >> 22)) & 0x3F)
+#define NANDC_V6_ECC_ERR_CNT1(x) x & (0x1F << 16)) >> 16) \
+   | ((x & (1 << 29)) >> 24)) & 0x3F)
+
+struct rk_nand {
+   uint32_t banks[NANDC_V6_NUM_BANKS];
+   struct nand_hw_control controller;
+   uint32_t ecc_strength;
+   struct mtd_info mtd;
+   bool bootromblocks;
+   void __iomem *regs;
+   int selected_bank;
+};
+
+static struct nand_ecclayout nand_oob_fix = {
+   .eccbytes = 24,
+   .eccpos = {
+  4, 5, 6, 7, 8, 9, 10},
+   .oobfree = {
+   {.offset = 0,
+.length = 4} }
+};
+
+static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl)
+{
+   return container_of(ctrl, struct rk_nand, controller);
+}
+
+static void rockchip_nand_init(struct rk_nand *rknand)
+{
+   writel(0, 

[U-Boot] [PATCH v2 08/19] rockchip: rk3066: add sdram driver

[Paweł Jarosz]

Add rockchip rk3066 sdram driver

Signed-off-by: Paweł Jarosz 
Acked-by: Simon Glass 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- use common rockchip_sdram_size
- moved sdram init from sdram_init.c

 arch/arm/mach-rockchip/rk3066/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 943 +++
 2 files changed, 944 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c

diff --git a/arch/arm/mach-rockchip/rk3066/Makefile 
b/arch/arm/mach-rockchip/rk3066/Makefile
index 61b7fd4..7663b6a 100644
--- a/arch/arm/mach-rockchip/rk3066/Makefile
+++ b/arch/arm/mach-rockchip/rk3066/Makefile
@@ -5,4 +5,5 @@
 #
 
 obj-y += clk_rk3066.o
+obj-y += sdram_rk3066.o
 obj-y += syscon_rk3066.o
diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c 
b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
new file mode 100644
index 000..e7475b8
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
@@ -0,0 +1,943 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Adapted from the very similar rk3188 ddr init.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct chan_info {
+   struct rk3288_ddr_pctl *pctl;
+   struct rk3288_ddr_publ *publ;
+   struct rk3188_msch *msch;
+};
+
+struct dram_info {
+   struct chan_info chan[1];
+   struct ram_info info;
+   struct clk ddr_clk;
+   struct rk3066_cru *cru;
+   struct rk3066_grf *grf;
+   struct rk3066_sgrf *sgrf;
+   struct rk3188_pmu *pmu;
+};
+
+struct rk3066_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_rockchip_rk3066_dmc of_plat;
+#endif
+   struct rk3288_sdram_channel ch[2];
+   struct rk3288_sdram_pctl_timing pctl_timing;
+   struct rk3288_sdram_phy_timing phy_timing;
+   struct rk3288_base_params base;
+   int num_channels;
+   struct regmap *map;
+};
+
+const int ddrconf_table[] = {
+   /*
+* [5:4] row(13+n)
+* [1:0] col(9+n), assume bw=2
+* row  col,bw
+*/
+   0,
+   (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+   (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+   (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
+   (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+   (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+   (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
+   (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+   (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
+   0,
+   0,
+   0,
+   0,
+   0,
+   0,
+   0,
+};
+
+#define TEST_PATTEN0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0  (1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1  (2 << 4)
+
+#ifdef CONFIG_TPL_BUILD
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+   int i;
+
+   for (i = 0; i < n / sizeof(u32); i++) {
+   writel(*src, dest);
+   src++;
+   dest++;
+   }
+}
+
+static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
+{
+   u32 phy_ctl_srstn_shift = 13;
+   u32 ctl_psrstn_shift = 11;
+   u32 ctl_srstn_shift = 10;
+   u32 phy_psrstn_shift = 9;
+   u32 phy_srstn_shift = 8;
+
+   rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
+1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
+1 << phy_srstn_shift,
+phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
+ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
+phy << phy_srstn_shift);
+}
+
+static void ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
+{
+   u32 phy_ctl_srstn_shift = 13;
+
+   rk_clrsetreg(>cru_softrst_con[5],
+1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
+}
+
+static void phy_pctrl_reset(struct rk3066_cru *cru,
+   struct rk3288_ddr_publ *publ,
+   int channel)
+{
+   int i;
+
+   ddr_reset(cru, channel, 1, 1);
+   udelay(1);
+   clrbits_le32(>acdllcr, ACDLLCR_DLLSRST);
+   for (i = 0; i < 4; i++)
+   clrbits_le32(>datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+   udelay(10);
+   setbits_le32(>acdllcr, ACDLLCR_DLLSRST);
+   for (i = 0; i < 4; i++)
+   setbits_le32(>datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+   udelay(10);
+   ddr_reset(cru, channel, 1, 0);
+   udelay(10);
+   ddr_reset(cru, channel, 0, 0);
+   udelay(10);
+}
+
+static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
+   u32 freq)

[U-Boot] [PATCH v2 07/19] rockchip: rk3066: add mk808 board files

[Paweł Jarosz]

mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
nand onboard.

Signed-off-by: Paweł Jarosz 
Acked-by: Simon Glass 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---
Changes since v1:
- added nand support
- dropped spl of-platdata

 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/rk3066a-mk808.dts  | 189 
 board/rikomagic/mk808_rk3066/Kconfig|  15 +++
 board/rikomagic/mk808_rk3066/MAINTAINERS|   6 +
 board/rikomagic/mk808_rk3066/Makefile   |   7 ++
 board/rikomagic/mk808_rk3066/mk808_rk3066.c |  10 ++
 configs/mk808_defconfig | 114 +
 include/configs/mk808_rk3066.h  |  61 +
 8 files changed, 403 insertions(+)
 create mode 100644 arch/arm/dts/rk3066a-mk808.dts
 create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
 create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
 create mode 100644 board/rikomagic/mk808_rk3066/Makefile
 create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
 create mode 100644 configs/mk808_defconfig
 create mode 100644 include/configs/mk808_rk3066.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1858e06..43a750b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+   rk3066a-mk808.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts
new file mode 100644
index 000..0a452d7
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "rk3066a.dtsi"
+
+/ {
+   model = "Rikomagic MK808";
+   compatible = "rikomagic,mk808", "rockchip,rk3066a";
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   memory@6000 {
+   reg = <0x6000 0x4000>;
+   device_type = "memory";
+   };
+
+   gpio-leds {
+   compatible = "gpio-leds";
+
+   blue {
+   label = "mk808:blue:power";
+   gpios = < 3 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   linux,default-trigger = "default-on";
+   };
+   };
+
+   vcc_io: vcc-io {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_io";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vcc_host: usb-host-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 6 GPIO_ACTIVE_HIGH>;
+   pinctrl-0 = <_drv>;
+   pinctrl-names = "default";
+   regulator-always-on;
+   regulator-name = "host-pwr";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   startup-delay-us = <10>;
+   vin-supply = <_io>;
+   };
+
+   vcc_otg: usb-otg-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 5 GPIO_ACTIVE_HIGH>;
+   pinctrl-0 = <_drv>;
+   pinctrl-names = "default";
+   regulator-always-on;
+   regulator-name = "vcc_otg";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   startup-delay-us = <10>;
+   vin-supply = <_io>;
+   };
+
+   vcc_sd: sdmmc-regulator {
+   compatible = "regulator-fixed";
+   gpio = < 7 GPIO_ACTIVE_LOW>;
+   pinctrl-0 = <_pwr>;
+   pinctrl-names = "default";
+   regulator-name = "vcc_sd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   vin-supply = <_io>;
+   };
+
+   vcc_wifi: sdio-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < 24 GPIO_ACTIVE_HIGH>;
+   pinctrl-0 = <_pwr>;
+   pinctrl-names = "default";
+   regulator-name = "vcc_wifi";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   vin-supply = <_io>;
+   };
+};
+
+ {
+   compatible = 

[U-Boot] [PATCH v2 09/19] mtd: nand: add support for the Sandisk SDTNQGAMA chip

[Paweł Jarosz]

Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size, 1KB write 
size and 40 bit ecc support

Signed-off-by: Paweł Jarosz 
---
Changes since v1:
- none

 drivers/mtd/nand/nand_ids.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index d36f900..7bd9f7d 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] = {
{"TC58NVG6D2 64G 3.3V 8-bit",
{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
  SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+   {"SDTNQGAMA 64G 3.3V 8-bit",
+   { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} },
+ SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
{"SDTNRGAMA 64G 3.3V 8-bit",
{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
-- 
2.7.4

___
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[U-Boot] [PATCH v2 06/19] rockchip: rk3066: add core support

[Paweł Jarosz]

Add core skeleton for rk3066

Signed-off-by: Paweł Jarosz 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- updated to shifted masks
- moved syscon.h below spl.h
- changed error to debug and return error reason
- changed Cortex-A7 to Cortex-A9
- added nand support
- added dfu support
- removed dram_init
- reset timer before enable
- moved configs to board config file
- moved arm clk setup to tpl
- moved ddr setup to tpl
- moved to boot device bootrom

 arch/arm/mach-rockchip/Kconfig|  16 +++
 arch/arm/mach-rockchip/Makefile   |   4 +
 arch/arm/mach-rockchip/rk3066-board-spl.c | 139 
 arch/arm/mach-rockchip/rk3066-board-tpl.c |  90 
 arch/arm/mach-rockchip/rk3066-board.c | 150 ++
 arch/arm/mach-rockchip/rk3066/Kconfig |  31 ++
 arch/arm/mach-rockchip/rk3066/Makefile|   8 ++
 arch/arm/mach-rockchip/rk3066/clk_rk3066.c|  33 ++
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c |  54 ++
 include/configs/rk3066_common.h   |  99 +
 10 files changed, 624 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
 create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
 create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
 create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
 create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
 create mode 100644 include/configs/rk3066_common.h

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d9b25d5..810353f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
  and video codec support. Peripherals include Gigabit Ethernet,
  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3066
+   bool "Support Rockchip RK3066"
+   select CPU_V7
+   select SUPPORT_SPL
+   select SUPPORT_TPL
+   select SPL
+   select TPL
+   select BOARD_LATE_INIT
+   select ROCKCHIP_BROM_HELPER
+   help
+ The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include ethernet, USB2 host
+ and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
@@ -164,6 +179,7 @@ config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3066/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk322x/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 79e9704..ae878ef 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,10 +11,12 @@
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 
+obj-tpl-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
@@ -22,6 +24,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o 
spl-boot-order.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
@@ -35,6 +38,7 @@ obj-y += rk_timer.o
 endif
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
 ifndef CONFIG_TPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 endif
diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c 
b/arch/arm/mach-rockchip/rk3066-board-spl.c
new file mode 100644
index 000..9acdd83
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 

[U-Boot] [PATCH v2 05/19] rockchip: rk3066: add rk3066 platform devicetree file

[Paweł Jarosz]

rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
watchdog and uart

Signed-off-by: Paweł Jarosz 
Reviewed-by: Simon Glass 
Acked-by: Philipp Tomsich 
Reviewed-by: Philipp Tomsich 
---
Changes since v1:
- added nand dts node

 arch/arm/dts/rk3066a.dtsi | 707 ++
 1 file changed, 707 insertions(+)
 create mode 100644 arch/arm/dts/rk3066a.dtsi

diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi
new file mode 100644
index 000..92ee1c2
--- /dev/null
+++ b/arch/arm/dts/rk3066a.dtsi
@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include "rk3xxx.dtsi"
+
+/ {
+   compatible = "rockchip,rk3066a";
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   enable-method = "rockchip,rk3066-smp";
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   next-level-cache = <>;
+   reg = <0x0>;
+   operating-points = <
+   /* kHzuV */
+   1416000 130
+   120 1175000
+   1008000 1125000
+   816000  1125000
+   60  110
+   504000  110
+   312000  1075000
+   >;
+   clock-latency = <4>;
+   clocks = < ARMCLK>;
+   };
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   next-level-cache = <>;
+   reg = <0x1>;
+   };
+   };
+
+   sram: sram@1008 {
+   compatible = "mmio-sram";
+   reg = <0x1008 0x1>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x1008 0x1>;
+
+   smp-sram@0 {
+   compatible = "rockchip,rk3066-smp-sram";
+   reg = <0x0 0x50>;
+   };
+   };
+
+   i2s0: i2s@10118000 {
+   compatible = "rockchip,rk3066-i2s";
+   reg = <0x10118000 0x2000>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus>;
+   dmas = <_s 4>, <_s 5>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_hclk", "i2s_clk";
+   clocks = < HCLK_I2S0>, < SCLK_I2S0>;
+   rockchip,playback-channels = <8>;
+   rockchip,capture-channels = <2>;
+   status = "disabled";
+   };
+
+   i2s1: i2s@1011a000 {
+   compatible = "rockchip,rk3066-i2s";
+   reg = <0x1011a000 0x2000>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus>;
+   dmas = <_s 6>, <_s 7>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_hclk", "i2s_clk";
+   clocks = < HCLK_I2S1>, < SCLK_I2S1>;
+   rockchip,playback-channels = <2>;
+   rockchip,capture-channels = <2>;
+   status = "disabled";
+   };
+
+   i2s2: i2s@1011c000 {
+   compatible = "rockchip,rk3066-i2s";
+   reg = <0x1011c000 0x2000>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus>;
+   dmas = <_s 9>, <_s 10>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_hclk", "i2s_clk";
+   clocks = < HCLK_I2S2>, < SCLK_I2S2>;
+   rockchip,playback-channels = <2>;
+   rockchip,capture-channels = <2>;
+   status = "disabled";
+   };
+
+   nandc: nandc@1050 {
+   compatible = "rockchip,nandc";
+   reg = <0x1050 0x2000>;
+   interrupts = ;
+   clock-names = "hclk";
+   clocks = < HCLK_NANDC0>;
+   status = "disabled";
+   };
+
+   cru: clock-controller@2000 {
+   compatible = "rockchip,rk3066a-cru";
+   reg = <0x2000 0x1000>;
+   rockchip,grf = <>;
+   u-boot,dm-pre-reloc;
+
+   #clock-cells = <1>;
+  

[U-Boot] [PATCH v2 03/19] rockchip: rk3066: add sysreset driver

[Paweł Jarosz]

Add support for system reset for rk3066 socs.

Signed-off-by: Paweł Jarosz 
Reviewed-by: Simon Glass 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- updated to shifted masks

 drivers/sysreset/Makefile  |  1 +
 drivers/sysreset/sysreset_rk3066.c | 61 ++
 2 files changed, 62 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rk3066.c

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index a5200d3..7d4d0cd 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
 endif
+obj-$(CONFIG_ROCKCHIP_RK3066) += sysreset_rk3066.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
diff --git a/drivers/sysreset/sysreset_rk3066.c 
b/drivers/sysreset/sysreset_rk3066.c
new file mode 100644
index 000..b5dcb9a
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3066.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+   struct rk3066_cru *cru = rockchip_get_cru();
+   struct rk3066_grf *grf;
+
+   if (IS_ERR(cru))
+   return PTR_ERR(cru);
+
+   switch (type) {
+   case SYSRESET_WARM:
+   grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   if (IS_ERR(grf))
+   return -EPROTONOSUPPORT;
+   /*
+* warm-reset keeps the remap value,
+* so make sure it's disabled.
+*/
+   rk_clrsetreg(>soc_con0,
+   NOC_REMAP_MASK, 0 << NOC_REMAP_SHIFT);
+
+   rk_clrreg(>cru_mode_con, 0x);
+   writel(0xeca8, >cru_glb_srst_snd_value);
+   break;
+   case SYSRESET_COLD:
+   rk_clrreg(>cru_mode_con, 0x);
+   writel(0xfdb9, >cru_glb_srst_fst_value);
+   break;
+   default:
+   return -EPROTONOSUPPORT;
+   }
+
+   return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3066_sysreset = {
+   .request= rk3066_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3066) = {
+   .name   = "rk3066_sysreset",
+   .id = UCLASS_SYSRESET,
+   .ops= _sysreset,
+};
-- 
2.7.4

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[U-Boot] [PATCH v2 04/19] rockchip: rk3066: add clock driver for rk3066 soc

[Paweł Jarosz]

Add clock driver for rk3066 platform.

Signed-off-by: Paweł Jarosz 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- updated to shifted masks
- moved clk init to tpl

 arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 
 drivers/clk/rockchip/Makefile   |   1 +
 drivers/clk/rockchip/clk_rk3066.c   | 587 
 3 files changed, 777 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
 create mode 100644 drivers/clk/rockchip/clk_rk3066.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
new file mode 100644
index 000..c4a6951
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2016 Heiko Stuebner 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ(1416 * 100)
+#define APLL_SAFE_HZ   (600 * 100)
+#define GPLL_HZ(594 * 100)
+#define CPLL_HZ(384 * 100)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ29700
+#define CPU_HCLK_HZ14850
+#define CPU_PCLK_HZ7425
+#define CPU_H2P_HZ 7425
+
+#define PERI_ACLK_HZ   14850
+#define PERI_HCLK_HZ   14850
+#define PERI_PCLK_HZ   7425
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3066_clk_priv {
+   struct rk3066_grf *grf;
+   struct rk3066_cru *cru;
+   ulong rate;
+   bool has_bwadj;
+};
+
+struct rk3066_cru {
+   struct rk3066_pll {
+   u32 con0;
+   u32 con1;
+   u32 con2;
+   u32 con3;
+   } pll[4];
+   u32 cru_mode_con;
+   u32 cru_clksel_con[35];
+   u32 cru_clkgate_con[10];
+   u32 reserved1[2];
+   u32 cru_glb_srst_fst_value;
+   u32 cru_glb_srst_snd_value;
+   u32 reserved2[2];
+   u32 cru_softrst_con[9];
+   u32 cru_misc_con;
+   u32 reserved3[2];
+   u32 cru_glb_cnt_th;
+};
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+   /* a9_core_div: core = core_src / (a9_core_div + 1) */
+   A9_CORE_DIV_SHIFT   = 9,
+   A9_CORE_DIV_MASK= 0x1f << A9_CORE_DIV_SHIFT,
+   CORE_PLL_SHIFT  = 8,
+   CORE_PLL_MASK   = 1 << CORE_PLL_SHIFT,
+   CORE_PLL_SELECT_APLL= 0,
+   CORE_PLL_SELECT_GPLL,
+
+   /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+   CORE_PERI_DIV_SHIFT = 6,
+   CORE_PERI_DIV_MASK  = 3 << CORE_PERI_DIV_SHIFT,
+
+   /* aclk_cpu pll selection */
+   CPU_ACLK_PLL_SHIFT  = 5,
+   CPU_ACLK_PLL_MASK   = 1 << CPU_ACLK_PLL_SHIFT,
+   CPU_ACLK_PLL_SELECT_APLL= 0,
+   CPU_ACLK_PLL_SELECT_GPLL,
+
+   /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+   A9_CPU_DIV_SHIFT= 0,
+   A9_CPU_DIV_MASK = 0x1f << A9_CPU_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+   /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+   AHB2APB_DIV_SHIFT   = 14,
+   AHB2APB_DIV_MASK= 3 << AHB2APB_DIV_SHIFT,
+
+   /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+   CPU_PCLK_DIV_SHIFT  = 12,
+   CPU_PCLK_DIV_MASK   = 3 << CPU_PCLK_DIV_SHIFT,
+
+   /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+   CPU_HCLK_DIV_SHIFT  = 8,
+   CPU_HCLK_DIV_MASK   = 3 << CPU_HCLK_DIV_SHIFT,
+
+   /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+   CORE_ACLK_DIV_SHIFT = 3,
+   CORE_ACLK_DIV_MASK  = 7 << CORE_ACLK_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+   PERI_SEL_PLL_SHIFT  = 15,
+   PERI_SEL_PLL_MASK   = 1 << PERI_SEL_PLL_SHIFT,
+   PERI_SEL_CPLL   = 0,
+   PERI_SEL_GPLL,
+
+   /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+   PERI_PCLK_DIV_SHIFT = 12,
+   PERI_PCLK_DIV_MASK  = 3 << PERI_PCLK_DIV_SHIFT,
+
+   /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+   PERI_HCLK_DIV_SHIFT = 8,
+   PERI_HCLK_DIV_MASK  = 3 << PERI_HCLK_DIV_SHIFT,
+
+   /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+   PERI_ACLK_DIV_SHIFT = 0,
+   PERI_ACLK_DIV_MASK  = 0x1f << PERI_ACLK_DIV_SHIFT,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+   MMC0_DIV_SHIFT  = 0,
+   MMC0_DIV_MASK   = 0x3f << MMC0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+   UART_PLL_SHIFT  = 15,
+   UART_PLL_MASK   = 1 << UART_PLL_SHIFT,
+   UART_PLL_SELECT_GENERAL = 0,
+   UART_PLL_SELECT_CODEC,
+
+   EMMC_DIV_SHIFT  

[U-Boot] [PATCH v2 02/19] rockchip: rk3066: add rk3066 pinctrl driver

[Paweł Jarosz]

Add driver supporting pin multiplexing on rk3066 platform.

Signed-off-by: Paweł Jarosz 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- updated to shifted masks
- added nand support

 arch/arm/include/asm/arch-rockchip/periph.h |   1 +
 drivers/pinctrl/Kconfig |   9 +
 drivers/pinctrl/rockchip/Makefile   |   1 +
 drivers/pinctrl/rockchip/pinctrl_rk3066.c   | 340 
 4 files changed, 351 insertions(+)
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c

diff --git a/arch/arm/include/asm/arch-rockchip/periph.h 
b/arch/arm/include/asm/arch-rockchip/periph.h
index 9f4bc2e..6c8c77d 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -43,6 +43,7 @@ enum periph_id {
PERIPH_ID_HDMI,
PERIPH_ID_GMAC,
PERIPH_ID_SFC,
+   PERIPH_ID_NAND,
 
PERIPH_ID_COUNT,
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bcbe4a1..c9eb49d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -168,6 +168,15 @@ config PINCTRL_ROCKCHIP_RK3036
  the GPIO definitions and pin control functions for each available
  multiplex function.
 
+config PINCTRL_ROCKCHIP_RK3066
+bool "Rockchip rk3066 pin control driver"
+depends on DM
+help
+  Support pin multiplexing control on Rockchip rk3066 SoCs. The driver 
is
+  controlled by a device tree node which contains both the GPIO
+  definitions and pin control functions for each available multiplex
+  function.
+
 config PINCTRL_ROCKCHIP_RK3188
bool "Rockchip rk3188 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile 
b/drivers/pinctrl/rockchip/Makefile
index 5251771..65923f9 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -6,6 +6,7 @@
 #
 
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3066) += pinctrl_rk3066.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3066.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3066.c
new file mode 100644
index 000..79e0a54
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3066.c
@@ -0,0 +1,340 @@
+/*
+ * Pinctrl driver for Rockchip 3066 SoCs
+ * (C) Copyright 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3066_pinctrl_priv {
+   struct rk3066_grf *grf;
+};
+
+static void pinctrl_rk3066_pwm_config(struct rk3066_grf *grf, int pwm_id)
+{
+   switch (pwm_id) {
+   case PERIPH_ID_PWM0:
+   rk_clrsetreg(>gpio0a_iomux, GPIO0A3_MASK,
+GPIO0A3_PWM0 << GPIO0A3_SHIFT);
+   break;
+   case PERIPH_ID_PWM1:
+   rk_clrsetreg(>gpio0a_iomux, GPIO0A4_MASK,
+GPIO0A4_PWM1 << GPIO0A4_SHIFT);
+   break;
+   case PERIPH_ID_PWM2:
+   rk_clrsetreg(>gpio0d_iomux, GPIO0D6_MASK,
+GPIO0D6_PWM2 << GPIO0D6_SHIFT);
+   break;
+   case PERIPH_ID_PWM3:
+   rk_clrsetreg(>gpio0d_iomux, GPIO0D7_MASK,
+GPIO0D7_PWM3 << GPIO0D7_SHIFT);
+   break;
+   default:
+   debug("pwm id = %d iomux error!\n", pwm_id);
+   break;
+   }
+}
+
+static void pinctrl_rk3066_i2c_config(struct rk3066_grf *grf, int i2c_id)
+{
+   switch (i2c_id) {
+   case PERIPH_ID_I2C0:
+   rk_clrsetreg(>gpio2d_iomux,
+GPIO2D4_MASK | GPIO2D5_MASK,
+GPIO2D4_I2C0_SDA << GPIO2D4_SHIFT |
+GPIO2D5_I2C0_SCL << GPIO2D5_SHIFT);
+   rk_clrsetreg(>soc_con1, 1 << RKI2C0_SEL_SHIFT,
+1 << RKI2C0_SEL_SHIFT);
+   break;
+   case PERIPH_ID_I2C1:
+   rk_clrsetreg(>gpio2d_iomux,
+GPIO2D6_MASK | GPIO2D7_MASK,
+GPIO2D6_I2C1_SDA << GPIO2D6_SHIFT |
+GPIO2D7_I2C1_SCL << GPIO2D7_SHIFT);
+   rk_clrsetreg(>soc_con1, 1 << RKI2C1_SEL_SHIFT,
+1 << RKI2C1_SEL_SHIFT);
+   break;
+   case PERIPH_ID_I2C2:
+   rk_clrsetreg(>gpio3a_iomux,
+GPIO3A1_MASK | GPIO3A0_MASK,
+GPIO3A1_I2C2_SCL << GPIO3A1_SHIFT |
+GPIO3A0_I2C2_SDA << GPIO3A0_SHIFT);
+  

[U-Boot] [PATCH v2 01/19] rockchip: rk3066: add grf header file

[Paweł Jarosz]

grf is needed by various drivers for rk3066 soc.

Signed-off-by: Paweł Jarosz 
Acked-by: Philipp Tomsich 
---
Changes since v1:
- updated to shifted masks

 arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 
 1 file changed, 621 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
new file mode 100644
index 000..be40884
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3066_H
+#define _ASM_ARCH_GRF_RK3066_H
+
+struct rk3066_grf_gpio_lh {
+   u32 l;
+   u32 h;
+};
+
+struct rk3066_grf {
+   struct rk3066_grf_gpio_lh gpio_dir[7];
+   struct rk3066_grf_gpio_lh gpio_do[7];
+   struct rk3066_grf_gpio_lh gpio_en[7];
+
+   u32 gpio0a_iomux;
+   u32 gpio0b_iomux;
+   u32 gpio0c_iomux;
+   u32 gpio0d_iomux;
+
+   u32 gpio1a_iomux;
+   u32 gpio1b_iomux;
+   u32 gpio1c_iomux;
+   u32 gpio1d_iomux;
+
+   u32 gpio2a_iomux;
+   u32 gpio2b_iomux;
+   u32 gpio2c_iomux;
+   u32 gpio2d_iomux;
+
+   u32 gpio3a_iomux;
+   u32 gpio3b_iomux;
+   u32 gpio3c_iomux;
+   u32 gpio3d_iomux;
+
+   u32 gpio4a_iomux;
+   u32 gpio4b_iomux;
+   u32 gpio4c_iomux;
+   u32 gpio4d_iomux;
+
+   u32 reserved0[5];
+
+   u32 gpio6b_iomux;
+
+   u32 reserved1[2];
+
+   struct rk3066_grf_gpio_lh gpio_pull[7];
+
+   u32 soc_con0;
+   u32 soc_con1;
+   u32 soc_con2;
+
+   u32 soc_status0;
+
+   u32 dmac1_con[3];
+   u32 dmac2_con[4];
+
+   u32 uoc0_con[3];
+   u32 uoc1_con[4];
+   u32 ddrc_con;
+   u32 ddrc_stat;
+
+   u32 reserved2[10];
+
+   u32 os_reg[4];
+};
+check_member(rk3066_grf, os_reg[3], 0x01d4);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+   GPIO0A6_SHIFT   = 12,
+   GPIO0A6_MASK= 1 << GPIO0A6_SHIFT,
+   GPIO0A6_GPIO= 0,
+   GPIO0A6_HOST_DRV_VBUS,
+
+   GPIO0A5_SHIFT   = 10,
+   GPIO0A5_MASK= 1 << GPIO0A5_SHIFT,
+   GPIO0A5_GPIO= 0,
+   GPIO0A5_OTG_DRV_VBUS,
+
+   GPIO0A4_SHIFT   = 8,
+   GPIO0A4_MASK= 1 << GPIO0A4_SHIFT,
+   GPIO0A4_GPIO= 0,
+   GPIO0A4_PWM1,
+
+   GPIO0A3_SHIFT   = 6,
+   GPIO0A3_MASK= 1 << GPIO0A3_SHIFT,
+   GPIO0A3_GPIO= 0,
+   GPIO0A3_PWM0
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+   GPIO0D7_SHIFT   = 14,
+   GPIO0D7_MASK= 1 << GPIO0D7_SHIFT,
+   GPIO0D7_GPIO= 0,
+   GPIO0D7_PWM3,
+
+   GPIO0D6_SHIFT   = 12,
+   GPIO0D6_MASK= 1 << GPIO0D6_SHIFT,
+   GPIO0D6_GPIO= 0,
+   GPIO0D6_PWM2
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+   GPIO1A7_SHIFT   = 14,
+   GPIO1A7_MASK= 3 << GPIO1A7_SHIFT,
+   GPIO1A7_GPIO= 0,
+   GPIO1A7_UART1_RTS_N,
+   GPIO1A7_SPI0_TXD,
+
+   GPIO1A6_SHIFT   = 12,
+   GPIO1A6_MASK= 3 << GPIO1A6_SHIFT,
+   GPIO1A6_GPIO= 0,
+   GPIO1A6_UART1_CTS_N,
+   GPIO1A6_SPI0_RXD,
+
+   GPIO1A5_SHIFT   = 10,
+   GPIO1A5_MASK= 3 << GPIO1A5_SHIFT,
+   GPIO1A5_GPIO= 0,
+   GPIO1A5_UART1_SOUT,
+   GPIO1A5_SPI0_CLK,
+
+   GPIO1A4_SHIFT   = 8,
+   GPIO1A4_MASK= 3 << GPIO1A4_SHIFT,
+   GPIO1A4_GPIO= 0,
+   GPIO1A4_UART1_SIN,
+   GPIO1A4_SPI0_CSN0,
+
+   GPIO1A3_SHIFT   = 6,
+   GPIO1A3_MASK= 1 << GPIO1A3_SHIFT,
+   GPIO1A3_GPIO= 0,
+   GPIO1A3_UART0_RTS_N,
+
+   GPIO1A2_SHIFT   = 4,
+   GPIO1A2_MASK= 1 << GPIO1A2_SHIFT,
+   GPIO1A2_GPIO= 0,
+   GPIO1A2_UART0_CTS_N,
+
+   GPIO1A1_SHIFT   = 2,
+   GPIO1A1_MASK= 1 << GPIO1A1_SHIFT,
+   GPIO1A1_GPIO= 0,
+   GPIO1A1_UART0_SOUT,
+
+   GPIO1A0_SHIFT   = 0,
+   GPIO1A0_MASK= 1 << GPIO1A0_SHIFT,
+   GPIO1A0_GPIO= 0,
+   GPIO1A0_UART0_SIN
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+   GPIO1B1_SHIFT   = 2,
+   GPIO1B1_MASK= 1 << GPIO1B1_SHIFT,
+   GPIO1B1_GPIO= 0,
+   GPIO1B1_UART2_SOUT,
+
+   GPIO1B0_SHIFT   = 0,
+   GPIO1B0_MASK= 1 << GPIO1B0_SHIFT,
+   GPIO1B0_GPIO= 0,
+   GPIO1B0_UART2_SIN
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+   GPIO2C7_SHIFT   = 14,
+   GPIO2C7_MASK= 3 << GPIO2C7_SHIFT,
+   GPIO2C7_GPIO= 0,
+ 

[U-Boot] [PATCH v2 00/19] add support for rk3066 platform.

[Paweł Jarosz]

This patch serie adds support for Rockchip RK3066 processor.

Paweł Jarosz (19):
  rockchip: rk3066: add grf header file
  rockchip: rk3066: add rk3066 pinctrl driver
  rockchip: rk3066: add sysreset driver
  rockchip: rk3066: add clock driver for rk3066 soc
  rockchip: rk3066: add rk3066 platform devicetree file
  rockchip: rk3066: add core support
  rockchip: rk3066: add mk808 board files
  rockchip: rk3066: add sdram driver
  mtd: nand: add support for the Sandisk SDTNQGAMA chip
  mtd: nand: add the rockchip nand controller driver
  rockchip: mkimage: add support for rockchip nand boot image
  rockchip: board: rk3066: convert board_usb_init to live tree functions
  ARM: dts: rockchip: prefer u-boot,dm-pre-reloc rather than
u-boot,dm-spl
  mmc: dw_mmc: support transfer mode autodetection
  mmc: dw_mmc: rockchip: add support for rk3066 sdmmc
  armv7: support rk3066 early back to bootrom in vector.S
  rockchip: sysreset: deduplicate rk3066 and rk3188 sysreset drivers
  dfu: fix spl build
  mtd: nand: spl: allow build nand_bbt, nand_ids and nand_util

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3066a-mk808.dts | 189 +
 arch/arm/dts/rk3066a.dtsi  | 707 +++
 arch/arm/dts/rk3xxx.dtsi   |   8 +-
 arch/arm/include/asm/arch-rockchip/boot0.h |  14 +
 arch/arm/include/asm/arch-rockchip/cru_rk3066.h| 189 +
 arch/arm/include/asm/arch-rockchip/grf_rk3066.h| 621 ++
 arch/arm/include/asm/arch-rockchip/periph.h|   1 +
 .../include/asm/arch-rockchip/sysreset_common.h|  20 +
 arch/arm/lib/vectors.S |  18 +-
 arch/arm/mach-rockchip/Kconfig |  16 +
 arch/arm/mach-rockchip/Makefile|   7 +
 arch/arm/mach-rockchip/rk3066-board-spl.c  | 139 +++
 arch/arm/mach-rockchip/rk3066-board-tpl.c  |  90 ++
 arch/arm/mach-rockchip/rk3066-board.c  | 112 +++
 arch/arm/mach-rockchip/rk3066/Kconfig  |  31 +
 arch/arm/mach-rockchip/rk3066/Makefile |   9 +
 arch/arm/mach-rockchip/rk3066/clk_rk3066.c |  33 +
 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c   | 943 +
 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c  |  54 ++
 arch/arm/mach-rockchip/sysreset-common.c   |  39 +
 board/rikomagic/mk808_rk3066/Kconfig   |  15 +
 board/rikomagic/mk808_rk3066/MAINTAINERS   |   6 +
 board/rikomagic/mk808_rk3066/Makefile  |   7 +
 board/rikomagic/mk808_rk3066/mk808_rk3066.c|  10 +
 common/image.c |   1 +
 configs/mk808_defconfig| 115 +++
 drivers/clk/rockchip/Makefile  |   1 +
 drivers/clk/rockchip/clk_rk3066.c  | 587 +
 drivers/dfu/dfu_nand.c |   6 +-
 drivers/mmc/dw_mmc.c   |   8 +
 drivers/mmc/rockchip_dw_mmc.c  |   1 +
 drivers/mtd/nand/Kconfig   |   6 +
 drivers/mtd/nand/Makefile  |   4 +
 drivers/mtd/nand/nand_ids.c|   3 +
 drivers/mtd/nand/rockchip_nand.c   | 660 ++
 drivers/pinctrl/Kconfig|   9 +
 drivers/pinctrl/rockchip/Makefile  |   1 +
 drivers/pinctrl/rockchip/pinctrl_rk3066.c  | 340 
 drivers/sysreset/Makefile  |   1 +
 drivers/sysreset/sysreset_rk3066.c |  49 ++
 drivers/sysreset/sysreset_rk3188.c |  35 +-
 include/configs/mk808_rk3066.h |  61 ++
 include/configs/rk3066_common.h|  99 +++
 include/dwmmc.h|   4 +
 include/fdtdec.h   |   1 +
 include/image.h|   1 +
 lib/fdtdec.c   |   1 +
 tools/Makefile |   2 +-
 tools/imagetool.h  |   1 +
 tools/mkimage.c|   8 +-
 tools/rkcommon.c   |  10 +-
 tools/rkcommon.h   |  10 +-
 tools/rknand.c | 156 
 tools/rksd.c   |   2 +-
 tools/rkspi.c  |   2 +-
 56 files changed, 5416 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/dts/rk3066a-mk808.dts
 create mode 100644 arch/arm/dts/rk3066a.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/sysreset_common.h
 create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
 create mode 100644 

[U-Boot] [PATCH 1/1] efi_loader: use EFI_PAGE_MASK instead of EFI_PAGE_SIZE - 1

[Heinrich Schuchardt]

We should be consistent in the way we calculate page sizes.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_runtime.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index dd52755d1d..ad7f3754bd 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -325,7 +325,7 @@ void efi_add_runtime_mmio(void *mmio_ptr, u64 len)
 {
struct efi_runtime_mmio_list *newmmio;
 
-   u64 pages = (len + EFI_PAGE_SIZE - 1) >> EFI_PAGE_SHIFT;
+   u64 pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
efi_add_memory_map(*(uintptr_t *)mmio_ptr, pages, EFI_MMAP_IO, false);
 
newmmio = calloc(1, sizeof(*newmmio));
-- 
2.11.0

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[U-Boot] [PATCH 1/1] efi_loader: use EFI_PAGE_SIZE instead of 4096

[Heinrich Schuchardt]

We should use constant EFI_PAGE_SIZE instead of 4096 where the
coding relies on 4096 being EFI_PAGE_SIZE.

Signed-off-by: Heinrich Schuchardt 
---
 cmd/bootefi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index d20775eccd..3196d86040 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -158,7 +158,7 @@ static void *copy_fdt(void *fdt)
}
 
/* Give us at least 4kb breathing room */
-   fdt_size = ALIGN(fdt_size + 4096, 4096);
+   fdt_size = ALIGN(fdt_size + 4096, EFI_PAGE_SIZE);
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
 
/* Safe fdt location is at 128MB */
@@ -166,7 +166,7 @@ static void *copy_fdt(void *fdt)
if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
   _fdt_addr) != EFI_SUCCESS) {
/* If we can't put it there, put it somewhere */
-   new_fdt_addr = (ulong)memalign(4096, fdt_size);
+   new_fdt_addr = (ulong)memalign(EFI_PAGE_SIZE, fdt_size);
if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
   _fdt_addr) != EFI_SUCCESS) {
printf("ERROR: Failed to reserve space for FDT\n");
-- 
2.11.0

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Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Heinrich Schuchardt]

On 08/10/2017 08:29 PM, Rob Clark wrote:
> This avoids printf() spam about file reads (such as loading an image)
> into unaligned buffers (and the associated memcpy()).  And generally
> seems like a good idea.
> 
> Signed-off-by: Rob Clark 
> ---
>  lib/efi_loader/efi_memory.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index 9e079f1fa3..2ba8d8b42b 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>   */
>  struct efi_pool_allocation {
>   u64 num_pages;
> - char data[];
> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>  };
>  
>  /*
> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
> long size,
>  {
>   efi_status_t r;
>   efi_physical_addr_t t;
> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct efi_pool_allocation),
> +  EFI_PAGE_SIZE);
>  
>   if (size == 0) {
>   *buffer = NULL;
> 

All other divisions by EFI_PAGE_SIZE are consistently handled in the
same way:

lib/efi_loader/efi_runtime.c:328:u64 pages = (len + EFI_PAGE_SIZE - 1)
>> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:123:
 >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:126:return (carve_end -
carve_start) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:140:newmap->desc.num_pages =
(map_end - carve_start) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:145:map_desc->num_pages =
(carve_start - map_start) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:331:uint64_t pages = (len +
EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:359:u64 num_pages = (size +
sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:448:u64 pages = (ram_size +
EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:465:uboot_pages = (gd->ram_top -
uboot_start) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:472:runtime_pages = (runtime_end -
runtime_start) >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_memory.c:481:   (64 *
1024 * 1024) >> EFI_PAGE_SHIFT,
lib/efi_loader/efi_image_loader.c:34:   int type =
*relocs >> EFI_PAGE_SHIFT;
lib/efi_loader/efi_image_loader.c:170:
(virt_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT);
arch/arm/cpu/armv8/fsl-layerscape/cpu.c:814:pages =
(ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
arch/arm/cpu/armv8/fsl-layerscape/fdt.c:112:
ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
cmd/bootefi.c:162:  fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
cmd/bootefi.c:243:  fdt_pages = fdt_size >> EFI_PAGE_SHIFT;

With you patch we are even inconsistent within the same .c-file.

Regards

Heinrich
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Re: [U-Boot] [PATCH] driver: net: ldpaa: Update priv->phydev after free()

[Joe Hershberger]

On Wed, Feb 15, 2017 at 9:14 AM, Ashish Kumar  wrote:
> From: Prabhakar Kushwaha 
>
> Even after memory free of phydev, priv is still pointing to the
> obsolete address.
> So update priv->phydev as NULL after memory free.
>
> Signed-off-by: Prabhakar Kushwaha 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v4 2/2] usb: net: Add support for Microchip LAN75xx and LAN78xx

[Joe Hershberger]

On Fri, Aug 11, 2017 at 11:44 AM,   wrote:
> From: Yuiko Oshino 
>
> Add support for Microchip LAN7500, LAN7800 and LAN7850,
> USB to 10/100/1000 Ethernet Controllers.
>
> Signed-off-by: Yuiko Oshino 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Rob Clark]

On Fri, Aug 11, 2017 at 2:10 PM, Heinrich Schuchardt  wrote:
> On 08/11/2017 07:27 PM, Rob Clark wrote:
>> On Fri, Aug 11, 2017 at 12:58 PM, Heinrich Schuchardt
>>  wrote:
>>> On 08/10/2017 08:29 PM, Rob Clark wrote:
 This avoids printf() spam about file reads (such as loading an image)
 into unaligned buffers (and the associated memcpy()).  And generally
 seems like a good idea.

 Signed-off-by: Rob Clark 
 ---
  lib/efi_loader/efi_memory.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
 index 9e079f1fa3..2ba8d8b42b 100644
 --- a/lib/efi_loader/efi_memory.c
 +++ b/lib/efi_loader/efi_memory.c
 @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
   */
  struct efi_pool_allocation {
   u64 num_pages;
 - char data[];
 + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
  };

  /*
 @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
 long size,
  {
   efi_status_t r;
   efi_physical_addr_t t;
 - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> 
 EFI_PAGE_SHIFT;
 + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct 
 efi_pool_allocation),
 +  EFI_PAGE_SIZE);
>>>
>>> It seems you missed my mail dated 2017-08-02T01:21Z:
>>>
>>> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
>>> architecture this is only available via stdlib which is not available in
>>> U-Boot.
>>>
>>> Please, use
>>> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>>> as in the original line.
>>>
>>
>> I didn't miss it.. but I did disagree with it.  It is an unsigned
>> division by a power-of-two.  The compiler turns this into a
>> right-shift.  So in fact both ways generate the same code, but the
>> DIV_ROUND_UP() is more clear.
>>
>> BR,
>> -R
>>
>
> I compiled:
>
> int main(int argc, char *argv[])
> {
> long long int a = 16;
> long long int b = 2;
> long long int c;
> c = a / b;
> return c;
> }
>
> on a mips system with gcc 6.3
>
> gcc -O0 -nostdlib test.c > test
>
> and got
>
> /tmp/ccenefOj.o: In function `main':
> test.c:(.text+0x48): undefined reference to `__divdi3'
> test.c:(.text+0x60): undefined reference to `__divdi3'
>

Note that EFI_LOADER does not even compile with -O0.. but try:  c = a / 2;

my guess is with -O0 gcc is not doing constant propagation.

I did already try this on aarch64 with -O0 (but without the variable in between)

BR,
-R
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Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Rob Clark]

On Fri, Aug 11, 2017 at 1:47 PM, Heinrich Schuchardt  wrote:
> On 08/11/2017 07:27 PM, Rob Clark wrote:
>> On Fri, Aug 11, 2017 at 12:58 PM, Heinrich Schuchardt
>>  wrote:
>>> On 08/10/2017 08:29 PM, Rob Clark wrote:
 This avoids printf() spam about file reads (such as loading an image)
 into unaligned buffers (and the associated memcpy()).  And generally
 seems like a good idea.

 Signed-off-by: Rob Clark 
 ---
  lib/efi_loader/efi_memory.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
 index 9e079f1fa3..2ba8d8b42b 100644
 --- a/lib/efi_loader/efi_memory.c
 +++ b/lib/efi_loader/efi_memory.c
 @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
   */
  struct efi_pool_allocation {
   u64 num_pages;
 - char data[];
 + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
  };

  /*
 @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
 long size,
  {
   efi_status_t r;
   efi_physical_addr_t t;
 - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> 
 EFI_PAGE_SHIFT;
 + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct 
 efi_pool_allocation),
 +  EFI_PAGE_SIZE);
>>>
>>> It seems you missed my mail dated 2017-08-02T01:21Z:
>>>
>>> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
>>> architecture this is only available via stdlib which is not available in
>>> U-Boot.
>>>
>>> Please, use
>>> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>>> as in the original line.
>>>
>>
>> I didn't miss it.. but I did disagree with it.  It is an unsigned
>> division by a power-of-two.  The compiler turns this into a
>> right-shift.  So in fact both ways generate the same code, but the
>> DIV_ROUND_UP() is more clear.
>
> This conversion is not enforced by the define in include/linux/kernel.h.
>
> This is not required by ISO/IEC 9899. So you should not rely on it.
> We surely do not want compiler specific coding in U-Boot.

I'm not sure why a standard would require this.  But in practice, it
is one of the easier things a compiler will do.  (Trust me, I've
implemented the same optimization in mesa's shader compiler.)

We elsewhere rely on DCE (dead code elimination) to avoid unresolved
symbols for stuff inside an 'if (CONFIG_IS_ENABLED(FOO))' and that is
a harder thing for a compiler to do.

So unless someone is trying to use a complete toy compiler, it
shouldn't be a problem.  And if they are, they have bigger issues ;-)

BR,
-R
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Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Heinrich Schuchardt]

On 08/11/2017 07:27 PM, Rob Clark wrote:
> On Fri, Aug 11, 2017 at 12:58 PM, Heinrich Schuchardt
>  wrote:
>> On 08/10/2017 08:29 PM, Rob Clark wrote:
>>> This avoids printf() spam about file reads (such as loading an image)
>>> into unaligned buffers (and the associated memcpy()).  And generally
>>> seems like a good idea.
>>>
>>> Signed-off-by: Rob Clark 
>>> ---
>>>  lib/efi_loader/efi_memory.c | 5 +++--
>>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
>>> index 9e079f1fa3..2ba8d8b42b 100644
>>> --- a/lib/efi_loader/efi_memory.c
>>> +++ b/lib/efi_loader/efi_memory.c
>>> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>>>   */
>>>  struct efi_pool_allocation {
>>>   u64 num_pages;
>>> - char data[];
>>> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>>>  };
>>>
>>>  /*
>>> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
>>> long size,
>>>  {
>>>   efi_status_t r;
>>>   efi_physical_addr_t t;
>>> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> 
>>> EFI_PAGE_SHIFT;
>>> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct 
>>> efi_pool_allocation),
>>> +  EFI_PAGE_SIZE);
>>
>> It seems you missed my mail dated 2017-08-02T01:21Z:
>>
>> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
>> architecture this is only available via stdlib which is not available in
>> U-Boot.
>>
>> Please, use
>> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>> as in the original line.
>>
> 
> I didn't miss it.. but I did disagree with it.  It is an unsigned
> division by a power-of-two.  The compiler turns this into a
> right-shift.  So in fact both ways generate the same code, but the
> DIV_ROUND_UP() is more clear.
> 
> BR,
> -R
> 

I compiled:

int main(int argc, char *argv[])
{
long long int a = 16;
long long int b = 2;
long long int c;
c = a / b;
return c;
}

on a mips system with gcc 6.3

gcc -O0 -nostdlib test.c > test

and got

/tmp/ccenefOj.o: In function `main':
test.c:(.text+0x48): undefined reference to `__divdi3'
test.c:(.text+0x60): undefined reference to `__divdi3'

Best regards

Heinrich
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Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Heinrich Schuchardt]

On 08/11/2017 07:27 PM, Rob Clark wrote:
> On Fri, Aug 11, 2017 at 12:58 PM, Heinrich Schuchardt
>  wrote:
>> On 08/10/2017 08:29 PM, Rob Clark wrote:
>>> This avoids printf() spam about file reads (such as loading an image)
>>> into unaligned buffers (and the associated memcpy()).  And generally
>>> seems like a good idea.
>>>
>>> Signed-off-by: Rob Clark 
>>> ---
>>>  lib/efi_loader/efi_memory.c | 5 +++--
>>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
>>> index 9e079f1fa3..2ba8d8b42b 100644
>>> --- a/lib/efi_loader/efi_memory.c
>>> +++ b/lib/efi_loader/efi_memory.c
>>> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>>>   */
>>>  struct efi_pool_allocation {
>>>   u64 num_pages;
>>> - char data[];
>>> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>>>  };
>>>
>>>  /*
>>> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
>>> long size,
>>>  {
>>>   efi_status_t r;
>>>   efi_physical_addr_t t;
>>> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> 
>>> EFI_PAGE_SHIFT;
>>> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct 
>>> efi_pool_allocation),
>>> +  EFI_PAGE_SIZE);
>>
>> It seems you missed my mail dated 2017-08-02T01:21Z:
>>
>> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
>> architecture this is only available via stdlib which is not available in
>> U-Boot.
>>
>> Please, use
>> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>> as in the original line.
>>
> 
> I didn't miss it.. but I did disagree with it.  It is an unsigned
> division by a power-of-two.  The compiler turns this into a
> right-shift.  So in fact both ways generate the same code, but the
> DIV_ROUND_UP() is more clear.

This conversion is not enforced by the define in include/linux/kernel.h.

This is not required by ISO/IEC 9899. So you should not rely on it.
We surely do not want compiler specific coding in U-Boot.

Regards

Heinrich
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Re: [U-Boot] [PATCH v1 03/15] part: extract MBR signature from partitions

[Rob Clark]

Ok, looks like Alexander updated efi-next in last couple days, I'll
rebase over the weekend.

BR,
-R

On Fri, Aug 11, 2017 at 12:25 PM, Heinrich Schuchardt
 wrote:
>
> Hello Rob,
>
> I couldn't apply your patch to either of
>
> u-boot/agraf/efi-next nor
> u-boot/master
>
> Applying: part: extract MBR signature from partitions
> error: patch failed: include/blk.h:62
> error: include/blk.h: patch does not apply
> Patch failed at 0001 part: extract MBR signature from partitions
>
> Plese, rebase your patch or indicate prerequisote patches.
>
> Best regards
>
> Heinrich
>
> On 08/10/2017 08:29 PM, Rob Clark wrote:
>> From: Peter Jones 
>>
>> EFI client programs need the signature information from the partition
>> table to determine the disk a partition is on, so we need to fill that
>> in here.
>>
>> Signed-off-by: Peter Jones 
>> [separated from efi_loader part, and fixed build-errors for non-
>>  CONFIG_EFI_PARTITION case]
>> Signed-off-by: Rob Clark 
>> ---
>>  disk/part_dos.c| 12 +---
>>  disk/part_efi.c| 20 
>>  include/blk.h  | 15 +++
>>  include/efi.h  |  4 
>>  include/part.h |  3 ++-
>>  include/part_efi.h |  4 
>>  6 files changed, 50 insertions(+), 8 deletions(-)
>>
>> diff --git a/disk/part_dos.c b/disk/part_dos.c
>> index 7ede15ec26..850a538e83 100644
>> --- a/disk/part_dos.c
>> +++ b/disk/part_dos.c
>> @@ -89,14 +89,20 @@ static int test_block_type(unsigned char *buffer)
>>
>>  static int part_test_dos(struct blk_desc *dev_desc)
>>  {
>> - ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
>> + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz);
>>
>> - if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1)
>> + if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1)
>>   return -1;
>>
>> - if (test_block_type(buffer) != DOS_MBR)
>> + if (test_block_type((unsigned char *)mbr) != DOS_MBR)
>>   return -1;
>>
>> + if (dev_desc->sig_type == SIG_TYPE_NONE &&
>> + mbr->unique_mbr_signature != 0) {
>> + dev_desc->sig_type = SIG_TYPE_MBR;
>> + dev_desc->mbr_sig = mbr->unique_mbr_signature;
>> + }
>> +
>>   return 0;
>>  }
>>
>> diff --git a/disk/part_efi.c b/disk/part_efi.c
>> index 1b7ba27947..71e4188455 100644
>> --- a/disk/part_efi.c
>> +++ b/disk/part_efi.c
>> @@ -871,11 +871,19 @@ static int is_pmbr_valid(legacy_mbr * mbr)
>>  static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
>>   gpt_header *pgpt_head, gpt_entry **pgpt_pte)
>>  {
>> + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz);
>> +
>>   if (!dev_desc || !pgpt_head) {
>>   printf("%s: Invalid Argument(s)\n", __func__);
>>   return 0;
>>   }
>>
>> + /* Read MBR Header from device */
>> + if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) {
>> + printf("*** ERROR: Can't read MBR header ***\n");
>> + return 0;
>> + }
>> +
>>   /* Read GPT Header from device */
>>   if (blk_dread(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
>>   printf("*** ERROR: Can't read GPT header ***\n");
>> @@ -885,6 +893,18 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 
>> lba,
>>   if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
>>   return 0;
>>
>> + if (dev_desc->sig_type == SIG_TYPE_NONE) {
>> + efi_guid_t empty = {};
>> + if (memcmp(_head->disk_guid, , sizeof(empty))) {
>> + dev_desc->sig_type = SIG_TYPE_GUID;
>> + memcpy(_desc->guid_sig, _head->disk_guid,
>> +   sizeof(empty));
>> + } else if (mbr->unique_mbr_signature != 0) {
>> + dev_desc->sig_type = SIG_TYPE_MBR;
>> + dev_desc->mbr_sig = mbr->unique_mbr_signature;
>> + }
>> + }
>> +
>>   /* Read and allocate Partition Table Entries */
>>   *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
>>   if (*pgpt_pte == NULL) {
>> diff --git a/include/blk.h b/include/blk.h
>> index ef29a07ee2..3a5e04c00d 100644
>> --- a/include/blk.h
>> +++ b/include/blk.h
>> @@ -8,6 +8,8 @@
>>  #ifndef BLK_H
>>  #define BLK_H
>>
>> +#include 
>> +
>>  #ifdef CONFIG_SYS_64BIT_LBA
>>  typedef uint64_t lbaint_t;
>>  #define LBAFlength "ll"
>> @@ -35,6 +37,14 @@ enum if_type {
>>   IF_TYPE_COUNT,  /* Number of interface types */
>>  };
>>
>> +enum sig_type {
>> + SIG_TYPE_NONE,
>> + SIG_TYPE_MBR,
>> + SIG_TYPE_GUID,
>> +
>> + SIG_TYPE_COUNT  /* Number of signature types */
>> +};
>> +
>>  /*
>>   * With driver model (CONFIG_BLK) this is uclass platform data, accessible
>>   * with dev_get_uclass_platdata(dev)
>> @@ -62,6 +72,11 @@ struct blk_desc {
>>   charvendor[40+1];   

Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Rob Clark]

On Fri, Aug 11, 2017 at 12:58 PM, Heinrich Schuchardt
 wrote:
> On 08/10/2017 08:29 PM, Rob Clark wrote:
>> This avoids printf() spam about file reads (such as loading an image)
>> into unaligned buffers (and the associated memcpy()).  And generally
>> seems like a good idea.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  lib/efi_loader/efi_memory.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
>> index 9e079f1fa3..2ba8d8b42b 100644
>> --- a/lib/efi_loader/efi_memory.c
>> +++ b/lib/efi_loader/efi_memory.c
>> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>>   */
>>  struct efi_pool_allocation {
>>   u64 num_pages;
>> - char data[];
>> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>>  };
>>
>>  /*
>> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
>> long size,
>>  {
>>   efi_status_t r;
>>   efi_physical_addr_t t;
>> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
>> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct efi_pool_allocation),
>> +  EFI_PAGE_SIZE);
>
> It seems you missed my mail dated 2017-08-02T01:21Z:
>
> With DIV_ROUND_UP you introduce a 64bit division. Depending on the
> architecture this is only available via stdlib which is not available in
> U-Boot.
>
> Please, use
> + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
> as in the original line.
>

I didn't miss it.. but I did disagree with it.  It is an unsigned
division by a power-of-two.  The compiler turns this into a
right-shift.  So in fact both ways generate the same code, but the
DIV_ROUND_UP() is more clear.

BR,
-R
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Re: [U-Boot] [u-boot-release] [PATCH v3 1/3] armv8: ls1088a: Add NXP LS1088A SoC support

[York Sun]

On 08/11/2017 12:25 AM, Ashish Kumar wrote:
> The QorIQ LS1088A processor is built on the Layerscape
> architecture combining eight ARM A53 processor cores
> with advanced, high-performance datapath acceleration
> and networks, peripheral interfaces required for
> networking, wireless infrastructure, and general-purpose
> embedded applications.
> 
> LS1088A is compliant to the Layerscape Chassis Generation 3.

s/compliant to/compliant with/

> 
> Features summary:
>   - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
>   - Cores are in 2 cluster of 4-cores each
>   - Cache coherent interconnect (CCI-400)
>   - One 64-bit DDR4 SDRAM memory controller with ECC
>   - Data path acceleration architecture 2.0 (DPAA2)
>   - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
>   - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
> 
> Signed-off-by: Alison Wang 
> Signed-off-by: Prabhakar Kushwaha 
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Raghav Dogra 
> Signed-off-by: Shaohui Xie 
> ---
> 
> v2:
>   Fix indentaion in commit msg
>   Separate RDB and Si specific file
>   Move Macros to Kconfig
> 
> v3:
> 1.Re-based on top of
>commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
>Merge: f0ca30f 6a5691e
>Author: Tom Rini 
>Date:   Tue Aug 8 17:06:19 2017 -0400
> 
>  Merge git://git.denx.de/u-boot-x86
> 
> 2.Incorporate review comments on v2
>Clean up done
> 
> 3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h
> 
>   arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  39 ++-
>   arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
>   .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|  10 ++
>   arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |   6 +-
>   arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 
> +
>   arch/arm/cpu/armv8/fsl-layerscape/soc.c|   5 +
>   arch/arm/dts/fsl-ls1088a.dtsi  |  78 +
>   arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +-
>   arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   4 +
>   .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
>   .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
>   arch/arm/include/asm/arch-fsl-layerscape/soc.h |   4 +
>   .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |  14 +++
>   drivers/ddr/fsl/util.c |   2 +-
>   drivers/net/ldpaa_eth/Makefile |   1 +
>   drivers/net/ldpaa_eth/ls1088a.c|  87 ++
>   16 files changed, 447 insertions(+), 9 deletions(-)
>   create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
>   create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
>   create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 1132969..a3c7490 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -49,6 +49,29 @@ config ARCH_LS1046A
>   select BOARD_EARLY_INIT_F
>   imply SCSI
>   
> +config ARCH_LS1088A
> + bool
> + select ARMV8_SET_SMPEN
> + select FSL_LSCH3
> + select SYS_FSL_DDR
> + select SYS_FSL_DDR_LE
> + select SYS_FSL_DDR_VER_50
> + select SYS_FSL_ERRATUM_A009803
> + select SYS_FSL_ERRATUM_A009942
> + select SYS_FSL_ERRATUM_A010165
> + select SYS_FSL_ERRATUM_A008511
> + select SYS_FSL_ERRATUM_A008850
> + select SYS_FSL_HAS_CCI400
> + select SYS_FSL_HAS_DDR4
> + select SYS_FSL_HAS_SEC
> + select SYS_FSL_SEC_COMPAT_5
> + select SYS_FSL_SEC_LE
> + select SYS_FSL_SRDS_1
> + select SYS_FSL_SRDS_2
> + select FSL_TZASC_1
> + select ARCH_EARLY_INIT_R
> + select BOARD_EARLY_INIT_F
> +
>   config ARCH_LS2080A
>   bool
>   select ARMV8_SET_SMPEN
> @@ -60,6 +83,7 @@ config ARCH_LS2080A
>   select SYS_FSL_DDR
>   select SYS_FSL_DDR_LE
>   select SYS_FSL_DDR_VER_50
> + select SYS_FSL_HAS_CCN504
>   select SYS_FSL_HAS_DP_DDR
>   select SYS_FSL_HAS_SEC
>   select SYS_FSL_HAS_DDR4
> @@ -98,7 +122,7 @@ config FSL_LSCH3
>   
>   config FSL_MC_ENET
>   bool "Management Complex network"
> - depends on ARCH_LS2080A
> + depends on ARCH_LS2080A || ARCH_LS1088A
>   default y
>   select RESV_RAM
>   help
> @@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
>   default "fsl,ls1043a-pcie" if ARCH_LS1043A
>   default "fsl,ls1046a-pcie" if ARCH_LS1046A
>   default "fsl,ls2080a-pcie" if ARCH_LS2080A
> + default "fsl,ls1080a-pcie" if ARCH_LS1088A

Did you intentionally use "ls1080a-pcie" here?

>   help
> This compatible is used to find pci controller node in Kernel DT
> to complete fixup.
> @@ -228,6 +253,7 @@ config MAX_CPUS
>   default 

Re: [U-Boot] [PATCH v1 13/15] efi_loader: make pool allocations cacheline aligned

[Heinrich Schuchardt]

On 08/10/2017 08:29 PM, Rob Clark wrote:
> This avoids printf() spam about file reads (such as loading an image)
> into unaligned buffers (and the associated memcpy()).  And generally
> seems like a good idea.
> 
> Signed-off-by: Rob Clark 
> ---
>  lib/efi_loader/efi_memory.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
> index 9e079f1fa3..2ba8d8b42b 100644
> --- a/lib/efi_loader/efi_memory.c
> +++ b/lib/efi_loader/efi_memory.c
> @@ -43,7 +43,7 @@ void *efi_bounce_buffer;
>   */
>  struct efi_pool_allocation {
>   u64 num_pages;
> - char data[];
> + char data[] __attribute__((aligned(ARCH_DMA_MINALIGN)));
>  };
>  
>  /*
> @@ -356,7 +356,8 @@ efi_status_t efi_allocate_pool(int pool_type, unsigned 
> long size,
>  {
>   efi_status_t r;
>   efi_physical_addr_t t;
> - u64 num_pages = (size + sizeof(u64) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
> + u64 num_pages = DIV_ROUND_UP(size + sizeof(struct efi_pool_allocation),
> +  EFI_PAGE_SIZE);

It seems you missed my mail dated 2017-08-02T01:21Z:

With DIV_ROUND_UP you introduce a 64bit division. Depending on the
architecture this is only available via stdlib which is not available in
U-Boot.

Please, use
+ EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
as in the original line.

Best regards

Heinrich

>  
>   if (size == 0) {
>   *buffer = NULL;
> 

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Re: [U-Boot] [PATCH v1 05/15] efi_loader: add device-path utils

[Heinrich Schuchardt]

On 08/10/2017 08:29 PM, Rob Clark wrote:
> Helpers to construct device-paths from devices, partitions, files, and
> for parsing and manipulating device-paths.
> 
> For non-legacy devices, this will use u-boot's device-model to construct
> device-paths which include bus hierarchy to construct device-paths.  For
> legacy devices we still fake it, but slightly more convincingly.
> 
> Signed-off-by: Rob Clark 
> ---
>  include/efi_api.h|  10 +
>  include/efi_loader.h |  20 ++
>  lib/efi_loader/Makefile  |   2 +-
>  lib/efi_loader/efi_device_path.c | 489 
> +++
>  4 files changed, 520 insertions(+), 1 deletion(-)
>  create mode 100644 lib/efi_loader/efi_device_path.c
> 
> diff --git a/include/efi_api.h b/include/efi_api.h
> index b761cf4822..4e27c82129 100644
> --- a/include/efi_api.h
> +++ b/include/efi_api.h
> @@ -314,6 +314,7 @@ struct efi_device_path_acpi_path {
>  #define DEVICE_PATH_TYPE_MESSAGING_DEVICE0x03
>  #  define DEVICE_PATH_SUB_TYPE_MSG_USB   0x05
>  #  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR  0x0b
> +#  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f
>  #  define DEVICE_PATH_SUB_TYPE_MSG_SD0x1a
>  #  define DEVICE_PATH_SUB_TYPE_MSG_MMC   0x1d
>  
> @@ -329,6 +330,15 @@ struct efi_device_path_mac_addr {
>   u8 if_type;
>  } __packed;
>  
> +struct efi_device_path_usb_class {
> + struct efi_device_path dp;
> + u16 vendor_id;
> + u16 product_id;
> + u8 device_class;
> + u8 device_subclass;
> + u8 device_protocol;
> +} __packed;
> +
>  struct efi_device_path_sd_mmc_path {
>   struct efi_device_path dp;
>   u8 slot_number;
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index 037cc7c543..bcca6e49ea 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -197,6 +197,26 @@ extern void *efi_bounce_buffer;
>  #define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
>  #endif
>  
> +
> +struct efi_device_path *efi_dp_next(struct efi_device_path *dp);
> +int efi_dp_match(struct efi_device_path *a, struct efi_device_path *b);
> +struct efi_object *efi_dp_find_obj(struct efi_device_path *dp);
> +unsigned efi_dp_size(struct efi_device_path *dp);
> +struct efi_device_path *efi_dp_dup(struct efi_device_path *dp);
> +
> +struct efi_device_path *efi_dp_from_dev(struct udevice *dev);
> +struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
> +struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part,
> +  const char *path);
> +struct efi_device_path *efi_dp_from_eth(void);
> +void efi_dp_split_file_path(struct efi_device_path *full_path,
> + struct efi_device_path **device_path,
> + struct efi_device_path **file_path);
> +
> +#define EFI_DP_TYPE(_dp, _type, _subtype) \
> + (((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
> +  ((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
> +
>  /* Convert strings from normal C strings to uEFI strings */
>  static inline void ascii2unicode(u16 *unicode, const char *ascii)
>  {
> diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
> index 30bf343a36..f35e5ce8a8 100644
> --- a/lib/efi_loader/Makefile
> +++ b/lib/efi_loader/Makefile
> @@ -15,7 +15,7 @@ always := $(efiprogs-y)
>  
>  obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
>  obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
> -obj-y += efi_memory.o efi_device_path_to_text.o
> +obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o
>  obj-$(CONFIG_LCD) += efi_gop.o
>  obj-$(CONFIG_DM_VIDEO) += efi_gop.o
>  obj-$(CONFIG_PARTITIONS) += efi_disk.o
> diff --git a/lib/efi_loader/efi_device_path.c 
> b/lib/efi_loader/efi_device_path.c
> new file mode 100644
> index 00..e8a6bbff82
> --- /dev/null
> +++ b/lib/efi_loader/efi_device_path.c
> @@ -0,0 +1,489 @@
> +/*
> + * EFI device path from u-boot device-model mapping
> + *
> + * (C) Copyright 2017 Rob Clark
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* template END node: */
> +static const struct efi_device_path END = {
> + .type = DEVICE_PATH_TYPE_END,
> + .sub_type = DEVICE_PATH_SUB_TYPE_END,
> + .length   = sizeof(END),
> +};
> +
> +#define U_BOOT_GUID \
> + EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
> +  0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
> +
> +/* template ROOT node, a fictional ACPI PNP device: */
> +static const struct efi_device_path_vendor ROOT = {
> + .dp = {
> + .type = DEVICE_PATH_TYPE_HARDWARE_DEVICE,
> + .sub_type = DEVICE_PATH_SUB_TYPE_VENDOR,
> + .length   = sizeof(ROOT),
> + },
> + .guid = U_BOOT_GUID,
> +};
> +
> +
> +/*
> + * Iterate to next block in 

[U-Boot] [PATCH v4 1/2] net: Add mii_resolve_flowctrl_fdx()

[yuiko.oshino]

From: Yuiko Oshino 

Add support for Microchip LAN7500, LAN7800 and LAN7850,
USB to 10/100/1000 Ethernet Controllers.

Signed-off-by: Yuiko Oshino 
Acked-by: Joe Hershberger 

---

Changes in v4:
   - none.

Changes in v3:
   - This patch is added to a series.

Changes in v2:
   - The patch's tag is changed to net:.

 include/linux/mii.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/include/linux/mii.h b/include/linux/mii.h
index 66b83d8..19afb74 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -190,4 +190,27 @@ static inline unsigned int mii_duplex (unsigned int 
duplex_lock,
return 0;
 }
 
+/**
+ * mii_resolve_flowctrl_fdx
+ * @lcladv: value of MII ADVERTISE register
+ * @rmtadv: value of MII LPA register
+ *
+ * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
+ */
+static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
+{
+   u8 cap = 0;
+
+   if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
+   cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+   } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
+   if (lcladv & ADVERTISE_PAUSE_CAP)
+   cap = FLOW_CTRL_RX;
+   else if (rmtadv & ADVERTISE_PAUSE_CAP)
+   cap = FLOW_CTRL_TX;
+   }
+
+   return cap;
+}
+
 #endif /* __LINUX_MII_H__ */
-- 
2.7.4


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Re: [U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

[York Sun]

On 08/11/2017 12:26 AM, Ran Wang wrote:

> +static void erratum_a009008(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
> + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
> +
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
> + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
> +#elif defined(CONFIG_ARCH_LS2080A)
> + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
> +
> + val &= ~(0xF << 6);
> + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
> +#endif
> +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
> +}

Ran,

Wouldn't it be cleaner to make an inline function like this

static inline void usb_errata_a009008(u32 __iomem *scfg, u32 offset)
{
u32 val;

val = scfg_in32(scfg + offset / 4) & ~(0xF << 6);
val |= USB_TXVREFTUNE << 6;
scfg_out32(scfg + offset / 4, val);
}

Then your function can be rewritten as

static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;

#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB1);
usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB2);
usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB3);
usb_errata_a009008(scfg, SCFG_USB3PRM1CR_USB4);
#elif defined(CONFIG_ARCH_LS2080A)
usb_errata_a009008(scfg, SCFG_USB3PRM1CR);
#else
#error Platform not defined
#endif
#endif
}

York
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Re: [U-Boot] [PATCH v1 03/15] part: extract MBR signature from partitions

[Heinrich Schuchardt]

Hello Rob,

I couldn't apply your patch to either of

u-boot/agraf/efi-next nor
u-boot/master

Applying: part: extract MBR signature from partitions
error: patch failed: include/blk.h:62
error: include/blk.h: patch does not apply
Patch failed at 0001 part: extract MBR signature from partitions

Plese, rebase your patch or indicate prerequisote patches.

Best regards

Heinrich

On 08/10/2017 08:29 PM, Rob Clark wrote:
> From: Peter Jones 
> 
> EFI client programs need the signature information from the partition
> table to determine the disk a partition is on, so we need to fill that
> in here.
> 
> Signed-off-by: Peter Jones 
> [separated from efi_loader part, and fixed build-errors for non-
>  CONFIG_EFI_PARTITION case]
> Signed-off-by: Rob Clark 
> ---
>  disk/part_dos.c| 12 +---
>  disk/part_efi.c| 20 
>  include/blk.h  | 15 +++
>  include/efi.h  |  4 
>  include/part.h |  3 ++-
>  include/part_efi.h |  4 
>  6 files changed, 50 insertions(+), 8 deletions(-)
> 
> diff --git a/disk/part_dos.c b/disk/part_dos.c
> index 7ede15ec26..850a538e83 100644
> --- a/disk/part_dos.c
> +++ b/disk/part_dos.c
> @@ -89,14 +89,20 @@ static int test_block_type(unsigned char *buffer)
>  
>  static int part_test_dos(struct blk_desc *dev_desc)
>  {
> - ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
> + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz);
>  
> - if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1)
> + if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1)
>   return -1;
>  
> - if (test_block_type(buffer) != DOS_MBR)
> + if (test_block_type((unsigned char *)mbr) != DOS_MBR)
>   return -1;
>  
> + if (dev_desc->sig_type == SIG_TYPE_NONE &&
> + mbr->unique_mbr_signature != 0) {
> + dev_desc->sig_type = SIG_TYPE_MBR;
> + dev_desc->mbr_sig = mbr->unique_mbr_signature;
> + }
> +
>   return 0;
>  }
>  
> diff --git a/disk/part_efi.c b/disk/part_efi.c
> index 1b7ba27947..71e4188455 100644
> --- a/disk/part_efi.c
> +++ b/disk/part_efi.c
> @@ -871,11 +871,19 @@ static int is_pmbr_valid(legacy_mbr * mbr)
>  static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
>   gpt_header *pgpt_head, gpt_entry **pgpt_pte)
>  {
> + ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, mbr, dev_desc->blksz);
> +
>   if (!dev_desc || !pgpt_head) {
>   printf("%s: Invalid Argument(s)\n", __func__);
>   return 0;
>   }
>  
> + /* Read MBR Header from device */
> + if (blk_dread(dev_desc, 0, 1, (ulong *)mbr) != 1) {
> + printf("*** ERROR: Can't read MBR header ***\n");
> + return 0;
> + }
> +
>   /* Read GPT Header from device */
>   if (blk_dread(dev_desc, (lbaint_t)lba, 1, pgpt_head) != 1) {
>   printf("*** ERROR: Can't read GPT header ***\n");
> @@ -885,6 +893,18 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 
> lba,
>   if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
>   return 0;
>  
> + if (dev_desc->sig_type == SIG_TYPE_NONE) {
> + efi_guid_t empty = {};
> + if (memcmp(_head->disk_guid, , sizeof(empty))) {
> + dev_desc->sig_type = SIG_TYPE_GUID;
> + memcpy(_desc->guid_sig, _head->disk_guid,
> +   sizeof(empty));
> + } else if (mbr->unique_mbr_signature != 0) {
> + dev_desc->sig_type = SIG_TYPE_MBR;
> + dev_desc->mbr_sig = mbr->unique_mbr_signature;
> + }
> + }
> +
>   /* Read and allocate Partition Table Entries */
>   *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
>   if (*pgpt_pte == NULL) {
> diff --git a/include/blk.h b/include/blk.h
> index ef29a07ee2..3a5e04c00d 100644
> --- a/include/blk.h
> +++ b/include/blk.h
> @@ -8,6 +8,8 @@
>  #ifndef BLK_H
>  #define BLK_H
>  
> +#include 
> +
>  #ifdef CONFIG_SYS_64BIT_LBA
>  typedef uint64_t lbaint_t;
>  #define LBAFlength "ll"
> @@ -35,6 +37,14 @@ enum if_type {
>   IF_TYPE_COUNT,  /* Number of interface types */
>  };
>  
> +enum sig_type {
> + SIG_TYPE_NONE,
> + SIG_TYPE_MBR,
> + SIG_TYPE_GUID,
> +
> + SIG_TYPE_COUNT  /* Number of signature types */
> +};
> +
>  /*
>   * With driver model (CONFIG_BLK) this is uclass platform data, accessible
>   * with dev_get_uclass_platdata(dev)
> @@ -62,6 +72,11 @@ struct blk_desc {
>   charvendor[40+1];   /* IDE model, SCSI Vendor */
>   charproduct[20+1];  /* IDE Serial no, SCSI product */
>   charrevision[8+1];  /* firmware revision */
> + enum sig_type   sig_type;   /* Partition table signature type */
> + union {
> + uint32_t mbr_sig;   /* MBR integer 

Re: [U-Boot] [PATCH v1 01/15] fs: add fs_readdir()

[Heinrich Schuchardt]

On 08/10/2017 08:29 PM, Rob Clark wrote:
> Needed to support efi file protocol.  The fallback.efi loader wants
> to be able to read the contents of the /EFI directory to find an OS
> to boot.
> 
> Also included is an ls2 command which implements ls on top of
> fs_readdir(), to more easily test the readdir functionality.
> 
> Signed-off-by: Rob Clark 
> ---
>  cmd/fs.c | 14 +++
>  fs/fs.c  | 80 
> 
>  include/fs.h | 23 +
>  3 files changed, 117 insertions(+)
> 
> diff --git a/cmd/fs.c b/cmd/fs.c
> index abfe5be172..58ddcec1a9 100644
> --- a/cmd/fs.c
> +++ b/cmd/fs.c
> @@ -75,6 +75,20 @@ U_BOOT_CMD(
>   "  device type 'interface' instance 'dev'."
>  )
>  
> +static int do_ls2_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
> + char * const argv[])
> +{
> + return do_ls2(cmdtp, flag, argc, argv, FS_TYPE_ANY);
> +}
> +
> +U_BOOT_CMD(
> + ls2,4,  1,  do_ls2_wrapper,
> + "list files in a directory using fs_readdir (default /)",
> + " [ [directory]]\n"
> + "- List files in directory 'directory' of partition 'part' on\n"
> + "  device type 'interface' instance 'dev'."
> +)
> +
>  static int do_fstype_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
>   char * const argv[])
>  {
> diff --git a/fs/fs.c b/fs/fs.c
> index 595ff1fe69..5720ceec49 100644
> --- a/fs/fs.c
> +++ b/fs/fs.c
> @@ -69,6 +69,12 @@ static inline int fs_uuid_unsupported(char *uuid_str)
>   return -1;
>  }
>  
> +static inline int fs_readdir_unsupported(const char *filename, loff_t offset,
> +  struct fs_dirent *dent)
> +{
> + return -ENXIO;
> +}
> +
>  struct fstype_info {
>   int fstype;
>   char *name;
> @@ -92,6 +98,7 @@ struct fstype_info {
>loff_t len, loff_t *actwrite);
>   void (*close)(void);
>   int (*uuid)(char *uuid_str);
> + int (*readdir)(const char *filename, loff_t offset, struct fs_dirent 
> *dent);
>  };
>  
>  static struct fstype_info fstypes[] = {
> @@ -112,6 +119,7 @@ static struct fstype_info fstypes[] = {
>   .write = fs_write_unsupported,
>  #endif
>   .uuid = fs_uuid_unsupported,
> + .readdir = fs_readdir_unsupported,
>   },
>  #endif
>  #ifdef CONFIG_FS_EXT4
> @@ -131,6 +139,7 @@ static struct fstype_info fstypes[] = {
>   .write = fs_write_unsupported,
>  #endif
>   .uuid = ext4fs_uuid,
> + .readdir = fs_readdir_unsupported,
>   },
>  #endif
>  #ifdef CONFIG_SANDBOX
> @@ -146,6 +155,7 @@ static struct fstype_info fstypes[] = {
>   .read = fs_read_sandbox,
>   .write = fs_write_sandbox,
>   .uuid = fs_uuid_unsupported,
> + .readdir = fs_readdir_unsupported,
>   },
>  #endif
>  #ifdef CONFIG_CMD_UBIFS
> @@ -161,6 +171,7 @@ static struct fstype_info fstypes[] = {
>   .read = ubifs_read,
>   .write = fs_write_unsupported,
>   .uuid = fs_uuid_unsupported,
> + .readdir = fs_readdir_unsupported,
>   },
>  #endif
>   {
> @@ -175,6 +186,7 @@ static struct fstype_info fstypes[] = {
>   .read = fs_read_unsupported,
>   .write = fs_write_unsupported,
>   .uuid = fs_uuid_unsupported,
> + .readdir = fs_readdir_unsupported,
>   },
>  };
>  
> @@ -334,6 +346,19 @@ int fs_write(const char *filename, ulong addr, loff_t 
> offset, loff_t len,
>   return ret;
>  }
>  
> +int fs_readdir(const char *filename, loff_t offset, struct fs_dirent *dent)
> +{
> + struct fstype_info *info = fs_get_info(fs_type);
> + int ret;
> +
> + memset(dent, 0, sizeof(*dent));
> +
> + ret = info->readdir(filename, offset, dent);
> + fs_close();
> +
> + return ret;
> +}
> +
>  int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
>   int fstype)
>  {
> @@ -440,6 +465,61 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * 
> const argv[],
>   return 0;
>  }
>  
> +int do_ls2(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
> + int fstype)
> +{
> + const char *filename = argc >= 4 ? argv[3] : "/";

Do we really want to update filename and dev_part_str if argc is illegal?

I would suggest to put the assignments below the argc check.

Could you, please, add comment lines above the function describing the
usage of argv[0..3].

Best regards

Heinrich

> + const char *ifname = argv[1];
> + const char *dev_part_str = (argc >= 3) ? argv[2] : NULL;
> + loff_t offset = 0;
> + int ret, files = 0, dirs = 0;
> +
> + if (argc < 2)
> + return CMD_RET_USAGE;
> + if (argc > 4)
> + return CMD_RET_USAGE;
> +
> + while (1) {
> + struct fs_dirent dent, dent2;
> + char buf[256];
> +
> + 

Re: [U-Boot] [PATCH] drivers:net:fsl-mc: Update MC address calculation

[York Sun]

On 08/10/2017 10:46 PM, Priyanka Jain wrote:
> 
>> -Original Message-
>> From: York Sun
>> Sent: Wednesday, August 09, 2017 10:19 PM
>> To: Priyanka Jain ; u-boot@lists.denx.de
>> Cc: Ashish Kumar 
>> Subject: Re: [PATCH] drivers:net:fsl-mc: Update MC address calculation
>>
>> On 06/23/2017 03:30 AM, Priyanka Jain wrote:
>>> Update MC address caluclation as per MC design requirement of address
>>> as least significant 512MB address of MC private allocated memory.
>>>
>>> Signed-off-by: Priyanka Jain 
>>> Signed-off-by: Ashish Kumar 
>>> ---
>>>drivers/net/fsl-mc/mc.c |7 ++-
>>>1 files changed, 6 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index
>>> eeecb2d..623586c 100644
>>> --- a/drivers/net/fsl-mc/mc.c
>>> +++ b/drivers/net/fsl-mc/mc.c
>>> @@ -704,10 +704,15 @@ int get_dpl_apply_status(void)
>>>
>>>/**
>>> * Return the MC address of private DRAM block.
>>> + * MC address should be least significant 512MB address
>>> + * of MC private memory
>>> */
>>>u64 mc_get_dram_addr(void)
>>>{
>>> -   return gd->arch.resv_ram;
>>> +   size_t mc_ram_size = mc_get_dram_block_size();
>>> +
>>> +   return (gd->arch.resv_ram + mc_ram_size - 1) &
>>> +   MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
>>>}
>>>
>>>/**
>>>
>>
>> Priyanka,
>>
>> This looks odd. You already have the address aligned by
>> CONFIG_SYS_MC_RSV_MEM_ALIGN (512MB by default), tracked by
>> gd->arch.resv_ram. Did you find the address is wrong sometimes?
>>
>> York
> 
> York,
> 
> As per MC design requirement, MC memory should be 512MB aligned for which 
> start address is gd->arch.resv_ram.
> But the MC core’s initial boot address should not contain start address. It 
> must be located in the least significant 512MB of its address range.
> So this change is basically shifting address from start of memory towards end 
> of Memory (which is least significant 512MB address).
> 

Priyanka,

You confused me. The reserved memory tracked by gd->arch.resv_ram is the 
beginning of the memory, aligned to 512MB (CONFIG_SYS_MC_RSV_MEM_ALIGN). 
It is naturally the lowest address in the reserved block. Isn't it 
"least significant"? If this involves complicated address allocation, 
please follow up with me for in-depth internal discussion.

York

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Re: [U-Boot] [PATCH v3 1/3] efi_loader: write protocol GUID in OpenProtocol

[Heinrich Schuchardt]

On 08/11/2017 12:11 PM, Alexander Graf wrote:
> 
> 
> On 05.08.17 21:32, Heinrich Schuchardt wrote:
>> To understand what happens in OpenProtocol it is necessary to know
>> the protocol interface GUID. Let's write a debug message.
>>
>> Using uuid_guid_get_str would be quite clumsy for this purpose.
>> This would involve evaluating _DEBUG which probably should not be used
>> outside common.h.
>>
>> Cc: Rob Clark 
>> Signed-off-by: Heinrich Schuchardt 
> 
> I agree with Rob that a printf extension would be the nicest way to go
> here. We could then just use that instead of the %p in EFI_ENTRY() that
> we have today.
> 
> 
> Alex
> 

Hello Alex,

I am aware of
[PATCH 4/5] vsprintf.c: add GUID printing,

I just wonder if you wnat to take this patch series as is and we modify
EFI_PRINT_GUID afterwards

or

we I shall remove GUID printing and resend the patch series without it.

Best regards

Heinrich
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Re: [U-Boot] [PATCH v2 4/5] arm: socfpga: Add intermediate driver between flash and FPGA manager

[Marek Vasut]

On 08/10/2017 06:43 AM, Chee, Tien Fong wrote:
> On Rab, 2017-08-09 at 10:29 +0200, Marek Vasut wrote:
>> On 08/09/2017 06:50 AM, Chee, Tien Fong wrote:
>> [...]
>>
>>>

>
>>
>> If this is for some FPGA loading, can this functionality be
>> scripted
>> instead?
>>
> Sorry, i'm not getting you. How functionality be scripted?
> Could
> you
> provide some example or details explanation?
 ie. "load" (from fs) + "fpga load" (program FPGA) commands ?
 I think the fpga command already has some support for loading
 from FS
 too.

>>> Currently, we already have fpga load commands in fpga driver, fpga
>>> rbf
>>> is loaded to memory, and programmed to fpga from memory, where
>>> memory
>>> location would be decided by user, it could be OCRAM or SDRAM.
>>>
>>> for fpga loadfs command, i plan to implement it after having
>>> complete
>>> boot to U-boot console, since this is quite complex and involving
>>> some
>>> hardware workaround issue, and some use case scenarios need to be
>>> considerd.
>> So the arria10 u-boot port is still unable to boot to console ?
>>
> Still need 2 to 3 more patchsets to get it boot to console.
>>>
>>> For example reconfiguring fpga with periperal rbf can
>>> corrupt the sdram since sdram IOs is part of the fpga periph rbf. I
>>> need console to run a lot different scenarios testing.
>> OK
>>
>>>
>>> We still need cff.c, because most functionality in cff.c are
>>> required
>>> by fpga loadfs command.
>> It seems a lot of stuff from this is common code, so why does it have
>> to
>> be in this driver again ?
> This driver contains a lot "smart" functionality such as:

I start to cringe when I read "smart functionality".

> 1: It having ability to the right memory(OCRAM or SDRAM) to achieve the
> best FPGA programing performance.

Did you find significant throughput difference ?

> 2: It can determine the right size buffer for the fpga rbf without info
> of buffer size defined by user.

You mean like $filesize variable in the command prompt ?

> 3: It has ability to know what kind of fpga rbf type, and security
> type, such as peripheral, core, combined rbf, encryption and
> unencryption based on any fpga file user pass in .

Is this information used for anything ? I was under the impression that
the user just needs to load in the correct RBF file into the FPGA.

> 4: It supports the checksum.

What checksum ? Can we have a generic hook into the FPGA framework ?

> 5: support raw flash without fs.

This should go into common code.

> 6: support the file name defined in DTS and U-boot environment
> variable.

I think you should extend the FPGA LOADFS here instead.

>>  Also, the ifdeffery is awful and the explicit
>> depedence on VFAT when loading from FS is real bad.
>>
> It is because a lot functions is common to sdmmc, nand and qspi in
> different fs such as vfat, ubi and raw. It is unavoidable to have some
> ifdeffery if we want to keep the function common to all flashes and
> fs. 

Can the FPGA LOADFS be extended generically ?

>> [...]


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Re: [U-Boot] [PATCH v2 2/5] arm: socfpga: Add checking function on FPGA setting in FDT

[Marek Vasut]

On 08/10/2017 06:51 AM, Chee, Tien Fong wrote:
> On Rab, 2017-08-09 at 10:20 +0200, Marek Vasut wrote:
>> On 08/09/2017 07:07 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2017-08-08 at 11:29 +0200, Marek Vasut wrote:

 On 08/08/2017 11:12 AM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien Fong Chee 
>
> Function for checking FPGA early release setting which is
> defined
> by user in FDT chosen section. This function would be used by
> later driver in decision applying appropriate FPGA
> configuration in
> early release or full FPGA booting mode.
 Isn't this a property of the FPGA driver ?
> This is not property of fpga driver. It acts like passing data flag to
> u-boot, so u-boot knows how to boot in the mode defined by user.

So it's a configuration option ? Doing what ... since there's no binding
document, it's not clear.

 Shouldn't this have altr, prefix ?
> This node doesn't represet a real device, it acts like a place for
> passing data to U-boot. So, this flag name doesn't matter with prefix,
> right?

But it's altera-specific, so it should have one ?

 Did this go through DT binding review?
> No, refer my explanation above.

>>> This is our own define under chosen section. This is flag to tell
>>> U-
>>> boot what kind of boot and what kind of fpga configuration we want
>>> during boot.
>> And you didn't answer any of the aforementioned questions :(
>>
> Sorry, it could be i misunderstand your question. please refer my
> asnwer in above.
>>>

>
>
> Signed-off-by: Tien Fong Chee 
> ---
>  arch/arm/mach-socfpga/include/mach/misc.h |  1 +
>  arch/arm/mach-socfpga/misc_arria10.c  | 20
> 
>  2 files changed, 21 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> b/arch/arm/mach-socfpga/include/mach/misc.h
> index 0b65783..e003f8a 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -26,6 +26,7 @@ static inline void socfpga_fpga_add(void) {}
>  unsigned int dedicated_uart_com_port(const void *blob);
>  unsigned int shared_uart_com_port(const void *blob);
>  unsigned int uart_com_port(const void *blob);
> +int is_early_release_fpga_config(const void *blob);
>  #endif
>  
>  #endif /* _MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/misc_arria10.c
> b/arch/arm/mach-
> socfpga/misc_arria10.c
> index 9d751f6..2d6e977 100644
> --- a/arch/arm/mach-socfpga/misc_arria10.c
> +++ b/arch/arm/mach-socfpga/misc_arria10.c
> @@ -235,6 +235,26 @@ unsigned int uart_com_port(const void
> *blob)
>   return shared_uart_com_port(blob);
>  }
>  
> +int is_chosen_boolean_true(const void *blob, const char *name)
> +{
> + int node;
> + int rval = 0;
> +
> + node = fdt_subnode_offset(blob, 0, "chosen");
> +
> + if (node >= 0)
> + rval = fdtdec_get_bool(blob, node, name);
> +
> + return rval;
> +}
> +
> +int is_early_release_fpga_config(const void *blob)
> +{
> + static const char *name = "early-release-fpga-config";
> +
> + return is_chosen_boolean_true(blob, name);
> +}
> +
>  /*
>   * Print CPU information
>   */
>


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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[Tom Rini]

On Thu, Aug 10, 2017 at 03:34:49PM +, York Sun wrote:

> Tom,
> 
> The following changes since commit eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
> 
>common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04 
> 20:38:39 -0400)
> 
> are available in the git repository at:
> 
>git://git.denx.de/u-boot-fsl-qoriq.git
> 
> for you to fetch changes up to 1c83df6f3f95055ed1c8fb40d1d0604863eab78b:
> 
>armv8: ls2080a: Increase env sector size for qspi boot (2017-08-09 
> 09:57:33 -0700)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[York Sun]

On 08/11/2017 07:34 AM, Tom Rini wrote:
> On Fri, Aug 11, 2017 at 02:35:24AM +, York Sun wrote:
>> On 08/10/2017 07:18 PM, Tom Rini wrote:
>>> On Thu, Aug 10, 2017 at 03:34:49PM +, York Sun wrote:
>>>
 Tom,

 The following changes since commit 
 eaa90e5df2a4a1cb12fb73571978a9379242d0b5:

  common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04
 20:38:39 -0400)

 are available in the git repository at:

  git://git.denx.de/u-boot-fsl-qoriq.git

 for you to fetch changes up to 1c83df6f3f95055ed1c8fb40d1d0604863eab78b:

  armv8: ls2080a: Increase env sector size for qspi boot (2017-08-09
 09:57:33 -0700)

>>>
>>> This seems to lead to a number of PowerPC boards failing, can you please
>>> throw this at travis-ci and fix the fallout?  See
>>> https://travis-ci.org/trini/u-boot/builds/263245350, thanks!
>>>
>>
>> I made sure the compiling was OK before request a pull. See
>> https://travis-ci.org/yorksun/u-boot/builds/262844095.
> 
> OK, confirmed, sorry for the noise!
> 

Glad it passed.

York
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[U-Boot] [PATCH v4 1/1] mmc: Add MMC support for stm32h7 Socs

[patrice.chotard]

From: Patrice Chotard 

This patch adds SD/MMC support for STM32H7 SoCs.

Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
 _ Full compliance with MultiMediaCard System Specification
   Version 4.51. Card support for three different databus modes:
   1-bit (default), 4-bit and 8-bit.
 _ Full compatibility with previous versions of MultiMediaCards
   (backward compatibility).
 _ Full compliance with SD memory card specifications version 4.1.
   (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
SPI mode and UHS-II mode not supported).
 _ Full compliance with SDIO card specification version 4.0.
   Card support for two different databus modes: 1-bit (default)
   and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
   speed, SPI mode and UHS-II mode not supported).
 _ Data transfer up to 208 Mbyte/s for the 8 bit mode.
   (depending maximum allowed IO speed).
 _ Data and command output enable signals to control external
   bidirectional drivers.

The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.

Signed-off-by: Christophe Kerello 
Signed-off-by: Patrice Chotard 
---
v4: _ replace mmc_create() usage by mmc_bind() callback
_ rename struct stm32_sdmmc2_host to stm32_sdmmc2_priv
v3: _ use registers offset instead of registers struct description
_ rename clk_reg_add and pwr_reg_add to respectively clk_reg_msk and 
pwr_reg_msk
_ don't exit in error if DT bus-width value is not correct, force it to 1
  and continue
v2: _ add .get_cd() callback support

 drivers/mmc/Kconfig|   8 +
 drivers/mmc/Makefile   |   1 +
 drivers/mmc/stm32_sdmmc2.c | 601 +
 3 files changed, 610 insertions(+)
 create mode 100644 drivers/mmc/stm32_sdmmc2.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 82b8d75..6ac7ab2 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -377,6 +377,14 @@ config GENERIC_ATMEL_MCI
  the SD Memory Card Specification V2.0, the SDIO V2.0 specification
  and CE-ATA V1.1.
 
+config STM32_SDMMC2
+   bool "STMicroelectronics STM32H7 SD/MMC Host Controller support"
+   depends on DM_MMC && BLK && OF_CONTROL && DM_MMC_OPS
+   help
+ This selects support for the SD/MMC controller on STM32H7 SoCs.
+ If you have a board based on such a SoC and with a SD/MMC slot,
+ say Y or M here.
+
 endif
 
 config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2d781c3..2584663 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_MMC_SANDBOX)  += sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
+obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o
 
 # SDHCI
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
new file mode 100644
index 000..9ef6b79
--- /dev/null
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD,  for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct stm32_sdmmc2_plat {
+   struct mmc_config cfg;
+   struct mmc mmc;
+};
+
+struct stm32_sdmmc2_priv {
+   fdt_addr_t base;
+   struct clk clk;
+   struct reset_ctl reset_ctl;
+   struct gpio_desc cd_gpio;
+   u32 clk_reg_msk;
+   u32 pwr_reg_msk;
+};
+
+struct stm32_sdmmc2_ctx {
+   u32 cache_start;
+   u32 cache_end;
+   u32 data_length;
+   bool dpsm_abort;
+};
+
+/* SDMMC REGISTERS OFFSET */
+#define SDMMC_POWER0x00/* SDMMC power control */
+#define SDMMC_CLKCR0x04/* SDMMC clock control */
+#define SDMMC_ARG  0x08/* SDMMC argument  */
+#define SDMMC_CMD  0x0C/* SDMMC command   */
+#define SDMMC_RESP10x14/* SDMMC response 1*/
+#define SDMMC_RESP20x18/* SDMMC response 2*/
+#define SDMMC_RESP30x1C/* SDMMC response 3*/
+#define SDMMC_RESP40x20/* SDMMC response 4*/
+#define SDMMC_DTIMER   0x24/* SDMMC data timer*/
+#define SDMMC_DLEN 0x28/* SDMMC data length   */
+#define SDMMC_DCTRL0x2C/* SDMMC data control  */
+#define SDMMC_DCOUNT   0x30/* SDMMC data counter  */
+#define SDMMC_STA  0x34/* SDMMC status 

Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[Tom Rini]

On Fri, Aug 11, 2017 at 02:35:24AM +, York Sun wrote:
> On 08/10/2017 07:18 PM, Tom Rini wrote:
> > On Thu, Aug 10, 2017 at 03:34:49PM +, York Sun wrote:
> > 
> >> Tom,
> >>
> >> The following changes since commit 
> >> eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
> >>
> >> common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04
> >> 20:38:39 -0400)
> >>
> >> are available in the git repository at:
> >>
> >> git://git.denx.de/u-boot-fsl-qoriq.git
> >>
> >> for you to fetch changes up to 1c83df6f3f95055ed1c8fb40d1d0604863eab78b:
> >>
> >> armv8: ls2080a: Increase env sector size for qspi boot (2017-08-09
> >> 09:57:33 -0700)
> >>
> > 
> > This seems to lead to a number of PowerPC boards failing, can you please
> > throw this at travis-ci and fix the fallout?  See
> > https://travis-ci.org/trini/u-boot/builds/263245350, thanks!
> > 
> 
> I made sure the compiling was OK before request a pull. See 
> https://travis-ci.org/yorksun/u-boot/builds/262844095.

OK, confirmed, sorry for the noise!

-- 
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Re: [U-Boot] [PATCH v3 1/1] mmc: Add MMC support for stm32h7 Socs

[Patrice CHOTARD]

Hi Simon

On 08/10/2017 05:57 PM, Patrice CHOTARD wrote:
> Hi Simon
> 
> On 08/06/2017 07:15 AM, Simon Glass wrote:
>> Hi Patrice,
>>
>> On 20 July 2017 at 02:34,   wrote:
>>> From: Patrice Chotard 
>>>
>>> This patch adds SD/MMC support for STM32H7 SoCs.
>>>
>>> Here is an extraction of SDMMC main features, embedded in
>>> STM32H7 SoCs.
>>> The SD/MMC block include the following:
>>>_ Full compliance with MultiMediaCard System Specification
>>>  Version 4.51. Card support for three different databus modes:
>>>  1-bit (default), 4-bit and 8-bit.
>>>_ Full compatibility with previous versions of MultiMediaCards
>>>  (backward compatibility).
>>>_ Full compliance with SD memory card specifications version 4.1.
>>>  (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
>>>   SPI mode and UHS-II mode not supported).
>>>_ Full compliance with SDIO card specification version 4.0.
>>>  Card support for two different databus modes: 1-bit (default)
>>>  and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
>>>  speed, SPI mode and UHS-II mode not supported).
>>>_ Data transfer up to 208 Mbyte/s for the 8 bit mode.
>>>  (depending maximum allowed IO speed).
>>>_ Data and command output enable signals to control external
>>>  bidirectional drivers.
>>>
>>> The current version of the SDMMC supports only one SD/SDIO/MMC card
>>> at any one time and a stack of MMC Version 4.51 or previous.
>>>
>>> Signed-off-by: Christophe Kerello 
>>> Signed-off-by: Patrice Chotard 
>>> ---
>>> v3: _ use registers offset instead of registers struct description
>>>   _ rename clk_reg_add and pwr_reg_add to respectively clk_reg_msk and 
>>> pwr_reg_msk
>>>   _ don't exit in error if DT bus-width value is not correct, force it 
>>> to 1
>>> and continue
>>> v2: _ add .get_cd() callback support
>>>
>>>drivers/mmc/Kconfig|   8 +
>>>drivers/mmc/Makefile   |   1 +
>>>drivers/mmc/stm32_sdmmc2.c | 598 
>>> +
>>>3 files changed, 607 insertions(+)
>>>create mode 100644 drivers/mmc/stm32_sdmmc2.c
>>>
>>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
>>> index 82b8d75..f2e4c26 100644
>>> --- a/drivers/mmc/Kconfig
>>> +++ b/drivers/mmc/Kconfig
>>> @@ -377,6 +377,14 @@ config GENERIC_ATMEL_MCI
>>> the SD Memory Card Specification V2.0, the SDIO V2.0 
>>> specification
>>> and CE-ATA V1.1.
>>>
>>> +config STM32_SDMMC2
>>> +   bool "STMicroelectronics STM32H7 SD/MMC Host Controller support"
>>> +   depends on DM_MMC && OF_CONTROL && DM_MMC_OPS
>>
>> I don't see a call to mmc_bind() anywhere. I'm not sure how this
>> driver actually works without that?
> 
> We use the mmc_create() API.

I get a more precise look at this API, and OK the driver must be updated 
using mmc_bind().

I will submit a v4 with this update.

Thanks for pointing this

Patrice

> 
> Patrice
> 
>>
>>> +   help
>>> + This selects support for the SD/MMC controller on STM32H7 SoCs.
>>> + If you have a board based on such a SoC and with a SD/MMC slot,
>>> + say Y or M here.
>>> +
>>>endif
>>
>> Regards,
>> Simon
>>
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[U-Boot] [PATCH] Convert CONFIG_SPL_OMAP3_ID_NAND to Kconfig

[Adam Ford]

This converts the following to Kconfig:
   CONFIG_SPL_OMAP3_ID_NAND

Signed-off-by: Adam Ford 
---
 README| 4 
 arch/arm/mach-omap2/Kconfig   | 1 +
 arch/arm/mach-omap2/omap3/Kconfig | 6 ++
 include/configs/cm_t35.h  | 1 -
 include/configs/omap3_beagle.h| 1 -
 include/configs/omap3_cairo.h | 1 -
 include/configs/omap3_evm.h   | 1 -
 include/configs/omap3_igep00x0.h  | 1 -
 include/configs/omap3_logic.h | 2 --
 include/configs/tao3530.h | 1 -
 scripts/config_whitelist.txt  | 1 -
 11 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/README b/README
index 3735916..22294bf 100644
--- a/README
+++ b/README
@@ -3028,10 +3028,6 @@ FIT uImage format:
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
 
-   CONFIG_SPL_OMAP3_ID_NAND
-   Support for an OMAP3-specific set of functions to return the
-   ID and MFR of the first attached NAND chip, if present.
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 89c91d1..533261c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -20,6 +20,7 @@ config OMAP34XX
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_SUPPORT
+   imply SPL_OMAP3_ID_NAND
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SYS_I2C_OMAP24XX
diff --git a/arch/arm/mach-omap2/omap3/Kconfig 
b/arch/arm/mach-omap2/omap3/Kconfig
index 7b298d6..b90cade 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -149,6 +149,12 @@ config TARGET_SNIPER
 
 endchoice
 
+config SPL_OMAP3_ID_NAND
+   bool "Support OMAP3-specific ID and MFR function"
+   help
+ Support for an OMAP3-specific set of functions to return the
+ ID and MFR of the first attached NAND chip, if present.
+
 config SYS_SOC
default "omap3"
 
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index f8f3c92..31c8389 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -260,7 +260,6 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_OMAP3_ID_NAND
 #define CONFIG_SPL_LDSCRIPT"arch/arm/mach-omap2/u-boot-spl.lds"
 
 /* NAND boot config */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index a87a75e..16951bd 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -258,7 +258,6 @@
 #define CONFIG_OMAP3_SPI
 
 /* Defines for SPL */
-#define CONFIG_SPL_OMAP3_ID_NAND
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 4f8ce54..30eaf50 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -183,7 +183,6 @@
 #define CONFIG_OMAP3_SPI
 
 /* Defines for SPL */
-#define CONFIG_SPL_OMAP3_ID_NAND
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index bc859c8..234cfe8 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -305,7 +305,6 @@
 #define CONFIG_SPL_BSS_START_ADDR  0x8000
 #define CONFIG_SPL_BSS_MAX_SIZE0x8 /* 512 KB */
 
-#define CONFIG_SPL_OMAP3_ID_NAND
 #define CONFIG_SPL_LDSCRIPT"arch/arm/mach-omap2/u-boot-spl.lds"
 
 /*
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 39f1e54..5ad354f 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -97,7 +97,6 @@
 #define CONFIG_SYS_ONENAND_BLOCK_SIZE  (128*1024)
 
 /* NAND config */
-#define CONFIG_SPL_OMAP3_ID_NAND
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT 64
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index e5ffb85..8a26536 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -259,8 +259,6 @@
 
 /* Defines for SPL */
 
-#define CONFIG_SPL_OMAP3_ID_NAND
-
 /* NAND: SPL falcon mode configs */
 #ifdef CONFIG_SPL_OS_BOOT
 #define CONFIG_CMD_SPL_NAND_OFS0x24
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 1f36ac6..4da0c4b 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -241,7 +241,6 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_OMAP3_ID_NAND
 #define CONFIG_SPL_LDSCRIPT"arch/arm/mach-omap2/u-boot-spl.lds"
 
 /* NAND boot config */
diff --git a/scripts/config_whitelist.txt 

[U-Boot] rerun eth_initialize()

[Matzi Kratzi]

Hi!
I have a board with an FPGA and my eth:s are connected through the FPGA.
I can load the FPGA before u-boot is started, but I would prefer not to.

Instead I would like to load the FPGA from u-boot instead.
Then I however get the problem that u-boot already has tried to initialize
eth.

Can I somehow run eth_initialize once more? Or delay it?

Kind Regards
Matzi
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[U-Boot] [PATCH] Convert CONFIG_NAND_OMAP_GPMC et al to Kconfig

[Adam Ford]

This converts the following to Kconfig:
   CONFIG_NAND_OMAP_GPMC
   CONFIG_NAND_OMAP_GPMC_PREFETCH
   CONFIG_NAND_OMAP_ELM
   CONFIG_SYS_NAND_BUSWIDTH_16BIT
   CONFIG_SPL_NAND_AM33XX_BCH
   CONFIG_SPL_NAND_SIMPLE

Signed-off-by: Adam Ford 
---
 README |  4 ---
 arch/arm/mach-omap2/Kconfig| 18 +
 configs/am335x_baltos_defconfig|  2 +-
 configs/am335x_evm_defconfig   |  1 +
 configs/am335x_evm_nor_defconfig   |  1 +
 configs/am335x_evm_usbspl_defconfig|  1 +
 configs/am335x_hs_evm_defconfig|  1 +
 configs/am3517_crane_defconfig |  1 +
 configs/am3517_evm_defconfig   |  2 ++
 configs/chiliboard_defconfig   |  2 +-
 configs/devkit8000_defconfig   |  1 +
 configs/eco5pk_defconfig   |  2 ++
 configs/igep0020_defconfig |  1 +
 configs/igep0030_defconfig |  1 +
 configs/igep0032_defconfig |  1 +
 configs/ipam390_defconfig  |  1 +
 configs/mcx_defconfig  |  2 ++
 configs/mt_ventoux_defconfig   |  2 ++
 configs/omap3_beagle_defconfig |  1 +
 configs/omap3_evm_defconfig|  1 +
 configs/omap3_ha_defconfig |  1 +
 configs/omap3_logic_defconfig  |  1 +
 configs/omap3_overo_defconfig  |  1 +
 configs/omap3_pandora_defconfig|  1 +
 configs/omap3_zoom1_defconfig  |  1 +
 configs/omapl138_lcdk_defconfig|  1 +
 configs/tao3530_defconfig  |  1 +
 configs/ti816x_evm_defconfig   |  2 ++
 configs/twister_defconfig  |  2 ++
 drivers/mtd/nand/Kconfig   | 47 +-
 include/configs/am335x_evm.h   |  6 -
 include/configs/am335x_igep003x.h  |  1 -
 include/configs/am3517_crane.h |  3 ---
 include/configs/am3517_evm.h   |  4 ---
 include/configs/am43xx_evm.h   |  5 
 include/configs/apf27.h|  1 -
 include/configs/baltos.h   |  3 ---
 include/configs/bav335x.h  |  5 
 include/configs/brppt1.h   |  3 ---
 include/configs/chiliboard.h   |  6 -
 include/configs/cm_t35.h   |  2 --
 include/configs/cm_t3517.h |  1 -
 include/configs/cm_t43.h   |  1 -
 include/configs/da850evm.h |  1 -
 include/configs/devkit3250.h   |  1 -
 include/configs/devkit8000.h   |  1 -
 include/configs/dra7xx_evm.h   |  6 -
 include/configs/ipam390.h  |  1 -
 include/configs/mcx.h  |  4 ---
 include/configs/omap3_beagle.h |  2 --
 include/configs/omap3_cairo.h  |  1 -
 include/configs/omap3_evm.h|  3 ---
 include/configs/omap3_igep00x0.h   |  2 --
 include/configs/omap3_logic.h  |  3 ---
 include/configs/omap3_overo.h  |  1 -
 include/configs/omap3_pandora.h|  1 -
 include/configs/omap3_zoom1.h  |  1 -
 include/configs/omapl138_lcdk.h|  2 --
 include/configs/pengwyn.h  |  2 --
 include/configs/siemens-am33x-common.h |  3 ---
 include/configs/tam3517-common.h   |  4 ---
 include/configs/tao3530.h  |  3 ---
 include/configs/tegra-common.h |  1 -
 include/configs/ti816x_evm.h   |  5 
 include/configs/ti_am335x_common.h |  4 ---
 include/configs/ti_armv7_omap.h|  1 -
 include/configs/ti_omap3_common.h  |  1 -
 include/configs/ti_omap4_common.h  |  4 ---
 include/configs/ti_omap5_common.h  |  4 ---
 include/configs/tricorder.h|  2 --
 scripts/config_whitelist.txt   |  5 
 71 files changed, 97 insertions(+), 117 deletions(-)

diff --git a/README b/README
index 3735916..dbbca43 100644
--- a/README
+++ b/README
@@ -2985,10 +2985,6 @@ FIT uImage format:
CONFIG_SPL_NAND_ECC
Include standard software ECC in the SPL
 
-   CONFIG_SPL_NAND_SIMPLE
-   Support for NAND boot using simple NAND drivers that
-   expose the cmd_ctrl() interface.
-
CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and
loader
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 89c91d1..eb3124f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -11,6 +11,7 @@ config OMAP34XX
select ARM_ERRATA_621766
select ARM_ERRATA_725233
select USE_TINY_PRINTF
+   imply NAND_OMAP_GPMC
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
imply SPL_GPIO_SUPPORT
@@ -19,6 +20,7 @@ config OMAP34XX
imply SPL_LIBDISK_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
+   imply SPL_NAND_SIMPLE
imply SPL_NAND_SUPPORT
imply SPL_POWER_SUPPORT
imply SPL_SERIAL_SUPPORT
@@ -29,6 +31,8 @@ config OMAP34XX
 config 

Re: [U-Boot] [linux-sunxi] [PATCHv6 00/28] Retrieve MAC address from EEPROM

[Vincent Legoll]

Hello,

> * Renamed sunxi_[eg]mac to sun[47]_mac to be more clear and allowing preparing
>   to merge common parts into sunxi_common

Wouldn't those better renamed to sun[47]i_mac instead, for consistency ?

-- 
Vincent Legoll
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Re: [U-Boot] [PATCH v3 1/2] usb: net: Add support for Microchip LAN75xx and LAN78xx

[Yuiko.Oshino]

>-Original Message-
>From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
>Sent: Thursday, August 10, 2017 5:12 PM
>To: Yuiko Oshino - C18177
>Cc: Marek Vasut; u-boot
>Subject: Re: [U-Boot] [PATCH v3 1/2] usb: net: Add support for Microchip
>LAN75xx and LAN78xx
>
>On Thu, Aug 10, 2017 at 2:32 PM,   wrote:
>>>-Original Message-
>>>From: Joe Hershberger [mailto:joe.hershber...@ni.com]
>>>Sent: Thursday, August 10, 2017 2:45 PM
>>>To: Yuiko Oshino - C18177
>>>Cc: Marek Vasut; u-boot; Joe Hershberger
>>>Subject: Re: [U-Boot] [PATCH v3 1/2] usb: net: Add support for
>>>Microchip LAN75xx and LAN78xx
>>>
>>>On Thu, Aug 10, 2017 at 1:13 PM,   wrote:
 Hi Marek,

>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Wednesday, August 9, 2017 1:12 PM
>To: Yuiko Oshino - C18177; u-boot@lists.denx.de
>Cc: Joe Hershberger
>Subject: Re: [PATCH v3 1/2] usb: net: Add support for Microchip
>LAN75xx and LAN78xx
>
>On 08/09/2017 06:25 PM, yuiko.osh...@microchip.com wrote:
>> From: Yuiko Oshino 
>>
>> Series-Changes: 3
>
>FYI, this will end in the commit message when applied, remove it or
>move it below the --- . Also commit message is missing.

 I did my best to follow the patman instructions and I added
 "commit-notes:" tag,
>>>but I guess it wasn't good enough.
>>>
>>>You need to not use commit notes here. That's for things that you want
>>>to be a note in the email, but not end up in the commit log.
>>
>> Understood. So what is the "commit message" that Marek meant that I missed?
>
>This:
>Add support for Microchip LAN7500, LAN7800 and LAN7850, USB to
>10/100/1000 Ethernet Controllers.
>
>>
>>>
 Should I always manually edit the patch before sending email in the patman?
>>>
>>>No, you shouldn't have to. The reason this failed to be removed is
>>>that you capitalized the 'C' in changes, and it didn't see it.
>>
>> I see...
>>
>>>
>>>Also, these tags are parsed and included as notes. You don't want to
>>>put these in a commit notes tag. That's only needed for other random commit
>notes.
>>>
>> What are "threse"?
>
>The tags I was referring to the Series-*: tags. It seemed like you were putting
>those tags into the Commit-notes: since that's there they should ultimately end
>up, but I'm saying that it happens for you.
>There should not be any nested tags.

Series-*: tags were placed after Commit-notes: and END, so I did not think it 
was nested.
In any case, I can delete the Commit-notes: and just add the non-tagged commit 
message.
And I fixed the C to c and they look much better.
Thank you so much.

>
 Also, when I am ready to update this patch again, should I do a
 series or just this
>>>patch?
>>>
>>>Do the series. Also, you should have the dependency patch first, and
>>>the dependent patch second (swap them around).
>>>
 How can I update the [PATCH v] number? If just his patch, then will
 it be [PATCH
>>>v4]?
>>>
>>>Go ahead and use v4. So use:
>>>
>>>Series-version: 4
>>>
>>
>> Got it.
>>
>
>>- All #ifdef CONFIG_DM_ETH and #endif are removed.
>>- The lan7x_eth_recv() is modifed to correctly support the Driver 
>> Model
>>  and returns packet_en.
>>- Add mii_resolve_flowctrl_fdx() patch in the series.
>>
>> Series-Changes: 2
>>- The wait_for_bit functions copy the real one.
>>- Uses phylib
>>- Unnecessary variables are removed
>>- All return values are checked
>>- Uses mii_resolve_flowctrl_fdx() from linux/mii.h
>>
>> Signed-off-by: Yuiko Oshino 
>> ---
>> Add support for Microchip LAN7500, LAN7800 and LAN7850, USB to
>> 10/100/1000 Ethernet Controllers.
>>>
>>>The fact that this is in the notes means that you put it under 
>>>"Commit-notes:" ...
>>>"END"
>>>
>> Yes, I did. Is the Commit-notes: == Commit message?
>
>That's not correct. Commit-notes: is for the random other notes that you want
>not to be in git.
>
>Just like not using patman, the standard un-tagged text is the Commit message.
>
>> Do I still need this tag?
>
>No, unless you have something to say in the notes beyond the change comments.
>
>> Following tags are all I need?
>> Series-to: u-boot
>> Series-version: 4
>> Series-changes: 4
>> Series-changes: 3
>> Series-changes: 2
>> Series-changes: 1
>
>Presumably there is no change for the initial version.

That's right...!

>
>> Signed-off-by: Yuiko Oshino 
>>
>> Should I add Acked-by:?
>
>Yes, you should add any Acked-by that you got on a previous version to the
>commit so it is already included in all following versions.
>
>>
>>
>>  drivers/usb/Kconfig   |   2 +
>>  drivers/usb/eth/Kconfig   |  17 ++
>>  drivers/usb/eth/Makefile  |   2 +
>>  drivers/usb/eth/lan75xx.c 

Re: [U-Boot] [PATCH v1 0/2] Add support for the A64-uQ7 modules

[Jagan Teki]

On Tue, Feb 21, 2017 at 5:17 AM, Philipp Tomsich
 wrote:
> This changeset adds support for the A64-uQ7 modules from Theobroma
> Systems, which is based on Allwinner's A64 (sun50iw1p1).
>
> It depends on the device-model support for the sunxi subarchitecture
> and the DM-based, dual-IO capable SPI driver which we submitted over
> the last couple of days.
>
> Given that these other patches are unmerged, this will (at this stage)
> mainly serve as a reference point to better point these other
> patchsets into perspective.
>
>
> Philipp Tomsich (2):
>   dts: lynx: add sun50i-a64-lynx.dts for the A64-uQ7
>   lynx_defconfig: add defconfig for A64-uQ7 module
>
>  arch/arm/dts/Makefile|   1 +
>  arch/arm/dts/sun50i-a64-lynx.dts | 247 
> +++

Need to wait till Linux upstream accept this new dts and resend the series.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH 2/2] Convert CONFIG_SYS_I2C_BUS_MAX to Kconfig

[Adam Ford]

This converts the following to Kconfig:
   CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford 
---
 arch/arm/include/asm/arch-am33xx/i2c.h |  1 -
 arch/arm/include/asm/arch-omap3/i2c.h  |  1 -
 arch/arm/include/asm/arch-omap4/i2c.h  |  1 -
 arch/arm/include/asm/arch-omap5/i2c.h  |  1 -
 drivers/i2c/Kconfig| 10 ++
 include/configs/socfpga_common.h   |  1 -
 include/configs/ti_armv7_keystone2.h   |  1 -
 7 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h 
b/arch/arm/include/asm/arch-am33xx/i2c.h
index a34282a..16e9a99 100644
--- a/arch/arm/include/asm/arch-am33xx/i2c.h
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -10,7 +10,6 @@
 #define  I2C_BASE1 0x44E0B000
 #define  I2C_BASE2 0x4802A000
 #define  I2C_BASE3 0x4819C000
-#define CONFIG_SYS_I2C_BUS_MAX 3
 
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h 
b/arch/arm/include/asm/arch-omap3/i2c.h
index d142175..48676dd 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP3_I2C_H_
 #define _OMAP3_I2C_H_
 
-#define CONFIG_SYS_I2C_BUS_MAX 3
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h 
b/arch/arm/include/asm/arch-omap4/i2c.h
index 1c5ed9b..96c0954 100644
--- a/arch/arm/include/asm/arch-omap4/i2c.h
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP4_I2C_H_
 #define _OMAP4_I2C_H_
 
-#define CONFIG_SYS_I2C_BUS_MAX 4
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h 
b/arch/arm/include/asm/arch-omap5/i2c.h
index 5122cd6..6d620dc 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -7,7 +7,6 @@
 #ifndef _OMAP5_I2C_H_
 #define _OMAP5_I2C_H_
 
-#define CONFIG_SYS_I2C_BUS_MAX 5
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 720e82d..f4fd843 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -207,6 +207,16 @@ config TEGRA186_BPMP_I2C
  by the BPMP, and can only be accessed by the main CPU via IPC
  requests to the BPMP. This driver covers the latter case.
 
+config SYS_I2C_BUS_MAX
+   int "Max I2C busses"
+   depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
+   default 2 if TI816X
+   default 3 if OMAP34XX || AM33XX || ARCH_KEYSTONE
+   default 4 if ARCH_SOCFPGA || OMAP44XX || AM44XX || AM43XX ||TI814X
+   default 5 if OMAP54XX
+   help
+ Define the maximum number of available I2C buses.
+
 source "drivers/i2c/muxes/Kconfig"
 
 endmenu
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 175b01e..73a9744 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -156,7 +156,6 @@
  * I2C support
  */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BUS_MAX 4
 #define CONFIG_SYS_I2C_BASESOCFPGA_I2C0_ADDRESS
 #define CONFIG_SYS_I2C_BASE1   SOCFPGA_I2C1_ADDRESS
 #define CONFIG_SYS_I2C_BASE2   SOCFPGA_I2C2_ADDRESS
diff --git a/include/configs/ti_armv7_keystone2.h 
b/include/configs/ti_armv7_keystone2.h
index 812ba51..6831b2c 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -160,7 +160,6 @@
 #define CONFIG_SYS_DAVINCI_I2C_SLAVE1  0x10 /* SMBus host address */
 #define CONFIG_SYS_DAVINCI_I2C_SPEED2  10
 #define CONFIG_SYS_DAVINCI_I2C_SLAVE2  0x10 /* SMBus host address */
-#define CONFIG_SYS_I2C_BUS_MAX 3
 
 /* EEPROM definitions */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-- 
2.7.4

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[U-Boot] [PATCH 1/2] Configs: Migrate I2C_BUS_MAX to CONFIG_SYS_I2C_BUS_MAX

[Adam Ford]

For consistency with other platforms and in preparation of Kconfig
migration, let's change Several TI platforms that use I2C_BUS_MAX
to CONFIG_SYS_I2C_BUS_MAX

Signed-off-by: Adam Ford 
---
 arch/arm/include/asm/arch-am33xx/i2c.h |  2 +-
 arch/arm/include/asm/arch-omap3/i2c.h  |  2 +-
 arch/arm/include/asm/arch-omap4/i2c.h  |  2 +-
 arch/arm/include/asm/arch-omap5/i2c.h  |  2 +-
 drivers/i2c/davinci_i2c.c  |  8 
 drivers/i2c/omap24xx_i2c.c | 12 ++--
 include/configs/ti_armv7_keystone2.h   |  2 +-
 scripts/config_whitelist.txt   |  2 +-
 8 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h 
b/arch/arm/include/asm/arch-am33xx/i2c.h
index 8642c8f..a34282a 100644
--- a/arch/arm/include/asm/arch-am33xx/i2c.h
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -10,7 +10,7 @@
 #define  I2C_BASE1 0x44E0B000
 #define  I2C_BASE2 0x4802A000
 #define  I2C_BASE3 0x4819C000
-#define I2C_BUS_MAX3
+#define CONFIG_SYS_I2C_BUS_MAX 3
 
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h 
b/arch/arm/include/asm/arch-omap3/i2c.h
index 6b3a3da..d142175 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -7,7 +7,7 @@
 #ifndef _OMAP3_I2C_H_
 #define _OMAP3_I2C_H_
 
-#define I2C_BUS_MAX3
+#define CONFIG_SYS_I2C_BUS_MAX 3
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h 
b/arch/arm/include/asm/arch-omap4/i2c.h
index 463e979..1c5ed9b 100644
--- a/arch/arm/include/asm/arch-omap4/i2c.h
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -7,7 +7,7 @@
 #ifndef _OMAP4_I2C_H_
 #define _OMAP4_I2C_H_
 
-#define I2C_BUS_MAX4
+#define CONFIG_SYS_I2C_BUS_MAX 4
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h 
b/arch/arm/include/asm/arch-omap5/i2c.h
index 2b55edf..5122cd6 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -7,7 +7,7 @@
 #ifndef _OMAP5_I2C_H_
 #define _OMAP5_I2C_H_
 
-#define I2C_BUS_MAX5
+#define CONFIG_SYS_I2C_BUS_MAX 5
 #define I2C_DEFAULT_BASE   I2C_BASE1
 
 struct i2c {
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index 2df07bb..a35ec46 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -343,11 +343,11 @@ static int _davinci_i2c_probe_chip(struct i2c_regs 
*i2c_base, uint8_t chip)
 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
 {
switch (adap->hwadapnr) {
-#if I2C_BUS_MAX >= 3
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
case 2:
return (struct i2c_regs *)I2C2_BASE;
 #endif
-#if I2C_BUS_MAX >= 2
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
case 1:
return (struct i2c_regs *)I2C1_BASE;
 #endif
@@ -412,7 +412,7 @@ U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, 
davinci_i2c_probe_chip,
 CONFIG_SYS_DAVINCI_I2C_SLAVE,
 0)
 
-#if I2C_BUS_MAX >= 2
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
 davinci_i2c_read, davinci_i2c_write,
 davinci_i2c_setspeed,
@@ -421,7 +421,7 @@ U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, 
davinci_i2c_probe_chip,
 1)
 #endif
 
-#if I2C_BUS_MAX >= 3
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
 davinci_i2c_read, davinci_i2c_write,
 davinci_i2c_setspeed,
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index f71e0a5..c98c627 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -706,15 +706,15 @@ static struct i2c *omap24_get_base(struct i2c_adapter 
*adap)
case 1:
return (struct i2c *)I2C_BASE2;
break;
-#if (I2C_BUS_MAX > 2)
+#if (CONFIG_SYS_I2C_BUS_MAX > 2)
case 2:
return (struct i2c *)I2C_BASE3;
break;
-#if (I2C_BUS_MAX > 3)
+#if (CONFIG_SYS_I2C_BUS_MAX > 3)
case 3:
return (struct i2c *)I2C_BASE4;
break;
-#if (I2C_BUS_MAX > 4)
+#if (CONFIG_SYS_I2C_BUS_MAX > 4)
case 4:
return (struct i2c *)I2C_BASE5;
break;
@@ -795,7 +795,7 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, 
omap24_i2c_probe,
 CONFIG_SYS_OMAP24_I2C_SPEED1,
 CONFIG_SYS_OMAP24_I2C_SLAVE1,
 1)
-#if (I2C_BUS_MAX > 2)
+#if (CONFIG_SYS_I2C_BUS_MAX > 2)
 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
 #endif
@@ -808,7 +808,7 @@ 

Re: [U-Boot] [PATCHv6 00/28] Retrieve MAC address from EEPROM

[Jagan Teki]

On Mon, May 15, 2017 at 6:17 PM, Tom Rini  wrote:
> On Mon, May 15, 2017 at 10:09:02AM +0200, Olliver Schinagl wrote:
>> Hey all,
>>
>> On 15-05-17 10:02, Olliver Schinagl wrote:
>> >This patch-series introduces methods to retrieve the MAC address from an
>> >onboard EEPROM. The series does a few small cleanups at the start, as either
>> >I ran into them while doing this series and fixed them along the way or
>> >actually depended on them.
>> >
>> >A manufacturer wants to produce boards and may even have MAC addresses for
>> >boards. Maintaining unique environments on a per-board basis however is
>> >horrible. Also this data should be very persistent, and not easily deletable
>> >by simply wiping the environment or device tree. Finally there are
>> >chips available on the market with a pre-programmed MAC address chips
>> >(proms)
>> >that a board manufacturer wants to use. Because of this, the MAC needs to be
>> >stored be able to read from such an 'external' source.
>> >
>> >The current idea of the eeprom layout, is to skip the first 8 bytes, so that
>> >other information can be stored there if needed, for example a header
>> >with some magic to identify the EEPROM. Or equivalent purposes.
>> >
>> >After those 8 bytes the MAC address follows the first macaddress. The
>> >macaddress is appended by a CRC8 byte and then padded to make for nice 8 
>> >bytes.
>> >Following the first macaddress one can store a second, or a third etc etc
>> >macaddress.
>> >
>> >The CRC8 is optional (via a define) but is strongly recommended to have. It
>> >helps preventing user error and more importantly, checks if the bytes
>> >read are actually a user inserted address. E.g. only writing 1 macaddress 
>> >into
>> >the eeprom but trying to consume 2.
>> >
>> >These patches where tested on Olimex OLinuXino Lime1 (A10/A20), Lime2 (NAND
>> >and eMMC) and A20-OLinuXino-MICRO-4G variants and have been in use
>> >internally on our production systems since v2 of this patch set.
>> >
>> >TODO in a follow up series:
>> >* Replace the I2C specific read function to a generic function using
>> >Maxime Ripard's EEPROM uclass once merged.
>> >* Upgrade to use the EERPOM layout functionality as suggested by Igor 
>> >Grinberg
>> >* Add EEPROM/Mac commands suggested by York Sun
>> >
>> >The series was initially based ontop of Joe's u-boot_net/next branches, but 
>> >I
>> >rebased it ontop of u-boot/master to get the latest sunxi changes, 
>> >including:
>> >sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC
>> >ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc
>> >
>> >Which are on their way to being merged in master. So once those land into 
>> >master
>> >this all should apply cleanly. Sorry Joe!
>>
>> So I accidentally added those too to this patch series as well
>> (first two patches). Which are technically not part of this series
>> and are on their way as it is. Does patchwork figure out this
>> automatically, or do you prefer a resend with the 2 patches removed?
>
> I've made patchwork reflect things correctly.

Few of the patches need re-work, so updated patchwork status as
"Changes Requested" for the series.

thanks!
-- 
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Hyderabad, India.
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Re: [U-Boot] [PATCH v4 00/26] sunxi: Allwinner A64: SPL support

[Jagan Teki]

On Wed, Jan 4, 2017 at 9:20 PM, Jagan Teki  wrote:
> On Mon, Jan 2, 2017 at 12:48 PM, Andre Przywara  
> wrote:
>> Hi,
>>
>> hopefully the final version of the SPL support series for the Allwinner A64
>> SoC. Actually no real code changes this time, just rebased on top of recent
>> master, adding some comments in patches 16/26 and 19/26 following Maxime's
>> suggestions and adding Acked-by:s and Reviewed-by:s.
>> I left the final patch 26/26 in for the sake of completeness, but don't 
>> expect
>> it to be merged. We need a clever solution to unify 32-bit and 64-bit board
>> configurations, but that shouldn't hold back this series for now.
>> Merging everything until and including patch 21/26 (sunxi: A64: enable SPL)
>> would be great, the other patches until 25/26 can go in as well, I think.
>>
>> -
>> As the previous versions this one includes support for both AArch64 and
>> AArch32 SPL builds. The FIT support is still missing, which means the
>> functionality is limited. Due to the missing ARM Trusted Firmware (ATF)
>> in this firmware chain we lose Ethernet and SMP, among other minor things.
>> A full 64-bit build can be written to an SD card as expected and will
>> boot the U-Boot proper prompt. However Linux will crash on boot, as
>> PSCI is missing.
>> Building the 32-bit version of the SPL and combining this with an ATF
>> build and the 64-bit U-Boot proper allows to use FEL booting now:
>> # sunxi-fel spl sunxi-spl.bin write 0x4a00 u-boot-dtb.bin \
>>   write 0x44000 bl31.bin reset64 0x44000
>> This way of booting the board gives full functionality.
>>
>> The first patch is a rather simple fix (with no changes to v2).
>> Patches 2-8 prepare the SPL code to be compiled for 64-bit in general and
>> AArch64 in particular.
>> Patches 9-11 refactor the existing boot0 header functionality to be used
>> by patch 12, which introduces the 64-bit switch in the first SPL
>> instructions.
>> Patches 13-20 then introduce the actual core of the SPL support: the DRAM
>> initialization, courtesy of Jens. This piggy backs on the existing
>> H3 DRAM code, deviating where needed. This has been reworked compared to
>> v2: I added a patch from Philipp to replace the rather uninspired
>> register writes in the MBUS priority setup function with some meaningful
>> code, explaining the various bits. Also the actual A64 DRAM code is no
>> longer #ifdef'ed into the H3 driver, but uses parameters to (static)
>> functions. The compiler detects this and removes the dead code from
>> the other variant, resulting in the same binary size for the H3.
>>
>> Patch 21 finally enables the 64-bit SPL support. So now building the
>> existing pine64_plus_defconfig will generate a sunxi-spl.bin, which
>> can be prepended to the U-Boot proper image (not .bin) to boot from
>> an SD card. Due to the missing ATF support this is of limited usability
>> at the moment, though. Also FEL support requires more love - to switch
>> back to AArch32 before returning to FEL (without crashing, that is ;-),
>> so this is disabled.
>> On my setup this results in a 26KB SPL binary, which is close to the
>> 28K limit mksunxiboot imposes at the moment. Adding anything (like
>> FIT support or DEBUG) will exceed this, and although I have patches
>> to let mksunxiboot get close to 32KB, this is the ulimate frontier.
>>
>> So patches 22-25 then teach the SPL how to detect an U-Boot image file
>> of a different bitness and do the RMR switch from AArch32 to AArch64,
>> if needed.
>> This is used by the final patch 26, which creates another _defconfig
>> to let the SPL compile for AArch32 using the Thumb2 encoding. This
>> results in a binary of less than 17KB in my case, so has plenty of
>> room for extensions.
>>
>> Cheers,
>> Andre.
>>
>> Changelog v3 .. v4:
>> - rebased on top of latest HEAD
>> - add various Reviewed-by: and Acked-by: tags
>> - add comments about register bit meanings in non-ODT-setting fix
>> - clarify meaning of delay values in single bit delay support patch
>> - removing stray semicolons from boot0.h header
>>
>> Changelog v2 .. v3:
>> - add various Reviewed-by: and Acked-by: tags
>> - split tiny-printf fix to handle "-" separately
>> - add various comments and extend commit messages
>> - add assembly file to re-create the embedded RMR switch code
>> - add patch 14/26 to explain the MBUS priority setup
>> - move DRAM r/w delay values into #defines to simplify re-usablity
>> - replace #ifdef'ed addition of A64 support to the H3 DRAM driver with an
>>   approach using static parameters
>>
>> Changelog v1 .. v2:
>> - drop SPI build fix (already merged)
>> - confine A31 register init change to H3 and A64
>> - use IS_ENABLED() instead of #idef to guard MBUS2 clock init
>> - fix tiny-printf (proper sign extension for 32-bit integers)
>> - add "size" output in commit msg to document tiny-printf size impact
>> - fix sdelay(): use only one register, add "cc" clobber
>> - update RMR switch 

Re: [U-Boot] [PATCH] sunxi: gpio: add missing compatible strings

[Jagan Teki]

On Thu, Jun 29, 2017 at 3:56 PM, Icenowy Zheng  wrote:
>
>
> 于 2017年6月29日 GMT+08:00 下午6:10:31, Andre Przywara  写到:
>>The sunxi GPIO driver is missing some compatible strings for recent
>>SoCs. While most of the sunxi GPIO code seems to not rely on this (and
>>so works anyway), the sunxi_name_to_gpio() function does and fails at
>>the moment (for instance when resolving the MMC CD pin name).
>>Add the compatible strings for the A64, H5 and V3s, which were missing
>>from the list. This now covers all pinctrl nodes in our own DTs.
>>Strictly speaking the V3s has only ports B, C, E, F and G, but I think
>>the other SoCs have gaps in there as well and for the pin number
>
> Yes, the current U-Boot driver doesn't care gaps at all, and I remember
> A64 has also no A bank.

then better have this change only when it required to do so.

thanks!
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Re: [U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

[Jagan Teki]

On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta  wrote:
> In some of the QSPI controller version, there must be atleast
> 128bit data available in TX FIFO for any pop operation otherwise
> error bit will be set. The code will not make any behavior change
> for previous controller as the transfer data size in ipcr register
> is still the same.
>
> Patch is tested on LS1046A which do not require 16 bytes aligned and
> LS1088A which require 16 bytes aligned data in TX FIFO
>
> Signed-off-by: Suresh Gupta 
> Signed-off-by: Anupam Kumar 

Can some one Tested and verified the result?

thanks!
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Re: [U-Boot] Please pull u-boot-fsl-qoriq master

[Tom Rini]

On Fri, Aug 11, 2017 at 02:35:24AM +, York Sun wrote:

> On 08/10/2017 07:18 PM, Tom Rini wrote:
> > On Thu, Aug 10, 2017 at 03:34:49PM +, York Sun wrote:
> > 
> >> Tom,
> >>
> >> The following changes since commit 
> >> eaa90e5df2a4a1cb12fb73571978a9379242d0b5:
> >>
> >> common/env_embedded.c: rename PPCENV/PPCTEXT macros (2017-08-04
> >> 20:38:39 -0400)
> >>
> >> are available in the git repository at:
> >>
> >> git://git.denx.de/u-boot-fsl-qoriq.git
> >>
> >> for you to fetch changes up to 1c83df6f3f95055ed1c8fb40d1d0604863eab78b:
> >>
> >> armv8: ls2080a: Increase env sector size for qspi boot (2017-08-09
> >> 09:57:33 -0700)
> >>
> > 
> > This seems to lead to a number of PowerPC boards failing, can you please
> > throw this at travis-ci and fix the fallout?  See
> > https://travis-ci.org/trini/u-boot/builds/263245350, thanks!
> > 
> 
> I made sure the compiling was OK before request a pull. See 
> https://travis-ci.org/yorksun/u-boot/builds/262844095.
> 
> Your travis build is still on-going. I will check a little bit later.

I had re-started some of the failing jobs on the off-chance it was
something else going wrong.  I'm re-trying just the QorIQ PR right now,
thanks!

-- 
Tom


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Re: [U-Boot] [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

[Jagan Teki]

On Fri, Aug 11, 2017 at 3:38 PM, Yogesh Narayan Gaur
 wrote:
>
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Friday, August 11, 2017 3:32 PM
>> To: Yogesh Narayan Gaur 
>> Cc: u-boot@lists.denx.de; York Sun 
>> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
>>
>> On Fri, Aug 11, 2017 at 3:30 PM, Yogesh Narayan Gaur
>>  wrote:
>> >
>> >
>> >> -Original Message-
>> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> >> Sent: Friday, August 11, 2017 3:25 PM
>> >> To: Yogesh Narayan Gaur 
>> >> Cc: u-boot@lists.denx.de; York Sun 
>> >> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
>> >>
>> >> On Tue, Aug 1, 2017 at 9:43 AM, Yogesh Gaur
>> >> 
>> >> wrote:
>> >> > Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
>> >> > Since the manufactory ID is changed to 0x2C, add it for micron and
>> >> > using it for relevant settings.
>> >> >
>> >> > The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't
>> >> > support dual and quad. Supports subsector erase with 4KB
>> >> > granularity, have support of FSR(flag status register) and flash size 
>> >> > is 64MB.
>> >> > ---
>> >> >  drivers/mtd/spi/sf_internal.h   | 1 +
>> >> >  drivers/mtd/spi/spi_flash.c | 2 ++
>> >> >  drivers/mtd/spi/spi_flash_ids.c | 1 +
>> >> >  3 files changed, 4 insertions(+)
>> >> >
>> >> > diff --git a/drivers/mtd/spi/sf_internal.h
>> >> > b/drivers/mtd/spi/sf_internal.h index 839cdbe..f46cb3a 100644
>> >> > --- a/drivers/mtd/spi/sf_internal.h
>> >> > +++ b/drivers/mtd/spi/sf_internal.h
>> >> > @@ -33,6 +33,7 @@ enum spi_nor_option_flags {
>> >> >  /* CFI Manufacture ID's */
>> >> >  #define SPI_FLASH_CFI_MFR_SPANSION 0x01
>> >> >  #define SPI_FLASH_CFI_MFR_STMICRO  0x20
>> >> > +#define SPI_FLASH_CFI_MFR_MICRON   0x2C
>> >>
>> >> Does this new mfr id from micro? so 0x20 still exists?
>> >>
>> > On older Micron flash like MT25QU512ABB mfr id still is 0x20 but in newer
>> flash, MT35X, it's been changed to 0x2c.
>>
>> OK, so the flash features like quad ennoblements, opcodes remains same?
>> except the mfr?
>>
> This flash support single bit and octal bit cmds no dual or quad support.
> Opcode for read/write/erase and other register operation related cmds are 
> similar to already supported flashes like MT25QU512ABB(n25q512a in existing 
> table).
> Only mfr id has been modified.

OK.

And better remove the new CONFIG_ macro since the both chips have
equal functionalities and anyway changes should managed by id table.
the chip you defined under STMICRO ifdef :)

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] sunxi: add MACPWR in Orange Pi PC2 defconfig

[Jagan Teki]

On Fri, Aug 11, 2017 at 3:30 PM, Jagan Teki  wrote:
> On Tue, Jul 4, 2017 at 4:13 PM, Icenowy Zheng  wrote:
>> The Ethernet function is enabled in the Orange Pi PC2 device tree and
>> defconfig, however, CONFIG_MACPWR is not properly set, which left the
>> PHY being disabled when booting, which makes the Ethernet function not
>> usable.
>>
>> Add the proper value of this option in the PC2 defconfig.
>>
>> Fixes: e7bd15ea156f ("sunxi: Add OrangePi PC 2 initial support")
>> Signed-off-by: Icenowy Zheng 
>
> Reviewed-by: Jagan Teki 

Applied to u-boot-sunxi/master

thanks!
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Re: [U-Boot] [PATCH] sunxi: reduce Orange Pi Zero DRAM clock speed

[Jagan Teki]

On Mon, Jul 24, 2017 at 1:44 AM, Clément Bœsch  wrote:
> Using `fel-boot-lima-memtester-on-orange-pi-pc 672` on an Orange Pi
> without heatsink results in the following error after a few minutes:
>   WRITE FAILURE: 0x0020 != 0xffdf at offset 0x0137f47c (bitflip).
>
> Also, the constructor repository (github/orangepi-xunlong) seems to
> contain that 624 Mhz clock speed in its u-boot fork. It may be that 672
> Mhz is the advertized overclocked speed.
>
> According to http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit
> it may be worth decreasing that value with other Orange Pi boards.
>
> See also e7d6aa0b74b7f4d08ee68da8a586c76c761348e2.

Applied to u-boot-sunxi/master

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH 1/2] sunxi: add PRCM secure switch register definition

[Jagan Teki]

On Thu, Jul 20, 2017 at 11:30 AM, Icenowy Zheng  wrote:
> Some new Allwinner SoCs' PRCM has a secure switch register, which
> controls the access to some clock and power registers in PRCM block.
>
> Add the definition of this register and its bits in the PRCM header
> file.
>
> Signed-off-by: Icenowy Zheng 

Applied both in u-boot-sunxi/master

thanks!
-- 
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U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v3 1/3] efi_loader: write protocol GUID in OpenProtocol

[Alexander Graf]

On 05.08.17 21:32, Heinrich Schuchardt wrote:

To understand what happens in OpenProtocol it is necessary to know
the protocol interface GUID. Let's write a debug message.

Using uuid_guid_get_str would be quite clumsy for this purpose.
This would involve evaluating _DEBUG which probably should not be used
outside common.h.

Cc: Rob Clark 
Signed-off-by: Heinrich Schuchardt 


I agree with Rob that a printf extension would be the nicest way to go 
here. We could then just use that instead of the %p in EFI_ENTRY() that 
we have today.



Alex
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Re: [U-Boot] [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

[Yogesh Narayan Gaur]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Friday, August 11, 2017 3:32 PM
> To: Yogesh Narayan Gaur 
> Cc: u-boot@lists.denx.de; York Sun 
> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
> 
> On Fri, Aug 11, 2017 at 3:30 PM, Yogesh Narayan Gaur
>  wrote:
> >
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> >> Sent: Friday, August 11, 2017 3:25 PM
> >> To: Yogesh Narayan Gaur 
> >> Cc: u-boot@lists.denx.de; York Sun 
> >> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
> >>
> >> On Tue, Aug 1, 2017 at 9:43 AM, Yogesh Gaur
> >> 
> >> wrote:
> >> > Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
> >> > Since the manufactory ID is changed to 0x2C, add it for micron and
> >> > using it for relevant settings.
> >> >
> >> > The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't
> >> > support dual and quad. Supports subsector erase with 4KB
> >> > granularity, have support of FSR(flag status register) and flash size is 
> >> > 64MB.
> >> > ---
> >> >  drivers/mtd/spi/sf_internal.h   | 1 +
> >> >  drivers/mtd/spi/spi_flash.c | 2 ++
> >> >  drivers/mtd/spi/spi_flash_ids.c | 1 +
> >> >  3 files changed, 4 insertions(+)
> >> >
> >> > diff --git a/drivers/mtd/spi/sf_internal.h
> >> > b/drivers/mtd/spi/sf_internal.h index 839cdbe..f46cb3a 100644
> >> > --- a/drivers/mtd/spi/sf_internal.h
> >> > +++ b/drivers/mtd/spi/sf_internal.h
> >> > @@ -33,6 +33,7 @@ enum spi_nor_option_flags {
> >> >  /* CFI Manufacture ID's */
> >> >  #define SPI_FLASH_CFI_MFR_SPANSION 0x01
> >> >  #define SPI_FLASH_CFI_MFR_STMICRO  0x20
> >> > +#define SPI_FLASH_CFI_MFR_MICRON   0x2C
> >>
> >> Does this new mfr id from micro? so 0x20 still exists?
> >>
> > On older Micron flash like MT25QU512ABB mfr id still is 0x20 but in newer
> flash, MT35X, it's been changed to 0x2c.
> 
> OK, so the flash features like quad ennoblements, opcodes remains same?
> except the mfr?
> 
This flash support single bit and octal bit cmds no dual or quad support.
Opcode for read/write/erase and other register operation related cmds are 
similar to already supported flashes like MT25QU512ABB(n25q512a in existing 
table).
Only mfr id has been modified.

--
Regards
Yogesh Gaur.

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

[Jagan Teki]

On Fri, Aug 11, 2017 at 3:30 PM, Yogesh Narayan Gaur
 wrote:
>
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Friday, August 11, 2017 3:25 PM
>> To: Yogesh Narayan Gaur 
>> Cc: u-boot@lists.denx.de; York Sun 
>> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
>>
>> On Tue, Aug 1, 2017 at 9:43 AM, Yogesh Gaur 
>> wrote:
>> > Add MT35XU512ABA1G12 parameters to NOR flash parameters array. Since
>> > the manufactory ID is changed to 0x2C, add it for micron and using it
>> > for relevant settings.
>> >
>> > The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't
>> > support dual and quad. Supports subsector erase with 4KB granularity,
>> > have support of FSR(flag status register) and flash size is 64MB.
>> > ---
>> >  drivers/mtd/spi/sf_internal.h   | 1 +
>> >  drivers/mtd/spi/spi_flash.c | 2 ++
>> >  drivers/mtd/spi/spi_flash_ids.c | 1 +
>> >  3 files changed, 4 insertions(+)
>> >
>> > diff --git a/drivers/mtd/spi/sf_internal.h
>> > b/drivers/mtd/spi/sf_internal.h index 839cdbe..f46cb3a 100644
>> > --- a/drivers/mtd/spi/sf_internal.h
>> > +++ b/drivers/mtd/spi/sf_internal.h
>> > @@ -33,6 +33,7 @@ enum spi_nor_option_flags {
>> >  /* CFI Manufacture ID's */
>> >  #define SPI_FLASH_CFI_MFR_SPANSION 0x01
>> >  #define SPI_FLASH_CFI_MFR_STMICRO  0x20
>> > +#define SPI_FLASH_CFI_MFR_MICRON   0x2C
>>
>> Does this new mfr id from micro? so 0x20 still exists?
>>
> On older Micron flash like MT25QU512ABB mfr id still is 0x20 but in newer 
> flash, MT35X, it's been changed to 0x2c.

OK, so the flash features like quad ennoblements, opcodes remains
same? except the mfr?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

[Yogesh Narayan Gaur]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Friday, August 11, 2017 3:25 PM
> To: Yogesh Narayan Gaur 
> Cc: u-boot@lists.denx.de; York Sun 
> Subject: Re: [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support
> 
> On Tue, Aug 1, 2017 at 9:43 AM, Yogesh Gaur 
> wrote:
> > Add MT35XU512ABA1G12 parameters to NOR flash parameters array. Since
> > the manufactory ID is changed to 0x2C, add it for micron and using it
> > for relevant settings.
> >
> > The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't
> > support dual and quad. Supports subsector erase with 4KB granularity,
> > have support of FSR(flag status register) and flash size is 64MB.
> > ---
> >  drivers/mtd/spi/sf_internal.h   | 1 +
> >  drivers/mtd/spi/spi_flash.c | 2 ++
> >  drivers/mtd/spi/spi_flash_ids.c | 1 +
> >  3 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/mtd/spi/sf_internal.h
> > b/drivers/mtd/spi/sf_internal.h index 839cdbe..f46cb3a 100644
> > --- a/drivers/mtd/spi/sf_internal.h
> > +++ b/drivers/mtd/spi/sf_internal.h
> > @@ -33,6 +33,7 @@ enum spi_nor_option_flags {
> >  /* CFI Manufacture ID's */
> >  #define SPI_FLASH_CFI_MFR_SPANSION 0x01
> >  #define SPI_FLASH_CFI_MFR_STMICRO  0x20
> > +#define SPI_FLASH_CFI_MFR_MICRON   0x2C
> 
> Does this new mfr id from micro? so 0x20 still exists?
> 
On older Micron flash like MT25QU512ABB mfr id still is 0x20 but in newer 
flash, MT35X, it's been changed to 0x2c.

--
Regards
Yogesh Gaur.

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] sunxi: add MACPWR in Orange Pi PC2 defconfig

[Jagan Teki]

On Tue, Jul 4, 2017 at 4:13 PM, Icenowy Zheng  wrote:
> The Ethernet function is enabled in the Orange Pi PC2 device tree and
> defconfig, however, CONFIG_MACPWR is not properly set, which left the
> PHY being disabled when booting, which makes the Ethernet function not
> usable.
>
> Add the proper value of this option in the PC2 defconfig.
>
> Fixes: e7bd15ea156f ("sunxi: Add OrangePi PC 2 initial support")
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Jagan Teki 

thanks!
-- 
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Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
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[U-Boot] [RFC/WIP 2/2] fs/fat: introduce new dirent iterator

[Rob Clark]

Untangle the directory traversal.  Eventually if this replaced
do_fat_read_at() and get_dentfromdir(), it would remove a lot of code.

Only tested with a grand total of one fat fs img.  Although it actually
seems to fix some bugs with existing traversal (I noticed some files in
the root directory that where not showing up with "ls").

I don't particularly want to convert read/ls/etc over to using this
myself, since I don't really have enough example fat filesystems to
test with, and I can't even get all of the fs-test.sh tests running
properly.  But something along the lines of this is what I think a
sane fat.c (and probably fat_write.c?) should be using.

This opens up the possibility for a faster stateful readdir (ie.
fs_opendir()/fs_readdir()/fs_closedir(), which didn't have to re-
traverse the directory structure at each fs_readdir() step.  I'm
not sure if it would be weird for readdir() to be stateful, while
the rest of u-boot's fs APIs are not.
---
 fs/fat/fat.c | 274 +++
 1 file changed, 274 insertions(+)

diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 68db36ebd7..2709147eaa 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1298,6 +1298,273 @@ exit:
return ret;
 }
 
+///
+
+/*
+ * Directory iterator, to simplify filesystem traversal
+ */
+
+typedef struct {
+   // TODO maybe it would simplify things if fat_itr was malloc'd and
+   // had ptr to it's parent?  if various fat_* API's re-used this it
+   // would perhaps give a way to have a common helper to find the
+   // parent directory iterator and then fat_itr_free() when done..
+   fsdata*fsdata;
+   unsigned   cursect;
+   dir_entry *dent;
+   intremaining; /* remaining dent's in current cluster */
+   intlast_cluster;
+   intis_root;
+
+   /* current iterator position values: */
+   char   l_name[VFAT_MAXLEN_BYTES];
+   char   s_name[14];
+   char  *name;  /* l_name if there is one, else s_name */
+
+   u8 block[MAX_CLUSTSIZE] __aligned(ARCH_DMA_MINALIGN);
+} fat_itr;
+
+static int fat_itr_isdir(fat_itr *itr);
+
+/* root directory iterator */
+static int fat_itr_root(fat_itr *itr, fsdata *fsdata)
+{
+   if (get_fs_info(fsdata))
+   return -1;
+
+   itr->fsdata = fsdata;
+   itr->cursect = fsdata->rootdir_sect;
+   itr->dent = NULL;
+   itr->remaining = 0;
+   itr->last_cluster = 0;
+   itr->is_root = 1;
+
+   return 0;
+}
+
+/* sub-directory iterator */
+static void fat_itr_child(fat_itr *itr, fat_itr *parent)
+{
+   fsdata *mydata = parent->fsdata;  // TODO ugg, get rid of stupid 
assumption of mydata in macros..
+   unsigned clustnum = START(parent->dent);
+
+   assert(fat_itr_isdir(parent));
+
+   itr->fsdata = parent->fsdata;
+   if (clustnum > 0) {
+   itr->cursect = itr->fsdata->data_begin +
+   (clustnum * itr->fsdata->clust_size);
+   } else {
+   itr->cursect = 0;
+   }
+   itr->dent = NULL;
+   itr->remaining = 0;
+   itr->last_cluster = 0;
+   itr->is_root = 0;
+}
+
+static void *next_cluster(fat_itr *itr)
+{
+   fsdata *mydata = itr->fsdata;  // TODO ugg, get rid of stupid 
assumption of mydata in macros..
+   int ret;
+
+   /* have we reached the end? */
+   if (itr->last_cluster)
+   return NULL;
+
+   debug("FAT read(sect=%d), clust_size=%d, DIRENTSPERBLOCK=%zd\n",
+ itr->cursect, itr->fsdata->clust_size, DIRENTSPERBLOCK);
+
+   /* NOTE: do_fat_read_at() had complicated logic to deal w/
+* vfat names that span multiple clusters in the fat16 case,
+* which get_dentfromdir() probably also needed (and was
+* missing).  And not entirely sure what fat32 didn't have
+* the same issue..  We solve that by only caring about one
+* dent at a time and iteratively constructing the vfat long
+* name.
+*/
+   ret = disk_read(itr->cursect, itr->fsdata->clust_size,
+   itr->block);
+   if (ret < 0) {
+   debug("Error: reading block\n");
+   return NULL;
+   }
+
+   // TODO maybe ((fatsize == 32) || !is_root) are same case?
+   if (itr->is_root) {
+   if (itr->fsdata->fatsize == 32) {
+   itr->cursect = get_fatent(itr->fsdata, itr->cursect);
+   if (CHECK_CLUST(itr->cursect, itr->fsdata->fatsize)) {
+   debug("cursect: 0x%x\n", itr->cursect);
+   itr->last_cluster = 1;
+   }
+   } else {
+   itr->cursect++;
+   if (itr->cursect - itr->fsdata->rootdir_sect >=
+   itr->fsdata->rootdir_size) {
+  

[U-Boot] [RFC/WIP 1/2] fs/fat: split out helper to init fsdata

[Rob Clark]

Want to re-use this in fat dirent iterator in next patch.
---
 fs/fat/fat.c  | 75 +++
 include/fat.h |  1 +
 2 files changed, 45 insertions(+), 31 deletions(-)

diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 3d5dde0d9e..68db36ebd7 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -831,36 +831,17 @@ exit:
return ret;
 }
 
-__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
-   __aligned(ARCH_DMA_MINALIGN);
-
-int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
-  loff_t maxsize, int dols, int dogetsize, loff_t *size)
+static int get_fs_info(fsdata *mydata)
 {
-   char fnamecopy[2048];
boot_sector bs;
volume_info volinfo;
-   fsdata datablock;
-   fsdata *mydata = 
-   dir_entry *dentptr = NULL;
-   __u16 prevcksum = 0x;
-   char *subname = "";
-   __u32 cursect;
-   int idx, isdir = 0;
-   int files = 0, dirs = 0;
-   int ret = (dols == LS_READDIR) ? -ENOTDIR : -1;
-   int firsttime;
__u32 root_cluster = 0;
-   __u32 read_blk;
-   int rootdir_size = 0;
-   int buffer_blk_cnt;
-   int do_read;
-   int readdir = (dols == LS_READDIR);
-   __u8 *dir_ptr;
+   int ret;
 
-   if (read_bootsectandvi(, , >fatsize)) {
+   ret = read_bootsectandvi(, , >fatsize);
+   if (ret) {
debug("Error: reading boot sector\n");
-   return -1;
+   return ret;
}
 
if (mydata->fatsize == 32) {
@@ -872,8 +853,7 @@ int do_fat_read_at(const char *filename, loff_t pos, void 
*buffer,
 
mydata->fat_sect = bs.reserved;
 
-   cursect = mydata->rootdir_sect
-   = mydata->fat_sect + mydata->fatlength * bs.fats;
+   mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats;
 
mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
mydata->clust_size = bs.cluster_size;
@@ -887,12 +867,12 @@ int do_fat_read_at(const char *filename, loff_t pos, void 
*buffer,
mydata->data_begin = mydata->rootdir_sect -
(mydata->clust_size * 2);
} else {
-   rootdir_size = ((bs.dir_entries[1]  * (int)256 +
-bs.dir_entries[0]) *
-sizeof(dir_entry)) /
-mydata->sect_size;
+   mydata->rootdir_size = ((bs.dir_entries[1]  * (int)256 +
+bs.dir_entries[0]) *
+sizeof(dir_entry)) /
+mydata->sect_size;
mydata->data_begin = mydata->rootdir_sect +
-   rootdir_size -
+   mydata->rootdir_size -
(mydata->clust_size * 2);
}
 
@@ -917,6 +897,39 @@ int do_fat_read_at(const char *filename, loff_t pos, void 
*buffer,
debug("Sector size: %d, cluster size: %d\n", mydata->sect_size,
  mydata->clust_size);
 
+   return 0;
+}
+
+__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
+   __aligned(ARCH_DMA_MINALIGN);
+
+int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
+  loff_t maxsize, int dols, int dogetsize, loff_t *size)
+{
+   char fnamecopy[2048];
+   fsdata datablock;
+   fsdata *mydata = 
+   dir_entry *dentptr = NULL;
+   __u16 prevcksum = 0x;
+   char *subname = "";
+   __u32 cursect;
+   int idx, isdir = 0;
+   int files = 0, dirs = 0;
+   int ret = (dols == LS_READDIR) ? -ENOTDIR : -1;
+   int firsttime;
+   __u32 root_cluster = 0;
+   __u32 read_blk;
+   int rootdir_size = 0;
+   int buffer_blk_cnt;
+   int do_read;
+   int readdir = (dols == LS_READDIR);
+   __u8 *dir_ptr;
+
+   if (get_fs_info(mydata))
+   return -1;
+
+   cursect = mydata->rootdir_sect;
+
/* "cwd" is always the root... */
while (ISDIRDELIM(*filename))
filename++;
diff --git a/include/fat.h b/include/fat.h
index 0ef3f5be16..4f5103a8b4 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -174,6 +174,7 @@ typedef struct {
__u16   clust_size; /* Size of clusters in sectors */
int data_begin; /* The sector of the first cluster, can be 
negative */
int fatbufnum;  /* Used by get_fatent, init to -1 */
+   int rootdir_size;
 } fsdata;
 
 typedef int(file_detectfs_func)(void);
-- 
2.13.0

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Re: [U-Boot] [PATCH 00/15] Add STM32H7 SoC and STM32H743-Disco board support

[Patrice CHOTARD]

Hi all

After some internal review, this series must be reworked.
A v2 will be submitted

Thanks

Patrice

On 08/04/2017 03:18 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard 
> 
> This series adds support for STM32H7 SoCs series and its Discovery board
> 
> For more detailed information about STM32H7 SoCs family please visit:
> www.st.com/en/microcontrollers/stm32h7-series.html
> 
> The STM32H743-discovery board offers:
>_ 2MBytes Flash
>_ 1 x micro USB OTG port
>_ 1 x STLink connector (micro USB)
>_ 1 x micro SD card slot
>_ 1 x RJ45 connector
>_ 1 x RCA connector
>_ 2 x Audio jack connectors (in and out)
>_ 2 x speaker connectors (left and right)
>_ 1 x joystick
>_ 1 x DCMI connector (Digital camera interface)
>_ 1 x 4 inch DSI LCD (Display Serial Interface)
>_ Arduino Uno Connectors
>_ 2 x PIO connectors (PMOD and PMOD+)
>_ 1 x wakeup button
>_ 1 x reset button
> 
> Christophe Kerello (1):
>dm: misc: add stm32 rcc driver
> 
> Patrice Chotard (14):
>pinctrl: stm32: add stm32h743-pinctrl compatible
>serial: stm32x7: add STM32H7 support
>dm: clk: add clk driver support for stm32h7 SoCs
>dm: reset: add stm32 reset driver
>ARM: DTS: stm32: add stm32h743i-disco files
>ARM: DTS: stm32: Enable Clock driver for stm32h743
>ARM: DTS: stm32: update usart compatible string for stm32h743
>ARM: DTS: stm32: add gpio compatible and aliases for stm32h743
>ARM: DTS: stm32: add sdram config for stm32h743i-disco
>ARM: DTS: stm32: add HSI and CSI fixed clock for stm32H743
>ARM: DTS: stm32: add u-boot,dm-pre-reloc for stm32h743i-disco
>ARM: DTS: stm32: set HSE clock to 25Mhz for stm32h743i-disco
>ARM: DTS: stm32: add "simple-bus" compatible for clocks node
>board: Add stm32h7 SoC and stm32h743-disco board support
> 
>   arch/arm/dts/Makefile |1 +
>   arch/arm/dts/stm32h743-pinctrl.dtsi   |  261 
>   arch/arm/dts/stm32h743.dtsi   |  142 ++
>   arch/arm/dts/stm32h743i-disco.dts |   96 ++
>   arch/arm/include/asm/arch-stm32h7/gpio.h  |  126 ++
>   arch/arm/include/asm/arch-stm32h7/rcc.h   |  304 
>   arch/arm/include/asm/arch-stm32h7/stm32.h |   21 +
>   arch/arm/mach-stm32/Kconfig   |4 +
>   arch/arm/mach-stm32/Makefile  |1 +
>   arch/arm/mach-stm32/stm32h7/Kconfig   |8 +
>   arch/arm/mach-stm32/stm32h7/Makefile  |8 +
>   arch/arm/mach-stm32/stm32h7/soc.c |   59 +
>   board/st/stm32h743-disco/Kconfig  |   19 +
>   board/st/stm32h743-disco/MAINTAINERS  |7 +
>   board/st/stm32h743-disco/Makefile |8 +
>   board/st/stm32h743-disco/stm32h743-disco.c|   80 +
>   configs/stm32h743-disco_defconfig |   42 +
>   doc/device-tree-bindings/clock/st,stm32h7-rcc.txt |  152 ++
>   doc/device-tree-bindings/reset/st,stm32-rcc.txt   |6 +
>   drivers/clk/Makefile  |1 +
>   drivers/clk/clk_stm32h7.c |  468 ++
>   drivers/misc/Kconfig  |9 +
>   drivers/misc/Makefile |1 +
>   drivers/misc/stm32_rcc.c  |   45 +
>   drivers/pinctrl/pinctrl_stm32.c   |1 +
>   drivers/reset/Kconfig |7 +
>   drivers/reset/Makefile|1 +
>   drivers/reset/stm32-reset.c   |   80 +
>   drivers/serial/Kconfig|7 +-
>   drivers/serial/serial_stm32x7.c   |2 +
>   include/configs/stm32h743-disco.h |   55 +
>   include/dt-bindings/clock/stm32h7-clks.h  |  165 +++
>   include/dt-bindings/memory/stm32-sdram.h  |7 +
>   include/dt-bindings/mfd/stm32h7-rcc.h |  138 ++
>   include/dt-bindings/pinctrl/stm32h7-pinfunc.h | 1612 
> +
>   35 files changed, 3941 insertions(+), 3 deletions(-)
>   create mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi
>   create mode 100644 arch/arm/dts/stm32h743.dtsi
>   create mode 100644 arch/arm/dts/stm32h743i-disco.dts
>   create mode 100644 arch/arm/include/asm/arch-stm32h7/gpio.h
>   create mode 100644 arch/arm/include/asm/arch-stm32h7/rcc.h
>   create mode 100644 arch/arm/include/asm/arch-stm32h7/stm32.h
>   create mode 100644 arch/arm/mach-stm32/stm32h7/Kconfig
>   create mode 100644 arch/arm/mach-stm32/stm32h7/Makefile
>   create mode 100644 arch/arm/mach-stm32/stm32h7/soc.c
>   create mode 100644 board/st/stm32h743-disco/Kconfig
>   create mode 100644 board/st/stm32h743-disco/MAINTAINERS
>   create mode 100644 board/st/stm32h743-disco/Makefile
>   create mode 100644 board/st/stm32h743-disco/stm32h743-disco.c
>   create mode 100644 

Re: [U-Boot] [PATCH] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

[Jagan Teki]

On Tue, Aug 1, 2017 at 9:43 AM, Yogesh Gaur  wrote:
> Add MT35XU512ABA1G12 parameters to NOR flash parameters array. Since the
> manufactory ID is changed to 0x2C, add it for micron and using it for
> relevant settings.
>
> The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
> dual and quad. Supports subsector erase with 4KB granularity, have support
> of FSR(flag status register) and flash size is 64MB.
> ---
>  drivers/mtd/spi/sf_internal.h   | 1 +
>  drivers/mtd/spi/spi_flash.c | 2 ++
>  drivers/mtd/spi/spi_flash_ids.c | 1 +
>  3 files changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index 839cdbe..f46cb3a 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -33,6 +33,7 @@ enum spi_nor_option_flags {
>  /* CFI Manufacture ID's */
>  #define SPI_FLASH_CFI_MFR_SPANSION 0x01
>  #define SPI_FLASH_CFI_MFR_STMICRO  0x20
> +#define SPI_FLASH_CFI_MFR_MICRON   0x2C

Does this new mfr id from micro? so 0x20 still exists?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [RFC] efi_loader: Add test to boot OpenBSD's efi bootloader

[Alexander Graf]

On 06.08.17 17:10, Rob Clark wrote:

Signed-off-by: Rob Clark 
---
Kinda works, but since we don't have an 'exit' command like grub, we
have to reboot, which leaves the "board" in a bad state (I guess,
since the next test fails).  I haven't tackled the travis bits to get
travis to download OpenBSD's bootloader, or other little details like
that.


I think it's a very good addition to the tests - we should definitely 
try and test the OpenBSD bootloader as well.


Adding the travis bits to download it should be a matter of wget'ing it 
into the right directory.


As for the reboot - I think you only have to get yourself back to a boot 
prompt and check for that. That's basically what ensure_spawned() does too.



Alex



So suggestions welcome ;-)

  test/py/tests/test_efi_loader.py | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 5d7f5dbfb2..376f6442a3 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -193,3 +193,22 @@ def test_efi_grub_net(u_boot_console):
  
  # And give us our U-Boot prompt back

  u_boot_console.run_command('')
+
+@pytest.mark.buildconfigspec('cmd_bootefi')
+def test_efi_openbsd_net(u_boot_console):
+"""Run OpenBSD's bootloader via TFTP.
+
+The bootaa64.efi file is downloaded from the TFTP server and
+gets executed.
+"""
+
+addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_openbsd_file')
+
+u_boot_console.run_command('bootefi %x' % addr, wait_for_prompt=False)
+
+# Check that bootloader loads properly:
+u_boot_console.wait_for('boot>')
+
+# There is no exit, but there is a reboot cmd.. maybe we need to do
+# more than this to get u-boot running again??
+u_boot_console.run_command('reboot', wait_for_prompt=False, 
wait_for_echo=False)


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Re: [U-Boot] [PATCH v4 1/4] dm: spi: add BCM63xx HSSPI driver

[Jagan Teki]

On Sun, Jul 30, 2017 at 5:44 PM, Álvaro Fernández Rojas
 wrote:
> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
>
> Signed-off-by: Álvaro Fernández Rojas 
> Reviewed-by: Simon Glass 
> Reviewed-by: Daniel Schwierzeck 
> ---
>  v4: no changes.
>  v3: Switch to CONFIG_BCM63XX_HSSPI and rebase on top of SPI v4.
>  v2: Introduce changes suggested by Simon Glass:
>   - Split bcm63xx_hsspi_xfer() into smaller functions.
>   - Check possible clock errors.
>   - Check possible reset errors.
>   - Switch to devfdt_get_addr_size_index().
>   - Use setbits32_be() for clock gate.
>
>  drivers/spi/Kconfig |   8 +
>  drivers/spi/Makefile|   1 +
>  drivers/spi/bcm63xx_hsspi.c | 413 
> 
>  3 files changed, 422 insertions(+)
>  create mode 100644 drivers/spi/bcm63xx_hsspi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 511643607b..97c3cb6103 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -40,6 +40,14 @@ config ATMEL_SPI
>   many AT91 (ARM) chips. This driver can be used to access
>   the SPI Flash, such as AT25DF321.
>
> +config BCM63XX_HSSPI
> +   bool "BCM63XX HSSPI driver"
> +   depends on ARCH_BMIPS
> +   help
> + Enable the BCM6328 HSSPI driver. This driver can be used to
> + access the SPI NOR flash on platforms embedding this Broadcom
> + SPI core.
> +
>  config BCM63XX_SPI
> bool "BCM6348 SPI driver"
> depends on ARCH_BMIPS
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index d9802dd8c3..fefafbe333 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>  obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> +obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
>  obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
>  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>  obj-$(CONFIG_CF_SPI) += cf_spi.o
> diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
> new file mode 100644
> index 00..538c4ec4fe
> --- /dev/null
> +++ b/drivers/spi/bcm63xx_hsspi.c
> @@ -0,0 +1,413 @@
> +/*
> + * Copyright (C) 2017 Álvaro Fernández Rojas 
> + *
> + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
> + * Copyright (C) 2000-2010 Broadcom Corporation
> + * Copyright (C) 2012-2013 Jonas Gorski 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define SPI_PP_SEL 0
> +
> +#define SPI_MAX_SYNC_CLOCK 3000
> +
> +/* SPI Control register */
> +#define SPI_CTL_REG0x000
> +#define SPI_CTL_CS_POL_SHIFT   0
> +#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT)
> +#define SPI_CTL_CLK_GATE_SHIFT 16
> +#define SPI_CTL_CLK_GATE_MASK  (1 << SPI_CTL_CLK_GATE_SHIFT)
> +#define SPI_CTL_CLK_POL_SHIFT  17
> +#define SPI_CTL_CLK_POL_MASK   (1 << SPI_CTL_CLK_POL_SHIFT)
> +
> +/* SPI Interrupts registers */
> +#define SPI_IR_STAT_REG0x008
> +#define SPI_IR_ST_MASK_REG 0x00c
> +#define SPI_IR_MASK_REG0x010
> +
> +#define SPI_IR_CLEAR_ALL   0xff001f1f
> +
> +/* SPI Ping-Pong Command registers */
> +#define SPI_PP_CMD_REG (0x080 + (0x40 * (SPI_PP_SEL)) + 0x00)
> +#define SPI_PP_CMD_OP_SHIFT0
> +#define SPI_PP_CMD_OP_START(0x1 << SPI_PP_CMD_OP_SHIFT)
> +#define SPI_PP_CMD_PFL_SHIFT   8
> +#define SPI_PP_CMD_PFL_MASK(0x7 << SPI_PP_CMD_PFL_SHIFT)
> +#define SPI_PP_CMD_SLAVE_SHIFT 12
> +#define SPI_PP_CMD_SLAVE_MASK  (0x7 << SPI_PP_CMD_SLAVE_SHIFT)
> +
> +/* SPI Ping-Pong Status registers */
> +#define SPI_PP_STAT_REG(0x080 + (0x40 * 
> (SPI_PP_SEL)) + 0x04)
> +#define SPI_PP_STAT_SRCBUSY_SHIFT  1
> +#define SPI_PP_STAT_SRCBUSY_MASK   (1 << SPI_PP_STAT_SRCBUSY_SHIFT)
> +
> +/* SPI Profile Clock registers */
> +#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
> +#define SPI_PFL_CLK_FREQ_SHIFT 0
> +#define SPI_PFL_CLK_FREQ_MASK  (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
> +#define SPI_PFL_CLK_RSTLOOP_SHIFT  15
> +#define SPI_PFL_CLK_RSTLOOP_MASK   (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
> +
> +/* SPI Profile Signal registers */
> +#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
> +#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
> +#define SPI_PFL_SIG_LATCHRIS_MASK  (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
> +#define SPI_PFL_SIG_LAUNCHRIS_SHIFT13
> +#define 

Re: [U-Boot] [PATCH v5 03/10] dm: spi: add BCM63xx SPI driver

[Jagan Teki]

On Thu, Aug 10, 2017 at 2:55 PM, Jagan Teki  wrote:
> On Sun, Jul 30, 2017 at 5:43 PM, Álvaro Fernández Rojas
>  wrote:
>> This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
>>
>> Signed-off-by: Álvaro Fernández Rojas 
>> Reviewed-by: Simon Glass 
>> Reviewed-by: Daniel Schwierzeck 
>> ---
>>  v5: Introduce changes suggested by Jagan Teki:
>>   - Use long structure instead of a custom bmips_spi_hw structure.
>>   - Define constants for each SPI core.
>>  v4: Introduce changes suggested by Jagan Teki:
>>   - Add data for each HW controller instead of having two separate configs.
>>   - Also check clock and reset returns as suggested by Simon Glass for HSSPI.
>>  v3: rename BCM6338 SPI driver to BCM6348
>>   switch to devfdt_get_addr_size_index()
>>  v2: no changes
>>
>>  drivers/spi/Kconfig   |   8 +
>>  drivers/spi/Makefile  |   1 +
>>  drivers/spi/bcm63xx_spi.c | 434 
>> ++
>>  3 files changed, 443 insertions(+)
>>  create mode 100644 drivers/spi/bcm63xx_spi.c
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 8a8e8e480f..511643607b 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -40,6 +40,14 @@ config ATMEL_SPI
>>   many AT91 (ARM) chips. This driver can be used to access
>>   the SPI Flash, such as AT25DF321.
>>
>> +config BCM63XX_SPI
>> +   bool "BCM6348 SPI driver"
>> +   depends on ARCH_BMIPS
>> +   help
>> + Enable the BCM6348/BCM6358 SPI driver. This driver can be used to
>> + access the SPI NOR flash on platforms embedding these Broadcom
>> + SPI cores.
>> +
>>  config CADENCE_QSPI
>> bool "Cadence QSPI driver"
>> help
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 9f8b86de76..d9802dd8c3 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>>  obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>> +obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
>>  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
>>  obj-$(CONFIG_CF_SPI) += cf_spi.o
>>  obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
>> diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
>> new file mode 100644
>> index 00..904db2b7c7
>> --- /dev/null
>> +++ b/drivers/spi/bcm63xx_spi.c
>> @@ -0,0 +1,434 @@
>> +/*
>> + * Copyright (C) 2017 Álvaro Fernández Rojas 
>> + *
>> + * Derived from linux/drivers/spi/spi-bcm63xx.c:
>> + * Copyright (C) 2009-2012 Florian Fainelli 
>> + * Copyright (C) 2010 Tanguy Bouzeloc 
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/* BCM6348 SPI core */
>> +#define SPI_6348_CLK   0x06
>> +#define SPI_6348_CMD   0x00
>> +#define SPI_6348_CTL   0x40
>> +#define SPI_6348_CTL_SHIFT 6
>> +#define SPI_6348_FILL  0x07
>> +#define SPI_6348_IR_MASK   0x04
>> +#define SPI_6348_IR_STAT   0x02
>> +#define SPI_6348_RX0x80
>> +#define SPI_6348_RX_SIZE   0x3f
>> +#define SPI_6348_TX0x41
>> +#define SPI_6348_TX_SIZE   0x3f
>> +
>> +/* BCM6358 SPI core */
>> +#define SPI_6358_CLK   0x706
>> +#define SPI_6358_CMD   0x700
>> +#define SPI_6358_CTL   0x000
>> +#define SPI_6358_CTL_SHIFT 14
>> +#define SPI_6358_FILL  0x707
>> +#define SPI_6358_IR_MASK   0x702
>> +#define SPI_6358_IR_STAT   0x704
>> +#define SPI_6358_RX0x400
>> +#define SPI_6358_RX_SIZE   0x220
>> +#define SPI_6358_TX0x002
>> +#define SPI_6358_TX_SIZE   0x21e
>> +
>> +/* SPI Clock register */
>> +#define SPI_CLK_SHIFT  0
>> +#define SPI_CLK_20MHZ  (0 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_0_391MHZ   (1 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_0_781MHZ   (2 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_1_563MHZ   (3 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_3_125MHZ   (4 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_6_250MHZ   (5 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_12_50MHZ   (6 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_25MHZ  (7 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_MASK   (7 << SPI_CLK_SHIFT)
>> +#define SPI_CLK_SSOFF_SHIFT3
>> +#define SPI_CLK_SSOFF_2(2 << SPI_CLK_SSOFF_SHIFT)
>> +#define SPI_CLK_SSOFF_MASK (7 << SPI_CLK_SSOFF_SHIFT)
>> +#define SPI_CLK_BSWAP_SHIFT7
>> +#define 

[U-Boot] [PATCH] qe: ready QE IRAM after uploading firmware successfully

[Zhao Qiang]

add if condition to check the return value, if 0, firmware is uploaded
successfully, then mark QE_IRAM as ready.

Signed-off-by: Zhao Qiang 
---
 drivers/qe/qe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 24e764d..8151068 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -225,8 +225,8 @@ void u_qe_init(void)
flush_cache((ulong)addr, cnt * 512);
}
 #endif
-   u_qe_upload_firmware(addr);
-   out_be32(_immr->iram.iready, QE_IRAM_READY);
+   if (!u_qe_upload_firmware(addr))
+   out_be32(_immr->iram.iready, QE_IRAM_READY);
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
free(addr);
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 09/10] ut: fix fdt_getprop_u32() change

[Pantelis Antoniou]

fdt_getprop_u32 is not exported and it's different than what the
unit test uses. Rename u32 prop access methods to something that's
unit test specific.

Signed-off-by: Pantelis Antoniou 
---
 test/overlay/cmd_ut_overlay.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c
index cbef720..7106f42 100644
--- a/test/overlay/cmd_ut_overlay.c
+++ b/test/overlay/cmd_ut_overlay.c
@@ -21,7 +21,7 @@
 extern u32 __dtb_test_fdt_base_begin;
 extern u32 __dtb_test_fdt_overlay_begin;
 
-static int fdt_getprop_u32_by_index(void *fdt, const char *path,
+static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path,
const char *name, int index,
u32 *out)
 {
@@ -42,10 +42,10 @@ static int fdt_getprop_u32_by_index(void *fdt, const char 
*path,
return 0;
 }
 
-static int fdt_getprop_u32(void *fdt, const char *path, const char *name,
+static int ut_fdt_getprop_u32(void *fdt, const char *path, const char *name,
   u32 *out)
 {
-   return fdt_getprop_u32_by_index(fdt, path, name, 0, out);
+   return ut_fdt_getprop_u32_by_index(fdt, path, name, 0, out);
 }
 
 static int fdt_getprop_str(void *fdt, const char *path, const char *name,
@@ -68,7 +68,7 @@ static int fdt_overlay_change_int_property(struct 
unit_test_state *uts)
void *fdt = uts->priv;
u32 val = 0;
 
-   ut_assertok(fdt_getprop_u32(fdt, "/test-node", "test-int-property",
+   ut_assertok(ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property",
));
ut_asserteq(43, val);
 
@@ -158,11 +158,11 @@ static int fdt_overlay_local_phandle(struct 
unit_test_state *uts)
local_phandle = fdt_get_phandle(fdt, off);
ut_assert(local_phandle);
 
-   ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
+   ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", 
"test-several-phandle",
 0, ));
ut_asserteq(local_phandle, val);
 
-   ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
+   ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", 
"test-several-phandle",
 1, ));
ut_asserteq(local_phandle, val);
 
@@ -189,11 +189,11 @@ static int fdt_overlay_local_phandles(struct 
unit_test_state *uts)
test_phandle = fdt_get_phandle(fdt, off);
ut_assert(test_phandle);
 
-   ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0,
+   ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0,
 ));
ut_asserteq(test_phandle, val);
 
-   ut_assertok(fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1,
+   ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1,
 ));
ut_asserteq(local_phandle, val);
 
-- 
2.1.4

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[U-Boot] [PATCH v2 04/10] fdt-overlay: Spit out a descriptive failure warning

[Pantelis Antoniou]

The most common trouble with overlays appears to be miscompiled
blobs without the -@ option.

In case of an error, spit out a descriptive error message.

Signed-off-by: Pantelis Antoniou 
---
 cmd/fdt.c  |  8 
 common/image-fit.c | 12 +++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/cmd/fdt.c b/cmd/fdt.c
index 05e19f8..9f192be 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -654,6 +654,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
unsigned long addr;
struct fdt_header *blob;
int ret;
+   bool has_symbols;
 
if (argc != 3)
return CMD_RET_USAGE;
@@ -666,9 +667,16 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
if (!fdt_valid())
return CMD_RET_FAILURE;
 
+   ret = fdt_path_offset(working_fdt, "/__symbols__");
+   has_symbols = ret >= 0;
+
ret = fdt_overlay_apply(working_fdt, blob);
if (ret) {
printf("fdt_overlay_apply(): %s\n", fdt_strerror(ret));
+   if (!has_symbols) {
+   printf("working fdt does did not have a 
/__symbols__ node\n");
+   printf("make sure you've compiled with -@\n");
+   }
return CMD_RET_FAILURE;
}
}
diff --git a/common/image-fit.c b/common/image-fit.c
index cb089ea..28140f1 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1946,6 +1946,7 @@ int boot_get_fdt_fit(bootm_headers_t *images, ulong addr,
const char *uname;
void *base, *ov;
int i, err, noffset, ov_noffset;
+   bool has_symbols;
 #endif
 
fit_uname = fit_unamep ? *fit_unamep : NULL;
@@ -2038,9 +2039,18 @@ int boot_get_fdt_fit(bootm_headers_t *images, ulong addr,
fdt_noffset = err;
goto out;
}
+
+   err = fdt_path_offset(base, "/__symbols__");
+   has_symbols = err >= 0;
+
err = fdt_overlay_apply(base, ov);
if (err < 0) {
-   printf("failed on fdt_overlay_apply\n");
+   printf("failed on fdt_overlay_apply(): %s\n",
+   fdt_strerror(err));
+   if (!has_symbols) {
+   printf("base fdt does did not have a 
/__symbols__ node\n");
+   printf("make sure you've compiled with -@\n");
+   }
fdt_noffset = err;
goto out;
}
-- 
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[U-Boot] [PATCH v2 08/10] config: sandbox: Add unit tests

[Pantelis Antoniou]

Add unit tests for sandbox default config.

Signed-off-by: Pantelis Antoniou 
---
 configs/sandbox_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index fd0b952..df8659a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -187,7 +187,9 @@ CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y
 CONFIG_LZ4=y
 CONFIG_ERRNO_STR=y
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_UNIT_TEST=y
 CONFIG_UT_TIME=y
 CONFIG_UT_DM=y
 CONFIG_UT_ENV=y
+CONFIG_UT_OVERLAY=y
-- 
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[U-Boot] [PATCH v2 10/10] test: overlay: Add unit test for stacked overlay

[Pantelis Antoniou]

Verify that stacked overlays work.

Signed-off-by: Pantelis Antoniou 
---
 test/overlay/Makefile |  1 +
 test/overlay/cmd_ut_overlay.c | 34 ++-
 test/overlay/test-fdt-overlay-stacked.dts | 21 +++
 3 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 test/overlay/test-fdt-overlay-stacked.dts

diff --git a/test/overlay/Makefile b/test/overlay/Makefile
index 907f085..416645c 100644
--- a/test/overlay/Makefile
+++ b/test/overlay/Makefile
@@ -13,3 +13,4 @@ DTC_FLAGS += -@
 # DT overlays
 obj-y += test-fdt-base.dtb.o
 obj-y += test-fdt-overlay.dtb.o
+obj-y += test-fdt-overlay-stacked.dtb.o
diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c
index 7106f42..24891ee 100644
--- a/test/overlay/cmd_ut_overlay.c
+++ b/test/overlay/cmd_ut_overlay.c
@@ -20,6 +20,7 @@
 
 extern u32 __dtb_test_fdt_base_begin;
 extern u32 __dtb_test_fdt_overlay_begin;
+extern u32 __dtb_test_fdt_overlay_stacked_begin;
 
 static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path,
const char *name, int index,
@@ -201,6 +202,19 @@ static int fdt_overlay_local_phandles(struct 
unit_test_state *uts)
 }
 OVERLAY_TEST(fdt_overlay_local_phandles, 0);
 
+static int fdt_overlay_stacked(struct unit_test_state *uts)
+{
+   void *fdt = uts->priv;
+   u32 val = 0;
+
+   ut_assertok(ut_fdt_getprop_u32(fdt, "/new-local-node",
+  "stacked-test-int-property", ));
+   ut_asserteq(43, val);
+
+   return CMD_RET_SUCCESS;
+}
+OVERLAY_TEST(fdt_overlay_stacked, 0);
+
 int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
struct unit_test *tests = ll_entry_start(struct unit_test,
@@ -210,7 +224,8 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
struct unit_test *test;
void *fdt_base = &__dtb_test_fdt_base_begin;
void *fdt_overlay = &__dtb_test_fdt_overlay_begin;
-   void *fdt_base_copy, *fdt_overlay_copy;
+   void *fdt_overlay_stacked = &__dtb_test_fdt_overlay_stacked_begin;
+   void *fdt_base_copy, *fdt_overlay_copy, *fdt_overlay_stacked_copy;
 
uts = calloc(1, sizeof(*uts));
if (!uts)
@@ -228,6 +243,10 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
if (!fdt_overlay_copy)
return -ENOMEM;
 
+   fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
+   if (!fdt_overlay_stacked_copy)
+   return -ENOMEM;
+
/*
 * Resize the FDT to 4k so that we have room to operate on
 *
@@ -245,9 +264,21 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy,
  FDT_COPY_SIZE));
 
+   /*
+* Resize the stacked overlay to 4k so that we have room to operate on
+*
+* (and relocate it since the memory might be mapped
+* read-only)
+*/
+   ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy,
+ FDT_COPY_SIZE));
+
/* Apply the overlay */
ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_copy));
 
+   /* Apply the stacked overlay */
+   ut_assertok(fdt_overlay_apply(fdt_base_copy, fdt_overlay_stacked_copy));
+
if (argc == 1)
printf("Running %d environment tests\n", n_ents);
 
@@ -263,6 +294,7 @@ int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 
printf("Failures: %d\n", uts->fail_count);
 
+   free(fdt_overlay_stacked_copy);
free(fdt_overlay_copy);
free(fdt_base_copy);
free(uts);
diff --git a/test/overlay/test-fdt-overlay-stacked.dts 
b/test/overlay/test-fdt-overlay-stacked.dts
new file mode 100644
index 000..9fb7c7b
--- /dev/null
+++ b/test/overlay/test-fdt-overlay-stacked.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016 NextThing Co
+ * Copyright (c) 2016 Free Electrons
+ * Copyright (c) 2018 Konsulko Group
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+   /* Test that we can reference an overlay symbol */
+   fragment@0 {
+   target = <>;
+
+   __overlay__ {
+   stacked-test-int-property = <43>;
+   };
+   };
+};
-- 
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[U-Boot] [PATCH v2 07/10] dtbo: make dtbos special

[Pantelis Antoniou]

Special rule for dtbo generation

Signed-off-by: Pantelis Antoniou 
---
 scripts/Makefile.lib | 17 +
 1 file changed, 17 insertions(+)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 9ce47b4..2a7ed70 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -321,6 +321,23 @@ $(obj)/%.dtb: $(src)/%.dts FORCE
 
 dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
 
+# DTCO
+# ---
+
+quiet_cmd_dtco = DTCO$@
+# Rule for objects only; does not put specific u-boot include at the end
+# No generation of assembly file either
+# Modified for U-Boot
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
+   $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \
+   $(DTC) -@ -O dtb -o $@ -b 0 \
+   -i $(dir $<) $(DTC_FLAGS) \
+   -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+   cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtbo: $(src)/%.dts FORCE
+   $(call if_changed_dep,dtco)
+
 # Fonts
 # ---
 
-- 
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[U-Boot] [PATCH v2 03/10] fit: Introduce methods for applying overlays on fit-load

[Pantelis Antoniou]

Introduce an overlay based method for constructing a base DT blob
to pass to the kernel.

Both canned and runtime feature selection is supported.

Signed-off-by: Pantelis Antoniou 
---
 common/image-fdt.c   |   7 +-
 common/image-fit.c   | 216 --
 doc/uImage.FIT/command_syntax_extensions.txt |  12 +-
 doc/uImage.FIT/overlay-fdt-boot.txt  | 221 +++
 doc/uImage.FIT/source_file_format.txt|   6 +-
 include/image.h  |  10 ++
 6 files changed, 454 insertions(+), 18 deletions(-)
 create mode 100644 doc/uImage.FIT/overlay-fdt-boot.txt

diff --git a/common/image-fdt.c b/common/image-fdt.c
index c6e8832..a59134c 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -356,17 +356,16 @@ int boot_get_fdt(int flag, int argc, char * const argv[], 
uint8_t arch,
if (fit_check_format(buf)) {
ulong load, len;
 
-   fdt_noffset = fit_image_load(images,
+   fdt_noffset = boot_get_fdt_fit(images,
fdt_addr, _uname_fdt,
_uname_config,
-   arch, IH_TYPE_FLATDT,
-   BOOTSTAGE_ID_FIT_FDT_START,
-   FIT_LOAD_OPTIONAL, , );
+   arch, , );
 
images->fit_hdr_fdt = map_sysmem(fdt_addr, 0);
images->fit_uname_fdt = fit_uname_fdt;
images->fit_noffset_fdt = fdt_noffset;
fdt_addr = load;
+
break;
} else
 #endif
diff --git a/common/image-fit.c b/common/image-fit.c
index 109ecfa..cb089ea 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 DECLARE_GLOBAL_DATA_PTR;
 #endif /* !USE_HOSTCC*/
 
@@ -434,6 +435,10 @@ void fit_image_print(const void *fit, int image_noffset, 
const char *p)
printf("0x%08lx\n", load);
}
 
+   /* optional load address for FDT */
+   if (type == IH_TYPE_FLATDT && !fit_image_get_load(fit, image_noffset, 
))
+   printf("%s  Load Address: 0x%08lx\n", p, load);
+
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
(type == IH_TYPE_RAMDISK)) {
ret = fit_image_get_entry(fit, image_noffset, );
@@ -1454,6 +1459,8 @@ int fit_conf_get_node(const void *fit, const char 
*conf_uname)
 {
int noffset, confs_noffset;
int len;
+   const char *s;
+   char *conf_uname_copy = NULL;
 
confs_noffset = fdt_path_offset(fit, FIT_CONFS_PATH);
if (confs_noffset < 0) {
@@ -1475,29 +1482,58 @@ int fit_conf_get_node(const void *fit, const char 
*conf_uname)
debug("Found default configuration: '%s'\n", conf_uname);
}
 
+   s = strchr(conf_uname, '#');
+   if (s) {
+   len = s - conf_uname;
+   conf_uname_copy = malloc(len + 1);
+   if (!conf_uname_copy) {
+   debug("Can't allocate uname copy: '%s'\n",
+   conf_uname);
+   return -ENOMEM;
+   }
+   memcpy(conf_uname_copy, conf_uname, len);
+   conf_uname_copy[len] = '\0';
+   conf_uname = conf_uname_copy;
+   }
+
noffset = fdt_subnode_offset(fit, confs_noffset, conf_uname);
if (noffset < 0) {
debug("Can't get node offset for configuration unit name: '%s' 
(%s)\n",
  conf_uname, fdt_strerror(noffset));
}
 
+   if (conf_uname_copy)
+   free(conf_uname_copy);
+
return noffset;
 }
 
-int fit_conf_get_prop_node(const void *fit, int noffset,
+int fit_conf_get_prop_node_count(const void *fit, int noffset,
const char *prop_name)
 {
-   char *uname;
+   return fdt_stringlist_count(fit, noffset, prop_name);
+}
+
+int fit_conf_get_prop_node_index(const void *fit, int noffset,
+   const char *prop_name, int index)
+{
+   const char *uname;
int len;
 
/* get kernel image unit name from configuration kernel property */
-   uname = (char *)fdt_getprop(fit, noffset, prop_name, );
+   uname = fdt_stringlist_get(fit, noffset, prop_name, index, );
if (uname == NULL)
return len;
 
return fit_image_get_node(fit, uname);
 }
 
+int fit_conf_get_prop_node(const void *fit, int noffset,
+   const char *prop_name)
+{
+   return fit_conf_get_prop_node_index(fit, noffset, prop_name, 0);
+}
+
 /**
  * fit_conf_print - prints out the FIT configuration details
  

[U-Boot] [PATCH v2 05/10] doc: Document how to apply fdt overlays

[Pantelis Antoniou]

We have the capability to apply overlays on the command line but
we didn't have a document explaining how.

Signed-off-by: Pantelis Antoniou 
---
 doc/README.fdt-overlays | 37 +
 1 file changed, 37 insertions(+)
 create mode 100644 doc/README.fdt-overlays

diff --git a/doc/README.fdt-overlays b/doc/README.fdt-overlays
new file mode 100644
index 000..ee868ec
--- /dev/null
+++ b/doc/README.fdt-overlays
@@ -0,0 +1,37 @@
+U-Boot FDT Overlay usage (without FIT images)
+=
+
+FDT overlays are now available for use even without FIT images.
+It is not as automagic as with FIT images though and require a few
+manual steps.
+
+1. Figure out where to place both the base device tree blob and the
+overlay. Make sure you have enough space to grow the base tree without
+overlapping anything.
+
+=> setenv fdtaddr 0x87f0
+=> setenv fdtovaddr 0x87fc
+
+2. Load the base blob and overlay blobs
+
+=> load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/base.dtb
+=> load ${devtype} ${bootpart} ${fdtovaddr} ${bootdir}/overlay.dtb
+
+3. Set it as the working fdt tree.
+
+=> fdtaddr $fdtaddr
+
+4. Grow it enough so it can 'fit' all the applied overlays
+
+=> fdt resize 8192
+
+5. You are now ready to apply the overlay.
+
+=> fdt apply $fdtovaddr
+
+Please note that in case of an error, both the base and overlays are going
+to be invalidated, so keep copies to avoid reloading.
+
+Pantelis Antoniou
+pantelis.anton...@konsulko.com
+11/7/2017
-- 
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[U-Boot] [PATCH v2 06/10] doc: overlays: Tweak documentation regarding overlays

[Pantelis Antoniou]

From: Franklin S Cooper Jr 

Pull some information regarding overlays from commit messages and
put them directly within the documentation. Also add some information
regarding required dtc version to properly use overlays.

Signed-off-by: Franklin S Cooper Jr 
---
 doc/README.fdt-overlays | 85 +++--
 doc/uImage.FIT/overlay-fdt-boot.txt |  8 +++-
 2 files changed, 87 insertions(+), 6 deletions(-)

diff --git a/doc/README.fdt-overlays b/doc/README.fdt-overlays
index ee868ec..39139cb 100644
--- a/doc/README.fdt-overlays
+++ b/doc/README.fdt-overlays
@@ -1,9 +1,76 @@
-U-Boot FDT Overlay usage (without FIT images)
+U-Boot FDT Overlay usage
 =
 
-FDT overlays are now available for use even without FIT images.
-It is not as automagic as with FIT images though and require a few
-manual steps.
+Overlays Syntax
+---
+
+Overlays require slightly different syntax compared to traditional overlays.
+Please refer to dt-object-internal.txt in the dtc sources for information
+regarding the internal format of overlays:
+https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/Documentation/dt-object-internal.txt
+
+Building Overlays
+-
+
+In a nutshell overlays provides a means to manipulate a symbol a previous dtb
+or overlay has defined. It requires both the base and all the overlays
+to be compiled with the -@ command line switch so that symbol information is
+included.
+
+Note support for -@ option can only be found in dtc version 1.4.4 or newer.
+Only version 4.14 or higher of the Linux kernel includes a built in version
+of dtc that meets this requirement.
+
+Building an overlay follows the same process as building a traditional dtb.
+
+For example:
+
+base.dts
+
+
+   /dts-v1/;
+   / {
+   foo: foonode {
+   foo-property;
+   };
+   };
+
+   $ dtc -@ -I dts -O dtb -o base.dtb base.dts
+
+bar.dts
+---
+
+   /dts-v1/;
+   /plugin/;
+   / {
+   fragment@1 {
+   target = <>;
+   __overlay__ {
+   overlay-1-property;
+   bar: barnode {
+   bar-property;
+   };
+   };
+   };
+   };
+
+   $ dtc -@ -I dts -O dtb -o bar.dtb bar.dts
+
+Ways to Utilize Overlays in U-boot
+--
+
+There are two ways to apply overlays in U-boot.
+1. Include and define overlays within a FIT image and have overlays
+   automatically applied.
+
+2. Manually load and apply overlays
+
+The remainder of this document will discuss using overlays via the manual
+approach. For information on using overlays as part of a FIT image please see:
+doc/uImage.FIT/overlay-fdt-boot.txt
+
+Manually Loading and Applying Overlays
+--
 
 1. Figure out where to place both the base device tree blob and the
 overlay. Make sure you have enough space to grow the base tree without
@@ -29,6 +96,16 @@ overlapping anything.
 
 => fdt apply $fdtovaddr
 
+6. Boot system like you would do with a traditional dtb.
+
+For bootm:
+
+=> bootm ${kerneladdr} - ${fdtaddr}
+
+For bootz:
+
+=> bootz ${kerneladdr} - ${fdtaddr}
+
 Please note that in case of an error, both the base and overlays are going
 to be invalidated, so keep copies to avoid reloading.
 
diff --git a/doc/uImage.FIT/overlay-fdt-boot.txt 
b/doc/uImage.FIT/overlay-fdt-boot.txt
index dbdf2a1..63e47da 100644
--- a/doc/uImage.FIT/overlay-fdt-boot.txt
+++ b/doc/uImage.FIT/overlay-fdt-boot.txt
@@ -1,5 +1,5 @@
-U-Boot FDT Overlay usage
-
+U-Boot FDT Overlay FIT usage
+
 
 Introduction
 
@@ -8,6 +8,10 @@ of similar boards and their expansion options. The same kernel 
on DT enabled
 platforms can support this easily enough by providing a DT blob upon boot
 that matches the desired configuration.
 
+This document focuses on specifically using overlays as part of a FIT image.
+General information regarding overlays including its syntax and building it
+can be found in doc/README.fdt-overlays
+
 Configuration without overlays
 --
 
-- 
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[U-Boot] [PATCH v2 02/10] fdt: Allow stacked overlays phandle references

[Pantelis Antoniou]

This patch enables an overlay to refer to a previous overlay's
labels by performing a merge of symbol information at application
time.

In a nutshell it allows an overlay to refer to a symbol that a previous
overlay has defined. It requires both the base and all the overlays
to be compiled with the -@ command line switch so that symbol
information is included.

base.dts


/dts-v1/;
/ {
foo: foonode {
foo-property;
};
};

$ dtc -@ -I dts -O dtb -o base.dtb base.dts

bar.dts
---

/dts-v1/;
/plugin/;
/ {
fragment@1 {
target = <>;
__overlay__ {
overlay-1-property;
bar: barnode {
bar-property;
};
};
};
};

$ dtc -@ -I dts -O dtb -o bar.dtb bar.dts

baz.dts
---

/dts-v1/;
/plugin/;
/ {
fragment@1 {
target = <>;
__overlay__ {
overlay-2-property;
baz: baznode {
baz-property;
};
};
};
};

$ dtc -@ -I dts -O dtb -o baz.dtb baz.dts

Applying the overlays:

$ fdtoverlay -i base.dtb -o target.dtb bar.dtb baz.dtb

Dumping:

$ fdtdump target.dtb
/ {
foonode {
overlay-1-property;
foo-property;
linux,phandle = <0x0001>;
phandle = <0x0001>;
barnode {
overlay-2-property;
phandle = <0x0002>;
linux,phandle = <0x0002>;
bar-property;
baznode {
phandle = <0x0003>;
linux,phandle = <0x0003>;
baz-property;
};
};
};
__symbols__ {
baz = "/foonode/barnode/baznode";
bar = "/foonode/barnode";
foo = "/foonode";
};
};

Signed-off-by: Pantelis Antoniou 
Signed-off-by: David Gibson 
---
 lib/libfdt/fdt_overlay.c | 228 ++-
 1 file changed, 206 insertions(+), 22 deletions(-)

diff --git a/lib/libfdt/fdt_overlay.c b/lib/libfdt/fdt_overlay.c
index ceb9687..bd81241 100644
--- a/lib/libfdt/fdt_overlay.c
+++ b/lib/libfdt/fdt_overlay.c
@@ -39,6 +39,7 @@ static uint32_t overlay_get_target_phandle(const void *fdto, 
int fragment)
  * @fdt: Base device tree blob
  * @fdto: Device tree overlay blob
  * @fragment: node offset of the fragment in the overlay
+ * @pathp: pointer which receives the path of the target (or NULL)
  *
  * overlay_get_target() retrieves the target offset in the base
  * device tree of a fragment, no matter how the actual targetting is
@@ -49,37 +50,47 @@ static uint32_t overlay_get_target_phandle(const void 
*fdto, int fragment)
  *  Negative error code on error
  */
 static int overlay_get_target(const void *fdt, const void *fdto,
- int fragment)
+ int fragment, char const **pathp)
 {
uint32_t phandle;
-   const char *path;
-   int path_len;
+   const char *path = NULL;
+   int path_len = 0, ret;
 
/* Try first to do a phandle based lookup */
phandle = overlay_get_target_phandle(fdto, fragment);
if (phandle == (uint32_t)-1)
return -FDT_ERR_BADPHANDLE;
 
-   if (phandle)
-   return fdt_node_offset_by_phandle(fdt, phandle);
+   /* no phandle, try path */
+   if (!phandle) {
+   /* And then a path based lookup */
+   path = fdt_getprop(fdto, fragment, "target-path", _len);
+   if (path)
+   ret = fdt_path_offset(fdt, path);
+   else
+   ret = path_len;
+   } else
+   ret = fdt_node_offset_by_phandle(fdt, phandle);
 
-   /* And then a path based lookup */
-   path = fdt_getprop(fdto, fragment, "target-path", _len);
-   if (!path) {
-   /*
-* If we haven't found either a target or a
-* target-path property in a node that contains a
-* __overlay__ subnode (we wouldn't be called
-* otherwise), consider it a improperly written
-* overlay
-*/
-   if (path_len == -FDT_ERR_NOTFOUND)
-   return -FDT_ERR_BADOVERLAY;
+   /*
+   * If we haven't found 

[U-Boot] [PATCH v2 01/10] Introduce fdt_setprop_placeholder() method

[Pantelis Antoniou]

In some cases you need to add a property but the contents of it
are not known at creation time, merely the extend of it.

This method allows you to create a property of a given size (filled
with garbage) while a pointer to the property data will be provided.

Signed-off-by: Pantelis Antoniou 
[dwg: Corrected commit message]
Signed-off-by: David Gibson 
---
 lib/libfdt/fdt_rw.c | 20 +---
 lib/libfdt/libfdt.h | 31 +++
 2 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 80a3212..3dc7752 100644
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
@@ -228,8 +228,8 @@ int fdt_set_name(void *fdt, int nodeoffset, const char 
*name)
return 0;
 }
 
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
-   const void *val, int len)
+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
+   int len, void **prop_data)
 {
struct fdt_property *prop;
int err;
@@ -242,8 +242,22 @@ int fdt_setprop(void *fdt, int nodeoffset, const char 
*name,
if (err)
return err;
 
+   *prop_data = prop->data;
+   return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+   const void *val, int len)
+{
+   void *prop_data;
+   int err;
+
+   err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, _data);
+   if (err)
+   return err;
+
if (len)
-   memcpy(prop->data, val, len);
+   memcpy(prop_data, val, len);
return 0;
 }
 
diff --git a/lib/libfdt/libfdt.h b/lib/libfdt/libfdt.h
index f3f9cad..6af94cb 100644
--- a/lib/libfdt/libfdt.h
+++ b/lib/libfdt/libfdt.h
@@ -1405,6 +1405,37 @@ int fdt_setprop(void *fdt, int nodeoffset, const char 
*name,
const void *val, int len);
 
 /**
+ * fdt_setprop _placeholder - allocate space for a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @len: length of the property value
+ * @prop_data: return pointer to property data
+ *
+ * fdt_setprop_placeholer() allocates the named property in the given node.
+ * If the property exists it is resized. In either case a pointer to the
+ * property data is returned.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
+   int len, void **prop_data);
+
+/**
  * fdt_setprop_u32 - set a property to a 32-bit integer
  * @fdt: pointer to the device tree blob
  * @nodeoffset: offset of the node whose property to change
-- 
2.1.4

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[U-Boot] [PATCH v2 00/10] uboot overlays, FIT image & unittest

[Pantelis Antoniou]

This patchset allows uboot to handle overlays in a manner that uses
a base DT blob and an arbitrary number of DT overlays blobs.

While it is intended to be used with FIT images since handling a multitude
of device tree blobs manually is a chore, manual fdt overlay application
is supported and described.

The first 2 patches have already been accepted in DTC mainline.
We can apply them now, or expect the updated drop from mainline.

The next patch contains the FIT FDT blob generation logic as well
as documentation about how it works. 

Path #4 spits out an informative message in case of an overlay
failure that may be attribute to mis-compilation (which is
a common problem).

Patches 5 & 6 are documentation entries.

Patch #7 makes sure unit tests using overlays can be used on
non-sandbox boards.

Patch #8 adds overlay unit tests as part of sandbox's defconfig.

Patch #9 fixes a problem with unit tests using an already
present symbol.

Finally, #10 adds a unit test using a stacked overlay.

The patchset is available at

https://github.com/pantoniou/u-boot/tree/uboot-overlays

and is against mainline u-boot as pulled today, 11/8/2017.

Franklin S Cooper Jr (1):
  doc: overlays: Tweak documentation regarding overlays

Pantelis Antoniou (9):
  Introduce fdt_setprop_placeholder() method
  fdt: Allow stacked overlays phandle references
  fit: Introduce methods for applying overlays on fit-load
  fdt-overlay: Spit out a descriptive failure warning
  doc: Document how to apply fdt overlays
  dtbo: make dtbos special
  config: sandbox: Add unit tests
  ut: fix fdt_getprop_u32() change
  test: overlay: Add unit test for stacked overlay

 cmd/fdt.c|   8 +
 common/image-fdt.c   |   7 +-
 common/image-fit.c   | 226 --
 configs/sandbox_defconfig|   2 +
 doc/README.fdt-overlays  | 114 ++
 doc/uImage.FIT/command_syntax_extensions.txt |  12 +-
 doc/uImage.FIT/overlay-fdt-boot.txt  | 225 ++
 doc/uImage.FIT/source_file_format.txt|   6 +-
 include/image.h  |  10 ++
 lib/libfdt/fdt_overlay.c | 228 ---
 lib/libfdt/fdt_rw.c  |  20 ++-
 lib/libfdt/libfdt.h  |  31 
 scripts/Makefile.lib |  17 ++
 test/overlay/Makefile|   1 +
 test/overlay/cmd_ut_overlay.c|  50 --
 test/overlay/test-fdt-overlay-stacked.dts|  21 +++
 16 files changed, 926 insertions(+), 52 deletions(-)
 create mode 100644 doc/README.fdt-overlays
 create mode 100644 doc/uImage.FIT/overlay-fdt-boot.txt
 create mode 100644 test/overlay/test-fdt-overlay-stacked.dts

-- 
2.1.4

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[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007

[Ran Wang]

Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009007():
1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  6 ++
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  7 +++
 3 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 0acff07..f45bb1d 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -69,6 +70,11 @@ config SYS_FSL_ERRATUM_A008997
help
Workaround for USB PHY erratum A008997
 
+config SYS_FSL_ERRATUM_A009007
+   bool
+   help
+   Workaround for USB PHY erratum A009007
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6f8eb0b..9e78344 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -93,6 +93,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+   out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+   out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+   out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+   out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
 
 void s_init(void)
 {
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 539c1cf..703e59f 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,6 +181,13 @@ struct ccsr_gur {
 #define USB_PCSTXSWINGFULL_MASK0xFE00
 #define USB_PCSTXSWINGFULL_VAL 0x8E00
 
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 7/8] armv7: Add workaround for USB erratum A-008997

[Ran Wang]

Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a008997():
1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  6 ++
 arch/arm/cpu/armv7/ls102xa/soc.c  | 14 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  3 +++
 3 files changed, 23 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 609333e..0acff07 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -63,6 +64,11 @@ config SYS_FSL_ERRATUM_A009798
help
Workaround for USB PHY erratum A009798
 
+config SYS_FSL_ERRATUM_A008997
+   bool
+   help
+   Workaround for USB PHY erratum A008997
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 9401175..6f8eb0b 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -81,6 +81,19 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM2CR / 4);
+
+   val &= ~USB_PCSTXSWINGFULL_MASK;
+   val |= USB_PCSTXSWINGFULL_VAL;
+   out_be32(scfg + SCFG_USB3PRM2CR / 4, val);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+
 void s_init(void)
 {
 }
@@ -170,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..539c1cf 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,9 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define SCFG_USB3PRM2CR0x074
+#define USB_PCSTXSWINGFULL_MASK0xFE00
+#define USB_PCSTXSWINGFULL_VAL 0x8E00
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 5/8] armv7: Add workaround for USB erratum A-009008

[Ran Wang]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is ovserved, change
set the same value.

Signed-off-by: Sriram Dash 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009008():
1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  6 ++
 arch/arm/cpu/armv7/ls102xa/soc.c  | 15 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 6a013b2..96e9782 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -51,6 +52,11 @@ config SECURE_BOOT
 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+   bool
+   help
+   Workaround for USB erratum A009008
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b84a1a6..ac060bb 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
 void s_init(void)
 {
 }
@@ -146,6 +158,9 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
+
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR0x070
+#define USB_TXVREFTUNE 0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 6/8] armv7: Add workaround for USB erratum A-009798

[Ran Wang]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009798():
1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  8 +++-
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 96e9782..609333e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -55,7 +56,12 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool
help
-   Workaround for USB erratum A009008
+   Workaround for USB PHY erratum A009008
+
+config SYS_FSL_ERRATUM_A009798
+   bool
+   help
+   Workaround for USB PHY erratum A009798
 
 config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ac060bb..9401175 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -71,6 +71,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
 
 void s_init(void)
 {
@@ -160,6 +169,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v2 4/8] armv8: Add workaround for USB erratum A-009007

[Ran Wang]

Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Changes identified in setup makes the Rx compliance test pass.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009007():
1.Put a blank line after variable declaration.
2.Create a mcro to run for each USB for easier to read and maintain.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  | 12 ++-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 40 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  8 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  9 +
 4 files changed, 68 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a2de86b..1744ed9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -25,6 +25,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -49,6 +50,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -88,6 +90,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -238,7 +241,14 @@ config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
 config SYS_FSL_ERRATUM_A008997
-   bool "Workaround for USB PHY erratum A008997"
+   bool
+   help
+   Workaround for USB PHY erratum A008997
+
+config SYS_FSL_ERRATUM_A009007
+   bool
+   help
+   Workaround for USB PHY erratum A009007
 
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 460e589..d01e665 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -118,6 +118,44 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+   out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);   \
+   out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);   \
+   out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);   \
+   out_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#elif defined(CONFIG_ARCH_LS2080A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+   out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+   out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+   out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+   out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#endif
+
+static void erratum_a009007(void)
+{
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   void __iomem *usb_phy = (void __iomem *)USB_PHY1;
+
+   PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+   usb_phy = (void __iomem *)USB_PHY2;
+   PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+   usb_phy = (void __iomem *)USB_PHY3;
+   PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#elif defined(CONFIG_ARCH_LS2080A)
+   void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+
+   PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
+   PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -267,6 +305,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -545,6 +584,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2e52078..69fd79c 100644
--- 

[U-Boot] [PATCH v2 3/8] armv8: Add workaround for USB erratum A-008997

[Ran Wang]

Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings

Change setting required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a008997():
1.Put a blank line after variable declaration.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 24 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 2dae539..a2de86b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -47,6 +48,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -85,6 +87,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009203
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -234,6 +237,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 14b5584..460e589 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -96,6 +96,28 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -244,6 +266,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -521,6 +544,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8bd40e8..2e52078 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -339,10 +339,14 @@ struct ccsr_gur {
 
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM2CR_USB1   0x074
 #define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM2CR_USB2   0x080
 #define SCFG_USB3PRM1CR_USB3   0x088
+#define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PCSTXSWINGFULL 0x47
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
-- 
2.1.0.27.g96db324

___
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[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798

[Ran Wang]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV woards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
Signed-off-by: Suresh Gupta 
Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009798():
1.Put a blank line after variable declaration.
2.Move common code together.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  5 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 22 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 300f5ce..2dae539 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -23,6 +23,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -45,6 +46,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -82,6 +84,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -228,6 +231,8 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
 
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 261b2dd..14b5584 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -76,6 +76,26 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_ARCH_LS2080A)
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -223,6 +243,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -499,6 +520,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 62d7046..8bd40e8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -342,6 +342,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c622ee5..2d309d5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
 #define SCFG_USB3PRM1CR 

[U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

[Ran Wang]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 1001 is observed, change
set the same value.

Signed-off-by: Ran Wang 
---
Change in v2:
In function erratum_a009008():
1.Put a blank line after variable declaration.
2.Move common code together.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  7 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 26 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 40 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5825f9b..300f5ce 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -22,6 +22,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -43,6 +44,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -79,6 +81,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
+   select SYS_FSL_ERRATUM_A009008
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -222,6 +225,10 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index aee1ffa..261b2dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,30 @@ bool soc_has_aiop(void)
return false;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_ARCH_LS2080A)
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -198,6 +222,7 @@ void fsl_lsch3_early_init_f(void)
 #endif
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -473,6 +498,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8ad199f..62d7046 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,6 +337,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 59410aa..c622ee5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ 

[U-Boot] [PATCH v3 2/3] armv8: ls1088ardb: Add support for LS1088ARDB platform

[Ashish Kumar]

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Alison Wang 
Signed-off-by: Prabhakar Kushwaha 
Signed-off-by: Ashish Kumar 
Signed-off-by: Raghav Dogra 
Signed-off-by: Shaohui Xie 
---
v2:
Fix indentaion in commit msg
Separate RDB and Si specific file

v3:
1.Re-based on top of
  commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
  Merge: f0ca30f 6a5691e
  Author: Tom Rini 
  Date:   Tue Aug 8 17:06:19 2017 -0400

Merge git://git.denx.de/u-boot-x86

2.Incorporate review comments on v2
  Remove EMU support
  Remove RAW timings 
  Disable default enabled CONFIG_DISPLAY_BOARDINFO and enable 
LATE_CONFIG_DISPLAY_BOARDINFO

3.Include PPA support 

 arch/arm/Kconfig  |  12 ++
 arch/arm/cpu/armv8/Kconfig|   1 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |   1 +
 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/fsl-ls1088a-rdb.dts  |  40 
 board/freescale/ls1088a/Kconfig   |  15 ++
 board/freescale/ls1088a/MAINTAINERS   |   9 +
 board/freescale/ls1088a/Makefile  |   9 +
 board/freescale/ls1088a/ddr.c | 106 ++
 board/freescale/ls1088a/ddr.h |  44 
 board/freescale/ls1088a/eth_ls1088ardb.c  | 102 +
 board/freescale/ls1088a/ls1088a.c | 340 ++
 board/freescale/ls1088a/ls1088a_qixis.h   |  34 +++
 configs/ls1088ardb_qspi_defconfig |  35 +++
 include/configs/ls1088a_common.h  | 204 ++
 include/configs/ls1088ardb.h  | 335 +
 16 files changed, 1289 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1088a-rdb.dts
 create mode 100644 board/freescale/ls1088a/Kconfig
 create mode 100644 board/freescale/ls1088a/MAINTAINERS
 create mode 100644 board/freescale/ls1088a/Makefile
 create mode 100644 board/freescale/ls1088a/ddr.c
 create mode 100644 board/freescale/ls1088a/ddr.h
 create mode 100644 board/freescale/ls1088a/eth_ls1088ardb.c
 create mode 100644 board/freescale/ls1088a/ls1088a.c
 create mode 100644 board/freescale/ls1088a/ls1088a_qixis.h
 create mode 100644 configs/ls1088ardb_qspi_defconfig
 create mode 100644 include/configs/ls1088a_common.h
 create mode 100644 include/configs/ls1088ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9cfeede..dcff602 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -892,6 +892,17 @@ config TARGET_LS1012AFRDM
  development platform that supports the QorIQ LS1012A
  Layerscape Architecture processor.
 
+config TARGET_LS1088ARDB
+   bool "Support ls1088ardb"
+   select ARCH_LS1088A
+   select ARM64
+   select ARMV8_MULTIENTRY
+   help
+ Support for NXP LS1088ARDB platform.
+ The LS1088AA Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1088A
+ Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select BOARD_LATE_INIT
@@ -1174,6 +1185,7 @@ source "board/creative/xfi3/Kconfig"
 source "board/freescale/ls2080a/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
 source "board/freescale/ls2080ardb/Kconfig"
+source "board/freescale/ls1088a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 8e4c3dd..aecdf81 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -88,6 +88,7 @@ config PSCI_RESET
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+  !TARGET_LS1088ARDB && \
   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a3c7490..35f3118 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -207,6 +207,7 @@ config SYS_LS_PPA_FW_ADDR
default 0x2040 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
default 0x4040 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
default 0x58040 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+   default 0x2040 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
default 0x6040 if SYS_LS_PPA_FW_IN_XIP
default 0x40 if SYS_LS_PPA_FW_IN_MMC
default 0x40 if 

[U-Boot] [PATCH v3 1/3] armv8: ls1088a: Add NXP LS1088A SoC support

[Ashish Kumar]

The QorIQ LS1088A processor is built on the Layerscape
architecture combining eight ARM A53 processor cores
with advanced, high-performance datapath acceleration
and networks, peripheral interfaces required for
networking, wireless infrastructure, and general-purpose
embedded applications.

LS1088A is compliant to the Layerscape Chassis Generation 3.

Features summary:
 - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
 - Cores are in 2 cluster of 4-cores each
 - Cache coherent interconnect (CCI-400)
 - One 64-bit DDR4 SDRAM memory controller with ECC
 - Data path acceleration architecture 2.0 (DPAA2)
 - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
 - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc

Signed-off-by: Alison Wang 
Signed-off-by: Prabhakar Kushwaha 
Signed-off-by: Ashish Kumar 
Signed-off-by: Raghav Dogra 
Signed-off-by: Shaohui Xie 
---

v2:
 Fix indentaion in commit msg
 Separate RDB and Si specific file
 Move Macros to Kconfig

v3:
1.Re-based on top of
  commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
  Merge: f0ca30f 6a5691e
  Author: Tom Rini 
  Date:   Tue Aug 8 17:06:19 2017 -0400

Merge git://git.denx.de/u-boot-x86

2.Incorporate review comments on v2
  Clean up done

3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  39 ++-
 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c|  10 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |   6 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   5 +
 arch/arm/dts/fsl-ls1088a.dtsi  |  78 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   4 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   4 +
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h  |  14 +++
 drivers/ddr/fsl/util.c |   2 +-
 drivers/net/ldpaa_eth/Makefile |   1 +
 drivers/net/ldpaa_eth/ls1088a.c|  87 ++
 16 files changed, 447 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
 create mode 100644 drivers/net/ldpaa_eth/ls1088a.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 1132969..a3c7490 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -49,6 +49,29 @@ config ARCH_LS1046A
select BOARD_EARLY_INIT_F
imply SCSI
 
+config ARCH_LS1088A
+   bool
+   select ARMV8_SET_SMPEN
+   select FSL_LSCH3
+   select SYS_FSL_DDR
+   select SYS_FSL_DDR_LE
+   select SYS_FSL_DDR_VER_50
+   select SYS_FSL_ERRATUM_A009803
+   select SYS_FSL_ERRATUM_A009942
+   select SYS_FSL_ERRATUM_A010165
+   select SYS_FSL_ERRATUM_A008511
+   select SYS_FSL_ERRATUM_A008850
+   select SYS_FSL_HAS_CCI400
+   select SYS_FSL_HAS_DDR4
+   select SYS_FSL_HAS_SEC
+   select SYS_FSL_SEC_COMPAT_5
+   select SYS_FSL_SEC_LE
+   select SYS_FSL_SRDS_1
+   select SYS_FSL_SRDS_2
+   select FSL_TZASC_1
+   select ARCH_EARLY_INIT_R
+   select BOARD_EARLY_INIT_F
+
 config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
@@ -60,6 +83,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
@@ -98,7 +122,7 @@ config FSL_LSCH3
 
 config FSL_MC_ENET
bool "Management Complex network"
-   depends on ARCH_LS2080A
+   depends on ARCH_LS2080A || ARCH_LS1088A
default y
select RESV_RAM
help
@@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
+   default "fsl,ls1080a-pcie" if ARCH_LS1088A
help
  This compatible is used to find pci controller node in Kernel DT
  to complete fixup.
@@ -228,6 +253,7 @@ config MAX_CPUS
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
+   default 8 if ARCH_LS1088A
default 1
help
  Set this number to the maximum number of possible CPUs in the SoC.
@@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET
 
 config SYS_FSL_IFC_BANK_COUNT
int "Maximum 

Re: [U-Boot] [Patch v2 2/3] armv8: ls1088ardb: Add support for LS1088ARDB platform

[Ashish Kumar]

Hello York,

Thanks for your comments,
Please see inline, most comments address in v3

Regards
Ashish

-Original Message-
From: York Sun [mailto:york@nxp.com] 
Sent: Wednesday, April 12, 2017 2:26 AM
To: Ashish Kumar ; u-boot@lists.denx.de; 
u-b...@linux.freescale.net
Cc: Alison Wang ; Prabhakar Kushwaha 
; Raghav Dogra ; Shaohui Xie 

Subject: Re: [Patch v2 2/3] armv8: ls1088ardb: Add support for LS1088ARDB 
platform

On 04/10/2017 09:19 AM, Ashish Kumar wrote:
> LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin 
> platform that supports the LS1088A family SoCs. This patch add basic 
> support of the platform.
>
> Signed-off-by: Alison Wang 
> Signed-off-by: Prabhakar Kushwaha 
> Signed-off-by: Ashish Kumar 
> Signed-off-by: Raghav Dogra 
> Signed-off-by: Shaohui Xie 
> ---
> v2:
> Fix indentaion in commit msg
> Separate RDB and Si specific file
>
>  arch/arm/Kconfig |  12 ++
>  arch/arm/cpu/armv8/Kconfig   |   1 +
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/fsl-ls1088a-rdb.dts |  40 
>  board/freescale/ls1088a/Kconfig  |  15 ++
>  board/freescale/ls1088a/MAINTAINERS  |   9 +
>  board/freescale/ls1088a/Makefile |   9 +
>  board/freescale/ls1088a/ddr.c| 215 +++
>  board/freescale/ls1088a/ddr.h|  46 
>  board/freescale/ls1088a/eth_ls1088ardb.c | 102 +
>  board/freescale/ls1088a/ls1088a.c| 336 ++
>  board/freescale/ls1088a/ls1088a_qixis.h  |  34 +++
>  configs/ls1088ardb_qspi_defconfig|  33 +++
>  include/configs/ls1088a_common.h | 205 ++
>  include/configs/ls1088ardb.h | 346 
> +++
>  15 files changed, 1405 insertions(+), 1 deletion(-)  create mode 
> 100644 arch/arm/dts/fsl-ls1088a-rdb.dts  create mode 100644 
> board/freescale/ls1088a/Kconfig  create mode 100644 
> board/freescale/ls1088a/MAINTAINERS
>  create mode 100644 board/freescale/ls1088a/Makefile  create mode 
> 100644 board/freescale/ls1088a/ddr.c  create mode 100644 
> board/freescale/ls1088a/ddr.h  create mode 100644 
> board/freescale/ls1088a/eth_ls1088ardb.c
>  create mode 100644 board/freescale/ls1088a/ls1088a.c  create mode 
> 100644 board/freescale/ls1088a/ls1088a_qixis.h
>  create mode 100644 configs/ls1088ardb_qspi_defconfig  create mode 
> 100644 include/configs/ls1088a_common.h  create mode 100644 
> include/configs/ls1088ardb.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 
> 0a05662..a441cb3 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -954,6 +954,17 @@ config TARGET_LS1012AFRDM
> development platform that supports the QorIQ LS1012A
> Layerscape Architecture processor.
>
> +config TARGET_LS1088ARDB
> + bool "Support ls1088ardb"
> + select ARCH_LS1088A
> + select ARM64
> + select ARMV8_MULTIENTRY
> + help
> +   Support for NXP LS1088ARDB platform.
> +   The LS1088AA Reference design board (RDB) is a high-performance
> +   development platform that supports the QorIQ LS1088A
> +   Layerscape Architecture processor.
> +
>  config TARGET_LS1021AQDS
>   bool "Support ls1021aqds"
>   select BOARD_LATE_INIT
> @@ -1207,6 +1218,7 @@ source "board/denx/m53evk/Kconfig"
>  source "board/freescale/ls2080a/Kconfig"
>  source "board/freescale/ls2080aqds/Kconfig"
>  source "board/freescale/ls2080ardb/Kconfig"
> +source "board/freescale/ls1088a/Kconfig"
>  source "board/freescale/ls1021aqds/Kconfig"
>  source "board/freescale/ls1043aqds/Kconfig"
>  source "board/freescale/ls1021atwr/Kconfig"
> diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig 
> index 0188b95..630bb78 100644
> --- a/arch/arm/cpu/armv8/Kconfig
> +++ b/arch/arm/cpu/armv8/Kconfig
> @@ -88,6 +88,7 @@ config PSCI_RESET
>   depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
>  !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
>  !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
> +!TARGET_LS1088ARDB && \
>  !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
>  !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
>  !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ diff --git 
> a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eb68c20..5ac8ea3 
> 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -163,7 +163,8 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
>   ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
>   ls1021a-iot-duart.dtb
>  dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
> - fsl-ls2080a-rdb.dtb
> + fsl-ls2080a-rdb.dtb \
> + 

Re: [U-Boot] [PATCH 2/2] sf: Preserve QE bit when clearing BP# bits for Macronix flash

[Bin Meng]

On Mon, Aug 7, 2017 at 3:54 PM, Jagan Teki  wrote:
> Hi Bing,
>
> On Mon, Aug 7, 2017 at 1:09 PM, Bin Meng  wrote:
>> On Fri, Aug 4, 2017 at 12:21 PM, Bin Meng  wrote:
>>> On Wed, Aug 2, 2017 at 6:26 AM, Bin Meng  wrote:
 Hi Jagan,

 On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki  
 wrote:
> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng  wrote:
>> On some flash (like Macronix), QE (quad enable) bit is in the same
>> status register as BP# bits, and we need preserve its original value
>> during a reboot cycle as this is required by some platforms (like
>> Intel ICH SPI controller working under descriptor mode).
>>
>> Signed-off-by: Bin Meng 
>> ---
>>
>>  drivers/mtd/spi/spi_flash.c | 17 +++--
>>  1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
>> index 0034a28..7d8c660 100644
>> --- a/drivers/mtd/spi/spi_flash.c
>> +++ b/drivers/mtd/spi/spi_flash.c
>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash)
>> if (IS_ERR_OR_NULL(info))
>> return -ENOENT;
>>
>> -   /* Flash powers up read-only, so clear BP# bits */
>> +   /*
>> +* Flash powers up read-only, so clear BP# bits.
>> +*
>> +* Note on some flash (like Macronix), QE (quad enable) bit is 
>> in the
>> +* same status register as BP# bits, and we need preserve its 
>> original
>> +* value during a reboot cycle as this is required by some 
>> platforms
>> +* (like Intel ICH SPI controller working under descriptor mode).
>> +*/
>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
>> -   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
>> write_sr(flash, 0);
>> +   if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
>> +   u8 sr = 0;
>> +
>> +   read_sr(flash, );
>> +   sr &= STATUS_QEB_MXIC;
>> +   write_sr(flash, sr);
>> +   }
>
> It doesn't make sense to have one(specific) controller fix to be
> generic to all macronix chips, think about alternative.
>

 This is no way to fix at the controller level. Actually this is
 nothing related to controller level. It's just the bootstrap settings
 (QE bit in this case) that cannot be overwritten by someone else
 (although it's seen on Intel, it might happen on some other
 architecture). The logic in the codes are having issues. Its comment
 says: clear BP# bits, but it clears QE bit for Macronix flash as well,
 which is wrong. The update was just to make sure the codes do as what
 its comment says.

 If you have any other alternative, please suggest.

>>>
>>> Ping again..
>
> Wait for sometime, I've queue that I need to review-it and respond
> accordingly patches with latest may take some time. And commenting
> yes will respond soon.
>

Ping!

Can you please respond with a reasonable time frame (ie: when you will
have time to look at this)?

Regards,
Bin
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