Re: [PATCH 1/2] arm: socfpga: arria10: add option to reprogram the FPGA every reboot

[Dinh Nguyen]

On 2/22/24 09:20, Michał Barnaś wrote:

Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10.
This option allows to change the bitstream on the filesystem and apply
changes with warm reboot without the need for a power cycle.

Signed-off-by: Michał Barnaś 
---

  arch/arm/mach-socfpga/Kconfig   | 8 
  arch/arm/mach-socfpga/spl_a10.c | 8 
  2 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 114d243812..89303f1f16 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -80,6 +80,14 @@ config TARGET_SOCFPGA_ARRIA10
imply FPGA_SOCFPGA
imply SPL_USE_TINY_PRINTF
  
+config TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM

+   bool "Always reprogram Arria 10 FPGA"
+   depends on TARGET_SOCFPGA_ARRIA10
+   help
+ Arria 10 FPGA is only programmed during the cold boot.
+ This option forces the FPGA to be reprogrammed every reboot,
+ allowing to change the bitstream and apply it with warm reboot.
+
  config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 9edbbf4a29..d5d3327a42 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -122,7 +122,11 @@ void spl_board_init(void)
arch_early_init_r();
  
  	/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */

+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
+   if (is_regular_boot_valid()) {
+#else
if (is_fpgamgr_user_mode()) {
+#endif
ret = config_pins(gd->fdt_blob, "shared");
if (ret)
return;
@@ -130,7 +134,11 @@ void spl_board_init(void)
ret = config_pins(gd->fdt_blob, "fpga");
if (ret)
return;
+#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
+   } else {
+#else
} else if (!is_fpgamgr_early_user_mode()) {
+#endif
/* Program IOSSM(early IO release) or full FPGA */
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  


I got an error while trying to apply this patch:

Checking patch arch/arm/mach-socfpga/Kconfig...
error: while searching for:
imply FPGA_SOCFPGA
imply SPL_USE_TINY_PRINTF

config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5

error: patch failed: arch/arm/mach-socfpga/Kconfig:80
Checking patch arch/arm/mach-socfpga/spl_a10.c...

Please rebase to the latest and re-send.

Dinh

Re: [PATCH 0/2] arm: socfpga: arria10: allow to reprogram FPGA with warm reboot

[Dinh Nguyen]

On 2/22/24 09:20, Michał Barnaś wrote:


By default, the board requires power cycle (cold boot) to program the
FPGA with bitstream. This change adds Kconfig that allows to enable
reprogramming the FPGA with every boot. This makes the update process
of the bitstream on the filesystem to be applied with simple system
reboot.




If we want to enable the reprogramming on every boot, would it make 
sense to just do it and not even bother with the Kconfig option?


Dinh

[PATCH] board: altera: c5/a10/a5/stratix10: remove Chin Liang as maintainer

[Dinh Nguyen]

Chin Liang is no longer actively maintaining this project.

Signed-off-by: Dinh Nguyen 
---
 board/altera/arria10-socdk/MAINTAINERS   | 1 -
 board/altera/arria5-socdk/MAINTAINERS| 1 -
 board/altera/cyclone5-socdk/MAINTAINERS  | 1 -
 board/altera/stratix10-socdk/MAINTAINERS | 1 -
 4 files changed, 4 deletions(-)

diff --git a/board/altera/arria10-socdk/MAINTAINERS 
b/board/altera/arria10-socdk/MAINTAINERS
index 5a76efb54b..e288584362 100644
--- a/board/altera/arria10-socdk/MAINTAINERS
+++ b/board/altera/arria10-socdk/MAINTAINERS
@@ -1,6 +1,5 @@
 SOCFPGA BOARD
 M: Dinh Nguyen 
-M: Chin-Liang See 
 S: Maintained
 F: board/altera/arria10-socdk/
 F: include/configs/socfpga_arria10_socdk.h
diff --git a/board/altera/arria5-socdk/MAINTAINERS 
b/board/altera/arria5-socdk/MAINTAINERS
index 873ec2be2d..a6c5bc8024 100644
--- a/board/altera/arria5-socdk/MAINTAINERS
+++ b/board/altera/arria5-socdk/MAINTAINERS
@@ -1,6 +1,5 @@
 SOCFPGA BOARD
 M: Dinh Nguyen 
-M: Chin-Liang See 
 S: Maintained
 F: board/altera/arria5-socdk/
 F: include/configs/socfpga_arria5_socdk.h
diff --git a/board/altera/cyclone5-socdk/MAINTAINERS 
b/board/altera/cyclone5-socdk/MAINTAINERS
index ecf1d04f76..6a8dfdd286 100644
--- a/board/altera/cyclone5-socdk/MAINTAINERS
+++ b/board/altera/cyclone5-socdk/MAINTAINERS
@@ -1,6 +1,5 @@
 SOCFPGA BOARD
 M: Dinh Nguyen 
-M: Chin-Liang See 
 S: Maintained
 F: board/altera/cyclone5-socdk/
 F: include/configs/socfpga_cyclone5_socdk.h
diff --git a/board/altera/stratix10-socdk/MAINTAINERS 
b/board/altera/stratix10-socdk/MAINTAINERS
index 6efd0cfc05..0b475980dd 100644
--- a/board/altera/stratix10-socdk/MAINTAINERS
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -1,6 +1,5 @@
 SOCFPGA BOARD
 M: Chin-Liang See 
-M: Dinh Nguyen 
 S: Maintained
 F: board/altera/stratix10-socdk/
 F: include/configs/socfpga_stratix10_socdk.h
-- 
2.25.1

Re: [PATCH] configs: socfpga: Add CONFIG_NET_RANDOM_ETHADDR=y to SOCFPGA defconfig

[Dinh Nguyen]

On 9/25/22 09:37, teik.heng.ch...@intel.com wrote:

From: Tien Fong Chee 

Ethernet initialization is only work with properly set MAC addresses.
Hence, this config is required to create the random MAC addresses
for Ethernet initialization.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Teik Heng Chong 
---
  configs/socfpga_arria10_defconfig  | 1 +
  configs/socfpga_arria5_defconfig   | 1 +
  configs/socfpga_cyclone5_defconfig | 1 +
  3 files changed, 3 insertions(+)

diff --git a/configs/socfpga_arria10_defconfig 
b/configs/socfpga_arria10_defconfig
index 3eac3dfa5d..53c01ff659 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y
  CONFIG_PHY_MICREL_KSZ90X1=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_MII=y
+CONFIG_NET_RANDOM_ETHADDR=y
  CONFIG_SPI=y
  CONFIG_TIMER=y
  CONFIG_SPL_TIMER=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index dbadb3d49a..da25aa9154 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -63,6 +63,7 @@ CONFIG_PHY_MICREL=y
  CONFIG_PHY_MICREL_KSZ90X1=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_MII=y
+CONFIG_NET_RANDOM_ETHADDR=y
  CONFIG_DM_RESET=y
  CONFIG_SPI=y
  CONFIG_CADENCE_QSPI=y
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 4fd14d2e2c..508bfe31fc 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -64,6 +64,7 @@ CONFIG_PHY_MICREL=y
  CONFIG_PHY_MICREL_KSZ90X1=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_MII=y
+CONFIG_NET_RANDOM_ETHADDR=y
  CONFIG_DM_RESET=y
  CONFIG_SPI=y
  CONFIG_CADENCE_QSPI=y


Acked-by: Dinh Nguyen 

Re: Revert "ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

[Dinh Nguyen]

CC Hean Loong:


On 8/6/20 7:36 AM, Wolfgang Grandegger wrote:
> Am 06.08.20 um 13:04 schrieb Marek Vasut:
>> On 8/6/20 12:53 PM, Wolfgang Grandegger wrote:
>>> This reverts commit c5f4b805755912a3d2fe20f014b6b6ab0473bd73.
>>>
>>> Conflicts:
>>> arch/arm/mach-socfpga/misc_gen5.c
>>>
>>> Without socfpga_sdram_apply_static_cfg(), the system hangs when Linux
>>> calls altvipfb2_start_hw() of the Intel Video and Image Processing(VIP)
>>> Frame Buffer II driver (drivers/video/fbdev/altvipfb2.c)
>>
>> There is no such driver in mainline U-Boot or Linux.
> 
> It's a simple frame buffer driver from linux-socfpga for the IP core
> Intel Video and Image Processing(VIP) Frame Buffer II. It actually
> hangs here when the streaming starts:
> 
> https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.44-lts/drivers/video/fbdev/altvipfb2.c#L69
> 
> I can also hang the system if I setup and start the FB with just a
> few U-Boot commands. I think the system hangs when the IP core starts
> reading the FB data from the system memory.
> 

Can you elaborate what you mean here? You are starting the Frame Buffer
driver with U-Boot?


>>> , but only
>>> after a power cycle (cold boot). The issue does not show up after a
>>> soft reset (warm boot) and with v2018.11.
>>
>> See the commit message of the patch this is reverting, I believe there
>> is a deeper issue with the static config register. Can you investigate?
> 
> I read the commit message, but well, I can't follow all the details :(.
> On the other hand, it seems also not clear why the fix was added. Any
> idea what to investigate.
> 

Dinh

Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot

[Dinh Nguyen]

On 6/15/20 12:56 AM, Nico Becker wrote:
> Am 12.06.2020 um 22:27 schrieb Dinh Nguyen:
>>
>> On 6/12/20 6:41 AM, Marek Vasut wrote:
>>> On 6/12/20 1:04 PM, Nico Becker wrote:
>>>> Am 12.06.2020 um 07:51 schrieb Nico Becker:
>>>>> Am 11.06.2020 um 03:51 schrieb Tan, Ley Foon:
>>>>>>> -Original Message-
>>>>>>> From: Dinh Nguyen 
>>>>>>> Sent: Thursday, June 11, 2020 2:55 AM
>>>>>>> To: Marek Vasut ; Nico Becker >>>>>> automation.de>; u-boot@lists.denx.de
>>>>>>> Cc: simon.k.r.goldschm...@gmail.com; Tan, Ley Foon
>>>>>>> 
>>>>>>> Subject: Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros
>>>>>>> error
>>>>>>> @kernel boot
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 6/10/20 8:23 AM, Marek Vasut wrote:
>>>>>>>> On 6/10/20 3:21 PM, Nico Becker wrote:
>>>>>>>>> Am 10.06.2020 um 15:19 schrieb Marek Vasut:
>>>>>>>>>> On 6/10/20 3:14 PM, Nico Becker wrote:
>>>>>>>>>>> if i remove the arm,shared-override option in the dts file, the
>>>>>>>>>>> kernel boot without an error.
>>>>>>>>>>> With the option the kernel boots with the following error:
>>>>>>>>>>> dmesg --level=err
>>>>>>>>>>> L2C-310: enabling full line of zeros but not enabled in
>>>>>>>>>>> Cortex-A9
>>>>>>>>>>>
>>>>>>>>>>> i ve no idea why the parameter have an effect on that. i try
>>>>>>>>>>> several kernels, allays the same behavior.
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/arch/arm/dts/socfpga.dtsi
>>>>>>>>>>> b/arch/arm/dts/socfpga.dtsi
>>>>>>>>>>> index eda558f2fe..c2173416c7 100644
>>>>>>>>>>> --- a/arch/arm/dts/socfpga.dtsi
>>>>>>>>>>> +++ b/arch/arm/dts/socfpga.dtsi
>>>>>>>>>>> @@ -719,7 +719,6 @@
>>>>>>>>>>>             arm,data-latency = <2 1 1>;
>>>>>>>>>>>             prefetch-data = <1>;
>>>>>>>>>>>             prefetch-instr = <1>;
>>>>>>>>>>> -            arm,shared-override;
>>>>>>>>>>>             arm,double-linefill = <1>;
>>>>>>>>>>>             arm,double-linefill-incr = <0>;
>>>>>>>>>>>             arm,double-linefill-wrap = <1>;
>>>>>>>>>>>
>>>>>>>>>> Do you use latest u-boot/master or some older version ? Which
>>>>>>>>>> one?
>>>>>>>>> sorry, i forget it.
>>>>>>>>>
>>>>>>>>> i use v2020.01
>>>>>>>> Should be OK I think. Hm, I suspect this is another fun with
>>>>>>>> the
>>>>>>>> ACTLR/CPACR registers, like
>>>>>>> 937db7188e3a5ab8f802eff9b57854189379667a .
>>>>>>>> Ley, any ideas ?
>>>>>>>>
>>>>>>> I just tested with
>>>>>>>
>>>>>>> 2020.07-rc4-00022-gbe79009f3b along with linux v5.7,
>>>>>>>
>>>>>>> and I no longer see the error.
>>>>>>>
>>>>>> Yes, I also just tested 2020.04 uboot and 5.4.23-lts kernel, also
>>>>>> didn't see this error.
>>>>>> What kernel version you are using?
>>>>>>
>>>>>> Regards
>>>>>> Ley Foon
>>>>> hello,
>>>>> i use kernel 4.14.126-rt62-ltsi.
>>>>>
>>>>> greetings
>>>>>
>>>>>
>>>> i try the u-boot version v2020.07-rc4 without the patch,
>>>> and everything seems okay, no error at boot.
>>>> i ve no idea why the error at boot time is gone with the 2020.07-rc4
>>>> version.
>>>> does anyone have any idea why?
>>>> thanks, greetings
>>> You can try git bisect between the two versions to find out which patch
>>> caused this.
>>>
>> This is the patch that fixed it:
>>
>> commit f62782fb2999dd8109a3ffe9ee0a51e54ab034ab
>> Author: Ley Foon Tan 
>> Date:   Fri Apr 17 14:45:35 2020 +0800
>>
>>  cache: l2x0: Fix write to incorrect shared-override bit
>>
>>  The existing code write bit-0 for shared attribute override
>> enable bit.
>>  It should be bit-22 based on cache controller specification [1].
>>
>>  [1]
>> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf
>>
>>
>>  Signed-off-by: Ley Foon Tan 
>>
>> Dinh
>>
> hello,
> thanks a lot!
> i try the git bisect method, i was  13 builds away.
> next time i check first the changelog
> greetings

May want to check your usage of git bisect, it took me less than 10 builds.

Dinh

Re: [PATCH] arm: dts: socfpga: l2c-310 full line of zeros error @kernel boot

[Dinh Nguyen]

On 6/10/20 8:23 AM, Marek Vasut wrote:
> On 6/10/20 3:21 PM, Nico Becker wrote:
>> Am 10.06.2020 um 15:19 schrieb Marek Vasut:
>>> On 6/10/20 3:14 PM, Nico Becker wrote:
 if i remove the arm,shared-override option in the dts file,
 the kernel boot without an error.
 With the option the kernel boots with the following error:
 dmesg --level=err
 L2C-310: enabling full line of zeros but not enabled in Cortex-A9

 i ve no idea why the parameter have an effect on that. i try several
 kernels, allays the same behavior.


 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
 index eda558f2fe..c2173416c7 100644
 --- a/arch/arm/dts/socfpga.dtsi
 +++ b/arch/arm/dts/socfpga.dtsi
 @@ -719,7 +719,6 @@
           arm,data-latency = <2 1 1>;
           prefetch-data = <1>;
           prefetch-instr = <1>;
 -            arm,shared-override;
           arm,double-linefill = <1>;
           arm,double-linefill-incr = <0>;
           arm,double-linefill-wrap = <1>;

>>> Do you use latest u-boot/master or some older version ? Which one?
>>
>> sorry, i forget it.
>>
>> i use v2020.01
> 
> Should be OK I think. Hm, I suspect this is another fun with the
> ACTLR/CPACR registers, like 937db7188e3a5ab8f802eff9b57854189379667a .
> Ley, any ideas ?
> 

I just tested with

2020.07-rc4-00022-gbe79009f3b along with linux v5.7,

and I no longer see the error.

Dinh

Re: [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines

[Dinh Nguyen]

On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> This is 2nd version of patchset to convert reset, system and clock manager
> drivers to use #define instead of struct.
> 
> Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
> 
> Patch 1 is new one, patch 2 to 4 have changes.
> 
> Main changes in this version are:
> - Get base address from DT
> - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> - Add prefix to defines.
> - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
> 
> History:
> v1: https://patchwork.ozlabs.org/cover/1149731/
> 

I think you also need to Simon Goldschmidt to this series.

Beside the minor incorrect address missing a zero in patch 1, I've
tested this series on the Sockit.

Tested-by: Dinh Nguyen 

Dinh


___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes

[Dinh Nguyen]

On 9/10/19 3:38 AM, Ley Foon Tan wrote:
> Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
> In preparation to get base address from DT.
> 
> Signed-off-by: Ley Foon Tan 
> ---
>  arch/arm/dts/socfpga-common-u-boot.dtsi  | 8 
>  arch/arm/dts/socfpga.dtsi| 2 +-
>  arch/arm/dts/socfpga_arria10.dtsi| 2 +-
>  arch/arm/dts/socfpga_arria10_socdk.dtsi  | 8 
>  arch/arm/dts/socfpga_stratix10.dtsi  | 2 +-
>  arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 
>  6 files changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi 
> b/arch/arm/dts/socfpga-common-u-boot.dtsi
> index 322c858c4b..d55460755f 100644
> --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> @@ -10,6 +10,10 @@
>   };
>  };
>  
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
>   {
>   u-boot,dm-pre-reloc;
>  };
> @@ -17,3 +21,7 @@
>   {
>   u-boot,dm-pre-reloc;
>  };
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 51a6a51b53..eda558f2fe 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -114,7 +114,7 @@
>   status = "disabled";
>   };
>  
> - clkmgr@ffd04000 {
> + clkmgr: clkmgr@ffd04000 {
>   compatible = "altr,clk-mgr";
>   reg = <0xffd04000 0x1000>;
>  
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
> b/arch/arm/dts/socfpga_arria10.dtsi
> index c11a5c0cc1..cc529bcd11 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -96,7 +96,7 @@
>   fpga-mgr = <_mgr>;
>   };
>  
> - clkmgr@ffd04000 {
> + clkmgr: clkmgr@ffd04000 {
>   compatible = "altr,clk-mgr";
>   reg = <0xffd04000 0x1000>;
>   u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi 
> b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index 6e5578d7bd..ef10708ee8 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -180,3 +180,11 @@
>  _sp_clk {
>   u-boot,dm-pre-reloc;
>  };
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> +
> + {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi 
> b/arch/arm/dts/socfpga_stratix10.dtsi
> index bd68a78a37..91f4e27ef5 100755
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -82,7 +82,7 @@
>   ranges = <0 0 0 0x>;
>   u-boot,dm-pre-reloc;
>  
> - clkmgr@ffd1000 {
> + clkmgr: clkmgr@ffd1000 {

Missing another zero in the address.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 01/15] arm: socfpga: agilex: Add base address for Intel Agilex SoC

[Dinh Nguyen]

On 6/24/19 8:16 PM, Ley Foon Tan wrote:
> On Tue, Jun 25, 2019 at 4:00 AM Simon Goldschmidt
>  wrote:
>>
>> Am 30.05.2019 um 11:03 schrieb Ley Foon Tan:
>>> Add base address for Intel Agilex SoC.
>>>
>>> Reuse base_addr_s10.h for Agilex, only one base address is
>>> different from S10.
>>>
>>> Signed-off-by: Ley Foon Tan 
>>> ---
>>
>> Wait, this is v2, right? What hss changed since v1? I notice v2 has 15
>> patches while v1 had 14.
>>
>> Have you ever considered using patman and its helper tags? It would
>> greatly reduce the effort for reviewers to keep things consistent and
>> including a list of changes in each patch.
>>
>> I mean, when reading v2, I want to rely on you saying "patches 1, 3, and
>> 5 of 14 have changed, the rest have not" to speed up my reviewing.
>> Patman really helps you with that, just try it! And if you don't want
>> to, well, look at how other developers send their multi-version patches...
>>
>> Regards,
>> Simon
>>
> I will look into Patman for next revision.
> 
> Here is summary for this series:
> 
> Patch 1, 5, 6, 7, 8, 13, 14, 15 have changed, the rest have not.
> *Patch 7 is new patch for clock manager driver with DM.
> 

Can you just resend the series with the version changes properly stated
in each patch? Also, its polite to include people in subsequent versions
that have made comments in previous version.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 04/14] arm: socfpga: agilex: Add reset manager support

[Dinh Nguyen]

On 5/10/19 12:54 AM, Ley Foon Tan wrote:
> Add reset manager support for Agilex.
> 
> Signed-off-by: Ley Foon Tan 
> ---
>  .../mach-socfpga/include/mach/reset_manager.h |  5 ++-
>  .../include/mach/reset_manager_agilex.h   | 38 +++

AFAIK, there's really nothing different in Agilex reset manager from the
Stratix10, can you just re-use the Stratix10?

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 01/14] arm: socfpga: agilex: Add base address for Intel Agilex SoC

[Dinh Nguyen]

On 5/10/19 12:54 AM, Ley Foon Tan wrote:
> Add base address for Intel Agilex SoC.
> 
> Signed-off-by: Ley Foon Tan 
> ---
>  .../include/mach/base_addr_agilex.h   | 38 +++
>  1 file changed, 38 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_agilex.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h
> new file mode 100644
> index 00..e90b61f29d
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_agilex.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + */
> +
> +#ifndef _SOCFPGA_AGILEX_BASE_HARDWARE_H_
> +#define _SOCFPGA_AGILEX_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_CCU_ADDRESS  0xf700
> +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS   0xf8020200
> +#define SOCFPGA_SMMU_ADDRESS 0xfa00
> +#define SOCFPGA_MAILBOX_ADDRESS  0xffa3
> +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
> +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
> +#define SOCFPGA_SYSTIMER0_ADDRESS0xffd0
> +#define SOCFPGA_SYSTIMER1_ADDRESS0xffd00100
> +#define SOCFPGA_L4WD0_ADDRESS0xffd00200
> +#define SOCFPGA_L4WD1_ADDRESS0xffd00300
> +#define SOCFPGA_L4WD2_ADDRESS0xffd00400
> +#define SOCFPGA_L4WD3_ADDRESS0xffd00500
> +#define SOCFPGA_GTIMER_SEC_ADDRESS   0xffd01000
> +#define SOCFPGA_GTIMER_NSEC_ADDRESS  0xffd02000
> +#define SOCFPGA_CLKMGR_ADDRESS   0xffd1
> +#define SOCFPGA_RSTMGR_ADDRESS   0xffd11000
> +#define SOCFPGA_SYSMGR_ADDRESS   0xffd12000
> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS  0xffd13000
> +#define SOCFPGA_FIREWALL_L4_PER  0xffd21000
> +#define SOCFPGA_FIREWALL_L4_SYS  0xffd21100
> +#define SOCFPGA_FIREWALL_SOC2FPGA0xffd21200
> +#define SOCFPGA_FIREWALL_LWSOC2FPGA  0xffd21300
> +#define SOCFPGA_FIREWALL_TCU 0xffd21400
> +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda
> +#define SOCFPGA_DMASECURE_ADDRESS0xffda1000
> +#define SOCFPGA_OCRAM_ADDRESS0xffe0
> +#define GICD_BASE0xfffc1000
> +#define GICC_BASE0xfffc2000
> +
> +#endif /* _SOCFPGA_AGILEX_BASE_HARDWARE_H_ */
> 

All of these addresses are identical to the Stratix10, couldn't you just
use the Stratix10 and any diffs, you can just use fdt?

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

On 4/24/19 7:58 AM, Tom Rini wrote:
> On Wed, Apr 24, 2019 at 07:32:14AM -0500, Dinh Nguyen wrote:
>>
>>
>> On 4/23/19 5:02 PM, Tom Rini wrote:
>>> On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote:
>>>> Hi,
>>>>
>>>> This is V4 of the series to add a UCLASS_CACHE dm driver to handling
>>>> the configuration of cache settings. Place this new driver under
>>>> /drivers/cache. In this initial revision, the driver is only configuring
>>>> what I think are essential cache settings. The more comprehensive cache
>>>> settings can be done in the OS.
>>>>
>>>> Diffs from v4:
>>>> - Fix compile error found in sandbox_cache.c
>>>
>>> Thanks.  I'd greatly appreciate it if you can throw this whole series at
>>> travis (or just do a world build locally) and report back that
>>> everything is OK now.
>>>
>>
>> Will do. By a "world build", you mean using buildman for all
>> architectures right?
> 
> Yes.  buildman can fetch a valid toolchain for everything I think (and
> there's a documented location in .travis.yml for the maybe 1-2 that it
> doesn't) and then build everything.
> 

buildman just completed and it did not report any errors for this series
of patches.

Dinh



signature.asc
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

On 4/23/19 5:02 PM, Tom Rini wrote:
> On Tue, Apr 23, 2019 at 04:55:00PM -0500, Dinh Nguyen wrote:
>> Hi,
>>
>> This is V4 of the series to add a UCLASS_CACHE dm driver to handling
>> the configuration of cache settings. Place this new driver under
>> /drivers/cache. In this initial revision, the driver is only configuring
>> what I think are essential cache settings. The more comprehensive cache
>> settings can be done in the OS.
>>
>> Diffs from v4:
>> - Fix compile error found in sandbox_cache.c
> 
> Thanks.  I'd greatly appreciate it if you can throw this whole series at
> travis (or just do a world build locally) and report back that
> everything is OK now.
> 

Will do. By a "world build", you mean using buildman for all
architectures right?

Dinh



signature.asc
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv5 4/6] dm: cache: add the pl310 cache controller driver

[Dinh Nguyen]

Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v4: no change
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
 drivers/cache/Kconfig  |  9 +
 drivers/cache/Makefile |  1 +
 drivers/cache/cache-l2x0.c | 76 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/cache/cache-l2x0.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
  is usually located on the same chip. This uclass can be used for
  configuring settings that be found from a device tree file.
 
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+   /* Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (!dev_read_u32(dev, "prefetch-data", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (!dev_read_u32(dev, "prefetch-instr", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse_and_init(dev);
+
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_CACHE,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv5 6/6] configs: socfpga: add imply pl310 cache controller

[Dinh Nguyen]

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f58f8fb235..f5132d8174 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv5 3/6] dm: cache: Create a uclass for cache

[Dinh Nguyen]

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v5: fix compile error for sandbox_cache.c
v4: re-order includes and add Reviewed-by:
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
 drivers/Kconfig   |  2 ++
 drivers/Makefile  |  1 +
 drivers/cache/Kconfig | 16 +++
 drivers/cache/Makefile|  3 +++
 drivers/cache/cache-uclass.c  | 24 ++
 drivers/cache/sandbox_cache.c | 34 +++
 include/cache.h   | 38 +++
 include/dm/uclass-id.h|  1 +
 test/dm/cache.c   | 20 ++
 9 files changed, 139 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e6702eced4..96ff4f566a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache controllers"
+   depends on DM
+   help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->get_info)
+   return -ENOSYS;
+
+   return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+   .id = UCLASS_CACHE,
+   .name   = "cache",
+   .post_bind  = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..14cc6b0c0a
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+   info->base = 0x11223344;
+
+   return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+   .get_info   = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+   { .compatible = "sandbox,cache" },
+   { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+   .name   = "cache_sandbox",
+   .id = UCLASS_CACHE,
+   .of_match   = sandbox_cache_ids,
+   .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+   phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+   /**
+* get_info() - Get basic cache info
+*
+ 

[U-Boot] [PATCHv5 5/6] ARM: socfpga: use the pl310 driver to configure the cache

[Dinh Nguyen]

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x0, >pl310_tag_latency_ctrl);
-   writel(0x10, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv5 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

[Dinh Nguyen]

Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv5 1/6] Documentation: dts: Add pl310 cache controller dts documentation

[Dinh Nguyen]

Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt 
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as 
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various 
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 
cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells 
of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges :  Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+  controllers with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  O

[U-Boot] [PATCHv5 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

Hi,

This is V4 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.

Diffs from v4:
- Fix compile error found in sandbox_cache.c


Dinh Nguyen (6):
  Documentation: dts: Add pl310 cache controller dts documentation
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache
  dm: cache: add the pl310 cache controller driver
  ARM: socfpga: use the pl310 driver to configure the cache
  configs: socfpga: add imply pl310 cache controller

 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 arch/arm/Kconfig  |   1 +
 arch/arm/include/asm/pl310.h  |   3 +
 arch/arm/mach-socfpga/misc.c  |  16 +--
 drivers/Kconfig   |   2 +
 drivers/Makefile  |   1 +
 drivers/cache/Kconfig |  25 
 drivers/cache/Makefile|   4 +
 drivers/cache/cache-l2x0.c|  76 
 drivers/cache/cache-uclass.c  |  24 
 drivers/cache/sandbox_cache.c |  34 ++
 include/cache.h   |  38 ++
 include/dm/uclass-id.h|   1 +
 test/dm/cache.c   |  20 +++
 14 files changed, 346 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [U-Boot, PATCHv4, 3/6] dm: cache: Create a uclass for cache

[Dinh Nguyen]

On 4/22/19 12:48 PM, Tom Rini wrote:
> On Mon, Apr 01, 2019 at 05:32:17PM -0500, Dinh Nguyen wrote:
> 
>> The cache UCLASS will be used for configure settings that can be found
>> in a CPU's L2 cache controller.
>>
>> Add a uclass and a test for cache.
>>
>> Reviewed-by: Simon Glass 
>> Signed-off-by: Dinh Nguyen 
>> ---
>> v4: re-order includes and add Reviewed-by:
>> v3: Add cache_get_info() to check for non-zero value
>> Add comments to cache_info struct
>> v2: separate out uclass patch from driver and add test
> 
> NAK:
>sandbox:  +   tools-only
> +(tools-only) In file included from drivers/cache/sandbox_cache.c:6:0:
> +(tools-only) include/cache.h:13:2: error: unknown type name 'phys_addr_t'
> +(tools-only)   phys_addr_t base; /* Base physical address of cache device. */
> +(tools-only)   ^~~
> +(tools-only)   int (*get_info)(struct udevice *dev, struct cache_info *info);
> +(tools-only)  ^~~
> +(tools-only)  int cache_get_info(struct udevice *dev, struct cache_info 
> *info);
> +(tools-only)^~~
> +(tools-only)   .get_info = sandbox_get_info,
> +(tools-only)   ^~~~
> +(tools-only) drivers/cache/sandbox_cache.c:21:14: note: (near initialization 
> for 'sandbox_cach
> e_ops.get_info')
> +(tools-only) make[3]: *** [drivers/cache/sandbox_cache.o] Error 1
> +(tools-only) make[2]: *** [drivers/cache] Error 2
> +(tools-only) make[1]: *** [drivers] Error 2
> +(tools-only) make: *** [sub-make] Error 2
> w+(tools-only) include/cache.h:24:25: warning: 'struct udevice' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
> w+(tools-only) include/cache.h:36:27: warning: 'struct udevice' declared 
> inside parameter list will not be visible outside of this definition or 
> declaration
> w+(tools-only) drivers/cache/sandbox_cache.c:21:14: warning: initialization 
> from incompatible pointer type [-Wincompatible-pointer-types]
> 

I apologize for that! V5 is enroute and should be error free.

Dinh



signature.asc
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv4 5/6] ARM: socfpga: use the pl310 driver to configure the cache

[Dinh Nguyen]

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x0, >pl310_tag_latency_ctrl);
-   writel(0x10, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv4 4/6] dm: cache: add the pl310 cache controller driver

[Dinh Nguyen]

Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v4: no change
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
 drivers/cache/Kconfig  |  9 +
 drivers/cache/Makefile |  1 +
 drivers/cache/cache-l2x0.c | 76 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/cache/cache-l2x0.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
  is usually located on the same chip. This uclass can be used for
  configuring settings that be found from a device tree file.
 
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+   /* Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (!dev_read_u32(dev, "prefetch-data", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (!dev_read_u32(dev, "prefetch-instr", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse_and_init(dev);
+
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_CACHE,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv4 3/6] dm: cache: Create a uclass for cache

[Dinh Nguyen]

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v4: re-order includes and add Reviewed-by:
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
 drivers/Kconfig   |  2 ++
 drivers/Makefile  |  1 +
 drivers/cache/Kconfig | 16 +++
 drivers/cache/Makefile|  3 +++
 drivers/cache/cache-uclass.c  | 24 ++
 drivers/cache/sandbox_cache.c | 34 +++
 include/cache.h   | 38 +++
 include/dm/uclass-id.h|  1 +
 test/dm/cache.c   | 20 ++
 9 files changed, 139 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache controllers"
+   depends on DM
+   help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->get_info)
+   return -ENOSYS;
+
+   return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+   .id = UCLASS_CACHE,
+   .name   = "cache",
+   .post_bind  = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..fccd32f592
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+   info->base = 0x11223344;
+
+   return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+   .get_info   = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+   { .compatible = "sandbox,cache" },
+   { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+   .name   = "cache_sandbox",
+   .id = UCLASS_CACHE,
+   .of_match   = sandbox_cache_ids,
+   .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+   phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+   /**
+* get_info() - Get basic cache info
+*
+* @dev:Devi

[U-Boot] [PATCHv4 6/6] configs: socfpga: add imply pl310 cache controller

[Dinh Nguyen]

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80..f4c6262bb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv4 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

[Dinh Nguyen]

Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv4 1/6] Documentation: dts: Add pl310 cache controller dts documentation

[Dinh Nguyen]

Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt 
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as 
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various 
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 
cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells 
of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges :  Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+  controllers with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  O

[U-Boot] [PATCHv4 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

Hi,

This is V4 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.

Diffs from v3:
- Re-order includes in a correct order
- Add final Reviewed-by: in "dm: cache: Create a uclass for cache"

Dinh Nguyen (6):
  Documentation: dts: Add pl310 cache controller dts documentation
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache
  dm: cache: add the pl310 cache controller driver
  ARM: socfpga: use the pl310 driver to configure the cache
  configs: socfpga: add imply pl310 cache controller

 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 arch/arm/Kconfig  |   1 +
 arch/arm/include/asm/pl310.h  |   3 +
 arch/arm/mach-socfpga/misc.c  |  16 +--
 drivers/Kconfig   |   2 +
 drivers/Makefile  |   1 +
 drivers/cache/Kconfig |  25 
 drivers/cache/Makefile|   4 +
 drivers/cache/cache-l2x0.c|  76 
 drivers/cache/cache-uclass.c  |  24 
 drivers/cache/sandbox_cache.c |  34 ++
 include/cache.h   |  38 ++
 include/dm/uclass-id.h|   1 +
 test/dm/cache.c   |  20 +++
 14 files changed, 346 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv3 4/6] dm: cache: add the pl310 cache controller driver

[Dinh Nguyen]

Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
v3: Add Reviewed-by and fix nits
v2: split out patch and address comments from Simon Glass
---
 drivers/cache/Kconfig  |  9 +
 drivers/cache/Makefile |  1 +
 drivers/cache/cache-l2x0.c | 76 ++
 3 files changed, 86 insertions(+)
 create mode 100644 drivers/cache/cache-l2x0.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
  is usually located on the same chip. This uclass can be used for
  configuring settings that be found from a device tree file.
 
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..67c752d076
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+   /* Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (!dev_read_u32(dev, "prefetch-data", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (!dev_read_u32(dev, "prefetch-instr", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse_and_init(dev);
+
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_CACHE,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv3 5/6] ARM: socfpga: use the pl310 driver to configure the cache

[Dinh Nguyen]

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x0, >pl310_tag_latency_ctrl);
-   writel(0x10, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv3 3/6] dm: cache: Create a uclass for cache

[Dinh Nguyen]

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Signed-off-by: Dinh Nguyen 
---
v3: Add cache_get_info() to check for non-zero value
Add comments to cache_info struct
v2: separate out uclass patch from driver and add test
---
 drivers/Kconfig   |  2 ++
 drivers/Makefile  |  1 +
 drivers/cache/Kconfig | 16 +++
 drivers/cache/Makefile|  3 +++
 drivers/cache/cache-uclass.c  | 24 ++
 drivers/cache/sandbox_cache.c | 34 +++
 include/cache.h   | 38 +++
 include/dm/uclass-id.h|  1 +
 test/dm/cache.c   | 20 ++
 9 files changed, 139 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache controllers"
+   depends on DM
+   help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..97ce0249a4
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->get_info)
+   return -ENOSYS;
+
+   return ops->get_info(dev, info);
+}
+
+UCLASS_DRIVER(cache) = {
+   .id = UCLASS_CACHE,
+   .name   = "cache",
+   .post_bind  = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..b67ce31218
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+   info->base = 0;
+
+   return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+   .get_info   = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+   { .compatible = "sandbox,cache" },
+   { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+   .name   = "cache_sandbox",
+   .id = UCLASS_CACHE,
+   .of_match   = sandbox_cache_ids,
+   .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..c6334ca27f
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+   phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+   /**
+* get_info() - Get basic cache info
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @info:   Place to put info
+* @return 0 if OK, -

[U-Boot] [PATCHv3 6/6] configs: socfpga: add imply pl310 cache controller

[Dinh Nguyen]

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80..f4c6262bb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv3 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

[Dinh Nguyen]

Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut 
Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv3 1/6] Documentation: dts: Add pl310 cache controller dts documentation

[Dinh Nguyen]

Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Reviewed-by: Simon Glass 
Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt 
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as 
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various 
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 
cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells 
of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges :  Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+  controllers with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  O

[U-Boot] [PATCHv3 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

Hi,

This is V3 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.

Diffs from v2:
- Add cache_get_info() to check for non-zero value
- Add comments to cache_info struct
- Fix up nits from Simon Glass


Dinh Nguyen (6):
  Documentation: dts: Add pl310 cache controller dts documentation
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache
  dm: cache: add the pl310 cache controller driver
  ARM: socfpga: use the pl310 driver to configure the cache
  configs: socfpga: add imply pl310 cache controller

 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 arch/arm/Kconfig  |   1 +
 arch/arm/include/asm/pl310.h  |   3 +
 arch/arm/mach-socfpga/misc.c  |  16 +--
 drivers/Kconfig   |   2 +
 drivers/Makefile  |   1 +
 drivers/cache/Kconfig |  25 
 drivers/cache/Makefile|   4 +
 drivers/cache/cache-l2x0.c|  76 
 drivers/cache/cache-uclass.c  |  24 
 drivers/cache/sandbox_cache.c |  34 ++
 include/cache.h   |  38 ++
 include/dm/uclass-id.h|   1 +
 test/dm/cache.c   |  20 +++
 14 files changed, 346 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/2] ARM: socfpga: Pull PL310 clearing into common code

[Dinh Nguyen]

On 3/22/19 9:30 AM, Marek Vasut wrote:
> Pull the PL310 clearing code into common code, so it can be reused
> by Arria10.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dalon Westergreen 
> Cc: Dinh Nguyen 
> ---
>  arch/arm/mach-socfpga/include/mach/misc.h |  1 +
>  arch/arm/mach-socfpga/misc.c  | 54 +++
>  arch/arm/mach-socfpga/spl_gen5.c  | 54 ---
>  3 files changed, 55 insertions(+), 54 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
> b/arch/arm/mach-socfpga/include/mach/misc.h
> index 86d5d2b62b..876b850be2 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void);
>  #endif
>  
>  void do_bridge_reset(int enable);
> +void socfpga_pl310_clear(void);
>  
>  #endif /* _MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index ec8339e045..14337ff2d9 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -46,6 +46,60 @@ int dram_init(void)
>   return 0;
>  }
>  
> +void socfpga_pl310_clear(void)
> +{
> + u32 mask = 0xff, ena = 0;
> +
> + icache_enable();
> +
> + /* Disable the L2 cache */
> + clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
> +
> + writel(0x0, >pl310_tag_latency_ctrl);
> + writel(0x10, >pl310_data_latency_ctrl);
> +
> + /* enable BRESP, instruction and data prefetch, full line of zeroes */
> + setbits_le32(>pl310_aux_ctrl,
> +  L310_AUX_CTRL_DATA_PREFETCH_MASK |
> +  L310_AUX_CTRL_INST_PREFETCH_MASK |
> +  L310_SHARED_ATT_OVERRIDE_ENABLE);
> +

Do we need to enable these bits here? They get enabled again in
v7_outer_cache_enable().

Otherwise, feel free to add:

Reviewed-by: Dinh Nguyen 

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

[Dinh Nguyen]

On 3/13/19 6:54 AM, Ley Foon Tan wrote:
> On Wed, 2019-03-13 at 10:33 -0500, Dinh Nguyen wrote:
>>
>> On 3/13/19 9:32 AM, Dinh Nguyen wrote:
>>>
>>>
>>>
>>> On 3/13/19 12:59 AM, Ley Foon Tan wrote:
>>>>
>>>> On Wed, 2019-03-13 at 04:30 +0100, Marek Vasut wrote:
>>>>>
>>>>> On 3/13/19 4:03 AM, Ley Foon Tan wrote:
>>>>>>
>>>>>>
>>>>>> Syscon register is required in dts to select correct
>>>>>> PHY interface.
>>>>>>
>>>>>> Fix error below:
>>>>>>
>>>>>> Net:   Failed to get syscon: -2
>>>>>>
>>>>>> Signed-off-by: Ley Foon Tan 
>>>>> Is this fixed in mainline Linux too ?
>>>> Didn't see this in mainline Linux.
>>>>
>>>> Dinh, do you aware of this? I see sysmgr-syscon error in EMAC in
>>>> v4.20
>>>> kernel.
>>>>
>>>> [1.427994] socfpga-dwmac ff80.ethernet: Could not read
>>>> reg_offset from sysmgr-syscon!
>>>> [1.436241] socfpga-dwmac ff80.ethernet: Unable to parse
>>>> OF data
>>>> [1.442646] socfpga-dwmac: probe of ff80.ethernet failed
>>>> with
>>>> error -22
>> It looks like you're running downstream Linux. The failed to probe
>> message is only in the downstream Linux, not upstream Linux.
>>
>> Dinh
>>
> Yes, I am using downstream socfpga-4.20 branch. Upstream Linux can ping
> IP address successfully?
> 

I can even mount an NFS. Anyways, I'm sending out a patch shortly.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

[Dinh Nguyen]

On 3/13/19 9:32 AM, Dinh Nguyen wrote:
> 
> 
> On 3/13/19 12:59 AM, Ley Foon Tan wrote:
>> On Wed, 2019-03-13 at 04:30 +0100, Marek Vasut wrote:
>>> On 3/13/19 4:03 AM, Ley Foon Tan wrote:
>>>>
>>>> Syscon register is required in dts to select correct
>>>> PHY interface.
>>>>
>>>> Fix error below:
>>>>
>>>> Net:   Failed to get syscon: -2
>>>>
>>>> Signed-off-by: Ley Foon Tan 
>>> Is this fixed in mainline Linux too ?
>> Didn't see this in mainline Linux.
>>
>> Dinh, do you aware of this? I see sysmgr-syscon error in EMAC in v4.20
>> kernel.
>>
>> [1.427994] socfpga-dwmac ff80.ethernet: Could not read
>> reg_offset from sysmgr-syscon!
>> [1.436241] socfpga-dwmac ff80.ethernet: Unable to parse OF data
>> [1.442646] socfpga-dwmac: probe of ff80.ethernet failed with
>> error -22

It looks like you're running downstream Linux. The failed to probe
message is only in the downstream Linux, not upstream Linux.

Dinh

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Add missing altr, sysmgr-syscon for EMAC

[Dinh Nguyen]

On 3/13/19 12:59 AM, Ley Foon Tan wrote:
> On Wed, 2019-03-13 at 04:30 +0100, Marek Vasut wrote:
>> On 3/13/19 4:03 AM, Ley Foon Tan wrote:
>>>
>>> Syscon register is required in dts to select correct
>>> PHY interface.
>>>
>>> Fix error below:
>>>
>>> Net:   Failed to get syscon: -2
>>>
>>> Signed-off-by: Ley Foon Tan 
>> Is this fixed in mainline Linux too ?
> Didn't see this in mainline Linux.
> 
> Dinh, do you aware of this? I see sysmgr-syscon error in EMAC in v4.20
> kernel.
> 
> [1.427994] socfpga-dwmac ff80.ethernet: Could not read
> reg_offset from sysmgr-syscon!
> [1.436241] socfpga-dwmac ff80.ethernet: Unable to parse OF data
> [1.442646] socfpga-dwmac: probe of ff80.ethernet failed with
> error -22
> 
> 

I see this in mainline Linux:

[0.911521] socfpga-dwmac ff80.ethernet: PTP uses main clock
[0.917530] socfpga-dwmac ff80.ethernet: No sysmgr-syscon node found
[0.924209] socfpga-dwmac ff80.ethernet: Unable to parse OF data
[0.930944] stmmaceth ff80.ethernet: PTP uses main clock
[0.936723] stmmaceth ff80.ethernet: User ID: 0x11, Synopsys ID: 0x37
[0.943496] stmmaceth ff80.ethernet: DWMAC1000


It doesn't fail probing though. I'll look into it.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2 3/6] dm: cache: Create a uclass for cache

[Dinh Nguyen]

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Signed-off-by: Dinh Nguyen 
---
v2: separate out uclass patch from driver and add test
---
 drivers/Kconfig   |  2 ++
 drivers/Makefile  |  1 +
 drivers/cache/Kconfig | 16 
 drivers/cache/Makefile|  3 +++
 drivers/cache/cache-uclass.c  | 13 +
 drivers/cache/sandbox_cache.c | 34 ++
 include/cache.h   | 33 +
 include/dm/uclass-id.h|  1 +
 test/dm/cache.c   | 19 +++
 9 files changed, 122 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..8b7c9c7f9f
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,16 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache controllers"
+   depends on DM
+   help
+ Enable driver model for cache controllers that are found on
+ most CPU's. Cache is memory that the CPU can access directly and
+ is usually located on the same chip. This uclass can be used for
+ configuring settings that be found from a device tree file.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..2ba68060c1
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
new file mode 100644
index 00..dd72e3e00f
--- /dev/null
+++ b/drivers/cache/cache-uclass.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+
+UCLASS_DRIVER(cache) = {
+   .id = UCLASS_CACHE,
+   .name   = "cache",
+   .post_bind  = dm_scan_fdt_dev,
+};
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
new file mode 100644
index 00..b67ce31218
--- /dev/null
+++ b/drivers/cache/sandbox_cache.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+   info->base = 0;
+
+   return 0;
+}
+
+static const struct cache_ops sandbox_cache_ops = {
+   .get_info   = sandbox_get_info,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+   { .compatible = "sandbox,cache" },
+   { }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+   .name   = "cache_sandbox",
+   .id = UCLASS_CACHE,
+   .of_match   = sandbox_cache_ids,
+   .ops= _cache_ops,
+};
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 00..7a6faaf11c
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+struct cache_info {
+   phys_addr_t base;
+};
+
+struct cache_ops {
+   /**
+* get_info() - Get basic cache info
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @info:   Place to put info
+* @return 0 if OK, -ve on error
+*/
+   int (*get_info)(struct udevice *dev, struct cache_info *info);
+};
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @info:  Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index

[U-Boot] [PATCHv2 5/6] ARM: socfpga: use the pl310 driver to configure the cache

[Dinh Nguyen]

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x0, >pl310_tag_latency_ctrl);
-   writel(0x10, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2 4/6] dm: cache: add the pl310 cache controller driver

[Dinh Nguyen]

Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Signed-off-by: Dinh Nguyen 
---
v2: split out patch and address comments from Simon Glass
---
 drivers/cache/Kconfig  |  9 +
 drivers/cache/Makefile |  1 +
 drivers/cache/cache-l2x0.c | 75 ++
 3 files changed, 85 insertions(+)
 create mode 100644 drivers/cache/cache-l2x0.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 8b7c9c7f9f..24def7ac0f 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -13,4 +13,13 @@ config CACHE
  is usually located on the same chip. This uclass can be used for
  configuring settings that be found from a device tree file.
 
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 2ba68060c1..9deb961d91 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..a23a66c4a8
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+   /* Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (!dev_read_u32(dev, "prefetch-data", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (!dev_read_u32(dev, "prefetch-instr", )) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse(dev);
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_CACHE,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2 6/6] configs: socfpga: add imply pl310 cache controller

[Dinh Nguyen]

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80..f4c6262bb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2 1/6] Documentation: dts: Add pl310 cache controller dts documentation

[Dinh Nguyen]

Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Signed-off-by: Dinh Nguyen 
---
 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 1 file changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt 
b/Documentation/devicetree/bindings/arm/l2c2x0.txt
new file mode 100644
index 00..fbe6cb21f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as 
PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various 
implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+  "arm,pl310-cache"
+  "arm,l220-cache"
+  "arm,l210-cache"
+  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+  "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+  "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 
cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells 
of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges :  Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+  non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+  if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+  if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if 
non-zero,
+  disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+  0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+  controllers with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  On systems where this ma

[U-Boot] [PATCHv2 2/6] ARM: pl310: Add macro's for handling tag and data latency mask

[Dinh Nguyen]

Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut 
Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2 0/6] dm: cache: add dm cache driver

[Dinh Nguyen]

Hi,

This is V2 of the series to add a UCLASS_CACHE dm driver to handling
the configuration of cache settings. Place this new driver under
/drivers/cache. In this initial revision, the driver is only configuring
what I think are essential cache settings. The more comprehensive cache
settings can be done in the OS.

Diffs from v1:
- Add a DTS bindings document from Linux for the PL310.
- Split up the UCLASS_CACHE addition from the driver patches.
- Add a sandbox cache driver.
- Add a simple test in test/dm/cache.c
- Address comments from Simon Glass.
- Add Reviewed-by's from Marek Vasut.

Dinh Nguyen (6):
  Documentation: dts: Add pl310 cache controller dts documentation
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache
  dm: cache: add the pl310 cache controller driver
  ARM: socfpga: use the pl310 driver to configure the cache
  configs: socfpga: add imply pl310 cache controller

 .../devicetree/bindings/arm/l2c2x0.txt| 114 ++
 arch/arm/Kconfig  |   1 +
 arch/arm/include/asm/pl310.h  |   3 +
 arch/arm/mach-socfpga/misc.c  |  16 +--
 drivers/Kconfig   |   2 +
 drivers/Makefile  |   1 +
 drivers/cache/Kconfig |  25 
 drivers/cache/Makefile|   4 +
 drivers/cache/cache-l2x0.c|  75 
 drivers/cache/cache-uclass.c  |  13 ++
 drivers/cache/sandbox_cache.c |  34 ++
 include/cache.h   |  33 +
 include/dm/uclass-id.h|   1 +
 test/dm/cache.c   |  19 +++
 14 files changed, 328 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/l2c2x0.txt
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c
 create mode 100644 drivers/cache/sandbox_cache.c
 create mode 100644 include/cache.h
 create mode 100644 test/dm/cache.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 3/4] configs: socfpga: add imply pl310 cache controller

[Dinh Nguyen]

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f42eccef80..f4c6262bb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -845,6 +845,7 @@ config ARCH_SOCFPGA
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI_SUPPORT
+   imply L2X0_CACHE
 
 config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 4/4] ARM: socfpga: use the pl310 driver to configure the cache

[Dinh Nguyen]

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62b..34d8c4c51b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x111, >pl310_tag_latency_ctrl);
-   writel(0x121, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   if (uclass_get_device(UCLASS_CACHE, 0, ))
+   pr_err("cache controller driver NOT found!\n");
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 0/4] dm: cache: add dm cache driver

[Dinh Nguyen]

Hi,

Add a UCLASS_CACHE dm driver to handling the configuration of cache
settings. Place this new driver under /drivers/cache. In this initial
revision, the driver is only configuring what I think are essential cache
settings. The more comprehensive cache settings can be done in the OS.

Dinh

Dinh Nguyen (4):
  ARM: pl310: Add macro's for handling tag and data latency mask
  dm: cache: Create a uclass for cache controller
  configs: socfpga: add imply pl310 cache controller
  ARM: socfpga: use the pl310 driver to configure the cache

 arch/arm/Kconfig |  1 +
 arch/arm/include/asm/pl310.h |  3 ++
 arch/arm/mach-socfpga/misc.c | 16 ++-
 drivers/Kconfig  |  2 +
 drivers/Makefile |  1 +
 drivers/cache/Kconfig| 22 ++
 drivers/cache/Makefile   |  3 ++
 drivers/cache/cache-l2x0.c   | 82 
 drivers/cache/cache-uclass.c | 13 ++
 include/dm/uclass-id.h   |  1 +
 10 files changed, 131 insertions(+), 13 deletions(-)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 2/4] dm: cache: Create a uclass for cache controller

[Dinh Nguyen]

The cache controller driver configures the cache settings that can be
found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Signed-off-by: Dinh Nguyen 
---
 drivers/Kconfig  |  2 +
 drivers/Makefile |  1 +
 drivers/cache/Kconfig| 22 ++
 drivers/cache/Makefile   |  3 ++
 drivers/cache/cache-l2x0.c   | 82 
 drivers/cache/cache-uclass.c | 13 ++
 include/dm/uclass-id.h   |  1 +
 7 files changed, 124 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/cache-l2x0.c
 create mode 100644 drivers/cache/cache-uclass.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index f24351ac4f..842201b753 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/block/Kconfig"
 
 source "drivers/bootcount/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/clk/Kconfig"
 
 source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a7bba3ed56..0a00096332 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/
 obj-y += block/
 obj-y += board/
 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-y += cache/
 obj-$(CONFIG_CPU) += cpu/
 obj-y += crypto/
 obj-$(CONFIG_FASTBOOT) += fastboot/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 00..d6b2b6762a
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,22 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+   bool "Enable Driver Model for Cache drivers"
+   depends on DM
+   help
+ Enable driver model for cache controllers.
+
+config L2X0_CACHE
+   tristate "PL310 cache driver"
+   select CACHE
+   depends on ARM
+   help
+ This driver is for the PL310 cache controller commonly found on
+ ARMv7(32-bit) devices. The driver configures the cache settings
+ found in the device tree.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 00..fca37de0a8
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
new file mode 100644
index 00..cdd6ddb59b
--- /dev/null
+++ b/drivers/cache/cache-l2x0.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch;
+   int ret;
+   struct pl310_regs *regs = (struct pl310_regs *)devfdt_get_addr(dev);
+
+   /*Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (dev_read_u32(dev, "prefetch-data", ) == 0) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   }
+
+   if (dev_read_u32(dev, "prefetch-instr", ) == 0) {
+   if (prefetch)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   else
+   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+   }
+
+   saved_reg |= dev_read_bool(dev, "arm,shared-override");
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   if (dev_read_u32_array(dev, "arm,tag-latency", tag, 3) == 0)
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   if (dev_read_u32_array(dev, "arm,data-latency", tag, 3) == 0)
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_ofdata_to_platdata(struct udevice *dev)
+{
+   return 0;
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_pa

[U-Boot] [PATCHv1 1/4] ARM: pl310: Add macro's for handling tag and data latency mask

[Dinh Nguyen]

Add the PL310 macros for latency control setup, read and write bits.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

[Dinh Nguyen]

On 3/7/19 2:24 AM, Chee, Tien Fong wrote:
> On Tue, 2019-03-05 at 22:52 -0600, Dinh Nguyen wrote:
>>
>> On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> After some series of patches to maximise reusable of memory pool,
>>> here come
>>> to result of reasonable size required for whole SDMMC boot working
>>> on A10
>>> SoCDK. Size required come from default max cluster(0x1) +
>>> others(0x2000) + additional memory for headroom(0x3000).
>> This commit log is really confusing. What "series of patches"?
> There are few patches for optimization the vfat needed to result this
> calculation. For previous records, you can check from here [v7]: https:
> //www.mail-archive.com/u-boot@lists.denx.de/msg314511.html.

Ok. Please state these facts in the commit log. I have no idea what
"series of patches" you were referring to.

> 
>>  I think
>> you're just needing a bigger malloc pool. Can you just say that and
>> explain why you need it?
> I put this details because Marek asked this before, so i think others
> also intrested to know.
> 

That's fine! Just that the details wasn't very clear.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK

[Dinh Nguyen]

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Update the default configuration file to enable the necessary functionality
> the get the kit working.
> 
> Signed-off-by: Tien Fong Chee 
> 
> ---
> 
> changes for v8
> - Moved the FIT related configs to the patch of configuration for FPGA
>   SoCFPGA A10 SoCDK.
> 
> changes for v7
> - Keep minimal configs.
> ---
>  configs/socfpga_arria10_defconfig | 15 +--
>  1 file changed, 9 insertions(+), 6 deletions(-)

Why are there 2 patches touching socfpga_arria10_defconfig in this
series? Can you squash them into 1?

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

[Dinh Nguyen]

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> After some series of patches to maximise reusable of memory pool, here come
> to result of reasonable size required for whole SDMMC boot working on A10
> SoCDK. Size required come from default max cluster(0x1) +
> others(0x2000) + additional memory for headroom(0x3000).

This commit log is really confusing. What "series of patches"? I think
you're just needing a bigger malloc pool. Can you just say that and
explain why you need it?

Thanks,
Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 4/9] ARM: socfpga: Move the watchdog reset to the looping location

[Dinh Nguyen]

It looks like this patch was not in the previous 9 versions of this
series? Please try to not add new functionality to a series that is
already gone through so many reviews. It make reviewing the series
really confusing!

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Ensure the watchdog is reset timely if the looping is long.

How are you ensuring this?

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages

[Dinh Nguyen]

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Ensure the comment and debug messages are always consistent with the rest.

The rest of what? This patch seems unnecessary to me.

Dinh

> 
> Signed-off-by: Tien Fong Chee 
> ---
>  drivers/fpga/socfpga_arria10.c | 13 +++--
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 114dd910ab..b0abe1955c 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -94,7 +94,7 @@ int fpgamgr_wait_early_user_mode(void)
>   i++;
>   }
>  
> - debug("Additional %i sync word needed\n", i);
> + debug("FPGA: Additional %i sync word needed\n", i);
>  
>   /* restoring original CDRATIO */
>   fpgamgr_set_cd_ratio(cd_ratio);
> @@ -172,9 +172,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int 
> cfg_width, u32 *rbf_data,
>   compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
>   compress = !compress;
>  
> - debug("header word %d = %08x\n", 69, rbf_data[69]);
> - debug("header word %d = %08x\n", 229, rbf_data[229]);
> - debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, 
> compress);
> + debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
> + debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
> + debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
> +  compress);
>  
>   /*
>* from the register map description of cdratio in imgcfg_ctrl_02:
> @@ -455,10 +456,10 @@ int socfpga_load(Altera_desc *desc, const void 
> *rbf_data, size_t rbf_size)
>  {
>   int status;
>  
> - /* disable all signals from hps peripheral controller to fpga */
> + /* Disable all signals from hps peripheral controller to fpga */
>   writel(0, _manager_base->fpgaintf_en_global);
>  
> - /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> + /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
>   socfpga_bridges_reset();
>  
>   /* Initialize the FPGA Manager */
> 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK

[Dinh Nguyen]

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Update the default configuration file to enable the necessary functionality
> to get the SoCFPGA loadfs driver support. This would enable the
> implementation of programming bitstream into FPGA from MMC.
> 
> Signed-off-by: Tien Fong Chee 
> 
> ---
> 
> changes for v8
> - Added FIT related configs
> 
> changes for v7
> - Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE
> ---
>  configs/socfpga_arria10_defconfig | 8 
>  1 file changed, 8 insertions(+)

What changed in v9 - v11?

Also this patch doesn't apply to v2019.04-rc4 at all:

error: patch failed: configs/socfpga_arria10_defconfig:27
error: configs/socfpga_arria10_defconfig: patch does not apply
dinguyen@b13cycling:~/linux_dev/u-boot$ git apply --reject patch1.patch
Checking patch configs/socfpga_arria10_defconfig...
error: while searching for:
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_FS_FAT=y
CONFIG_FPGA_SOCFPGA=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y

error: patch failed: configs/socfpga_arria10_defconfig:27
Applying patch configs/socfpga_arria10_defconfig with 1 reject...
Rejected hunk #1.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCHv1 2/3] defconfig: socfpga_sockit_defconfig: enable L2X0_CACHE driver

[Dinh Nguyen]

On 3/5/19 1:20 PM, Marek Vasut wrote:
> On 3/5/19 8:03 PM, Dinh Nguyen wrote:
>> Enable CONFIG_MISC and CONFIG_L2X0_CACHE config options.
>>
>> Signed-off-by: Dinh Nguyen 
>> ---
>>  configs/socfpga_sockit_defconfig | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/configs/socfpga_sockit_defconfig 
>> b/configs/socfpga_sockit_defconfig
>> index 4c17d1a9e4..0009b0ebc3 100644
>> --- a/configs/socfpga_sockit_defconfig
>> +++ b/configs/socfpga_sockit_defconfig
>> @@ -47,6 +47,8 @@ CONFIG_DM_GPIO=y
>>  CONFIG_DWAPB_GPIO=y
>>  CONFIG_DM_I2C=y
>>  CONFIG_SYS_I2C_DW=y
>> +CONFIG_MISC=y
>> +CONFIG_L2X0_CACHE=y
>>  CONFIG_DM_MMC=y
>>  CONFIG_MMC_DW=y
>>  CONFIG_MTD_DEVICE=y
> 
> I think you can just add it as a default into arch/arm/socfpga/Kconfig
> with 'imply CONFIG_...' instead.
> 

Ah, yes...thanks. This would prevent the need make the same edits for
all the other socfpga_*_defconfigs.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCHv1 3/3] ARM: socfpga: let the pl310 driver configure the cache settings

[Dinh Nguyen]

On 3/5/19 1:20 PM, Marek Vasut wrote:
> On 3/5/19 8:03 PM, Dinh Nguyen wrote:
>> Load the PL310 L2 cache driver and allow it to setup the cache settings
>>
>> Signed-off-by: Dinh Nguyen 
>> ---
>>  arch/arm/mach-socfpga/misc.c | 15 ++-
>>  1 file changed, 2 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index fcf211d62b..fb0cfd3c1a 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -59,20 +59,9 @@ void enable_caches(void)
>>  #ifdef CONFIG_SYS_L2_PL310
>>  void v7_outer_cache_enable(void)
>>  {
>> -/* Disable the L2 cache */
>> -clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>> -
>> -writel(0x111, >pl310_tag_latency_ctrl);
>> -writel(0x121, >pl310_data_latency_ctrl);
>> -
>> -/* enable BRESP, instruction and data prefetch, full line of zeroes */
>> -setbits_le32(>pl310_aux_ctrl,
>> - L310_AUX_CTRL_DATA_PREFETCH_MASK |
>> - L310_AUX_CTRL_INST_PREFETCH_MASK |
>> - L310_SHARED_ATT_OVERRIDE_ENABLE);
>> +struct udevice *dev;
>>  
>> -/* Enable the L2 cache */
>> -setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>> +uclass_first_device(UCLASS_MISC, );
> 
> Error handling might help here
> 

Agreed..Just trying to solicit comments on whether this is the right
approach? Will add error handling..

Thanks for reviewing...
Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC PATCHv1 1/3] misc: pl310: add a misc driver for the pl310 cache controller

[Dinh Nguyen]

On 3/5/19 1:19 PM, Marek Vasut wrote:
> On 3/5/19 8:03 PM, Dinh Nguyen wrote:
>> The driver will read the cache properties from the device tree file and
>> set it up.
>>

>>  
>> +config L2X0_CACHE
>> +bool "L2x0 Cache support"
>> +depends on MISC
>> +help
>> +  Select this to enable a PL310 L2 Cache driver. The driver will
>> +  configure the L2 Cache settings found in the device tree.
> 
> I wonder whether we don't need some drivers/plat or drivers/soc for this ?

You mean for plat specific implementations?

> 
>>  config ALTERA_SYSID
>>  bool "Altera Sysid support"
>>  depends on MISC
>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>> index 6bdf5054f4..ea726f4668 100644
>> --- a/drivers/misc/Makefile
>> +++ b/drivers/misc/Makefile
>> @@ -23,6 +23,7 @@ obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
>>  endif
>>  endif
>>  obj-$(CONFIG_ALI152X) += ali512x.o
>> +obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
>>  obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
>>  obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
>>  obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
>> diff --git a/drivers/misc/cache-l2x0.c b/drivers/misc/cache-l2x0.c
>> new file mode 100644
>> index 00..b31598b1cd
>> --- /dev/null
>> +++ b/drivers/misc/cache-l2x0.c
>> @@ -0,0 +1,84 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2007 ARM Limited
> 
> 2007 ? :)

I think I can remove this. I started with the Linux's cache-l2x0, but
removed almost all of the code. Just a left-over artifact.


>> +
>> +saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
>> + L310_LATENCY_CTRL_WR(tag[1] - 1) |
>> + L310_LATENCY_CTRL_SETUP(tag[2] - 1);
>> +
>> +writel(saved_reg, >pl310_tag_latency_ctrl);
>> +
>> +saved_reg = readl(>pl310_data_latency_ctrl);
>> +dev_read_u32_array(dev, "arm,data-latency", tag, 3);
> 
> What happens if the array isn't present ?
> Should we _not_ configure the latencies in such case ?

Right, I have a to-do list that need to handle error conditions like this.

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[Dinh Nguyen]

Curious, you sent out 3 versions(2x v10, and v11) within ~2 hours. What
versions should we be reviewing?

On 3/5/19 10:23 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> This patch adds description on properties about file name used for both
> peripheral bitstream and core bitstream.
> 
> Signed-off-by: Tien Fong Chee 
> 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC PATCHv1 3/3] ARM: socfpga: let the pl310 driver configure the cache settings

[Dinh Nguyen]

Load the PL310 L2 cache driver and allow it to setup the cache settings

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 15 ++-
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62b..fb0cfd3c1a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,9 @@ void enable_caches(void)
 #ifdef CONFIG_SYS_L2_PL310
 void v7_outer_cache_enable(void)
 {
-   /* Disable the L2 cache */
-   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-
-   writel(0x111, >pl310_tag_latency_ctrl);
-   writel(0x121, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   struct udevice *dev;
 
-   /* Enable the L2 cache */
-   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+   uclass_first_device(UCLASS_MISC, );
 }
 
 void v7_outer_cache_disable(void)
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC PATCHv1 2/3] defconfig: socfpga_sockit_defconfig: enable L2X0_CACHE driver

[Dinh Nguyen]

Enable CONFIG_MISC and CONFIG_L2X0_CACHE config options.

Signed-off-by: Dinh Nguyen 
---
 configs/socfpga_sockit_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 4c17d1a9e4..0009b0ebc3 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -47,6 +47,8 @@ CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_L2X0_CACHE=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
 CONFIG_MTD_DEVICE=y
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC PATCHv1 1/3] misc: pl310: add a misc driver for the pl310 cache controller

[Dinh Nguyen]

The driver will read the cache properties from the device tree file and
set it up.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h |  3 ++
 drivers/misc/Kconfig |  7 +++
 drivers/misc/Makefile|  1 +
 drivers/misc/cache-l2x0.c| 84 
 4 files changed, 95 insertions(+)
 create mode 100644 drivers/misc/cache-l2x0.c

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..f69e9e45f8 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -18,6 +18,9 @@
 #define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
 
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d6e677fba8..c5c34b4dbb 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -13,6 +13,13 @@ config MISC
  set of generic read, write and ioctl methods may be used to
  access the device.
 
+config L2X0_CACHE
+   bool "L2x0 Cache support"
+   depends on MISC
+   help
+ Select this to enable a PL310 L2 Cache driver. The driver will
+ configure the L2 Cache settings found in the device tree.
+
 config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 6bdf5054f4..ea726f4668 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
 endif
 endif
 obj-$(CONFIG_ALI152X) += ali512x.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
 obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
diff --git a/drivers/misc/cache-l2x0.c b/drivers/misc/cache-l2x0.c
new file mode 100644
index 00..b31598b1cd
--- /dev/null
+++ b/drivers/misc/cache-l2x0.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2007 ARM Limited
+ *
+ * copied from Linux(arch/arm/mm/cache-l2x0.c
+ */
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static void l2c310_of_parse(struct udevice *dev)
+{
+   u32 tag[3] = { 0, 0, 0 };
+   u32 saved_reg, prefetch_i, prefetch_d;
+   bool shared_override;
+   struct pl310_regs *regs = (struct pl310_regs *)devfdt_get_addr(dev);
+
+   /*Disable the L2 Cache */
+   clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+
+   dev_read_u32(dev, "prefetch-data", _d);
+   dev_read_u32(dev, "prefetch-instr", _i);
+   shared_override = dev_read_bool(dev, "arm,shared-override");
+
+   saved_reg = readl(>pl310_aux_ctrl);
+   if (prefetch_d)
+   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+   if (prefetch_i)
+   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+   if (shared_override)
+   saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
+
+   writel(saved_reg, >pl310_aux_ctrl);
+
+   saved_reg = readl(>pl310_tag_latency_ctrl);
+   dev_read_u32_array(dev, "arm,tag-latency", tag, 3);
+
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+
+   writel(saved_reg, >pl310_tag_latency_ctrl);
+
+   saved_reg = readl(>pl310_data_latency_ctrl);
+   dev_read_u32_array(dev, "arm,data-latency", tag, 3);
+
+   saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+L310_LATENCY_CTRL_WR(tag[1] - 1) |
+L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+
+   writel(saved_reg, >pl310_data_latency_ctrl);
+
+   /* Enable the L2 cache */
+   setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_ofdata_to_platdata(struct udevice *dev)
+{
+   return 0;
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+   l2c310_of_parse(dev);
+   return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+   { .compatible = "arm,pl310-cache" },
+   {}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+   .name   = "pl310_cache",
+   .id = UCLASS_MISC,
+   .of_match = l2x0_ids,
+   .probe  = l2x0_probe,
+   .ofdata_to_platdata = l2x0_ofdata_to_platdata,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC PATCHv1 0/3] misc: pl310: add a dm cache driver

[Dinh Nguyen]

Hello,

I'm soliciting comments of this patchset. The patchset adds a driver
for the cache controller(specifically the PL310). This cache controller
can be found on many ARMv7 SoCs. I don't think it's used on ARMv8
platforms.

This driver will retrieve the cache properties from the board DTS files
and set the corresponding bits in cache controller.

I think we can do something similar without make this driver and placing
the file in /arch/arm/cpu/armv7, but wanted to get feedback.

To-dos:
- Add error checking
- Add more cache properties

Thanks,

Dinh Nguyen (3):
  misc: pl310: add a misc driver for the pl310 cache controller
  defconfig: socfpga_sockit_defconfig: enable L2X0_CACHE driver
  ARM: socfpga: let the pl310 driver configure the cache settings

 arch/arm/include/asm/pl310.h |  3 ++
 arch/arm/mach-socfpga/misc.c | 15 +-
 configs/socfpga_sockit_defconfig |  2 +
 drivers/misc/Kconfig |  7 +++
 drivers/misc/Makefile|  1 +
 drivers/misc/cache-l2x0.c| 84 
 6 files changed, 99 insertions(+), 13 deletions(-)
 create mode 100644 drivers/misc/cache-l2x0.c

-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv2] ARM: socfpga: fix data and tag latency values for pl310 cache controller

[Dinh Nguyen]

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/mach-socfpga/misc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62b..ec8339e045 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,8 +62,8 @@ void v7_outer_cache_enable(void)
/* Disable the L2 cache */
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 
-   writel(0x111, >pl310_tag_latency_ctrl);
-   writel(0x121, >pl310_data_latency_ctrl);
+   writel(0x0, >pl310_tag_latency_ctrl);
+   writel(0x10, >pl310_data_latency_ctrl);
 
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(>pl310_aux_ctrl,
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] ARM: socfpga: configure pl310 from dts

[Dinh Nguyen]

Read the cache properties of the L2 cache controller from the device
tree and configure it.

Signed-off-by: Dinh Nguyen 
---
 arch/arm/include/asm/pl310.h |  4 
 arch/arm/mach-socfpga/misc.c | 45 +---
 2 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index b83978b1cc..346dbe476d 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -19,6 +19,10 @@
 #define L310_AUX_CTRL_DATA_PREFETCH_MASK   (1 << 28)
 #define L310_AUX_CTRL_INST_PREFETCH_MASK   (1 << 29)
 
+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)((n) << 8)
+
 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
 #define L2X0_CACHE_ID_PART_L310 (3 << 6)
 #define L2X0_CACHE_ID_RTL_MASK  0x3f
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62b..b53f22e621 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -57,19 +57,48 @@ void enable_caches(void)
 }
 
 #ifdef CONFIG_SYS_L2_PL310
+static void setup_cache_latency(void)
+{
+   const void *blob = gd->fdt_blob;
+   int node;
+   u32 latency;
+   u32 data[3];
+
+   /* find the l2-cache node */
+   node = fdt_node_offset_by_compatible(blob, -1, "arm,pl310-cache");
+
+   fdtdec_get_int_array(blob, node, "arm,tag-latency", data, 3);
+   latency = L310_LATENCY_CTRL_RD(data[0] - 1) |
+ L310_LATENCY_CTRL_WR(data[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(data[2] - 1);
+
+   writel(latency, >pl310_tag_latency_ctrl);
+
+   fdtdec_get_int_array(blob, node, "arm,data-latency", data, 3);
+   latency = L310_LATENCY_CTRL_RD(data[0] - 1) |
+ L310_LATENCY_CTRL_WR(data[1] - 1) |
+ L310_LATENCY_CTRL_SETUP(data[2] - 1);
+   writel(latency, >pl310_data_latency_ctrl);
+
+   if (fdtdec_get_bool(blob, node, "arm,shared-override"))
+   setbits_le32(>pl310_aux_ctrl,
+L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+   if (fdtdec_get_config_int(blob, "prefetch-data", 1))
+   setbits_le32(>pl310_aux_ctrl,
+L310_AUX_CTRL_DATA_PREFETCH_MASK);
+
+   if (fdtdec_get_config_int(blob, "prefetch-instr", 1))
+   setbits_le32(>pl310_aux_ctrl,
+L310_AUX_CTRL_INST_PREFETCH_MASK);
+}
+
 void v7_outer_cache_enable(void)
 {
/* Disable the L2 cache */
clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
 
-   writel(0x111, >pl310_tag_latency_ctrl);
-   writel(0x121, >pl310_data_latency_ctrl);
-
-   /* enable BRESP, instruction and data prefetch, full line of zeroes */
-   setbits_le32(>pl310_aux_ctrl,
-L310_AUX_CTRL_DATA_PREFETCH_MASK |
-L310_AUX_CTRL_INST_PREFETCH_MASK |
-L310_SHARED_ATT_OVERRIDE_ENABLE);
+   setup_cache_latency();
 
/* Enable the L2 cache */
setbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
-- 
2.20.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

[Dinh Nguyen]

On 3/1/19 10:09 AM, Marek Vasut wrote:
> On 3/1/19 4:19 PM, Dinh Nguyen wrote:
>>
>>
>> On 3/1/19 3:40 AM, Marek Vasut wrote:
>>> On 3/1/19 12:59 AM, Dinh Nguyen wrote:
>>>> Hi Marek,
>>>>
>>>> On 2/19/19 4:01 AM, Simon Goldschmidt wrote:
>>>>> On Tue, Feb 19, 2019 at 1:44 AM Marek Vasut  wrote:
>>>>>>
>>>>>> Configure the PL310 tag and data latency registers, which slightly
>>>>>> improves performance and aligns the behavior with Linux.
>>>>>>
>>>>>> Signed-off-by: Marek Vasut 
>>>>>> Cc: Dalon Westergreen 
>>>>>> Cc: Dinh Nguyen 
>>>>>> ---
>>>>>>  arch/arm/mach-socfpga/misc.c | 3 +++
>>>>>>  1 file changed, 3 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>>>>>> index 78fbe28724..1ea4e32c11 100644
>>>>>> --- a/arch/arm/mach-socfpga/misc.c
>>>>>> +++ b/arch/arm/mach-socfpga/misc.c
>>>>>> @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
>>>>>> /* Disable the L2 cache */
>>>>>> clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>>>>>>
>>>>>> +   writel(0x111, >pl310_tag_latency_ctrl);
>>>>>> +   writel(0x121, >pl310_data_latency_ctrl);
>>>>>
>>>>> Would it make sense to add defines as named constants for this?
>>>>> OTOH, in Linux, the values in the devicetree aren't really described,
>>>>> either, so:
>>>>
>>>> I was thinking the same, so I'm working on a patch to get these values
>>>> from the device tree.
>>>>
>>>> So while I was doing that, I realized that this patch is wrong.
>>>>
>>>> The patch should be like this:
>>>>
>>>>writel(0x0, >pl310_tag_latency_ctrl);
>>>>writel(0x010, >pl310_data_latency_ctrl);
>>>>
>>>> The reason is for the latency values:
>>>>
>>>> 000 = 1 cycle of latency, there is no additional latency.
>>>> 001 = 2 cycles of latency.
>>>> 010 = 3 cycles of latency.
>>>> 011 = 4 cycles of latency.
>>>> 100 = 5 cycles of latency.
>>>> 101 = 6 cycles of latency.
>>>> 110 = 7 cycles of latency.
>>>> 111 = 8 cycles of latency.
>>>>
>>>> So from the values in the device tree, they should be n-1.
>>>>
>>>> It looks like you've already sent the patch to Tom. I'll send a follow
>>>> up patch to fix that when it lands.
>>>
>>> Drat, thanks.
>>>
>>> Better yet, pull the latency config into a function, so it can be used
>>> by other platforms. The prototype should take 7 parameters, address and
>>> latency in cycles, so that it shields the users from this n-1 stuff.
>>>
>>
>> Agreed. I'm working on an RFC patch that creates a UBOOT_MISC driver to
>> handle all of the pl310 settings. Hope to send it out sometime next week.
> 
> I'd like a simpler fix for this release if possible, and a subsequent
> patch for the DM conversion.
> 

ok..

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

[Dinh Nguyen]

On 3/1/19 3:40 AM, Marek Vasut wrote:
> On 3/1/19 12:59 AM, Dinh Nguyen wrote:
>> Hi Marek,
>>
>> On 2/19/19 4:01 AM, Simon Goldschmidt wrote:
>>> On Tue, Feb 19, 2019 at 1:44 AM Marek Vasut  wrote:
>>>>
>>>> Configure the PL310 tag and data latency registers, which slightly
>>>> improves performance and aligns the behavior with Linux.
>>>>
>>>> Signed-off-by: Marek Vasut 
>>>> Cc: Dalon Westergreen 
>>>> Cc: Dinh Nguyen 
>>>> ---
>>>>  arch/arm/mach-socfpga/misc.c | 3 +++
>>>>  1 file changed, 3 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>>>> index 78fbe28724..1ea4e32c11 100644
>>>> --- a/arch/arm/mach-socfpga/misc.c
>>>> +++ b/arch/arm/mach-socfpga/misc.c
>>>> @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
>>>> /* Disable the L2 cache */
>>>> clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>>>>
>>>> +   writel(0x111, >pl310_tag_latency_ctrl);
>>>> +   writel(0x121, >pl310_data_latency_ctrl);
>>>
>>> Would it make sense to add defines as named constants for this?
>>> OTOH, in Linux, the values in the devicetree aren't really described,
>>> either, so:
>>
>> I was thinking the same, so I'm working on a patch to get these values
>> from the device tree.
>>
>> So while I was doing that, I realized that this patch is wrong.
>>
>> The patch should be like this:
>>
>>  writel(0x0, >pl310_tag_latency_ctrl);
>>  writel(0x010, >pl310_data_latency_ctrl);
>>
>> The reason is for the latency values:
>>
>> 000 = 1 cycle of latency, there is no additional latency.
>> 001 = 2 cycles of latency.
>> 010 = 3 cycles of latency.
>> 011 = 4 cycles of latency.
>> 100 = 5 cycles of latency.
>> 101 = 6 cycles of latency.
>> 110 = 7 cycles of latency.
>> 111 = 8 cycles of latency.
>>
>> So from the values in the device tree, they should be n-1.
>>
>> It looks like you've already sent the patch to Tom. I'll send a follow
>> up patch to fix that when it lands.
> 
> Drat, thanks.
> 
> Better yet, pull the latency config into a function, so it can be used
> by other platforms. The prototype should take 7 parameters, address and
> latency in cycles, so that it shields the users from this n-1 stuff.
> 

Agreed. I'm working on an RFC patch that creates a UBOOT_MISC driver to
handle all of the pl310 settings. Hope to send it out sometime next week.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

[Dinh Nguyen]

Hi Marek,

On 2/19/19 4:01 AM, Simon Goldschmidt wrote:
> On Tue, Feb 19, 2019 at 1:44 AM Marek Vasut  wrote:
>>
>> Configure the PL310 tag and data latency registers, which slightly
>> improves performance and aligns the behavior with Linux.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Dalon Westergreen 
>> Cc: Dinh Nguyen 
>> ---
>>  arch/arm/mach-socfpga/misc.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>> index 78fbe28724..1ea4e32c11 100644
>> --- a/arch/arm/mach-socfpga/misc.c
>> +++ b/arch/arm/mach-socfpga/misc.c
>> @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
>> /* Disable the L2 cache */
>> clrbits_le32(>pl310_ctrl, L2X0_CTRL_EN);
>>
>> +   writel(0x111, >pl310_tag_latency_ctrl);
>> +   writel(0x121, >pl310_data_latency_ctrl);
> 
> Would it make sense to add defines as named constants for this?
> OTOH, in Linux, the values in the devicetree aren't really described,
> either, so:

I was thinking the same, so I'm working on a patch to get these values
from the device tree.

So while I was doing that, I realized that this patch is wrong.

The patch should be like this:

writel(0x0, >pl310_tag_latency_ctrl);
writel(0x010, >pl310_data_latency_ctrl);

The reason is for the latency values:

000 = 1 cycle of latency, there is no additional latency.
001 = 2 cycles of latency.
010 = 3 cycles of latency.
011 = 4 cycles of latency.
100 = 5 cycles of latency.
101 = 6 cycles of latency.
110 = 7 cycles of latency.
111 = 8 cycles of latency.

So from the values in the device tree, they should be n-1.

It looks like you've already sent the patch to Tom. I'll send a follow
up patch to fix that when it lands.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: cache: Fix incorrect bitwise operation

[Dinh Nguyen]

On 2/18/19 6:43 PM, Marek Vasut wrote:
> The loop implemented in the code is supposed to check whether the
> PL310 operation register has any bit from the mask set. Currently,
> the code checks whether the PL310 operation register has any bit
> set AND whether the mask is non-zero, which is incorrect. Fix the
> conditional.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dalon Westergreen 
> Cc: Dinh Nguyen 
> Cc: Tom Rini 
> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
> ---
>  arch/arm/lib/cache-pl310.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
> index 1296ba6efd..bb4157 100644
> --- a/arch/arm/lib/cache-pl310.c
> +++ b/arch/arm/lib/cache-pl310.c
> @@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg)
>   /* Invalidate all ways */
>   writel(way_mask, op_reg);
>   /* Wait for all ways to be invalidated */
> - while (readl(op_reg) && way_mask)
> + while (readl(op_reg) & way_mask)
>   ;
>   pl310_cache_sync();
>  }
> 

Thanks for fixing this!

Reviewed-by: Dinh Nguyen 

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: socfpga: Configure PL310 latencies

[Dinh Nguyen]

On 2/18/19 6:44 PM, Marek Vasut wrote:
> Configure the PL310 tag and data latency registers, which slightly
> improves performance and aligns the behavior with Linux.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dalon Westergreen 
> Cc: Dinh Nguyen 
> ---
>  arch/arm/mach-socfpga/misc.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

Looks good!

Reviewed-by: Dinh Nguyen 


___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM

[Dinh Nguyen]

Hi Marek,

On 2/9/19 4:01 AM, Marek Vasut wrote:
> On 2/7/19 10:23 PM, Simon Goldschmidt wrote:
>> To clean up reset handling for socfpga gen5, let's move the code snippet
>> taking the DDR controller out of reset from SPL to the DDR driver.
>>
>> While at it, port the ddr driver to UCLASS_RAM and use dts.
>>
>> Signed-off-by: Simon Goldschmidt 
>> ---
>>
>> This is an RFC to show what the SDRAM driver moved to DM (UCLASS_RAM) would
>> look like. It's RFC both because Dinh did not seem too fond of changing the
>> register address of the SDR in devicetree to include what the undocumented
>> registers 'sequencer.c' uses as well as because of my observed code growth.
> 
> Dinh, if the SDRAM controller spans some addresses, it should be
> described like so in the DT. Whether those registers are documented or
> not does not matter, DT is a hardware description and should describe
> hardware accurately.

Yes, I agree with above statement. I'll wait for this patch to land here
and will take the DTS patch to sync up Linux and U-Boot DTS.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 1/4] arm: socfpga: imply SPL config instead of select

[Dinh Nguyen]

On 1/14/19 10:05 AM, Simon Goldschmidt wrote:
> Hi Dinh,
> 
> Am 14.01.2019 um 16:58 schrieb Dinh Nguyen:
>> Hi Simon,
>>
>> On 1/14/19 9:50 AM, Simon Goldschmidt wrote:
>>> Am 11.01.2019 um 23:02 schrieb Marek Vasut:
>>>> On 1/11/19 9:39 PM, Simon Goldschmidt wrote:
>>>>> Am 07.01.2019 um 23:53 schrieb Marek Vasut:
>>>>>> On 1/7/19 10:14 PM, Simon Goldschmidt wrote:
>>>>>>> In order to build a smaller SPL, let's imply SPL_DM_RESET and
>>>>>>> SPL_WATCHDOG_SUPPORT instead of selecting them, so they can be
>>>>>>> disabled
>>>>>>> via defconfig.
>>>>>>>
>>>>>>> This also seems to be required to use OF_PLATDATA, as the reset
>>>>>>> drivers
>>>>>>> don't seem to work with it.
>>>>>>
>>>>>> How do you un-reset IP blocks if you disable the reset controller ?
>>>>>
>>>>> I found that out just now: there's the function
>>>>> 'reset_deassert_peripherals_handoff()' in spl_gen5.c that should
>>>>> "De-assert reset for peripherals and bridges based on handoff".
>>>>> However,
>>>>> at least for Gen5, it just writes a 0 to rstmgr->permodrst. By doing
>>>>> that, it enables *ALL* peripherals on the SoC (except for some DMA
>>>>> channels that aren't really used) :-)
>>>>>
>>>>> I guess that needs some cleaning up as well ;-)
>>>>
>>>> Yes
>>>>
>>>>> I think the proper thing to do here would be to remove this
>>>>> function and
>>>>> convert all drivers to provide appropriate 'resets' properties in the
>>>>> dts?
>>>>
>>>> Indeed
>>>
>>> So I just did that and it works nice for SPL and U-Boot: By adding some
>>> "resets" properties the the main dtsi and adding reset bulk code to the
>>> cadence_qspi, denali_dt nand and drivers, I can nearly remove the reset
>>> code from arch/mach_socfpga.
>>>
>>> The problem would be that now Linux cannot use peripherals that aren't
>>> enabled by U-Boot because it relies on them being enabled. How are such
>>> dependencies solved? Because even if I would add reset support in the
>>> corresponding Linux drivers, we probably could not bootolder Kernels
>>> (e.g. the Debian 9 kernel - v4.9.x) with a new U-Boot...
>>>
>>
>> I added an early reset driver for SoCFPGA that should take care of this.
>> The patch is in v5.0-rc2[1].
> 
> OK, it's good to know that this work is already done, I haven't
> monitored this close enough.
> 
> But am I correct that my above problem remains even in v5.0 as not all
> peripherals in socfpga.dtsi have a "resets" property set (e.g. mmc and
> qspi) and would thuse not be taken out of reset by Linux?
> 

Yes, I see that. I will send a patch for those.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 1/4] arm: socfpga: imply SPL config instead of select

[Dinh Nguyen]

Hi Simon,

On 1/14/19 9:50 AM, Simon Goldschmidt wrote:
> Am 11.01.2019 um 23:02 schrieb Marek Vasut:
>> On 1/11/19 9:39 PM, Simon Goldschmidt wrote:
>>> Am 07.01.2019 um 23:53 schrieb Marek Vasut:
 On 1/7/19 10:14 PM, Simon Goldschmidt wrote:
> In order to build a smaller SPL, let's imply SPL_DM_RESET and
> SPL_WATCHDOG_SUPPORT instead of selecting them, so they can be
> disabled
> via defconfig.
>
> This also seems to be required to use OF_PLATDATA, as the reset
> drivers
> don't seem to work with it.

 How do you un-reset IP blocks if you disable the reset controller ?
>>>
>>> I found that out just now: there's the function
>>> 'reset_deassert_peripherals_handoff()' in spl_gen5.c that should
>>> "De-assert reset for peripherals and bridges based on handoff". However,
>>> at least for Gen5, it just writes a 0 to rstmgr->permodrst. By doing
>>> that, it enables *ALL* peripherals on the SoC (except for some DMA
>>> channels that aren't really used) :-)
>>>
>>> I guess that needs some cleaning up as well ;-)
>>
>> Yes
>>
>>> I think the proper thing to do here would be to remove this function and
>>> convert all drivers to provide appropriate 'resets' properties in the
>>> dts?
>>
>> Indeed
> 
> So I just did that and it works nice for SPL and U-Boot: By adding some
> "resets" properties the the main dtsi and adding reset bulk code to the
> cadence_qspi, denali_dt nand and drivers, I can nearly remove the reset
> code from arch/mach_socfpga.
> 
> The problem would be that now Linux cannot use peripherals that aren't
> enabled by U-Boot because it relies on them being enabled. How are such
> dependencies solved? Because even if I would add reset support in the
> corresponding Linux drivers, we probably could not bootolder Kernels
> (e.g. the Debian 9 kernel - v4.9.x) with a new U-Boot...
> 

I added an early reset driver for SoCFPGA that should take care of this.
The patch is in v5.0-rc2[1].

Dinh

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/reset?id=b3ca9888f35fa6919569cf27c929dc0ac49e9716
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] net: phy: add TSE PCS support to dwmac-socfpga

[Dinh Nguyen]

On 09/25/2018 10:00 AM, Dinh Nguyen wrote:
> 
> 
> On 09/25/2018 01:24 AM, Ooi, Joyce wrote:
>> This adds support for TSE PCS that uses SGMII adapter when the
>> phy-mode in device tree is set to sgmii.
> 
> Can you add a bit more description to your commit message? TSE(Triple
> Speed Ethernet), but what is PCS?
> 
>>
>> Signed-off-by: Ooi, Joyce 
>> ---
>>  drivers/net/Makefile   |   3 +-
>>  drivers/net/designware.c   |   5 ++
>>  drivers/net/designware.h   |   1 +
>>  drivers/net/dwmac_socfpga.c| 121 +
>>  drivers/net/phy/altr_tse_pcs.c | 197 
>> +
>>  drivers/net/phy/altr_tse_pcs.h |  59 
>>  6 files changed, 385 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/net/phy/altr_tse_pcs.c
>>  create mode 100644 drivers/net/phy/altr_tse_pcs.h
>>
>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
>> index 48a2878..c2333b5 100644
>> --- a/drivers/net/Makefile
>> +++ b/drivers/net/Makefile
>> @@ -14,7 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
>>  obj-$(CONFIG_CS8900) += cs8900.o
>>  obj-$(CONFIG_TULIP) += dc2114x.o
>>  obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
>> -obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
>> +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac-socfpga.o
> 
> Huh? What's this change for?
> 
> Also, I'm getting these compile errors against the latest U-Boot, top
> commit = "284b27cf81da10d55 Merge branch 'master' of
> git://git.denx.de/u-boot-mips"   :
> 
> drivers/net/dwmac_socfpga.c: In function ‘socfpga_dw_tse_pcs_init’:
> drivers/net/dwmac_socfpga.c:67:9: warning: implicit declaration of
> function ‘mbox_get_fpga_config_status’ [-Wimplicit-function-declaration]
>ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
>  ^~~
>   LD  common/built-in.o
>   LD  drivers/net/dwmac-socfpga.o
>   LD  drivers/net/built-in.o
>   LD  cmd/built-in.o
>   CC  lib/smbios.o
>   CC  lib/display_options.o
>   CC  lib/efi_loader/efi_reloc.o
>   CC  lib/efi_loader/helloworld.o
>   LD  lib/efi_loader/helloworld_efi.so
>   OBJCOPY lib/efi_loader/helloworld.efi
> rm lib/efi_loader/helloworld_efi.so lib/efi_loader/helloworld.o
>   LD  lib/built-in.o
>   LD  u-boot
> drivers/net/built-in.o: In function `dwmac_socfpga_ofdata_to_platdata':
> /home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:170:
> undefined reference to `syscon_node_to_regmap'
> /home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:177:
> undefined reference to `regmap_get_range'
> drivers/net/built-in.o: In function `socfpga_dw_tse_pcs_init':
> /home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:67:
> undefined reference to `mbox_get_fpga_config_status'
> 
> 
> In the future, please test before submitting patches.
> 

For the arria10 defconfig, I get the following compile error:

drivers/net/dwmac_socfpga.c: In function ‘socfpga_dw_tse_pcs_init’:
drivers/net/dwmac_socfpga.c:67:9: warning: implicit declaration of
function ‘mbox_get_fpga_config_status’ [-Wimplicit-function-declaration]
   ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
 ^~~
drivers/net/dwmac_socfpga.c:74:3: error: too many arguments to function
‘socfpga_bridges_reset’
   socfpga_bridges_reset(1);
   ^
In file included from ./arch/arm/include/asm/arch/reset_manager.h:44:0,
 from drivers/net/dwmac_socfpga.c:21:
./arch/arm/include/asm/arch/reset_manager_arria10.h:15:5: note: declared
here
 int socfpga_bridges_reset(void);

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] net: phy: add TSE PCS support to dwmac-socfpga

[Dinh Nguyen]

On 09/25/2018 01:24 AM, Ooi, Joyce wrote:
> This adds support for TSE PCS that uses SGMII adapter when the
> phy-mode in device tree is set to sgmii.

Can you add a bit more description to your commit message? TSE(Triple
Speed Ethernet), but what is PCS?

> 
> Signed-off-by: Ooi, Joyce 
> ---
>  drivers/net/Makefile   |   3 +-
>  drivers/net/designware.c   |   5 ++
>  drivers/net/designware.h   |   1 +
>  drivers/net/dwmac_socfpga.c| 121 +
>  drivers/net/phy/altr_tse_pcs.c | 197 
> +
>  drivers/net/phy/altr_tse_pcs.h |  59 
>  6 files changed, 385 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/net/phy/altr_tse_pcs.c
>  create mode 100644 drivers/net/phy/altr_tse_pcs.h
> 
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 48a2878..c2333b5 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -14,7 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
>  obj-$(CONFIG_CS8900) += cs8900.o
>  obj-$(CONFIG_TULIP) += dc2114x.o
>  obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
> -obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
> +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac-socfpga.o

Huh? What's this change for?

Also, I'm getting these compile errors against the latest U-Boot, top
commit = "284b27cf81da10d55 Merge branch 'master' of
git://git.denx.de/u-boot-mips"   :

drivers/net/dwmac_socfpga.c: In function ‘socfpga_dw_tse_pcs_init’:
drivers/net/dwmac_socfpga.c:67:9: warning: implicit declaration of
function ‘mbox_get_fpga_config_status’ [-Wimplicit-function-declaration]
   ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
 ^~~
  LD  common/built-in.o
  LD  drivers/net/dwmac-socfpga.o
  LD  drivers/net/built-in.o
  LD  cmd/built-in.o
  CC  lib/smbios.o
  CC  lib/display_options.o
  CC  lib/efi_loader/efi_reloc.o
  CC  lib/efi_loader/helloworld.o
  LD  lib/efi_loader/helloworld_efi.so
  OBJCOPY lib/efi_loader/helloworld.efi
rm lib/efi_loader/helloworld_efi.so lib/efi_loader/helloworld.o
  LD  lib/built-in.o
  LD  u-boot
drivers/net/built-in.o: In function `dwmac_socfpga_ofdata_to_platdata':
/home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:170:
undefined reference to `syscon_node_to_regmap'
/home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:177:
undefined reference to `regmap_get_range'
drivers/net/built-in.o: In function `socfpga_dw_tse_pcs_init':
/home/dinguyen/linux_dev/u-boot/drivers/net/dwmac_socfpga.c:67:
undefined reference to `mbox_get_fpga_config_status'


In the future, please test before submitting patches.

Thanks,
Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 5/5] arm: dts: socfpga: stratix10: update pdma

[Dinh Nguyen]

On 07/10/2018 08:11 AM, Chee, Tien Fong wrote:
> On Mon, 2018-07-09 at 22:28 +0200, Marek Vasut wrote:
>> On 07/09/2018 08:03 PM, Dinh Nguyen wrote:
>>>
>>>
>>>
>>> On 05/31/2018 03:08 AM, tien.fong.c...@intel.com wrote:
>>>>
>>>> From: Tien Fong Chee 
>>>>
>>>> Update pdma properties for Stratix 10
>>>>
>>>> Signed-off-by: Tien Fong Chee 
>>>> ---
>>>>  arch/arm/dts/socfpga_stratix10.dtsi | 20 
>>>>  1 file changed, 20 insertions(+)
>>>>
>>>> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
>>>> b/arch/arm/dts/socfpga_stratix10.dtsi
>>>> index ccd3f32..311ba09 100644
>>>> --- a/arch/arm/dts/socfpga_stratix10.dtsi
>>>> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
>>>> @@ -82,6 +82,26 @@
>>>>    ranges = <0 0 0 0x>;
>>>>    u-boot,dm-pre-reloc;
>>>>  
>>>> +  amba {
>>>> +  u-boot,dm-pre-reloc;
>>>> +  compatible = "arm,amba-bus";
>>>> +  #address-cells = <1>;
>>>> +  #size-cells = <1>;
>>>> +  ranges;
>>>> +
>>>> +  pdma: pdma@ffda {
>>>> +  u-boot,dm-pre-reloc;
>>>> +  compatible =
>>>> "arm,pl330", "arm,dma330";
>>> I think you got "arm,dma330" binding wrong. I don't see any binding
>>> with
>>> that name.
> Here https://patchwork.ozlabs.org/patch/923234/ .

Oh okay...why do you need to add the additional binding "arm,dma330"?

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 5/5] arm: dts: socfpga: stratix10: update pdma

[Dinh Nguyen]

On 05/31/2018 03:08 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> Update pdma properties for Stratix 10
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  arch/arm/dts/socfpga_stratix10.dtsi | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi 
> b/arch/arm/dts/socfpga_stratix10.dtsi
> index ccd3f32..311ba09 100644
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -82,6 +82,26 @@
>   ranges = <0 0 0 0x>;
>   u-boot,dm-pre-reloc;
>  
> + amba {
> + u-boot,dm-pre-reloc;
> + compatible = "arm,amba-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + pdma: pdma@ffda {
> + u-boot,dm-pre-reloc;
> + compatible = "arm,pl330", "arm,dma330";

I think you got "arm,dma330" binding wrong. I don't see any binding with
that name.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: socfpga: Adjust NAND register layout on Arria10

[Dinh Nguyen]

On 05/29/2018 11:36 AM, Marek Vasut wrote:
> Adjust the NAND register size on Arria10 to reflect reality.
> 
> Signed-off-by: Marek Vasut 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> ---
>  arch/arm/dts/socfpga_arria10.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
> b/arch/arm/dts/socfpga_arria10.dtsi
> index b51febda9c..2f935a21e9 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -637,8 +637,8 @@
>   #address-cells = <1>;
>   #size-cells = <1>;
>   compatible = "denali,denali-nand-dt", 
> "altr,socfpga-denali-nand";
> - reg = <0xffb9 0x72000>,
> -   <0xffb8 0x1>;
> + reg = <0xffb9 0x20>,
> +   <0xffb8 0x1000>;
>   reg-names = "nand_data", "denali_reg";
>   interrupts = <0 99 4>;
>   dma-mask = <0x>;
> 

Acked-by: Dinh Nguyen 
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [U-Boot, v3, 1/3] mmc: dwmmc: socfpga: Add reset ctrl to driver

[Dinh Nguyen]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256



On 05/25/2018 06:16 AM, Tom Rini wrote:
> On Fri, May 25, 2018 at 10:45:53AM +0800, Ley Foon Tan wrote:
>> On Thu, May 24, 2018 at 8:39 PM, Tom Rini 
>> wrote:
>>> On Tue, May 08, 2018 at 11:19:24AM +0800, Ley Foon Tan wrote:
>>> 
 Add code to reset all reset signals as in mmc DT node. A
 reset property is an optional feature, so only print out a
 warning and do not fail if a reset property is not present.
 
 If a reset property is discovered, then use it to deassert,
 thus bringing the IP out of reset.
 
 Signed-off-by: Ley Foon Tan  
 Reviewed-by: Simon Glass  --- 
 drivers/mmc/socfpga_dw_mmc.c |   17 + 1 files
 changed, 17 insertions(+), 0 deletions(-)
 
 diff --git a/drivers/mmc/socfpga_dw_mmc.c
 b/drivers/mmc/socfpga_dw_mmc.c index fa0e449..eb7e64e 100644 
 --- a/drivers/mmc/socfpga_dw_mmc.c +++
 b/drivers/mmc/socfpga_dw_mmc.c @@ -13,6 +13,7 @@ #include
  #include  #include  
 +#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 @@ -33,6 +34,20 @@ struct dwmci_socfpga_priv_data { unsigned
 intsmplsel; };
 
 +static void socfpga_dwmci_reset(struct udevice *dev) +{ +
 struct reset_ctl_bulk reset_bulk; + int ret; + + ret
 = reset_get_bulk(dev, _bulk); + if (ret) { +
 dev_warn(dev, "Can't get reset: %d\n", ret); +
 return; + } + + reset_deassert_bulk(_bulk); +}
>>> 
>>> The driver doesn't depend on DM_RESET and this code hunk
>>> doesn't either so it fails to build on a number of platforms.
>>> This type of comment applies to the whole series, and may be
>>> fixed differently in different cases (it might be OK to enforce
>>> DM_RESET for this driver, but not for the ns16550 driver).
>>> 
>>> -- Tom
>>> 
>> include/reset.h has the DM_RESET wrapper, so it will not cause
>> the compilation error if the CONFIG_DM_RESET is disabled.
>> 
>> I have tried compile the uboot with CONFIG_DM_RESET disabled, 
>> compilation is fine.

The case is fine when CONFIG_DM_RESET is disabled, but it fails when
CONFIG_DM_RESET is enabled.

You need:

CONFIG_SPL_RESET_SUPPORT=y

Dinh
-BEGIN PGP SIGNATURE-
Version: GnuPG v2

iQIcBAEBCAAGBQJbDVXVAAoJEBmUBAuBoyj0GrwP/1UAMiFWllpyq/19Lktr8yDa
hZxl4Ynj6HHOSSUWorZeAdaAE0r79lPMR037G7XLV1EiVfe7XkKgVXp8EUusNbMA
nYY+TOe321MoSF+agXoVr6QbwTwH67lAJO5uZ+sbStlElkH1ATTbbsNE092P6Gp9
WgwK8fT1p78BJQ4djTUwDnxIFe9hW3O4VhIeKEte0Ny7cgxsoYH0a6eXd1ozjOp/
H7j31vgjemPUYQI7gf+2JEz/38DaFOMvF4n5eofftIV44Nx8yE/VzgM+9ry+QxNn
h+7/VM2LYbTTwDA+9YuRyleLrv8hcIgbcd/TFnxkBr8Yw4N3JSQjhyjeK/LkTGge
hyixyy132bng89GcGZn3oXxKLTdUi3v9pwBI5payjZ/sKuH8nySM3OAas3nrPWI3
g62t8/x3ufD+ZegaVWL66Sp2kLt3xamJe+WrLtcGgXzOLJDC9lsE8/iV+d2Jrat6
4x6gvcxPJvd0WieEapzsP6SqU/J0yA/RrMAtTwASQrXd9yH5CH6+FD/Yw+ShyEiO
FiIz/p80NL3yqkFOBASm422r8RKPZ84hOeHNbV79rWNrBaQHAlK/mKwPrNjhao7l
j3izAGOi75/aQO8QBnD2uCDXHRDL0+mCPPcwBzX90/HtubIjB/ZHiZuDuwCa+JrN
wwbHCJO6WDj3sqv0iErz
=JhCN
-END PGP SIGNATURE-
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 0/3] drivers: Add reset ctrl to drivers

[Dinh Nguyen]

On Fri, May 4, 2018 at 5:49 AM, Ley Foon Tan  wrote:
> Add reset ctrl to dwmmc socfpga, designware Ethernet and ns16550 serial 
> drivers.
>
> A reset property is an optional feature, so only print out a warning and
> do not fail if a reset property is not present.
>
> If a reset property is discovered, then use it to deassert, thus bringing the
> IP out of reset.
>
> This is preparation to upstream Intel Stratix 10 SoC support in [1].
>
> v2 change:
> - remove 'return' in designware emac driver
> - keep reset control in socfpga_dw_mmc.c because it didn't call to common 
> dwmmc probe
>   function when in SPL.
> - add reviewed-by in ns16550 patch
>
> History:
> v1: https://patchwork.ozlabs.org/cover/905519/
>
> [1]: https://patchwork.ozlabs.org/cover/900499/
>
> Ley Foon Tan (3):
>   mmc: dwmmc: socfpga: Add reset ctrl to driver
>   serial: ns16550: Add reset ctrl to driver
>   net: designware: Add reset ctrl to driver
>
>  drivers/mmc/socfpga_dw_mmc.c |   19 +++
>  drivers/net/designware.c |   11 +++
>  drivers/serial/ns16550.c |   12 
>  3 files changed, 42 insertions(+), 0 deletions(-)

Please run get_maintainer.pl on V3. You're forgetting to include the
maintainers on these subsystems.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC] spl: dw_mmc_socfpga: udevice structure is NULL in SPL

[Dinh Nguyen]

On 04/25/2018 09:26 PM, Ley Foon Tan wrote:
> On Thu, Apr 26, 2018 at 10:24 AM, Dinh Nguyen <dingu...@kernel.org> wrote:
>> Hi,
>>
>> I am trying to add support for the sdmmc driver to use the reset manager
>> driver in SPL. But I'm noticing that the udevice struct dev that passed
>> into socfpga_dwmmc_probe() is NULL, thus, I can't use the
>> reset_get_by_() functions to get the reset information because it needs
>> the dev structure is NULL.
>>
>> Not sure if I'm missing a config option or something?
>>
>> Thanks,
>> Dinh
> 
> 
> I think you need add " u-boot,dm-pre-reloc;" into reset manager and DW
> MMC device tree nodes.
> 

Ah yes, thanks! That solved the problem.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [RFC] spl: dw_mmc_socfpga: udevice structure is NULL in SPL

[Dinh Nguyen]

Hi,

I am trying to add support for the sdmmc driver to use the reset manager
driver in SPL. But I'm noticing that the udevice struct dev that passed
into socfpga_dwmmc_probe() is NULL, thus, I can't use the
reset_get_by_() functions to get the reset information because it needs
the dev structure is NULL.

Not sure if I'm missing a config option or something?

Thanks,
Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCHv1 14/14] reset: remove request and free functions

[Dinh Nguyen]

On 04/16/2018 01:51 PM, Stephen Warren wrote:
> On 04/16/2018 12:43 PM, Simon Glass wrote:
>> +Stephen for comment
>>
>> Hi Dinh,
>>
>> On 14 April 2018 at 12:51, Dinh Nguyen <dingu...@kernel.org> wrote:
>>> The request and free reset functions are not really used for any useful
>>> purpose but for debugging. We can safely remove them.
>>
>> The API is set to line up with clocks. I think in general we do want
>> to be able to request and free these devices, just as we do for GPIOs.
>> What is the goal of removing these methods?
> 
> Many of the request methods do in fact do something; they check the
> validity of the reset ID so that check doesn't need to be duplicated
> everywhere. Even ignoring that, any resource management API should have
> explicit request/free APIs so that lifetime can be tracked if needed.

Agreed, that the checks were in some of the request functions, but the
majority did not do any checks, just a debug() statement. All of the
platforms that did the checks, I just moved them to reset_assert and
reset_deassert.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCHv1 14/14] reset: remove request and free functions

[Dinh Nguyen]

On 04/16/2018 01:43 PM, Simon Glass wrote:
> +Stephen for comment
> 
> Hi Dinh,
> 
> On 14 April 2018 at 12:51, Dinh Nguyen <dingu...@kernel.org> wrote:
>> The request and free reset functions are not really used for any useful
>> purpose but for debugging. We can safely remove them.
> 
> The API is set to line up with clocks. I think in general we do want
> to be able to request and free these devices, just as we do for GPIOs.
> What is the goal of removing these methods?
> 

It was a suggestion from Marek. I just didn't see any useful code
implemented in any of the request/free functions.

Dinh
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 13/14] reset: test: remove sandbox_reset_test_free function

[Dinh Nguyen]

Remove sandbox_reset_test_free() because it calls reset_free, which is
being removed.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 arch/sandbox/include/asm/reset.h   | 1 -
 drivers/reset/sandbox-reset-test.c | 7 ---
 test/dm/reset.c| 2 --
 3 files changed, 10 deletions(-)

diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
index 0cd7702..c54b266 100644
--- a/arch/sandbox/include/asm/reset.h
+++ b/arch/sandbox/include/asm/reset.h
@@ -19,7 +19,6 @@ int sandbox_reset_test_assert(struct udevice *dev);
 int sandbox_reset_test_assert_bulk(struct udevice *dev);
 int sandbox_reset_test_deassert(struct udevice *dev);
 int sandbox_reset_test_deassert_bulk(struct udevice *dev);
-int sandbox_reset_test_free(struct udevice *dev);
 int sandbox_reset_test_release_bulk(struct udevice *dev);
 
 #endif
diff --git a/drivers/reset/sandbox-reset-test.c 
b/drivers/reset/sandbox-reset-test.c
index f0ceaa0..91a1f6e 100644
--- a/drivers/reset/sandbox-reset-test.c
+++ b/drivers/reset/sandbox-reset-test.c
@@ -57,13 +57,6 @@ int sandbox_reset_test_deassert_bulk(struct udevice *dev)
return reset_deassert_bulk(>bulk);
 }
 
-int sandbox_reset_test_free(struct udevice *dev)
-{
-   struct sandbox_reset_test *sbrt = dev_get_priv(dev);
-
-   return reset_free(>ctl);
-}
-
 int sandbox_reset_test_release_bulk(struct udevice *dev)
 {
struct sandbox_reset_test *sbrt = dev_get_priv(dev);
diff --git a/test/dm/reset.c b/test/dm/reset.c
index 8dc0023..289693d 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -35,8 +35,6 @@ static int dm_test_reset(struct unit_test_state *uts)
ut_assertok(sandbox_reset_test_deassert(dev_test));
ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
 
-   ut_assertok(sandbox_reset_test_free(dev_test));
-
return 0;
 }
 DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 10/14] net: dwc_eth_qos: remove reset_free from driver

[Dinh Nguyen]

The call to free the reset control line is a deadend call that doesn't
lead to any reset control functionality.

Also the reset_free() function will be remove in a subsequent patch, so
remove it here.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/net/dwc_eth_qos.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 232e803..a3f1b40 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1371,7 +1371,6 @@ static int eqos_probe_resources_tegra186(struct udevice 
*dev)
   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret) {
pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
-   goto err_free_reset_eqos;
}
 
ret = clk_get_by_name(dev, "slave_bus", >clk_slave_bus);
@@ -1418,8 +1417,6 @@ err_free_clk_slave_bus:
clk_free(>clk_slave_bus);
 err_free_gpio_phy_reset:
dm_gpio_free(dev, >phy_reset_gpio);
-err_free_reset_eqos:
-   reset_free(>reset_ctl);
 
debug("%s: returns %d\n", __func__, ret);
return ret;
@@ -1437,7 +1434,6 @@ static int eqos_remove_resources_tegra186(struct udevice 
*dev)
clk_free(>clk_slave_bus);
clk_free(>clk_master_bus);
dm_gpio_free(dev, >phy_reset_gpio);
-   reset_free(>reset_ctl);
 
debug("%s: OK\n", __func__);
return 0;
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 09/14] reset: sandbox: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/sandbox-reset.c | 25 ++---
 1 file changed, 6 insertions(+), 19 deletions(-)

diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
index c310749..a75143f 100644
--- a/drivers/reset/sandbox-reset.c
+++ b/drivers/reset/sandbox-reset.c
@@ -20,29 +20,15 @@ struct sandbox_reset {
struct sandbox_reset_signal signals[SANDBOX_RESET_SIGNALS];
 };
 
-static int sandbox_reset_request(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
-
-   if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
-   return -EINVAL;
-
-   return 0;
-}
-
-static int sandbox_reset_free(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
-
-   return 0;
-}
-
 static int sandbox_reset_assert(struct reset_ctl *reset_ctl)
 {
struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
 
debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
 
+   if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
+   return -EINVAL;
+
sbr->signals[reset_ctl->id].asserted = true;
 
return 0;
@@ -54,6 +40,9 @@ static int sandbox_reset_deassert(struct reset_ctl *reset_ctl)
 
debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
 
+   if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
+   return -EINVAL;
+
sbr->signals[reset_ctl->id].asserted = false;
 
return 0;
@@ -79,8 +68,6 @@ static const struct udevice_id sandbox_reset_ids[] = {
 };
 
 struct reset_ops sandbox_reset_reset_ops = {
-   .request = sandbox_reset_request,
-   .free = sandbox_reset_free,
.rst_assert = sandbox_reset_assert,
.rst_deassert = sandbox_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 08/14] reset: socfpga: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-socfpga.c | 18 --
 1 file changed, 18 deletions(-)

diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 466455d..3d04132 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -52,25 +52,7 @@ static int socfpga_reset_deassert(struct reset_ctl 
*reset_ctl)
return 0;
 }
 
-static int socfpga_reset_request(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
- reset_ctl, reset_ctl->dev, reset_ctl->id);
-
-   return 0;
-}
-
-static int socfpga_reset_free(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
- reset_ctl->dev, reset_ctl->id);
-
-   return 0;
-}
-
 static const struct reset_ops socfpga_reset_ops = {
-   .request = socfpga_reset_request,
-   .free = socfpga_reset_free,
.rst_assert = socfpga_reset_assert,
.rst_deassert = socfpga_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 03/14] reset: uniphier: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-uniphier.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index a40cea5..5b1d923 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -171,16 +171,6 @@ struct uniphier_reset_priv {
const struct uniphier_reset_data *data;
 };
 
-static int uniphier_reset_request(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
-static int uniphier_reset_free(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
 static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
 {
struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
@@ -226,8 +216,6 @@ static int uniphier_reset_deassert(struct reset_ctl 
*reset_ctl)
 }
 
 static const struct reset_ops uniphier_reset_ops = {
-   .request = uniphier_reset_request,
-   .free = uniphier_reset_free,
.rst_assert = uniphier_reset_assert,
.rst_deassert = uniphier_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 12/14] usb: ehci/ohci: remove reset_free function

[Dinh Nguyen]

The call to free the reset control line is a deadend call that doesn't
lead to any reset control functionality.

Also the reset_free() function will be remove in a subsequent patch, so
remove it here.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/usb/host/ehci-generic.c | 1 -
 drivers/usb/host/ohci-generic.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index b012d86..8ed6a27 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -133,7 +133,6 @@ static int ehci_usb_probe(struct udevice *dev)
if (reset_deassert(>resets[i])) {
dev_err(dev, "failed to deassert reset %d\n",
i);
-   reset_free(>resets[i]);
goto reset_err;
}
priv->reset_count++;
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index 5bdd799..f61c0fc 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -125,7 +125,6 @@ static int ohci_usb_probe(struct udevice *dev)
err = reset_deassert(>resets[i]);
if (err) {
dev_err(dev, "failed to deassert reset %d\n", 
i);
-   reset_free(>resets[i]);
goto reset_err;
}
priv->reset_count++;
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 14/14] reset: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-uclass.c | 28 
 include/reset-uclass.h   | 21 -
 include/reset.h  | 23 ---
 3 files changed, 72 deletions(-)

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 9a5c9c9..24dd48c 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -72,12 +72,6 @@ int reset_get_by_index(struct udevice *dev, int index,
return ret;
}
 
-   ret = ops->request(reset_ctl);
-   if (ret) {
-   debug("ops->request() failed: %d\n", ret);
-   return ret;
-   }
-
return 0;
 }
 
@@ -133,24 +127,6 @@ int reset_get_by_name(struct udevice *dev, const char 
*name,
return reset_get_by_index(dev, index, reset_ctl);
 }
 
-int reset_request(struct reset_ctl *reset_ctl)
-{
-   struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
-
-   debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
-
-   return ops->request(reset_ctl);
-}
-
-int reset_free(struct reset_ctl *reset_ctl)
-{
-   struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
-
-   debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
-
-   return ops->free(reset_ctl);
-}
-
 int reset_assert(struct reset_ctl *reset_ctl)
 {
struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
@@ -209,10 +185,6 @@ int reset_release_all(struct reset_ctl *reset_ctl, int 
count)
ret = reset_assert(_ctl[i]);
if (ret)
return ret;
-
-   ret = reset_free(_ctl[i]);
-   if (ret)
-   return ret;
}
 
return 0;
diff --git a/include/reset-uclass.h b/include/reset-uclass.h
index 50fbeb1..a6301cf 100644
--- a/include/reset-uclass.h
+++ b/include/reset-uclass.h
@@ -40,27 +40,6 @@ struct reset_ops {
int (*of_xlate)(struct reset_ctl *reset_ctl,
struct ofnode_phandle_args *args);
/**
-* request - Request a translated reset control.
-*
-* The reset core calls this function as the second step in
-* implementing a client's reset_get_by_*() call, following a
-* successful xxx_xlate() call.
-*
-* @reset_ctl:  The reset control struct to request; this has been
-*  filled in by a previoux xxx_xlate() function call.
-* @return 0 if OK, or a negative error code.
-*/
-   int (*request)(struct reset_ctl *reset_ctl);
-   /**
-* free - Free a previously requested reset control.
-*
-* This is the implementation of the client reset_free() API.
-*
-* @reset_ctl:  The reset control to free.
-* @return 0 if OK, or a negative error code.
-*/
-   int (*free)(struct reset_ctl *reset_ctl);
-   /**
 * rst_assert - Assert a reset signal.
 *
 * Note: This function is named rst_assert not assert to avoid
diff --git a/include/reset.h b/include/reset.h
index d38f176..505de77 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -134,24 +134,6 @@ int reset_get_by_name(struct udevice *dev, const char 
*name,
  struct reset_ctl *reset_ctl);
 
 /**
- * reset_request - Request a reset signal.
- *
- * @reset_ctl: A reset control struct.
- *
- * @return 0 if OK, or a negative error code.
- */
-int reset_request(struct reset_ctl *reset_ctl);
-
-/**
- * reset_free - Free a previously requested reset signal.
- *
- * @reset_ctl: A reset control struct that was previously successfully
- * requested by reset_get_by_*().
- * @return 0 if OK, or a negative error code.
- */
-int reset_free(struct reset_ctl *reset_ctl);
-
-/**
  * reset_assert - Assert a reset signal.
  *
  * This function will assert the specified reset signal, thus resetting the
@@ -254,11 +236,6 @@ static inline int reset_get_by_name(struct udevice *dev, 
const char *name,
return -ENOTSUPP;
 }
 
-static inline int reset_free(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
 static inline int reset_assert(struct reset_ctl *reset_ctl)
 {
return 0;
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 05/14] reset: meson: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-meson.c | 18 +++---
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 5324f86..8bbaa6c 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -20,19 +20,6 @@ struct meson_reset_priv {
struct regmap *regmap;
 };
 
-static int meson_reset_request(struct reset_ctl *reset_ctl)
-{
-   if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
-   return -EINVAL;
-
-   return 0;
-}
-
-static int meson_reset_free(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
 static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
 {
struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
@@ -41,6 +28,9 @@ static int meson_reset_level(struct reset_ctl *reset_ctl, 
bool assert)
uint reg_offset = LEVEL_OFFSET + (bank << 2);
uint val;
 
+   if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+   return -EINVAL;
+
regmap_read(priv->regmap, reg_offset, );
if (assert)
val &= ~BIT(offset);
@@ -62,8 +52,6 @@ static int meson_reset_deassert(struct reset_ctl *reset_ctl)
 }
 
 struct reset_ops meson_reset_ops = {
-   .request = meson_reset_request,
-   .free = meson_reset_free,
.rst_assert = meson_reset_assert,
.rst_deassert = meson_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 06/14] reset: bcm6345: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-bcm6345.c | 21 ++---
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c
index ebf6bee..b49a2f1 100644
--- a/drivers/reset/reset-bcm6345.c
+++ b/drivers/reset/reset-bcm6345.c
@@ -23,6 +23,9 @@ static int bcm6345_reset_assert(struct reset_ctl *rst)
 {
struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
 
+   if (rst->id >= MAX_RESETS)
+   return -EINVAL;
+
clrbits_be32(priv->regs, BIT(rst->id));
mdelay(20);
 
@@ -33,28 +36,16 @@ static int bcm6345_reset_deassert(struct reset_ctl *rst)
 {
struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
 
+   if (rst->id >= MAX_RESETS)
+   return -EINVAL;
+
setbits_be32(priv->regs, BIT(rst->id));
mdelay(20);
 
return 0;
 }
 
-static int bcm6345_reset_free(struct reset_ctl *rst)
-{
-   return 0;
-}
-
-static int bcm6345_reset_request(struct reset_ctl *rst)
-{
-   if (rst->id >= MAX_RESETS)
-   return -EINVAL;
-
-   return bcm6345_reset_assert(rst);
-}
-
 struct reset_ops bcm6345_reset_reset_ops = {
-   .free = bcm6345_reset_free,
-   .request = bcm6345_reset_request,
.rst_assert = bcm6345_reset_assert,
.rst_deassert = bcm6345_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 11/14] phy: bcm63xx: remove reset_free function

[Dinh Nguyen]

The call to free the reset control line is a deadend call that doesn't
lead to any reset control functionality.

Also the reset_free() function will be remove in a subsequent patch, so
remove it here.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/phy/bcm6318-usbh-phy.c | 4 
 drivers/phy/bcm6348-usbh-phy.c | 4 
 drivers/phy/bcm6358-usbh-phy.c | 4 
 drivers/phy/bcm6368-usbh-phy.c | 4 
 drivers/spi/bcm63xx_hsspi.c| 4 
 drivers/spi/bcm63xx_spi.c  | 4 
 6 files changed, 24 deletions(-)

diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c
index 6d54214..70907be 100644
--- a/drivers/phy/bcm6318-usbh-phy.c
+++ b/drivers/phy/bcm6318-usbh-phy.c
@@ -125,10 +125,6 @@ static int bcm6318_usbh_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
mdelay(100);
 
return 0;
diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c
index 169ee0e..2cc04e1 100644
--- a/drivers/phy/bcm6348-usbh-phy.c
+++ b/drivers/phy/bcm6348-usbh-phy.c
@@ -77,10 +77,6 @@ static int bcm6348_usbh_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
return 0;
 }
 
diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c
index e000316..0440388 100644
--- a/drivers/phy/bcm6358-usbh-phy.c
+++ b/drivers/phy/bcm6358-usbh-phy.c
@@ -77,10 +77,6 @@ static int bcm6358_usbh_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
return 0;
 }
 
diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c
index 71abc0f..38dd5e0 100644
--- a/drivers/phy/bcm6368-usbh-phy.c
+++ b/drivers/phy/bcm6368-usbh-phy.c
@@ -165,10 +165,6 @@ static int bcm6368_usbh_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
/* enable usb_ref clock */
ret = clk_get_by_name(dev, "usb_ref", );
if (!ret) {
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 3393166..ddf75f0 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -383,10 +383,6 @@ static int bcm63xx_hsspi_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
/* initialize hardware */
writel_be(0, priv->regs + SPI_IR_MASK_REG);
 
diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
index f0df687..71bb07d 100644
--- a/drivers/spi/bcm63xx_spi.c
+++ b/drivers/spi/bcm63xx_spi.c
@@ -409,10 +409,6 @@ static int bcm63xx_spi_probe(struct udevice *dev)
if (ret < 0)
return ret;
 
-   ret = reset_free(_ctl);
-   if (ret < 0)
-   return ret;
-
/* initialize hardware */
writeb_be(0, priv->base + regs[SPI_IR_MASK]);
 
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 07/14] reset: ast2500: remove request function

[Dinh Nguyen]

The request reset function is not really used for any useful purpose
except for debugging. We can safely remove it.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/ast2500-reset.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
index b2c89e1..65708cf 100644
--- a/drivers/reset/ast2500-reset.c
+++ b/drivers/reset/ast2500-reset.c
@@ -68,14 +68,6 @@ static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
return ret;
 }
 
-static int ast2500_reset_request(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
- reset_ctl->dev, reset_ctl->id);
-
-   return 0;
-}
-
 static int ast2500_reset_probe(struct udevice *dev)
 {
struct ast2500_reset_priv *priv = dev_get_priv(dev);
@@ -92,7 +84,6 @@ static const struct udevice_id ast2500_reset_ids[] = {
 
 struct reset_ops ast2500_reset_ops = {
.rst_assert = ast2500_reset_assert,
-   .request = ast2500_reset_request,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 04/14] reset: rockchip: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/reset-rockchip.c | 26 +++---
 1 file changed, 3 insertions(+), 23 deletions(-)

diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
index 01047a2..5eecd51 100644
--- a/drivers/reset/reset-rockchip.c
+++ b/drivers/reset/reset-rockchip.c
@@ -24,27 +24,6 @@ struct rockchip_reset_priv {
u32 reset_reg_num;
 };
 
-static int rockchip_reset_request(struct reset_ctl *reset_ctl)
-{
-   struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-
-   debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
- reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
-
-   if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
-   return -EINVAL;
-
-   return 0;
-}
-
-static int rockchip_reset_free(struct reset_ctl *reset_ctl)
-{
-   debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
- reset_ctl->dev, reset_ctl->id);
-
-   return 0;
-}
-
 static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
 {
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
@@ -55,6 +34,9 @@ static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
  reset_ctl, reset_ctl->dev, reset_ctl->id,
  priv->base + (bank * 4));
 
+   if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
+   return -EINVAL;
+
rk_setreg(priv->base + (bank * 4), BIT(offset));
 
return 0;
@@ -76,8 +58,6 @@ static int rockchip_reset_deassert(struct reset_ctl 
*reset_ctl)
 }
 
 struct reset_ops rockchip_reset_ops = {
-   .request = rockchip_reset_request,
-   .free = rockchip_reset_free,
.rst_assert = rockchip_reset_assert,
.rst_deassert = rockchip_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCHv1 02/14] reset: sti: remove request and free functions

[Dinh Nguyen]

The request and free reset functions are not really used for any useful
purpose but for debugging. We can safely remove them.

Signed-off-by: Dinh Nguyen <dingu...@kernel.org>
---
 drivers/reset/sti-reset.c   | 12 
 drivers/reset/stm32-reset.c | 12 
 2 files changed, 24 deletions(-)

diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
index 0fc5a28..672dd97 100644
--- a/drivers/reset/sti-reset.c
+++ b/drivers/reset/sti-reset.c
@@ -277,16 +277,6 @@ static int sti_reset_program_hw(struct reset_ctl 
*reset_ctl, int assert)
return 0;
 }
 
-static int sti_reset_request(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
-static int sti_reset_free(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
 static int sti_reset_assert(struct reset_ctl *reset_ctl)
 {
return sti_reset_program_hw(reset_ctl, true);
@@ -298,8 +288,6 @@ static int sti_reset_deassert(struct reset_ctl *reset_ctl)
 }
 
 struct reset_ops sti_reset_ops = {
-   .request = sti_reset_request,
-   .free = sti_reset_free,
.rst_assert = sti_reset_assert,
.rst_deassert = sti_reset_deassert,
 };
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index e98f34b..efde745 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -23,16 +23,6 @@ struct stm32_reset_priv {
fdt_addr_t base;
 };
 
-static int stm32_reset_request(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
-static int stm32_reset_free(struct reset_ctl *reset_ctl)
-{
-   return 0;
-}
-
 static int stm32_reset_assert(struct reset_ctl *reset_ctl)
 {
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
@@ -68,8 +58,6 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
 }
 
 static const struct reset_ops stm32_reset_ops = {
-   .request= stm32_reset_request,
-   .free   = stm32_reset_free,
.rst_assert = stm32_reset_assert,
.rst_deassert   = stm32_reset_deassert,
 };
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot