Re: [U-Boot] [PATCH 01/11] i2c: Clean drivers/i2c/ Makefile
Hi Wolfgang, the patches are older and progress in U-BOOT is too big. That's why some patches contains faults. And you applied some patches from Jean-Christophe before these which fixed the same issue. In driver folder only pcmcia and usb need some fix in Makefile. Regards, Michal Dear [EMAIL PROTECTED], In message [EMAIL PROTECTED] you wrote: From: Michal Simek [EMAIL PROTECTED] Signed-off-by: Michal Simek [EMAIL PROTECTED] --- drivers/i2c/Makefile | 10 +- drivers/i2c/fsl_i2c.c |2 -- drivers/i2c/mxc_i2c.c |2 +- drivers/i2c/omap1510_i2c.c |4 drivers/i2c/omap24xx_i2c.c |4 drivers/i2c/tsi108_i2c.c |2 -- 6 files changed, 6 insertions(+), 18 deletions(-) Applied, thanks. Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc440: New board: Avnet Virtex5 FXT Evaluation
his case or will see warning message that on this file in doc folder is described that only change xparameters file is enought for run u-boot on his platform. Simple step by step manual. He do some steps (I think 3 step should be enough) and load u-boot to his platform and run it. And if generic file cover most of possibilities u-boot will run. And then just look how to add his own platform to u-boot and in his private repo will do folder with names which he choose. Best regards, Michal Best regards On Sat, Aug 23, 2008 at 15:05, Michal Simek [EMAIL PROTECTED] wrote: Hi Ricardo, Stefan and Wolfgang, I looked at patches which Ricardo sent. It is really nice to see that someone wants to add new xilinx boards to U-BOOT. But IMHO this is not the right way. I think that one xilinx board with ppc405 and ppc440 is enough. This is FPGA you can choose almost everything what you want to change. - It is useless add new board which has only different setting. It doesn't matter if is avnet or xilinx board and they have different size of flash, ram or whatever. I think that the right way is to have one generic platform and your xparameters can direct it. With adding new board you see avnet board in board folder but that's all. Setting is almost the same with ml507. Please do not extend U-BOOT code with boards which do not add important change. I hope you understand what I mean. The next reason should be what is avnet reference design? (You can use some edk version with ppc440 and there are some changes between version) In Microblaze case you can see I add only two boards - one is with flash and second without. I can do thousands design with different setting but this is not good solution. Please do not add this board and do not start new way that every fpga board will have own folder and config file. This only extend U-BOOT size and that's all. No additional information. My propose solution is to have one generic board (ml507 is ok) and improve ml507 config file for usage with others board. This is what wrote Wolfgang in emails about ml507. Do not hardcode value in memory settings and other. Best regards, Michal Ricardo Ribalda Delgado wrote: Cheap board by Avnet for evaluating the Virtex5 FX technology. This patch adds support for: - UartLite - 16MB Flash - 64MB RAM Prior using U-boot in this board, read carefully the ERRATA by Avnet to solve some memory initialization issues. Signed-off-by: Ricardo Ribalda Delgado [EMAIL PROTECTED] --- CREDITS|2 +- MAINTAINERS|1 + MAKEALL|2 + Makefile | 12 +++ board/avnet/v5fx30teval/.gitignore |2 + board/avnet/v5fx30teval/Makefile | 58 + board/avnet/v5fx30teval/config.mk | 27 ++ board/avnet/v5fx30teval/init.S | 58 + board/avnet/v5fx30teval/u-boot-ram.lds | 134 + board/avnet/v5fx30teval/u-boot-rom.lds | 144 board/avnet/v5fx30teval/v5fx30teval.c | 47 ++ board/avnet/v5fx30teval/xparameters.h | 36 include/configs/v5fx30teval.h | 121 +++ 13 files changed, 643 insertions(+), 1 deletions(-) create mode 100644 board/avnet/v5fx30teval/.gitignore create mode 100644 board/avnet/v5fx30teval/Makefile create mode 100644 board/avnet/v5fx30teval/config.mk create mode 100644 board/avnet/v5fx30teval/init.S create mode 100644 board/avnet/v5fx30teval/u-boot-ram.lds create mode 100644 board/avnet/v5fx30teval/u-boot-rom.lds create mode 100644 board/avnet/v5fx30teval/v5fx30teval.c create mode 100644 board/avnet/v5fx30teval/xparameters.h create mode 100644 include/configs/v5fx30teval.h diff --git a/CREDITS b/CREDITS index 4fe4e63..48be11b 100644 --- a/CREDITS +++ b/CREDITS @@ -405,7 +405,7 @@ D: Atmel AT91CAP9ADK support N: Ricardo Ribalda Delgado E: [EMAIL PROTECTED] -D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460 +D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval W: http://www.ii.uam.es/~rribalda N: Stefan Roese diff --git a/MAINTAINERS b/MAINTAINERS index 31493c2..4a950f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -318,6 +318,7 @@ Daniel Poirot [EMAIL PROTECTED] Ricardo Ribalda [EMAIL PROTECTED] ml507 PPC440x5 + v5fx30teval PPC440x5 Stefan Roese [EMAIL PROTECTED] diff --git a/MAKEALL b/MAKEALL index edfee90..a1c1957 100755 --- a/MAKEALL +++ b/MAKEALL @@ -231,6 +231,8 @@ LIST_4xx=\ sequoia_nand\ taihu \ taishan \ + v5fx30teval \ + v5fx30teval_flash \ VOH405 \ VOM405 \ W7OLMC \ diff --git a/Makefile b/Makefile index f02ab65..7561eef 100644
Re: [U-Boot] [PATCH] ppc44x: RFC: Unification of virtex5 pp440 boards
And one more thing. I would like to see readme in one board folder where will be written what design it is. If you use reference design from xilinx page please write it. Or if is the design from BSB just write it to this file. M Ricardo Ribalda Delgado wrote: Hi Stefan First of all: Thanks for taking some time in reading the patch I looked at your patch. your xparameters contain space before tab Sorry :), BTW: do you know how to highlight this in vim? macro XPAR_DDR2_SDRAM_MEM_BASEADDR is in generic file board/xilinx/ppc440-generic/xilinx_ppc440_generic.c. This is not much generic value. MB use XILINX_RAM_START for every memory. Software doesn't care if is ddr2 or ddr or sdram - just memory. That was a reason why I did special bsp for generation of xparameters.h. I would like to mantain the Xparameters file created by edk: It is very convenient for the user, he just have to replace the xparameters.h file with his file. I can add something like #ifdef XPAR_OTHER_RAM_NAME #define #XPAR_DDR2_SDRAM_MEM_BASEADDR XPAR_OTHER_RAM_NAME #endif avnet and ml507 folder contain only checkboard function with one puts. This is not much for whole board. The name should be in xparameters.h and written in generic platform. ml507 and avnet directories was just an example of how to create a board that replaces the generic functions. Anyway, I consider to left them, those two are the more representative boards and should be supported explicitly by u-boot. Also, there is no code replication I see simplier way just add #define BOARD_NAME Avnet bla bla or for xilinx too. And small change in puts. If the user is using the generic design, he should see generic design in the prompt. Anyway, this is just a personal opinion, no big deal changing this Why is xparameters.h in generic folder? You meant that is generic code - there should be nothing specific like addresses are. (That's for your patches not for generic solution which I have in my mind) The generic folder is also a the generic-board folder. XPAR_SPI_0_NUM_TRANSFER_BITS, XPAR_IIC_EEPROM_BASEADDR and XPAR_SPI_0_BASEADDR are not used anywhere. And maybe some others. (LL_TEMAC driver is not in U-BOOT - I have full version with fifo and sgdma in my repo but LLTEMAC_0_BASEADDR is not used in U-BOOT yet) I use it on my design, that lines can be replaced. Anyway I have a working version of Xilinx SPI, I am waiting for some more tests to release it. Please compare both configs files - you can see changes which are board specific. 1. point to proper xparameters.h 2. ENV_OFFSET - this could be generic It hardly depends on the .bit size and the flash size 3. prompt - the same situation as is checkboard function it is nice to see what version are you using. At least it makes me a little more sane 4. flash size - cfi take cares about - not important ok, I thought it was important because what i see in other boards 5. max flash sect - just choose one max value. ok 6. mtd relate things - just generic name should be used - physmap-flash.0: is good with relation with Linux kernel and physmap driver. It helps you with synchronization through command line. Same as 3, but I can change it, it is less critical 7. Size of ram - xparameters.h I add this because a requeriment by Stefan 8. Stefan please correct me but I think that u-boot doesn't handle sector size for storing variables. If no - This should be a small problem that boards have different sect size - this cause error with sector boundary. - this should be written in readme file. And that's all. I haven't seen nothing why is this style oriented to board. We have a generic board and specific boards that can overwrite the generic functions and add more functionality like custom link script, custom xparameters and custom boot, My opinion is that it is style oriented On the base what I see in your patch is. That you create board folder with one important file which is xparameters.h for every board. This file contains max 10 important value which are hw desing specific and they are no relation with board. They have only relation with hw design which you build and which you can change as you want. There is nothing what solve real problem. IMHO this is too little for adding any specific as new xilinx board is. A simple board will just replace the xparameters.h file in ppc440-generic folder, more complex boards stil need a folder with their initialitation rutines. Also, as a comertial matter I believe that it is a good idea that the most/sold boards have their folder. Future collaborations will have a place to put their work and will be more visual to common users. That's exactly what I wrote. Use proper BSP not for generation linux parameters but u-boot specific and take care about name. This solves a lot of problems which can
Re: [U-Boot] [PATCH v7] net: ll_temac: Add LL TEMAC driver to u-boot
Stephan Linz wrote: Am Donnerstag, den 05.01.2012, 20:19 +0100 schrieb Wolfgang Denk: Dear Stephan Linz, In message 1325783490.7827.45.camel@keto you wrote: Michals latest Microblaze platform patches will enable this driver for board/xilinx/microblaze-generic and we know about a success story on a propietary Virtex5 FX board (ppc440) -- tested by Ricardo Ribalda. -- snip -- So I'll rework the driver and present a new v8 patch as soon as possible. OK. Please submit it only if it comes with code that references the driver. Hi Wolfgang, I understand your opinions to stick together all the different code fragments. Unfortunately, this driver will be used by systems with synthesized hardware (FPGA SoftCPU systems). The target board (hardware around the FPGA) will be fixed but the content (CPU, controller, busses, interfacess, addresses, ...) will be variable and not fixed. That's why we use a so named microblaze-generic board configuration controlled by the header xparameters.h in board directory. The default content of xparameters.h is really only basic and enables not nearly half of all possibilities. For example the default configuration in xparameters.h will enable the Xilinx EMAC-Lite driver (with XILINX_EMACLITE_BASEADDR) but do nothing to enable the Xilinx AXI-EMAC driver (with XILINX_AXIEMAC_BASEADDR) -- it makes no sense to enable both at the same time. Every fpga system is different that's why I have created microblaze-generic board and BSP generator to generate xparameters.h and config.mk for specific configurations. Make no sense to create new board for every configuration. The same arguments is valid for xilinx ppc405/ppc440 systems where I am still don't like that there are avnet boards and maybe others. I'll provide the same way for the Xilinx LL_TEMAC driver as for the Xilinx AXI-EMAC driver. I prepare the microblaze-generic board code to support all potential Ethernet drivers but leave out the specific usage. You are right when you say that there is no code that refere to the new driver code -- there are also no configuration for this. And yes we adapt/change the xparameters.h out of mainline tree to enable the driver code -- but I think, that is not really a out of tree port. But what would be the best implementation for unspecified targets here? @Michal: Is there anybody who use the current default configuration from microblaze-generic/xparameters.h on a real FPGA system design? If not we could expand xparameters.h with a fantasy configuration to enable all potential drivers used on a Microblaze system. So we have a reference to driver code and can test the rebuild again and again with a simple 'make microblaze-generic'. What do you mean? It is the same situation as is for axi-emac and even emaclite. xparamters.h/config.mk are for any old platform which none uses it. IMHO Stephan suggestion could work - enable all drivers in xparameters.h and enable code compilation. I can also extend my testing system to compile u-boot with ll_temac and test it on qemu every day. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7] net: ll_temac: Add LL TEMAC driver to u-boot
Wolfgang Denk wrote: Dear Stephan Linz, In message 1325956366.18981.47.camel@keto you wrote: I'll provide the same way for the Xilinx LL_TEMAC driver as for the Xilinx AXI-EMAC driver. I prepare the microblaze-generic board code to support all potential Ethernet drivers but leave out the specific usage. You are right when you say that there is no code that refere to the new driver code -- there are also no configuration for this. And yes we adapt/change the xparameters.h out of mainline tree to enable the driver code -- but I think, that is not really a out of tree port. But what would be the best implementation for unspecified targets here? The question is actually a very simple one here: is there any board configuration in mainline that will actually compile and link against this driver? If yes, then everything is fine. If not, we would not even know if there were gross syntax errors in that code, and we would never notce when changes to other parts break compatibility with it. This is why I will not add any code that is not used in mainline - out-of-tree users don't help a bit. OK. Stephan, please send v8 with suggested changes with all patches or link to patches which are necessary to use. Please also define fake address XILINX_LLTEMAC_BASEADDR in xparameters.h to be compiled. The same we will do for axi emac driver. Stephan if you like I can add that changes to my custodian git tree and do final testing before we ask Wolfgang to merge. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] net: ll_temac: Add LL TEMAC driver to u-boot
Hi Stephan, Stephan Linz wrote: Xilinx LocalLink Tri-Mode Ether MAC driver can be used by Xilinx Microblaze or Xilinx ppc405/440 in SDMA and FIFO mode. DCR or XPS bus can be used. The driver uses and requires MII and PHYLIB. CP: 4 warnings: 'Use of volatile is usually wrong' I won't fix this, because it depends on the network driver subsystem. Signed-off-by: Stephan Linz l...@li-pro.net --- v9: Remove private Rx/Tx transfer buffer for SDMA and FIFO. Use the PktBuf infrastruct from upper network layer. Review all the recv/send functions for SDMA and FIFO mode and insert more detailed comments. Test with tftp put/get on ML605 and SP3ADSP1800. v8: Remove deprecated interface: miiphy_register() Implement MDIO bus/phy access code as independent part of driver. Make the direct PHY access code accessible for upper layer like the MDIO command. Define proper device names for TEMAC and MII interfaces. Support of TEMAC0 and TEMAC1 at same time is prepared and should work. v7: Call udelay() in polling loops to avoid unintended watchdog reset Define well known timeout values in usec Handle timeouts as error situations Reduce duplicated code in SDMA operations Add a real and plausible PHY detect mask Remove ETH_HALTING code exclusion Code cleanup as recommended Fix typos v6: Code cleanup with ./tools/checkpatch.pl v5: Remove more endless loops Remove useless parenthesis in pointer operations Move phyaddr predefinition on top Remove supernumerary newlines Remove parenthesis around numbers (globally) v4: Separate fifo and sdma code from driver core Split sdma code into separate DCR and XPS bus access code Add extensive register struct definitions and enumerations Add new callbacks into fifo an sdma code Prepare CDMAC buffer handling to be unique for every instance Separate Xilinx specific indirect DCR access, so we can move to arch Remove useless 'emac' parameter from indirect access helper functions Correct MDIO clock setup. Remove endless loops Common code beautifying v3: Use helper functions for fifo mode Use helper functions for indirect accesses Code cleanup Add comments for MAGIC values Simplify code in fifo mode v2: Remove helper function for access to temac Remove SDMA/FIFO/DCR macros and configure it in board Setup mac by write_hwaddr --- drivers/net/Makefile |2 + drivers/net/xilinx_ll_temac.c | 386 drivers/net/xilinx_ll_temac_fifo.c | 143 drivers/net/xilinx_ll_temac_mdio.c | 165 ++ drivers/net/xilinx_ll_temac_sdma.c | 370 +++ include/netdev.h |1 + include/xilinx_ll_temac.h | 430 include/xilinx_ll_temac_fifo.h | 122 ++ include/xilinx_ll_temac_mdio.h | 53 + include/xilinx_ll_temac_sdma.h | 281 +++ 10 files changed, 1953 insertions(+), 0 deletions(-) create mode 100644 drivers/net/xilinx_ll_temac.c create mode 100644 drivers/net/xilinx_ll_temac_fifo.c create mode 100644 drivers/net/xilinx_ll_temac_mdio.c create mode 100644 drivers/net/xilinx_ll_temac_sdma.c create mode 100644 include/xilinx_ll_temac.h create mode 100644 include/xilinx_ll_temac_fifo.h create mode 100644 include/xilinx_ll_temac_mdio.h create mode 100644 include/xilinx_ll_temac_sdma.h Wolfgang: I just wanted to know what it is the rule for adding headers. I would prefer to add these headers to drivers/net/ folder instead include. diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f4f7ea3..430f90c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -77,6 +77,8 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ + xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c new file mode 100644 index 000..7124561 --- /dev/null +++ b/drivers/net/xilinx_ll_temac.c @@ -0,0 +1,386 @@ +/* + * Xilinx xps_ll_temac ethernet driver for u-boot + * + * supports SDMA or FIFO access and MDIO bus communication + * + * Copyright (C) 2011 - 2012 Stephan Linz l...@li-pro.net + * Copyright (C) 2008 - 2011 Michal Simek mon...@monstr.eu + * Copyright (C) 2008 - 2011 PetaLogix + * + * Based on Yoshio Kashiwagi kashiw...@co-nss.co.jp driver + * Copyright (C) 2008 Nissin Systems Co.,Ltd. + * March 2008 created + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either
Re: [U-Boot] [PATCH 2/8] microblaze: Enable several ethernet driver compilation
Stephan Linz wrote: U-Boot's multipple network supports enables to use several ethernet drivers but microblaze-generic platform config file select only one driver. Reported-by: Michal Simek mon...@monstr.eu Signed-off-by: Stephan Linz l...@li-pro.net --- include/configs/microblaze-generic.h | 12 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 03a6f5a..09ac870 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -65,11 +65,15 @@ /* ethernet */ #undef CONFIG_SYS_ENET -#ifdef XILINX_EMACLITE_BASEADDR -# define CONFIG_XILINX_EMACLITE1 +#if defined(XILINX_EMACLITE_BASEADDR) +# define CONFIG_XILINX_EMACLITE1 # define CONFIG_SYS_ENET -#elif XILINX_LLTEMAC_BASEADDR -# define CONFIG_XILINX_LL_TEMAC1 +#endif +#if defined(XILINX_LLTEMAC_BASEADDR) || defined(XILINX_LLTEMAC_BASEADDR1) || \ +defined(XILINX_LLTEMAC_BASEADDR2) || defined(XILINX_LLTEMAC_BASEADDR3) || \ +defined(XILINX_LLTEMAC_BASEADDR4) || defined(XILINX_LLTEMAC_BASEADDR5) || \ +defined(XILINX_LLTEMAC_BASEADDR6) || defined(XILINX_LLTEMAC_BASEADDR7) +# define CONFIG_XILINX_LL_TEMAC1 Why to do it in this way? I believe that the first lltemac driver will have XILINX_LLTEMAC_BASEADDR and then others. But for all configurations if there is lltemac driver then will have anyone just BASEADDR. Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] microblaze: Add faked LL_TEMAC driver configuration
Stephan Linz wrote: Expand the specific configuration for the microblaze-generic board in xparameters.h with a faked setup to enable the LL_TEMAC driver. Note: From now the microblaze-generic board is no longer a valid board configuration for a real piece of hardware. Rather than, we use the file config.mk and xparameters.h as a faked board configuration to force the compilation of all potential driver code for Microblaze systems. Signed-off-by: Stephan Linz l...@li-pro.net --- board/xilinx/microblaze-generic/config.mk |6 -- board/xilinx/microblaze-generic/xparameters.h | 24 ++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk index f8d7e26..9fd1015 100644 --- a/board/xilinx/microblaze-generic/config.mk +++ b/board/xilinx/microblaze-generic/config.mk @@ -21,8 +21,10 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# CAUTION: This file is automatically generated by libgen. -# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 +# CAUTION: This file is a faked configuration !!! +# There is no real target for the microblaze-generic +# configuration. You have to replace this file with +# the generated file from your Xilinx design flow. # CONFIG_SYS_TEXT_BASE = 0x2900 diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index fae03bf..69758c3 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -21,8 +21,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 + * CAUTION: This file is a faked configuration !!! + * There is no real target for the microblaze-generic + * configuration. You have to replace this file with + * the generated file from your Xilinx design flow. */ #define XILINX_BOARD_NAME microblaze-generic @@ -69,3 +71,21 @@ /* Ethernet controller is Ethernet_MAC */ #define XILINX_EMACLITE_BASEADDR 0x40C0 + +/* Ethernet controller is Ethernet_MAC */ +#define XILINX_LLTEMAC_BASEADDR0x4400 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 +#define XILINX_LLTEMAC_BASEADDR1 0x4440 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 0x42000200 +#define XILINX_LLTEMAC_BASEADDR2 0x4410 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR2 0x42000280 +#define XILINX_LLTEMAC_BASEADDR3 0x44100040 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR3 0x42000300 Do these two options test anything? +#define XILINX_LLTEMAC_BASEADDR4 0x4420 +#define XILINX_LLTEMAC_FIFO_BASEADDR4 0x4210 +#define XILINX_LLTEMAC_BASEADDR5 0x44200040 +#define XILINX_LLTEMAC_FIFO_BASEADDR5 0x4211 +#define XILINX_LLTEMAC_BASEADDR6 0x4430 +#define XILINX_LLTEMAC_FIFO_BASEADDR6 0x4212 +#define XILINX_LLTEMAC_BASEADDR7 0x44300040 +#define XILINX_LLTEMAC_FIFO_BASEADDR7 0x4213 The same here. Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] fpga: Clean coding style
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/fpga/fpga.c | 214 +++-
1 file changed, 96 insertions(+), 118 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 26d2443..0d29894 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -22,122 +22,99 @@
*
*/
-/*
- * Generic FPGA support
- */
+/* Generic FPGA support */
#include common.h /* core U-Boot definitions */
#include xilinx.h /* xilinx specific definitions */
#include altera.h /* altera specific definitions */
#include lattice.h
-#if 0
-#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
-#endif
-
/* Local definitions */
#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES5
#endif
-/* Enable/Disable debug console messages */
-#ifdef FPGA_DEBUG
-#definePRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#definePRINTF(fmt,args...)
-#endif
-
/* Local static data */
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
-/* Local static functions */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn );
-static int fpga_dev_info( int devnum );
-
-
-/* - */
-
-/* fpga_no_sup
+/*
+ * fpga_no_sup
* 'no support' message function
*/
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(char *fn, char *msg)
{
- if ( fn msg ) {
- printf( %s: No support for %s.\n, fn, msg);
- } else if ( msg ) {
- printf( No support for %s.\n, msg);
- } else {
- printf( No FPGA suport!\n);
- }
+ if (fn msg)
+ printf(%s: No support for %s.\n, fn, msg);
+ else if (msg)
+ printf(No support for %s.\n, msg);
+ else
+ printf(No FPGA suport!\n);
}
/* fpga_get_desc
* map a device number to a descriptor
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum )
+static const fpga_desc *const fpga_get_desc(int devnum)
{
- fpga_desc *desc = (fpga_desc * )NULL;
+ fpga_desc *desc = (fpga_desc *)NULL;
- if (( devnum = 0 ) (devnum next_desc )) {
+ if ((devnum = 0) (devnum next_desc)) {
desc = desc_table[devnum];
- PRINTF( %s: found fpga descriptor #%d @ 0x%p\n,
- __FUNCTION__, devnum, desc );
+ debug(%s: found fpga descriptor #%d @ 0x%p\n,
+ __func__, devnum, desc);
}
return desc;
}
-
-/* fpga_validate
+/*
+ * fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn )
+static const fpga_desc *const fpga_validate(int devnum, const void *buf,
+size_t bsize, char *fn)
{
- fpga_desc * desc = fpga_get_desc( devnum );
+ fpga_desc *desc = fpga_get_desc(devnum);
- if ( !desc ) {
- printf( %s: Invalid device number %d\n, fn, devnum );
- }
+ if (!desc)
+ printf(%s: Invalid device number %d\n, fn, devnum);
- if ( !buf ) {
- printf( %s: Null buffer.\n, fn );
+ if (!buf) {
+ printf(%s: Null buffer.\n, fn);
return (fpga_desc * const)NULL;
}
return desc;
}
-
-/* fpga_dev_info
+/*
+ * fpga_dev_info
* generic multiplexing code
*/
-static int fpga_dev_info( int devnum )
+static int fpga_dev_info(int devnum)
{
- int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ int ret_val = FPGA_FAIL; /* assume failure */
+ const fpga_desc * const desc = fpga_get_desc(devnum);
- if ( desc ) {
- PRINTF( %s: Device Descriptor @ 0x%p\n,
- __FUNCTION__, desc-devdesc );
+ if (desc) {
+ debug(%s: Device Descriptor @ 0x%p\n,
+ __func__, desc-devdesc);
- switch ( desc-devtype ) {
+ switch (desc-devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- printf( Xilinx Device\nDescriptor @ 0x%p\n, desc );
- ret_val = xilinx_info( desc-devdesc );
+ printf(Xilinx Device\nDescriptor @ 0x%p\n, desc);
+ ret_val = xilinx_info(desc-devdesc
[U-Boot] [PATCH 2/2] fpga: Fix debug message compilation error
CONFIG_FPGA in past was bitfield where bits were use for vendor identification. This fix should be the part of this commit: Improve configuration of FPGA subsystem (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184) Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/fpga/fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 0d29894..3bea26c 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -145,7 +145,7 @@ void fpga_init(void) next_desc = 0; memset(desc_table, 0, sizeof(desc_table)); - debug(%s: CONFIG_FPGA = 0x%x\n, __func__, CONFIG_FPGA); + debug(%s\n, __func__); } /* -- 1.8.2.1 pgpwS2_EWrZpJ.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] fpga: Clean coding style
On 04/26/2013 12:25 PM, Michal Simek wrote: No functional changes. Signed-off-by: Michal Simek michal.si...@xilinx.com --- drivers/fpga/fpga.c | 214 +++- 1 file changed, 96 insertions(+), 118 deletions(-) There are compilation failures which I missed. Will fix it in v2. I have created some other patches for cmd/fpga to clean it up. M -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 14/15] i2c: zynq: Add support for Xilinx Zynq
On 04/29/2013 05:39 AM, Heiko Schocher wrote: Hello Michal, AOn 23.04.2013 12:46, Michal Simek wrote: Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger joe.hershber...@ni.com Signed-off-by: Michal Simek michal.si...@xilinx.com CC: Heiko Schocher h...@denx.de --- Changes in v2: - Remove CONFIG_ prefix from non configurable macros (i2c) - Fix checkpatch warnings (i2c) - Fix #definespaceMacro name (i2c) - Fix multiline comments (i2c) - Remove trailing 1 for configurations (i2c) arch/arm/include/asm/arch-zynq/hardware.h | 2 + drivers/i2c/Makefile | 1 + drivers/i2c/zynq_i2c.c| 306 ++ include/configs/zynq.h| 11 ++ 4 files changed, 320 insertions(+) create mode 100644 drivers/i2c/zynq_i2c.c As this is in a patchserie, I just ack your patch: Ackd-by: Heiko Schocher h...@denx.de Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/1] GPIO support for Microblaze
On 04/27/2013 05:35 PM, Simon Glass wrote: Hi Michal, On Wed, Apr 24, 2013 at 1:30 AM, Michal Simek mon...@monstr.eu wrote: Hi Simon, here is also one small problem if you want to use patman just for one patch then cover letter contains 0/1 but patch itself doesn't contain 1/1. I think will be good to just add 1/1 to patch too. Generated by: ./tools/patman/patman -c 1 Possibly, although here patman is just using 'git format-patch' to create the initial patch file. It is just to call git format-patch -n instead of git format-patch all the time. For more that one patch is -n used all the time. There is a 'Series-notes:' tag for adding notes to the cover letter. I wonder if we should add a way to add text below the cut in a patch? Isn't it already done - if you just add text below ---? Then in the case where you only have one patch you might not need a cover letter. I would prefer to support both option. If you have one patch you can add notes below --- or just create cover letter. Developer should choose which way is better for his case. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] gpio: Add support for microblaze xilinx GPIO
On 04/27/2013 05:45 PM, Simon Glass wrote:
Hi Michal,
On Wed, Apr 24, 2013 at 1:27 AM, Michal Simek michal.si...@xilinx.com wrote:
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use gpio status command
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/microblaze/include/asm/gpio.h | 50 +---
.../xilinx/microblaze-generic/microblaze-generic.c | 17 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/xilinx_gpio.c | 323
+
include/configs/microblaze-generic.h | 3 +-
5 files changed, 353 insertions(+), 41 deletions(-)
create mode 100644 drivers/gpio/xilinx_gpio.c
diff --git a/arch/microblaze/include/asm/gpio.h
b/arch/microblaze/include/asm/gpio.h
index 883f4d4..69df8c5 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,41 +1,21 @@
#ifndef _ASM_MICROBLAZE_GPIO_H_
#define _ASM_MICROBLAZE_GPIO_H_
-#include asm/io.h
+/* Allocation functions */
+extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
+ u32 gpio_no1);
+extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
+
+/* Standard functions */
+extern int gpio_request(unsigned gpio, const char *label);
+extern int gpio_free(unsigned gpio);
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
+extern int gpio_get_value(unsigned gpio);
+extern int gpio_set_value(unsigned gpio, int value);
+extern int gpio_is_valid(int number);
You should just be able to include asm-generic/gpio.h for these.
Thanks for pointing to this.
+/* Get gpio pin name if used/setup */
+static char *get_name(unsigned gpio)
+{
+ u32 gpio_priv;
+ debug(%s\n, __func__);
+
+ struct xilinx_gpio_priv *priv = gpio_get_controller(gpio);
It looks like gpio_get_controller() can return NULL, but you use it anyway?
yep. I have fixed that return path if gpio_get_controller returns NULL.
+
+int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no)
+{
+ struct xilinx_gpio_priv *priv;
+
+ priv = calloc(1, sizeof(struct xilinx_gpio_priv));
+
+ /* Setup gpio name */
+ if (name != NULL) {
+ strncpy(priv-name, name, GPIO_NAME_SIZE);
+ priv-name[GPIO_NAME_SIZE - 1] = '\0';
+ }
+ priv-regs = (struct gpio_regs *)baseaddr;
+
+ priv-gpio_min = xilinx_gpio_max;
+ xilinx_gpio_max = priv-gpio_min + gpio_no;
+ priv-gpio_max = xilinx_gpio_max - 1;
+
+ priv-gpio_name = calloc(gpio_no, sizeof(struct gpio_names));
+
+ INIT_LIST_HEAD(priv-list);
+ list_add_tail(priv-list, gpio_list);
+
+ printf(%s: Add %s (%d-%d)\n, __func__, name,
+ priv-gpio_min, priv-gpio_max);
+
+ /* Return the first gpio allocated for this device */
+ return priv-gpio_min;
+}
In terms of allocation, is this function intended to tell the GPIO
driver that there are new GPIOs available?
yep. That was my intention. Just call it from board file to tell
there are new gpios.
For device tree the GPIO banks can be split into individual nodes each
with the same compatible string. Then during device init you can build
a table of available GPIOs. Each bank gets a phandle so that it can be
used elsewhere. For example you might do:
gpio-controllers {
gpa: gpio-a {
compatible = xilinx,gpio-controller;
reg = some_address size;
};
gpb: gpio-b {
compatible = xilinx,gpio-controller;
reg = some_address size;
};
};
example-peripheral {
gpios = gpa 5 ..., gpb 6 ...;
};
The exact binding of GPIOs is up to you - use the same one as Linux if
you have one there.
yep. I have designed these functions based on device-tree description
and to be able to use it for binding.
In general while loop over dts with compatible string to call this gpio_alloc
or gpio_alloc_dual based on properties.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo
[U-Boot] Pull request - microblaze
Hi Tom, please pull these microblaze changes to your tree. 2 of that patches was reviewed by you. Thanks, Michal The following changes since commit d10f68ae47b67acab8b110b5c605dde4197a1820: Prepare v2013.04 (2013-04-19 10:25:43 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git microblaze for you to fetch changes up to 0f21f98dd4d6bff72df4eeaca4163779896cb336: watchdog: Add support for Xilinx Microblaze watchdog (2013-04-30 11:22:43 +0200) Michal Simek (4): microblaze: Fix reset function microblaze: Enable netconsole microblaze: Disable all cpu features before reset watchdog: Add support for Xilinx Microblaze watchdog arch/microblaze/include/asm/processor.h | 4 +++ arch/microblaze/lib/board.c | 3 ++ board/xilinx/microblaze-generic/microblaze-generic.c | 11 -- board/xilinx/microblaze-generic/xparameters.h| 4 +++ doc/README.watchdog | 3 ++ drivers/watchdog/Makefile| 1 + drivers/watchdog/xilinx_tb_wdt.c | 87 ++ include/configs/microblaze-generic.h | 17 - 8 files changed, 126 insertions(+), 4 deletions(-) create mode 100644 drivers/watchdog/xilinx_tb_wdt.c -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - zynq
Hi Tom and Albert, please pull this patchset related to arm zynq to your tree. I haven't got any ACK for gem and platform changes but the whole patchset was reviewed by Tom. Also not all patches are ARM core specific but they are affecting zynq platform that's why I think it can go directly to Tom tree. Please let me know if you have any problem with it. I can create more branches with specific patches which should go through specific trees. I have removed fpga related patch because I have some others pending fpga patches and I will group them together. Thanks, Michal The following changes since commit d10f68ae47b67acab8b110b5c605dde4197a1820: Prepare v2013.04 (2013-04-19 10:25:43 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git zynq for you to fetch changes up to 8934f7846501070a5b01c1fab5db27559e9d70d1: i2c: zynq: Add support for Xilinx Zynq (2013-04-30 11:39:28 +0200) David Andrey (3): arm: zynq: U-Boot udelay 1000 FIX net: gem: Pass phy address to init net: gem: Preserve clk on emio interface Michal Simek (11): arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses zynq: Move scutimer baseaddr to hardware.h net: phy: Define Marvell 88e1518 phy net: gem: Remove WRAP bit from TX buffer description net: gem: Simplify return path in zynq_gem_recv net: gem: Do not initialize BDs again net: gem: Fix gem driver on 1Gbps LAN zynq: Move macros to hardware.h net: gem: Add support for phy autodetection mmc: Add support for Xilinx Zynq sdhci controller i2c: zynq: Add support for Xilinx Zynq arch/arm/cpu/armv7/zynq/slcr.c | 26 arch/arm/cpu/armv7/zynq/timer.c| 49 --- arch/arm/include/asm/arch-zynq/hardware.h | 26 +--- arch/arm/include/asm/arch-zynq/sys_proto.h | 4 ++ board/xilinx/zynq/board.c | 29 - drivers/i2c/Makefile | 1 + drivers/i2c/zynq_i2c.c | 306 + drivers/mmc/Makefile | 1 + drivers/mmc/zynq_sdhci.c | 40 drivers/net/phy/marvell.c | 11 drivers/net/zynq_gem.c | 199 +- include/configs/zynq.h | 33 -- include/netdev.h | 2 +- 13 files changed, 644 insertions(+), 83 deletions(-) create mode 100644 drivers/i2c/zynq_i2c.c create mode 100644 drivers/mmc/zynq_sdhci.c -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request - microblaze
On 04/30/2013 05:44 PM, Tom Rini wrote: On Tue, Apr 30, 2013 at 11:26:44AM +0200, Michal Simek wrote: Hi Tom, please pull these microblaze changes to your tree. 2 of that patches was reviewed by you. Thanks, Michal The following changes since commit d10f68ae47b67acab8b110b5c605dde4197a1820: Prepare v2013.04 (2013-04-19 10:25:43 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git microblaze for you to fetch changes up to 0f21f98dd4d6bff72df4eeaca4163779896cb336: watchdog: Add support for Xilinx Microblaze watchdog (2013-04-30 11:22:43 +0200) Michal Simek (4): microblaze: Fix reset function microblaze: Enable netconsole microblaze: Disable all cpu features before reset watchdog: Add support for Xilinx Microblaze watchdog arch/microblaze/include/asm/processor.h | 4 +++ arch/microblaze/lib/board.c | 3 ++ board/xilinx/microblaze-generic/microblaze-generic.c | 11 -- board/xilinx/microblaze-generic/xparameters.h| 4 +++ doc/README.watchdog | 3 ++ drivers/watchdog/Makefile| 1 + drivers/watchdog/xilinx_tb_wdt.c | 87 ++ include/configs/microblaze-generic.h | 17 - 8 files changed, 126 insertions(+), 4 deletions(-) create mode 100644 drivers/watchdog/xilinx_tb_wdt.c Applied to u-boot/master, thanks! Have you pushed it to git.denx.de? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request - zynq
On 04/30/2013 04:50 PM, Tom Rini wrote: On Tue, Apr 30, 2013 at 11:49:33AM +0200, Michal Simek wrote: Hi Tom and Albert, please pull this patchset related to arm zynq to your tree. I haven't got any ACK for gem and platform changes but the whole patchset was reviewed by Tom. Also not all patches are ARM core specific but they are affecting zynq platform that's why I think it can go directly to Tom tree. Please let me know if you have any problem with it. I can create more branches with specific patches which should go through specific trees. I have removed fpga related patch because I have some others pending fpga patches and I will group them together. Thanks, Michal The following changes since commit d10f68ae47b67acab8b110b5c605dde4197a1820: Prepare v2013.04 (2013-04-19 10:25:43 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git zynq for you to fetch changes up to 8934f7846501070a5b01c1fab5db27559e9d70d1: i2c: zynq: Add support for Xilinx Zynq (2013-04-30 11:39:28 +0200) David Andrey (3): arm: zynq: U-Boot udelay 1000 FIX net: gem: Pass phy address to init net: gem: Preserve clk on emio interface Michal Simek (11): arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses zynq: Move scutimer baseaddr to hardware.h net: phy: Define Marvell 88e1518 phy net: gem: Remove WRAP bit from TX buffer description net: gem: Simplify return path in zynq_gem_recv net: gem: Do not initialize BDs again net: gem: Fix gem driver on 1Gbps LAN zynq: Move macros to hardware.h net: gem: Add support for phy autodetection mmc: Add support for Xilinx Zynq sdhci controller i2c: zynq: Add support for Xilinx Zynq arch/arm/cpu/armv7/zynq/slcr.c | 26 arch/arm/cpu/armv7/zynq/timer.c| 49 --- arch/arm/include/asm/arch-zynq/hardware.h | 26 +--- arch/arm/include/asm/arch-zynq/sys_proto.h | 4 ++ board/xilinx/zynq/board.c | 29 - drivers/i2c/Makefile | 1 + drivers/i2c/zynq_i2c.c | 306 + drivers/mmc/Makefile | 1 + drivers/mmc/zynq_sdhci.c | 40 drivers/net/phy/marvell.c | 11 drivers/net/zynq_gem.c | 199 +- include/configs/zynq.h | 33 -- include/netdev.h | 2 +- 13 files changed, 644 insertions(+), 83 deletions(-) create mode 100644 drivers/i2c/zynq_i2c.c create mode 100644 drivers/mmc/zynq_sdhci.c Unless Albert really doesn't want this, I'm fine going through his tree as it's all ARM related. Albert: any comment? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/7] FPGA cleanup + zynq support
Fpga code is pretty old and none has tried to clean it up.
My attempt is related to new code I want to push to mainline
which is add support for checking bitstream and if bitstream
is valid for the selected device.
For this I need to do cleanup code and move code
from cmd_fpga.c to fpga.c in driver folder.
Zynq driver:
Depends on previous zynq patches sent some days ago.
Tested by:
set fload tftp \${addr} fpga.bin\;fpga info 0\;fpga load 0 \${addr} \${filesize}
set floadb tftp \${addr} download.bit\;fpga info 0\;fpga loadb 0 \${addr}
\${filesize}
set addr 1000
run fload
run floadb
set addr 1001
run fload
run floadb
set addr 1002
run fload
run floadb
set addr 1003
run fload
run floadb
Thanks for your comments,
Michal
Changes in v2:
- Fix compilation warnings
- Fix grammer in the commit message
- Fix bugs reported by Tom Rini
- Fix checkpatch warnings (fpga)
- Fix comments (fpga)
- Do not use CamelCase for XilinxZynq (fpga)
- Move to fpga series and extend this driver
- New patch in this series
Michal Simek (7):
fpga: Clean coding style
fpga: Fix debug message compilation error
cmd: fpga: Clean coding style
cmd: fpga: Move fpga_loadbitstream to fpga.c
cmd: fpga: Do not include net.h
fpga: zynq: Add support for loading bitstream
fpga: Check device name against bitstream name
arch/arm/cpu/armv7/zynq/slcr.c | 35 +++
arch/arm/include/asm/arch-zynq/hardware.h | 10 +-
arch/arm/include/asm/arch-zynq/sys_proto.h | 3 +
board/xilinx/zynq/board.c | 37 +++
common/cmd_fpga.c | 254 +++--
drivers/fpga/Makefile | 1 +
drivers/fpga/fpga.c| 330 +--
drivers/fpga/xilinx.c | 39
drivers/fpga/zynqpl.c | 355 +
include/configs/zynq.h | 6 +
include/fpga.h | 1 +
include/xilinx.h | 5 +
include/zynqpl.h | 59 +
13 files changed, 840 insertions(+), 295 deletions(-)
create mode 100644 drivers/fpga/zynqpl.c
create mode 100644 include/zynqpl.h
--
1.8.2.1
pgpTiaVVSxhpP.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/7] fpga: Clean coding style
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Fix compilation warnings
drivers/fpga/fpga.c | 216
1 file changed, 98 insertions(+), 118 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 26d2443..ddebd49 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -22,122 +22,99 @@
*
*/
-/*
- * Generic FPGA support
- */
+/* Generic FPGA support */
#include common.h /* core U-Boot definitions */
#include xilinx.h /* xilinx specific definitions */
#include altera.h /* altera specific definitions */
#include lattice.h
-#if 0
-#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
-#endif
-
/* Local definitions */
#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES5
#endif
-/* Enable/Disable debug console messages */
-#ifdef FPGA_DEBUG
-#definePRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#definePRINTF(fmt,args...)
-#endif
-
/* Local static data */
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
-/* Local static functions */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn );
-static int fpga_dev_info( int devnum );
-
-
-/* - */
-
-/* fpga_no_sup
+/*
+ * fpga_no_sup
* 'no support' message function
*/
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(char *fn, char *msg)
{
- if ( fn msg ) {
- printf( %s: No support for %s.\n, fn, msg);
- } else if ( msg ) {
- printf( No support for %s.\n, msg);
- } else {
- printf( No FPGA suport!\n);
- }
+ if (fn msg)
+ printf(%s: No support for %s.\n, fn, msg);
+ else if (msg)
+ printf(No support for %s.\n, msg);
+ else
+ printf(No FPGA suport!\n);
}
/* fpga_get_desc
* map a device number to a descriptor
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum )
+static const fpga_desc *const fpga_get_desc(int devnum)
{
- fpga_desc *desc = (fpga_desc * )NULL;
+ fpga_desc *desc = (fpga_desc *)NULL;
- if (( devnum = 0 ) (devnum next_desc )) {
+ if ((devnum = 0) (devnum next_desc)) {
desc = desc_table[devnum];
- PRINTF( %s: found fpga descriptor #%d @ 0x%p\n,
- __FUNCTION__, devnum, desc );
+ debug(%s: found fpga descriptor #%d @ 0x%p\n,
+ __func__, devnum, desc);
}
return desc;
}
-
-/* fpga_validate
+/*
+ * fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn )
+static const fpga_desc *const fpga_validate(int devnum, const void *buf,
+size_t bsize, char *fn)
{
- fpga_desc * desc = fpga_get_desc( devnum );
+ const fpga_desc *desc = fpga_get_desc(devnum);
- if ( !desc ) {
- printf( %s: Invalid device number %d\n, fn, devnum );
- }
+ if (!desc)
+ printf(%s: Invalid device number %d\n, fn, devnum);
- if ( !buf ) {
- printf( %s: Null buffer.\n, fn );
+ if (!buf) {
+ printf(%s: Null buffer.\n, fn);
return (fpga_desc * const)NULL;
}
return desc;
}
-
-/* fpga_dev_info
+/*
+ * fpga_dev_info
* generic multiplexing code
*/
-static int fpga_dev_info( int devnum )
+static int fpga_dev_info(int devnum)
{
- int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ int ret_val = FPGA_FAIL; /* assume failure */
+ const fpga_desc * const desc = fpga_get_desc(devnum);
- if ( desc ) {
- PRINTF( %s: Device Descriptor @ 0x%p\n,
- __FUNCTION__, desc-devdesc );
+ if (desc) {
+ debug(%s: Device Descriptor @ 0x%p\n,
+ __func__, desc-devdesc);
- switch ( desc-devtype ) {
+ switch (desc-devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- printf( Xilinx Device\nDescriptor @ 0x%p\n, desc );
- ret_val = xilinx_info( desc-devdesc );
+ printf(Xilinx Device\nDescriptor @ 0x%p\n, desc
[U-Boot] [PATCH v2 2/7] fpga: Fix debug message compilation error
CONFIG_FPGA in past was a bitfield where bits were use for vendor identification. This fix should be the part of this commit: Improve configuration of FPGA subsystem (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184) Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: - Fix grammer in the commit message drivers/fpga/fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index ddebd49..43bdf4f 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -145,7 +145,7 @@ void fpga_init(void) next_desc = 0; memset(desc_table, 0, sizeof(desc_table)); - debug(%s: CONFIG_FPGA = 0x%x\n, __func__, CONFIG_FPGA); + debug(%s\n, __func__); } /* -- 1.8.2.1 pgpOwwRMBNxTn.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/7] cmd: fpga: Clean coding style
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
I had to shorten some debug messages and divide them
to two parts to pass checkpatch.
---
common/cmd_fpga.c | 213 +++---
1 file changed, 107 insertions(+), 106 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 1834246..f3579bb 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -34,7 +34,7 @@
#include malloc.h
/* Local functions */
-static int fpga_get_op (char *opstr);
+static int fpga_get_op(char *opstr);
/* Local defines */
#define FPGA_NONE -1
@@ -45,7 +45,7 @@ static int fpga_get_op (char *opstr);
#define FPGA_LOADMK 4
/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
+int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
unsigned int length;
@@ -58,38 +58,36 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
dataptr = (unsigned char *)fpgadata;
/* skip the first bytes of the bitsteam, their meaning is unknown */
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- dataptr+=length;
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ dataptr += length;
/* get design name (identifier, length, string) */
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
if (*dataptr++ != 0x61) {
- debug(%s: Design name identifier not recognized
- in bitstream\n,
- __func__);
+ debug(%s: Design name id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( design filename = \%s\\n, buffer);
/* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) {
- printf(%s: Part number identifier not recognized
- in bitstream\n,
- __func__);
+ printf(%s: Part number id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( part number = \%s\\n, buffer);
@@ -101,35 +99,35 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
}
length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( date = \%s\\n, buffer);
/* get time (identifier, length, string) */
if (*dataptr++ != 0x64) {
printf(%s: Time identifier not recognized in bitstream\n,
- __func__);
+ __func__);
return FPGA_FAIL;
}
length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( time = \%s\\n, buffer);
/* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) {
- printf(%s: Data length identifier not recognized in
bitstream\n,
- __func__);
+ printf(%s: Data length id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- swapsize = ((unsigned int) *dataptr 24) +
- ((unsigned int) *(dataptr+1) 16) +
- ((unsigned int) *(dataptr+2) 8 ) +
- ((unsigned int) *(dataptr+3) ) ;
- dataptr+=4;
+ swapsize = ((unsigned int) *dataptr 24) +
+ ((unsigned int) *(dataptr + 1) 16) +
+ ((unsigned int) *(dataptr + 2) 8) +
+ ((unsigned int) *(dataptr + 3));
+ dataptr += 4;
printf( bytes in bitstream = %d\n, swapsize);
rc = fpga_load(dev, dataptr, swapsize);
@@ -148,81 +146,81 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
* If there is no data addr field, the fpgadata environment variable is used.
* The info command requires no data address field.
*/
-int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+int do_fpga(cmd_tbl_t
[U-Boot] [PATCH v2 7/7] fpga: Check device name against bitstream name
Ensure that wrong bitstream won't be loaded
to current device.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- New patch in this series
drivers/fpga/fpga.c | 20
drivers/fpga/xilinx.c | 2 ++
include/xilinx.h | 1 +
include/zynqpl.h | 8
4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index b74c84f..5ba8cf0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -197,8 +197,14 @@ int fpga_loadbitstream(unsigned long dev, char *fpgadata,
size_t size)
unsigned char *dataptr;
unsigned int i;
int rc;
+ const fpga_desc *desc;
+ Xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata;
+ /* Find out fpga_description */
+ desc = fpga_validate(dev, dataptr, 0, (char *)__func__);
+ /* Assign xilinx device description */
+ xdesc = desc-devdesc;
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr 8) + *(dataptr + 1);
@@ -232,6 +238,20 @@ int fpga_loadbitstream(unsigned long dev, char *fpgadata,
size_t size)
dataptr += 2;
for (i = 0; i length; i++)
buffer[i] = *dataptr++;
+
+ if (xdesc-name) {
+ i = strncmp(buffer, xdesc-name, strlen(xdesc-name));
+ if (i) {
+ printf(%s: Wrong bitstream ID for this device\n,
+ __func__);
+ printf(%s: Bitstream ID %s, current device ID %d/%s\n,
+ __func__, dev, xdesc-name, buffer);
+ return FPGA_FAIL;
+ }
+ } else {
+ printf(%s: Please fill correct device ID to Xilinx_desc\n,
+ __func__);
+ }
printf( part number = \%s\\n, buffer);
/* get date (identifier, length, string) */
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index fe324ab..bd740c2 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -220,6 +220,8 @@ int xilinx_info (Xilinx_desc * desc)
printf (Device Size: \t%d bytes\n
Cookie:\t0x%x (%d)\n,
desc-size, desc-cookie, desc-cookie);
+ if (desc-name)
+ printf(Device name: \t%s\n, desc-name);
if (desc-iface_fns) {
printf (Device Function Table @ 0x%p\n,
desc-iface_fns);
diff --git a/include/xilinx.h b/include/xilinx.h
index 592cbea..bcfe76d 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -81,6 +81,7 @@ typedef struct { /* typedef Xilinx_desc */
size_t size;/* bytes of data part can accept */
void *iface_fns;/* interface function table */
int cookie; /* implementation specific cookie */
+ char *name; /* device name in bitstream */
} Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions
diff --git a/include/zynqpl.h b/include/zynqpl.h
index bc9b948..0247ef6 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -45,15 +45,15 @@ extern int zynq_info(Xilinx_desc *desc);
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, 7z010 }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, 7z020 }
#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, 7z030 }
#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, 7z045 }
#endif /* _ZYNQPL_H_ */
--
1.8.2.1
pgppLAojCDRxW.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/7] cmd: fpga: Move fpga_loadbitstream to fpga.c
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
common/cmd_fpga.c | 94 -
drivers/fpga/fpga.c | 94 +
include/fpga.h | 1 +
3 files changed, 95 insertions(+), 94 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index f3579bb..aa14ceb 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -44,100 +44,6 @@ static int fpga_get_op(char *opstr);
#define FPGA_DUMP 3
#define FPGA_LOADMK 4
-/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
-{
-#if defined(CONFIG_FPGA_XILINX)
- unsigned int length;
- unsigned int swapsize;
- char buffer[80];
- unsigned char *dataptr;
- unsigned int i;
- int rc;
-
- dataptr = (unsigned char *)fpgadata;
-
- /* skip the first bytes of the bitsteam, their meaning is unknown */
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- dataptr += length;
-
- /* get design name (identifier, length, string) */
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- if (*dataptr++ != 0x61) {
- debug(%s: Design name id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
-
- printf( design filename = \%s\\n, buffer);
-
- /* get part number (identifier, length, string) */
- if (*dataptr++ != 0x62) {
- printf(%s: Part number id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( part number = \%s\\n, buffer);
-
- /* get date (identifier, length, string) */
- if (*dataptr++ != 0x63) {
- printf(%s: Date identifier not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr+1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( date = \%s\\n, buffer);
-
- /* get time (identifier, length, string) */
- if (*dataptr++ != 0x64) {
- printf(%s: Time identifier not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr+1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( time = \%s\\n, buffer);
-
- /* get fpga data length (identifier, length) */
- if (*dataptr++ != 0x65) {
- printf(%s: Data length id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
- swapsize = ((unsigned int) *dataptr 24) +
- ((unsigned int) *(dataptr + 1) 16) +
- ((unsigned int) *(dataptr + 2) 8) +
- ((unsigned int) *(dataptr + 3));
- dataptr += 4;
- printf( bytes in bitstream = %d\n, swapsize);
-
- rc = fpga_load(dev, dataptr, swapsize);
- return rc;
-#else
- printf(Bitstream support only for Xilinx devices\n);
- return FPGA_FAIL;
-#endif
-}
-
/* - */
/* command form:
* fpga op device number data addr datasize
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 43bdf4f..b74c84f 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -187,6 +187,100 @@ int fpga_add(fpga_type devtype, void *desc)
return devnum;
}
+/* Convert bitstream data and load into the fpga */
+int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
+{
+#if defined(CONFIG_FPGA_XILINX)
+ unsigned int length;
+ unsigned int swapsize;
+ char buffer[80];
+ unsigned char *dataptr;
+ unsigned int i;
+ int rc;
+
+ dataptr = (unsigned char *)fpgadata;
+
+ /* skip the first bytes of the bitsteam, their meaning is unknown */
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ dataptr += length;
+
+ /* get design name (identifier, length, string) */
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ if (*dataptr++ != 0x61) {
+ debug(%s: Design name id not recognized in bitstream\n,
+ __func__);
+ return
[U-Boot] [PATCH v2 6/7] fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger joe.hershber...@ni.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Fix bugs reported by Tom Rini
- Fix checkpatch warnings (fpga)
- Fix comments (fpga)
- Do not use CamelCase for XilinxZynq (fpga)
- Move to fpga series and extend this driver
This patch was the part of zynq series but I have decided
to extend it with partial bitstream support, loadb support
and create separate patchset just for fpga patches.
The origin patch was reviewed by Tom Rini.
---
arch/arm/cpu/armv7/zynq/slcr.c | 35 +++
arch/arm/include/asm/arch-zynq/hardware.h | 10 +-
arch/arm/include/asm/arch-zynq/sys_proto.h | 3 +
board/xilinx/zynq/board.c | 37 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/xilinx.c | 37 +++
drivers/fpga/zynqpl.c | 355 +
include/configs/zynq.h | 6 +
include/xilinx.h | 4 +
include/zynqpl.h | 59 +
10 files changed, 545 insertions(+), 2 deletions(-)
create mode 100644 drivers/fpga/zynqpl.c
create mode 100644 include/zynqpl.h
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 5a8674a..52048c6 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -28,6 +28,9 @@
#define SLCR_LOCK_MAGIC0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000
+#define SLCR_IDCODE_SHIFT 12
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
@@ -87,3 +90,35 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
out:
zynq_slcr_lock();
}
+
+void zynq_slcr_devcfg_disable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Disable AXI interface */
+ writel(0x, slcr_base-fpga_rst_ctrl);
+
+ /* Set Level Shifters DT618760 */
+ writel(0xA, slcr_base-lvl_shftr_en);
+
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Set Level Shifters DT618760 */
+ writel(0xF, slcr_base-lvl_shftr_en);
+
+ /* Disable AXI interface */
+ writel(0x0, slcr_base-fpga_rst_ctrl);
+
+ zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+ return (readl(slcr_base-pss_idcode) SLCR_IDCODE_MASK)
+ SLCR_IDCODE_SHIFT;
+}
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 6af892a..8b8a91a 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -53,11 +53,17 @@ struct slcr_regs {
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h
b/arch/arm/include/asm/arch-zynq/sys_proto.h
index af9e7f8..2317121 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -27,6 +27,9 @@ extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 1589d21..b02c364 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -22,15 +22,52 @@
#include common.h
#include netdev.h
+#include zynqpl.h
#include asm/arch/hardware.h
#include asm/arch/sys_proto.h
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FPGA
+Xilinx_desc fpga;
+
+/* It can be done differently */
+Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+#endif
+
int board_init(void)
{
+#ifdef CONFIG_FPGA
+ u32 idcode;
+
+ idcode = zynq_slcr_get_idcode();
+
+ switch (idcode) {
+ case XILINX_ZYNQ_7010
[U-Boot] [PATCH v2 5/7] cmd: fpga: Do not include net.h
There is no reason to include net.h header in fpga code. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: None common/cmd_fpga.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index aa14ceb..5e1d037 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -27,9 +27,6 @@ */ #include common.h #include command.h -#if defined(CONFIG_CMD_NET) -#include net.h -#endif #include fpga.h #include malloc.h -- 1.8.2.1 pgpQIlyXBORXq.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] gpio: Add support for microblaze xilinx GPIO
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use gpio status command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Use asm-generic/gpio.h file
- Add gpio_set_value()
- Check return value from gpio_get_controller
GPIO support for Microblaze
I want to also write gpio support for Zynq
and this driver should be also used for arm zynq.
Currently we have support just for only gpio controller
but not for various of them.
That's why I would like to get some input from you
if possible to add dynamic gpio allocation which
could be also helpful for OF support.
Output from my gpio status on Microblaze is below.
Thanks,
Michal
U-Boot gpio status
gpio_info: reset/4000 (0-0)
GPIO_0: reset_pin is an INPUT value = 0
gpio_info: led/4004 (1-5)
GPIO_1: UNKNOWN is an INPUT value = 0
GPIO_2: UNKNOWN is an OUTPUT value = 1
GPIO_3: UNKNOWN is an INPUT value = 0
GPIO_4: UNKNOWN is an INPUT value = 0
GPIO_5: UNKNOWN is an OUTPUT value = 0
---
arch/microblaze/include/asm/gpio.h | 40 +--
.../xilinx/microblaze-generic/microblaze-generic.c | 17 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/xilinx_gpio.c | 364 +
include/configs/microblaze-generic.h | 3 +-
5 files changed, 386 insertions(+), 39 deletions(-)
create mode 100644 drivers/gpio/xilinx_gpio.c
diff --git a/arch/microblaze/include/asm/gpio.h
b/arch/microblaze/include/asm/gpio.h
index 883f4d4..f5cad56 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,41 +1,15 @@
#ifndef _ASM_MICROBLAZE_GPIO_H_
#define _ASM_MICROBLAZE_GPIO_H_
-#include asm/io.h
+#include asm-generic/gpio.h
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
+/* Allocation functions */
+extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
+ u32 gpio_no1);
+extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
-static inline int gpio_free(unsigned gpio)
-{
- return 0;
-}
+#define gpio_status() gpio_info()
+extern void gpio_info(void);
-static inline int gpio_direction_input(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_set_value(unsigned gpio, int value)
-{
- return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
- return 0;
-}
#endif
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c
b/board/xilinx/microblaze-generic/microblaze-generic.c
index befbb3a..2f5f20e 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -31,12 +31,17 @@
#include asm/processor.h
#include asm/microblaze_intc.h
#include asm/asm.h
+#include asm/gpio.h
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
- ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+#ifdef CONFIG_XILINX_GPIO
+ if (reset_pin != -1)
+ gpio_direction_output(reset_pin, 1);
#endif
#ifdef CONFIG_XILINX_TB_WATCHDOG
@@ -52,8 +57,10 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int gpio_init (void)
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x;
+#ifdef CONFIG_XILINX_GPIO
+ reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, reset, 1);
+ if (reset_pin != -1)
+ gpio_request(reset_pin, reset_pin);
#endif
return 0;
}
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9df1e26..830e8e6 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
COBJS-$(CONFIG_DB8500_GPIO)+= db8500_gpio.o
COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
+COBJS-$(CONFIG_XILINX_GPIO)+= xilinx_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
new file mode 100644
index
Re: [U-Boot] [PATCH v2 4/7] cmd: fpga: Move fpga_loadbitstream to fpga.c
On 05/01/2013 05:03 PM, Tom Rini wrote: On Wed, May 01, 2013 at 10:59:20AM +0200, Michal Simek wrote: In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it. Signed-off-by: Michal Simek michal.si...@xilinx.com [snip] +++ b/drivers/fpga/fpga.c [snip] +#else +printf(Bitstream support only for Xilinx devices\n); +return FPGA_FAIL; +#endif How about we re-work this as a __weak fpga_loadbitstream in drivers/fpga/fpga.c that just says Bitstream support not implemented for this FPGA device, return FPGA_FAIL, and move the xilinx one into drivers/fpga/xilinx.c ? yep. Make sense to do it because at least from this code altera or lattice don't support bitstream loading. It will be more problematic if there is a board on the market with different fpgas. I even not sure if other fpga vendors have bitstream with any header which should be used by this command. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] FPGA cleanup + zynq support
On 05/01/2013 05:14 PM, Tom Rini wrote: On Wed, May 01, 2013 at 10:59:16AM +0200, Michal Simek wrote: Fpga code is pretty old and none has tried to clean it up. My attempt is related to new code I want to push to mainline which is add support for checking bitstream and if bitstream is valid for the selected device. For this I need to do cleanup code and move code from cmd_fpga.c to fpga.c in driver folder. Aside from my comments to 4/7, everything else looks good and a step forward. ok Looking at 7/7 however, it seems like: - None of CONFIG_SYS_XILINX_IF_* are used - CONFIG_SYS_... model definitions... aren't used, now that CONFIG_FPGA isn't a bitfield anymore, and are only used by configs that still act like it is. So we could just clean up and remove those parts of the header, yes? yep, you are right. I will create one more patch which remove these values. (It should be done in 2008). Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] gpio: Add support for microblaze xilinx GPIO
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use gpio status command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Use asm-generic/gpio.h file
- Add gpio_set_value()
- Check return value from gpio_get_controller
GPIO support for Microblaze
I want to also write gpio support for Zynq
and this driver should be also used for arm zynq.
Currently we have support just for only gpio controller
but not for various of them.
That's why I would like to get some input from you
if possible to add dynamic gpio allocation which
could be also helpful for OF support.
Output from my gpio status on Microblaze is below.
Thanks,
Michal
U-Boot gpio status
gpio_info: reset/4000 (0-0)
GPIO_0: reset_pin is an INPUT value = 0
gpio_info: led/4004 (1-5)
GPIO_1: UNKNOWN is an INPUT value = 0
GPIO_2: UNKNOWN is an OUTPUT value = 1
GPIO_3: UNKNOWN is an INPUT value = 0
GPIO_4: UNKNOWN is an INPUT value = 0
GPIO_5: UNKNOWN is an OUTPUT value = 0
---
arch/microblaze/include/asm/gpio.h | 40 +--
.../xilinx/microblaze-generic/microblaze-generic.c | 17 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/xilinx_gpio.c | 364 +
include/configs/microblaze-generic.h | 3 +-
5 files changed, 386 insertions(+), 39 deletions(-)
create mode 100644 drivers/gpio/xilinx_gpio.c
diff --git a/arch/microblaze/include/asm/gpio.h
b/arch/microblaze/include/asm/gpio.h
index 883f4d4..f5cad56 100644
--- a/arch/microblaze/include/asm/gpio.h
+++ b/arch/microblaze/include/asm/gpio.h
@@ -1,41 +1,15 @@
#ifndef _ASM_MICROBLAZE_GPIO_H_
#define _ASM_MICROBLAZE_GPIO_H_
-#include asm/io.h
+#include asm-generic/gpio.h
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
+/* Allocation functions */
+extern int gpio_alloc_dual(u32 baseaddr, const char *name, u32 gpio_no0,
+ u32 gpio_no1);
+extern int gpio_alloc(u32 baseaddr, const char *name, u32 gpio_no);
-static inline int gpio_free(unsigned gpio)
-{
- return 0;
-}
+#define gpio_status() gpio_info()
+extern void gpio_info(void);
-static inline int gpio_direction_input(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_set_value(unsigned gpio, int value)
-{
- return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
- return 0;
-}
#endif
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c
b/board/xilinx/microblaze-generic/microblaze-generic.c
index befbb3a..2f5f20e 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -31,12 +31,17 @@
#include asm/processor.h
#include asm/microblaze_intc.h
#include asm/asm.h
+#include asm/gpio.h
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
- ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+#ifdef CONFIG_XILINX_GPIO
+ if (reset_pin != -1)
+ gpio_direction_output(reset_pin, 1);
#endif
#ifdef CONFIG_XILINX_TB_WATCHDOG
@@ -52,8 +57,10 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int gpio_init (void)
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x;
+#ifdef CONFIG_XILINX_GPIO
+ reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, reset, 1);
+ if (reset_pin != -1)
+ gpio_request(reset_pin, reset_pin);
#endif
return 0;
}
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9df1e26..830e8e6 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
COBJS-$(CONFIG_DB8500_GPIO)+= db8500_gpio.o
COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
+COBJS-$(CONFIG_XILINX_GPIO)+= xilinx_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c
new file mode 100644
index
[U-Boot] [PATCH v3 0/9] FPGA cleanup + zynq support
Fpga code is pretty old and none has tried to clean it up.
My attempt is related to new code I want to push to mainline
which is add support for checking bitstream and if bitstream
is valid for the selected device.
For this I need to do cleanup code and move code
from cmd_fpga.c to fpga.c in driver folder.
Zynq driver:
Depends on previous zynq patches sent some days ago.
Tested by:
set fload tftp \${addr} fpga.bin\;fpga info 0\;fpga load 0 \${addr} \${filesize}
set floadb tftp \${addr} download.bit\;fpga info 0\;fpga loadb 0 \${addr}
\${filesize}
set addr 1000
run fload
run floadb
set addr 1001
run fload
run floadb
set addr 1002
run fload
run floadb
set addr 1003
run fload
run floadb
Thanks for your comments,
Michal
Changes in v3:
- Setup fpga_loadbitstream as weak function
- New patch in this series
- Rebase because of change in previous patch
- fpga_validate should be global function
- fix one printf function
- change parameter name according to previous patch dev-devnum
- New patch in this series
Changes in v2:
- Fix compilation warnings
- Fix grammer in the commit message
- Fix bugs reported by Tom Rini
- Fix checkpatch warnings (fpga)
- Fix comments (fpga)
- Do not use CamelCase for XilinxZynq (fpga)
- Move to fpga series and extend this driver
- New patch in this series
Michal Simek (9):
fpga: Clean coding style
fpga: Fix debug message compilation error
cmd: fpga: Clean coding style
cmd: fpga: Move fpga_loadbitstream to fpga.c
fpga: Change the first parameter in fpga_loadbitstream
cmd: fpga: Do not include net.h
fpga: zynq: Add support for loading bitstream
fpga: Check device name against bitstream name
fpga: Remove all CONFIG_SYS_* fpga related options
arch/arm/cpu/armv7/zynq/slcr.c | 35 +++
arch/arm/include/asm/arch-zynq/hardware.h | 10 +-
arch/arm/include/asm/arch-zynq/sys_proto.h | 3 +
board/xilinx/zynq/board.c | 37 +++
common/cmd_fpga.c | 254 +++--
drivers/fpga/Makefile | 1 +
drivers/fpga/fpga.c| 225 +-
drivers/fpga/xilinx.c | 146
drivers/fpga/zynqpl.c | 355 +
include/altera.h | 17 --
include/configs/M54455EVB.h| 2 +-
include/configs/MERGERBOX.h| 2 +-
include/configs/MVBC_P.h | 2 +-
include/configs/MVBLM7.h | 2 +-
include/configs/MVSMR.h| 2 +-
include/configs/omap3_mvblx.h | 2 +-
include/configs/zynq.h | 6 +
include/fpga.h | 13 +-
include/lattice.h | 3 -
include/xilinx.h | 25 +-
include/zynqpl.h | 59 +
21 files changed, 848 insertions(+), 353 deletions(-)
create mode 100644 drivers/fpga/zynqpl.c
create mode 100644 include/zynqpl.h
--
1.8.2.1
pgp7I5fLp0Nfb.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/9] fpga: Clean coding style
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3: None
Changes in v2:
- Fix compilation warnings
drivers/fpga/fpga.c | 216
1 file changed, 98 insertions(+), 118 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 26d2443..ddebd49 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -22,122 +22,99 @@
*
*/
-/*
- * Generic FPGA support
- */
+/* Generic FPGA support */
#include common.h /* core U-Boot definitions */
#include xilinx.h /* xilinx specific definitions */
#include altera.h /* altera specific definitions */
#include lattice.h
-#if 0
-#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
-#endif
-
/* Local definitions */
#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES5
#endif
-/* Enable/Disable debug console messages */
-#ifdef FPGA_DEBUG
-#definePRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#definePRINTF(fmt,args...)
-#endif
-
/* Local static data */
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
-/* Local static functions */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn );
-static int fpga_dev_info( int devnum );
-
-
-/* - */
-
-/* fpga_no_sup
+/*
+ * fpga_no_sup
* 'no support' message function
*/
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(char *fn, char *msg)
{
- if ( fn msg ) {
- printf( %s: No support for %s.\n, fn, msg);
- } else if ( msg ) {
- printf( No support for %s.\n, msg);
- } else {
- printf( No FPGA suport!\n);
- }
+ if (fn msg)
+ printf(%s: No support for %s.\n, fn, msg);
+ else if (msg)
+ printf(No support for %s.\n, msg);
+ else
+ printf(No FPGA suport!\n);
}
/* fpga_get_desc
* map a device number to a descriptor
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_get_desc( int devnum )
+static const fpga_desc *const fpga_get_desc(int devnum)
{
- fpga_desc *desc = (fpga_desc * )NULL;
+ fpga_desc *desc = (fpga_desc *)NULL;
- if (( devnum = 0 ) (devnum next_desc )) {
+ if ((devnum = 0) (devnum next_desc)) {
desc = desc_table[devnum];
- PRINTF( %s: found fpga descriptor #%d @ 0x%p\n,
- __FUNCTION__, devnum, desc );
+ debug(%s: found fpga descriptor #%d @ 0x%p\n,
+ __func__, devnum, desc);
}
return desc;
}
-
-/* fpga_validate
+/*
+ * fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__))
fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn )
+static const fpga_desc *const fpga_validate(int devnum, const void *buf,
+size_t bsize, char *fn)
{
- fpga_desc * desc = fpga_get_desc( devnum );
+ const fpga_desc *desc = fpga_get_desc(devnum);
- if ( !desc ) {
- printf( %s: Invalid device number %d\n, fn, devnum );
- }
+ if (!desc)
+ printf(%s: Invalid device number %d\n, fn, devnum);
- if ( !buf ) {
- printf( %s: Null buffer.\n, fn );
+ if (!buf) {
+ printf(%s: Null buffer.\n, fn);
return (fpga_desc * const)NULL;
}
return desc;
}
-
-/* fpga_dev_info
+/*
+ * fpga_dev_info
* generic multiplexing code
*/
-static int fpga_dev_info( int devnum )
+static int fpga_dev_info(int devnum)
{
- int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ int ret_val = FPGA_FAIL; /* assume failure */
+ const fpga_desc * const desc = fpga_get_desc(devnum);
- if ( desc ) {
- PRINTF( %s: Device Descriptor @ 0x%p\n,
- __FUNCTION__, desc-devdesc );
+ if (desc) {
+ debug(%s: Device Descriptor @ 0x%p\n,
+ __func__, desc-devdesc);
- switch ( desc-devtype ) {
+ switch (desc-devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- printf( Xilinx Device\nDescriptor @ 0x%p\n, desc );
- ret_val = xilinx_info( desc-devdesc );
+ printf(Xilinx Device\nDescriptor @ 0x%p
[U-Boot] [PATCH v3 2/9] fpga: Fix debug message compilation error
CONFIG_FPGA in past was a bitfield where bits were use for vendor identification. This fix should be the part of this commit: Improve configuration of FPGA subsystem (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184) Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v3: None Changes in v2: - Fix grammer in the commit message drivers/fpga/fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index ddebd49..43bdf4f 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -145,7 +145,7 @@ void fpga_init(void) next_desc = 0; memset(desc_table, 0, sizeof(desc_table)); - debug(%s: CONFIG_FPGA = 0x%x\n, __func__, CONFIG_FPGA); + debug(%s\n, __func__); } /* -- 1.8.2.1 pgpK3qmqqokDg.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 6/9] cmd: fpga: Do not include net.h
There is no reason to include net.h header in fpga code. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v3: None Changes in v2: None common/cmd_fpga.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index aa14ceb..5e1d037 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -27,9 +27,6 @@ */ #include common.h #include command.h -#if defined(CONFIG_CMD_NET) -#include net.h -#endif #include fpga.h #include malloc.h -- 1.8.2.1 pgpQsWFeI5g4S.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/9] cmd: fpga: Clean coding style
No functional changes.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3: None
Changes in v2: None
I had to shorten some debug messages and divide them
to two parts to pass checkpatch.
---
common/cmd_fpga.c | 213 +++---
1 file changed, 107 insertions(+), 106 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 1834246..f3579bb 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -34,7 +34,7 @@
#include malloc.h
/* Local functions */
-static int fpga_get_op (char *opstr);
+static int fpga_get_op(char *opstr);
/* Local defines */
#define FPGA_NONE -1
@@ -45,7 +45,7 @@ static int fpga_get_op (char *opstr);
#define FPGA_LOADMK 4
/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
+int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
unsigned int length;
@@ -58,38 +58,36 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
dataptr = (unsigned char *)fpgadata;
/* skip the first bytes of the bitsteam, their meaning is unknown */
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- dataptr+=length;
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ dataptr += length;
/* get design name (identifier, length, string) */
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
if (*dataptr++ != 0x61) {
- debug(%s: Design name identifier not recognized
- in bitstream\n,
- __func__);
+ debug(%s: Design name id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( design filename = \%s\\n, buffer);
/* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) {
- printf(%s: Part number identifier not recognized
- in bitstream\n,
- __func__);
+ printf(%s: Part number id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ length = (*dataptr 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( part number = \%s\\n, buffer);
@@ -101,35 +99,35 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
}
length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( date = \%s\\n, buffer);
/* get time (identifier, length, string) */
if (*dataptr++ != 0x64) {
printf(%s: Time identifier not recognized in bitstream\n,
- __func__);
+ __func__);
return FPGA_FAIL;
}
length = (*dataptr 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;ilength;i++)
+ dataptr += 2;
+ for (i = 0; i length; i++)
buffer[i] = *dataptr++;
printf( time = \%s\\n, buffer);
/* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) {
- printf(%s: Data length identifier not recognized in
bitstream\n,
- __func__);
+ printf(%s: Data length id not recognized in bitstream\n,
+ __func__);
return FPGA_FAIL;
}
- swapsize = ((unsigned int) *dataptr 24) +
- ((unsigned int) *(dataptr+1) 16) +
- ((unsigned int) *(dataptr+2) 8 ) +
- ((unsigned int) *(dataptr+3) ) ;
- dataptr+=4;
+ swapsize = ((unsigned int) *dataptr 24) +
+ ((unsigned int) *(dataptr + 1) 16) +
+ ((unsigned int) *(dataptr + 2) 8) +
+ ((unsigned int) *(dataptr + 3));
+ dataptr += 4;
printf( bytes in bitstream = %d\n, swapsize);
rc = fpga_load(dev, dataptr, swapsize);
@@ -148,81 +146,81 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata,
size_t size)
* If there is no data addr field, the fpgadata environment variable is used.
* The info command requires no data address field.
*/
-int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv
[U-Boot] [PATCH v3 4/9] cmd: fpga: Move fpga_loadbitstream to fpga.c
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- Setup fpga_loadbitstream as weak function
Changes in v2: None
common/cmd_fpga.c | 94 ---
drivers/fpga/fpga.c | 9 +
drivers/fpga/xilinx.c | 86 ++
include/fpga.h| 1 +
4 files changed, 96 insertions(+), 94 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index f3579bb..aa14ceb 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -44,100 +44,6 @@ static int fpga_get_op(char *opstr);
#define FPGA_DUMP 3
#define FPGA_LOADMK 4
-/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
-{
-#if defined(CONFIG_FPGA_XILINX)
- unsigned int length;
- unsigned int swapsize;
- char buffer[80];
- unsigned char *dataptr;
- unsigned int i;
- int rc;
-
- dataptr = (unsigned char *)fpgadata;
-
- /* skip the first bytes of the bitsteam, their meaning is unknown */
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- dataptr += length;
-
- /* get design name (identifier, length, string) */
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- if (*dataptr++ != 0x61) {
- debug(%s: Design name id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
-
- printf( design filename = \%s\\n, buffer);
-
- /* get part number (identifier, length, string) */
- if (*dataptr++ != 0x62) {
- printf(%s: Part number id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr + 1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( part number = \%s\\n, buffer);
-
- /* get date (identifier, length, string) */
- if (*dataptr++ != 0x63) {
- printf(%s: Date identifier not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr+1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( date = \%s\\n, buffer);
-
- /* get time (identifier, length, string) */
- if (*dataptr++ != 0x64) {
- printf(%s: Time identifier not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr 8) + *(dataptr+1);
- dataptr += 2;
- for (i = 0; i length; i++)
- buffer[i] = *dataptr++;
- printf( time = \%s\\n, buffer);
-
- /* get fpga data length (identifier, length) */
- if (*dataptr++ != 0x65) {
- printf(%s: Data length id not recognized in bitstream\n,
- __func__);
- return FPGA_FAIL;
- }
- swapsize = ((unsigned int) *dataptr 24) +
- ((unsigned int) *(dataptr + 1) 16) +
- ((unsigned int) *(dataptr + 2) 8) +
- ((unsigned int) *(dataptr + 3));
- dataptr += 4;
- printf( bytes in bitstream = %d\n, swapsize);
-
- rc = fpga_load(dev, dataptr, swapsize);
- return rc;
-#else
- printf(Bitstream support only for Xilinx devices\n);
- return FPGA_FAIL;
-#endif
-}
-
/* - */
/* command form:
* fpga op device number data addr datasize
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 43bdf4f..f0253bf 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -188,6 +188,15 @@ int fpga_add(fpga_type devtype, void *desc)
}
/*
+ * Convert bitstream data and load into the fpga
+ */
+int __weak fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
+{
+ printf(Bitstream support not implemented for this FPGA device\n);
+ return FPGA_FAIL;
+}
+
+/*
* Generic multiplexing code
*/
int fpga_load(int devnum, const void *buf, size_t bsize)
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 32787b2..7d0342a 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -48,6 +48,92 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn);
/* - */
+int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
+{
+ unsigned int length
[U-Boot] [PATCH v3 5/9] fpga: Change the first parameter in fpga_loadbitstream
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this series
Changes in v2: None
drivers/fpga/fpga.c | 2 +-
drivers/fpga/xilinx.c | 4 ++--
include/fpga.h| 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index f0253bf..244f503 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -190,7 +190,7 @@ int fpga_add(fpga_type devtype, void *desc)
/*
* Convert bitstream data and load into the fpga
*/
-int __weak fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
+int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
{
printf(Bitstream support not implemented for this FPGA device\n);
return FPGA_FAIL;
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 7d0342a..df5f9bf 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -48,7 +48,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn);
/* - */
-int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size)
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
{
unsigned int length;
unsigned int swapsize;
@@ -131,7 +131,7 @@ int fpga_loadbitstream(unsigned long dev, char *fpgadata,
size_t size)
dataptr += 4;
printf( bytes in bitstream = %d\n, swapsize);
- return fpga_load(dev, dataptr, swapsize);
+ return fpga_load(devnum, dataptr, swapsize);
}
int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
diff --git a/include/fpga.h b/include/fpga.h
index 0d01e04..38f62c0 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -68,7 +68,7 @@ extern void fpga_init(void);
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
extern int fpga_load(int devnum, const void *buf, size_t bsize);
-extern int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size);
+extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
--
1.8.2.1
pgpZTl7MNSGGO.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 7/9] fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger joe.hershber...@ni.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3: None
Changes in v2:
- Fix bugs reported by Tom Rini
- Fix checkpatch warnings (fpga)
- Fix comments (fpga)
- Do not use CamelCase for XilinxZynq (fpga)
- Move to fpga series and extend this driver
This patch was the part of zynq series but I have decided
to extend it with partial bitstream support, loadb support
and create separate patchset just for fpga patches.
The origin patch was reviewed by Tom Rini.
---
arch/arm/cpu/armv7/zynq/slcr.c | 35 +++
arch/arm/include/asm/arch-zynq/hardware.h | 10 +-
arch/arm/include/asm/arch-zynq/sys_proto.h | 3 +
board/xilinx/zynq/board.c | 37 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/xilinx.c | 37 +++
drivers/fpga/zynqpl.c | 355 +
include/configs/zynq.h | 6 +
include/xilinx.h | 4 +
include/zynqpl.h | 59 +
10 files changed, 545 insertions(+), 2 deletions(-)
create mode 100644 drivers/fpga/zynqpl.c
create mode 100644 include/zynqpl.h
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 5a8674a..52048c6 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -28,6 +28,9 @@
#define SLCR_LOCK_MAGIC0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000
+#define SLCR_IDCODE_SHIFT 12
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
@@ -87,3 +90,35 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
out:
zynq_slcr_lock();
}
+
+void zynq_slcr_devcfg_disable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Disable AXI interface */
+ writel(0x, slcr_base-fpga_rst_ctrl);
+
+ /* Set Level Shifters DT618760 */
+ writel(0xA, slcr_base-lvl_shftr_en);
+
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Set Level Shifters DT618760 */
+ writel(0xF, slcr_base-lvl_shftr_en);
+
+ /* Disable AXI interface */
+ writel(0x0, slcr_base-fpga_rst_ctrl);
+
+ zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+ return (readl(slcr_base-pss_idcode) SLCR_IDCODE_MASK)
+ SLCR_IDCODE_SHIFT;
+}
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 6af892a..8b8a91a 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -53,11 +53,17 @@ struct slcr_regs {
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h
b/arch/arm/include/asm/arch-zynq/sys_proto.h
index af9e7f8..2317121 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -27,6 +27,9 @@ extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 1589d21..b02c364 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -22,15 +22,52 @@
#include common.h
#include netdev.h
+#include zynqpl.h
#include asm/arch/hardware.h
#include asm/arch/sys_proto.h
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FPGA
+Xilinx_desc fpga;
+
+/* It can be done differently */
+Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+#endif
+
int board_init(void)
{
+#ifdef CONFIG_FPGA
+ u32 idcode;
+
+ idcode = zynq_slcr_get_idcode();
+
+ switch (idcode) {
+ case
[U-Boot] [PATCH v3 8/9] fpga: Check device name against bitstream name
Ensure that wrong bitstream won't be loaded
to current device.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- Rebase because of change in previous patch
- fpga_validate should be global function
- fix one printf function
- change parameter name according to previous patch dev-devnum
Changes in v2:
- New patch in this series
drivers/fpga/fpga.c | 4 ++--
drivers/fpga/xilinx.c | 23 +++
include/fpga.h| 2 ++
include/xilinx.h | 1 +
include/zynqpl.h | 8
5 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 244f503..f70bff6 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -72,8 +72,8 @@ static const fpga_desc *const fpga_get_desc(int devnum)
* fpga_validate
* generic parameter checking code
*/
-static const fpga_desc *const fpga_validate(int devnum, const void *buf,
-size_t bsize, char *fn)
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+size_t bsize, char *fn)
{
const fpga_desc *desc = fpga_get_desc(devnum);
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 496aa2f..49e9437 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -30,6 +30,7 @@
*/
#include common.h
+#include fpga.h
#include virtex2.h
#include spartan2.h
#include spartan3.h
@@ -58,8 +59,14 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t
size)
char buffer[80];
unsigned char *dataptr;
unsigned int i;
+ const fpga_desc *desc;
+ Xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata;
+ /* Find out fpga_description */
+ desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
+ /* Assign xilinx device description */
+ xdesc = desc-devdesc;
/* skip the first bytes of the bitsteam, their meaning is unknown */
length = (*dataptr 8) + *(dataptr + 1);
@@ -93,6 +100,20 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t
size)
dataptr += 2;
for (i = 0; i length; i++)
buffer[i] = *dataptr++;
+
+ if (xdesc-name) {
+ i = strncmp(buffer, xdesc-name, strlen(xdesc-name));
+ if (i) {
+ printf(%s: Wrong bitstream ID for this device\n,
+ __func__);
+ printf(%s: Bitstream ID %s, current device ID %d/%s\n,
+ __func__, buffer, devnum, xdesc-name);
+ return FPGA_FAIL;
+ }
+ } else {
+ printf(%s: Please fill correct device ID to Xilinx_desc\n,
+ __func__);
+ }
printf( part number = \%s\\n, buffer);
/* get date (identifier, length, string) */
@@ -306,6 +327,8 @@ int xilinx_info (Xilinx_desc * desc)
printf (Device Size: \t%d bytes\n
Cookie:\t0x%x (%d)\n,
desc-size, desc-cookie, desc-cookie);
+ if (desc-name)
+ printf(Device name: \t%s\n, desc-name);
if (desc-iface_fns) {
printf (Device Function Table @ 0x%p\n,
desc-iface_fns);
diff --git a/include/fpga.h b/include/fpga.h
index 38f62c0..ebefba8 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -71,5 +71,7 @@ extern int fpga_load(int devnum, const void *buf, size_t
bsize);
extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
+extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
+ size_t bsize, char *fn);
#endif /* _FPGA_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
index 592cbea..bcfe76d 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -81,6 +81,7 @@ typedef struct { /* typedef Xilinx_desc */
size_t size;/* bytes of data part can accept */
void *iface_fns;/* interface function table */
int cookie; /* implementation specific cookie */
+ char *name; /* device name in bitstream */
} Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions
diff --git a/include/zynqpl.h b/include/zynqpl.h
index bc9b948..0247ef6 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -45,15 +45,15 @@ extern int zynq_info(Xilinx_desc *desc);
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, 7z010 }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie
[U-Boot] [PATCH v3 9/9] fpga: Remove all CONFIG_SYS_* fpga related options
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v3:
- New patch in this series
Changes in v2: None
include/altera.h | 17 -
include/configs/M54455EVB.h | 2 +-
include/configs/MERGERBOX.h | 2 +-
include/configs/MVBC_P.h | 2 +-
include/configs/MVBLM7.h | 2 +-
include/configs/MVSMR.h | 2 +-
include/configs/omap3_mvblx.h | 2 +-
include/fpga.h| 10 --
include/lattice.h | 3 ---
include/xilinx.h | 24
10 files changed, 6 insertions(+), 60 deletions(-)
diff --git a/include/altera.h b/include/altera.h
index 7a2bece..6aad5ee 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -27,23 +27,6 @@
#ifndef _ALTERA_H_
#define _ALTERA_H_
-/* Altera Model definitions
- */
-#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA |
CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA |
CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA |
CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- */
-#define CONFIG_SYS_ALTERA_IF_PSCONFIG_SYS_FPGA_IF( 0x1 ) /*
passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast
passive parallel */
-/* Add new interfaces here */
-
typedef enum { /* typedef Altera_iface */
min_altera_iface_type, /* insert all new types after this */
passive_serial, /* serial data and external clock */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 1bc2c5a..536b755 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -238,7 +238,7 @@
/* FPGA - Spartan 2 */
/* experiment
-#define CONFIG_FPGACONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index c296e3c..30fb6c2 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -606,7 +606,7 @@
* FPGA
*/
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGACONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 6850965..7271468 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -310,7 +310,7 @@
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGACONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA 1
#define CONFIG_FPGA_CYCLON21
#define CONFIG_FPGA_COUNT 1
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index a99ad3c..a9c00ac 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -499,7 +499,7 @@
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGACONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index bf2f44e..5d2ff14 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -280,7 +280,7 @@
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGACONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX 1
#define CONFIG_FPGA_SPARTAN2 1
#define CONFIG_FPGA_COUNT 1
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 376a3d0..f9adc01 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -273,7 +273,7 @@
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
diff --git a/include/fpga.h b/include/fpga.h
index ebefba8..38e9018 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -31,16 +31,6 @@
#define CONFIG_MAX_FPGA_DEVICES5
#endif
-/* CONFIG_FPGA bit assignments */
-#define CONFIG_SYS_FPGA_MAN(x) (x)
-#define CONFIG_SYS_FPGA_DEV(x) ((x) 8 )
-#define CONFIG_SYS_FPGA_IF(x) ((x) 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 )
-#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN
[U-Boot] [PATCH 1/2] microblaze: bootm: Fix coding style issues
Prepare place for new patch.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/microblaze/lib/bootm.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 66d21f4..b992a4d 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -32,11 +32,12 @@
DECLARE_GLOBAL_DATA_PTR;
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t
*images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
/* First parameter is mapped to $r5 for kernel boot args */
- void(*theKernel) (char *, ulong, ulong);
- char*commandline = getenv (bootargs);
+ void(*thekernel) (char *, ulong, ulong);
+ char*commandline = getenv(bootargs);
ulong rd_data_start, rd_data_end;
if ((flag != 0) (flag != BOOTM_STATE_OS_GO))
@@ -51,10 +52,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
of_flat_tree = images-ft_addr;
#endif
- theKernel = (void (*)(char *, ulong, ulong))images-ep;
+ thekernel = (void (*)(char *, ulong, ulong))images-ep;
/* find ramdisk */
- ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_MICROBLAZE,
+ ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
rd_data_start, rd_data_end);
if (ret)
return 1;
@@ -64,9 +65,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
if (!of_flat_tree argc 3)
of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
#ifdef DEBUG
- printf (## Transferring control to Linux (at address 0x%08lx) \
- ramdisk 0x%08lx, FDT 0x%08lx...\n,
- (ulong) theKernel, rd_data_start, (ulong) of_flat_tree);
+ printf(## Transferring control to Linux (at address 0x%08lx) ,
+ (ulong)thekernel);
+ printf(ramdisk 0x%08lx, FDT 0x%08lx...\n,
+ rd_data_start, (ulong) of_flat_tree);
#endif
#ifdef XILINX_USE_DCACHE
@@ -78,7 +80,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
* r6: pointer to ramdisk
* r7: pointer to the fdt, followed by the board info data
*/
- theKernel (commandline, rd_data_start, (ulong) of_flat_tree);
+ thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
/* does not return */
return 1;
--
1.8.2.1
pgprXnWHKIFFu.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] microblaze: bootm: Add support for loading initrd
fdt_initrd add additional information to DTB about initrd addresses which are later used by kernel. Signed-off-by: Michal Simek michal.si...@xilinx.com --- arch/microblaze/lib/bootm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index b992a4d..bb01a71 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -64,6 +64,11 @@ int do_bootm_linux(int flag, int argc, char * const argv[], if (!of_flat_tree argc 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); + + /* fixup the initrd now that we know where it should be */ + if (images-rd_start images-rd_end of_flat_tree) + fdt_initrd(of_flat_tree, images-rd_start, images-rd_end, 1); + #ifdef DEBUG printf(## Transferring control to Linux (at address 0x%08lx) , (ulong)thekernel); -- 1.8.2.1 pgptnS3dEVBgu.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - fpga
Hi Tom and Albert, I have created fpga branch. It is based on zynq patches(and request) I sent last week. The reason why it is based on it is that new zynq fpga driver and changes in zynq I have done. Just talk to each other and be aware that this fpga patchset is based on zynq one. Thanks, Michal The following changes since commit 8934f7846501070a5b01c1fab5db27559e9d70d1: i2c: zynq: Add support for Xilinx Zynq (2013-04-30 11:39:28 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git fpga for you to fetch changes up to b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c: fpga: Remove all CONFIG_SYS_* fpga related options (2013-05-06 10:41:30 +0200) Michal Simek (9): fpga: Clean coding style fpga: Fix debug message compilation error cmd: fpga: Clean coding style cmd: fpga: Move fpga_loadbitstream to fpga.c fpga: Change the first parameter in fpga_loadbitstream cmd: fpga: Do not include net.h fpga: zynq: Add support for loading bitstream fpga: Check device name against bitstream name fpga: Remove all CONFIG_SYS_* fpga related options arch/arm/cpu/armv7/zynq/slcr.c | 35 arch/arm/include/asm/arch-zynq/hardware.h | 10 +++- arch/arm/include/asm/arch-zynq/sys_proto.h | 3 + board/xilinx/zynq/board.c | 37 common/cmd_fpga.c | 254 ++--- drivers/fpga/Makefile | 1 + drivers/fpga/fpga.c| 225 +++- drivers/fpga/xilinx.c | 146 +++ drivers/fpga/zynqpl.c | 355 ++ include/altera.h | 17 -- include/configs/M54455EVB.h| 2 +- include/configs/MERGERBOX.h| 2 +- include/configs/MVBC_P.h | 2 +- include/configs/MVBLM7.h | 2 +- include/configs/MVSMR.h| 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/zynq.h | 6 ++ include/fpga.h | 13 + include/lattice.h | 3 - include/xilinx.h | 25 +--- include/zynqpl.h | 59 +++ 21 files changed, 848 insertions(+), 353 deletions(-) create mode 100644 drivers/fpga/zynqpl.c create mode 100644 include/zynqpl.h -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] microblaze: bootm: Add support for loading initrd
On 05/03/2013 09:26 AM, Michal Simek wrote: fdt_initrd add additional information to DTB about initrd addresses which are later used by kernel. Signed-off-by: Michal Simek michal.si...@xilinx.com --- arch/microblaze/lib/bootm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index b992a4d..bb01a71 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -64,6 +64,11 @@ int do_bootm_linux(int flag, int argc, char * const argv[], if (!of_flat_tree argc 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); + + /* fixup the initrd now that we know where it should be */ + if (images-rd_start images-rd_end of_flat_tree) + fdt_initrd(of_flat_tree, images-rd_start, images-rd_end, 1); Michal: You should also check return value. BTW: it should be also checked for arm and ppc. will send v2. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] microblaze: bootm: Fix coding style issues
Prepare place for new patch.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
arch/microblaze/lib/bootm.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 66d21f4..b992a4d 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -32,11 +32,12 @@
DECLARE_GLOBAL_DATA_PTR;
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t
*images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
{
/* First parameter is mapped to $r5 for kernel boot args */
- void(*theKernel) (char *, ulong, ulong);
- char*commandline = getenv (bootargs);
+ void(*thekernel) (char *, ulong, ulong);
+ char*commandline = getenv(bootargs);
ulong rd_data_start, rd_data_end;
if ((flag != 0) (flag != BOOTM_STATE_OS_GO))
@@ -51,10 +52,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
of_flat_tree = images-ft_addr;
#endif
- theKernel = (void (*)(char *, ulong, ulong))images-ep;
+ thekernel = (void (*)(char *, ulong, ulong))images-ep;
/* find ramdisk */
- ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_MICROBLAZE,
+ ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
rd_data_start, rd_data_end);
if (ret)
return 1;
@@ -64,9 +65,10 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
if (!of_flat_tree argc 3)
of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
#ifdef DEBUG
- printf (## Transferring control to Linux (at address 0x%08lx) \
- ramdisk 0x%08lx, FDT 0x%08lx...\n,
- (ulong) theKernel, rd_data_start, (ulong) of_flat_tree);
+ printf(## Transferring control to Linux (at address 0x%08lx) ,
+ (ulong)thekernel);
+ printf(ramdisk 0x%08lx, FDT 0x%08lx...\n,
+ rd_data_start, (ulong) of_flat_tree);
#endif
#ifdef XILINX_USE_DCACHE
@@ -78,7 +80,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *ima
* r6: pointer to ramdisk
* r7: pointer to the fdt, followed by the board info data
*/
- theKernel (commandline, rd_data_start, (ulong) of_flat_tree);
+ thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
/* does not return */
return 1;
--
1.8.2.1
pgp_hFfJIJS36.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] microblaze: bootm: Add support for loading initrd
fdt_initrd add additional information to DTB about initrd addresses which are later used by kernel. Signed-off-by: Michal Simek michal.si...@xilinx.com --- Changes in v2: - Check return value from fdt_initrd arch/microblaze/lib/bootm.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index b992a4d..3842709 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -64,6 +64,14 @@ int do_bootm_linux(int flag, int argc, char * const argv[], if (!of_flat_tree argc 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); + + /* fixup the initrd now that we know where it should be */ + if (images-rd_start images-rd_end of_flat_tree) + ret = fdt_initrd(of_flat_tree, images-rd_start, +images-rd_end, 1); + if (ret) + return 1; + #ifdef DEBUG printf(## Transferring control to Linux (at address 0x%08lx) , (ulong)thekernel); -- 1.8.2.1 pgpYRme2dmIoT.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH] patman: Do not hardcode python path
Patman requires python 2.7.4 to run but it doesn't need to be placed in /usr/bin/python. Use env to ensure that the interpreter used is the first one on environment's $PATH on system with several versions of Python installed. Signed-off-by: Michal Simek michal.si...@xilinx.com --- tools/patman/patman.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/patman.py b/tools/patman/patman.py index a8061a9..7a317c5 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python # # Copyright (c) 2011 The Chromium OS Authors. # -- 1.8.2.1 pgpiBS5xLFu1U.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] nand onfi 8bit/16bit bus support
Hi guys, Zynq supports 8 and 16bit ONFI nand flashes. We can count number of connected pins and from that we know if 8bit or 16bit nand flash is used. I have looked at the code and contains ONFI detection with correct detection of bus width + checking later. Why also not setup proper chip-options for NAND_BUSWIDTH_16? Not sure how others but if driver expect just ONFI devices and support 8 and 16bit options why not just to setup chip options based on information from ONFI or not check that (busw != (chip-options NAND_BUSWIDTH_16)) for onfi case. Just wanted to get input from you before I will try to create patch to support this. I just want to be sure that I am not doing something what it is wrong for other platforms. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - microblaze
Hi Tom, please pull these two patches to your tree. One fix coding style and the second and support for initrd. Thanks, Michal The following changes since commit fe8e4dbad1d31c452af3fbabba21e72b210381b3: nds32: Use sections header to obtain link symbols (2013-05-08 12:38:10 +0800) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git microblaze for you to fetch changes up to a8425d52885de047fc00019cdf3e697b4d32b67a: microblaze: bootm: Add support for loading initrd (2013-05-09 11:13:44 +0200) Michal Simek (2): microblaze: bootm: Fix coding style issues microblaze: bootm: Add support for loading initrd arch/microblaze/lib/bootm.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request - microblaze
Hi Tom, I were too fast. :-( I forget to add that gpio patch Here is the correct one. I have added that patch on the top of that two. Thanks, Michal The following changes since commit fe8e4dbad1d31c452af3fbabba21e72b210381b3: nds32: Use sections header to obtain link symbols (2013-05-08 12:38:10 +0800) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git microblaze for you to fetch changes up to 4e779ad2e54e39d5343c8c83b4fc686a7bb16859: gpio: Add support for microblaze xilinx GPIO (2013-05-09 11:20:08 +0200) Michal Simek (3): microblaze: bootm: Fix coding style issues microblaze: bootm: Add support for loading initrd gpio: Add support for microblaze xilinx GPIO arch/microblaze/include/asm/gpio.h | 40 + arch/microblaze/lib/bootm.c | 28 ++-- board/xilinx/microblaze-generic/microblaze-generic.c | 17 ++- drivers/gpio/Makefile| 1 + drivers/gpio/xilinx_gpio.c | 364 ++ include/configs/microblaze-generic.h | 3 +- 6 files changed, 405 insertions(+), 48 deletions(-) create mode 100644 drivers/gpio/xilinx_gpio.c On 05/09/2013 11:16 AM, Michal Simek wrote: Hi Tom, please pull these two patches to your tree. One fix coding style and the second and support for initrd. Thanks, Michal The following changes since commit fe8e4dbad1d31c452af3fbabba21e72b210381b3: nds32: Use sections header to obtain link symbols (2013-05-08 12:38:10 +0800) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git microblaze for you to fetch changes up to a8425d52885de047fc00019cdf3e697b4d32b67a: microblaze: bootm: Add support for loading initrd (2013-05-09 11:13:44 +0200) Michal Simek (2): microblaze: bootm: Fix coding style issues microblaze: bootm: Add support for loading initrd arch/microblaze/lib/bootm.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH] arm: lds: Remove libgcc eabi exception handling tables
Remove ARM eabi exception handling tables (for frame unwinding).
AFAICT, u-boot stubs away the frame unwiding routines, so the tables will
more or less just consume space. It should be OK to remove them.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Other options could be to complete u-boot/arch/arm/lib/* so that
libgcc routines with exception handling dont get pulled in. Or
to avoid user code (like the mentioned patch) which causes external
libgcc functions to get pulled in...
---
arch/arm/cpu/u-boot.lds | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index d9bbee3..e139b90 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -106,4 +106,6 @@ SECTIONS
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.ARM.exidx*) }
+ /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}
--
1.8.2.1
pgpSrR8pbvnUC.pgp
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nand onfi 8bit/16bit bus support
On 05/09/2013 11:37 PM, Scott Wood wrote: On 05/06/2013 11:53:52 AM, Michal Simek wrote: Hi guys, Zynq supports 8 and 16bit ONFI nand flashes. We can count number of connected pins and from that we know if 8bit or 16bit nand flash is used. I have looked at the code and contains ONFI detection with correct detection of bus width + checking later. Why also not setup proper chip-options for NAND_BUSWIDTH_16? Not sure how others but if driver expect just ONFI devices and support 8 and 16bit options why not just to setup chip options based on information from ONFI or not check that (busw != (chip-options NAND_BUSWIDTH_16)) for onfi case. This is fixed in current Linux, with NAND_BUSWIDTH_AUTO. There was a patchset to merge in recent Linux MTD code a while back, but an expected respin didn't come. I'll try to fix it up when I process this merge window's patches. Ok. Nice. That will be really helpful. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: lds: Remove libgcc eabi exception handling tables
On 05/10/2013 09:07 PM, Albert ARIBAUD wrote: Hi Michal, On Thu, 9 May 2013 11:35:33 +0200, Michal Simek michal.si...@xilinx.com wrote: Remove ARM eabi exception handling tables (for frame unwinding). AFAICT, u-boot stubs away the frame unwiding routines, so the tables will more or less just consume space. It should be OK to remove them. Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- Other options could be to complete u-boot/arch/arm/lib/* so that libgcc routines with exception handling dont get pulled in. Or to avoid user code (like the mentioned patch) which causes external libgcc functions to get pulled in... Er... which mentioned patch? Ah yeah. Let me give you background. After adding: arm: zynq: U-Boot udelay 1000 FIX (sha1: d54cc007878697a92e7f696b71a3eb203c0386e2) we have found that new program header is added to u-boot for zynq. Program Header: 0x7001 off0x000405fc vaddr 0x040385fc paddr 0x040385fc align 2**2 filesz 0x0020 memsz 0x0020 flags r-- LOAD off0x8000 vaddr 0x0400 paddr 0x0400 align 2**15 filesz 0x00041240 memsz 0x00041240 flags rwx STACK off0x vaddr 0x paddr 0x align 2**2 filesz 0x memsz 0x flags rwx Tracing down this we found that uldivmod is used 27: 0 NOTYPE GLOBAL DEFAULT UND __aeabi_uldivmod Based on that Edgar proposed this patch. After my experiment we can also use the patch below to fix it because external libgcc functions are not pulled it. But probably removing that ARM eabi exception handling tables is better solution then try to change code not to use it. But for me it is no problem to send the patch below to fix this problem. Thanks, Michal diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c index 1b56373..4b26e96 100644 --- a/arch/arm/cpu/armv7/zynq/timer.c +++ b/arch/arm/cpu/armv7/zynq/timer.c @@ -118,12 +118,13 @@ void __udelay(unsigned long usec) u32 timeend; u32 timediff; u32 timenow; + u64 temp; if (usec == 0) return; - countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) / - 100); + temp = (TIMER_TICK_HZ * usec) / 100; + countticks = (u32)temp; /* decrementing timer */ timeend = readl(timer_base-counter) - countticks; -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: lds: Remove libgcc eabi exception handling tables
Hi Albert, On 05/14/2013 05:44 PM, Albert ARIBAUD wrote: Hi Michal, On Mon, 13 May 2013 09:45:12 +0200, Michal Simek mon...@monstr.eu wrote: On 05/10/2013 09:07 PM, Albert ARIBAUD wrote: Hi Michal, On Thu, 9 May 2013 11:35:33 +0200, Michal Simek michal.si...@xilinx.com wrote: Remove ARM eabi exception handling tables (for frame unwinding). AFAICT, u-boot stubs away the frame unwiding routines, so the tables will more or less just consume space. It should be OK to remove them. Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com --- Other options could be to complete u-boot/arch/arm/lib/* so that libgcc routines with exception handling dont get pulled in. Or to avoid user code (like the mentioned patch) which causes external libgcc functions to get pulled in... Er... which mentioned patch? Ah yeah. Let me give you background. After adding: arm: zynq: U-Boot udelay 1000 FIX (sha1: d54cc007878697a92e7f696b71a3eb203c0386e2) we have found that new program header is added to u-boot for zynq. Program Header: 0x7001 off0x000405fc vaddr 0x040385fc paddr 0x040385fc align 2**2 filesz 0x0020 memsz 0x0020 flags r-- LOAD off0x8000 vaddr 0x0400 paddr 0x0400 align 2**15 filesz 0x00041240 memsz 0x00041240 flags rwx STACK off0x vaddr 0x paddr 0x align 2**2 filesz 0x memsz 0x flags rwx Tracing down this we found that uldivmod is used 27: 0 NOTYPE GLOBAL DEFAULT UND __aeabi_uldivmod Based on that Edgar proposed this patch. Ok, so Michal and I just did some fiddling with zynq builds and *exidx* sections. By default the *exidx* sections are between rodata and data, so removing them causes many apparent changes at the binary level. However, builds of zynq based on ARM master with the patch above vs master with a patch mapping *exidx* sections after BSS gives identical binaries. Thus the RFC has no functional effect. Also, ARM EHABI states that [exception] Tables are not required for ABI compliance at the C/Assembler level but are required for C++. http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038a/IHI0038A_ehabi.pdf So as long as we don't put any C++ code in U-Boot (a prospect that I don't see happening any time soon), this RFC is safe and either is a no-op or removes useless bytes from the binary. Any update on this? Have you decided to add or not to add to this release? If you I need to fix zynq timer code do not use exception handling table. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/8] sf: winbond: Update the names for W25Q 0x40XX ID's flash parts
move this discussion back to mailing list. On 06/05/2013 05:56 PM, Jagan Teki wrote: And are your ok with below representation for common id's parts ? + .name = W25Q80BL/W25Q80BV, + .name = W25Q16CL/W25Q16DV, + .name = W25Q32BV/W25Q32FV_SPI, + .name = W25Q64CV/W25Q64FV_SPI, + .name = W25Q128BV/W25Q128FV_SPI, + .name = W25Q32DW/W25Q32FV_QPI, + .name = W25Q64DW/W25Q64FV_QPI, + .name = W25Q128FW/W25Q128FV_QPI, Any comments on above representation of part names, as the id's to these pairs are common. This will enhance u-boot sf to support all parts from winbond, but seems like different view of names. what's the difference between that parts? parts were diff in terms of voltages and sone SPI and QPI configurations. but from the manufacture defeat, pair of parts were same ID's ok. Does software care if it is W25G80BL or BV? Or software behaviour is the same and there is only difference in voltage or so. SW is same even if it 1.8 or 3.3 v. The only reason for giving the pair of names to support all different parts You are supporting them but you are just not list them. I don't care about it so much but it is increase u-boot size. Why does u-boot size increase, is it because of below representation on name filed = W25Q80BL/W25Q80BV Just because of longer names which go probably to rodata section. It is not a problem for me at all. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - sf tree
Hi Mike and Tom, please pull these sf changes to your tree. Tom: I have sent private email to Mike but I haven't got any response from him. Also I haven't got reactions on mailing list. That's why I am not sure if Mike still cares about this subsystem. If not, please let me know who is responsible for it or just add these patches to your tree. Thanks, Michal The following changes since commit 6ad77d88e57f6ab815ec7e85c5ac329054318c73: Marek Vasut (1): vfat: Fix mkcksum argument sizes are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git mainline/sf Jagannadha Sutradharudu Teki (7): sf: spansion: Correct the first byte of idcode1 for S25FL256S part sf: winbond: Add W25Q64W sf: stmicro: Add support for N25Q64 sf: stmicro: Add support for N25Q64A sf: stmicro: Add support for N25Q32 sf: stmicro: Add support for N25Q32A sf: stmicro: Add support for N25Q256A drivers/mtd/spi/spansion.c |2 +- drivers/mtd/spi/stmicro.c | 30 ++ drivers/mtd/spi/winbond.c |5 + 3 files changed, 36 insertions(+), 1 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - microblaze
Hi Tom, please pull all these changes to your tree. The major change is remove really ancient i2c driver + helper files for this driver. Thanks, Michal The following changes since commit 6ad77d88e57f6ab815ec7e85c5ac329054318c73: Marek Vasut (1): vfat: Fix mkcksum argument sizes are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Alexey Brodkin (1): block: systemace: Added missing else in ace_writew David Holsgrove (1): microblaze: Add muldi3.c which contains routines for _muldi3 Jason Wu (1): spi: xilinx_spi: Perform software reset during slave setup Michal Simek (5): common: cmd_bdinfo: Fix bdinfo to show all MACs for Microblaze and ARM board: xilinx: Remove unused ancient i2c driver board: xilinx: Remove common folder common: cmd_bdinfo: Fix compilation warning for microblaze microblaze: Remove FSL support from generic board arch/microblaze/lib/Makefile |1 + arch/microblaze/lib/muldi3.c | 91 ++ board/xilinx/common/xbasic_types.c | 165 --- board/xilinx/common/xbasic_types.h | 283 - board/xilinx/common/xbuf_descriptor.h | 252 board/xilinx/common/xdma_channel.c | 738 --- board/xilinx/common/xdma_channel.h | 291 - board/xilinx/common/xdma_channel_i.h | 110 -- board/xilinx/common/xdma_channel_sg.c | 1317 board/xilinx/common/xio.h | 81 -- board/xilinx/common/xipif_v1_23_b.c| 331 - board/xilinx/common/xipif_v1_23_b.h| 746 --- board/xilinx/common/xpacket_fifo_v1_00_b.c | 448 --- board/xilinx/common/xpacket_fifo_v1_00_b.h | 306 - board/xilinx/common/xstatus.h | 347 - board/xilinx/common/xversion.c | 350 -- board/xilinx/common/xversion.h | 97 -- .../xilinx/microblaze-generic/microblaze-generic.c | 20 - board/xilinx/xilinx_iic/xiic_l.c | 484 --- board/xilinx/xilinx_iic/xiic_l.h | 150 --- board/xilinx/zynq/Makefile |3 - common/cmd_bdinfo.c| 27 +- drivers/block/systemace.c |4 +- drivers/spi/xilinx_spi.c |2 + drivers/spi/xilinx_spi.h |3 + include/configs/microblaze-generic.h |4 - 26 files changed, 121 insertions(+), 6530 deletions(-) create mode 100644 arch/microblaze/lib/muldi3.c delete mode 100644 board/xilinx/common/xbasic_types.c delete mode 100644 board/xilinx/common/xbasic_types.h delete mode 100644 board/xilinx/common/xbuf_descriptor.h delete mode 100644 board/xilinx/common/xdma_channel.c delete mode 100644 board/xilinx/common/xdma_channel.h delete mode 100644 board/xilinx/common/xdma_channel_i.h delete mode 100644 board/xilinx/common/xdma_channel_sg.c delete mode 100644 board/xilinx/common/xio.h delete mode 100644 board/xilinx/common/xipif_v1_23_b.c delete mode 100644 board/xilinx/common/xipif_v1_23_b.h delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.c delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.h delete mode 100644 board/xilinx/common/xstatus.h delete mode 100644 board/xilinx/common/xversion.c delete mode 100644 board/xilinx/common/xversion.h delete mode 100644 board/xilinx/xilinx_iic/xiic_l.c delete mode 100644 board/xilinx/xilinx_iic/xiic_l.h -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] xilinx: zynq: Enable DCC and create new zynq_dcc board
Enable DCC driver for arm zynq platform to be compiled. Signed-off-by: Michal Simek michal.si...@xilinx.com --- boards.cfg |1 + include/configs/zynq.h |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/boards.cfg b/boards.cfg index 98f7a14..1d30a18 100644 --- a/boards.cfg +++ b/boards.cfg @@ -296,6 +296,7 @@ snowball arm armv7 snowball st-e kzm9garm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq +zynq_dcc arm armv7 zynq xilinx zynqzynq:ZYNQ_DCC socfpga_cyclone5arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 18fd76f..2989e72 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -58,6 +58,11 @@ #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000 +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: zynq: Add SLCR support with system reset
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/Makefile |1 +
arch/arm/cpu/armv7/zynq/cpu.c |2 +
arch/arm/cpu/armv7/zynq/slcr.c | 63
arch/arm/include/asm/arch-zynq/hardware.h | 41 ++
arch/arm/include/asm/arch-zynq/sys_proto.h | 30 +
5 files changed, 137 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/slcr.c
create mode 100644 arch/arm/include/asm/arch-zynq/hardware.h
create mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 499ace4..388085d 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).o
COBJS-y:= timer.o
COBJS-y+= cpu.o
+COBJS-y+= slcr.o
COBJS := $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index ab615cc..91618d3 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,11 +21,13 @@
* MA 02111-1307 USA
*/
#include common.h
+#include asm/arch/sys_proto.h
inline void lowlevel_init(void) {}
void reset_cpu(ulong addr)
{
+ zynq_slcr_cpu_reset();
while (1)
;
}
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644
index 000..788a8fd
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include malloc.h
+#include asm/arch/hardware.h
+
+#define SLCR_LOCK_MAGIC0x767B
+#define SLCR_UNLOCK_MAGIC 0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+ if (!slcr_lock)
+ writel(SLCR_LOCK_MAGIC, slcr_base-slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+ if (slcr_lock)
+ writel(SLCR_UNLOCK_MAGIC, slcr_base-slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+ /*
+* Unlock the SLCR then reset the system.
+* Note that this seems to require raw i/o
+* functions or there's a lockup?
+*/
+ zynq_slcr_unlock();
+
+ /*
+* Clear 0x0F00 bits of reboot status register to workaround
+* the FSBL not loading the bitstream after soft-reboot
+* This is a temporary solution until we know more.
+*/
+ clrbits_le32(slcr_base-reboot_status, 0xF00);
+
+ writel(1, slcr_base-pss_rst_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
new file mode 100644
index 000..ad17b27
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define XPSS_SYS_CTRL_BASEADDR 0xF800
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+ u32 scl; /* 0x0 */
+ u32
[U-Boot] [PATCH 3/3] arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not
require to do it in asm.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 26 +++-
arch/arm/include/asm/arch-zynq/hardware.h | 46 -
2 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 91618d3..e8f4c19 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,9 +21,33 @@
* MA 02111-1307 USA
*/
#include common.h
+#include asm/io.h
#include asm/arch/sys_proto.h
+#include asm/arch/hardware.h
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, scu_base-filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, devcfg_base-unlock);
+ writel(0x, devcfg_base-rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, slcr_base-ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, slcr_base-fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0x, slcr_base-trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, slcr_base-ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, slcr_base-ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index ad17b27..d0c69da 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -24,6 +24,8 @@
#define _ASM_ARCH_HARDWARE_H
#define XPSS_SYS_CTRL_BASEADDR 0xF800
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPSS_SCU_BASEADDR 0xF8F0
/* Reflect slcr offsets */
struct slcr_regs {
@@ -32,10 +34,52 @@ struct slcr_regs {
u32 slcr_unlock; /* 0x8 */
u32 reserved1[125];
u32 pss_rst_ctrl; /* 0x200 */
- u32 reserved2[21];
+ u32 reserved2[15];
+ u32 fpga_rst_ctrl; /* 0x240 */
+ u32 reserved3[5];
u32 reboot_status; /* 0x258 */
+ u32 boot_mode; /* 0x25c */
+ u32 reserved4[116];
+ u32 trust_zone; /* 0x430 */ /* FIXME */
+ u32 reserved5[115];
+ u32 ddr_urgent; /* 0x600 */
+ u32 reserved6[6];
+ u32 ddr_urgent_sel; /* 0x61c */
+ u32 reserved7[188];
+ u32 ocm_cfg; /* 0x910 */
};
#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+struct devcfg_regs {
+ u32 ctrl; /* 0x0 */
+ u32 lock; /* 0x4 */
+ u32 cfg; /* 0x8 */
+ u32 int_sts; /* 0xc */
+ u32 int_mask; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 dma_src_addr; /* 0x18 */
+ u32 dma_dst_addr; /* 0x1c */
+ u32 dma_src_len; /* 0x20 */
+ u32 dma_dst_len; /* 0x24 */
+ u32 rom_shadow; /* 0x28 */
+ u32 reserved1[2];
+ u32 unlock; /* 0x34 */
+ u32 reserved2[18];
+ u32 mctrl; /* 0x80 */
+ u32 reserved3;
+ u32 write_count; /* 0x88 */
+ u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+ u32 reserved1[16];
+ u32 filter_start; /* 0x40 */
+ u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request - microblaze
2013/2/4 Tom Rini tr...@ti.com: On Mon, Feb 04, 2013 at 12:26:08PM +0100, Michal Simek wrote: Hi Tom, please pull all these changes to your tree. The major change is remove really ancient i2c driver + helper files for this driver. Thanks, Michal The following changes since commit 6ad77d88e57f6ab815ec7e85c5ac329054318c73: Marek Vasut (1): vfat: Fix mkcksum argument sizes are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Alexey Brodkin (1): block: systemace: Added missing else in ace_writew David Holsgrove (1): microblaze: Add muldi3.c which contains routines for _muldi3 Jason Wu (1): spi: xilinx_spi: Perform software reset during slave setup Michal Simek (5): common: cmd_bdinfo: Fix bdinfo to show all MACs for Microblaze and ARM board: xilinx: Remove unused ancient i2c driver board: xilinx: Remove common folder common: cmd_bdinfo: Fix compilation warning for microblaze microblaze: Remove FSL support from generic board arch/microblaze/lib/Makefile |1 + arch/microblaze/lib/muldi3.c | 91 ++ board/xilinx/common/xbasic_types.c | 165 --- board/xilinx/common/xbasic_types.h | 283 - board/xilinx/common/xbuf_descriptor.h | 252 board/xilinx/common/xdma_channel.c | 738 --- board/xilinx/common/xdma_channel.h | 291 - board/xilinx/common/xdma_channel_i.h | 110 -- board/xilinx/common/xdma_channel_sg.c | 1317 board/xilinx/common/xio.h | 81 -- board/xilinx/common/xipif_v1_23_b.c| 331 - board/xilinx/common/xipif_v1_23_b.h| 746 --- board/xilinx/common/xpacket_fifo_v1_00_b.c | 448 --- board/xilinx/common/xpacket_fifo_v1_00_b.h | 306 - board/xilinx/common/xstatus.h | 347 - board/xilinx/common/xversion.c | 350 -- board/xilinx/common/xversion.h | 97 -- .../xilinx/microblaze-generic/microblaze-generic.c | 20 - board/xilinx/xilinx_iic/xiic_l.c | 484 --- board/xilinx/xilinx_iic/xiic_l.h | 150 --- board/xilinx/zynq/Makefile |3 - common/cmd_bdinfo.c| 27 +- drivers/block/systemace.c |4 +- drivers/spi/xilinx_spi.c |2 + drivers/spi/xilinx_spi.h |3 + include/configs/microblaze-generic.h |4 - 26 files changed, 121 insertions(+), 6530 deletions(-) create mode 100644 arch/microblaze/lib/muldi3.c delete mode 100644 board/xilinx/common/xbasic_types.c delete mode 100644 board/xilinx/common/xbasic_types.h delete mode 100644 board/xilinx/common/xbuf_descriptor.h delete mode 100644 board/xilinx/common/xdma_channel.c delete mode 100644 board/xilinx/common/xdma_channel.h delete mode 100644 board/xilinx/common/xdma_channel_i.h delete mode 100644 board/xilinx/common/xdma_channel_sg.c delete mode 100644 board/xilinx/common/xio.h delete mode 100644 board/xilinx/common/xipif_v1_23_b.c delete mode 100644 board/xilinx/common/xipif_v1_23_b.h delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.c delete mode 100644 board/xilinx/common/xpacket_fifo_v1_00_b.h delete mode 100644 board/xilinx/common/xstatus.h delete mode 100644 board/xilinx/common/xversion.c delete mode 100644 board/xilinx/common/xversion.h delete mode 100644 board/xilinx/xilinx_iic/xiic_l.c delete mode 100644 board/xilinx/xilinx_iic/xiic_l.h Applied to u-boot/master and sorry about the delay! You are not delayed. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sf: spansion: Correct the first byte of idcode1 for S25FL256S part
Hi, 2013/2/4 Marek Vasut ma...@denx.de: Dear Michal Simek, was this ever applied? I have sent pull request to Tom and Mike. All patches around cf are here. http://git.denx.de/?p=u-boot/u-boot-microblaze.git;a=shortlog;h=refs/heads/mainline/sf Interesting that Tom applied this patch and don't the rest sf: stmicro: add support for N25Q064 Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request for ARM zynq
Hi Albert, please pull these three patches to your arm custodian tree. All of them are related to xilinx zynq. Also after my discussion with Wolfgang Denk I have enabled DCC for zynq because we are using it in one configuration and this driver is not compiled by any platform. Thanks, Michal The following changes since commit d62ef5619c9249772247d6af3b8e65207ae0c871: Jagannadha Sutradharudu Teki (1): sf: stmicro: Add support for N25Q256A are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git mainline/arm Michal Simek (3): xilinx: zynq: Enable DCC and create new zynq_dcc board arm: zynq: Add SLCR support with system reset arm: zynq: Add lowlevel initialization to C arch/arm/cpu/armv7/zynq/Makefile |1 + arch/arm/cpu/armv7/zynq/cpu.c | 28 +- arch/arm/cpu/armv7/zynq/slcr.c | 63 arch/arm/include/asm/arch-zynq/hardware.h | 85 arch/arm/include/asm/arch-zynq/sys_proto.h | 30 ++ boards.cfg |1 + include/configs/zynq.h |5 ++ 7 files changed, 212 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/slcr.c create mode 100644 arch/arm/include/asm/arch-zynq/hardware.h create mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request for ARM zynq
Hi Albert and Tom, can you please look at my pull request? Thanks, Michal 2012/9/13 Michal Simek mon...@monstr.eu: Hi Albert, CC: Joe and Tom a month ago I have sent 4 Xilinx ARM zynq patches to mailing list (v2) (reminder yesterday) and I haven't got any reaction from anybody. The first patches were commented by Joe and problems fixed in the next version. There is one network driver which should require ACK from Joe and others from ARM maintainer. I would like to get these patches to mainline. Albert and Tom: Can you please look at these patches and tell me what you thing? The best will be if you can pull them to your trees. Here are links to patchwork http://patchwork.ozlabs.org/patch/177907/ http://patchwork.ozlabs.org/patch/177908/ http://patchwork.ozlabs.org/patch/177909/ http://patchwork.ozlabs.org/patch/177910/ Thanks, Michal The following changes since commit a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-avr32 are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master-zynq Michal Simek (4): serial: Add Zynq serial driver net: Add driver for Zynq Gem IP arm: Support new Xilinx Zynq platform xilinx: Add new Zynq board arch/arm/cpu/armv7/zynq/Makefile| 52 arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 ++ board/xilinx/zynq/Makefile | 54 board/xilinx/zynq/board.c | 64 + boards.cfg |1 + drivers/net/Makefile|1 + drivers/net/zynq_gem.c | 453 +++ drivers/serial/Makefile |1 + drivers/serial/serial_zynq.c| 200 ++ include/configs/zynq.h | 110 include/netdev.h|2 +- 12 files changed, 1115 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 drivers/net/zynq_gem.c create mode 100644 drivers/serial/serial_zynq.c create mode 100644 include/configs/zynq.h -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/12] cmd_sf: Add support for read and write instructions
2013/3/5 Tom Rini tr...@ti.com: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 03/05/2013 01:34 PM, Jagan Teki wrote: Okay.. what I understand is - Currently, all the flash supported commands are provided to user as choice. what what i suppose to implement. He needs to choose the best option based on what the controller and chip connected supports. I guess your idea is to dynamically perform the fastest read/write command based on fastest command supported by controller and chip. I don't know how to support this. Dang, OK. Any update on this? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sf: spansion: Add support for S25FL256S
Add support for Spansion S25FL256S SPI flash.
Signed-off-by: Michal Simek mon...@monstr.eu
---
drivers/mtd/spi/spansion.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 9a114ac..32b76e0 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -96,6 +96,13 @@ static const struct spansion_spi_flash_params
spansion_spi_flash_table[] = {
.nr_sectors = 256,
.name = S25FL129P_64K,
},
+ {
+ .idcode1 = 0x2019,
+ .idcode2 = 0x4d01,
+ .pages_per_sector = 256,
+ .nr_sectors = 512,
+ .name = S25FL256S,
+ },
};
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: Remove additional config flags
These options are just duplicated from arch/arm/cpu/armv7/config.mk Signed-off-by: Michal Simek mon...@monstr.eu --- arch/arm/cpu/armv7/highbank/config.mk|1 - arch/arm/cpu/armv7/omap-common/config.mk |9 - 2 files changed, 0 insertions(+), 10 deletions(-) delete mode 100644 arch/arm/cpu/armv7/highbank/config.mk diff --git a/arch/arm/cpu/armv7/highbank/config.mk b/arch/arm/cpu/armv7/highbank/config.mk deleted file mode 100644 index 935a147..000 --- a/arch/arm/cpu/armv7/highbank/config.mk +++ /dev/null @@ -1 +0,0 @@ -PLATFORM_CPPFLAGS += -march=armv7-a diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk index c400dcc..217fc14 100644 --- a/arch/arm/cpu/armv7/omap-common/config.mk +++ b/arch/arm/cpu/armv7/omap-common/config.mk @@ -20,15 +20,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v7a. PLATFORM_CPPFLAGS += -march=armv5 -# = -# -# Supply options according to compiler version -# -# = -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Xilinx Zynq platform
Hi, I am sending basic support for new Xilinx Zynq platform. It is new ARM cortex a9 cpu with programmable logic. For more information look at www.xilinx.com/zynq. In future we are going to extend this platform for i2c, spi, mmc, fpga, nand, nor support, and maybe more. These drivers will be send in the next round when this series is applied to mainline. Also this platform can also use all drivers targetted to Microblaze (axi) for example emaclite, axi ethernet, uartlite, ns16550a, etc. As all others Xilinx platforms this is candidate for OF driven configuration. It is tested on ZC702 platform. Thanks for your review. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] net: Add driver for Zynq Gem IP
Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek mon...@monstr.eu
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/Makefile |1 +
drivers/net/xilinx_gem.c | 514 ++
include/netdev.h |1 +
3 files changed, 516 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/xilinx_gem.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 430f90c..e510ffa 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -77,6 +77,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+COBJS-$(CONFIG_XILINX_GEM) += xilinx_gem.o
COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
diff --git a/drivers/net/xilinx_gem.c b/drivers/net/xilinx_gem.c
new file mode 100644
index 000..7c8c14d
--- /dev/null
+++ b/drivers/net/xilinx_gem.c
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2011 Michal Simek
+ *
+ * Michal SIMEK mon...@monstr.eu
+ *
+ * Based on Xilinx gmac driver:
+ * (C) Copyright 2011 Xilinx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include net.h
+#include config.h
+#include malloc.h
+#include asm/io.h
+#include phy.h
+#include miiphy.h
+
+#if !defined(CONFIG_PHYLIB)
+# error XILINX_GEM_ETHERNET requires PHYLIB
+#endif
+
+/* Bit/mask specification */
+#define XEMACPSS_PHYMNTNC_OP_MASK 0x4002 /* operation mask bits */
+#define XEMACPSS_PHYMNTNC_OP_R_MASK0x2000 /* read operation */
+#define XEMACPSS_PHYMNTNC_OP_W_MASK0x1000 /* write operation */
+#define XEMACPSS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
+#define XEMACPSS_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
+
+#define XEMACPSS_RXBUF_EOF_MASK0x8000 /* End of frame. */
+#define XEMACPSS_RXBUF_SOF_MASK0x4000 /* Start of frame. */
+#define XEMACPSS_RXBUF_LEN_MASK0x3FFF /* Mask for length
field */
+
+#define XEMACPSS_RXBUF_WRAP_MASK 0x0002 /* Wrap bit, last BD */
+#define XEMACPSS_RXBUF_NEW_MASK0x0001 /* Used bit.. */
+#define XEMACPSS_RXBUF_ADD_MASK0xFFFC /* Mask for address
*/
+
+/* Wrap bit, last descriptor */
+#define XEMACPSS_TXBUF_WRAP_MASK 0x4000
+#define XEMACPSS_TXBUF_LAST_MASK 0x8000 /* Last buffer */
+
+#define XEMACPSS_TXSR_HRESPNOK_MASK0x0100 /* Transmit hresp not OK */
+#define XEMACPSS_TXSR_URUN_MASK0x0040 /* Transmit underrun
*/
+/* Transmit buffs exhausted mid frame */
+#define XEMACPSS_TXSR_BUFEXH_MASK 0x0010
+
+#define XEMACPSS_NWCTRL_TXEN_MASK 0x0008 /* Enable transmit */
+#define XEMACPSS_NWCTRL_RXEN_MASK 0x0004 /* Enable receive */
+#define XEMACPSS_NWCTRL_MDEN_MASK 0x0010 /* Enable MDIO port */
+#define XEMACPSS_NWCTRL_STARTTX_MASK 0x0200 /* Start tx (tx_go) */
+
+#define XEMACPSS_NWSR_MDIOIDLE_MASK0x0004 /* PHY management idle */
+
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG 1
+
+/* Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ * 0x1000: 10Mbps full duplex support
+ * 0x0800: 10Mbps half duplex support
+ * 0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK0x1808
+
+/* Device registers */
+struct gem_regs {
+ u32 nwctrl; /* Network Control reg */
+ u32 nwcfg; /* Network Config reg */
+ u32 nwsr; /* Network Status reg */
+ u32 reserved1;
+ u32 dmacr; /* DMA Control reg */
+ u32 txsr; /* TX Status reg */
+ u32 rxqbase; /* RX Q Base address reg */
+ u32 txqbase; /* TX Q Base address reg */
+ u32 rxsr; /* RX Status reg */
+ u32 reserved2[2];
+ u32 idr; /* Interrupt Disable reg */
+ u32 reserved3;
+ u32 phymntnc; /* Phy Maintaince reg */
+ u32 reserved4[18];
+ u32 hashl; /* Hash Low address reg */
+ u32 hashh; /* Hash High address reg */
+#define
[U-Boot] [PATCH 3/4] arm: Support new Xilinx Zynq platform
Add timer driver.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/Makefile | 48
arch/arm/cpu/armv7/zynq/timer.c | 151 ++
2 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000..814c1d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS = timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000..d79da97
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, g...@denx.de
+ *
+ * (C) Copyright 2003
+ * Texas Instruments www.ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
+
+static struct scu_timer *timer_base = CONFIG_XPSS_SCUTIMER_BASEADDR;
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0xFF00 /* Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x0002 /* Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x0001 /* Timer enable */
+
+#define TIMER_LOAD_VAL 0x
+#define TIMER_PRESCALE 255
+#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
+
+int timer_init(void)
+{
+ u32 val;
+
+ /* Load the timer counter register */
+ writel(0x, timer_base-counter);
+
+ /* Start the A9Timer device */
+ val = readl(timer_base-control);
+ /* Enable Auto reload mode */
+ val |= XSCUTIMER_CONTROL_AUTO_RELOAD_MASK;
+ /* Clear prescaler control bits */
+ val = ~XSCUTIMER_CONTROL_PRESCALER_MASK;
+ /* Set prescaler value */
+ val |= (TIMER_PRESCALE XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+ /* Enable
[U-Boot] [PATCH 4/4] xilinx: Add new Zynq board
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek mon...@monstr.eu
---
board/xilinx/zynq/Makefile| 57 +
board/xilinx/zynq/board.c | 64 +
board/xilinx/zynq/lowlevel_init.S | 27 +++
boards.cfg|1 +
4 files changed, 149 insertions(+), 0 deletions(-)
create mode 100644 board/xilinx/zynq/Makefile
create mode 100644 board/xilinx/zynq/board.c
create mode 100644 board/xilinx/zynq/lowlevel_init.S
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 000..373a8a7
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y:= board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 000..716fcfe
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_XILINX_GEM) defined(CONFIG_XPSS_GEM_BASEADDR0)
+ ret |= xilinx_gem_initialize(bis, CONFIG_XPSS_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
diff --git a/board/xilinx/zynq/lowlevel_init.S
b/board/xilinx/zynq/lowlevel_init.S
new file mode 100644
index 000..642eb18
--- /dev/null
+++ b/board/xilinx/zynq/lowlevel_init.S
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU
[U-Boot] [PATCH 1/4] serial: Add Dragonfire serial driver
The driver is used on Xilinx Zynq platform.
Signed-off-by: Michal Simek mon...@monstr.eu
---
drivers/serial/Makefile |1 +
drivers/serial/serial_xpssuart.c | 218 ++
2 files changed, 219 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/serial_xpssuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..81350d0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_XPSS_SERIAL) += serial_xpssuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_xpssuart.c b/drivers/serial/serial_xpssuart.c
new file mode 100644
index 000..3c6d838
--- /dev/null
+++ b/drivers/serial/serial_xpssuart.c
@@ -0,0 +1,218 @@
+/*
+ * U-Boot driver for Xilinx Dragonfire UART.
+ *
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+
+#define XDFUART_SR_TXFULL 0x0010 /* TX FIFO full */
+#define XDFUART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
+
+#define XDFUART_CR_TX_EN 0x0010 /* TX enabled */
+#define XDFUART_CR_RX_EN 0x0004 /* RX enabled */
+#define XDFUART_CR_TXRST 0x0002 /* TX logic reset */
+#define XDFUART_CR_RXRST 0x0001 /* RX logic reset */
+
+#define XDFUART_MR_PARITY_NONE 0x0020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define XDFUART_BDIV 15 /* Default/reset BDIV value */
+#define XDFUART_BASECLK3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[4] = {
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR0
+ [0] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR1
+ [1] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR1,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR2
+ [2] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR2,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR3
+ [3] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR3,
+#endif
+};
+
+struct xdfuart_params {
+ u32 baudrate;
+ u32 clock;
+};
+
+static struct xdfuart_params xdf_ports_param[4] = {
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE0) defined(CONFIG_XPSS_SERIAL_CLOCK0)
+ [0].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE0,
+ [0].clock = CONFIG_XPSS_SERIAL_CLOCK0,
+#endif
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE1) defined(CONFIG_XPSS_SERIAL_CLOCK1)
+ [1].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE1,
+ [1].clock = CONFIG_XPSS_SERIAL_CLOCK1,
+#endif
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE2) defined(CONFIG_XPSS_SERIAL_CLOCK2)
+ [2].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE2,
+ [2].clock = CONFIG_XPSS_SERIAL_CLOCK2,
+#endif
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE3) defined(CONFIG_XPSS_SERIAL_CLOCK3)
+ [3].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE3,
+ [3].clock = CONFIG_XPSS_SERIAL_CLOCK3,
+#endif
+};
+
+/* Set up the baud rate in gd struct */
+static void xdfuart_serial_setbrg(const int port)
+{
+ /* Calculation results. */
+ unsigned int calc_bauderror, bdiv, bgen;
+ unsigned long calc_baud = 0;
+ unsigned long baud = xdf_ports_param[port].baudrate;
+ unsigned long clock = xdf_ports_param[port].clock;
+ struct xdfuart *regs = xdf_ports[port];
+
+ /*master clock
+* Baud rate = --
+* bgen * (bdiv + 1)
+*
+* Find acceptable values for baud generation
[U-Boot] [PATCH 4/4 v2] xilinx: Add new Zynq board
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek mon...@monstr.eu
---
v2: Forget to also add config file
---
board/xilinx/zynq/Makefile| 57 +
board/xilinx/zynq/board.c | 64 +++
board/xilinx/zynq/lowlevel_init.S | 27
boards.cfg|1 +
include/configs/zynq.h| 124 +
5 files changed, 273 insertions(+), 0 deletions(-)
create mode 100644 board/xilinx/zynq/Makefile
create mode 100644 board/xilinx/zynq/board.c
create mode 100644 board/xilinx/zynq/lowlevel_init.S
create mode 100644 include/configs/zynq.h
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 000..373a8a7
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y:= board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 000..716fcfe
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_XILINX_GEM) defined(CONFIG_XPSS_GEM_BASEADDR0)
+ ret |= xilinx_gem_initialize(bis, CONFIG_XPSS_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
diff --git a/board/xilinx/zynq/lowlevel_init.S
b/board/xilinx/zynq/lowlevel_init.S
new file mode 100644
index 000..642eb18
--- /dev/null
+++ b/board/xilinx/zynq/lowlevel_init.S
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR
Re: [U-Boot] [PATCH 4/4] xilinx: Add new Zynq board
On 08/14/2012 01:42 PM, Michal Simek wrote: Add support for Xilinx Zynq board. Signed-off-by: Michal Simek mon...@monstr.eu --- board/xilinx/zynq/Makefile| 57 + board/xilinx/zynq/board.c | 64 + board/xilinx/zynq/lowlevel_init.S | 27 +++ boards.cfg|1 + 4 files changed, 149 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 board/xilinx/zynq/lowlevel_init.S oops. I forget to add also config file. Will send v2 patch. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] arm: Support new Xilinx Zynq platform
On 08/14/2012 05:36 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
Add timer driver.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/Makefile | 48
arch/arm/cpu/armv7/zynq/timer.c | 151 ++
2 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000..814c1d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
You should include the lowlevel_init.o here instead of in the board.
Probably make sense.
+COBJS = timer.o
+
Preferably emulate the Makefile in arch/arm/cpu/armv7/tegra2/. By
that I mean use COBJS-y instead of COBJS directly. This is more
forward looking to allow for features to be disabled in the future.
no problem with that.
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000..d79da97
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, g...@denx.de
+ *
+ * (C) Copyright 2003
+ * Texas Instruments www.ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
You are using the timer in the ARM Cortex A9 core. This is not
Zynq-specific in any way. It should be made available in a different
place. Probably in arch/arm/lib. It should be stripped on any XSCU
references. Use ARM names instead.
Based on this I can't see the reason why XSCU should be stripped.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/BABDEAGJ.html
It is SCU private timer. Agree that we can remove X prefix.
I don't think that arch/arm/lib is the proper location for that.
I am not arm specialist to say
Re: [U-Boot] [PATCH 1/4] serial: Add Dragonfire serial driver
On 08/14/2012 04:09 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
The driver is used on Xilinx Zynq platform.
Signed-off-by: Michal Simek mon...@monstr.eu
---
drivers/serial/Makefile |1 +
drivers/serial/serial_xpssuart.c | 218 ++
2 files changed, 219 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/serial_xpssuart.c
I think this would be clearer if it was named serial_zynq.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..81350d0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_XPSS_SERIAL) += serial_xpssuart.o
Replace every reference to XPSS with ZYNQ.
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_xpssuart.c b/drivers/serial/serial_xpssuart.c
new file mode 100644
index 000..3c6d838
--- /dev/null
+++ b/drivers/serial/serial_xpssuart.c
@@ -0,0 +1,218 @@
+/*
+ * U-Boot driver for Xilinx Dragonfire UART.
Use the released name Zynq not the old codename Dragonfire.
ok.
+ *
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+
+#define XDFUART_SR_TXFULL 0x0010 /* TX FIFO full */
+#define XDFUART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
Replace all references to XDFUART with ZYNQ_UART.
agree.
+
+#define XDFUART_CR_TX_EN 0x0010 /* TX enabled */
+#define XDFUART_CR_RX_EN 0x0004 /* RX enabled */
+#define XDFUART_CR_TXRST 0x0002 /* TX logic reset */
+#define XDFUART_CR_RXRST 0x0001 /* RX logic reset */
+
+#define XDFUART_MR_PARITY_NONE 0x0020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define XDFUART_BDIV 15 /* Default/reset BDIV value */
+#define XDFUART_BASECLK3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[4] = {
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR0
+ [0] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR1
+ [1] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR1,
+#endif
There are 2 UARTS in hard silicon.
My fault.
They should be supported with
their known base addresses (0xE000 and 0xE0001000) here without
pushing that into the config header.
I am not sure that hardcoding addresses here is the right thing to do.
The main reason is that none has tested option that hard IPs can be
also used from programmable logic. It means that this driver
could be possible to use from Microblaze with address translation.
No problem to setup these addresses in config file.
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR2
+ [2] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR2,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR3
+ [3] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR3,
+#endif
+};
+
+struct xdfuart_params {
+ u32 baudrate;
+ u32 clock;
+};
+
+static struct xdfuart_params xdf_ports_param[4] = {
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE0) defined(CONFIG_XPSS_SERIAL_CLOCK0)
+ [0].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE0,
+ [0].clock = CONFIG_XPSS_SERIAL_CLOCK0,
+#endif
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE1) defined(CONFIG_XPSS_SERIAL_CLOCK1)
+ [1].baudrate = CONFIG_XPSS_SERIAL_BAUDRATE1,
+ [1].clock = CONFIG_XPSS_SERIAL_CLOCK1,
+#endif
+#if defined(CONFIG_XPSS_SERIAL_BAUDRATE2) defined
Re: [U-Boot] [PATCH 2/4] net: Add driver for Zynq Gem IP
Hi Joe,
On 08/14/2012 04:59 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek mon...@monstr.eu
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/Makefile |1 +
drivers/net/xilinx_gem.c | 514 ++
include/netdev.h |1 +
3 files changed, 516 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/xilinx_gem.c
Call this zynq_gem.c My understanding is this is only available in
the hard silicon for Zynq.
That's correct understanding.
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 430f90c..e510ffa 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -77,6 +77,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+COBJS-$(CONFIG_XILINX_GEM) += xilinx_gem.o
COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
diff --git a/drivers/net/xilinx_gem.c b/drivers/net/xilinx_gem.c
new file mode 100644
index 000..7c8c14d
--- /dev/null
+++ b/drivers/net/xilinx_gem.c
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2011 Michal Simek
+ *
+ * Michal SIMEK mon...@monstr.eu
+ *
+ * Based on Xilinx gmac driver:
+ * (C) Copyright 2011 Xilinx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include net.h
+#include config.h
+#include malloc.h
+#include asm/io.h
+#include phy.h
+#include miiphy.h
+
+#if !defined(CONFIG_PHYLIB)
+# error XILINX_GEM_ETHERNET requires PHYLIB
+#endif
+
+/* Bit/mask specification */
+#define XEMACPSS_PHYMNTNC_OP_MASK 0x4002 /* operation mask bits */
+#define XEMACPSS_PHYMNTNC_OP_R_MASK0x2000 /* read operation */
+#define XEMACPSS_PHYMNTNC_OP_W_MASK0x1000 /* write operation */
+#define XEMACPSS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
+#define XEMACPSS_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
Replace all XEMACPSS with ZYNQ_GEM
ok
+
+#define XEMACPSS_RXBUF_EOF_MASK0x8000 /* End of frame. */
+#define XEMACPSS_RXBUF_SOF_MASK0x4000 /* Start of frame. */
+#define XEMACPSS_RXBUF_LEN_MASK0x3FFF /* Mask for length
field */
+
+#define XEMACPSS_RXBUF_WRAP_MASK 0x0002 /* Wrap bit, last BD */
+#define XEMACPSS_RXBUF_NEW_MASK0x0001 /* Used bit.. */
+#define XEMACPSS_RXBUF_ADD_MASK0xFFFC /* Mask for address
*/
+
+/* Wrap bit, last descriptor */
+#define XEMACPSS_TXBUF_WRAP_MASK 0x4000
+#define XEMACPSS_TXBUF_LAST_MASK 0x8000 /* Last buffer */
+
+#define XEMACPSS_TXSR_HRESPNOK_MASK0x0100 /* Transmit hresp not OK */
+#define XEMACPSS_TXSR_URUN_MASK0x0040 /* Transmit underrun
*/
+/* Transmit buffs exhausted mid frame */
+#define XEMACPSS_TXSR_BUFEXH_MASK 0x0010
+
+#define XEMACPSS_NWCTRL_TXEN_MASK 0x0008 /* Enable transmit */
+#define XEMACPSS_NWCTRL_RXEN_MASK 0x0004 /* Enable receive */
+#define XEMACPSS_NWCTRL_MDEN_MASK 0x0010 /* Enable MDIO port */
+#define XEMACPSS_NWCTRL_STARTTX_MASK 0x0200 /* Start tx (tx_go) */
+
+#define XEMACPSS_NWSR_MDIOIDLE_MASK0x0004 /* PHY management idle */
+
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG 1
+
+/* Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ * 0x1000: 10Mbps full duplex support
+ * 0x0800: 10Mbps half duplex support
+ * 0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK0x1808
+
+/* Device registers */
+struct gem_regs {
+ u32 nwctrl; /* Network Control reg */
+ u32 nwcfg; /* Network Config reg */
+ u32 nwsr; /* Network Status reg */
+ u32 reserved1;
+ u32 dmacr; /* DMA Control reg */
+ u32 txsr; /* TX Status reg */
+ u32 rxqbase; /* RX Q Base address reg */
+ u32 txqbase; /* TX Q
Re: [U-Boot] [PATCH 3/4] arm: Support new Xilinx Zynq platform
On 08/14/2012 06:41 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 11:28 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 05:36 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
Add timer driver.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/Makefile | 48
arch/arm/cpu/armv7/zynq/timer.c | 151
++
2 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
diff --git a/arch/arm/cpu/armv7/zynq/Makefile
b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000..814c1d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
You should include the lowlevel_init.o here instead of in the board.
Probably make sense.
+COBJS = timer.o
+
Preferably emulate the Makefile in arch/arm/cpu/armv7/tegra2/. By
that I mean use COBJS-y instead of COBJS directly. This is more
forward looking to allow for features to be disabled in the future.
no problem with that.
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/zynq/timer.c
b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000..d79da97
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, g...@denx.de
+ *
+ * (C) Copyright 2003
+ * Texas Instruments www.ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
You are using the timer in the ARM Cortex A9 core. This is not
Zynq-specific in any way. It should be made available in a different
place. Probably in arch/arm/lib. It should be stripped on any XSCU
references. Use ARM names instead.
Based on this I can't see the reason why XSCU should be stripped.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407f/BABDEAGJ.html
Re: [U-Boot] [PATCH 1/4] serial: Add Dragonfire serial driver
On 08/14/2012 06:45 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 11:38 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 04:09 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
The driver is used on Xilinx Zynq platform.
Signed-off-by: Michal Simek mon...@monstr.eu
---
drivers/serial/Makefile |1 +
drivers/serial/serial_xpssuart.c | 218
++
2 files changed, 219 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/serial_xpssuart.c
I think this would be clearer if it was named serial_zynq.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..81350d0 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_XPSS_SERIAL) += serial_xpssuart.o
Replace every reference to XPSS with ZYNQ.
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_xpssuart.c
b/drivers/serial/serial_xpssuart.c
new file mode 100644
index 000..3c6d838
--- /dev/null
+++ b/drivers/serial/serial_xpssuart.c
@@ -0,0 +1,218 @@
+/*
+ * U-Boot driver for Xilinx Dragonfire UART.
Use the released name Zynq not the old codename Dragonfire.
ok.
+ *
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+
+#define XDFUART_SR_TXFULL 0x0010 /* TX FIFO full */
+#define XDFUART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
Replace all references to XDFUART with ZYNQ_UART.
agree.
+
+#define XDFUART_CR_TX_EN 0x0010 /* TX enabled */
+#define XDFUART_CR_RX_EN 0x0004 /* RX enabled */
+#define XDFUART_CR_TXRST 0x0002 /* TX logic reset */
+#define XDFUART_CR_RXRST 0x0001 /* RX logic reset */
+
+#define XDFUART_MR_PARITY_NONE 0x0020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define XDFUART_BDIV 15 /* Default/reset BDIV value */
+#define XDFUART_BASECLK3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[4] = {
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR0
+ [0] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_XPSS_SERIAL_BASEADDR1
+ [1] = (struct xdfuart *)CONFIG_XPSS_SERIAL_BASEADDR1,
+#endif
There are 2 UARTS in hard silicon.
My fault.
They should be supported with
their known base addresses (0xE000 and 0xE0001000) here without
pushing that into the config header.
I am not sure that hardcoding addresses here is the right thing to do.
The main reason is that none has tested option that hard IPs can be
also used from programmable logic. It means that this driver
could be possible to use from Microblaze with address translation.
No problem to setup these addresses in config file.
I accept that you can access these from microblaze, but I think that
will be the 1% use-case. You can make the base address overridable,
but use the ARM core address space by default and have them here
instead of copied to every config.
None has shown any table with use cases that why you can't say it will be 1%
use-cases.
+ I don't think that hardcode IP address in generic driver is right way to go.
For example we are using SERIAL0 as console and in EDK you can setup which
IP it is. It means that sometimes SERIAL0 is at 0xe0001000 and sometimes at
0xe000.
This setting is also done for Linux
Re: [U-Boot] [PATCH 3/4] arm: Support new Xilinx Zynq platform
On 08/14/2012 07:15 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 12:11 PM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 06:41 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 11:28 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 05:36 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu wrote:
Add timer driver.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/Makefile | 48
arch/arm/cpu/armv7/zynq/timer.c | 151
++
2 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
diff --git a/arch/arm/cpu/armv7/zynq/Makefile
b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000..814c1d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
You should include the lowlevel_init.o here instead of in the board.
Probably make sense.
+COBJS = timer.o
+
Preferably emulate the Makefile in arch/arm/cpu/armv7/tegra2/. By
that I mean use COBJS-y instead of COBJS directly. This is more
forward looking to allow for features to be disabled in the future.
no problem with that.
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/zynq/timer.c
b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000..d79da97
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, g...@denx.de
+ *
+ * (C) Copyright 2003
+ * Texas Instruments www.ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
You are using the timer in the ARM Cortex A9 core. This is not
Zynq-specific in any way. It should be made available in a different
place. Probably in arch/arm/lib. It should be stripped on any XSCU
references. Use ARM names instead.
Based
Re: [U-Boot] [PATCH 3/4] arm: Support new Xilinx Zynq platform
On 08/14/2012 08:19 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 12:39 PM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 07:15 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 12:11 PM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 06:41 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 11:28 AM, Michal Simek mon...@monstr.eu wrote:
On 08/14/2012 05:36 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 6:42 AM, Michal Simek mon...@monstr.eu
wrote:
Add timer driver.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/arm/cpu/armv7/zynq/Makefile | 48
arch/arm/cpu/armv7/zynq/timer.c | 151
++
2 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/zynq/Makefile
create mode 100644 arch/arm/cpu/armv7/zynq/timer.c
diff --git a/arch/arm/cpu/armv7/zynq/Makefile
b/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000..814c1d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
You should include the lowlevel_init.o here instead of in the board.
Probably make sense.
+COBJS = timer.o
+
Preferably emulate the Makefile in arch/arm/cpu/armv7/tegra2/. By
that I mean use COBJS-y instead of COBJS directly. This is more
forward looking to allow for features to be disabled in the future.
no problem with that.
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/zynq/timer.c
b/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000..d79da97
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. philippe.ro...@arm.com
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, g...@denx.de
+ *
+ * (C) Copyright 2003
+ * Texas Instruments www.ti.com
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Marius Groeger mgroe...@sysgo.de
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH www.elinos.com
+ * Alex Zuepke a...@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+ u32 load; /* Timer Load Register */
+ u32 counter; /* Timer Counter Register */
+ u32 control; /* Timer Control Register */
+};
You are using the timer in the ARM Cortex A9 core. This is not
Zynq-specific in any way. It should
Re: [U-Boot] [PATCH 4/4 v2] xilinx: Add new Zynq board
Hi Joe,
sorry missed this one.
On 08/14/2012 05:48 PM, Joe Hershberger wrote:
Hi Michal,
On Tue, Aug 14, 2012 at 7:15 AM, Michal Simek mon...@monstr.eu wrote:
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek mon...@monstr.eu
---
v2: Forget to also add config file
---
board/xilinx/zynq/Makefile| 57 +
board/xilinx/zynq/board.c | 64 +++
board/xilinx/zynq/lowlevel_init.S | 27
This lowlevel_init.S should be in arch/arm/cpu/armv7/zynq/
It will be in the next version.
boards.cfg|1 +
include/configs/zynq.h| 124 +
5 files changed, 273 insertions(+), 0 deletions(-)
create mode 100644 board/xilinx/zynq/Makefile
create mode 100644 board/xilinx/zynq/board.c
create mode 100644 board/xilinx/zynq/lowlevel_init.S
create mode 100644 include/configs/zynq.h
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 000..373a8a7
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y:= board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 000..716fcfe
--- /dev/null
+++ b/board/xilinx/zynq/board.c
Are you thinking that this will be the one and only Zynq board?
Perhaps a layout like what Xilinx has in their branch is more
appropriate.
http://git.xilinx.com/?p=u-boot-xarm.git;a=history;f=board/xilinx/zynq_common;hb=refs/heads/master
My intention is to have one zynq generic board as I have it for microblaze.
The main reason is that every board design could be different and supporting
all variants is impossible.
When DM is ready to use with OF then DTS will handle the board differences.
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_XILINX_GEM) defined(CONFIG_XPSS_GEM_BASEADDR0)
+ ret |= xilinx_gem_initialize(bis, CONFIG_XPSS_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
diff
Re: [U-Boot] [PATCH 4/4 v2] xilinx: Add new Zynq board
Hi Joe, On 08/15/2012 07:31 PM, Joe Hershberger wrote: Hi Michal, On Wed, Aug 15, 2012 at 3:49 AM, Michal Simek mon...@monstr.eu wrote: Hi Joe, sorry missed this one. On 08/14/2012 05:48 PM, Joe Hershberger wrote: Are you thinking that this will be the one and only Zynq board? Perhaps a layout like what Xilinx has in their branch is more appropriate. http://git.xilinx.com/?p=u-boot-xarm.git;a=history;f=board/xilinx/zynq_common;hb=refs/heads/master My intention is to have one zynq generic board as I have it for microblaze. The main reason is that every board design could be different and supporting all variants is impossible. I believe this is a fundamental misunderstanding of the Zynq architecture. I don't think that this is not my fundamental misunderstanding. With the microblaze and virtex ppc architecture you basically have an FPGA that happens to have a processor in it. The Zynq architecture is the opposite... an ARM system that happens to have an FPGA attached to it. We are working in this area for quite a long time to be convinced that this is the best solution we can make. And even this is only one way how to maintain this platform. Creating new u-boot board description for every board or configuration is bad idea. The different boards have plenty of hard IP and peripherals available for all of the key interfaces that u-boot needs to be aware of. Certainly there can be other peripherals added to the fabric and those can be handles with device tree. Generally these boards are well defined, unlike microblaze targets. Zynq is not like any other ARM based board. There is still a lot of space for configuring it and you need all the time any input from user even if you use reference board. All reference boards contains a lot of connectors which started with FMC, pins, configurable options. When DM is ready to use with OF then DTS will handle the board differences. That's fine, but I doubt we will see u-boot collapse into directory of DTS files and one board per architecture. I expect it to have much more impact as a way of eliminating the separate targets for boards that have several variants in their configuration (PCI or not, etc). My expectation is to have one DTS for microblaze and one for Zynq. Then user can use device-tree generator from Xilinx EDK to get DTS and will replace template in u-boot. --snip-- +#defineCONFIG_ETHADDR 00:0a:35:00:b2:02 Don't put MAC addresses in a config file. Where should be MAC address setup? In the environment. no problem with that +#define CONFIG_IPADDR 192.168.0.105 +#define CONFIG_SERVERIP192.168.0.101 +#defineCONFIG_GATEWAYIP192.168.0.1 Is this really helpful? yes or no. Why not to define? It is setup for my network but it can be easily changed. Again... the environment. It is easily added to the environment. no problem with that + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL + +/* MII and Phylib */ +#define CONFIG_MII +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_BROADCOM +#define CONFIG_PHY_DAVICOM +#define CONFIG_PHY_GIGE +#define CONFIG_PHY_LXT +#define CONFIG_PHY_MARVELL +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_NATSEMI +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_VITESSE I guess since this is a ficticious board it has every manufacturer's phy on it? This is not fictitious board. It is targetting to zc702 with Marwell phy but this configuration should work for zynq generic board as I describe above. This comes back to the fact that you know what phy is on this board because it is not a random board with a Zynq on it, it is a specific board with specific peripherals. Of course you always know it but not if you create generic platform. But if you like I will remove others phys which are not physically placed on zc702. I have checked u-boot size and enabling all phys increase u-boot size for 4.5kB which is fine. That's not a reasonable approach. It you take that approach with every peripheral, then u-boot explodes in size. Don't agree with that. There is not unlimited number of peripherals/drivers which you can use. I don't expect any u-boot size explosion. Enabling support for basic drivers is reasonable. Anyway I am OK to remove other phys and wait till DM with OF is ready. Because in that time I expect that we will have to enable all platform acceptable drivers anyway. Also still there are others option with using programmable logic with axi_ethernet IP where other phys can be used. And yet this board has no other phy on the fabric. Let the board that does enable those phys. I don't think that creating special u-boot board for every zynq platform is good solution. But we will see when DM is done
[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver
The driver is used on Xilinx Zynq platform.
Signed-off-by: Michal Simek mon...@monstr.eu
---
v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART
Rename driver name
Remove driver description
---
drivers/serial/Makefile |1 +
drivers/serial/serial_zynq.c | 200 ++
2 files changed, 201 insertions(+), 0 deletions(-)
create mode 100644 drivers/serial/serial_zynq.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 65d0f23..dfc22a4 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
new file mode 100644
index 000..c49da3b
--- /dev/null
+++ b/drivers/serial/serial_zynq.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2012 Michal Simek mon...@monstr.eu
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+
+#define ZYNQ_UART_SR_TXFULL0x0010 /* TX FIFO full */
+#define ZYNQ_UART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
+
+#define ZYNQ_UART_CR_TX_EN 0x0010 /* TX enabled */
+#define ZYNQ_UART_CR_RX_EN 0x0004 /* RX enabled */
+#define ZYNQ_UART_CR_TXRST 0x0002 /* TX logic reset */
+#define ZYNQ_UART_CR_RXRST 0x0001 /* RX logic reset */
+
+#define ZYNQ_UART_MR_PARITY_NONE 0x0020 /* No parity mode */
+
+/* Some clock/baud constants */
+#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
+#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
+
+struct xdfuart {
+ u32 control; /* Control Register [8:0] */
+ u32 mode; /* Mode Register [10:0] */
+ u32 reserved1[4];
+ u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
+ u32 reserved2[4];
+ u32 channel_sts; /* Channel Status [11:0] */
+ u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
+ u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
+};
+
+static struct xdfuart *xdf_ports[2] = {
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+ [0] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+#endif
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+ [1] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#endif
+};
+
+struct xdfuart_params {
+ u32 baudrate;
+ u32 clock;
+};
+
+static struct xdfuart_params xdf_ports_param[2] = {
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
+ [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
+ [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
+ [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
+ [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
+#endif
+};
+
+/* Set up the baud rate in gd struct */
+static void xdfuart_serial_setbrg(const int port)
+{
+ /* Calculation results. */
+ unsigned int calc_bauderror, bdiv, bgen;
+ unsigned long calc_baud = 0;
+ unsigned long baud = xdf_ports_param[port].baudrate;
+ unsigned long clock = xdf_ports_param[port].clock;
+ struct xdfuart *regs = xdf_ports[port];
+
+ /*master clock
+* Baud rate = --
+* bgen * (bdiv + 1)
+*
+* Find acceptable values for baud generation.
+*/
+ for (bdiv = 4; bdiv 255; bdiv++) {
+ bgen = clock / (baud * (bdiv + 1));
+ if (bgen 2 || bgen 65535)
+ continue;
+
+ calc_baud = clock / (bgen * (bdiv + 1));
+
+ /*
+* Use first calculated baudrate with
+* an acceptable (3%) error
+*/
+ if (baud calc_baud)
+ calc_bauderror = baud - calc_baud;
+ else
+ calc_bauderror
[U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP
Device driver for Zynq Gem IP.
Signed-off-by: Michal Simek mon...@monstr.eu
CC: Joe Hershberger joe.hershber...@gmail.com
---
v2: Remove phylib protection
Rename driver file name xilinx_gem to zynq_gem
Rename XEMACPSS to ZYNQ_GEM
Rename gemac_priv to zynq_gem_priv
Rename gem_regs to zynq_gem_regs
Add zynq_ prefix to several functions
Remove phy detection
Rename driver name XGem to Gem
Change setup_mac function to reflect u-boot style
---
drivers/net/Makefile |1 +
drivers/net/zynq_gem.c | 453
include/netdev.h |2 +-
3 files changed, 455 insertions(+), 1 deletions(-)
create mode 100644 drivers/net/zynq_gem.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 430f90c..b298588 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -79,6 +79,7 @@ COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
+COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
new file mode 100644
index 000..d62a493
--- /dev/null
+++ b/drivers/net/zynq_gem.c
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2011 Michal Simek
+ *
+ * Michal SIMEK mon...@monstr.eu
+ *
+ * Based on Xilinx gmac driver:
+ * (C) Copyright 2011 Xilinx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include net.h
+#include config.h
+#include malloc.h
+#include asm/io.h
+#include phy.h
+#include miiphy.h
+
+#if !defined(CONFIG_PHYLIB)
+# error XILINX_GEM_ETHERNET requires PHYLIB
+#endif
+
+/* Bit/mask specification */
+#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x4002 /* operation mask bits */
+#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK0x2000 /* read operation */
+#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK0x1000 /* write operation */
+#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
+#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
+
+#define ZYNQ_GEM_RXBUF_EOF_MASK0x8000 /* End of frame. */
+#define ZYNQ_GEM_RXBUF_SOF_MASK0x4000 /* Start of frame. */
+#define ZYNQ_GEM_RXBUF_LEN_MASK0x3FFF /* Mask for length
field */
+
+#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x0002 /* Wrap bit, last BD */
+#define ZYNQ_GEM_RXBUF_NEW_MASK0x0001 /* Used bit.. */
+#define ZYNQ_GEM_RXBUF_ADD_MASK0xFFFC /* Mask for address
*/
+
+/* Wrap bit, last descriptor */
+#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x4000
+#define ZYNQ_GEM_TXBUF_LAST_MASK 0x8000 /* Last buffer */
+
+#define ZYNQ_GEM_TXSR_HRESPNOK_MASK0x0100 /* Transmit hresp not OK */
+#define ZYNQ_GEM_TXSR_URUN_MASK0x0040 /* Transmit underrun
*/
+/* Transmit buffs exhausted mid frame */
+#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x0010
+
+#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x0008 /* Enable transmit */
+#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x0004 /* Enable receive */
+#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x0010 /* Enable MDIO port */
+#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x0200 /* Start tx (tx_go) */
+
+#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK0x0004 /* PHY management idle */
+
+/* Device registers */
+struct zynq_gem_regs {
+ u32 nwctrl; /* Network Control reg */
+ u32 nwcfg; /* Network Config reg */
+ u32 nwsr; /* Network Status reg */
+ u32 reserved1;
+ u32 dmacr; /* DMA Control reg */
+ u32 txsr; /* TX Status reg */
+ u32 rxqbase; /* RX Q Base address reg */
+ u32 txqbase; /* TX Q Base address reg */
+ u32 rxsr; /* RX Status reg */
+ u32 reserved2[2];
+ u32 idr; /* Interrupt Disable reg */
+ u32 reserved3;
+ u32 phymntnc; /* Phy Maintaince reg */
+ u32 reserved4[18];
+ u32 hashl; /* Hash Low address reg */
+ u32 hashh; /* Hash High address reg */
+#define LADDR_LOW 0
+#define LADDR_HIGH 1
[U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board
Add support for Xilinx Zynq board.
Signed-off-by: Michal Simek mon...@monstr.eu
---
v2: Forget to also add config file
v3: Change name for serial driver
Remove lowlevel_init from board folder
Remove XPSS part from timer baseaddr
Change name for Zynq gem driver
Clean coding style
Remove mac + ip addresses from config file
Remove additional PHYs
---
board/xilinx/zynq/Makefile | 54 +
board/xilinx/zynq/board.c | 64 +
boards.cfg |1 +
include/configs/zynq.h | 110
4 files changed, 229 insertions(+), 0 deletions(-)
create mode 100644 board/xilinx/zynq/Makefile
create mode 100644 board/xilinx/zynq/board.c
create mode 100644 include/configs/zynq.h
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 000..ef4faa1
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS-y:= board.o
+
+COBJS := $(sort $(COBJS-y))
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 000..4cb36f6
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012 Michal Simek mon...@monstr.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include netdev.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+ ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..aeca912 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -261,6 +261,7 @@ seaboard arm armv7
seaboardnvidia
ventana arm armv7 ventana
nvidia tegra2
whistler arm armv7 whistler
nvidia tegra2
u8500_href arm armv7 u8500
st-ericssonu8500
+zynq arm armv7 zynq
xilinx zynq
actux1_4_16 arm ixp actux1 -
- actux1:FLASH2X2
actux1_4_32 arm ixp actux1
[U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
Add timer driver. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Move lowlevel_init.S from board to cpu folder Remove XPSS prefix Rename XSCUTIMER - SCUTIMER Keep timer in zynq folder till ARM custodian comments it. --- arch/arm/cpu/armv7/zynq/Makefile| 52 +++ arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 +++ 3 files changed, 230 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile new file mode 100644 index 000..1d2d7e1 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +SOBJS-y:= lowlevel_init.o +COBJS-y:= timer.o + +SOBJS := $(SOBJS-y) +COBJS := $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/cpu/armv7/zynq/lowlevel_init.S new file mode 100644 index 000..642eb18 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/lowlevel_init.S @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2012 Michal Simek mon...@monstr.eu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include config.h +#include linux/linkage.h + +ENTRY(lowlevel_init) +mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c new file mode 100644 index 000..0252220 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/timer.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2012 Michal Simek mon...@monstr.eu + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, l...@denx.de + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. philippe.ro...@arm.com + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, g...@denx.de + * + * (C) Copyright 2003 + * Texas Instruments www.ti.com + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Marius Groeger mgroe...@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH www.elinos.com + * Alex Zuepke a...@sysgo.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS
Re: [U-Boot] [PATCH 4/4 v2] xilinx: Add new Zynq board
On 08/16/2012 07:27 PM, Joe Hershberger wrote: Hi Michal, On Thu, Aug 16, 2012 at 1:12 AM, Michal Simek mon...@monstr.eu wrote: Hi Joe, On 08/15/2012 07:31 PM, Joe Hershberger wrote: Hi Michal, I believe this is a fundamental misunderstanding of the Zynq architecture. I don't think that this is not my fundamental misunderstanding. With the microblaze and virtex ppc architecture you basically have an FPGA that happens to have a processor in it. The Zynq architecture is the opposite... an ARM system that happens to have an FPGA attached to it. We are working in this area for quite a long time to be convinced that this is the best solution we can make. And even this is only one way how to maintain this platform. Creating new u-boot board description for every board or configuration is bad idea. The different boards have plenty of hard IP and peripherals available for all of the key interfaces that u-boot needs to be aware of. Certainly there can be other peripherals added to the fabric and those can be handles with device tree. Generally these boards are well defined, unlike microblaze targets. Zynq is not like any other ARM based board. There is still a lot of space for configuring it and you need all the time any input from user even if you use reference board. All reference boards contains a lot of connectors which started with FMC, pins, configurable options. It is possible to add custom features in the fabric. I agree that it is not reasonable to support many different possible things there. That should be left to the user to customize. ok. On the other hand, I think it should be easy to use a given board without first learning everything about it. Please consider each board as though it has no fabric. What can be supported on the board with what is connected to the MIO port? Can it run u-boot? Access memory? Access Ethernet or USB? Boot Linux? In general, the answer to all these is yes. However each board has different things populated. Different RAM, different types of flash interfaces, different Ethernet phys, etc. For this purpose will be reference designs and BSPs for reference boards and none has to spend time on these details. It means one BSP for zc702 for EDK 14.2 one for 14.3, etc. The same for the ZED board and others. If you want to do it for your custom board then you have to compile FSBL in SDK anyway and SDK will also generate DTS or currently what we use in PetaLinux configuration file for u-boot because configuration from DTS is not ready. This will be well documented and there are just some steps which is quite easy to do. But I believe in near future when DM with OF is ready you will need just DTS. I have to also check what xilinx will be distributed with their reference board but I expect that it will be the same as was with previous boards. It means SD(COMPACT flash in past) card with several demos where one will be Linux with DTS file. If I get a Zed board and you get a ZC702 board, we should not each have to write a DTS file and customize all the other config file settings when those differences are known based on the board, just because it is possible to further extend each of these boards beyond their MIO capabilities. I am not sure how did you write your DTS file but we and Xilinx are using device-tree BSP in EDK to generate it. It means you don't need to write it at all. We also have customization extension to setup phy addresses for example. This extension is used in PetaLinux and I expect will be also available in public git repository soon too. You need to compile fsbl and in the same SDK menu you just select device-tree BSP to generate it. Not sure if Xilinx included this to the latest EDK 14.2 but definitely they have this BSP here http://git.xilinx.com/?p=device-tree.git;a=summary. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - microblaze
Dear Wolfgang, please pull the following changes to your tree. Thanks, Michal The following changes since commit a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-avr32 are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Michal Simek (10): block: systemace: Simplify base and width initialization serial: Support serial multi for Microblaze serial: uartlite: Init all uartlites for serial multi microblaze: Add support for device tree driven board configuration microblaze: board: Remove compilation warning microblaze: intc: Registering interrupt should return value microblaze: intc: Coding style cleanup microblaze: timer: Prepare for device-tree initialization microblaze: Clean microblaze initialization microblaze: board: Use bi_flashstart instead of CONFIG_SYS_FLASH_BASE Stephan Linz (1): spi: xilinx: Remove unused variable arch/microblaze/config.mk |2 + arch/microblaze/cpu/interrupts.c | 42 ++-- arch/microblaze/cpu/start.S|2 +- arch/microblaze/cpu/timer.c| 69 ++- arch/microblaze/cpu/u-boot.lds |1 + arch/microblaze/include/asm/global_data.h |1 + arch/microblaze/include/asm/microblaze_intc.h | 11 +++- arch/microblaze/include/asm/microblaze_timer.h |3 + arch/microblaze/include/asm/processor.h|3 + arch/microblaze/lib/board.c| 59 ++--- .../xilinx/microblaze-generic/microblaze-generic.c |9 +++ drivers/block/systemace.c | 38 +++ drivers/serial/serial_xuartlite.c | 34 ++ drivers/spi/xilinx_spi.c |1 - include/configs/microblaze-generic.h | 12 +--- include/serial.h |3 +- 16 files changed, 171 insertions(+), 119 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP
On 08/16/2012 08:30 AM, Michal Simek wrote: Device driver for Zynq Gem IP. Signed-off-by: Michal Simek mon...@monstr.eu CC: Joe Hershberger joe.hershber...@gmail.com --- v2: Remove phylib protection Rename driver file name xilinx_gem to zynq_gem Rename XEMACPSS to ZYNQ_GEM Rename gemac_priv to zynq_gem_priv Rename gem_regs to zynq_gem_regs Add zynq_ prefix to several functions Remove phy detection Rename driver name XGem to Gem Change setup_mac function to reflect u-boot style --- drivers/net/Makefile |1 + drivers/net/zynq_gem.c | 453 include/netdev.h |2 +- 3 files changed, 455 insertions(+), 1 deletions(-) create mode 100644 drivers/net/zynq_gem.c Joe: I am not sure if you have seen this patch. Can you please review it and comment it. If is ok, I would like to ask you to add this patch to your net custodian tree or sending me your ACK. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver
On 08/16/2012 08:30 AM, Michal Simek wrote: The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description --- drivers/serial/Makefile |1 + drivers/serial/serial_zynq.c | 200 ++ 2 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c Joe: you have reviewed the first version of this patch. Can you comment it? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
On 08/16/2012 08:30 AM, Michal Simek wrote: Add timer driver. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Move lowlevel_init.S from board to cpu folder Remove XPSS prefix Rename XSCUTIMER - SCUTIMER Keep timer in zynq folder till ARM custodian comments it. --- arch/arm/cpu/armv7/zynq/Makefile| 52 +++ arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 +++ 3 files changed, 230 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c We haven't got any reaction for Albert. Marek and Joe: Can you review this? And give me your ACK or NACK. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board
On 08/16/2012 08:30 AM, Michal Simek wrote: Add support for Xilinx Zynq board. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Forget to also add config file v3: Change name for serial driver Remove lowlevel_init from board folder Remove XPSS part from timer baseaddr Change name for Zynq gem driver Clean coding style Remove mac + ip addresses from config file Remove additional PHYs --- board/xilinx/zynq/Makefile | 54 + board/xilinx/zynq/board.c | 64 + boards.cfg |1 + include/configs/zynq.h | 110 4 files changed, 229 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 include/configs/zynq.h The same for this one. Marek and Joe: Can you please review this? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request for ARM zynq
Hi Albert, CC: Joe and Tom a month ago I have sent 4 Xilinx ARM zynq patches to mailing list (v2) (reminder yesterday) and I haven't got any reaction from anybody. The first patches were commented by Joe and problems fixed in the next version. There is one network driver which should require ACK from Joe and others from ARM maintainer. I would like to get these patches to mainline. Albert and Tom: Can you please look at these patches and tell me what you thing? The best will be if you can pull them to your trees. Here are links to patchwork http://patchwork.ozlabs.org/patch/177907/ http://patchwork.ozlabs.org/patch/177908/ http://patchwork.ozlabs.org/patch/177909/ http://patchwork.ozlabs.org/patch/177910/ Thanks, Michal The following changes since commit a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-avr32 are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master-zynq Michal Simek (4): serial: Add Zynq serial driver net: Add driver for Zynq Gem IP arm: Support new Xilinx Zynq platform xilinx: Add new Zynq board arch/arm/cpu/armv7/zynq/Makefile| 52 arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 ++ board/xilinx/zynq/Makefile | 54 board/xilinx/zynq/board.c | 64 + boards.cfg |1 + drivers/net/Makefile|1 + drivers/net/zynq_gem.c | 453 +++ drivers/serial/Makefile |1 + drivers/serial/serial_zynq.c| 200 ++ include/configs/zynq.h | 110 include/netdev.h|2 +- 12 files changed, 1115 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 drivers/net/zynq_gem.c create mode 100644 drivers/serial/serial_zynq.c create mode 100644 include/configs/zynq.h -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
On 09/13/2012 11:32 AM, Marek Vasut wrote: Dear Michal Simek, On 08/16/2012 08:30 AM, Michal Simek wrote: Add timer driver. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Move lowlevel_init.S from board to cpu folder Remove XPSS prefix Rename XSCUTIMER - SCUTIMER Keep timer in zynq folder till ARM custodian comments it. --- arch/arm/cpu/armv7/zynq/Makefile| 52 +++ arch/arm/cpu/armv7/zynq/lowlevel_init.S | 27 ++ arch/arm/cpu/armv7/zynq/timer.c | 151 +++ 3 files changed, 230 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/zynq/Makefile create mode 100644 arch/arm/cpu/armv7/zynq/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/zynq/timer.c We haven't got any reaction for Albert. Marek and Joe: Can you review this? And give me your ACK or NACK. Oh I'll gladly torture you :-) Go ahead. :-) btw I might need a bit of a review for a ublaze stuff eventually and maybe some xilinx uart too, there's a large stdio patchset I have queued. Would you review please? Feel free to contact me if you need any help with any xilinx stuff. Microblaze/xilinx ppc or current arm code. I am keen to change current code to u-boot new standard and also with dts support. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver
On 09/13/2012 11:21 AM, Marek Vasut wrote: Dear Michal Simek, The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek mon...@monstr.eu --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description --- drivers/serial/Makefile |1 + drivers/serial/serial_zynq.c | 200 ++ 2 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c [...] It looks ok, but can you make it support CONFIG_SERIAL_MULTI right away please? Yes, it will add serial_multi in the next patch. Can you give me your ACK or reviewed-by line? :-) Maybe you have seen it. I have asked for pulling serial multi for uartlite. Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
On 09/13/2012 11:31 AM, Marek Vasut wrote:
Dear Michal Simek,
[...]
+#include config.h
+#include linux/linkage.h
+
+ENTRY(lowlevel_init)
+mov pc, lr
+ENDPROC(lowlevel_init)
inline void lowlevel_init(void) {} works as well and you don't need the assembly
file.
:-) yes. The reason why I have done it in this way that we have some asm code
which will go to this area. That's why I have kept it in asm instead of C.
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4 v3] xilinx: Add new Zynq board
On 09/13/2012 11:35 AM, Marek Vasut wrote:
Dear Michal Simek,
[...]
+int board_init(void)
+{
+ icache_enable();
Uh oh ... isn't this on by default when CONFIG_ICACHE_OFF isn't present?
Will check this one.
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
You don't need this.
Will check it too.
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+ ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
ret |= ? ;-)
The reason is that I will wire axi_ethernet and ethernet lite drivers here too.
If this is the problem I can fix it but the next patch will return it
to this style.
+#endif
+
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+ gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ while (1)
+ ;
+}
This is definitelly CPU specific.
[...]
Right, Moving to different folder make sense.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP
On 09/13/2012 11:28 AM, Marek Vasut wrote:
Dear Michal Simek,
[...]
+static inline int mdio_wait(struct eth_device *dev)
+{
+ struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev-iobase;
+ u32 timeout = 200;
+
+ /* Wait till MDIO interface is ready to accept a new transaction. */
+ while (timeout !(readl(regs-nwsr) ZYNQ_GEM_NWSR_MDIOIDLE_MASK)) {
I'd say, rework this to
while (--timeout) {
if (readl() ... )
break;
WATCHDOG_RESET();
}
The WATCHDOG_RESET will give you the udelay and restart the WDT if you use any.
Also, I think it's more readable when you omit the complex condition for the
while cycle and split it a bit.
make sense
+ timeout--;
+ udelay(1);
+ }
+
+ if (!timeout) {
+ printf(%s: Timeout\n, __func__);
+ return 1;
+ }
+
+ return 0;
+}
[...]
+static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
+{
+ int tmp;
+ int i;
+ struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev-iobase;
+ struct zynq_gem_priv *priv = dev-priv;
+ struct phy_device *phydev;
+ u32 supported = SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full;
+
+ if (priv-initialized)
+ return 0;
+
+ /* Disable all interrupts */
+ writel(0x, regs-idr);
+
+ /* Disable the receiver transmitter */
+ writel(0, regs-nwctrl);
+ writel(0, regs-txsr);
+ writel(0, regs-rxsr);
+ writel(0, regs-phymntnc);
+
+ /* Clear the Hash registers for the mac address pointed by AddressPtr */
+ writel(0x0, regs-hashl);
+ /* Write bits [63:32] in TOP */
+ writel(0x0, regs-hashh);
+
+ /* Clear all counters */
+ for (i = 0; i = (sizeof(struct zynq_gem_regs) -
+ offsetof(struct zynq_gem_regs, stat)) / 4; i++)
Add a const int variable and use it here so you don't have to break the for () .
if you like.
+ readl(regs-stat[i]);
+
+ /* Setup RxBD space */
+ memset((priv-rx_bd), 0, sizeof(priv-rx_bd));
+ /* Create the RxBD ring */
+ memset((priv-rxbuffers), 0, sizeof(priv-rxbuffers));
+
+ for (i = 0; i RX_BUF; i++) {
+ priv-rx_bd[i].status = 0xF000;
+ priv-rx_bd[i].addr = (u32)((char *) (priv-rxbuffers) +
+ (i * PKTSIZE_ALIGN));
+ }
+ /* WRAP bit to last BD */
+ priv-rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
+ /* Write RxBDs to IP */
+ writel((u32) (priv-rx_bd), regs-rxqbase);
+
+
+ /* MAC Setup */
+ /*
+* Following is the setup for Network Configuration register.
+* Bit 0: Set for 100 Mbps operation.
+* Bit 1: Set for Full Duplex mode.
+* Bit 4: Unset to allow Copy all frames - MAC checking
+* Bit 17: Set for FCS removal.
+* Bits 20-18: Set with value binary 010 to divide pclk by 32
+* (pclk up to 80 MHz)
+*/
+ writel(0x000A0003, regs-nwcfg);
Well you know ... magic numbers and defined bits ;-)
:-) Or. let me create macros.
+ /*
+* Following is the setup for DMA Configuration register.
+* Bits 4-0: To set AHB fixed burst length for DMA data operations -
+* Set with binary 00100 to use INCR4 AHB bursts.
+* Bits 9-8: Receiver packet buffer memory size -
+* Set with binary 11 to Use full configured addressable space (8 Kb)
+* Bit 10 : Transmitter packet buffer memory size -
+* Set with binary 1 to Use full configured addressable space (4 Kb)
+* Bits 23-16 : DMA receive buffer size in AHB system memory -
+* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer)
+*/
+ writel(0x00180704, regs-dmacr);
the same here.
+
+ /*
+* Following is the setup for Network Control register.
+* Bit 2: Set to enable Receive operation.
+* Bit 3: Set to enable Transmitt operation.
+* Bit 4: Set to enable MDIO operation.
+*/
+ tmp = readl(regs-nwctrl);
+ /* MDIO, Rx and Tx enable */
+ tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK |
+ ZYNQ_GEM_NWCTRL_TXEN_MASK;
+ writel(tmp, regs-nwctrl);
setbits_le32()
ok.
+ /* interface - look at tsec */
+ phydev = phy_connect(priv-bus, priv-phyaddr, dev, 0);
+
+ phydev-supported = supported;
+ phydev-advertising = phydev-supported;
+ priv-phydev = phydev;
+ phy_config(phydev);
+ phy_startup(phydev);
+
+ priv-initialized = 1;
+ return 0;
+}
+
+static int
Re: [U-Boot] [PATCH 3/4 v2] arm: Support new Xilinx Zynq platform
On 09/13/2012 12:31 PM, Marek Vasut wrote:
Dear Michal Simek,
On 09/13/2012 11:31 AM, Marek Vasut wrote:
Dear Michal Simek,
[...]
+#include config.h
+#include linux/linkage.h
+
+ENTRY(lowlevel_init)
+mov pc, lr
+ENDPROC(lowlevel_init)
inline void lowlevel_init(void) {} works as well and you don't need the
assembly file.
:
:-) yes. The reason why I have done it in this way that we have some asm
:code
which will go to this area. That's why I have kept it in asm instead of C.
What code? Will the code go into lowlevel_init() ?
For example SLCR locking if is not locked from the first stage bootloader.
Also if necessary OCM and DDR remap, FPGA reset can be also there
based on configuration.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
