Re: [coreboot] SPI controller and Lock bits

ks! I had a lot of fun, and this community is really great! I hope we still get to work together again in the future and cross paths! > On Tue, Oct 16, 2018 at 7:45 PM Sam Kuper wrote: >> >> Hi Youness, >> >> On 15/10/2018, Youness Alaoui wrote: >> > One t

Re: [coreboot] SPI controller and Lock bits

Hi Everyone! Sorry for the 2 weeks late reply, I've read your responses, but I've been too busy and dealing with stuff and haven't had/taken the time to reply but your input was very much appreciated and not ignored! One thing to note is that this week will be my last week at Purism as I'm going

Re: [coreboot] SPI controller and Lock bits

On Sat, Sep 29, 2018 at 12:21 PM Nico Huber wrote: > > On 9/27/18 10:29 PM, Youness Alaoui wrote: > > Thanks everyone for the responses. > > So far my understanding on the task at hand is : > > - Add a CONFIG to decide if we set FLOCKDN or not (and one to decide > &g

Re: [coreboot] SPI controller and Lock bits

Oh boy, lots of emails to answer! So first, thanks for everyone who shared their input, I very much appreciate it. > I think you can decide what hardware your products include, right? I meant dedicated hardware on the mainboard. Yes, but I'm currently looking for a solution to existing hardware,

Re: [coreboot] SPI controller and Lock bits

On Thu, Sep 27, 2018 at 10:18 PM Sam Kuper wrote: > > On 28/09/2018, Peter Stuge wrote: > > Youness Alaoui wrote: > >> avoid any malware writing to the flash > > > > Just disallow flash writes by the platform. Allow flash writes only > > by dedicated hard

Re: [coreboot] SPI controller and Lock bits

Thanks everyone for the responses. So far my understanding on the task at hand is : - Add a CONFIG to decide if we set FLOCKDN or not (and one to decide if we lock it on the resume path?) - Remove the chipset_lockdown devicetree config and change the code to always assume it's LOCKDOWN_COREBOOT

[coreboot] SPI controller and Lock bits

Hi, I'm trying to add a way to lock the SPI flash to be read-only via software *after* coreboot boots. The scenario is basically with using Heads, you could authenticate to it (with a yubikey/nitrokey/librem key) then be able to flash a new rom (update your BIOS), but once you boot an OS, Heads

Re: [coreboot] T450S + Coreboot

On Sat, Sep 8, 2018 at 2:31 PM Peter Stuge wrote: > > Youness Alaoui wrote: > > So, back to the ME, we know exactly what it does, it's all extremely > > well documented and explained > > I disagree with this. > > It is absolutely true that *some* of what the ME does

Re: [coreboot] T450S + Coreboot

because it's younger" nor will it be based on "for some unknown reason, AMD will be fine with us reverse engineering it". Besides, my understanding is that coreboot does not support ryzen CPUs, so a huge amount of work would be required if we went that way, no ? > Best r

Re: [coreboot] T450S + Coreboot

for "Youness" to see my blog posts in chronological order on the right side bar. Good luck with your project! > Make It So, > Brian Herman > > > > > > > > > > > > So you have made it to the end.. > Thanks for reading! > > On Wed, Aug 29

Re: [coreboot] T450S + Coreboot

Wow, Mike, seriously, I am going to side 100% with Nico, you are spreading FUD, making your own personal opinions (which are themselves derived from other people's FUD) and stating them as the universal law. The ME is not known to be a backdoor. It doesn't mean that it's not a backdoor, it simply

Re: [coreboot] Intel ME what is it? And when did this dangerous thing get installed?

I think there's a good explanation of it in the FAQ of the libreboot project here : https://libreboot.org/faq.html#intelme If there are more specific questions that you have, ask them and I might be able to answer them! On Wed, Aug 29, 2018 at 2:36 AM Gregg Levine wrote: > > Hello! > Would one

Re: [coreboot] Using linux as payload

Hi, I might not be the best one to answer your question, but here are my thoughts : - the "unknown type 'payload'" error is probably because cbfs changed the type name from "payload' to "simple elf" since you can add elfs in there that are not actual 'payloads'. I think though that it

Re: [coreboot] Kaby Lake FSP

y, I would expect the > frequency of FSP releases to lengthen as a platform ages. > > Thanks, > Nate > > -Original Message- > From: Youness Alaoui [mailto:kakar...@kakaroto.homelinux.net] > Sent: Monday, July 16, 2018 12:29 PM > To: Desimone, Nathaniel L

Re: [coreboot] Kaby Lake FSP

Hi Nate, Thanks a lot for listening to our request and taking care of this! I'm happy to see the binaries finally updated and the FSP headers in coreboot having a matching publicly available binary to use. You've only mentioned Kabylake in your email, is it safe to assume that you'll use these

Re: [coreboot] Porting coreboot to new board

ard ? > I think there are no "Intel® XEON® Processor E3-1505M v5" boards in last > version of coreboot. > Am I right ? > > Best regards, > Zvika > > On Tue, May 29, 2018 at 9:15 PM Youness Alaoui > wrote: >> >> Hi, >> >> I suggest y

Re: [coreboot] Porting coreboot to new board

Hi, I suggest you read the wiki : https://www.coreboot.org/Developer_Manual and https://www.coreboot.org/Motherboard_Porting_Guide I would also suggest maybe (optional) that you read my blog posts about my own experience porting coreboot to a new motherboard :

Re: [coreboot] FSP 2.0 headers in coreboot

On Fri, May 18, 2018 at 2:59 PM, Nico Huber wrote: > > I have to admit, I don't like your patch. While it gets the job done, > it brings `MemInfoHob.h` and `FspsUpd.h` out of sync, so the state in > coreboot as a whole would match neither version. > Good point. It is a

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

et so it's at that address, and the len has to match (or be superior) to the ucode file size. I hope that helps, Youness. On Sun, May 20, 2018 at 7:25 PM, Piotr Król <piotr.k...@3mdeb.com> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA256 > > > > On 05/18/2018 07:53 PM,

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

Hi Piotr, The Librems use the FSP 2.0 for SKL because I was told (I can't remember by who, but I think it was on coreboot IRC channel) that the FSP 2.0 works for both Skylake and Kabylake and that FSP 2.0 was better supported within coreboot than FSP 1.1. We had the Librems use FSP 1.1 before,

Re: [SeaBIOS] Librem 15v3 hangs at Booting from Hard Disk...

On Wed, May 9, 2018 at 9:14 PM, Philip C. wrote: > Hello everyone! > > I've been having some issues with a laptop recently. My Librem 15v3 was > bouncing along, until one day I ran into an apt-get upgrade issue. I > attempted to fix the affected script by pointing it to the

Re: [coreboot] FSP 2.0 headers in coreboot

I feel like this discussion is getting slightly out of hand, so let's try to regroup a bit and move the discussion back to the original topic : how to handle the FSP headers in coreboot. I fully understand and agree with Nico's frustration about the blobs situation and I think that's a bigger

Re: [coreboot] FSP 2.0 headers in coreboot

Sorry for being late to answer to my own thread (busy busy busy). A few notes : The initial check-in of the kabylake FSP was uploaded with a BSD license : https://github.com/IntelFsp/FSP/tree/d88078a708e768c7b6ee5cbc996299d303c3c702/KabylakeFspBinPkg Later commits added Intel's Restricted Use

[coreboot] FSP 2.0 headers in coreboot

Hi, I've just pushed a commit for review on gerrit (https://review.coreboot.org/#/c/coreboot/+/26108/) and I'm hoping to open the discussion here on whether the public coreboot code should have the FSP headers that match the public FSP headers or if they should match the 'google fsp' headers. My

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

I set that, I was able to access Index I/O on my coreboot-ed machine, and that opens up the software-based flashing support. On Mon, Mar 5, 2018 at 5:34 PM, Youness Alaoui <kakar...@kakaroto.homelinux.net> wrote: > Thanks for the advice Mike, but I think you misunderstood the issue. I

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

tp://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate ; > in short : use a keyboard flex cable to reach EC spi pins as well as > its' ground, and a test hook clip to easily get a ground of your > motherboard > > On Mon, Mar 5, 2018 at 11:00 PM, Youness Alaoui > <kakar...@kakaroto.h

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

On Sun, Mar 4, 2018 at 4:50 AM, Paul Kocialkowski <cont...@paulk.fr> wrote: > Hi, > > Le vendredi 16 février 2018 à 14:09 -0500, Youness Alaoui a écrit : >> > > Sure, you can trust hardware flashing more than software flashing, >> > > but >> > &

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

/O on the device via UART. Also, > note that the emulator can now emulate a virtual console so it's > already possible to build and interract with the firmware! > That's some really great news. A dev board will definitely be useful for testing/debugging/developing Origami-EC! > Cheers, > >

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

g (or AMI is doing right.. my guess is that it's probably something with the EC ACPI code), we'd have to figure that out first in order to get the read/write support. > > Latest status update for Origami-EC firmware: > https://www.mail-archive.com/coreboot@coreboot.org/msg50646.

Re: [coreboot] ENE KB3940Q-A1 embedded controller custom firmware

Hi Marty, Unfortunately, the EC firmware on the Librems is not open and we have someone working on that aspect, but with everything we have to handle, I think it's only being done part time. We found something similar to you with the private submodule for the PS/2 module on the OLPC code. More

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Sat, Dec 23, 2017 at 11:32 PM, taii...@gmx.com wrote: > On 12/23/2017 07:16 PM, Todd Weaver wrote: > >> Intel did not mislead, we told them, and continue to, that we _want_ an >> ME-less design (which is their term for what we asked for). And as we >> grow our leverage will

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Sat, Dec 23, 2017 at 12:28 AM, Zoran Stojsavljevic wrote: > Hello Youness, > > With all due respect, you write too long emails, trying to defend > Purism. Lot of yours argument I do not buy. > Some of them I do. > I know I write too long emails, a long time ago I

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Tue, Dec 19, 2017 at 8:04 PM, taii...@gmx.com <taii...@gmx.com> wrote: > On 12/18/2017 01:59 PM, Youness Alaoui wrote: > >> As for Taiidan's response, I think Matt's response to it is pretty >> good already, and I'm tired of seeing Taiidan jumping at the chance to >

Re: [coreboot] Coreboot Purism BIOS is free? open?

oncerns, and we have > experience with truly blob-free, powerful hardware -- combining those > two could yield an interesting machine... > > On 12/19/2017 02:41 PM, Youness Alaoui wrote: >> On Tue, Dec 19, 2017 at 2:07 PM, Timothy Pearson >> <tpear...@raptorengineeri

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Tue, Dec 19, 2017 at 2:07 PM, Timothy Pearson wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 12/19/2017 11:51 AM, Dame Más wrote: >> I finished the University and I have free time to do things. And this >> seems like an interesting project to

Re: [coreboot] Coreboot Purism BIOS is free? open?

Hi Dame, The coreboot on Purism machines is indeed open and available, and it is all merged into upstream coreboot, so there is no specific repository for it other than the coreboot repository (the code is in src/mainboard/purism/ subdirectory). Here is the build script we use to build coreboot

Re: [coreboot] Black screen during SeaBIOS boot

Try a 'cbmem -t' to see how long coreboot itself took to boot. There might be some delay somewhere causing it to take longer to boot (current system I'm on, it takes 8 seconds, and on other systems I saw it take 15 seconds, because it waits for the ME to respond until it times out) so it might not

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

ear...@raptorengineering.com> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > Thank you for the detailed response; I figured there had to be some > basic miscommunication somewhere. :-) So I assume we now agree that the > ME on Sylake + is not disabled, merely limited? &

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

s) the kernel loads the BUP, and the HAP bit only disables > the normal userspace processes [1]. > > What proof do you have that the kernel itself is halted? > > [1] http://blog.ptsecurity.com/2017/08/disabling-intel-me.html > > On 12/13/2017 11:34 AM, Youness Alaoui wrote

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

> I guess I still disagree with the use of the word "disabled". If the ME > wasn't required for boot, and was actually disabled within a few cycles > of its CPU starting, the remaining attack surface simply wouldn't exist. > This is not what happens though, and AFAIK even the ME kernel continues

Re: [coreboot] What’s the release plan for coreboot 4.7?

Hi, What happened with the plan for the 4.7 release? I thought it was supposed to be out at the end of October, now we're approaching the end of November. Was it forgotten, delayed or cancelled ? If delayed, what's the blocking issue ? Thanks, Youness. On Wed, Oct 4, 2017 at 11:24 AM, Martin

Re: [coreboot] greetings and laptop questions

> While I understand your frustration, and agree with the general thrust > of your email, and disregarding the "10 years", the Samsung Chromebook > Plus (and many other devices of similar age) beg to differ. > There are devices from 2016 and 2017 shipping with coreboot and no CPU > level blobs in

Re: [coreboot] greetings and laptop questions

On Sun, Oct 8, 2017 at 6:15 PM, taii...@gmx.com wrote: > >> >> (I also am looking at system76 and Purism but I am bit leery of spending a >> lot with a small / new company - comments appreciated) > > Purism dishonestly markets their products - while they claim that their >

Re: [coreboot] SPI Flash debug console on H8SCM

Hi Fabian, It was ported to older intel architectures by Nicola Corna here : https://review.coreboot.org/#/c/21107/ I don't know what would need to be done to port it to work with amd, but in theory, all it needs is for the chipset to support SPI operations. If it can read and write to the spi

[SeaBIOS] [PATCH] hw/nvme: Enable NVMe support for non-qemu hardware

/pipermail/seabios/2017-May/011356.html) but the patch was incomplete, so I've updated mine to mention it. Patch is inlined below for review. Thanks! Youness. >From ff8e3f40cbf5a4cc6035635ae23462505265a74a Mon Sep 17 00:00:00 2001 From: Youness Alaoui <youness.ala...@puri.sm> Date

Re: [SeaBIOS] [PATCH] hw/nvme: Enable NVMe support for non-qemu hardware

Thanks! And sorry, seems I registered using one email address and sent the patch using another. On Mon, Jun 12, 2017 at 9:12 PM, Kevin O'Connor <ke...@koconnor.net> wrote: > On Mon, Jun 12, 2017 at 05:53:24PM -0600, Youness Alaoui wrote: >> I submitted this a while back (A

[coreboot] SPI Flash debug console

Hi everyone, I mentioned this during my presentation at the coreboot conference last week, and I was waiting for it to be merged before I announced it on the mailing list. For those of you working on recent hardware (this was tested on skylake only, for broadwell to work, we need to add the spi

Re: [coreboot] Denver conference

wrote: > On Thu, Jun 1, 2017 at 2:46 PM, Youness Alaoui > <kakar...@kakaroto.homelinux.net> wrote: >> >> Then I suppose once they arrive at the conference registration booth >> to get their lanyard, they'll be told hat they haven't paid yet and >> that

Re: [coreboot] Denver conference

boot list? ;-) > > Zoran > > On Thu, Jun 1, 2017 at 9:31 PM, Youness Alaoui > <kakar...@kakaroto.homelinux.net> wrote: >> >> If you registered for the conference, and didn't receive the invoice >> to pay the conference attendance fees, then let Martin know that

Re: [coreboot] Denver conference

If you registered for the conference, and didn't receive the invoice to pay the conference attendance fees, then let Martin know that you didn't receive the invoice. If you received it, then pay it and that's it. On Thu, Jun 1, 2017 at 2:35 PM, Zoran Stojsavljevic

Re: [coreboot] GPIO PADRSTCFG conflict in datasheet

ues for RSMRST depending on whether it's GPP or GPD, so I vote for changing the define in coreboot so it stops being confusing for those who want to use RSMRST. I'll send a patch shortly to do it as I suggested in my previous email, unless someone else has a better idea. Thanks, Youness. On Thu, May

Re: [coreboot] VGA rom doesn't work

Congratulations on getting the ME working again. Your VGA device is 8086,1616, so that's what you need to set. The 8086,0406 is probably just the default one in coreboot, but you still have to configure it. In 'make menuconfig', go to Devices menu and set the "VGA Device ID" to "8086,1616", then

[coreboot] GPIO PADRSTCFG conflict in datasheet

Hi, I'm working on a skylake port and I've noticed something with the PADRSTCFG field of the GPIO Pad configuration. If you look at the 100-series datasheet volume 2 ( https://www-ssl.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html). The Pad configuration DW0 for

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

nic...@gmx.de> wrote: > On 03.05.2017 01:39, Youness Alaoui wrote: > > to answer Nico's other post: > > I'm quite surprised and disappointed by your answer. You have every right > > to say that you are disappointed or distrusting Purism due to past > actions, &

Re: [coreboot] Will we maintain Skylake/FSP1.1?

I thought FSP 1.1 was for skylake and FSP 2.0 for Kabylake, I didn't realize 2.0 would be compatible with skylake too. Does this mean a skylake port could use fsp 1.1 or 2.0 ? In that case, is the 2.0 version better maintained, more stable, easier to integrate, etc.. or are both 1.1 and 2.0

[coreboot] PCIe Role-based error reporting

Hi, I'm looking at the src/device/pciexp_device.c file trying to understand what it does and I've noticed this in pciexp_enable_aspm : /* Enable ASPM role based error reporting. */ devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); devcap |= PCI_EXP_DEVCAP_RBER; pci_write_config32(endp,

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

Looks like I failed at answering Taiidan without generating a flame war. Sorry if anyone got offended, that wasn't my aim. To answer the various questions that were thrown, here's what I think : Taiidan, you ask why Purism doesn't just create laptops using FX2 or ARM or whatever... Well, because

Re: [coreboot] Remote security exploit in all 2008+ Intel platforms

On Mon, May 1, 2017 at 7:22 PM, taii...@gmx.com wrote: > On 05/01/2017 06:44 PM, ron minnich wrote: > > On Mon, May 1, 2017 at 1:17 PM Rene Shuster >> wrote: >> >> Yes Puri.sm has been debunked. >>> >>> I disagree. I've seen the systems. From what I

Re: [coreboot] Intel ME The Way of the Static Analysis

Thanks for the links. This is the article that I had seen : http://blog.ptsecurity.com/2017/04/intel-me-way-of-static-analysis.html On Tue, Apr 25, 2017 at 10:38 AM, Shawn wrote: > slide: > https://www.troopers.de/downloads/troopers17/TR17_ME11_Static.pdf > > video: >

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

t least SBIOS and descriptor.bin from real (UEFI) > BIOS, and put, where? > > And then, to add to the Coreboot image. Using make menuconfig. Where and > how? > > (Courtesy Aaron Durbin): http://elinux.org/Minnowboard:MinnowMaxCoreboot# > TXE_and_SPI_descriptor > > Thank you all

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

Zoran, read this : https://puri.sm/posts/librem-13-coreboot-report-january-12-2017/ It might help you understand what that IFD and 0x5aa5f00f is (little endian makes it 0x0FF0A55A) I had the same confusion when I started, and when I figured things out, I wrote that blog post that explained the

Re: [E-devel] EFL Portability (need BSD, Solaris and Windows input!)

Hi Gustavo, I'd have to agree with you on how the includes should be done, the only issue I see is that there are some things that you just can't do that way. Without actually testing, I can't guarantee it will just work, but from what I remember, we had to include Escape.h in some places because

Re: [E-devel] E SVN: kakaroto trunk/edje/src/bin

to backport it. On Wed, Nov 28, 2012 at 1:46 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: Oh cool, I'll backport it tomorrow! Thanks! I never realized there were branches, I thought new releases were always taken from the trunk! Thanks for the answers! On Tue, Nov 27, 2012

Re: [E-devel] E SVN: kakaroto trunk/edje/src/bin

Backported? Sorry, what do you mean ? Are there different development branches now ? (I haven't paid much attention to E develpment lately) If yes, then yeah, it should be backported as it's a critical fix in my opinion. On Mon, Nov 26, 2012 at 4:26 AM, Cedric BAIL cedric.b...@free.fr wrote: On

Re: [E-devel] E SVN: kakaroto trunk/edje/src/bin

Oh cool, I'll backport it tomorrow! Thanks! I never realized there were branches, I thought new releases were always taken from the trunk! Thanks for the answers! On Tue, Nov 27, 2012 at 9:59 PM, Carsten Haitzler ras...@rasterman.comwrote: On Tue, 27 Nov 2012 11:45:20 -0500 Youness Alaoui

Re: [E-devel] E SVN: kakaroto trunk/GAMES/eskiss/data/edje

Ah ok, thanks for the clarification. Issue was that edje_cc complains now with an error, so eskiss wasn't compiling anymore. On Sat, Jul 21, 2012 at 4:28 PM, Gustavo Sverzut Barbieri barbi...@profusion.mobi wrote: On Sat, Jul 21, 2012 at 1:50 PM, Enlightenment SVN no-re...@enlightenment.org

Re: [E-devel] [e-users] Exquisite bootsplash release

Haitzler ras...@rasterman.comwrote: On Mon, 20 Feb 2012 04:00:16 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: On Sun, Feb 19, 2012 at 11:44 PM, Carsten Haitzler ras...@rasterman.comwrote: On Fri, 17 Feb 2012 01:16:12 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net

Re: [Amsn-devel] 0.99 TODO

0.99 TODO 1) Close the vulnerability bug, explain that it really is no vulnerability, get back to all distros... then possibly close the tracker and redirect to forum/ML/IRC Was fixed, vivia did the tests, 0.98.4 was indeed vulnerable 2) MSNP2Pv2 (me, possibly with help from

Re: [Amsn-devel] 0.99 TODO

with the jump from msnp6 to msnp9, with a checkbox in the login screen. What do you think ? KaKaRoTo On Fri, May 18, 2012 at 7:18 PM, Philippe Valembois - Phil lephilouso...@users.sourceforge.net wrote: Le 18/05/2012 23:47, Youness Alaoui a écrit : 0.99 TODO 1) Close

Re: [Patch] Fix ftdi.h for async write API change

On Mon, Mar 26, 2012 at 11:28 AM, Thomas Jarosch thomas.jaro...@intra2net.com wrote: On Monday, 26. March 2012 00:26:45 Youness Alaoui wrote: I've been playing around withlibftdi and I noticed that the git master version has an API change, removing the ftdi_{read|write}_data_async

Re: [E-devel] [e-users] Exquisite bootsplash release

On Sun, Feb 19, 2012 at 11:44 PM, Carsten Haitzler ras...@rasterman.comwrote: On Fri, 17 Feb 2012 01:16:12 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: (FYI: for those who didn't read from IRC, when Carsten realized I meant to transform exquisite into a library+tools

Re: [E-devel] EFL documentation

Good stuff! :) Any chance this will cover internals too (maybe as a secondary objective) ? While the public API is generally well documented, internal APIs aren't. I'm referring anyways to the difficulty to understand how to write a new evas engine for example. On Fri, Feb 17, 2012 at 3:22 PM,

Re: [E-devel] [e-users] Exquisite bootsplash release

, KaKaRoTo On Tue, Feb 14, 2012 at 12:25 AM, Carsten Haitzler ras...@rasterman.comwrote: On Tue, 14 Feb 2012 00:07:38 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: well it's more because it really has very little additional beyond a progressbar and it functions for the same purpose

Re: [E-devel] [e-users] Exquisite bootsplash release

...@rasterman.comwrote: On Sun, 12 Feb 2012 07:13:39 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: ummm... if an app wants to do this its as easy as loading an edje obj and sending signals/setting text and dragables. that's a VERY thin library there. you want this for app splashes while apps

Re: [E-devel] [e-users] Exquisite bootsplash release

Haitzler ras...@rasterman.comwrote: On Mon, 13 Feb 2012 03:46:22 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: hmm well if mainloop is alive... making an elementary widget would be the way to go... :) call it the splash widget - u can fill a window with it, just put it on the left

Re: [E-devel] [e-users] Exquisite bootsplash release

This looks pretty good! I've been thinking that this could be used for applications as well, not just for the init scripts. So I'm thinking of modifying exquisite into a libexquisite (which the exquisite tool itself would use). It's basically just about having a way of creating an exquisite (edje)

Re: [E-devel] Edje aspect.preference big-endian issue

01:01:45 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net said: i expected you would have already... ? commit! :) hehe, well, I just looked over edje_private.h and I didn't see any enum being used like aspect_preference was.Although maybe it's best if someone else had a quick look

Re: [E-devel] Windows installer

On Thu, Jan 19, 2012 at 12:15 AM, Sanjeev as290...@samsung.com wrote: Hi Vincent, I tested the windows installer, it installed without any issues. (Windows 7 Enterprise Edition) I think the following can be made better. 1. Picks up the default install folder as C:\Program Files\Efl. We

Re: [E-devel] Windows installer

On Thu, Jan 19, 2012 at 1:15 AM, Vincent Torri vincent.to...@gmail.comwrote: hey On Thu, Jan 19, 2012 at 6:32 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Thu, Jan 19, 2012 at 12:15 AM, Sanjeev as290...@samsung.com wrote: Hi Vincent, I tested the windows installer

Re: [E-devel] Windows installer

On Thu, Jan 19, 2012 at 1:50 AM, Vincent Torri vincent.to...@gmail.comwrote: On Thu, Jan 19, 2012 at 7:41 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Thu, Jan 19, 2012 at 1:15 AM, Vincent Torri vincent.to...@gmail.com wrote: hey On Thu, Jan 19, 2012 at 6:32 AM

Re: [E-devel] eina_lock_void issue

On Tue, Jan 17, 2012 at 11:26 PM, Carsten Haitzler ras...@rasterman.comwrote: On Sat, 14 Jan 2012 23:19:59 -0500 Michael Blumenkrantz michael.blumenkra...@gmail.com said: On Sat, 14 Jan 2012 23:15:37 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net wrote: Hi, I've just

Re: [E-devel] Edje aspect.preference big-endian issue

: On Fri, 13 Jan 2012 22:47:38 +0100 Cedric BAIL cedric.b...@free.fr said: On Fri, Jan 13, 2012 at 8:30 PM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Fri, Jan 13, 2012 at 10:32 AM, Cedric BAIL cedric.b...@free.fr wrote: On Fri, Jan 13, 2012 at 8:12 AM, Youness Alaoui kakar

Re: [E-devel] eina_lock_void issue

Oh, I just did a rebase on svn and you already committed a patch that did this. I thought it needed more discussion before a decision is made. Thanks! :) On Wed, Jan 18, 2012 at 12:32 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Tue, Jan 17, 2012 at 11:26 PM, Carsten Haitzler

Re: [Telepathy] Telepathy and EFL

On 01/15/2012 06:51 PM, Danielle Madeley wrote: 20:38 kuuko Hello, I'm looking into rewriting a python app that's using the low level telepathy functionality. I understand that telepathy-python has been deprecated in favor of telepathy-glib

Re: [E-devel] edje and epp

Good point about the authors.. There are 22 total who contributed to edje_cc* files and only 6 to edje_cc.c specifically. git log edje_cc* | grep Author | awk '{print $2}' | sort | uniq | wc 22 I definitely agree that it would be stupid to change the other libs or even edje itself to GPL, and I

[E-devel] eina_lock_void issue

Hi, I've just updated my EFL build for the PS3 and it was broken. eina_init isn't working anymore because eina_value doesn't init itself correctly. The issue is that if it's unable to iitialize a lock, it will fail the init which fails eina_init (and ecore_init, etc..) The problem is that on the

Re: [E-devel] eina_lock_void issue

On Sat, Jan 14, 2012 at 11:38 PM, Gustavo Sverzut Barbieri barbi...@profusion.mobi wrote: On Sun, Jan 15, 2012 at 2:19 AM, Michael Blumenkrantz michael.blumenkra...@gmail.com wrote: On Sat, 14 Jan 2012 23:15:37 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net wrote: Hi, I've

Re: [E-devel] eina_lock_void issue

On Sun, Jan 15, 2012 at 1:52 AM, David Seikel onef...@gmail.com wrote: On Sat, 14 Jan 2012 23:15:37 -0500 Youness Alaoui kakar...@kakaroto.homelinux.net wrote: Hi, I've just updated my EFL build for the PS3 and it was broken. eina_init isn't working anymore because eina_value doesn't

Re: [E-devel] eina_lock_void issue

, 2012 at 2:27 AM, Vincent Torri vincent.to...@gmail.comwrote: On Sun, Jan 15, 2012 at 8:06 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Sun, Jan 15, 2012 at 1:52 AM, David Seikel onef...@gmail.com wrote: On Sat, 14 Jan 2012 23:15:37 -0500 Youness Alaoui kakar

Re: [E-devel] eina_lock_void issue

win32 API. One call and that's all, it's faster than pthread-win32 and it consumes less memory. Vincent On Sun, Jan 15, 2012 at 2:27 AM, Vincent Torri vincent.to...@gmail.com wrote: On Sun, Jan 15, 2012 at 8:06 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: On Sun, Jan

Re: [E-devel] edje and epp

On Sun, Jan 15, 2012 at 2:36 AM, Michael Blumenkrantz michael.blumenkra...@gmail.com wrote: On Sun, 15 Jan 2012 08:26:17 +0100 Vincent Torri vincent.to...@gmail.com wrote: On Sun, Jan 15, 2012 at 8:06 AM, David Seikel onef...@gmail.com wrote: On Sun, 15 Jan 2012 08:00:06 +0100 Vincent

[E-devel] devilhorms: elementary broken

Hi, According to a user on #edevelop, the latest SVN version of elementary is broken since SVN r67129, the following chang eintroduced by devilhorns broke it : http://trac.enlightenment.org/e/changeset/67129 This removes an API from ecore_evas which causes an undefined symbol in libelementary :

Re: [E-devel] Edje aspect.preference big-endian issue

On Fri, Jan 13, 2012 at 10:32 AM, Cedric BAIL cedric.b...@free.fr wrote: Hi, On Fri, Jan 13, 2012 at 8:12 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: I've had an issue recently when I tried to run my app (using edje) on the PS3, the aspect ratio of all the images were wrong

Re: [E-devel] E SVN: barbieri IN trunk/eina/src: include lib tests

You use 'timercmp' which is not POSIX and you're not checking for it in the configure... you should use something else instead or provide a replacement if it's not found. After the include of sys/time.h, I added a simple : #ifndef timercmp #define ... /* copy/pasted from /usr/include/sys/time.h */

Re: [E-devel] E SVN: barbieri IN trunk/eina/src: include lib tests

ok, that's another possible solution :) Thanks, I'll revert my local changes then. On Thu, Jan 12, 2012 at 11:45 AM, Gustavo Sverzut Barbieri barbi...@profusion.mobi wrote: On Thu, Jan 12, 2012 at 6:16 AM, Youness Alaoui kakar...@kakaroto.homelinux.net wrote: You use 'timercmp' which

[E-devel] Edje aspect.preference big-endian issue

Hi, I've had an issue recently when I tried to run my app (using edje) on the PS3, the aspect ratio of all the images were wrong, and it looked really bad. I investigated the issue and found out that the aspect_preference was the cause and that when it's set to 'BOTH' for example, the

Re: [E-devel] E SVN: kakaroto trunk/edje/src/lib

Alright, we reached the deadline (actually it was yesterday but I was busy) and there's still no real agreement about this, however it seems most of you want the patch reverted, so I will remove it and document it properly. Thanks for your input. On Mon, Jan 9, 2012 at 5:14 PM, Youness Alaoui

Re: [E-devel] E SVN: kakaroto trunk/edje/src/lib

Bruno, while your example is valid, it's not how it will usually be. Most of the time people will use animations, which are bound to keyboard/mouse events. In my code for example, I can scroll a list using the arrow keys, but if you press the arrow twice, then two signals are sent, thus canceling

Re: [E-devel] E SVN: kakaroto trunk/edje/src/lib

@Gustavo: I understand your point about leaks but I'd expect a developer to not need a visual aid for him to write proper code. Not leaking is standard programing knowledge, so it's not about being novice in using the EFL. My issue is that I don't want to destroy the objects, just hide them

Re: [E-devel] E SVN: kakaroto trunk/ecore/src/lib/ecore_con

No, on the ps3 :) On Sat, Jan 7, 2012 at 9:10 AM, Michael Blumenkrantz michael.blumenkra...@gmail.com wrote: On Sat, 7 Jan 2012 03:39:23 -0800 Enlightenment SVN no-re...@enlightenment.org wrote: Log: Ecore-con: Let's not break compilation if net/if.h is not found (or old system)

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