Re: [AMDGPU][DC] Bonaire - Unable to enable DC on Mobile CIK - Invalid Connector ObjectID

On 04/12/2018 12:54 AM, Alex Deucher wrote: On Thu, Apr 12, 2018 at 12:48 AM, Shawn Starr wrote: When trying an early 4.17-rc0 RPM from Fedora, I get: [2.794243] [drm:construct [amdgpu]] *ERROR* construct: Invalid Connector ObjectID from Adapter Service for

Re: [AMDGPU][DC] Bonaire - Unable to enable DC on Mobile CIK - Invalid Connector ObjectID

On Thu, Apr 12, 2018 at 12:48 AM, Shawn Starr wrote: > When trying an early 4.17-rc0 RPM from Fedora, > > I get: > > [2.794243] [drm:construct [amdgpu]] *ERROR* construct: Invalid Connector > ObjectID from Adapter Service for connector index:1! type 0 expected 3 > >

[AMDGPU][DC] Bonaire - Unable to enable DC on Mobile CIK - Invalid Connector ObjectID

When trying an early 4.17-rc0 RPM from Fedora, I get: [2.794243] [drm:construct [amdgpu]] *ERROR* construct: Invalid Connector ObjectID from Adapter Service for connector index:1! type 0 expected 3 We've had issues with connector types on this laptop before and found some workarounds,

Re: [PATCH v4 2/2] drm/amdgpu: Free VGA stolen memory as soon as possible.

On Thu, Apr 12, 2018 at 12:08 AM, Andrey Grodzovsky wrote: > Reserved VRAM is used to avoid overriding pre OS FB. > Once our display stack takes over we don't need the reserved > VRAM anymore. > > v2: > Remove comment, we know actually why we need to reserve the stolen

Re: [PATCH v4 1/2] drm/amdgpu/gmc: steal the appropriate amount of vram for fw hand-over

On 04/12/2018 12:16 AM, Alex Deucher wrote: On Thu, Apr 12, 2018 at 12:08 AM, Andrey Grodzovsky wrote: From: Alex Deucher Steal 9 MB for vga emulation and fb if vga is enabled, otherwise, steal enough to cover the current display size as

Re: [PATCH v4 1/2] drm/amdgpu/gmc: steal the appropriate amount of vram for fw hand-over

On Thu, Apr 12, 2018 at 12:08 AM, Andrey Grodzovsky wrote: > From: Alex Deucher > > Steal 9 MB for vga emulation and fb if vga is enabled, otherwise, > steal enough to cover the current display size as set by the vbios. > > If no memory is used

[PATCH v4 2/2] drm/amdgpu: Free VGA stolen memory as soon as possible.

Reserved VRAM is used to avoid overriding pre OS FB. Once our display stack takes over we don't need the reserved VRAM anymore. v2: Remove comment, we know actually why we need to reserve the stolen VRAM. Fix return type for amdgpu_ttm_late_init. v3: Return 0 in amdgpu_bo_late_init, rebase on

[PATCH v4 1/2] drm/amdgpu/gmc: steal the appropriate amount of vram for fw hand-over

From: Alex Deucher Steal 9 MB for vga emulation and fb if vga is enabled, otherwise, steal enough to cover the current display size as set by the vbios. If no memory is used (e.g., secondary or headless card), skip stolen memory reserve. Signed-off-by: Alex Deucher

Re: [PATCH] drm/amdgpu/powerplay: rename smu7_upload_mc_firmware

Reviewed-by: Rex Zhu Best Regards Rex From: amd-gfx on behalf of Alex Deucher Sent: Thursday, April 12, 2018 7:11 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander

Re: [PATCH] drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji

Reviewed-by: Rex Zhu Best Regards Rex From: amd-gfx on behalf of Alex Deucher Sent: Thursday, April 12, 2018 6:59 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander

[PATCH v8 05/10] drm/dp_mst: Make drm_dp_mst_topology_state subclassable

This is useful for drivers (which will probably be all of them soon) which need to track state that is exclusive to the topology, and not a specific connector on said topology. This includes things such as the link rate and lane count that are shared by all of the connectors on the topology.

[PATCH v8 00/10] drm/i915: Implement proper fallback training for MST

Next version of https://patchwork.freedesktop.org/series/41576/ Only changes are removing duplicate SoBs that git send-email annoyingly added. Sorry about that :( Lyude Paul (10): drm/atomic: Print debug message on atomic check failure drm/i915: Move DP modeset retry work into intel_dp

RE: RFC for a render API to support adaptive sync and VRR

> From: Michel Dänzer [mailto:mic...@daenzer.net] > Sent: Wednesday, April 11, 2018 05:50 > On 2018-04-11 08:57 AM, Nicolai Hähnle wrote: > > On 10.04.2018 23:45, Cyr, Aric wrote: > >> How does it work fine today given that all kernel seems to know is > >> 'current' or 'current+1' vsyncs. > >>

[PATCH] drm/amdgpu/powerplay: rename smu7_upload_mc_firmware

It doesn't actually upload any firmware is just checks the version. The actual upload happens in the gmc modules. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH] drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji

Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-)

[PATCH v7 05/10] drm/dp_mst: Make drm_dp_mst_topology_state subclassable

This is useful for drivers (which will probably be all of them soon) which need to track state that is exclusive to the topology, and not a specific connector on said topology. This includes things such as the link rate and lane count that are shared by all of the connectors on the topology.

[PATCH v7 00/10] drm/i915: Implement proper fallback training for MST

Next version of https://patchwork.freedesktop.org/series/41576/ All changes in this patch series are just to make checkpatch a little happier, no functional changes. Lyude Paul (10): drm/atomic: Print debug message on atomic check failure drm/i915: Move DP modeset retry work into intel_dp

[PATCH V3] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

Code is expecing to observe the same number of buffers returned from dma_map_sg() function compared to sg_alloc_table_from_pages(). This doesn't hold true universally especially for systems with IOMMU. The hardware actually needs the dma_address on a page by page basis. Joining multiple

Re: [PATCH xf86-video-amdgpu 3/5] Keep CRTC properties consistent

On 2018-04-11 04:39 AM, Michel Dänzer wrote: On 2018-04-10 08:02 PM, Leo Li wrote: On 2018-04-09 11:03 AM, Michel Dänzer wrote: On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: From: "Leo (Sunpeng) Li" In cases where CRTC properties are updated without going through

Re: [PATCH xf86-video-amdgpu 1/5] Add functions for changing CRTC color management properties

On 2018-04-11 04:39 AM, Michel Dänzer wrote: On 2018-04-10 08:02 PM, Leo Li wrote: On 2018-04-09 11:03 AM, Michel Dänzer wrote: On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: From: "Leo (Sunpeng) Li" This change adds a few functions in preparation of enabling CRTC

Re: [PATCH xf86-video-amdgpu 2/5] Hook up CRTC color management functions

On 2018-04-11 04:48 AM, Michel Dänzer wrote: On 2018-04-10 08:02 PM, Leo Li wrote: On 2018-04-09 11:03 AM, Michel Dänzer wrote: On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: From: "Leo (Sunpeng) Li" The functions insert into the output resource creation, and

Re: [PATCH] drm/amdgpu: Always call kfd post reset after reset

On 2018-04-11 03:47 PM, Shaoyun Liu wrote: > Even reset failed, kfd post reset need to be called to make lock balance on > kfd side > > Change-Id: I8b6ef29d7527915611be0b96a9cd039bc75bb0a9 > Signed-off-by: Shaoyun Liu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7

Re: [PATCH] drm/amdgpu: Always call kfd post reset after reset

On Wed, Apr 11, 2018 at 3:47 PM, Shaoyun Liu wrote: > Even reset failed, kfd post reset need to be called to make lock balance on > kfd side > > Change-Id: I8b6ef29d7527915611be0b96a9cd039bc75bb0a9 > Signed-off-by: Shaoyun Liu Reviewed-by: Alex Deucher

[PATCH] drm/amdgpu: Always call kfd post reset after reset

Even reset failed, kfd post reset need to be called to make lock balance on kfd side Change-Id: I8b6ef29d7527915611be0b96a9cd039bc75bb0a9 Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-)

[PATCH v6 05/10] drm/dp_mst: Make drm_dp_mst_topology_state subclassable

This is useful for drivers (which will probably be all of them soon) which need to track state that is exclusive to the topology, and not a specific connector on said topology. This includes things such as the link rate and lane count that are shared by all of the connectors on the topology.

[PATCH v6 00/10] drm/i915: Implement proper fallback training for MST

Latest version of PW series 39642, hopefully this should also actually come up on intel-gfx and go through CI. No changes other than rebasing to the current drm-intel-next-queued Lyude Paul (10): drm/atomic: Print debug message on atomic check failure drm/i915: Move DP modeset retry work

Re: [PATCH 2/2] drm/amdgpu: Allow dma_map_sg() coalescing

Am 11.04.2018 um 19:11 schrieb Robin Murphy: Now that drm_prime_sg_to_page_addr_arrays() understands the case where dma_map_sg() has coalesced segments and returns 0 < count < nents, we can relax the check to only consider genuine failure. That pattern is repeated in pretty much all drivers

Re: [PATCH 1/2] drm/prime: Iterate SG DMA addresses separately

Am 11.04.2018 um 19:11 schrieb Robin Murphy: For dma_map_sg(), DMA API implementations are free to merge consecutive segments into a single DMA mapping if conditions are suitable, thus the resulting DMA addresses may be packed into fewer entries than ttm->sg->nents implies.

Re: [1/2] drm/prime: Iterate SG DMA addresses separately

On 11/04/18 18:11, Robin Murphy wrote: For dma_map_sg(), DMA API implementations are free to merge consecutive segments into a single DMA mapping if conditions are suitable, thus the resulting DMA addresses may be packed into fewer entries than ttm->sg->nents implies.

Re: [PATCH 3/3] drm/amd/pp: Remove struct pp_gpu_power

I am OK with this change. Regards, Eric On 2018-04-11 01:25 PM, Tom St Denis wrote: On 04/11/2018 01:23 PM, Alex Deucher wrote: On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: This struct can't be used for all asics. Currently smu only calculate average gpu power in real

Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

This patch change the power registers reading from average to maximum. If SMU team verifies it, I am OK with it. Regards, Eric On 2018-04-11 01:21 PM, Alex Deucher wrote: On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: pkgpwr is the average gpu power of 100ms. it is

Re: [PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

If it is verified by SMU team, I am OK with it. Regards, Eric On 2018-04-11 01:19 PM, Alex Deucher wrote: On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: we don't have limit of [50ms, 4sec] sampling period. smu calculate average gpu power in real time. we can read average

[PATCH 1/2] drm/prime: Iterate SG DMA addresses separately

For dma_map_sg(), DMA API implementations are free to merge consecutive segments into a single DMA mapping if conditions are suitable, thus the resulting DMA addresses may be packed into fewer entries than ttm->sg->nents implies. drm_prime_sg_to_page_addr_arrays() does not account for this,

[PATCH 2/2] drm/amdgpu: Allow dma_map_sg() coalescing

Now that drm_prime_sg_to_page_addr_arrays() understands the case where dma_map_sg() has coalesced segments and returns 0 < count < nents, we can relax the check to only consider genuine failure. Signed-off-by: Robin Murphy --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-

Re: [PATCH] drm/amd/pp: Clear smu response register before send smu message

On Wed, Apr 11, 2018 at 6:20 AM, Rex Zhu wrote: > smu firmware do not update response register immediately under > some delay tasks. so we read out the original value. > > so clear the register first. > > Signed-off-by: Rex Zhu Acked-by: Alex Deucher

Re: [PATCH] drm/amd/pp: Fix logic error in smu7_check_dpm_table_updated

On Wed, Apr 11, 2018 at 8:00 AM, Rex Zhu wrote: > Signed-off-by: Rex Zhu Is this really worth it? It just saves a few cycles, but I'm worried if we ever extend or rewrite the function we may miss later updates. At the very least, I'd add a comment saying

Re: [PATCH 3/3] drm/amd/pp: Remove struct pp_gpu_power

On 04/11/2018 01:23 PM, Alex Deucher wrote: On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: This struct can't be used for all asics. Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, we can read them per 1ms through some registers. but

Re: [PATCH 3/3] drm/amd/pp: Remove struct pp_gpu_power

On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: > This struct can't be used for all asics. > > Currently smu only calculate average gpu power in real time. > > for vddc/vddci/max power, > we can read them per 1ms through some registers. but > > 1. the type of return values is not

Re: [PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: > pkgpwr is the average gpu power of 100ms. it is calculated by > firmware in real time. > > 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr > directly. > > 2. On Fiji/tonga/bonaire/hawwii, without

Re: [PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

On Wed, Apr 11, 2018 at 2:31 AM, Rex Zhu wrote: > we don't have limit of [50ms, 4sec] sampling period. > smu calculate average gpu power in real time. > we can read average gpu power through smu message or > read special register. > > This reverts commit

Re: RFC for a render API to support adaptive sync and VRR

On 2018-04-10 06:26 PM, Cyr, Aric wrote:> > My guess is they prefer to “do nothing” and let driver/HW manage it, > otherwise you exempt all existing games from supporting adaptive sync > without a rewrite or update. Nobody is saying adaptive sync should only work with explicit target presentation

Re: [PATCH V2] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

On 11/04/18 15:33, Sinan Kaya wrote: On 4/11/2018 8:03 AM, Robin Murphy wrote: On 10/04/18 21:59, Sinan Kaya wrote: Code is expecing to observe the same number of buffers returned from dma_map_sg() function compared to sg_alloc_table_from_pages(). This doesn't hold true universally especially

Re: [PATCHv2] drm/amdkfd: Remove vla

On 2018-04-10 09:02 PM, Laura Abbott wrote: > There's an ongoing effort to remove VLAs[1] from the kernel to eventually > turn on -Wvla. Switch to a constant value that covers all hardware. > > [1] https://lkml.org/lkml/2018/3/7/621 > > Signed-off-by: Laura Abbott > --- > v2:

Re: [PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read debugfs entry

On 04/11/2018 08:17 AM, Christian König wrote: Am 11.04.2018 um 14:03 schrieb Tom St Denis: On 04/11/2018 07:58 AM, Christian König wrote:   -    if (size & 3 || *pos & 3) +    if (size & 3 || size > (4 * AMDGPU_DEBUGFS_MAX_SGPR_READ)) I think checking the position alignment here is

Re: [PATCH 2/2] drm/amdgpu: Add APU support in vi_set_vce_clocks

On Wed, Apr 11, 2018 at 2:08 AM, Rex Zhu wrote: > 1. fix set vce clocks failed on Cz/St >which lead 1s delay when boot up. > 2. remove the workaround in vce_v3_0.c > > Reviewed-by: Alex Deucher > Reviewed-by: Huang Rui >

Re: [PATCH V2] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

On 10/04/18 21:59, Sinan Kaya wrote: Code is expecing to observe the same number of buffers returned from dma_map_sg() function compared to sg_alloc_table_from_pages(). This doesn't hold true universally especially for systems with IOMMU. So why not fix said code? It's clearly not a real

Re: Lenovo ThinkVision X1 27" USB-C occasionally hangs the kernel (usbhid) and isn't setting a proper resolution when USB 3.0 (FHD) switched to USB 2.0 (UHD)

On Wed, Apr 11, 2018 at 02:09:29PM +0300, Heikki Krogerus wrote: > On Wed, Apr 11, 2018 at 08:28:44AM +, andrey.ara...@nixaid.com wrote: > > Thank you for the insights, Heikki! > > > > Please find the acpi.dump.tgz file is a attached. > > > > I do not have the USBC* and INT3515* devices, >

[PATCH 3/5] drm/ttm: remove the backing store if no placement is given

Pipeline removal of the BOs backing store when the placement is given during validation. Signed-off-by: Christian König --- drivers/gpu/drm/ttm/ttm_bo.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c

[PATCH 1/5] dma-buf: use parameter structure for dma_buf_attach

Move the parameters into a structure to make it simpler to extend it in follow up patches. This also adds the importer private as parameter so that we can directly work with a completely filled in attachment structure. Signed-off-by: Christian König ---

[PATCH 4/5] drm/amdgpu: add independent DMA-buf export v2

Instead of relying on the DRM functions just implement our own export functions. This adds support for taking care of unpinned DMA-buf. v2: fix unintended recursion, remove debugging leftovers Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h

[PATCH 5/5] drm/amdgpu: add independent DMA-buf import v3

Instead of relying on the DRM functions just implement our own import functions. This adds support for taking care of unpinned DMA-buf. v2: enable for all exporters, not just amdgpu, fix invalidation handling, lock reservation object while setting callback v3: change to new dma_buf attach

[PATCH 2/5] dma-buf: add optional invalidate_mappings callback v3

Each importer can now provide an invalidate_mappings callback. This allows the exporter to provide the mappings without the need to pin the backing store. v2: don't try to invalidate mappings when the callback is NULL, lock the reservation obj while using the attachments, add helper to

[PATCH] drm/amdgpu: print DMA-buf status in debugfs

Just note if a BO was imported/exported. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index

[PATCH] drm/amd/pp: Fix logic error in smu7_check_dpm_table_updated

Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 68b9e0b..31d271f 100644

Re: [PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read debugfs entry

Am 11.04.2018 um 14:03 schrieb Tom St Denis: On 04/11/2018 07:58 AM, Christian König wrote:   -    if (size & 3 || *pos & 3) +    if (size & 3 || size > (4 * AMDGPU_DEBUGFS_MAX_SGPR_READ)) I think checking the position alignment here is still necessary, cause we can't read from not dw

Re: [PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read debugfs entry

On 04/11/2018 07:58 AM, Christian König wrote:   -    if (size & 3 || *pos & 3) +    if (size & 3 || size > (4 * AMDGPU_DEBUGFS_MAX_SGPR_READ)) I think checking the position alignment here is still necessary, cause we can't read from not dw boundaries don't we? The index is a dword

Re: [PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read debugfs entry

  -    if (size & 3 || *pos & 3) +    if (size & 3 || size > (4 * AMDGPU_DEBUGFS_MAX_SGPR_READ)) I think checking the position alignment here is still necessary, cause we can't read from not dw boundaries don't we? Christian. Am 11.04.2018 um 13:55 schrieb Tom St Denis: Ping? On

Re: [PATCH] drm/amd/amdgpu: Fix amdgpu_debugfs_gpr_read debugfs entry

Ping? On 04/09/2018 08:16 AM, Tom St Denis wrote: We don't need to check the alignment of the offset and there was potential a buffer overflow as well. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 ++-- 1 file changed, 6

[PATCH] drm/amd/pp: Clear smu response register before send smu message

smu firmware do not update response register immediately under some delay tasks. so we read out the original value. so clear the register first. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 +---

Re: RFC for a render API to support adaptive sync and VRR

On 2018-04-10 07:25 PM, Cyr, Aric wrote: >> From: Michel Dänzer [mailto:mic...@daenzer.net] >> On 2018-04-10 07:13 PM, Cyr, Aric wrote: From: Michel Dänzer [mailto:mic...@daenzer.net] On 2018-04-10 06:26 PM, Cyr, Aric wrote: > From: Koenig, Christian Sent: Tuesday, April 10, 2018

Re: RFC for a render API to support adaptive sync and VRR

On 2018-04-11 08:57 AM, Nicolai Hähnle wrote: > On 10.04.2018 23:45, Cyr, Aric wrote: > For video games we have a similar situation where a frame is > rendered > for a certain world time and in the ideal case we would actually > display the frame at this world time.

Re: [PATCHv2] drm/amdkfd: Remove vla

Am 11.04.2018 um 03:02 schrieb Laura Abbott: There's an ongoing effort to remove VLAs[1] from the kernel to eventually turn on -Wvla. Switch to a constant value that covers all hardware. [1] https://lkml.org/lkml/2018/3/7/621 Signed-off-by: Laura Abbott It would be nicer

Re: [PATCH 3/3] drm/amdgpu: set preferred_domain independent of fallback handling

Am 11.04.2018 um 04:38 schrieb zhoucm1: On 2018年04月10日 21:42, Christian König wrote: When GEM needs to fallback to GTT for VRAM BOs we still want the preferred domain to be untouched so that the BO has a cance to move back to VRAM in the future. Signed-off-by: Christian König

Re: [PATCH V2] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

Am 11.04.2018 um 08:26 schrieb Huang Rui: On Tue, Apr 10, 2018 at 04:59:55PM -0400, Sinan Kaya wrote: Code is expecing to observe the same number of buffers returned from dma_map_sg() function compared to sg_alloc_table_from_pages(). This doesn't hold true universally especially for systems

Re: [PATCH xf86-video-amdgpu 2/5] Hook up CRTC color management functions

On 2018-04-10 08:02 PM, Leo Li wrote: > On 2018-04-09 11:03 AM, Michel Dänzer wrote: >> On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: >>> From: "Leo (Sunpeng) Li" >>> >>> The functions insert into the output resource creation, and property >>> change functions. CRTC

Re: [PATCH xf86-video-amdgpu 1/5] Add functions for changing CRTC color management properties

On 2018-04-10 08:02 PM, Leo Li wrote: > On 2018-04-09 11:03 AM, Michel Dänzer wrote: >> On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: >>> From: "Leo (Sunpeng) Li" >>> >>> This change adds a few functions in preparation of enabling CRTC color >>> managment via the randr

Re: [PATCH xf86-video-amdgpu 3/5] Keep CRTC properties consistent

On 2018-04-10 08:02 PM, Leo Li wrote: > On 2018-04-09 11:03 AM, Michel Dänzer wrote: >> On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote: >>> From: "Leo (Sunpeng) Li" >>> >>> In cases where CRTC properties are updated without going through >>> RRChangeOutputProperty, we don't

[PATCH V2] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

Code is expecing to observe the same number of buffers returned from dma_map_sg() function compared to sg_alloc_table_from_pages(). This doesn't hold true universally especially for systems with IOMMU. IOMMU driver tries to combine buffers into a single DMA address as much as it can. The right

Re: RFC for a render API to support adaptive sync and VRR

On 10.04.2018 23:45, Cyr, Aric wrote: For video games we have a similar situation where a frame is rendered for a certain world time and in the ideal case we would actually display the frame at this world time. That seems like it would be a poorly written game that flips like that, unless they

[PATCH 3/3] drm/amd/pp: Remove struct pp_gpu_power

This struct can't be used for all asics. Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, we can read them per 1ms through some registers. but 1. the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. 2.

[PATCH 2/3] drm/amd/pp: Refine get_gpu_power for VI

pkgpwr is the average gpu power of 100ms. it is calculated by firmware in real time. 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr directly. 2. On Fiji/tonga/bonaire/hawwii, without PPSMC_MSG_GetCurrPkgPwr support. Send PPSMC_MSG_PmStatusLogStart/Sample to let smu

[PATCH 1/3] Revert "drm/amd/powerply: fix power reading on Fiji"

we don't have limit of [50ms, 4sec] sampling period. smu calculate average gpu power in real time. we can read average gpu power through smu message or read special register. This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71. Signed-off-by: Rex Zhu ---

[PATCH 2/2] drm/amdgpu: Add APU support in vi_set_vce_clocks

1. fix set vce clocks failed on Cz/St which lead 1s delay when boot up. 2. remove the workaround in vce_v3_0.c Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Acked-by: Shirish S

[PATCH 1/2] drm/amdgpu: Add APU support in vi_set_uvd_clocks

fix the issue set uvd clock failed on CZ/ST which lead 1s delay when boot up. Reviewed-by: Alex Deucher Reviewed-by: Huang Rui Acked-by: Christian König Acked-by: Shirish S Signed-off-by: Rex Zhu

Re: [PATCH V2] drm/amdgpu: limit DMA size to PAGE_SIZE for scatter-gather buffers

On Tue, Apr 10, 2018 at 04:59:55PM -0400, Sinan Kaya wrote: > Code is expecing to observe the same number of buffers returned from > dma_map_sg() function compared to sg_alloc_table_from_pages(). This > doesn't hold true universally especially for systems with IOMMU. > > IOMMU driver tries to