[AMD Official Use Only - Internal Distribution Only]
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, December 1, 2020 7:59 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/display: move
Fulfill the UMD PSTATE profiling clocks of sienna cichlid.
Change-Id: Ib9078c73d3fbd786080449255645ae8b9f879092
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 ++
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h | 4
2 files changed, 10
Hi Andrey,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-exynos/exynos-drm-next]
[also build test WARNING on drm-intel/for-linux-next
tegra-drm/drm/tegra/for-next drm-tip/drm-tip linus/master v5.10-rc7
next-20201208]
[cannot apply to drm/drm-next
On Tue, Dec 8, 2020 at 3:16 PM Andrey Grodzovsky
wrote:
>
> For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
> was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
> and amdgpu_gem_object_funcs setting into single function called
> from both code
Fulfill the 2nd usb2.0 port workaround for sienna cichlid.
Change-Id: Id5a89a468787846ed0050b56cd318a9574185567
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 38 ++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git
The workaround is needed by sienna cichlid.
Change-Id: Ib3d065b53dcb331d085e9bb9eeda99021a212206
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h | 2 ++
Used for determining 2ND_USB20PORT support from firmware_capability.
Change-Id: I3ff37f0a0dab311566bdd0aba189f2b7fa89ec2c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/atomfirmware.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
That will help to determine whether 2ND_USB20_PORT workaround is
needed for Sienna Cichlid.
Change-Id: I3852e7c8cb11c12845ca81e7967e332c499cb470
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h| 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 ++
2 files
New SMC message was introduced for gpo control on sienna cichlid.
Change-Id: I6f09ae96e9dd7a290c9975564740f597a08ff2fa
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_types.h| 1 +
.../gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h| 4 +-
Ping?
On Mon, Nov 30, 2020 at 6:59 PM Alex Deucher wrote:
>
> It's only used when CONFIG_DRM_AMD_DC_DCN is set. Fixes and set but
> not used warning.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
> 1 file changed, 1 insertion(+), 4
On Sun, Dec 6, 2020 at 10:45 PM Likun Gao wrote:
>
> From: Likun Gao
>
> Only APU should deal with the situation that amdgpu suspend/resume with
> s0i3 support to skip RLC/CP/GFX disable during suspend.
>
> Signed-off-by: Likun Gao
> Change-Id: Icca91b3497f12a6d78f005ee63461cf0e8f24958
> ---
>
Reviewed-by: Huang Rui
On Wed, Dec 09, 2020 at 10:19:24AM +0800, Deucher, Alexander wrote:
>[AMD Official Use Only - Internal Distribution Only]
>
>Acked-by: Alex Deucher
> __
>
>From: amd-gfx on behalf of
>
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher
From: amd-gfx on behalf of
Changfeng.Zhu
Sent: Tuesday, December 8, 2020 9:06 PM
To: amd-gfx@lists.freedesktop.org ; Huang, Ray
Cc: Zhu, Changfeng
Subject: [PATCH] drm/amd/pm:
From: changzhu
From: Changfeng
When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that
it can't be able to switch to mak gpu clk during compute workload.
It needs to update WORKLOAD_PPLIB setting to fix this issue.
Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd
On Tue, Dec 8, 2020 at 7:21 PM 'Nick Desaulniers' via Clang Built
Linux wrote:
>
> On Tue, Dec 8, 2020 at 6:26 AM Arnd Bergmann wrote:
> >
> > On Mon, Dec 7, 2020 at 11:28 PM 'Nick Desaulniers' via Clang Built
> > Linux wrote:
> Hmm...no warnings for me with t
On Tue, Dec 8, 2020 at 3:16 PM Andrey Grodzovsky
wrote:
>
> For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
> was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
> and amdgpu_gem_object_funcs setting into single function called
> from both code
[AMD Public Use]
Very good, thanks!
I'll take a look at the overlay ones, then.
-Original Message-
From: Simon Ser
Sent: Tuesday, December 8, 2020 7:00 AM
To: Cornij, Nikola
Cc: Alex Deucher ; Kazlauskas, Nicholas
; Deucher, Alexander ;
Wentland, Harry ; amd-gfx list
Subject: RE:
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single function called
from both code paths.
Fixes: d693def4fd1c ("drm: Remove obsolete GEM and PRIME
On 12/8/20 8:04 PM, Christian König wrote:
Am 08.12.20 um 19:59 schrieb Nirmoy Das:
BO created with amdgpu_bo_create_reserved() wasn't clean
properly before, which causes:
[ 21.056218] WARNING: CPU: 0 PID: 7 at
drivers/gpu/drm/ttm/ttm_bo.c:518 ttm_bo_release+0x2bf/0x310 [ttm]
[
From: Anthony Koo
- Add new aux_channel_type
- Changed port_index to instance in dmub_cmd_dp_aux_control_data
- Change aux_return_code_type to sync up with driver
- param for ramping abm based on backlight level
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Aric Cyr
[Why]
Typo in MPCC visual confirmation.
[How]
Fix to correct values.
Signed-off-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git
From: Aric Cyr
[Why]
FP2 is not double buffered and must wait for VACTIVE
before programming.
[How]
Only update when there is a full update we should
change FP2 to avoid delay every flip.
Signed-off-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
From: Felipe
[Why]
The OGAM LUT precision was accumulating too much error
in the higher end.
[How]
Instead of calculating all points of the LUT in relation
to the previous ones, perform a full calculation in one
of the intermediate segments to stop error propagation.
Signed-off-by: Felipe
From: "Leo (Hanghong) Ma"
[Why]
We are missing the DP info frame update on dcn30, and this will
lead to DP SDPs not being sent;
[How]
Add the DP info frame update for dcn30;
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Roman Li
Acked-by: Qingqing Zhuo
---
From: Jake Wang
[Why]
For certain timings, Renoir may underflow due to sr exit
latency being too slow.
[How]
Updated wm table for renoir.
Signed-off-by: Jake Wang
Reviewed-by: Yongqiang Sun
Acked-by: Qingqing Zhuo
---
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c| 12 ++--
From: Martin Leung
[Why]
race condition of programming FP2 wrt pipe locking
and vactive state can cause underflow/black screen
[How]
Enforce the FP2 is only programmed during vactive,
and unlock pipe soon afterwards.
Signed-off-by: Martin Leung
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
From: Eric Bernstein
[Why]
dcn30_link_encoder_validate_output_with_stream was a static function.
[How]
remove the static define and include it in the header.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
---
From: Victor Lu
[Why]
There is a warning that triggers when pstate takes too long.
Pstate can take up to ~200us on Linux without hanging but
it is currently set to 40us.
[How]
Change the timeout for the warning to be 180us on Linux.
Signed-off-by: Victor Lu
Reviewed-by: Roman Li
Acked-by:
From: Wayne Lin
[Why]
Find out when we try to disable CRC calculation,
crc generation is still enabled. Main reason is
that dc_stream_configure_crc() will never get
called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE.
[How]
Add checking condition that when source is
From: Aric Cyr
[Why]
Many VR headsets require a HSYNC width of 4, but DCN
has default minimum of 8.
[How]
Change the arbitrary minimum HSYNC width to 4 to match
DCN20.
Signed-off-by: Aric Cyr
Reviewed-by: Charlene Liu
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
---
From: Max Tseng
[Why]
some DP_SEC register defs and masks are missing.
[How]
add the missing defs and masks.
Signed-off-by: Max Tseng
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 6 ++
This DC patchset brings improvements in multiple areas.
In summary, we highlight:
* DC 3.2.116
* Firmware release 0.0.46
* Bug fixes on VR light up issues, missing register definitions, etc.
* Improvements on OGAM LUT calculation, FP2 timing and more
---
Anthony Koo (1):
drm/amd/display: [FW
Am 08.12.20 um 20:11 schrieb Andrey Grodzovsky:
On 12/8/20 2:01 PM, Christian König wrote:
Am 08.12.20 um 19:52 schrieb Andrey Grodzovsky:
On 12/8/20 1:47 PM, Christian König wrote:
Am 08.12.20 um 19:44 schrieb Andrey Grodzovsky:
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um
On 12/8/20 2:01 PM, Christian König wrote:
Am 08.12.20 um 19:52 schrieb Andrey Grodzovsky:
On 12/8/20 1:47 PM, Christian König wrote:
Am 08.12.20 um 19:44 schrieb Andrey Grodzovsky:
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20
Am 08.12.20 um 19:59 schrieb Nirmoy Das:
BO created with amdgpu_bo_create_reserved() wasn't clean
properly before, which causes:
[ 21.056218] WARNING: CPU: 0 PID: 7 at drivers/gpu/drm/ttm/ttm_bo.c:518
ttm_bo_release+0x2bf/0x310 [ttm]
[ 21.056430] Call Trace:
[ 21.056525]
Am 08.12.20 um 19:52 schrieb Andrey Grodzovsky:
On 12/8/20 1:47 PM, Christian König wrote:
Am 08.12.20 um 19:44 schrieb Andrey Grodzovsky:
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um
BO created with amdgpu_bo_create_reserved() wasn't clean
properly before, which causes:
[ 21.056218] WARNING: CPU: 0 PID: 7 at drivers/gpu/drm/ttm/ttm_bo.c:518
ttm_bo_release+0x2bf/0x310 [ttm]
[ 21.056430] Call Trace:
[ 21.056525] amdgpu_bo_unref+0x1a/0x30 [amdgpu]
[ 21.056635]
On 12/8/20 1:47 PM, Christian König wrote:
Am 08.12.20 um 19:44 schrieb Andrey Grodzovsky:
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs
Am 08.12.20 um 19:44 schrieb Andrey Grodzovsky:
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of
On 12/8/20 1:29 PM, Christian König wrote:
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in
[AMD Public Use]
Seems logical to me.
Reviewed-by: Kent Russell
> -Original Message-
> From: amd-gfx On Behalf Of Felix
> Kuehling
> Sent: Tuesday, December 8, 2020 12:31 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 1/1] drm/amdkfd: Fix leak in dmabuf import
>
> Release
Am 08.12.20 um 19:26 schrieb Andrey Grodzovsky:
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of
amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO
creation
On 12/8/20 12:36 PM, Christian König wrote:
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single
Looks good to me, Please feel free to use:
Reviewed-by: Shashank Sharma
Regards
Shashank
-Original Message-
From: Christian König
Sent: Tuesday, December 8, 2020 11:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sharma, Shashank
Subject: [PATCH] drm/amdgpu: limit the
Am 08.12.20 um 17:05 schrieb Alex Deucher:
Rather than in late_init to avoid race conditions between freeing the
buffers and the initial modeset.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König for patches #1
and #2, acked-by for #3.
---
Am 08.12.20 um 16:55 schrieb Nirmoy Das:
BO created with amdgpu_bo_create_reserved wasn't clean
properly before which causes:
I would rather like to keep the code as it is and just replace the
amdgpu_bo_unref() with amdgpu_bo_free_kernel().
But apart from that I think we can stick with
Am 08.12.20 um 18:10 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single function called
from both code paths.
Can you
Release dmabuf reference before returning from kfd_ioctl_import_dmabuf.
amdgpu_amdkfd_gpuvm_import_dmabuf takes a reference to the underlying
GEM BO and doesn't keep the reference to the dmabuf wrapper.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 ++
1 file
The text output should not be more than a page, so only print the first
32 page table entries.
If we need all of them we can still look into the binary trace.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
On Tue, Dec 8, 2020 at 12:10 PM Andrey Grodzovsky
wrote:
>
> For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
> was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
> and amdgpu_gem_object_funcs setting into single function called
> from both code
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single function called
from both code paths.
This fixes null ptr regression casued by commit
d693def drm:
If we need to keep the stolen vga memory, make sure it is
at least as big as the legacy vga size.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
No longer used.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h| 1 -
Rather than in late_init to avoid race conditions between freeing the
buffers and the initial modeset.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++--
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
2 files changed, 7 insertions(+), 6
BO created with amdgpu_bo_create_reserved wasn't clean
properly before which causes:
[ 21.056218] WARNING: CPU: 0 PID: 7 at drivers/gpu/drm/ttm/ttm_bo.c:518
ttm_bo_release+0x2bf/0x310 [ttm]
[ 21.056430] Call Trace:
[ 21.056525] amdgpu_bo_unref+0x1a/0x30 [amdgpu]
[ 21.056635]
[AMD Official Use Only - Internal Distribution Only]
Hi Dan,
Thanks for catching this!
I've removed the extra NULL check as it's not needed.
Cheers,
Eryk Brol
From: Dan Carpenter
Sent: Friday, December 4, 2020 10:18 AM
To: Brol, Eryk
Cc:
On 12/8/20 3:45 PM, Christian König wrote:
Yes, correct.
You could add an amdgpu_bo_free_reserved() function, but we only have
this one case for that so I think it's probably not worth it.
Just one more comment below.
Am 08.12.20 um 15:42 schrieb Nirmoy:
I think I know why I needed to keep
Yes, correct.
You could add an amdgpu_bo_free_reserved() function, but we only have
this one case for that so I think it's probably not worth it.
Just one more comment below.
Am 08.12.20 um 15:42 schrieb Nirmoy:
I think I know why I needed to keep that amdgpu_bo_unreserve() before
calling
I think I know why I needed to keep that amdgpu_bo_unreserve() before
calling amdgpu_bo_free_kernel().
amdgpu_bo_free_kernel() --> amdgpu_bo_reserve()->ttm_bo_reserve()-->
dma_resv_lock(bo->base.resv, ticket).
amdgpu_bo_create_reserved() already locked that dma_resv by calling
BO created with amdgpu_bo_create_reserved wasn't clean
properly before which causes:
[ 21.056218] WARNING: CPU: 0 PID: 7 at drivers/gpu/drm/ttm/ttm_bo.c:518
ttm_bo_release+0x2bf/0x310 [ttm]
[ 21.056219] Modules linked in: amdgpu(E) iommu_v2(E) gpu_sched(E)
drm_ttm_helper(E) ttm(E)
On Tue, Dec 08, 2020 at 09:39:18PM +0800, Lazar, Lijo wrote:
> [AMD Public Use]
>
> > You can create two new callbacks in ppt_funcs->inform_rlc(smu, on), and set
> > on as bool type
>
> We can't keep adding ASIC specific workarounds as ppt_funcs. We should make
> use of the existing ones or
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Rodrigo
Siqueira
Sent: Monday, December 7, 2020 5:55 PM
To: Wentland, Harry ; Kazlauskas, Nicholas
; Pillai, Aurabindo
Cc: amd-gfx@lists.freedesktop.org
[AMD Public Use]
> You can create two new callbacks in ppt_funcs->inform_rlc(smu, on), and set
> on as bool type
We can't keep adding ASIC specific workarounds as ppt_funcs. We should make use
of the existing ones or have something generic to handle these quirks. System
features control is
On Tue, Dec 08, 2020 at 07:19:42PM +0800, Hou, Xiaomeng (Matthew) wrote:
> RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFM
> is
> unaware of RLC being halted and will continue sending messages, which would
> eventually caused ACPI related hang. So send message to
On Mon, Dec 7, 2020 at 1:57 PM Arnd Bergmann wrote:
>
> On Mon, Dec 7, 2020 at 9:50 PM Christian König
> wrote:
> > Am 07.12.20 um 21:47 schrieb Alex Deucher:
> > > On Fri, Dec 4, 2020 at 3:13 AM Arnd Bergmann wrote:
> > >> From: Arnd Bergmann
> > >>
> > >> As the DRM_AMD_DC_DCN3_0 code was
The flag is set by the kernel when it detects that contiguous VRAM is
necessary by because of some hardware restriction. It should never be
set by userspace manually.
I've added giant page optimizations as a best effort handling which
atomatically kicks in when enough VRAM is available. If
Am 08.12.20 um 11:17 schrieb Nirmoy Das:
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
Hi Nikola,
On Tuesday, December 8th, 2020 at 2:36 AM, Cornij, Nikola
wrote:
> [AMD Public Use]
>
> Hi Simon,
>
> It looks to me I'm kinda late to the party to look at your questions under
> https://lists.freedesktop.org/archives/amd-gfx/2020-November/056032.html...
>
> Does the commit below
[AMD Official Use Only - Internal Distribution Only]
From: amd-gfx on behalf of Xiaomeng Hou
Sent: Tuesday, December 8, 2020 7:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Hou, Xiaomeng (Matthew) ; Quan, Evan
Subject:
[AMD Official Use Only - Internal Distribution Only]
From: amd-gfx on behalf of Xiaomeng Hou
Sent: Tuesday, December 8, 2020 7:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Hou, Xiaomeng (Matthew) ; Quan, Evan
Subject:
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFM is
unaware of RLC being halted and will continue sending messages, which would
eventually caused ACPI related hang. So send message to inform PMFM the rlc
status before start/stop rlc.
Signed-off-by: Xiaomeng Hou
Add this interface to notify PMFW the status (Normal/Off) of RLC engine.
Before notify RLC status normal, need check its current status first. Send the
message only when current status is still off.
Signed-off-by: Xiaomeng Hou
Change-Id: I2f1a7de23df7315a7b220ba6d0a4bcaa75c93fea
---
Add new PMFW message to notify RLC engine status.
Signed-off-by: Xiaomeng Hou
Change-Id: I7d714f8f245835cacb25e7cc4b248ddf183aebc1
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 2 +-
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
[AMD Public Use]
Rather than introduce this as a generic step in amdgpu_smu, confine the work
around only to sienna cichlid. For ex: this may be done just before enabling
dpm with system_features control override.
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Hi! I am not quite familiar with it, and I was wondering why this flag is
blocked. As the VM subsystem supports giant pages, it might be useful to add
this flag in amdgpu_gem_create_ioctl.
-原始邮件-
发件人: "Christian König"
发送时间: 2020-12-08 15:41:02 (星期二)
收件人: "Chen Lei" ,
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
On Fri, 20 Nov 2020 12:21:39 -0600, Gustavo A. R. Silva wrote:
> This series aims to fix almost all remaining fall-through warnings in
> order to enable -Wimplicit-fallthrough for Clang.
>
> In preparation to enable -Wimplicit-fallthrough for Clang, explicitly
> add multiple
Fulfill the 2nd usb2.0 port workaround for sienna cichlid.
Change-Id: I912660ee590e9ce352a20bbdf8903a61f88cd59e
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 25 +++
1 file changed, 25 insertions(+)
diff --git
2nd usb2.0 port workaround wrapper.
Change-Id: I615d8a568b1f6623a060ba5081c2d2a1235f32b9
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
3 files changed, 8
The workaround is needed by sienna cichlid.
Change-Id: Ib3d065b53dcb331d085e9bb9eeda99021a212206
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h | 2 ++
Used for determining 2ND_USB20PORT support from firmware_capability.
Change-Id: I3ff37f0a0dab311566bdd0aba189f2b7fa89ec2c
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/atomfirmware.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
That will help to determine whether 2ND_USB20_PORT workaround is
needed for Sienna Cichlid.
Change-Id: I3852e7c8cb11c12845ca81e7967e332c499cb470
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h| 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 ++
2 files
New SMC message was introduced for gpo control on sienna cichlid.
Change-Id: I6f09ae96e9dd7a290c9975564740f597a08ff2fa
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/inc/smu_types.h| 1 +
.../gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h| 4 +-
ping for a review of the nouveau patch
Am 01.12.20 um 11:35 schrieb Thomas Zimmermann:
Using struct drm_device.pdev is deprecated. Convert nouveau to struct
drm_device.dev. No functional changes.
Signed-off-by: Thomas Zimmermann
Cc: Ben Skeggs
---
drivers/gpu/drm/nouveau/dispnv04/arb.c
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