In dce110, the plane configuration is such that plane 0
or the primary plane should be rendered with only RGB data.
This patch adds the validation to ensure that no video data
is rendered on plane 0.
Signed-off-by: Shirish S
Reviewed-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/dce110/dce
Reviewed-by: Xiangliang Yu
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Emily Deng
> Sent: Wednesday, March 07, 2018 9:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily
> Subject: [PATCH v2] drm/amdgpu: Clean sdma wptr regi
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Rex Zhu
Sent: Tuesday, March 6, 2018 9:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Fix "Add auto power profilng switch based on
workloads"
1. fix typo "<" should be "<<
On 03/05/2018 10:56 PM, Alex Deucher wrote:
On Mon, Mar 5, 2018 at 12:44 PM, Michel Dänzer wrote:
From: Michel Dänzer
Since xf86CursorCloseScreen runs after RADEONCloseScreen_KMS,
PointPriv->spriteFuncs doesn't point to the same struct in the latter as
in RADEONCursorInit_KMS. So we were rest
Actually, for mailbox registers once the byte field is touched even not
changed, the mailbox behaves, so we need the byte width accessing to those sort
of regs.
Please correct the typo in commit title. With that change,
Reviewed-by: Pixel Ding
—
Sincerely Yours,
Pixel
On 06/03/2018, 7:05 P
1. fix typo "<" should be "<<"
2. fix code style
3. fix uninitialized point *workload
Signed-off-by: Rex Zhu
Change-Id: I35d03d19360c75e8eb2021bd3db63e52c93e1e61
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 14 +++---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 10 +
Hi Alex,
Have resent the V2 with R-B of Daniel.
Regards,
Shirish S
-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com]
Sent: Tuesday, March 6, 2018 11:01 PM
To: Vishwakarma, Pratik
Cc: Daniel Vetter ; Deucher, Alexander
; amd-gfx@lists.freedesktop.org; Maling list -
Add reverse iterator for_each_oldnew_plane_in_state_reverse to
compliment the for_each_oldnew_plane_in_state way or reading plane
states.
The plane states are required to be read in reverse order for
amd drivers, cause the z order convention followed in linux is
opposite to how the planes are supp
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.
v2:add comment above the code and correct coding style
Signed-off-by: E
Thanks for all of the help. I've purchased a Gigabyte GA-B250-Fintech
motherboard, and was able to get 9 cards running on the system. So the 8
card limit does appear to be a BIOS issue with the ASUS B250 Mining Expert
Here are some of my experiences with mining motherboards.
https://bitquant.wo
From: Vitaly Prosyak
Signed-off-by: Vitaly Prosyak
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b/
From: Bhawanpreet Lakha
HW Engineer's Notes:
During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
VGA_TEST_ENABLE, to leave it
From: Mikita Lipski
Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110
Adding constructors and destructors for each module.
Adding register list for DMCU in dce80 as some registers are missing
in dce80 from the basic list. DMCU is never used, so it would not have
any functional i
From: Dmytro Laktyushkin
We have unused variables being populated when notifying pplib.
This change amends that.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 +--
drivers/gpu/drm/amd/display/dc/
From: Yongqiang Sun
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 1
set dispclk to request value.
Decrease clock, currrent dpp
Note: sending with --no-validate since dce_calcs has ridiculously long lines.
* Fix corrupt screen issue when booting on Raven
* Enable backlight support for pre-DCE11 ASICs
* Update dce_calcs formula
* Bunch of Raven patches and fixes all around
Anthony Koo (2):
drm/amd/display: Implement
From: SivapiriyanKumarasamy
Add null check for stream update
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Krunoslav Kovac
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display
From: Anthony Koo
Stats will be used for debug purposes
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/basics/logger.c | 3 +-
drivers/gpu/drm/amd/display/include/logger_types.h | 1 +
.../drm/amd/display/modules/freesyn
From: "Jerry (Fangzhi) Zuo"
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 10 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
2 files changed, 6 insertions(+
From: "Leo (Sunpeng) Li"
While checking plane states for updates during atomic check, we create
dc_plane_states in preparation. These dc states should be freed if
something errors.
Although the input transfer function is also freed by
dc_plane_state_release(), we should free it (on error) under
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 19aec82a9429
From: "Leo (Sunpeng) Li"
Should return -ENOMEM when allocation fails.
Also, just return the error code instead of using a variable.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++--
1 file changed, 3 insertions(+),
From: Yongqiang Sun
300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 5 +
drivers/gpu/drm/amd/display/dc/dc
From: "Leo (Sunpeng) Li"
DRM's documentation for the color transform matrix does not specify
whether the values are in signed-magnitude, or 2's complement.
Therefore, it was assumed to use 2's complement.
However, existing usermode implementations use signed-magnitude.
Therefore, conform to exis
From: Eric Yang
Per discussion with VBIOS team, the orginal check is not correct in
all cases on latest VBIOS. Additional check is needed. This change should
maintain old behaviour on older VBIOS.
Signed-off-by: Eric Yang
Reviewed-by: Charlene Liu
Acked-by: Harry Wentland
---
drivers/gpu/drm
From: Yongqiang Sun
root cause:
DMCU try to perform a smoothness brightness change.Incorrect initial
brightness level causes the 1 sec dim.
Change:
Cache brightness level in stream, and clear it when edp backlight on.
If brightness level in stream is 0, set brightness with ramp value is 0.
DMCU w
From: Krunoslav Kovac
In MPO scenario when playing SDR clip in HDR desktop mode, Win is
boosting desktop and requests driver to boost MPO. But driver boosting
is currently done in regamma which is stream property and thus shared
between grph and video.
Redesigning the boosting in RV: use CM_HDR_
From: "Jerry (Fangzhi) Zuo"
Signed-off-by: Jerry (Fangzhi) Zuo
Reviewed-by: Hersen Wu
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 +++---
drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 5 +++--
drivers/gpu/drm/amd/display/dc/bios/command_table
From: Samson Tam
Signed-off-by: Samson Tam
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
.../drm/amd/display/modules/freesync/freesync.c| 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gp
From: Dmytro Laktyushkin
Bw spreadsheet was updated while dce_calcs was not
Change-Id: I66bb120aa855afbb90647047a39f32a2b10886eb
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 160 +++--
From: SivapiriyanKumarasamy
Avoid hanging DMCU by setting abm level only when OTG unblanked
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +
drivers/gpu/drm/amd/display/dc/dc.h
From: Anthony Koo
Time stamping will be part of surface, and will be updated when address is
flipped.
FreeSync parameters will be attached to stream, as it adjusts the timing
dynamically.
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/di
From: Bhawanpreet Lakha
Use DC_LOGGER macro for logs.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c| 14 +-
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 3 +--
drivers/gpu/drm/amd/display/dc/dml/
From: Shirish S
The order of planes is given by the order they are enumerated
by kms.
Planes with a higher ID appears above planes with a lower ID.
Currently the planes are enumerated in the wrong order,
putting the nv12 only plane after the two RGBA planes.
This patch corrects the plane enumer
From: Yongqiang Sun
This change make sure bandwidth is set properly.
For increase bandwidth, set bandwidth before backend
and front end programming.
For decrease bandwidth, set bandwidth after.
To avoid smu hang when reboot and dpms due to 0 disp clk,
keep min disp clock as 100Mhz.
Signed-off-by
From: Eric Yang
The work around for hw bug causes S3 resume failure. Don't execute
disable vga logic if not in vga mode.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h| 4 +++-
drivers/gpu/drm/amd/disp
From: Bhawanpreet Lakha
These MACROS are only being used by a few files but
gets pulled in by dc.h
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../amd/display/dc/dml/display_rq_dlg_helpers.c| 1 +
.../gpu/drm/amd/display/dc/dml/dml_common_defs.h
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 +--
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 ++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drive
From: SivapiriyanKumarasamy
Fix bug and make changes from review 132656
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++-
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5
On Tue, Mar 06, 2018 at 05:44:41PM -0500, Felix Kuehling wrote:
> Hi all,
>
> Christian raised two potential issues in a recent KFD upstreaming code
> review that are related to the KFD ioctl APIs:
>
> 1. behaviour of -ERESTARTSYS
> 2. transactional nature of KFD ioctl definitions, or lack ther
On 7 March 2018 at 08:44, Felix Kuehling wrote:
> Hi all,
>
> Christian raised two potential issues in a recent KFD upstreaming code
> review that are related to the KFD ioctl APIs:
>
> 1. behaviour of -ERESTARTSYS
> 2. transactional nature of KFD ioctl definitions, or lack thereof
>
> I appreci
Hi all,
Christian raised two potential issues in a recent KFD upstreaming code
review that are related to the KFD ioctl APIs:
1. behaviour of -ERESTARTSYS
2. transactional nature of KFD ioctl definitions, or lack thereof
I appreciate constructive feedback, but I also want to encourage an
open-
NAK.
For KFD we need the ability to create a BO from an SG list that doesn't
come from another BO. We use this for mapping pages from the doorbell
aperture into GPUVM for GPU self-dispatch.
If you remove this now, I'll need to add it back in some form in a month
or two when I get to that part of
Series are:
Reviewed-by: Leo Liu
On 03/06/2018 03:14 PM, James Zhu wrote:
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla: https://bugs.freedesktop.org/show_bug
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_
Max uvd handles should use adev->uvd.max_handles instead of
AMDGPU_MAX_UVD_HANDLES here.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/
Am 06.03.2018 um 19:15 schrieb Michel Dänzer:
On 2018-03-06 07:02 PM, Christian König wrote:
Am 06.03.2018 um 18:51 schrieb Michel Dänzer:
On 2018-03-06 06:44 PM, Christian König wrote:
Am 06.03.2018 um 18:22 schrieb Li, Samuel:
addition to that I agree with Michel that the module parameter i
On 2018-03-06 07:02 PM, Christian König wrote:
> Am 06.03.2018 um 18:51 schrieb Michel Dänzer:
>> On 2018-03-06 06:44 PM, Christian König wrote:
>>> Am 06.03.2018 um 18:22 schrieb Li, Samuel:
> addition to that I agree with Michel that the module parameter is
> overkill.
That I already
> Buffer placement is specified by the DDX/Mesa, when we override that in the
> kernel we just force unnecessary buffer moves.
Since scan out buffer is moved to GTT now, DDX/Mesa might need to make some
changes for this too.
Regards,
Samuel Li
> -Original Message-
> From: Christian Kön
Am 06.03.2018 um 18:51 schrieb Michel Dänzer:
On 2018-03-06 06:44 PM, Christian König wrote:
Am 06.03.2018 um 18:22 schrieb Li, Samuel:
addition to that I agree with Michel that the module parameter is
overkill.
That I already explained. Currently SG display feature needs to
provide options fo
On 2018-03-06 06:44 PM, Christian König wrote:
> Am 06.03.2018 um 18:22 schrieb Li, Samuel:
>>
>>> addition to that I agree with Michel that the module parameter is
>>> overkill.
>> That I already explained. Currently SG display feature needs to
>> provide options for all kinds of use cases. All am
Am 06.03.2018 um 18:22 schrieb Li, Samuel:
And exactly that's the problematical assumption.
Not assumption, I tested. You have any typical use case that it might become a
problem?
Not 100% sure, but I doubt you have tried that with different userspace
programs.
Especially animated boot scr
On 2018-03-06 18:28, Tom St Denis wrote:
I routinely rebase this patch on top of our amd-staging-drm-next tree at
fdo.
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next
Awesome.
So I used this tree, branch amd-staging-drm-next, and applied the patch
- and my screen works
I'm pleased to announce the 18.0.0 release of xf86-video-ati, the Xorg
driver for ATI/AMD Radeon GPUs supported by the radeon kernel driver.
This release supports xserver versions 1.13-1.19. It also works with
xserver 1.20 RC1, so unless something unexpected happens, it should work
with xserver 1.
Hi,
On 2018-03-06 12:18, Tom St Denis wrote:
I believe this is the same issue I had which is a VGA handoff problem.
Can you try this patch the display team sent me?
Harry: Will this patch be promoted in the next cycle?
What is the base for this patch? I cannot apply it on the top of any
4.
On Tue, Mar 6, 2018 at 5:52 AM, Vishwakarma, Pratik
wrote:
> Hi Daniel,
>
> I have checked make htmldocs on v2 of this patch. I have attached output
> drm-kms.html on that thread.
> No indentation issue is observed. Attached again for reference.
> Can you please provide RB on that?
How did you s
I routinely rebase this patch on top of our amd-staging-drm-next tree at
fdo.
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next
Tom
On 03/06/2018 12:27 PM, KARBOWSKI Piotr wrote:
Hi,
On 2018-03-06 12:18, Tom St Denis wrote:
I believe this is the same issue I had which
> And exactly that's the problematical assumption.
Not assumption, I tested. You have any typical use case that it might become a
problem?
> addition to that I agree with Michel that the module parameter is overkill.
That I already explained. Currently SG display feature needs to provide options
And exactly that's the problematical assumption.
This doesn't print only when the module is loaded, but rather when a
framebuffer object is created.
And depending on the use case that can even be many many times per second.
Please remove that printing, addition to that I agree with Michel tha
This information is kind of important, and it only prints once typically when
module is loaded.
Regards,
Samuel Li
> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, March 06, 2018 12:04 PM
> To: Li, Samuel
> Cc: Koenig, Christian ; amd-gfx list
On Tue, Mar 6, 2018 at 12:02 PM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> Since xf86CursorCloseScreen runs after AMDGPUCloseScreen_KMS,
> PointPriv->spriteFuncs doesn't point to the same struct in the latter as
> in AMDGPUCursorInit_KMS. So we were restoring info->Set/MoveCursor to
> the wr
On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li wrote:
>>> domain = amdgpu_display_framebuffer_domains(adev);
>>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Scatter gather display: enabled\n");
>>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Sc
From: Michel Dänzer
Since xf86CursorCloseScreen runs after AMDGPUCloseScreen_KMS,
PointPriv->spriteFuncs doesn't point to the same struct in the latter as
in AMDGPUCursorInit_KMS. So we were restoring info->Set/MoveCursor to
the wrong struct. Then in the next server generation,
info->Set/MoveCurs
On 2018-03-06 11:13 AM, Alex Deucher wrote:
> On Tue, Mar 6, 2018 at 6:18 AM, Tom St Denis wrote:
>> I believe this is the same issue I had which is a VGA handoff problem.
>>
>> Can you try this patch the display team sent me?
>>
>> Harry: Will this patch be promoted in the next cycle?
>
> I thi
>> domain = amdgpu_display_framebuffer_domains(adev);
>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>> +DRM_INFO("Scatter gather display: enabled\n");
>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>> +DRM_INFO("Scatter gather display: auto\n");
>> +}
>
> Dito and
On Tue, Mar 6, 2018 at 5:10 AM, Rex Zhu wrote:
> Powerplay is for the hw ip smu, for RV, smu10 is used,
> so use smu10 as the prefix of the files name.
>
> Change-Id: Icf9c8a9d4b5deccd4fbfb9ecfab443db79934c77
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile |
On Tue, Mar 6, 2018 at 6:18 AM, Tom St Denis wrote:
> I believe this is the same issue I had which is a VGA handoff problem.
>
> Can you try this patch the display team sent me?
>
> Harry: Will this patch be promoted in the next cycle?
I think it will eventually. IIRC, there were some regressio
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Rex Zhu
Sent: Tuesday, March 6, 2018 1:47:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Add #ifdef checks for CONFIG_ACPI
Fix compiling error when CONFIG_ACPI not enabled.
Below mail was rejected, maybe due to attachment. Sending again without
attachment.
Regards
Pratik
-Original Message-
From: Vishwakarma, Pratik
Sent: Tuesday, March 6, 2018 4:22 PM
To: 'Daniel Vetter' ; Alex Deucher
Cc: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org; Maling list -
Better to set this with all other fields as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_tt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 65976238d24b..7e672be987b5 100644
--- a/drive
Allows us to gut a BO of it's backing store when the driver says that it
isn't needed any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 15 ---
drivers/gpu/drm/ttm/ttm_bo_util.c | 24
include/drm/ttm/ttm_bo_driver.h | 9 +
Instead of moving this to the SYSTEM domain just drop the backing store
and let the resulting allocation be freed.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drive
Drop the "kernel" and sg parameter and give the BO type to create
explicit to amdgpu_bo_create instead of figuring it out from the
parameters.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 5 +--
drivers
Just set the GTT domain as mandatory, so that the BO is validated into
it on first use. This allows us to setup the sg table later on.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
Instead of calculating the size in bytes just to recalculate the number
of pages from it pass the BO directly to the function.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
drivers/gpu/drm/ast/ast_ttm.c | 6 +++---
drivers/gpu/drm/bo
Acked-by: Rex Zhu for the series.
Best Regards
Rex
From: amd-gfx on behalf of Alex Deucher
Sent: Tuesday, March 6, 2018 2:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; sta...@vger.kernel.org
Subject: [PATCH 2/2] drm/amdgpu: fix KV harvesting
Reviewed-by: Rex Zhu
Best Regards
Rex
From: Christian König
Sent: Tuesday, March 6, 2018 9:58 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amd/pp: fix "Delete the wrapper layer of
smu_allocate/free_memory"
For amdgpu_bo_create_kernel to
For amdgpu_bo_create_kernel to work the handle must be NULL initialized,
otherwise we only try to pin and map the BO.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 2 +-
2 files changed, 2 in
I believe this is the same issue I had which is a VGA handoff problem.
Can you try this patch the display team sent me?
Harry: Will this patch be promoted in the next cycle?
Tom
On 03/05/2018 11:40 AM, KARBOWSKI Piotr wrote:
Hi list,
I'd like to report a very odd screen artifacts while runn
this patch actually refactor mailbox implmentations, and
all below changes are needed together to fix all those mailbox
handshake issues exposured by heavey TDR test.
1)refactor all mailbox functions based on byte accessing for mb_control
reason is to avoid touching non-related bits when writing t
mailbox register can be accessed with a byte boundry according
to BIF team, so this patch prepares register byte access
and will be used by following patches
Change-Id: I1e84f1c6e8e75dc42eb5be09c492fa5e7eb7502a
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 ++
d
Am 06.03.2018 um 10:59 schrieb Emily Deng:
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.
Signed-off-by: Emily Deng
On Wed, Feb 28, 2018 at 09:26:26AM -0500, Alex Deucher wrote:
> + dri-devel
>
>
> On Wed, Feb 28, 2018 at 4:33 AM, S, Shirish wrote:
> > From: Shirish S
> >
> > Add reverse iterator "for_each_oldnew_plane_in_state_reverse" to
> > complement "for_each_oldnew_plane_in_state" way of reading plane
The sdma v4 doesn't have the issue about the conflict between doorbell and sdma
wptr polling.
Best Wishes,
Emily Deng
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of zhoucm1
> Sent: Tuesday, March 06, 2018 6:03 PM
> To: Deng, Emily ; a
looks we didn't hit similar issues during vega10 testing ...
From: amd-gfx on behalf of zhoucm1
Sent: Tuesday, March 6, 2018 6:02:35 PM
To: Deng, Emily; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr
How about other sdma version? like sdma v4 etc.
Regards,
David Zhou
On 2018年03月06日 17:59, Emily Deng wrote:
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up
Acked-by: Thomas Hellstrom
On 03/06/2018 10:13 AM, Christian König wrote:
Hi Michel & Thomas,
any more comments on this? Or can I commit it?
Thanks,
Christian.
Am 27.02.2018 um 12:49 schrieb Christian König:
Let's stop mangling everything in a single header and create one header
per object
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
On 2018-03-06 10:13 AM, Christian König wrote:
> Hi Michel & Thomas,
>
> any more comments on this? Or can I commit it?
Acked-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
Better to add comment above the code.
Reviewed-by: Xiangliang Yu
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Emily Deng
> Sent: Tuesday, March 06, 2018 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily
> Subject: [PATCH
On Tue, Mar 06, 2018 at 10:30:56AM +0100, Christian König wrote:
> Am 06.03.2018 um 10:15 schrieb Daniel Vetter:
> > On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:
> > > Am 28.02.2018 um 10:48 schrieb Lucas Stach:
> > > > Hi Christian,
> > > >
> > > > Am Dienstag, den 27.02.2018,
On Tue, Mar 06, 2018 at 10:25:03AM +0100, Christian König wrote:
> Am 06.03.2018 um 10:21 schrieb Daniel Vetter:
> > On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:
> > > Most of the time we only need the dma addresses.
> > >
> > > Signed-off-by: Christian König
> > > ---
> > >
Am 06.03.2018 um 10:15 schrieb Daniel Vetter:
On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:
Am 28.02.2018 um 10:48 schrieb Lucas Stach:
Hi Christian,
Am Dienstag, den 27.02.2018, 12:49 +0100 schrieb Christian König:
Unpin the GEM object only after freeing the sg table.
Wha
Am 06.03.2018 um 10:21 schrieb Daniel Vetter:
On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:
Most of the time we only need the dma addresses.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_prime.c | 20 ++--
1 file changed, 10 insertions(+), 10 dele
On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:
> Most of the time we only need the dma addresses.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/drm_prime.c | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/
On Tue, Feb 27, 2018 at 01:07:06PM +0100, Christian König wrote:
> Hi guys,
>
> at least on amdgpu and radeon the page array allocated by ttm_dma_tt_init is
> completely unused in the case of DMA-buf sharing. So I'm trying to get rid
> of that by only allocating the DMA address array.
>
> Now the
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:
> Am 28.02.2018 um 10:48 schrieb Lucas Stach:
> > Hi Christian,
> >
> > Am Dienstag, den 27.02.2018, 12:49 +0100 schrieb Christian König:
> > > Unpin the GEM object only after freeing the sg table.
> > What is the race that is being
Hi Michel & Thomas,
any more comments on this? Or can I commit it?
Thanks,
Christian.
Am 27.02.2018 um 12:49 schrieb Christian König:
Let's stop mangling everything in a single header and create one header
per object instead.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_tt.c
Hi all,
Please ignore this patch, the root cause about the sdma hang introduced by
sdma wptr polling
has been found, will submit another patch.
Best Wishes,
Emily Deng
> -Original Message-
> From: Emily Deng [mailto:emily.d...@amd.com]
> Sent: Tuesday, March 06, 2018 10:15 AM
> To:
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