[PATCH] drm/amd/display: validate plane format on primary plane

[Shirish S]

In dce110, the plane configuration is such that plane 0
or the primary plane should be rendered with only RGB data.

This patch adds the validation to ensure that no video data
is rendered on plane 0.

Signed-off-by: Shirish S 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 830cbbc..b1f14be 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -879,6 +879,13 @@ static bool dce110_validate_surface_sets(
plane->src_rect.height > 1080))
return false;
 
+   /* we don't have the logic to support underlay
+* only yet so block the use case where we get
+* NV12 plane as top layer
+*/
+   if (j == 0)
+   return false;
+
/* irrespective of plane format,
 * stream should be RGB encoded
 */
-- 
2.7.4

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RE: [PATCH v2] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Yu, Xiangliang]

Reviewed-by: Xiangliang Yu 


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Emily Deng
> Sent: Wednesday, March 07, 2018 9:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily 
> Subject: [PATCH v2] drm/amdgpu: Clean sdma wptr register when only
> enable wptr polling
> 
> The sdma wptr polling memory is not fast enough, then the sdma wptr
> register will be random, and not equal to sdma rptr, which will cause sdma
> engine hang when load driver, so clean up the sdma wptr directly to fix this
> issue.
> 
> v2:add comment above the code and correct coding style
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 521978c..89ec17c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -719,14 +719,17 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
>   WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
>  upper_32_bits(wptr_gpu_addr));
>   wptr_poll_cntl =
> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> - if (ring->use_pollmem)
> + if (ring->use_pollmem) {
> + /*wptr polling is not enogh fast, directly clean the
> wptr register */
> + WREG32(mmSDMA0_GFX_RB_WPTR +
> sdma_offsets[i], 0);
>   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> 
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>  ENABLE, 1);
> - else
> + } else {
>   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> 
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>  ENABLE, 0);
> + }
>   WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL +
> sdma_offsets[i], wptr_poll_cntl);
> 
>   /* enable DMA RB */
> --
> 2.7.4
> 
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Re: [PATCH] drm/amd/pp: Fix "Add auto power profilng switch based on workloads"

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Tuesday, March 6, 2018 9:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Fix "Add auto power profilng switch based on 
workloads"

1. fix typo "<" should be "<<"
2. fix code style
3. fix uninitialized point *workload

Signed-off-by: Rex Zhu 

Change-Id: I35d03d19360c75e8eb2021bd3db63e52c93e1e61
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 14 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 10 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  2 +-
 5 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 84e65df..b989bf3 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1081,7 +1081,7 @@ static int pp_dpm_switch_power_profile(void *handle,
 {
 struct pp_hwmgr *hwmgr;
 struct pp_instance *pp_handle = (struct pp_instance *)handle;
-   long *workload;
+   long workload;
 uint32_t index;

 if (pp_check(pp_handle))
@@ -1100,19 +1100,19 @@ static int pp_dpm_switch_power_profile(void *handle,
 mutex_lock(_handle->pp_lock);

 if (!en) {
-   hwmgr->workload_mask &= ~(1 < hwmgr->workload_prority[type]);
+   hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
 index = fls(hwmgr->workload_mask);
-   index = index > 0 && index <= Workload_Policy_Max? index - 1 : 
0;
-   *workload = hwmgr->workload_setting[index];
+   index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 
0;
+   workload = hwmgr->workload_setting[index];
 } else {
-   hwmgr->workload_mask |= (1 < hwmgr->workload_prority[type]);
+   hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
 index = fls(hwmgr->workload_mask);
 index = index <= Workload_Policy_Max ? index - 1 : 0;
-   *workload = hwmgr->workload_setting[index];
+   workload = hwmgr->workload_setting[index];
 }

 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-   hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
+   hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, , 0);
 mutex_unlock(_handle->pp_lock);

 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index aa83114..af1b22d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -133,11 +133,11 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr 
*hwmgr)
 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;

-   hwmgr->workload_setting[0]= PP_SMC_POWER_PROFILE_POWERSAVING;
-   hwmgr->workload_setting[1]= PP_SMC_POWER_PROFILE_VIDEO;
-   hwmgr->workload_setting[2]= PP_SMC_POWER_PROFILE_FULLSCREEN3D;
-   hwmgr->workload_setting[3]= PP_SMC_POWER_PROFILE_VR;
-   hwmgr->workload_setting[4]= PP_SMC_POWER_PROFILE_COMPUTE;
+   hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
+   hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
+   hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
+   hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
 }

 int hwmgr_early_init(struct pp_instance *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 51439a1..d0ef8f9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -251,7 +251,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, 
bool skip,

 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
 index = fls(hwmgr->workload_mask);
-   index = index > 0 && index <= Workload_Policy_Max? index - 1 : 
0;
+   index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 
0;
 workload = hwmgr->workload_setting[index];

 if (hwmgr->power_profile_mode != workload && 
hwmgr->hwmgr_func->set_power_profile_mode)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4f26014..d4d1d2e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1510,7 

Re: [PATCH xf86-video-ati] Only change Set/MoveCursor hooks from what we expect

[Mario Kleiner]

On 03/05/2018 10:56 PM, Alex Deucher wrote:

On Mon, Mar 5, 2018 at 12:44 PM, Michel Dänzer  wrote:

From: Michel Dänzer 

Since xf86CursorCloseScreen runs after RADEONCloseScreen_KMS,
PointPriv->spriteFuncs doesn't point to the same struct in the latter as
in RADEONCursorInit_KMS. So we were restoring info->Set/MoveCursor to
the wrong struct. Then in the next server generation,
info->Set/MoveCursor would end up pointing to
drmmode_sprite_set/move_cursor, resulting in an infinite loop if one of
them was called.

To avoid this, only change the Set/MoveCursor hooks if their values
match our expectations, otherwise leave them as is. This is kind of a
hack, but the alternative would be invasive and thus risky changes to
the way we're wrapping CloseScreen, and it's not even clear that can
work without changing xserver code.

Fixes: 1fe8ca75974c ("Keep track of how many SW cursors are visible on
   each screen")
Signed-off-by: Michel Dänzer 


Acked-by: Alex Deucher 



Nope, not quite, unfortunately. Tested against x-server master, mesa 
master, ati-ddx master, with sddm login manager. With a freshly started 
server, now on a dual-x-screen setup, instead of an infinite loop, i get 
a server crash as soon as i move the mouse cursor from X-Screen 0 to 
X-Screen 1:


(gdb) c
Continuing.

Thread 1 "X" received signal SIGSEGV, Segmentation fault.
0x in ?? ()
(gdb) bt
#0  0x in ?? ()
#1  0x004bcad2 in xf86CursorSetCursor (pDev=0x11912e0, 
pScreen=0xf9a510, pCurs=0x1177610, x=32, y=358) at xf86CursorRD.c:345
#2  0x0057a758 in miPointerUpdateSprite (pDev=0x11912e0) at 
mipointer.c:453
#3  0x0057aada in miPointerDisplayCursor (pDev=0x11912e0, 
pScreen=0xf9a510, pCursor=0x1177610) at mipointer.c:206
#4  0x004cb1b6 in CursorDisplayCursor (pDev=, 
pScreen=0xf9a510, pCursor=0x1177610) at cursor.c:168
#5  0x0050f78b in AnimCurDisplayCursor (pDev=0x11912e0, 
pScreen=0xf9a510, pCursor=0x1177610) at animcur.c:196
#6  0x004473b8 in ChangeToCursor (pDev=0x11912e0, 
cursor=0x1177610) at events.c:936
#7  0x0044b20a in CheckMotion (ev=ev@entry=0x7ffdad7a7060, 
pDev=pDev@entry=0x11912e0) at events.c:3081
#8  0x0051ee6b in ProcessDeviceEvent 
(ev=ev@entry=0x7ffdad7a7060, device=device@entry=0x11912e0) at 
exevents.c:1716
#9  0x0051f5fb in ProcessOtherEvent (ev=0x7ffdad7a7060, 
device=0x11912e0) at exevents.c:1873
#10 0x005403a2 in ProcessPointerEvent (ev=0x7ffdad7a7060, 
mouse=0x11912e0) at xkbAccessX.c:756
#11 0x00571712 in mieqProcessDeviceEvent (dev=0x1368e10, 
event=0x7ffdad7a7cc0, screen=0xf9a510) at mieq.c:496

#12 0x0057184a in mieqProcessInputEvents () at mieq.c:551
#13 0x0047a8a9 in ProcessInputEvents () at xf86Events.c:151
#14 0x0043e2a7 in Dispatch () at dispatch.c:417
#15 0x00442568 in dix_main (argc=11, argv=0x7ffdad7a8ad8, 
envp=) at main.c:276
#16 0x7f20fdf60830 in __libc_start_main (main=0x42c520 , 
argc=11, argv=0x7ffdad7a8ad8, init=, fini=out>, rtld_fini=, stack_end=0x7ffdad7a8ac8) at 
../csu/libc-start.c:291


-mario



---
  src/radeon_kms.c | 16 ++--
  1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 85390e306..790d4be16 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -2017,10 +2017,12 @@ static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
 return FALSE;
 }

-   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
-   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
-   PointPriv->spriteFuncs->SetCursor = drmmode_sprite_set_cursor;
-   PointPriv->spriteFuncs->MoveCursor = drmmode_sprite_move_cursor;
+   if (PointPriv->spriteFuncs->SetCursor != drmmode_sprite_set_cursor) {
+   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
+   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
+   PointPriv->spriteFuncs->SetCursor = drmmode_sprite_set_cursor;
+   PointPriv->spriteFuncs->MoveCursor = drmmode_sprite_move_cursor;
+   }
  }

  if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE))
@@ -2184,8 +2186,10 @@ static Bool RADEONCloseScreen_KMS(ScreenPtr pScreen)
 miPointerScreenPtr PointPriv =
 dixLookupPrivate(>devPrivates, miPointerScreenKey);

-   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
-   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
+   if (PointPriv->spriteFuncs->SetCursor == drmmode_sprite_set_cursor) {
+   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
+   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
+   }
  }

  pScreen->BlockHandler = info->BlockHandler;
--
2.16.2

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Re: [PATCH 1/2] drm/amdgpu: imlement mmio byte access helpers

[Ding, Pixel]

Actually, for mailbox registers once the byte field is touched even not 
changed, the mailbox behaves, so we need the byte width accessing to those sort 
of regs.

Please correct the typo in commit title. With that change,
Reviewed-by: Pixel Ding 


— 
Sincerely Yours,
Pixel


On 06/03/2018, 7:05 PM, "amd-gfx on behalf of Monk Liu" 
 wrote:

mailbox register can be accessed with a byte boundry according
to BIF team, so this patch prepares register byte access
and will be used by following patches

Change-Id: I1e84f1c6e8e75dc42eb5be09c492fa5e7eb7502a
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ++
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 292c7e7..72385bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1635,6 +1635,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, 
uint32_t reg,
uint32_t acc_flags);
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags);
+void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t 
value);
+uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
+
 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
 
@@ -1658,6 +1661,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 
AMDGPU_REGS_NO_KIQ)
 
+#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
+#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
+
 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", 
amdgpu_mm_rreg(adev, (reg), 0))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65584f6..c8e1940 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -121,6 +121,32 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, 
uint32_t reg,
return ret;
 }
 
+/*
+ * MMIO register read with bytes helper functions
+ * @offset:bytes offset from MMIO start
+ *
+*/
+
+uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
+   if (offset < adev->rmmio_size)
+   return (readb(adev->rmmio + offset));
+   BUG();
+}
+
+/*
+ * MMIO register write with bytes helper functions
+ * @offset:bytes offset from MMIO start
+ * @value: the value want to be written to the register
+ *
+*/
+void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t 
value) {
+   if (offset < adev->rmmio_size)
+   writeb(value, adev->rmmio + offset);
+   else
+   BUG();
+}
+
+
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags)
 {
-- 
2.7.4

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[PATCH] drm/amd/pp: Fix "Add auto power profilng switch based on workloads"

[Rex Zhu]

1. fix typo "<" should be "<<"
2. fix code style
3. fix uninitialized point *workload

Signed-off-by: Rex Zhu 

Change-Id: I35d03d19360c75e8eb2021bd3db63e52c93e1e61
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 14 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 10 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  2 +-
 5 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 84e65df..b989bf3 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1081,7 +1081,7 @@ static int pp_dpm_switch_power_profile(void *handle,
 {
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
-   long *workload;
+   long workload;
uint32_t index;
 
if (pp_check(pp_handle))
@@ -1100,19 +1100,19 @@ static int pp_dpm_switch_power_profile(void *handle,
mutex_lock(_handle->pp_lock);
 
if (!en) {
-   hwmgr->workload_mask &= ~(1 < hwmgr->workload_prority[type]);
+   hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
index = fls(hwmgr->workload_mask);
-   index = index > 0 && index <= Workload_Policy_Max? index - 1 : 
0;
-   *workload = hwmgr->workload_setting[index];
+   index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 
0;
+   workload = hwmgr->workload_setting[index];
} else {
-   hwmgr->workload_mask |= (1 < hwmgr->workload_prority[type]);
+   hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
index = fls(hwmgr->workload_mask);
index = index <= Workload_Policy_Max ? index - 1 : 0;
-   *workload = hwmgr->workload_setting[index];
+   workload = hwmgr->workload_setting[index];
}
 
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-   hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
+   hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, , 0);
mutex_unlock(_handle->pp_lock);
 
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index aa83114..af1b22d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -133,11 +133,11 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr 
*hwmgr)
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
 
-   hwmgr->workload_setting[0]= PP_SMC_POWER_PROFILE_POWERSAVING;
-   hwmgr->workload_setting[1]= PP_SMC_POWER_PROFILE_VIDEO;
-   hwmgr->workload_setting[2]= PP_SMC_POWER_PROFILE_FULLSCREEN3D;
-   hwmgr->workload_setting[3]= PP_SMC_POWER_PROFILE_VR;
-   hwmgr->workload_setting[4]= PP_SMC_POWER_PROFILE_COMPUTE;
+   hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
+   hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
+   hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
+   hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
 }
 
 int hwmgr_early_init(struct pp_instance *handle)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 51439a1..d0ef8f9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -251,7 +251,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, 
bool skip,
 
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
index = fls(hwmgr->workload_mask);
-   index = index > 0 && index <= Workload_Policy_Max? index - 1 : 
0;
+   index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 
0;
workload = hwmgr->workload_setting[index];
 
if (hwmgr->power_profile_mode != workload && 
hwmgr->hwmgr_func->set_power_profile_mode)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4f26014..d4d1d2e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1510,7 +1510,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->current_profile_setting.mclk_up_hyst = 0;
data->current_profile_setting.mclk_down_hyst = 100;
data->current_profile_setting.mclk_activity = 
SMU7_MCLK_TARGETACTIVITY_DFLT;
-   hwmgr->workload_mask = 1 < 
hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];

RE: [PATCH] drm/atomic: Add new reverse iterator over all plane state

[S, Shirish]

Hi Alex,

Have resent the V2 with R-B of Daniel.

Regards,
Shirish S


-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com] 
Sent: Tuesday, March 6, 2018 11:01 PM
To: Vishwakarma, Pratik 
Cc: Daniel Vetter ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org; Maling list - DRI 
developers ; S, Shirish 
Subject: Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state

On Tue, Mar 6, 2018 at 5:52 AM, Vishwakarma, Pratik 
 wrote:
> Hi Daniel,
>
> I have checked make htmldocs on v2 of this patch. I have attached output 
> drm-kms.html on that thread.
> No indentation issue is observed. Attached again for reference.
> Can you please provide RB on that?

How did you send the patch?  I can't get V2 to apply.  The patch is mangled.  
Please use git-send-email if you didn't before.

Alex

>
> Regards
> Pratik
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf 
> Of Daniel Vetter
> Sent: Tuesday, March 6, 2018 3:36 PM
> To: Alex Deucher 
> Cc: Deucher, Alexander ; 
> amd-gfx@lists.freedesktop.org; Maling list - DRI developers 
> ; S, Shirish 
> Subject: Re: [PATCH] drm/atomic: Add new reverse iterator over all 
> plane state
>
> On Wed, Feb 28, 2018 at 09:26:26AM -0500, Alex Deucher wrote:
>> + dri-devel
>>
>>
>> On Wed, Feb 28, 2018 at 4:33 AM, S, Shirish  wrote:
>> > From: Shirish S 
>> >
>> > Add reverse iterator "for_each_oldnew_plane_in_state_reverse" to 
>> > complement "for_each_oldnew_plane_in_state" way of reading plane 
>> > states.
>> >
>> > The plane states are required to be read in reverse order for 
>> > amdgpu, as the z order convention followed in linux is opposite to 
>> > how the planes are supposed to be presented to DC engine, which is 
>> > in common to both windows and linux.
>> >
>> > Signed-off-by: Shirish S 
>> > Signed-off-by: Pratik Vishwakarma 
>
> Makes sense.
>> > ---
>> >  include/drm/drm_atomic.h | 22 ++
>> >  1 file changed, 22 insertions(+)
>> >
>> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h 
>> > index cf13842..b947930 100644
>> > --- a/include/drm/drm_atomic.h
>> > +++ b/include/drm/drm_atomic.h
>> > @@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct 
>> > drm_printer *p);
>> >   (new_plane_state) = 
>> > (__state)->planes[__i].new_state, 1))
>> >
>> >  /**
>> > + * for_each_oldnew_plane_in_state_reverse - iterate over all 
>> > + planes in an atomic
>> > + * update in reverse order
>
> Are you sure this renders correctly in kernel-doc? Iirc you have to indent 
> the continuation line.
>
> Assuming this is fixed:
>
> Reviewed-by: Daniel Vetter 
>
>> > + * @__state:  drm_atomic_state pointer
>> > + * @plane:  drm_plane iteration cursor
>> > + * @old_plane_state:  drm_plane_state iteration cursor for 
>> > +the old state
>> > + * @new_plane_state:  drm_plane_state iteration cursor for 
>> > +the new state
>> > + * @__i: int iteration cursor, for macro-internal use
>> > + *
>> > + * This iterates over all planes in an atomic update in reverse 
>> > +order,
>> > + * tracking both old and  new state. This is useful in places 
>> > +where the
>> > + * state delta needs to be considered, for example in atomic check 
>> > functions.
>> > + */
>> > +#define for_each_oldnew_plane_in_state_reverse(__state, plane, 
>> > old_plane_state, new_plane_state, __i) \
>> > +   (for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1);   
>> >  \
>> > +(__i) >= 0;\
>> > +(__i)--)   \
>> > +   for_each_if ((__state)->planes[__i].ptr &&  \
>> > +((plane) = (__state)->planes[__i].ptr, \
>> > + (old_plane_state) = 
>> > (__state)->planes[__i].old_state,\
>> > + (new_plane_state) = 
>> > +(__state)->planes[__i].new_state, 1)))
>> > +
>> > +/**
>> >   * for_each_old_plane_in_state - iterate over all planes in an atomic 
>> > update
>> >   * @__state:  drm_atomic_state pointer
>> >   * @plane:  drm_plane iteration cursor
>> > --
>> > 2.7.4
>> >
>> > ___
>> > amd-gfx mailing list
>> > amd-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>> ___
>> dri-devel mailing list
>> dri-de...@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, 

[PATCH] drm/atomic: Add new reverse iterator over all plane state (V2)

[Shirish S]

Add reverse iterator for_each_oldnew_plane_in_state_reverse to
compliment the for_each_oldnew_plane_in_state way or reading plane
states.

The plane states are required to be read in reverse order for
amd drivers, cause the z order convention followed in linux is
opposite to how the planes are supposed to be presented to DC
engine, which is in common to both windows and linux.

V2: fix compile time errors due to -Werror flag.

Signed-off-by: Shirish S 
Signed-off-by: Pratik Vishwakarma 
Reviewed-by: Daniel Vetter 
---
 include/drm/drm_atomic.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index cf13842..3fe8dde 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct 
drm_printer *p);
  (new_plane_state) = 
(__state)->planes[__i].new_state, 1))
 
 /**
+ * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an 
atomic
+ * update in reverse order
+ * @__state:  drm_atomic_state pointer
+ * @plane:  drm_plane iteration cursor
+ * @old_plane_state:  drm_plane_state iteration cursor for the old state
+ * @new_plane_state:  drm_plane_state iteration cursor for the new state
+ * @__i: int iteration cursor, for macro-internal use
+ *
+ * This iterates over all planes in an atomic update in reverse order,
+ * tracking both old and  new state. This is useful in places where the
+ * state delta needs to be considered, for example in atomic check functions.
+ */
+#define for_each_oldnew_plane_in_state_reverse(__state, plane, 
old_plane_state, new_plane_state, __i) \
+   for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \
+(__i) >= 0;\
+(__i)--)   \
+   for_each_if ((__state)->planes[__i].ptr &&  \
+((plane) = (__state)->planes[__i].ptr, \
+ (old_plane_state) = 
(__state)->planes[__i].old_state,\
+ (new_plane_state) = 
(__state)->planes[__i].new_state, 1))
+
+/**
  * for_each_old_plane_in_state - iterate over all planes in an atomic update
  * @__state:  drm_atomic_state pointer
  * @plane:  drm_plane iteration cursor
-- 
2.7.4

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[PATCH v2] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Emily Deng]

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

v2:add comment above the code and correct coding style
Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..89ec17c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,14 +719,17 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
*adev)
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
   upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
sdma_offsets[i]);
-   if (ring->use_pollmem)
+   if (ring->use_pollmem) {
+   /*wptr polling is not enogh fast, directly clean the 
wptr register */
+   WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 1);
-   else
+   } else {
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 0);
+   }
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], 
wptr_poll_cntl);
 
/* enable DMA RB */
-- 
2.7.4

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Re: amdgpu with 8+ cards for GPU mining?

[Joseph Wang]

Thanks for all of the help.  I've purchased a Gigabyte GA-B250-Fintech
motherboard, and was able to get 9 cards running on the system.  So the 8
card limit does appear to be a BIOS issue with the ASUS B250 Mining Expert

Here are some of my experiences with mining motherboards.

https://bitquant.wordpress.com/2018/03/07/mining-motherboards-notes/
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[PATCH 20/28] drm/amd/display: Fix handling of linear transfer function

[Harry Wentland]

From: Vitaly Prosyak 

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 57d5c2575de1..e7e374f56864 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1267,7 +1267,8 @@ bool  mod_color_calculate_curve(enum 
dc_transfer_func_predefined trans,
bool ret = false;
struct pwl_float_data_ex *rgb_regamma = NULL;
 
-   if (trans == TRANSFER_FUNCTION_UNITY) {
+   if (trans == TRANSFER_FUNCTION_UNITY ||
+   trans == TRANSFER_FUNCTION_LINEAR) {
points->end_exponent = 0;
points->x_point_at_y1_red = 1;
points->x_point_at_y1_green = 1;
@@ -1337,7 +1338,8 @@ bool  mod_color_calculate_degamma_curve(enum 
dc_transfer_func_predefined trans,
bool ret = false;
struct pwl_float_data_ex *rgb_degamma = NULL;
 
-   if (trans == TRANSFER_FUNCTION_UNITY) {
+   if (trans == TRANSFER_FUNCTION_UNITY ||
+   trans == TRANSFER_FUNCTION_LINEAR) {
 
for (i = 0; i <= MAX_HW_POINTS ; i++) {
points->red[i]= coordinates_x[i].x;
-- 
2.14.1

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[PATCH 09/28] drm/amd/display: Fix takover from VGA mode

[Harry Wentland]

From: Bhawanpreet Lakha 

HW Engineer's Notes:
 During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
 hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 VGA_TEST_ENABLE, to leave it in the same state as before.

Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h| 10 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 3336428b1fed..c7ea2c6037b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -190,6 +190,7 @@
SR(D2VGA_CONTROL), \
SR(D3VGA_CONTROL), \
SR(D4VGA_CONTROL), \
+   SR(VGA_TEST_CONTROL), \
SR(DC_IP_REQUEST_CNTL), \
BL_REG_LIST()
 
@@ -261,6 +262,7 @@ struct dce_hwseq_registers {
uint32_t D2VGA_CONTROL;
uint32_t D3VGA_CONTROL;
uint32_t D4VGA_CONTROL;
+   uint32_t VGA_TEST_CONTROL;
/* MMHUB registers. read only. temporary hack */
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -404,7 +406,9 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
 
 #define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \
@@ -483,7 +487,9 @@ struct dce_hwseq_registers {
type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
type DENTIST_DPPCLK_WDIVIDER; \
-   type DENTIST_DISPCLK_WDIVIDER;
+   type DENTIST_DISPCLK_WDIVIDER; \
+   type VGA_TEST_ENABLE; \
+   type VGA_TEST_RENDER_START;
 
 struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c1a07ecd2927..f1990c3c893d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -224,6 +224,16 @@ static void disable_vga(
REG_WRITE(D2VGA_CONTROL, 0);
REG_WRITE(D3VGA_CONTROL, 0);
REG_WRITE(D4VGA_CONTROL, 0);
+
+   /* HW Engineer's Notes:
+*  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
+*  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets 
updated correctly.
+*
+*  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
+*  VGA_TEST_ENABLE, to leave it in the same state as before.
+*/
+   REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
+   REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 }
 
 static void dpp_pg_control(
-- 
2.14.1

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[PATCH 15/28] drm/amd/display: Enable backlight support for pre-DCE11 ASICs

[Harry Wentland]

From: Mikita Lipski 

Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110
Adding constructors and destructors for each module.
Adding register list for DMCU in dce80 as some registers are missing
in dce80 from the basic list. DMCU is never used, so it would not have
any functional impact.

Signed-off-by: Mikita Lipski 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  | 35 +
 .../drm/amd/display/dc/dce100/dce100_resource.c| 50 +
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 87 ++
 3 files changed, 172 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 1d4546f23135..c24c0e5ea44e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -46,6 +46,23 @@
SR(SMU_INTERRUPT_CONTROL), \
SR(DC_DMCU_SCRATCH)
 
+#define DMCU_DCE80_REG_LIST() \
+   SR(DMCU_CTRL), \
+   SR(DMCU_STATUS), \
+   SR(DMCU_RAM_ACCESS_CTRL), \
+   SR(DMCU_IRAM_WR_CTRL), \
+   SR(DMCU_IRAM_WR_DATA), \
+   SR(MASTER_COMM_DATA_REG1), \
+   SR(MASTER_COMM_DATA_REG2), \
+   SR(MASTER_COMM_DATA_REG3), \
+   SR(MASTER_COMM_CMD_REG), \
+   SR(MASTER_COMM_CNTL_REG), \
+   SR(DMCU_IRAM_RD_CTRL), \
+   SR(DMCU_IRAM_RD_DATA), \
+   SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
+   SR(SMU_INTERRUPT_CONTROL), \
+   SR(DC_DMCU_SCRATCH)
+
 #define DMCU_DCE110_COMMON_REG_LIST() \
DMCU_COMMON_REG_LIST_DCE_BASE(), \
SR(DCI_MEM_PWR_STATUS)
@@ -83,6 +100,24 @@
STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 
+#define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
+   DMCU_SF(DMCU_CTRL, \
+   DMCU_ENABLE, mask_sh), \
+   DMCU_SF(DMCU_STATUS, \
+   UC_IN_STOP_MODE, mask_sh), \
+   DMCU_SF(DMCU_STATUS, \
+   UC_IN_RESET, mask_sh), \
+   DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+   IRAM_HOST_ACCESS_EN, mask_sh), \
+   DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+   IRAM_WR_ADDR_AUTO_INC, mask_sh), \
+   DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+   IRAM_RD_ADDR_AUTO_INC, mask_sh), \
+   DMCU_SF(MASTER_COMM_CMD_REG, \
+   MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
+   DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
+   DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
+
 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
DMCU_SF(DCI_MEM_PWR_STATUS, \
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3bdbed80f7f8..3092f76bdb75 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -51,6 +51,9 @@
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
 
+#include "dce/dce_dmcu.h"
+#include "dce/dce_abm.h"
+
 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
 #include "gmc/gmc_8_2_d.h"
 #include "gmc/gmc_8_2_sh_mask.h"
@@ -320,7 +323,29 @@ static const struct dce110_clk_src_mask cs_mask = {
CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
+static const struct dce_dmcu_registers dmcu_regs = {
+   DMCU_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+   DMCU_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+   DMCU_MASK_SH_LIST_DCE110(_MASK)
+};
+
+static const struct dce_abm_registers abm_regs = {
+   ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+   ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
 
+static const struct dce_abm_mask abm_mask = {
+   ABM_MASK_SH_LIST_DCE110(_MASK)
+};
 
 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
 
@@ -622,6 +647,12 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(>base.display_clock);
 
+   if (pool->base.abm != NULL)
+   dce_abm_destroy(>base.abm);
+
+   if (pool->base.dmcu != NULL)
+   dce_dmcu_destroy(>base.dmcu);
+
if (pool->base.irqs != NULL)
dal_irq_service_destroy(>base.irqs);
 }
@@ -829,6 +860,25 @@ static bool construct(
goto res_create_fail;
}
 
+   pool->base.dmcu = dce_dmcu_create(ctx,
+   _regs,
+   _shift,
+   _mask);
+   if (pool->base.dmcu == NULL) {
+   dm_error("DC: failed to create dmcu!\n");
+   BREAK_TO_DEBUGGER();
+  

[PATCH 28/28] drm/amd/display: clean up dcn pplib notification call

[Harry Wentland]

From: Dmytro Laktyushkin 

We have unused variables being populated when notifying pplib.
This change amends that.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  4 +--
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 18 ---
 drivers/gpu/drm/amd/display/dc/dc.h|  4 +--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 35 +-
 4 files changed, 15 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 8bab3fec4d8d..4bb43a371292 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -983,8 +983,6 @@ bool dcn_validate_bandwidth(
context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 
100 / 32);
}
 
-   context->bw.dcn.calc_clk.dram_ccm_us = 
(int)(v->dram_clock_change_margin);
-   context->bw.dcn.calc_clk.min_active_dram_ccm_us = 
(int)(v->min_active_dram_clock_change_margin);
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = 
(int)(v->dcf_clk_deep_sleep * 1000);
context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
 
@@ -998,7 +996,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
 
-   context->bw.dcn.calc_clk.max_dppclk_khz = 
context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
+   context->bw.dcn.calc_clk.dppclk_khz = 
context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
 
switch (v->voltage_level) {
case 0:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index f82275eb81bc..5a552cb3f8a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -358,25 +358,19 @@ void context_clock_trace(
struct dal_logger *logger =  core_dc->ctx->logger;
 
CLOCK_TRACE("Current: dispclk_khz:%d  max_dppclk_khz:%d  
dcfclk_khz:%d\n"
-   "dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n"
-   "dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
+   "dcfclk_deep_sleep_khz:%d  fclk_khz:%d  
socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
-   context->bw.dcn.calc_clk.max_dppclk_khz,
+   context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
-   context->bw.dcn.calc_clk.socclk_khz,
-   context->bw.dcn.calc_clk.dram_ccm_us,
-   context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+   context->bw.dcn.calc_clk.socclk_khz);
CLOCK_TRACE("Calculated: dispclk_khz:%d  max_dppclk_khz:%d  
dcfclk_khz:%d\n"
-   "dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n"
-   "dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
+   "dcfclk_deep_sleep_khz:%d  fclk_khz:%d  
socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
-   context->bw.dcn.calc_clk.max_dppclk_khz,
+   context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
-   context->bw.dcn.calc_clk.fclk_khz,
-   context->bw.dcn.calc_clk.dram_ccm_us,
-   context->bw.dcn.calc_clk.min_active_dram_ccm_us);
+   context->bw.dcn.calc_clk.fclk_khz);
 #endif
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1a7e7a645a6e..fa4b3c8b3bb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -186,14 +186,12 @@ enum wm_report_mode {
 
 struct dc_clocks {
int dispclk_khz;
-   int max_dppclk_khz;
int max_supported_dppclk_khz;
+   int dppclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
int fclk_khz;
-   int dram_ccm_us;
-   int min_active_dram_ccm_us;
 };
 
 struct dc_debug {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f9b910b7f6d..4365906b14ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ 

[PATCH 23/28] drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk.

[Harry Wentland]

From: Yongqiang Sun 

Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 1
set dispclk to request value.
Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is
higher than maximum dpp clk as per dpm table.
set dispclk to the value of maximum supported dpp clk
set div to 0
set dispclk to request value.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  19 +++
 drivers/gpu/drm/amd/display/dc/dc.h|   1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c|   2 -
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 142 +
 4 files changed, 139 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 8020bc7742c1..8bab3fec4d8d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1000,6 +1000,25 @@ bool dcn_validate_bandwidth(
 
context->bw.dcn.calc_clk.max_dppclk_khz = 
context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
 
+   switch (v->voltage_level) {
+   case 0:
+   context->bw.dcn.calc_clk.max_supported_dppclk_khz =
+   (int)(dc->dcn_soc->max_dppclk_vmin0p65 
* 1000);
+   break;
+   case 1:
+   context->bw.dcn.calc_clk.max_supported_dppclk_khz =
+   (int)(dc->dcn_soc->max_dppclk_vmid0p72 
* 1000);
+   break;
+   case 2:
+   context->bw.dcn.calc_clk.max_supported_dppclk_khz =
+   (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 
1000);
+   break;
+   default:
+   context->bw.dcn.calc_clk.max_supported_dppclk_khz =
+   (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 
1000);
+   break;
+   }
+
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1626dc1dc143..1a7e7a645a6e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -187,6 +187,7 @@ enum wm_report_mode {
 struct dc_clocks {
int dispclk_khz;
int max_dppclk_khz;
+   int max_supported_dppclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 78e6beb6cf26..76fc903515ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -623,7 +623,6 @@ static bool dce_apply_clock_voltage_request(
}
}
if (send_request) {
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
struct dc *core_dc = clk->ctx->dc;
/*use dcfclk request voltage*/
@@ -631,7 +630,6 @@ static bool dce_apply_clock_voltage_request(
clock_voltage_req.clocks_in_khz =
dcn_find_dcfclk_suits_all(core_dc, 
>cur_clocks_value);
}
-#endif
dm_pp_apply_clock_for_voltage_request(
clk->ctx, _voltage_req);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 50088b674795..9f9b910b7f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1699,16 +1699,22 @@ static void update_dchubp_dpp(
union plane_size size = plane_state->plane_size;
 
/* depends on DML calculation, DPP clock value may change dynamically */
+   /* If request max dpp clk is lower than current dispclk, no need to
+* divided by 2
+*/
if (plane_state->update_flags.bits.full_update) {
+   bool should_divided_by_2 = 
context->bw.dcn.calc_clk.max_dppclk_khz <=
+   context->bw.dcn.cur_clk.dispclk_khz / 2;
+
dpp->funcs->dpp_dppclk_control(
dpp,
-   context->bw.dcn.calc_clk.max_dppclk_khz <
-

[PATCH 17/28] drm/amd/display: Implement stats logging

[Harry Wentland]

From: Anthony Koo 

Stats will be used for debug purposes

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/basics/logger.c |   3 +-
 drivers/gpu/drm/amd/display/include/logger_types.h |   1 +
 .../drm/amd/display/modules/freesync/freesync.c| 129 ++--
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |   9 +
 .../gpu/drm/amd/display/modules/inc/mod_stats.h|  65 
 drivers/gpu/drm/amd/display/modules/stats/stats.c  | 334 +
 6 files changed, 510 insertions(+), 31 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
 create mode 100644 drivers/gpu/drm/amd/display/modules/stats/stats.c

diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 180a9d69d351..31bee054f43a 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -60,7 +60,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_LINK_LOSS,   "LinkLoss"},
{LOG_EVENT_UNDERFLOW,   "Underflow"},
{LOG_IF_TRACE,  "InterfaceTrace"},
-   {LOG_DTN,   "DTN"}
+   {LOG_DTN,   "DTN"},
+   {LOG_PROFILING, "Profiling"}
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h 
b/drivers/gpu/drm/amd/display/include/logger_types.h
index b727f5eeb3a9..427796bdc14a 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -98,6 +98,7 @@ enum dc_log_type {
LOG_EVENT_UNDERFLOW,
LOG_IF_TRACE,
LOG_PERF_TRACE,
+   LOG_PROFILING,
 
LOG_SECTION_TOTAL_COUNT
 };
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index b4723af368a5..e849b704f2f6 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -33,7 +33,7 @@
 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
 /* Number of elements in the render times cache array */
-#define RENDER_TIMES_MAX_COUNT 20
+#define RENDER_TIMES_MAX_COUNT 10
 /* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
 #define BTR_EXIT_MARGIN 2000
 /* Number of consecutive frames to check before entering/exiting fixed 
refresh*/
@@ -52,7 +52,7 @@ struct gradual_static_ramp {
unsigned int ramp_current_frame_duration_in_ns;
 };
 
-struct time_cache {
+struct freesync_time {
/* video (48Hz feature) related */
unsigned int update_duration_in_ns;
 
@@ -64,6 +64,9 @@ struct time_cache {
 
unsigned int render_times_index;
unsigned int render_times[RENDER_TIMES_MAX_COUNT];
+
+   unsigned int min_window;
+   unsigned int max_window;
 };
 
 struct below_the_range {
@@ -98,11 +101,14 @@ struct freesync_state {
bool static_screen;
bool video;
 
+   unsigned int vmin;
+   unsigned int vmax;
+
+   struct freesync_time time;
+
unsigned int nominal_refresh_rate_in_micro_hz;
bool windowed_fullscreen;
 
-   struct time_cache time;
-
struct gradual_static_ramp static_ramp;
struct below_the_range btr;
struct fixed_refresh fixed_refresh;
@@ -124,9 +130,9 @@ struct freesync_registry_options {
 struct core_freesync {
struct mod_freesync public;
struct dc *dc;
+   struct freesync_registry_options opts;
struct freesync_entity *map;
int num_entities;
-   struct freesync_registry_options opts;
 };
 
 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
@@ -146,7 +152,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
goto fail_alloc_context;
 
core_freesync->map = kzalloc(sizeof(struct freesync_entity) * 
MOD_FREESYNC_MAX_CONCURRENT_STREAMS,
-GFP_KERNEL);
+   GFP_KERNEL);
 
if (core_freesync->map == NULL)
goto fail_alloc_map;
@@ -330,6 +336,25 @@ bool mod_freesync_remove_stream(struct mod_freesync 
*mod_freesync,
return true;
 }
 
+static void adjust_vmin_vmax(struct core_freesync *core_freesync,
+   struct dc_stream_state **streams,
+   int num_streams,
+   int map_index,
+   unsigned int v_total_min,
+   unsigned int v_total_max)
+{
+   if (num_streams == 0 || streams == NULL || num_streams > 1)
+   return;
+
+   core_freesync->map[map_index].state.vmin = 

[PATCH 00/28] DC Patches Mar 6, 2018

[Harry Wentland]

Note: sending with --no-validate since dce_calcs has ridiculously long lines.

 * Fix corrupt screen issue when booting on Raven
 * Enable backlight support for pre-DCE11 ASICs
 * Update dce_calcs formula
 * Bunch of Raven patches and fixes all around

Anthony Koo (2):
  drm/amd/display: Implement stats logging
  drm/amd/display: Add variable refresh rate parameters to DC structures

Bhawanpreet Lakha (3):
  drm/amd/display: Fix takover from VGA mode
  drm/amd/display: Move DTRACE and dml_print defines
  drm/amd/display: Use MACROS instead of dm_logger

Dmytro Laktyushkin (2):
  drm/amd/display: update dce_calcs to latest version
  drm/amd/display: clean up dcn pplib notification call

Eric Yang (2):
  drm/amd/display: fix check condition for edp power control
  drm/amd/display: early return if not in vga mode in disable_vga

Harry Wentland (1):
  drm/amd/display: Check for HW blocks in HWSS, rather than DC core for
cursor

Jerry (Fangzhi) Zuo (2):
  drm/amd/display: Allow passing of syspll id to get_smu_clock_info
  drm/amd/display: Use actual TG instance instead of pipe instance

Krunoslav Kovac (1):
  drm/amd/display: use HW hdr mult for brightness boost

Leo (Sunpeng) Li (3):
  drm/amd/display: Fix memleaks when atomic check fails.
  drm/amd/display: Use correct error codes
  drm/amd/display: Convert CTM to 2's complement

Mikita Lipski (1):
  drm/amd/display: Enable backlight support for pre-DCE11 ASICs

Samson Tam (1):
  drm/amd/display: add support for regkey "LCDFreeSyncDefault"

Shirish S (1):
  drm/amd/display: Correct the plane enumeration order

SivapiriyanKumarasamy (3):
  drm/amd/display: Vari-bright looks disabled near end of MM14
  drm/amd/display: Varibright fix bug and review comments
  drm/amd/display: Varibright add null check

Tony Cheng (1):
  drm/amd/display: dal 3.1.38

Vitaly Prosyak (1):
  drm/amd/display: Fix handling of linear transfer function

Yongqiang Sun (4):
  drm/amd/display: Remove 300Mhz minimum disp clk limit.
  drm/amd/display: Modified set bandwidth sequence.
  drm/amd/display: Set disp clk in a safe way to avoid over high dpp
clk.
  drm/amd/display: Fixed dim around 1sec when resume from S3

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 112 ---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |  23 ++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c|  15 +-
 drivers/gpu/drm/amd/display/dc/basics/logger.c |   3 +-
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |   6 +-
 .../gpu/drm/amd/display/dc/bios/command_table2.c   |   5 +-
 .../gpu/drm/amd/display/dc/bios/command_table2.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   | 160 ++
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  23 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  20 +-
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c |  32 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|   3 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   9 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  12 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h |   7 +
 drivers/gpu/drm/amd/display/dc/dc_types.h  |  18 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c|   2 -
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h  |  35 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c |  10 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |  18 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  |   3 +-
 .../drm/amd/display/dc/dce100/dce100_resource.c|  50 +++
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  28 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  87 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |   1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |  16 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c|   9 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 257 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   7 +-
 .../amd/display/dc/dml/display_rq_dlg_helpers.c|   1 +
 .../gpu/drm/amd/display/dc/dml/dml_common_defs.h   |   2 -
 .../gpu/drm/amd/display/dc/dml/dml_inline_defs.h   |   1 +
 drivers/gpu/drm/amd/display/dc/dml/dml_logger.h|  38 +++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   2 +
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h |   6 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h|   3 +
 drivers/gpu/drm/amd/display/include/logger_types.h |   1 +
 .../drm/amd/display/modules/color/color_gamma.c|   6 +-
 .../drm/amd/display/modules/freesync/freesync.c| 155 --
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |   9 +
 .../gpu/drm/amd/display/modules/inc/mod_stats.h|  65 
 drivers/gpu/drm/amd/display/modules/stats/stats.c  | 334 +
 44 files changed, 1357 insertions(+), 249 deletions(-)
 create mode 100644 

[PATCH 05/28] drm/amd/display: Varibright add null check

[Harry Wentland]

From: SivapiriyanKumarasamy 

Add null check for stream update

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Krunoslav Kovac 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 40a65cb9ee23..e72fdb5697fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1363,7 +1363,7 @@ static void commit_planes_for_stream(struct dc *dc,
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, 
stream_status->plane_count, context);
 
-   if (stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
+   if (stream_update && stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
if (pipe_ctx->stream_res.tg->funcs->is_blanked) 
{
// if otg funcs defined check if 
blanked before programming
if 
(!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
-- 
2.14.1

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[PATCH 26/28] drm/amd/display: Use actual TG instance instead of pipe instance

[Harry Wentland]

From: "Jerry (Fangzhi) Zuo" 

Signed-off-by: Jerry (Fangzhi) Zuo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c  | 10 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |  2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 4b8e7ce2de8c..487724345d9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -56,7 +56,7 @@ void dce_pipe_control_lock(struct dc *dc,
if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
return;
 
-   val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
+   val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
BLND_DCP_GRPH_V_UPDATE_LOCK, _grph,
BLND_SCL_V_UPDATE_LOCK, ,
BLND_BLND_V_UPDATE_LOCK, ,
@@ -67,19 +67,19 @@ void dce_pipe_control_lock(struct dc *dc,
blnd = lock_val;
update_lock_mode = lock_val;
 
-   REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
+   REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
BLND_SCL_V_UPDATE_LOCK, scl);
 
if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
-   REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
+   REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
BLND_BLND_V_UPDATE_LOCK, blnd,
BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
 
if (hws->wa.blnd_crtc_trigger) {
if (!lock) {
-   uint32_t value = 
REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
-   REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], 
value);
+   uint32_t value = 
REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
+   
REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
}
}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 206569e13a2c..3e9cd1b7f32c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1132,7 +1132,7 @@ static void build_audio_output(
 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
struct tg_color *color)
 {
-   uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 
4;
+   uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - 
pipe_ctx->stream_res.tg->inst) / 4;
 
switch (pipe_ctx->plane_res.scl_data.format) {
case PIXEL_FORMAT_ARGB:
-- 
2.14.1

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[PATCH 01/28] drm/amd/display: Fix memleaks when atomic check fails.

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

While checking plane states for updates during atomic check, we create
dc_plane_states in preparation. These dc states should be freed if
something errors.

Although the input transfer function is also freed by
dc_plane_state_release(), we should free it (on error) under the same
scope as where it is created.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +--
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d774ef3c821a..5f14590e5d4d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1987,6 +1987,10 @@ static int fill_plane_attributes(struct amdgpu_device 
*adev,
 * every time.
 */
ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
+   if (ret) {
+   dc_transfer_func_release(dc_plane_state->in_transfer_func);
+   dc_plane_state->in_transfer_func = NULL;
+   }
 
return ret;
 }
@@ -4776,6 +4780,7 @@ static int dm_update_planes_state(struct dc *dc,
*lock_and_validation_needed = true;
 
} else { /* Add new planes */
+   struct dc_plane_state *dc_new_plane_state;
 
if (drm_atomic_plane_disabling(plane->state, 
new_plane_state))
continue;
@@ -4794,34 +4799,45 @@ static int dm_update_planes_state(struct dc *dc,
 
WARN_ON(dm_new_plane_state->dc_state);
 
-   dm_new_plane_state->dc_state = 
dc_create_plane_state(dc);
-
-   DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc 
%d\n",
-   plane->base.id, 
new_plane_crtc->base.id);
-
-   if (!dm_new_plane_state->dc_state) {
+   dc_new_plane_state = dc_create_plane_state(dc);
+   if (!dc_new_plane_state) {
ret = -EINVAL;
return ret;
}
 
+   DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc 
%d\n",
+   plane->base.id, 
new_plane_crtc->base.id);
+
ret = fill_plane_attributes(
new_plane_crtc->dev->dev_private,
-   dm_new_plane_state->dc_state,
+   dc_new_plane_state,
new_plane_state,
new_crtc_state);
-   if (ret)
+   if (ret) {
+   dc_plane_state_release(dc_new_plane_state);
return ret;
+   }
 
+   /*
+* Any atomic check errors that occur after this will
+* not need a release. The plane state will be attached
+* to the stream, and therefore part of the atomic
+* state. It'll be released when the atomic state is
+* cleaned.
+*/
if (!dc_add_plane_to_context(
dc,
dm_new_crtc_state->stream,
-   dm_new_plane_state->dc_state,
+   dc_new_plane_state,
dm_state->context)) {
 
+   dc_plane_state_release(dc_new_plane_state);
ret = -EINVAL;
return ret;
}
 
+   dm_new_plane_state->dc_state = dc_new_plane_state;
+
/* Tell DC to do a full surface update every time there
 * is a plane change. Inefficient, but works for now.
 */
-- 
2.14.1

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[PATCH 19/28] drm/amd/display: dal 3.1.38

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 19aec82a9429..1626dc1dc143 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.37"
+#define DC_VER "3.1.38"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 02/28] drm/amd/display: Use correct error codes

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

Should return -ENOMEM when allocation fails.
Also, just return the error code instead of using a variable.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5f14590e5d4d..8ea484b0fe81 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4800,10 +4800,8 @@ static int dm_update_planes_state(struct dc *dc,
WARN_ON(dm_new_plane_state->dc_state);
 
dc_new_plane_state = dc_create_plane_state(dc);
-   if (!dc_new_plane_state) {
-   ret = -EINVAL;
-   return ret;
-   }
+   if (!dc_new_plane_state)
+   return -ENOMEM;
 
DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc 
%d\n",
plane->base.id, 
new_plane_crtc->base.id);
@@ -4832,8 +4830,7 @@ static int dm_update_planes_state(struct dc *dc,
dm_state->context)) {
 
dc_plane_state_release(dc_new_plane_state);
-   ret = -EINVAL;
-   return ret;
+   return -EINVAL;
}
 
dm_new_plane_state->dc_state = dc_new_plane_state;
-- 
2.14.1

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[PATCH 07/28] drm/amd/display: Remove 300Mhz minimum disp clk limit.

[Harry Wentland]

From: Yongqiang Sun 

300Mhz disp clk limit was a workaround that was fixed in SMU and is no
longer needed.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 5 +
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 2 --
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e72fdb5697fc..fa402291a921 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -803,6 +803,8 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.enable_accelerated_mode(dc, context);
 
+   dc->hwss.set_bandwidth(dc, context, false);
+
/* re-program planes for existing stream, in case we need to
 * free up plane resource for later use
 */
@@ -869,6 +871,9 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
context->streams[i]->timing.pix_clk_khz);
}
 
+   /* pplib is notified if disp_num changed */
+   dc->hwss.set_bandwidth(dc, context, true);
+
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
dc_release_state(dc->current_state);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c2041a63cccd..ca0484894084 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2106,9 +2106,6 @@ enum dc_status dce110_apply_ctx_to_hw(
return status;
}
 
-   /* pplib is notified if disp_num changed */
-   dc->hwss.set_bandwidth(dc, context, true);
-
/* to save power */
apply_min_clocks(dc, context, _state, false);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 617aa8ca0156..e7406c74dd48 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -440,8 +440,6 @@ static const struct dc_debug debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
 
-   .min_disp_clk_khz = 30,
-
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,
-- 
2.14.1

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[PATCH 06/28] drm/amd/display: Convert CTM to 2's complement

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

DRM's documentation for the color transform matrix does not specify
whether the values are in signed-magnitude, or 2's complement.
Therefore, it was assumed to use 2's complement.

However, existing usermode implementations use signed-magnitude.
Therefore, conform to existing standards, and convert to 2's complement
internally.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index e845c511656e..f6cb502c303f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -193,6 +193,7 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
struct drm_property_blob *blob = crtc->base.ctm;
struct dc_stream_state *stream = crtc->stream;
struct drm_color_ctm *ctm;
+   int64_t val;
int i;
 
if (!blob) {
@@ -206,7 +207,9 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
 * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating
 * with homogeneous coordinates, augment the matrix with 0's.
 *
-* The format provided is S31.32, which is the same as our fixed31_32.
+* The format provided is S31.32, using signed-magnitude representation.
+* Our fixed31_32 is also S31.32, but is using 2's complement. We have
+* to convert from signed-magnitude to 2's complement.
 */
for (i = 0; i < 12; i++) {
/* Skip 4th element */
@@ -214,8 +217,14 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
stream->gamut_remap_matrix.matrix[i] = 
dal_fixed31_32_zero;
continue;
}
-   /* csc[i] = ctm[i - floor(i/4)] */
-   stream->gamut_remap_matrix.matrix[i].value = ctm->matrix[i - 
(i/4)];
+
+   /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */
+   val = ctm->matrix[i - (i/4)];
+   /* If negative, convert to 2's complement. */
+   if (val & (1ULL << 63))
+   val = -(val & ~(1ULL << 63));
+
+   stream->gamut_remap_matrix.matrix[i].value = val;
}
 }
 
-- 
2.14.1

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[PATCH 10/28] drm/amd/display: fix check condition for edp power control

[Harry Wentland]

From: Eric Yang 

Per discussion with VBIOS team, the orginal check is not correct in
all cases on latest VBIOS. Additional check is needed. This change should
maintain old behaviour on older VBIOS.

Signed-off-by: Eric Yang 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 14 ++
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c| 10 +++---
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index c7ea2c6037b2..19ca7f000506 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -329,6 +329,8 @@ struct dce_hwseq_registers {
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 
@@ -405,10 +407,12 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
-   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
+   HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
+   HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
+   HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 
 #define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \
@@ -440,7 +444,9 @@ struct dce_hwseq_registers {
type ENABLE_L1_TLB;\
type SYSTEM_ACCESS_MODE;\
type LVTMA_BLON;\
-   type LVTMA_PWRSEQ_TARGET_STATE_R;
+   type LVTMA_PWRSEQ_TARGET_STATE_R;\
+   type LVTMA_DIGON;\
+   type LVTMA_DIGON_OVRD;
 
 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
type HUBP_VTG_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ca0484894084..9de3d793f12e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -737,10 +737,14 @@ static bool is_panel_backlight_on(struct dce_hwseq *hws)
 
 static bool is_panel_powered_on(struct dce_hwseq *hws)
 {
-   uint32_t value;
+   uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
+
+
+   REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, 
_seq_state);
+
+   REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, _on, LVTMA_DIGON_OVRD, 
_on_ovrd);
 
-   REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, );
-   return value == 1;
+   return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
 }
 
 static enum bp_result link_transmitter_control(
-- 
2.14.1

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[PATCH 27/28] drm/amd/display: Fixed dim around 1sec when resume from S3

[Harry Wentland]

From: Yongqiang Sun 

root cause:
DMCU try to perform a smoothness brightness change.Incorrect initial
brightness level causes the 1 sec dim.
Change:
Cache brightness level in stream, and clear it when edp backlight on.
If brightness level in stream is 0, set brightness with ramp value is 0.
DMCU will set the brightness without smoothness transition.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c   | 5 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h  | 1 +
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +++-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f8c09273e0f1..e6d5dcb35e96 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1960,6 +1960,11 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link, uint32_t level,
(abm->funcs->set_backlight_level == NULL))
return false;
 
+   if (stream->bl_pwm_level == 0)
+   frame_ramp = 0;
+
+   ((struct dc_stream_state *)stream)->bl_pwm_level = level;
+
use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
 
DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", level, level);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 13e5ac9cfe13..d017df56b2ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -78,6 +78,7 @@ struct dc_stream_state {
 
/* DMCU info */
unsigned int abm_level;
+   unsigned int bl_pwm_level;
 
/* from core_stream struct */
struct dc_context *ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3e9cd1b7f32c..30dd62f0f5fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1006,8 +1006,10 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
if (dc_is_dp_signal(pipe_ctx->stream->signal))

pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc,
 );
 
-   if (link->local_sink && link->local_sink->sink_signal == 
SIGNAL_TYPE_EDP)
+   if (link->local_sink && link->local_sink->sink_signal == 
SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, true);
+   stream->bl_pwm_level = 0;
+   }
 }
 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
 {
-- 
2.14.1

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[PATCH 14/28] drm/amd/display: use HW hdr mult for brightness boost

[Harry Wentland]

From: Krunoslav Kovac 

In MPO scenario when playing SDR clip in HDR desktop mode, Win is
boosting desktop and requests driver to boost MPO. But driver boosting
is currently done in regamma which is stream property and thus shared
between grph and video.

Redesigning the boosting in RV: use CM_HDR_MULT register which was added
for this scenario. It also has the benefit that it can be done in HIRQL.

Signed-off-by: Krunoslav Kovac 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c |  3 ---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c |  1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 16 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c  |  9 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 20 
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h  |  3 +++
 6 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 16a1931bc4cd..63a3d468939a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1110,9 +1110,6 @@ static enum surface_update_type 
get_plane_info_update_type(const struct dc_surfa
if (u->plane_info->input_tf != u->surface->input_tf)
update_flags->bits.input_tf_change = 1;
 
-   if (u->plane_info->sdr_white_level != u->surface->sdr_white_level)
-   update_flags->bits.output_tf_change = 1;
-
if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
update_flags->bits.horizontal_mirror_change = 1;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index f0b798930b51..e305c28c98de 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -464,6 +464,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.set_cursor_attributes = dpp1_set_cursor_attributes,
.set_cursor_position = dpp1_set_cursor_position,
.dpp_dppclk_control = dpp1_dppclk_control,
+   .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
 };
 
 static struct dpp_caps dcn10_dpp_cap = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 07003d9c6bba..17b062a8f88a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -113,7 +113,8 @@
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
-   SRI(DPP_CONTROL, DPP_TOP, id)
+   SRI(DPP_CONTROL, DPP_TOP, id), \
+   SRI(CM_HDR_MULT_COEF, CM, id)
 
 
 
@@ -308,7 +309,8 @@
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
-   TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh)
+   TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
+   TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
 
 #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
TF_REG_LIST_SH_MASK_DCN(mask_sh),\
@@ -1012,7 +1014,8 @@
type CUR0_COLOR0; \
type CUR0_COLOR1; \
type DPPCLK_RATE_CONTROL; \
-   type DPP_CLOCK_ENABLE;
+   type DPP_CLOCK_ENABLE; \
+   type CM_HDR_MULT_COEF;
 
 struct dcn_dpp_shift {
TF_REG_FIELD_LIST(uint8_t)
@@ -1258,7 +1261,8 @@ struct dcn_dpp_mask {
uint32_t CURSOR0_CONTROL; \
uint32_t CURSOR0_COLOR0; \
uint32_t CURSOR0_COLOR1; \
-   uint32_t DPP_CONTROL;
+   uint32_t DPP_CONTROL; \
+   uint32_t CM_HDR_MULT_COEF;
 
 struct dcn_dpp_registers {
DPP_COMMON_REG_VARIABLE_LIST
@@ -1414,6 +1418,10 @@ void dpp1_dppclk_control(
bool dppclk_div,
bool enable);
 
+void dpp1_set_hdr_multiplier(
+   struct dpp *dpp_base,
+   uint32_t multiplier);
+
 void dpp1_construct(struct dcn10_dpp *dpp1,
struct dc_context *ctx,
uint32_t inst,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index bd3fcdfb79c5..fb32975e4b67 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -804,3 +804,12 @@ void dpp1_program_input_lut(
REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, _num);
 }
+
+void dpp1_set_hdr_multiplier(
+   struct dpp *dpp_base,
+   uint32_t multiplier)
+{
+   struct dcn10_dpp *dpp = 

[PATCH 08/28] drm/amd/display: Allow passing of syspll id to get_smu_clock_info

[Harry Wentland]

From: "Jerry (Fangzhi) Zuo" 

Signed-off-by: Jerry (Fangzhi) Zuo 
Reviewed-by: Hersen Wu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c   | 6 +++---
 drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 5 +++--
 drivers/gpu/drm/amd/display/dc/bios/command_table2.h | 2 +-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 1689c670ca6f..e7680c41f117 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -44,7 +44,7 @@
 
 #include "bios_parser_common.h"
 #define LAST_RECORD_TYPE 0xff
-
+#define SMU9_SYSPLL0_ID  0
 
 struct i2c_id_config_access {
uint8_t bfI2C_LineMux:4;
@@ -1220,7 +1220,7 @@ static unsigned int bios_parser_get_smu_clock_info(
if (!bp->cmd_tbl.get_smu_clock_info)
return BP_RESULT_FAILURE;
 
-   return bp->cmd_tbl.get_smu_clock_info(bp);
+   return bp->cmd_tbl.get_smu_clock_info(bp, 0);
 }
 
 static enum bp_result bios_parser_program_crtc_timing(
@@ -1376,7 +1376,7 @@ static enum bp_result get_firmware_info_v3_1(
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
/* VBIOS gives in 10KHz */
info->smu_gpu_pll_output_freq =
-   bp->cmd_tbl.get_smu_clock_info(bp) * 10;
+   bp->cmd_tbl.get_smu_clock_info(bp, 
SMU9_SYSPLL0_ID) * 10;
}
 
return BP_RESULT_OK;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index e362658aa3ce..3f63f712c8a4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -796,7 +796,7 @@ static enum bp_result set_dce_clock_v2_1(
  **
  */
 
-static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp);
+static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t 
id);
 
 static void init_get_smu_clock_info(struct bios_parser *bp)
 {
@@ -805,12 +805,13 @@ static void init_get_smu_clock_info(struct bios_parser 
*bp)
 
 }
 
-static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp)
+static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
 {
struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
 
smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
+   smu_input.syspll_id = id;
 
/* Get Specific Clock */
if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h 
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
index 59061b806df5..ec1c0c9f3f1d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
@@ -96,7 +96,7 @@ struct cmd_tbl {
struct bios_parser *bp,
struct bp_set_dce_clock_parameters *bp_params);
unsigned int (*get_smu_clock_info)(
-   struct bios_parser *bp);
+   struct bios_parser *bp, uint8_t id);
 
 };
 
-- 
2.14.1

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[PATCH 22/28] drm/amd/display: add support for regkey "LCDFreeSyncDefault"

[Harry Wentland]

From: Samson Tam 

Signed-off-by: Samson Tam 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/modules/freesync/freesync.c| 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index e849b704f2f6..27d4003aa2c7 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -46,6 +46,8 @@
 
 #define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal"
 
+#define FREESYNC_DEFAULT_REGKEY "LCDFreeSyncDefault"
+
 struct gradual_static_ramp {
bool ramp_is_active;
bool ramp_direction_is_up;
@@ -125,6 +127,8 @@ struct freesync_entity {
 struct freesync_registry_options {
bool drr_external_supported;
bool drr_internal_supported;
+   bool lcd_freesync_default_set;
+   int lcd_freesync_default_value;
 };
 
 struct core_freesync {
@@ -189,6 +193,16 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
(data & 1) ? false : true;
}
 
+   if (dm_read_persistent_data(dc->ctx, NULL, NULL,
+   FREESYNC_DEFAULT_REGKEY,
+   , sizeof(data), )) {
+   core_freesync->opts.lcd_freesync_default_set = true;
+   core_freesync->opts.lcd_freesync_default_value = data;
+   } else {
+   core_freesync->opts.lcd_freesync_default_set = false;
+   core_freesync->opts.lcd_freesync_default_value = 0;
+   }
+
return _freesync->public;
 
 fail_construct:
@@ -294,6 +308,18 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,

core_freesync->map[core_freesync->num_entities].user_enable.
enable_for_video =
(persistent_freesync_enable & 4) ? true : false;
+   /* If FreeSync display and LCDFreeSyncDefault is set, use as 
default values write back to userenable */
+   } else if (caps->supported && 
(core_freesync->opts.lcd_freesync_default_set)) {
+   
core_freesync->map[core_freesync->num_entities].user_enable.enable_for_gaming =
+   (core_freesync->opts.lcd_freesync_default_value 
& 1) ? true : false;
+   
core_freesync->map[core_freesync->num_entities].user_enable.enable_for_static =
+   (core_freesync->opts.lcd_freesync_default_value 
& 2) ? true : false;
+   
core_freesync->map[core_freesync->num_entities].user_enable.enable_for_video =
+   (core_freesync->opts.lcd_freesync_default_value 
& 4) ? true : false;
+   dm_write_persistent_data(dc->ctx, stream->sink,
+   FREESYNC_REGISTRY_NAME,
+   "userenable", 
_freesync->opts.lcd_freesync_default_value,
+   sizeof(int), );
} else {

core_freesync->map[core_freesync->num_entities].user_enable.
enable_for_gaming = false;
-- 
2.14.1

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[PATCH 24/28] drm/amd/display: update dce_calcs to latest version

[Harry Wentland]

From: Dmytro Laktyushkin 

Bw spreadsheet was updated while dce_calcs was not

Change-Id: I66bb120aa855afbb90647047a39f32a2b10886eb
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 160 +++
 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h   |   6 +
 2 files changed, 110 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 6d38b8f43198..0cbab81ab304 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -85,7 +85,6 @@ static void calculate_bandwidth(
const uint32_t s_mid5 = 5;
const uint32_t s_mid6 = 6;
const uint32_t s_high = 7;
-   const uint32_t bus_efficiency = 1;
const uint32_t dmif_chunk_buff_margin = 1;
 
uint32_t max_chunks_fbc_mode;
@@ -592,7 +591,12 @@ static void calculate_bandwidth(
/* 1 = use channel 0 and 1*/
/* 2 = use channel 0,1,2,3*/
if ((fbc_enabled == 1 && lpt_enabled == 1)) {
-   data->dram_efficiency = bw_int_to_fixed(1);
+   if (vbios->memory_type == bw_def_hbm)
+   data->dram_efficiency = bw_frc_to_fixed(5, 10);
+   else
+   data->dram_efficiency = bw_int_to_fixed(1);
+
+
if (dceip->low_power_tiling_mode == 0) {
data->number_of_dram_channels = 1;
}
@@ -607,7 +611,10 @@ static void calculate_bandwidth(
}
}
else {
-   data->dram_efficiency = bw_frc_to_fixed(8, 10);
+   if (vbios->memory_type == bw_def_hbm)
+   data->dram_efficiency = bw_frc_to_fixed(5, 10);
+   else
+   data->dram_efficiency = bw_frc_to_fixed(8, 10);
}
/*memory request size and latency hiding:*/
/*request size is normally 64 byte, 2-line interleaved, with full 
latency hiding*/
@@ -1171,9 +1178,9 @@ static void calculate_bandwidth(
}
for (i = 0; i <= 2; i++) {
for (j = 0; j <= 7; j++) {
-   data->dmif_burst_time[i][j] = 
bw_max3(data->dmif_total_page_close_open_time, 
bw_div(data->total_display_reads_required_dram_access_data, 
(bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), 
bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), 
bw_int_to_fixed(data->number_of_dram_channels, 
bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], 
vbios->data_return_bus_width), bw_int_to_fixed(bus_efficiency);
+   data->dmif_burst_time[i][j] = 
bw_max3(data->dmif_total_page_close_open_time, 
bw_div(data->total_display_reads_required_dram_access_data, 
(bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), 
bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), 
bw_int_to_fixed(data->number_of_dram_channels, 
bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], 
vbios->data_return_bus_width), 
bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 
100);
if (data->d1_display_write_back_dwb_enable == 1) {
-   data->mcifwr_burst_time[i][j] = 
bw_max3(data->mcifwr_total_page_close_open_time, 
bw_div(data->total_display_writes_required_dram_access_data, 
(bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), 
bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), 
bw_int_to_fixed(data->number_of_dram_wrchannels, 
bw_div(data->total_display_writes_required_data, (bw_mul(bw_mul(sclk[j], 
vbios->data_return_bus_width), bw_int_to_fixed(bus_efficiency);
+   data->mcifwr_burst_time[i][j] = 
bw_max3(data->mcifwr_total_page_close_open_time, 
bw_div(data->total_display_writes_required_dram_access_data, 
(bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), 
bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), 
bw_int_to_fixed(data->number_of_dram_wrchannels, 
bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], 
vbios->data_return_bus_width;
}
}
}
@@ -1258,6 +1265,16 @@ static void calculate_bandwidth(
/*  / (dispclk - display bw)*/
/*the minimum latency hiding is the minimum for all pipes of one screen 
line time, plus one more line time if doing lb prefetch, plus the dmif data 
buffer size equivalent in time, minus the urgent latency.*/
/*the minimum latency hiding is  further limited by the cursor.  the 
cursor latency hiding is the number of lines of the cursor buffer, minus one if 
the downscaling 

[PATCH 03/28] drm/amd/display: Vari-bright looks disabled near end of MM14

[Harry Wentland]

From: SivapiriyanKumarasamy 

Avoid hanging DMCU by setting abm level only when OTG unblanked

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  8 +
 drivers/gpu/drm/amd/display/dc/dc.h|  5 
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  4 +++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 35 ++
 4 files changed, 40 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8394d69b963f..a0b91eeb1939 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -42,6 +42,7 @@
 #include "dmcu.h"
 #include "dpp.h"
 #include "timing_generator.h"
+#include "abm.h"
 #include "virtual/virtual_link_encoder.h"
 
 #include "link_hwss.h"
@@ -1361,6 +1362,13 @@ static void commit_planes_for_stream(struct dc *dc,
 
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, 
stream_status->plane_count, context);
+
+   if (stream_update->abm_setting.stream_update) {
+   if (dc->res_pool->abm)
+   dc->res_pool->abm->funcs->set_abm_level(
+   dc->res_pool->abm, 
stream->abm_settings.abm_level);
+   stream->abm_settings.stream_update = 0;
+   }
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2cd97342bf0f..bf4f2e6960cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -60,6 +60,11 @@ struct dc_versions {
struct dmcu_version dmcu_version;
 };
 
+struct abm_setting {
+   bool stream_update;
+   unsigned int abm_level;
+};
+
 struct dc_caps {
uint32_t max_streams;
uint32_t max_links;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index f44cd4d87b79..76189418cbfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -74,6 +74,9 @@ struct dc_stream_state {
unsigned char psr_version;
/* TODO: CEA VIC */
 
+   /* DMCU info */
+   struct abm_setting abm_settings;
+
/* from core_stream struct */
struct dc_context *ctx;
 
@@ -106,6 +109,7 @@ struct dc_stream_update {
struct dc_transfer_func *out_transfer_func;
struct dc_hdr_static_metadata *hdr_static_metadata;
enum color_transfer_func color_output_tf;
+   struct abm_setting abm_setting;
 };
 
 bool dc_is_stream_unchanged(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1907ade1574a..c434e38e6e46 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1780,14 +1780,33 @@ static void update_dchubp_dpp(
hubp->funcs->set_blank(hubp, false);
 }
 
+static void dcn10_otg_blank(
+   struct stream_resource stream_res,
+   struct abm *abm,
+   struct dc_stream_state *stream,
+   bool blank)
+{
+
+   if (!blank) {
+   if (stream_res.tg->funcs->set_blank)
+   stream_res.tg->funcs->set_blank(stream_res.tg, blank);
+   if (abm)
+   abm->funcs->set_abm_level(abm, 
stream->abm_settings.abm_level);
+   } else if (blank) {
+   if (abm)
+   abm->funcs->set_abm_immediate_disable(abm);
+   if (stream_res.tg->funcs->set_blank)
+   stream_res.tg->funcs->set_blank(stream_res.tg, blank);
+   }
+}
 
 static void program_all_pipe_in_tree(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
 {
-
if (pipe_ctx->top_pipe == NULL) {
+   bool blank = !is_pipe_tree_visible(pipe_ctx);
 
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = 
pipe_ctx->pipe_dlg_param.vready_offset;
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = 
pipe_ctx->pipe_dlg_param.vstartup_start;
@@ -1798,10 +1817,8 @@ static void program_all_pipe_in_tree(
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg);
 
-   if (pipe_ctx->stream_res.tg->funcs->set_blank)
-   pipe_ctx->stream_res.tg->funcs->set_blank(
-   pipe_ctx->stream_res.tg,
-   

[PATCH 18/28] drm/amd/display: Add variable refresh rate parameters to DC structures

[Harry Wentland]

From: Anthony Koo 

Time stamping will be part of surface, and will be updated when address is 
flipped.
FreeSync parameters will be attached to stream, as it adjusts the timing 
dynamically.

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h  |  2 ++
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 12 +++-
 drivers/gpu/drm/amd/display/dc/dc_stream.h   |  2 ++
 drivers/gpu/drm/amd/display/dc/dc_types.h| 18 ++
 4 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2cd97342bf0f..19aec82a9429 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -447,6 +447,7 @@ union surface_update_flags {
 
 struct dc_plane_state {
struct dc_plane_address address;
+   struct dc_plane_flip_time time;
struct scaling_taps scaling_quality;
struct rect src_rect;
struct rect dst_rect;
@@ -557,6 +558,7 @@ struct dc_transfer_func *dc_create_transfer_func(void);
  */
 struct dc_flip_addrs {
struct dc_plane_address address;
+   unsigned int flip_timestamp_in_us;
bool flip_immediate;
/* TODO: add flip duration for FreeSync */
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index e91ac6811990..b83a7dc2f5a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -692,8 +692,18 @@ struct crtc_trigger_info {
enum trigger_delay delay;
 };
 
-struct dc_crtc_timing {
+enum vrr_state {
+   VRR_STATE_OFF = 0,
+   VRR_STATE_VARIABLE,
+   VRR_STATE_FIXED,
+};
 
+struct dc_crtc_timing_adjust {
+   uint32_t v_total_min;
+   uint32_t v_total_max;
+};
+
+struct dc_crtc_timing {
uint32_t h_total;
uint32_t h_border_left;
uint32_t h_addressable;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index bafe3889676f..13e5ac9cfe13 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -48,6 +48,8 @@ struct dc_stream_status {
 struct dc_stream_state {
struct dc_sink *sink;
struct dc_crtc_timing timing;
+   struct dc_crtc_timing_adjust timing_adjust;
+   struct vrr_params vrr_params;
 
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 8811b6f86bff..9441305d3ab5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -521,6 +521,24 @@ struct audio_info {
struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
 };
 
+struct vrr_params {
+   enum vrr_state state;
+   uint32_t window_min;
+   uint32_t window_max;
+   uint32_t inserted_frame_duration_in_us;
+   uint32_t frames_to_insert;
+   uint32_t frame_counter;
+};
+
+#define DC_PLANE_UPDATE_TIMES_MAX 10
+
+struct dc_plane_flip_time {
+   unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
+   unsigned int index;
+   unsigned int prev_update_time_in_us;
+};
+
+// Will combine with vrr_params at some point.
 struct freesync_context {
bool supported;
bool enabled;
-- 
2.14.1

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[PATCH 13/28] drm/amd/display: Use MACROS instead of dm_logger

[Harry Wentland]

From: Bhawanpreet Lakha 

Use DC_LOGGER macro for logs.

Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c| 14 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c |  3 +--
 drivers/gpu/drm/amd/display/dc/dml/dml_logger.h   |  7 +--
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index c15565092ca8..f82275eb81bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -36,26 +36,22 @@
 #include "hw_sequencer.h"
 
 #include "resource.h"
+#define DC_LOGGER \
+   logger
 
 #define SURFACE_TRACE(...) do {\
if (dc->debug.surface_trace) \
-   dm_logger_write(logger, \
-   LOG_IF_TRACE, \
-   ##__VA_ARGS__); \
+   DC_LOG_IF_TRACE(__VA_ARGS__); \
 } while (0)
 
 #define TIMING_TRACE(...) do {\
if (dc->debug.timing_trace) \
-   dm_logger_write(logger, \
-   LOG_SYNC, \
-   ##__VA_ARGS__); \
+   DC_LOG_SYNC(__VA_ARGS__); \
 } while (0)
 
 #define CLOCK_TRACE(...) do {\
if (dc->debug.clock_trace) \
-   dm_logger_write(logger, \
-   LOG_BANDWIDTH_CALCS, \
-   ##__VA_ARGS__); \
+   DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
 } while (0)
 
 void pre_surface_trace(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 81776e4797ed..8167cad7bcf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -767,8 +767,7 @@ void dce110_link_encoder_construct(
bp_cap_info.DP_HBR3_EN;
enc110->base.features.flags.bits.HDMI_6GB_EN = 
bp_cap_info.HDMI_6GB_EN;
} else {
-   dm_logger_write(enc110->base.ctx->logger, LOG_WARNING,
-   "%s: Failed to get encoder_cap_info from VBIOS 
with error code %d!\n",
+   DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS 
with error code %d!\n",
__func__,
result);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h
index 7c22f3d75cd4..465859b77248 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h
@@ -27,8 +27,11 @@
 #ifndef __DML_LOGGER_H_
 #define __DML_LOGGER_H_
 
-#define dml_print(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
-#define DTRACE(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
+#define DC_LOGGER \
+   mode_lib->logger
+
+#define dml_print(str, ...) {DC_LOG_DML(str, ##__VA_ARGS__); }
+#define DTRACE(str, ...) {DC_LOG_DML(str, ##__VA_ARGS__); }
 
 #endif
 
-- 
2.14.1

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[PATCH 21/28] drm/amd/display: Correct the plane enumeration order

[Harry Wentland]

From: Shirish S 

The order of planes is given by the order they are enumerated
by kms.
Planes with a higher ID appears above planes with a lower ID.

Currently the planes are enumerated in the wrong order,
putting the nv12 only plane after the two RGBA planes.

This patch corrects the plane enumeration order such that all
the overlay planes are initialized first then the primary planes.

Due to this change in order the dc_add_plane_to_context() shall
receive the planes in reverse order hence this patch reverses
the parsing of planes in DM side itself.

Signed-off-by: Shirish S 
Signed-off-by: Pratik Vishwakarma 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 ---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 23 +++
 2 files changed, 76 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8ea484b0fe81..bf72f767bab6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1365,6 +1365,43 @@ amdgpu_dm_register_backlight_device(struct 
amdgpu_display_manager *dm)
 
 #endif
 
+static int initialize_plane(struct amdgpu_display_manager *dm,
+struct amdgpu_mode_info *mode_info,
+int plane_id)
+{
+   struct amdgpu_plane *plane;
+   unsigned long possible_crtcs;
+   int ret = 0;
+
+   plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
+   mode_info->planes[plane_id] = plane;
+
+   if (!plane) {
+   DRM_ERROR("KMS: Failed to allocate plane\n");
+   return -ENOMEM;
+   }
+   plane->base.type = mode_info->plane_type[plane_id];
+
+   /*
+* HACK: IGT tests expect that each plane can only have one
+* one possible CRTC. For now, set one CRTC for each
+* plane that is not an underlay, but still allow multiple
+* CRTCs for underlay planes.
+*/
+   possible_crtcs = 1 << plane_id;
+   if (plane_id >= dm->dc->caps.max_streams)
+   possible_crtcs = 0xff;
+
+   ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], 
possible_crtcs);
+
+   if (ret) {
+   DRM_ERROR("KMS: Failed to initialize plane\n");
+   return ret;
+   }
+
+   return ret;
+}
+
 /* In this architecture, the association
  * connector -> encoder -> crtc
  * id not really requried. The crtc and connector will hold the
@@ -1375,12 +1412,12 @@ amdgpu_dm_register_backlight_device(struct 
amdgpu_display_manager *dm)
 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 {
struct amdgpu_display_manager *dm = >dm;
-   uint32_t i;
+   int32_t i;
struct amdgpu_dm_connector *aconnector = NULL;
struct amdgpu_encoder *aencoder = NULL;
struct amdgpu_mode_info *mode_info = >mode_info;
uint32_t link_cnt;
-   unsigned long possible_crtcs;
+   int32_t total_overlay_planes, total_primary_planes;
 
link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
@@ -1388,30 +1425,22 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
return -1;
}
 
-   for (i = 0; i < dm->dc->caps.max_planes; i++) {
-   struct amdgpu_plane *plane;
+   /* Identify the number of planes to be initialized */
+   total_overlay_planes = dm->dc->caps.max_slave_planes;
+   total_primary_planes = dm->dc->caps.max_planes - 
dm->dc->caps.max_slave_planes;
 
-   plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
-   mode_info->planes[i] = plane;
-
-   if (!plane) {
-   DRM_ERROR("KMS: Failed to allocate plane\n");
+   /* First initialize overlay planes, index starting after primary planes 
*/
+   for (i = (total_overlay_planes - 1); i >= 0; i--) {
+   if (initialize_plane(dm, mode_info, (total_primary_planes + 
i))) {
+   DRM_ERROR("KMS: Failed to initialize overlay plane\n");
goto fail;
}
-   plane->base.type = mode_info->plane_type[i];
-
-   /*
-* HACK: IGT tests expect that each plane can only have one
-* one possible CRTC. For now, set one CRTC for each
-* plane that is not an underlay, but still allow multiple
-* CRTCs for underlay planes.
-*/
-   possible_crtcs = 1 << i;
-   if (i >= dm->dc->caps.max_streams)
-   possible_crtcs = 0xff;
+   }
 
-   if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 
possible_crtcs)) {
-   DRM_ERROR("KMS: Failed to initialize 

[PATCH 11/28] drm/amd/display: Modified set bandwidth sequence.

[Harry Wentland]

From: Yongqiang Sun 

This change make sure bandwidth is set properly.
For increase bandwidth, set bandwidth before backend
and front end programming.
For decrease bandwidth, set bandwidth after.
To avoid smu hang when reboot and dpms due to 0 disp clk,
keep min disp clock as 100Mhz.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  4 +--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 40 --
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  6 
 3 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fa402291a921..16a1931bc4cd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -871,11 +871,11 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
context->streams[i]->timing.pix_clk_khz);
}
 
+   dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+
/* pplib is notified if disp_num changed */
dc->hwss.set_bandwidth(dc, context, true);
 
-   dc_enable_stereo(dc, context, dc_streams, context->stream_count);
-
dc_release_state(dc->current_state);
 
dc->current_state = context;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f1990c3c893d..5257f32c965b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2088,6 +2088,11 @@ static void dcn10_apply_ctx_for_surface(
 */
 }
 
+static inline bool should_set_clock(bool decrease_allowed, int calc_clk, int 
cur_clk)
+{
+   return ((decrease_allowed && calc_clk < cur_clk) || calc_clk > cur_clk);
+}
+
 static void dcn10_set_bandwidth(
struct dc *dc,
struct dc_state *context,
@@ -2105,29 +2110,40 @@ static void dcn10_set_bandwidth(
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
return;
 
-   if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
-   > dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
+   if (should_set_clock(
+   decrease_allowed,
+   context->bw.dcn.calc_clk.dispclk_khz,
+   dc->current_state->bw.dcn.cur_clk.dispclk_khz)) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dcn.calc_clk.dispclk_khz);
context->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz;
}
-   if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
-   > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
+
+   if (should_set_clock(
+   decrease_allowed,
+   context->bw.dcn.calc_clk.dcfclk_khz,
+   dc->current_state->bw.dcn.cur_clk.dcfclk_khz)) {
context->bw.dcn.cur_clk.dcfclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz;
smu_req.hard_min_dcefclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz;
}
-   if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
-   > dc->current_state->bw.dcn.cur_clk.fclk_khz) {
+
+   if (should_set_clock(
+   decrease_allowed,
+   context->bw.dcn.calc_clk.fclk_khz,
+   dc->current_state->bw.dcn.cur_clk.fclk_khz)) {
context->bw.dcn.cur_clk.fclk_khz =
context->bw.dcn.calc_clk.fclk_khz;
smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
}
-   if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
-   > 
dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
+
+   if (should_set_clock(
+   decrease_allowed,
+   context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
+   
dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz)) {
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
}
@@ -2140,12 +2156,16 @@ static void dcn10_set_bandwidth(
*smu_req_cur = smu_req;
 
/* Decrease in freq is increase in period so opposite comparison for 
dram_ccm */
-   if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
+   if ((decrease_allowed && context->bw.dcn.calc_clk.dram_ccm_us
+  

[PATCH 16/28] drm/amd/display: early return if not in vga mode in disable_vga

[Harry Wentland]

From: Eric Yang 

The work around for hw bug causes S3 resume failure. Don't execute
disable vga logic if not in vga mode.

Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h|  4 +++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 19ca7f000506..18dbd0bd7874 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -407,6 +407,7 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+   HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
@@ -495,7 +496,8 @@ struct dce_hwseq_registers {
type DENTIST_DPPCLK_WDIVIDER; \
type DENTIST_DISPCLK_WDIVIDER; \
type VGA_TEST_ENABLE; \
-   type VGA_TEST_RENDER_START;
+   type VGA_TEST_RENDER_START; \
+   type D1VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0874d4a3fd72..50088b674795 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -220,10 +220,14 @@ static void enable_power_gating_plane(
 static void disable_vga(
struct dce_hwseq *hws)
 {
+   unsigned int in_vga_mode = 0;
+
+   REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, _vga_mode);
+
+   if (in_vga_mode == 0)
+   return;
+
REG_WRITE(D1VGA_CONTROL, 0);
-   REG_WRITE(D2VGA_CONTROL, 0);
-   REG_WRITE(D3VGA_CONTROL, 0);
-   REG_WRITE(D4VGA_CONTROL, 0);
 
/* HW Engineer's Notes:
 *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
-- 
2.14.1

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[PATCH 12/28] drm/amd/display: Move DTRACE and dml_print defines

[Harry Wentland]

From: Bhawanpreet Lakha 

These MACROS are only being used by a few files but
gets pulled in by dc.h

Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dml/display_rq_dlg_helpers.c|  1 +
 .../gpu/drm/amd/display/dc/dml/dml_common_defs.h   |  2 --
 .../gpu/drm/amd/display/dc/dml/dml_inline_defs.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dml/dml_logger.h| 35 ++
 4 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_logger.h

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
index 189052e911fc..48400d642610 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
@@ -24,6 +24,7 @@
  */
 
 #include "display_rq_dlg_helpers.h"
+#include "dml_logger.h"
 
 void print__rq_params_st(struct display_mode_lib *mode_lib, 
display_rq_params_st rq_param)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
index b2847bc469fe..f78cbae9db88 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
@@ -31,8 +31,6 @@
 #include "display_mode_structs.h"
 #include "display_mode_enums.h"
 
-#define dml_print(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
-#define DTRACE(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
 
 double dml_round(double a);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
index e68086b8a22f..f9cf08357989 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
@@ -28,6 +28,7 @@
 
 #include "dml_common_defs.h"
 #include "../calcs/dcn_calc_math.h"
+#include "dml_logger.h"
 
 static inline double dml_min(double a, double b)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h 
b/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h
new file mode 100644
index ..7c22f3d75cd4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_logger.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#ifndef __DML_LOGGER_H_
+#define __DML_LOGGER_H_
+
+#define dml_print(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
+#define DTRACE(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, 
##__VA_ARGS__); }
+
+#endif
+
+
-- 
2.14.1

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[PATCH 25/28] drm/amd/display: Check for HW blocks in HWSS, rather than DC core for cursor

[Harry Wentland]

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 +--
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 9 ++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index cd5819789d76..ce0747ed0f00 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -198,8 +198,7 @@ bool dc_stream_set_cursor_attributes(
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[i];
 
-   if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm &&
-   !pipe_ctx->plane_res.dpp) || !pipe_ctx->plane_res.ipp)
+   if (pipe_ctx->stream != stream)
continue;
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != 
pipe_ctx->top_pipe->plane_state)
continue;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9de3d793f12e..206569e13a2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2937,15 +2937,18 @@ void dce110_set_cursor_attribute(struct pipe_ctx 
*pipe_ctx)
 {
struct dc_cursor_attributes *attributes = 
_ctx->stream->cursor_attributes;
 
-   if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
+   if (pipe_ctx->plane_res.ipp &&
+   pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
pipe_ctx->plane_res.ipp, attributes);
 
-   if (pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
+   if (pipe_ctx->plane_res.mi &&
+   pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
pipe_ctx->plane_res.mi, attributes);
 
-   if (pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
+   if (pipe_ctx->plane_res.xfm &&
+   pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
pipe_ctx->plane_res.xfm, attributes);
 }
-- 
2.14.1

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[PATCH 04/28] drm/amd/display: Varibright fix bug and review comments

[Harry Wentland]

From: SivapiriyanKumarasamy 

Fix bug and make changes from review 132656

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 14 +++-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  5 +
 drivers/gpu/drm/amd/display/dc/dc.h|  5 -
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  4 ++--
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 25 --
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  1 +
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  2 ++
 7 files changed, 37 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a0b91eeb1939..40a65cb9ee23 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1363,11 +1363,15 @@ static void commit_planes_for_stream(struct dc *dc,
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, 
stream_status->plane_count, context);
 
-   if (stream_update->abm_setting.stream_update) {
-   if (dc->res_pool->abm)
-   dc->res_pool->abm->funcs->set_abm_level(
-   dc->res_pool->abm, 
stream->abm_settings.abm_level);
-   stream->abm_settings.stream_update = 0;
+   if (stream_update->abm_level && 
pipe_ctx->stream_res.abm) {
+   if (pipe_ctx->stream_res.tg->funcs->is_blanked) 
{
+   // if otg funcs defined check if 
blanked before programming
+   if 
(!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
+   
pipe_ctx->stream_res.abm->funcs->set_abm_level(
+   
pipe_ctx->stream_res.abm, stream->abm_level);
+   } else
+   
pipe_ctx->stream_res.abm->funcs->set_abm_level(
+   
pipe_ctx->stream_res.abm, stream->abm_level);
}
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b9fc6d842931..ba3487e97361 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1124,6 +1124,7 @@ bool dc_add_plane_to_context(
ASSERT(tail_pipe);
 
free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
+   free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
free_pipe->stream_res.stream_enc = 
tail_pipe->stream_res.stream_enc;
free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
@@ -1736,6 +1737,10 @@ enum dc_status resource_map_pool_resources(
   pipe_ctx->stream_res.audio, true);
}
 
+   /* Add ABM to the resource if on EDP */
+   if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal))
+   pipe_ctx->stream_res.abm = pool->abm;
+
for (i = 0; i < context->stream_count; i++)
if (context->streams[i] == stream) {
context->stream_status[i].primary_otg_inst = 
pipe_ctx->stream_res.tg->inst;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index bf4f2e6960cb..2cd97342bf0f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -60,11 +60,6 @@ struct dc_versions {
struct dmcu_version dmcu_version;
 };
 
-struct abm_setting {
-   bool stream_update;
-   unsigned int abm_level;
-};
-
 struct dc_caps {
uint32_t max_streams;
uint32_t max_links;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 76189418cbfa..bafe3889676f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -75,7 +75,7 @@ struct dc_stream_state {
/* TODO: CEA VIC */
 
/* DMCU info */
-   struct abm_setting abm_settings;
+   unsigned int abm_level;
 
/* from core_stream struct */
struct dc_context *ctx;
@@ -109,7 +109,7 @@ struct dc_stream_update {
struct dc_transfer_func *out_transfer_func;
struct dc_hdr_static_metadata *hdr_static_metadata;
enum color_transfer_func color_output_tf;
-   struct abm_setting abm_setting;
+   

Re: New KFD ioctls: taking the skeletons out of the closet

[Jerome Glisse]

On Tue, Mar 06, 2018 at 05:44:41PM -0500, Felix Kuehling wrote:
> Hi all,
> 
> Christian raised two potential issues in a recent KFD upstreaming code
> review that are related to the KFD ioctl APIs:
> 
>  1. behaviour of -ERESTARTSYS
>  2. transactional nature of KFD ioctl definitions, or lack thereof
> 
> I appreciate constructive feedback, but I also want to encourage an
> open-minded rather than a dogmatic approach to API definitions. So let
> me take all the skeletons out of my closet and get these APIs reviewed
> in the appropriate forum before we commit to them upstream. See the end
> of this email for reference.
> 
> The controversial part at this point is kfd_ioctl_map_memory_to_gpu. If
> any of the other APIs raise concerns or questions, please ask.
> 
> Because of the HSA programming model, KFD memory management APIs are
> synchronous. There is no pipelining. Command submission to GPUs through
> user mode queues does not involve KFD. This means KFD doesn't know what
> memory is used by the GPUs and when it's used. That means, when the
> map_memory_to_gpu ioctl returns to user mode, all memory mapping
> operations are complete and the memory can be used by the CPUs or GPUs
> immediately.
> 
> HSA also uses a shared virtual memory model, so typically memory gets
> mapped on multiple GPUs and CPUs at the same virtual address.

Does this means that GPU memory get pin ? Or system memory for that matter
too. This was discuss previously but this really goes against kernel mantra
ie kernel no longer manage resources but userspace can hog GPU memory or
even system memory. This is bad !

Cheers,
Jérôme
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Re: New KFD ioctls: taking the skeletons out of the closet

[Dave Airlie]

On 7 March 2018 at 08:44, Felix Kuehling  wrote:
> Hi all,
>
> Christian raised two potential issues in a recent KFD upstreaming code
> review that are related to the KFD ioctl APIs:
>
>  1. behaviour of -ERESTARTSYS
>  2. transactional nature of KFD ioctl definitions, or lack thereof
>
> I appreciate constructive feedback, but I also want to encourage an
> open-minded rather than a dogmatic approach to API definitions. So let
> me take all the skeletons out of my closet and get these APIs reviewed
> in the appropriate forum before we commit to them upstream. See the end
> of this email for reference.
>
> The controversial part at this point is kfd_ioctl_map_memory_to_gpu. If
> any of the other APIs raise concerns or questions, please ask.
>
> Because of the HSA programming model, KFD memory management APIs are
> synchronous. There is no pipelining. Command submission to GPUs through
> user mode queues does not involve KFD. This means KFD doesn't know what
> memory is used by the GPUs and when it's used. That means, when the
> map_memory_to_gpu ioctl returns to user mode, all memory mapping
> operations are complete and the memory can be used by the CPUs or GPUs
> immediately.

I've got a few opinions, but first up I still dislike user-mode queues
and everything
they entail. I still feel they are solving a Windows problem and not a
Linux problem,
and it would be nice if we had some Linux numbers on what they gain us over
a dispatch ioctl, because they sure bring a lot of memory management issues.

That said amdkfd is here.

The first question you should ask (which you haven't asked here at all) is
what should userspace do with the ioctl result.

>
> HSA also uses a shared virtual memory model, so typically memory gets
> mapped on multiple GPUs and CPUs at the same virtual address.
>
> The point of contention seems to be the ability to map memory to
> multiple GPUs in a single ioctl and the behaviour in failure cases. I'll
> discuss two main failure cases:
>
> 1: Failure after all mappings have been dispatched via SDMA, but a
> signal interrupts the wait for completion and we return -ERESTARTSYS.
> Documentation/kernel-hacking/hacking.rst only says "[...] you should be
> prepared to process the restart, e.g. if you're in the middle of
> manipulating some data structure." I think we do that by ensuring that
> memory that's already mapped won't be mapped again. So the restart will
> become a no-op and just end up waiting for all the previous mappings to
> complete.

-ERESTARTSYS at that late stage points to a badly synchronous API,
I'd have said you should have two ioctls, one that returns a fence after
starting the processes, and one that waits for the fence separately.

The overhead of ioctls isn't your enemy until you've measured it and
proven it's a problem.

>
> Christian has a stricter requirement, and I'd like to know where that
> comes from: "An interrupted IOCTL should never have a visible effect."

Christian might be taking things a bit further but synchronous gpu access
APIs are bad, but I don't think undoing a bunch of work is a good plan either
just because you got ERESTARTSYS. If you get ERESTARTSYS can you
handle it, if I've fired off 5 SDMAs and wait for them will I fire off 5 more?
will I wait for the original SDMAs if I reenter?

>
> 2: Failure to map on some but not all GPUs. This comes down to the
> question, do all ioctl APIs or system calls in general need to be
> transactional? As a counter example I'd give incomplete read or write
> system calls that return how much was actually read or written. Our
> current implementation of map_memory_to_gpu doesn't do this, but it
> could be modified to return to user mode how many of the mappings, or
> which mappings specifically failed or succeeded.

What should userspace do? if it only get mappings on 3 of the gpus instead
of say 4? Is there a sane resolution other than calling the ioctl again with
the single GPU? Would it drop the GPU from the working set from that point on?

Need more info to do what can come out of the API doing incomplete
operations.

> The alternative would be to break multi-GPU mappings, and the final wait
> for completion, into multiple ioctl calls. That would result in
> additional system call overhead. I'd argue that the end result is the
> same for user mode, so I don't see why I'd use multiple ioctls over a
> single one.

Again stop worrying about ioctl overhead, this isn't Windows. If you
can show the overhead as being a problem then address it, but I
think it's premature worrying about it at this stage.

Dave.
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New KFD ioctls: taking the skeletons out of the closet

[Felix Kuehling]

Hi all,

Christian raised two potential issues in a recent KFD upstreaming code
review that are related to the KFD ioctl APIs:

 1. behaviour of -ERESTARTSYS
 2. transactional nature of KFD ioctl definitions, or lack thereof

I appreciate constructive feedback, but I also want to encourage an
open-minded rather than a dogmatic approach to API definitions. So let
me take all the skeletons out of my closet and get these APIs reviewed
in the appropriate forum before we commit to them upstream. See the end
of this email for reference.

The controversial part at this point is kfd_ioctl_map_memory_to_gpu. If
any of the other APIs raise concerns or questions, please ask.

Because of the HSA programming model, KFD memory management APIs are
synchronous. There is no pipelining. Command submission to GPUs through
user mode queues does not involve KFD. This means KFD doesn't know what
memory is used by the GPUs and when it's used. That means, when the
map_memory_to_gpu ioctl returns to user mode, all memory mapping
operations are complete and the memory can be used by the CPUs or GPUs
immediately.

HSA also uses a shared virtual memory model, so typically memory gets
mapped on multiple GPUs and CPUs at the same virtual address.

The point of contention seems to be the ability to map memory to
multiple GPUs in a single ioctl and the behaviour in failure cases. I'll
discuss two main failure cases:

1: Failure after all mappings have been dispatched via SDMA, but a
signal interrupts the wait for completion and we return -ERESTARTSYS.
Documentation/kernel-hacking/hacking.rst only says "[...] you should be
prepared to process the restart, e.g. if you're in the middle of
manipulating some data structure." I think we do that by ensuring that
memory that's already mapped won't be mapped again. So the restart will
become a no-op and just end up waiting for all the previous mappings to
complete.

Christian has a stricter requirement, and I'd like to know where that
comes from: "An interrupted IOCTL should never have a visible effect."

2: Failure to map on some but not all GPUs. This comes down to the
question, do all ioctl APIs or system calls in general need to be
transactional? As a counter example I'd give incomplete read or write
system calls that return how much was actually read or written. Our
current implementation of map_memory_to_gpu doesn't do this, but it
could be modified to return to user mode how many of the mappings, or
which mappings specifically failed or succeeded.

I'd like to know whether such behaviour is acceptable.

The alternative would be to break multi-GPU mappings, and the final wait
for completion, into multiple ioctl calls. That would result in
additional system call overhead. I'd argue that the end result is the
same for user mode, so I don't see why I'd use multiple ioctls over a
single one.

I'm looking forward to your feedback.

Thanks,
  Felix


Reference: After the last rework, these are the ioctls I'm hoping to
upstream in my current patch series (with annotations):

/* Acquire a VM from a DRM render node FD for use by KFD on a specific device
 *
 * @drm_fd: DRM render node file descriptor
 * @gpu_id: device identifier (used throughout the KFD API)
 */
struct kfd_ioctl_acquire_vm_args {
__u32 drm_fd;   /* to KFD */
__u32 gpu_id;   /* to KFD */
};

/* Allocation flags: memory types */
#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM(1 << 0)
#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL(1 << 3)
/* Allocation flags: attributes/access options */
#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE(1 << 31)
#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE  (1 << 30)
#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC  (1 << 29)
#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE   (1 << 28)
#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM   (1 << 27)
#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT(1 << 26)

/* Allocate memory for later SVM (shared virtual memory) mapping.
 *
 * @va_addr: virtual address of the memory to be allocated
 *   all later mappings on all GPUs will use this address
 * @size:size in bytes
 * @handle:  buffer handle returned to user mode, used to refer to
 *   this allocation for mapping, unmapping and freeing
 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
 *   for userptrs this is overloaded to specify the CPU address
 * @gpu_id:  device identifier
 * @flags:   memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
 */
struct kfd_ioctl_alloc_memory_of_gpu_args {
__u64 va_addr;  /* to KFD */
__u64 size; /* to KFD */
__u64 handle;   /* from KFD */
__u64 mmap_offset;  /* to KFD (userptr), from KFD (mmap offset) */
__u32 gpu_id;   /* to KFD */
__u32 flags;
};

/* Free memory 

Re: [PATCH 2/2] drm/amdgpu:Always save uvd vcpu_bo in VM Mode

[Leo Liu]

Series are:

Reviewed-by: Leo Liu 


On 03/06/2018 03:14 PM, James Zhu wrote:

When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 9d037cb..61a31e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -303,7 +303,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
if (atomic_read(>uvd.handles[i]))
break;
  
-	if (i == adev->uvd.max_handles)

+   /* only valid for physical mode */
+   if (i == adev->uvd.max_handles && adev->asic_type < CHIP_POLARIS10)
return 0;
  
  	size = amdgpu_bo_size(adev->uvd.vcpu_bo);


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[PATCH 2/2] drm/amdgpu:Always save uvd vcpu_bo in VM Mode

[James Zhu]

When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105021
Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 9d037cb..61a31e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -303,7 +303,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
if (atomic_read(>uvd.handles[i]))
break;
 
-   if (i == adev->uvd.max_handles)
+   /* only valid for physical mode */
+   if (i == adev->uvd.max_handles && adev->asic_type < CHIP_POLARIS10)
return 0;
 
size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu:Correct max uvd handles

[James Zhu]

Max uvd handles should use adev->uvd.max_handles instead of
AMDGPU_MAX_UVD_HANDLES here.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 7ad814d..9d037cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -303,7 +303,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
if (atomic_read(>uvd.handles[i]))
break;
 
-   if (i == AMDGPU_MAX_UVD_HANDLES)
+   if (i == adev->uvd.max_handles)
return 0;
 
size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

Am 06.03.2018 um 19:15 schrieb Michel Dänzer:

On 2018-03-06 07:02 PM, Christian König wrote:

Am 06.03.2018 um 18:51 schrieb Michel Dänzer:

On 2018-03-06 06:44 PM, Christian König wrote:

Am 06.03.2018 um 18:22 schrieb Li, Samuel:

addition to that I agree with Michel that the module parameter is
overkill.

That I already explained. Currently SG display feature needs to
provide options for all kinds of use cases. All amd drivers so far
provides options, and the default configuration is actually to
allocate everything from GTT when possible.

That isn't job of the kernel to have this parameter. Saying that we
should probably add a DDX and/or environment option to control that.

Why would we need that? It's the kernel driver's job to handle this as
needed.

Buffer placement is specified by the DDX/Mesa, when we override that in
the kernel we just force unnecessary buffer moves.

Userspace just needs a way to know which domains can/should be used for
scanout buffers, e.g. via an info ioctl.


Yeah, but why shouldn't they then make the decision where to place it as 
well?


See when we enforce a certain placement in the kernel we will just get 
an unnecessary buffer move with old user space components.


In other words the kernel just needs to advertise that the hw/sw 
combination allows scanout from GTT as well and then an updated 
userspace can actually make use of that placement or decide to not use 
it in certain situations. E.g. the last time I tested it placing things 
into GTT still resulted in quite a performance penalty for rendering.


The major use case I can currently see are A+A laptop, cause there it 
can avoid the additional buffer move from GTT to VRAM for the APU.


Regards,
Christian.
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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Michel Dänzer]

On 2018-03-06 07:02 PM, Christian König wrote:
> Am 06.03.2018 um 18:51 schrieb Michel Dänzer:
>> On 2018-03-06 06:44 PM, Christian König wrote:
>>> Am 06.03.2018 um 18:22 schrieb Li, Samuel:
> addition to that I agree with Michel that the module parameter is
> overkill.
 That I already explained. Currently SG display feature needs to
 provide options for all kinds of use cases. All amd drivers so far
 provides options, and the default configuration is actually to
 allocate everything from GTT when possible.
>>> That isn't job of the kernel to have this parameter. Saying that we
>>> should probably add a DDX and/or environment option to control that.
>> Why would we need that? It's the kernel driver's job to handle this as
>> needed.
> 
> Buffer placement is specified by the DDX/Mesa, when we override that in
> the kernel we just force unnecessary buffer moves.

Userspace just needs a way to know which domains can/should be used for
scanout buffers, e.g. via an info ioctl.


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RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Li, Samuel]

> Buffer placement is specified by the DDX/Mesa, when we override that in the 
> kernel we just force unnecessary buffer moves.
Since scan out buffer is moved to GTT now, DDX/Mesa might need to make some 
changes for this too.

Regards,
Samuel Li


> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Tuesday, March 06, 2018 1:02 PM
> To: Michel Dänzer ; Koenig, Christian
> ; Li, Samuel ; Alex
> Deucher 
> Cc: amd-gfx list 
> Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support
> 
> Am 06.03.2018 um 18:51 schrieb Michel Dänzer:
> > On 2018-03-06 06:44 PM, Christian König wrote:
> >> Am 06.03.2018 um 18:22 schrieb Li, Samuel:
>  addition to that I agree with Michel that the module parameter is
>  overkill.
> >>> That I already explained. Currently SG display feature needs to
> >>> provide options for all kinds of use cases. All amd drivers so far
> >>> provides options, and the default configuration is actually to
> >>> allocate everything from GTT when possible.
> >> That isn't job of the kernel to have this parameter. Saying that we
> >> should probably add a DDX and/or environment option to control that.
> > Why would we need that? It's the kernel driver's job to handle this as
> > needed.
> 
> Buffer placement is specified by the DDX/Mesa, when we override that in
> the kernel we just force unnecessary buffer moves.
> 
> Regards,
> Christian.
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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

Am 06.03.2018 um 18:51 schrieb Michel Dänzer:

On 2018-03-06 06:44 PM, Christian König wrote:

Am 06.03.2018 um 18:22 schrieb Li, Samuel:

addition to that I agree with Michel that the module parameter is
overkill.

That I already explained. Currently SG display feature needs to
provide options for all kinds of use cases. All amd drivers so far
provides options, and the default configuration is actually to
allocate everything from GTT when possible.

That isn't job of the kernel to have this parameter. Saying that we
should probably add a DDX and/or environment option to control that.

Why would we need that? It's the kernel driver's job to handle this as
needed.


Buffer placement is specified by the DDX/Mesa, when we override that in 
the kernel we just force unnecessary buffer moves.


Regards,
Christian.
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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Michel Dänzer]

On 2018-03-06 06:44 PM, Christian König wrote:
> Am 06.03.2018 um 18:22 schrieb Li, Samuel:
>>
>>> addition to that I agree with Michel that the module parameter is
>>> overkill.
>> That I already explained. Currently SG display feature needs to
>> provide options for all kinds of use cases. All amd drivers so far
>> provides options, and the default configuration is actually to
>> allocate everything from GTT when possible.
> 
> That isn't job of the kernel to have this parameter. Saying that we
> should probably add a DDX and/or environment option to control that.

Why would we need that? It's the kernel driver's job to handle this as
needed.


-- 
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Libre software enthusiast | Mesa and X developer
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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

Am 06.03.2018 um 18:22 schrieb Li, Samuel:

And exactly that's the problematical assumption.

Not assumption, I tested. You have any typical use case that it might become a 
problem?


Not 100% sure, but I doubt you have tried that with different userspace 
programs.


Especially animated boot screens could allocated quite a number of 
framebuffers.





addition to that I agree with Michel that the module parameter is overkill.

That I already explained. Currently SG display feature needs to provide options 
for all kinds of use cases. All amd drivers so far provides options, and the 
default configuration is actually to allocate everything from GTT when possible.


That isn't job of the kernel to have this parameter. Saying that we 
should probably add a DDX and/or environment option to control that.


Regards,
Christian.



Regards,
Samuel Li



-Original Message-
From: Koenig, Christian
Sent: Tuesday, March 06, 2018 12:12 PM
To: Li, Samuel ; Alex Deucher

Cc: amd-gfx list 
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

And exactly that's the problematical assumption.

This doesn't print only when the module is loaded, but rather when a
framebuffer object is created.

And depending on the use case that can even be many many times per
second.

Please remove that printing, addition to that I agree with Michel that the
module parameter is overkill.

Regards,
Christian.

Am 06.03.2018 um 18:09 schrieb Li, Samuel:

This information is kind of important, and it only prints once typically when

module is loaded.

Regards,
Samuel Li



-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com]
Sent: Tuesday, March 06, 2018 12:04 PM
To: Li, Samuel 
Cc: Koenig, Christian ; amd-gfx list 
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display
support

On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li  wrote:

domain = amdgpu_display_framebuffer_domains(adev);
+if (domain == AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: enabled\n");
+} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: auto\n");
+}

Dito and printing that here is not a good idea as far as I can see.

Christian.

The intention here is to print out when fb is created. You have
other

suggestions?

Make it DRM_DEBUG?  otherwise you'll spam the logs.


Sam


On 2018-03-03 08:41 AM, Christian König wrote:

Am 03.03.2018 um 00:25 schrieb Samuel Li:

It's enabled by default. -1 is auto, to allow both vram and gtt
memory be available, for testing purpose only.
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
4 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 292c7e7..6b0ee34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
extern int amdgpu_compute_multipipe;
extern int amdgpu_gpu_recovery;
extern int amdgpu_emu_mode;
+extern int amdgpu_sg_display;
  #ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 5495b29..dfa11b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -513,8 +513,13 @@ uint32_t

amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)

#if defined(CONFIG_DRM_AMD_DC)
if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <

CHIP_RAVEN &&

adev->flags & AMD_IS_APU &&
-amdgpu_device_asic_has_dc_support(adev->asic_type))
-domain |= AMDGPU_GEM_DOMAIN_GTT;
+amdgpu_device_asic_has_dc_support(adev->asic_type)) {
+if (amdgpu_sg_display == 1) {
+domain = AMDGPU_GEM_DOMAIN_GTT;
+} else if (amdgpu_sg_display == -1) {
+domain |= AMDGPU_GEM_DOMAIN_GTT;
+}

Coding style, that if shouldn't use "{" and "}".


+}
#endif
  return domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e670936..f0ada24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
int amdgpu_compute_multipipe = -1;
int amdgpu_gpu_recovery = -1; /* auto */
int amdgpu_emu_mode = 0;
+int amdgpu_sg_display = 1;
  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in

megabytes");

module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);

@@

-290,6 +291,9 @@ 

Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[KARBOWSKI Piotr]

On 2018-03-06 18:28, Tom St Denis wrote:
I routinely rebase this patch on top of our amd-staging-drm-next tree at 
fdo.


https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next


Awesome.

So I used this tree, branch amd-staging-drm-next, and applied the patch 
- and my screen works now!


Is there a chance that those changes will still be included in 4.16, 
like, next rc?


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[ANNOUNCE] xf86-video-ati 18.0.0

[Michel Dänzer]

I'm pleased to announce the 18.0.0 release of xf86-video-ati, the Xorg
driver for ATI/AMD Radeon GPUs supported by the radeon kernel driver.
This release supports xserver versions 1.13-1.19. It also works with
xserver 1.20 RC1, so unless something unexpected happens, it should work
with xserver 1.20 as well.

Highlights:

* New year-based versioning scheme
* Page flipping can now be used even when the HW cursor can't be used in
  some cases
* Support for 30-bit RGB colour output. Note that gamma correction is
  currently not available with 30-bit colour. Also, GLAMOR hardware
  acceleration is not available with 30-bit colour with xserver versions
  before 1.20.

Plus other improvements and fixes. Thanks to everybody who contributed
to this release in any way!


Christoph Haag (1):
  fix include order for present.h configure test

Daniel Martin (3):
  modesetting: Check crtc before searching link-status property
  modesetting: Use helper to fetch drmModeProperty(Blob)s
  modesetting: Reset output_id if drmModeGetConnector failed

Darren Salt (1):
  Clarify when TearFree is automatically enabled.

Fredrik Höglund (1):
  exa: Accelerate ARGB2101010 pictures

Joakim Tjernlund (1):
  Fix non GLAMOR build

Keith Packard (2):
  modesetting: Skip no-longer-present connectors when resetting BAD links
  modesetting: Update property values at detect and uevent time

Mario Kleiner (5):
  Define per x-screen individual drmmode_crtc_funcs
  Skip xf86HandleColormaps() at color depth 30. (v2)
  Support exa screen color depth 30 on Linux 3.16 and later. (v2)
  Add missing depth 30 -> cpp=4 handling for DRI2.
  Make XvMC extension initialize at depth 30.

Michel Dänzer (23):
  Fix VT switching with ShadowFB
  Post-release version bump
  Bail if there's a problem with ShadowFB
  Unreference pixmap's FB with EXA as well in radeon_set_pixmap_bo
  Free pRADEONEnt memory in RADEONFreeRec
  Free memory returned by xf86GetEntityInfo
  Call TimerFree for timer created in LeaveVT
  Always call drmModeFreeProperty after drmModeGetProperty
  Use correct ScrnInfoPtr in redisplay_dirty
  Add radeon_dirty_src_drawable helper
  Move cursor related ScreenInit calls into RADEONCursorInit_KMS
  Keep track of how many SW cursors are visible on each screen
  Always use screen depth/bpp for KMS framebuffers
  glamor: Allow depth 30 with Xorg >= 1.19.99.1
  Don't use RADEONEntPriv in RADEONFreeRec
  Don't call RADEONFreeRec from RADEONPreInit_KMS
  Call RADEONFreeRec from RADEONFreeScreen_KMS even if info == NULL
  If glamor is too old for depth 30, fall back to EXA or ShadowFB
  Simplify depth 30 "kernel too old" error message
  Don't bail from drmmode_set_desired_modes immediately
  Disable all unused CRTCs before setting desired modes
  Only change Set/MoveCursor hooks from what we expect
  Bump version for 18.0.0 release

git tag: xf86-video-ati-18.0.0

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.0.tar.bz2
MD5:  4d41bfe860dc719654cad3f82d00f6f3  xf86-video-ati-18.0.0.tar.bz2
SHA1: da1b89a747264d976d824ddc7b5b4f803d3cf765  xf86-video-ati-18.0.0.tar.bz2
SHA256: 2c0368fb620d1fdfa2b435e672d65444c2fb9df21bbaf979298484b89ef83981  
xf86-video-ati-18.0.0.tar.bz2
SHA512: 
a9a634091f208099885039d42433cee061e03968417c0d535691833abcc9162d8d0a46f99bac902f0885beb14dcc9a011d104b535ffe492562fd5bb740ad4721
  xf86-video-ati-18.0.0.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.0.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.0.tar.gz
MD5:  a7beafba592be85a16dd8e94e60fc1a7  xf86-video-ati-18.0.0.tar.gz
SHA1: 02bcbc78d8c9552dce400e84190b68e54384eb31  xf86-video-ati-18.0.0.tar.gz
SHA256: a755ea4e0afbdd38a4bd13d42c1a684fbdcf0ae84474433b1cde7e1a91e8159d  
xf86-video-ati-18.0.0.tar.gz
SHA512: 
0b627012966d52d8060e621bdf6793fb35f9dc28f31534410f94a12da9ab854cae69bc4937a837edf5d96300b9d906d377940227d7ee8513a9872bed9238c2b1
  xf86-video-ati-18.0.0.tar.gz
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-18.0.0.tar.gz.sig


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Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[KARBOWSKI Piotr]

Hi,

On 2018-03-06 12:18, Tom St Denis wrote:

I believe this is the same issue I had which is a VGA handoff problem.

Can you try this patch the display team sent me?

Harry:  Will this patch be promoted in the next cycle?


What is the base for this patch? I cannot apply it on the top of any 
4.16-rc I try


1 out of 4 hunks FAILED -- saving rejects to file 
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h.rej


is there any tree that contain this fix, that I can clone sources from?

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Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state

[Alex Deucher]

On Tue, Mar 6, 2018 at 5:52 AM, Vishwakarma, Pratik
 wrote:
> Hi Daniel,
>
> I have checked make htmldocs on v2 of this patch. I have attached output 
> drm-kms.html on that thread.
> No indentation issue is observed. Attached again for reference.
> Can you please provide RB on that?

How did you send the patch?  I can't get V2 to apply.  The patch is
mangled.  Please use git-send-email if you didn't before.

Alex

>
> Regards
> Pratik
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
> Daniel Vetter
> Sent: Tuesday, March 6, 2018 3:36 PM
> To: Alex Deucher 
> Cc: Deucher, Alexander ; 
> amd-gfx@lists.freedesktop.org; Maling list - DRI developers 
> ; S, Shirish 
> Subject: Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state
>
> On Wed, Feb 28, 2018 at 09:26:26AM -0500, Alex Deucher wrote:
>> + dri-devel
>>
>>
>> On Wed, Feb 28, 2018 at 4:33 AM, S, Shirish  wrote:
>> > From: Shirish S 
>> >
>> > Add reverse iterator "for_each_oldnew_plane_in_state_reverse" to
>> > complement "for_each_oldnew_plane_in_state" way of reading plane
>> > states.
>> >
>> > The plane states are required to be read in reverse order for
>> > amdgpu, as the z order convention followed in linux is opposite to
>> > how the planes are supposed to be presented to DC engine, which is
>> > in common to both windows and linux.
>> >
>> > Signed-off-by: Shirish S 
>> > Signed-off-by: Pratik Vishwakarma 
>
> Makes sense.
>> > ---
>> >  include/drm/drm_atomic.h | 22 ++
>> >  1 file changed, 22 insertions(+)
>> >
>> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
>> > index cf13842..b947930 100644
>> > --- a/include/drm/drm_atomic.h
>> > +++ b/include/drm/drm_atomic.h
>> > @@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct 
>> > drm_printer *p);
>> >   (new_plane_state) =
>> > (__state)->planes[__i].new_state, 1))
>> >
>> >  /**
>> > + * for_each_oldnew_plane_in_state_reverse - iterate over all planes
>> > + in an atomic
>> > + * update in reverse order
>
> Are you sure this renders correctly in kernel-doc? Iirc you have to indent 
> the continuation line.
>
> Assuming this is fixed:
>
> Reviewed-by: Daniel Vetter 
>
>> > + * @__state:  drm_atomic_state pointer
>> > + * @plane:  drm_plane iteration cursor
>> > + * @old_plane_state:  drm_plane_state iteration cursor for
>> > +the old state
>> > + * @new_plane_state:  drm_plane_state iteration cursor for
>> > +the new state
>> > + * @__i: int iteration cursor, for macro-internal use
>> > + *
>> > + * This iterates over all planes in an atomic update in reverse
>> > +order,
>> > + * tracking both old and  new state. This is useful in places where
>> > +the
>> > + * state delta needs to be considered, for example in atomic check 
>> > functions.
>> > + */
>> > +#define for_each_oldnew_plane_in_state_reverse(__state, plane, 
>> > old_plane_state, new_plane_state, __i) \
>> > +   (for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1);   
>> >  \
>> > +(__i) >= 0;\
>> > +(__i)--)   \
>> > +   for_each_if ((__state)->planes[__i].ptr &&  \
>> > +((plane) = (__state)->planes[__i].ptr, \
>> > + (old_plane_state) = 
>> > (__state)->planes[__i].old_state,\
>> > + (new_plane_state) =
>> > +(__state)->planes[__i].new_state, 1)))
>> > +
>> > +/**
>> >   * for_each_old_plane_in_state - iterate over all planes in an atomic 
>> > update
>> >   * @__state:  drm_atomic_state pointer
>> >   * @plane:  drm_plane iteration cursor
>> > --
>> > 2.7.4
>> >
>> > ___
>> > amd-gfx mailing list
>> > amd-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>> ___
>> dri-devel mailing list
>> dri-de...@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[Tom St Denis]

I routinely rebase this patch on top of our amd-staging-drm-next tree at 
fdo.


https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next


Tom


On 03/06/2018 12:27 PM, KARBOWSKI Piotr wrote:

Hi,

On 2018-03-06 12:18, Tom St Denis wrote:

I believe this is the same issue I had which is a VGA handoff problem.

Can you try this patch the display team sent me?

Harry:  Will this patch be promoted in the next cycle?


What is the base for this patch? I cannot apply it on the top of any 
4.16-rc I try


     1 out of 4 hunks FAILED -- saving rejects to file 
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h.rej


is there any tree that contain this fix, that I can clone sources from?

-- Piotr.

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RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Li, Samuel]

> And exactly that's the problematical assumption.
Not assumption, I tested. You have any typical use case that it might become a 
problem?

> addition to that I agree with Michel that the module parameter is overkill.
That I already explained. Currently SG display feature needs to provide options 
for all kinds of use cases. All amd drivers so far provides options, and the 
default configuration is actually to allocate everything from GTT when 
possible. 

Regards,
Samuel Li


> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, March 06, 2018 12:12 PM
> To: Li, Samuel ; Alex Deucher
> 
> Cc: amd-gfx list 
> Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support
> 
> And exactly that's the problematical assumption.
> 
> This doesn't print only when the module is loaded, but rather when a
> framebuffer object is created.
> 
> And depending on the use case that can even be many many times per
> second.
> 
> Please remove that printing, addition to that I agree with Michel that the
> module parameter is overkill.
> 
> Regards,
> Christian.
> 
> Am 06.03.2018 um 18:09 schrieb Li, Samuel:
> > This information is kind of important, and it only prints once typically 
> > when
> module is loaded.
> >
> > Regards,
> > Samuel Li
> >
> >
> >> -Original Message-
> >> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> >> Sent: Tuesday, March 06, 2018 12:04 PM
> >> To: Li, Samuel 
> >> Cc: Koenig, Christian ; amd-gfx list  >> g...@lists.freedesktop.org>
> >> Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display
> >> support
> >>
> >> On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li  wrote:
> >domain = amdgpu_display_framebuffer_domains(adev);
> > +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
> > +DRM_INFO("Scatter gather display: enabled\n");
> > +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
> > +DRM_INFO("Scatter gather display: auto\n");
> > +}
>  Dito and printing that here is not a good idea as far as I can see.
> 
>  Christian.
> >>>
> >>> The intention here is to print out when fb is created. You have
> >>> other
> >> suggestions?
> >>
> >> Make it DRM_DEBUG?  otherwise you'll spam the logs.
> >>
> >>> Sam
> >>>
> >>>
> >>> On 2018-03-03 08:41 AM, Christian König wrote:
>  Am 03.03.2018 um 00:25 schrieb Samuel Li:
> > It's enabled by default. -1 is auto, to allow both vram and gtt
> > memory be available, for testing purpose only.
> > ---
> >drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> >drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
> >drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
> >drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
> >4 files changed, 17 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 292c7e7..6b0ee34 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
> >extern int amdgpu_compute_multipipe;
> >extern int amdgpu_gpu_recovery;
> >extern int amdgpu_emu_mode;
> > +extern int amdgpu_sg_display;
> >  #ifdef CONFIG_DRM_AMDGPU_SI
> >extern int amdgpu_si_support;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 5495b29..dfa11b1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -513,8 +513,13 @@ uint32_t
> >> amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
> >#if defined(CONFIG_DRM_AMD_DC)
> >if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
> >> CHIP_RAVEN &&
> >adev->flags & AMD_IS_APU &&
> > -amdgpu_device_asic_has_dc_support(adev->asic_type))
> > -domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +amdgpu_device_asic_has_dc_support(adev->asic_type)) {
> > +if (amdgpu_sg_display == 1) {
> > +domain = AMDGPU_GEM_DOMAIN_GTT;
> > +} else if (amdgpu_sg_display == -1) {
> > +domain |= AMDGPU_GEM_DOMAIN_GTT;
> > +}
>  Coding style, that if shouldn't use "{" and "}".
> 
> > +}
> >#endif
> >  return domain;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index e670936..f0ada24 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
> >int amdgpu_compute_multipipe = -1;
> >int 

Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Christian König]

And exactly that's the problematical assumption.

This doesn't print only when the module is loaded, but rather when a 
framebuffer object is created.


And depending on the use case that can even be many many times per second.

Please remove that printing, addition to that I agree with Michel that 
the module parameter is overkill.


Regards,
Christian.

Am 06.03.2018 um 18:09 schrieb Li, Samuel:

This information is kind of important, and it only prints once typically when 
module is loaded.

Regards,
Samuel Li



-Original Message-
From: Alex Deucher [mailto:alexdeuc...@gmail.com]
Sent: Tuesday, March 06, 2018 12:04 PM
To: Li, Samuel 
Cc: Koenig, Christian ; amd-gfx list 
Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li  wrote:

   domain = amdgpu_display_framebuffer_domains(adev);
+if (domain == AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: enabled\n");
+} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: auto\n");
+}

Dito and printing that here is not a good idea as far as I can see.

Christian.


The intention here is to print out when fb is created. You have other

suggestions?

Make it DRM_DEBUG?  otherwise you'll spam the logs.


Sam


On 2018-03-03 08:41 AM, Christian König wrote:

Am 03.03.2018 um 00:25 schrieb Samuel Li:

It's enabled by default. -1 is auto, to allow both vram and gtt
memory be available, for testing purpose only.
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
   4 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 292c7e7..6b0ee34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
   extern int amdgpu_compute_multipipe;
   extern int amdgpu_gpu_recovery;
   extern int amdgpu_emu_mode;
+extern int amdgpu_sg_display;
 #ifdef CONFIG_DRM_AMDGPU_SI
   extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 5495b29..dfa11b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -513,8 +513,13 @@ uint32_t

amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)

   #if defined(CONFIG_DRM_AMD_DC)
   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <

CHIP_RAVEN &&

   adev->flags & AMD_IS_APU &&
-amdgpu_device_asic_has_dc_support(adev->asic_type))
-domain |= AMDGPU_GEM_DOMAIN_GTT;
+amdgpu_device_asic_has_dc_support(adev->asic_type)) {
+if (amdgpu_sg_display == 1) {
+domain = AMDGPU_GEM_DOMAIN_GTT;
+} else if (amdgpu_sg_display == -1) {
+domain |= AMDGPU_GEM_DOMAIN_GTT;
+}

Coding style, that if shouldn't use "{" and "}".


+}
   #endif
 return domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e670936..f0ada24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
   int amdgpu_compute_multipipe = -1;
   int amdgpu_gpu_recovery = -1; /* auto */
   int amdgpu_emu_mode = 0;
+int amdgpu_sg_display = 1;
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in

megabytes");

   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@
-290,6 +291,9 @@ module_param_named(gpu_recovery,

amdgpu_gpu_recovery, int, 0444);

   MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 =

disable)");

   module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
   +MODULE_PARM_DESC(sg_display, "Enable scatter gather display, (1 =
enable, 0 = disable, -1 = auto");
+module_param_named(sg_display, amdgpu_sg_display, int, 0444);
+
   #ifdef CONFIG_DRM_AMDGPU_SI
 #if defined(CONFIG_DRM_RADEON) ||
defined(CONFIG_DRM_RADEON_MODULE) diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 1206301..10f1f4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -138,6 +138,11 @@ static int

amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,

   mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd-

width, cpp,

 fb_tiled);
   domain = amdgpu_display_framebuffer_domains(adev);
+if (domain == AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: enabled\n");
+} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+DRM_INFO("Scatter gather display: auto\n");
+}

Dito and printing 

RE: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Li, Samuel]

This information is kind of important, and it only prints once typically when 
module is loaded. 

Regards,
Samuel Li


> -Original Message-
> From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> Sent: Tuesday, March 06, 2018 12:04 PM
> To: Li, Samuel 
> Cc: Koenig, Christian ; amd-gfx list  g...@lists.freedesktop.org>
> Subject: Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support
> 
> On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li  wrote:
> >>>   domain = amdgpu_display_framebuffer_domains(adev);
> >>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
> >>> +DRM_INFO("Scatter gather display: enabled\n");
> >>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
> >>> +DRM_INFO("Scatter gather display: auto\n");
> >>> +}
> >>
> >> Dito and printing that here is not a good idea as far as I can see.
> >>
> >> Christian.
> >
> >
> > The intention here is to print out when fb is created. You have other
> suggestions?
> 
> Make it DRM_DEBUG?  otherwise you'll spam the logs.
> 
> >
> > Sam
> >
> >
> > On 2018-03-03 08:41 AM, Christian König wrote:
> >> Am 03.03.2018 um 00:25 schrieb Samuel Li:
> >>> It's enabled by default. -1 is auto, to allow both vram and gtt
> >>> memory be available, for testing purpose only.
> >>> ---
> >>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> >>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
> >>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
> >>>   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
> >>>   4 files changed, 17 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index 292c7e7..6b0ee34 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
> >>>   extern int amdgpu_compute_multipipe;
> >>>   extern int amdgpu_gpu_recovery;
> >>>   extern int amdgpu_emu_mode;
> >>> +extern int amdgpu_sg_display;
> >>> #ifdef CONFIG_DRM_AMDGPU_SI
> >>>   extern int amdgpu_si_support;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> index 5495b29..dfa11b1 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> >>> @@ -513,8 +513,13 @@ uint32_t
> amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
> >>>   #if defined(CONFIG_DRM_AMD_DC)
> >>>   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
> CHIP_RAVEN &&
> >>>   adev->flags & AMD_IS_APU &&
> >>> -amdgpu_device_asic_has_dc_support(adev->asic_type))
> >>> -domain |= AMDGPU_GEM_DOMAIN_GTT;
> >>> +amdgpu_device_asic_has_dc_support(adev->asic_type)) {
> >>> +if (amdgpu_sg_display == 1) {
> >>> +domain = AMDGPU_GEM_DOMAIN_GTT;
> >>> +} else if (amdgpu_sg_display == -1) {
> >>> +domain |= AMDGPU_GEM_DOMAIN_GTT;
> >>> +}
> >>
> >> Coding style, that if shouldn't use "{" and "}".
> >>
> >>> +}
> >>>   #endif
> >>> return domain;
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> index e670936..f0ada24 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >>> @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
> >>>   int amdgpu_compute_multipipe = -1;
> >>>   int amdgpu_gpu_recovery = -1; /* auto */
> >>>   int amdgpu_emu_mode = 0;
> >>> +int amdgpu_sg_display = 1;
> >>> MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in
> megabytes");
> >>>   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@
> >>> -290,6 +291,9 @@ module_param_named(gpu_recovery,
> amdgpu_gpu_recovery, int, 0444);
> >>>   MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 =
> disable)");
> >>>   module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
> >>>   +MODULE_PARM_DESC(sg_display, "Enable scatter gather display, (1 =
> >>> enable, 0 = disable, -1 = auto");
> >>> +module_param_named(sg_display, amdgpu_sg_display, int, 0444);
> >>> +
> >>>   #ifdef CONFIG_DRM_AMDGPU_SI
> >>> #if defined(CONFIG_DRM_RADEON) ||
> >>> defined(CONFIG_DRM_RADEON_MODULE) diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> >>> index 1206301..10f1f4f 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> >>> @@ -138,6 +138,11 @@ static int
> amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
> >>>   mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd-
> >width, cpp,
> >>> fb_tiled);
> >>>   domain = amdgpu_display_framebuffer_domains(adev);
> >>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
> >>> +DRM_INFO("Scatter 

Re: [PATCH xf86-video-amdgpu] Only change Set/MoveCursor hooks from what we expect

[Alex Deucher]

On Tue, Mar 6, 2018 at 12:02 PM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> Since xf86CursorCloseScreen runs after AMDGPUCloseScreen_KMS,
> PointPriv->spriteFuncs doesn't point to the same struct in the latter as
> in AMDGPUCursorInit_KMS. So we were restoring info->Set/MoveCursor to
> the wrong struct. Then in the next server generation,
> info->Set/MoveCursor would end up pointing to
> drmmode_sprite_set/move_cursor, resulting in an infinite loop if one of
> them was called.
>
> To avoid this, only change the Set/MoveCursor hooks if their values
> match our expectations, otherwise leave them as is. This is kind of a
> hack, but the alternative would be invasive and thus risky changes to
> the way we're wrapping CloseScreen, and it's not even clear that can
> work without changing xserver code.
>
> Fixes: 69e20839bfeb ("Keep track of how many SW cursors are visible on
>   each screen")
> (Ported from radeon commit 504b8721b17a672caf1ed3eab087027c02458cab)
>
> Signed-off-by: Michel Dänzer 

Acked-by: Alex Deucher 

> ---
>  src/amdgpu_kms.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index e1aae9952..90e1f2531 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -1551,10 +1551,12 @@ static Bool AMDGPUCursorInit_KMS(ScreenPtr pScreen)
> return FALSE;
> }
>
> -   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
> -   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
> -   PointPriv->spriteFuncs->SetCursor = drmmode_sprite_set_cursor;
> -   PointPriv->spriteFuncs->MoveCursor = 
> drmmode_sprite_move_cursor;
> +   if (PointPriv->spriteFuncs->SetCursor != 
> drmmode_sprite_set_cursor) {
> +   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
> +   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
> +   PointPriv->spriteFuncs->SetCursor = 
> drmmode_sprite_set_cursor;
> +   PointPriv->spriteFuncs->MoveCursor = 
> drmmode_sprite_move_cursor;
> +   }
> }
>
> if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE))
> @@ -1731,8 +1733,10 @@ static Bool AMDGPUCloseScreen_KMS(ScreenPtr pScreen)
> miPointerScreenPtr PointPriv =
> dixLookupPrivate(>devPrivates, 
> miPointerScreenKey);
>
> -   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
> -   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
> +   if (PointPriv->spriteFuncs->SetCursor == 
> drmmode_sprite_set_cursor) {
> +   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
> +   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
> +   }
> }
>
> pScreen->BlockHandler = info->BlockHandler;
> --
> 2.16.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Alex Deucher]

On Tue, Mar 6, 2018 at 11:49 AM, Samuel Li  wrote:
>>>   domain = amdgpu_display_framebuffer_domains(adev);
>>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Scatter gather display: enabled\n");
>>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Scatter gather display: auto\n");
>>> +}
>>
>> Dito and printing that here is not a good idea as far as I can see.
>>
>> Christian.
>
>
> The intention here is to print out when fb is created. You have other 
> suggestions?

Make it DRM_DEBUG?  otherwise you'll spam the logs.

>
> Sam
>
>
> On 2018-03-03 08:41 AM, Christian König wrote:
>> Am 03.03.2018 um 00:25 schrieb Samuel Li:
>>> It's enabled by default. -1 is auto, to allow both vram and gtt
>>> memory be available, for testing purpose only.
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
>>>   4 files changed, 17 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 292c7e7..6b0ee34 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
>>>   extern int amdgpu_compute_multipipe;
>>>   extern int amdgpu_gpu_recovery;
>>>   extern int amdgpu_emu_mode;
>>> +extern int amdgpu_sg_display;
>>> #ifdef CONFIG_DRM_AMDGPU_SI
>>>   extern int amdgpu_si_support;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> index 5495b29..dfa11b1 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> @@ -513,8 +513,13 @@ uint32_t amdgpu_display_framebuffer_domains(struct 
>>> amdgpu_device *adev)
>>>   #if defined(CONFIG_DRM_AMD_DC)
>>>   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
>>>   adev->flags & AMD_IS_APU &&
>>> -amdgpu_device_asic_has_dc_support(adev->asic_type))
>>> -domain |= AMDGPU_GEM_DOMAIN_GTT;
>>> +amdgpu_device_asic_has_dc_support(adev->asic_type)) {
>>> +if (amdgpu_sg_display == 1) {
>>> +domain = AMDGPU_GEM_DOMAIN_GTT;
>>> +} else if (amdgpu_sg_display == -1) {
>>> +domain |= AMDGPU_GEM_DOMAIN_GTT;
>>> +}
>>
>> Coding style, that if shouldn't use "{" and "}".
>>
>>> +}
>>>   #endif
>>> return domain;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> index e670936..f0ada24 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
>>>   int amdgpu_compute_multipipe = -1;
>>>   int amdgpu_gpu_recovery = -1; /* auto */
>>>   int amdgpu_emu_mode = 0;
>>> +int amdgpu_sg_display = 1;
>>> MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>>>   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
>>> @@ -290,6 +291,9 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, 
>>> int, 0444);
>>>   MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
>>>   module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
>>>   +MODULE_PARM_DESC(sg_display, "Enable scatter gather display, (1 = 
>>> enable, 0 = disable, -1 = auto");
>>> +module_param_named(sg_display, amdgpu_sg_display, int, 0444);
>>> +
>>>   #ifdef CONFIG_DRM_AMDGPU_SI
>>> #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>>> index 1206301..10f1f4f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>>> @@ -138,6 +138,11 @@ static int amdgpufb_create_pinned_object(struct 
>>> amdgpu_fbdev *rfbdev,
>>>   mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
>>> fb_tiled);
>>>   domain = amdgpu_display_framebuffer_domains(adev);
>>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Scatter gather display: enabled\n");
>>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>>> +DRM_INFO("Scatter gather display: auto\n");
>>> +}
>>
>> Dito and printing that here is not a good idea as far as I can see.
>>
>> Christian.
>>
>>> height = ALIGN(mode_cmd->height, 8);
>>>   size = mode_cmd->pitches[0] * height;
>>
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[PATCH xf86-video-amdgpu] Only change Set/MoveCursor hooks from what we expect

[Michel Dänzer]

From: Michel Dänzer 

Since xf86CursorCloseScreen runs after AMDGPUCloseScreen_KMS,
PointPriv->spriteFuncs doesn't point to the same struct in the latter as
in AMDGPUCursorInit_KMS. So we were restoring info->Set/MoveCursor to
the wrong struct. Then in the next server generation,
info->Set/MoveCursor would end up pointing to
drmmode_sprite_set/move_cursor, resulting in an infinite loop if one of
them was called.

To avoid this, only change the Set/MoveCursor hooks if their values
match our expectations, otherwise leave them as is. This is kind of a
hack, but the alternative would be invasive and thus risky changes to
the way we're wrapping CloseScreen, and it's not even clear that can
work without changing xserver code.

Fixes: 69e20839bfeb ("Keep track of how many SW cursors are visible on
  each screen")
(Ported from radeon commit 504b8721b17a672caf1ed3eab087027c02458cab)

Signed-off-by: Michel Dänzer 
---
 src/amdgpu_kms.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index e1aae9952..90e1f2531 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -1551,10 +1551,12 @@ static Bool AMDGPUCursorInit_KMS(ScreenPtr pScreen)
return FALSE;
}
 
-   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
-   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
-   PointPriv->spriteFuncs->SetCursor = drmmode_sprite_set_cursor;
-   PointPriv->spriteFuncs->MoveCursor = drmmode_sprite_move_cursor;
+   if (PointPriv->spriteFuncs->SetCursor != 
drmmode_sprite_set_cursor) {
+   info->SetCursor = PointPriv->spriteFuncs->SetCursor;
+   info->MoveCursor = PointPriv->spriteFuncs->MoveCursor;
+   PointPriv->spriteFuncs->SetCursor = 
drmmode_sprite_set_cursor;
+   PointPriv->spriteFuncs->MoveCursor = 
drmmode_sprite_move_cursor;
+   }
}
 
if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE))
@@ -1731,8 +1733,10 @@ static Bool AMDGPUCloseScreen_KMS(ScreenPtr pScreen)
miPointerScreenPtr PointPriv =
dixLookupPrivate(>devPrivates, 
miPointerScreenKey);
 
-   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
-   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
+   if (PointPriv->spriteFuncs->SetCursor == 
drmmode_sprite_set_cursor) {
+   PointPriv->spriteFuncs->SetCursor = info->SetCursor;
+   PointPriv->spriteFuncs->MoveCursor = info->MoveCursor;
+   }
}
 
pScreen->BlockHandler = info->BlockHandler;
-- 
2.16.2

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Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[Harry Wentland]

On 2018-03-06 11:13 AM, Alex Deucher wrote:
> On Tue, Mar 6, 2018 at 6:18 AM, Tom St Denis  wrote:
>> I believe this is the same issue I had which is a VGA handoff problem.
>>
>> Can you try this patch the display team sent me?
>>
>> Harry:  Will this patch be promoted in the next cycle?
> 
> I think it will eventually.  IIRC, there were some regressions with it
> that are still being worked out.
> 

Should be in next set of DC patches.

Harry

> Alex
> 
>>
>> Tom
>>
>>
>> On 03/05/2018 11:40 AM, KARBOWSKI Piotr wrote:
>>>
>>> Hi list,
>>>
>>> I'd like to report a very odd screen artifacts while running both
>>> 4.16-rc3, as well as latest 4.16-rc4 with git linux-firmware.
>>>
>>> I am using Ryzen 2400G with the integrate Vega.
>>>
>>> I am aware that RAVEN support is yet to be finished, however I've read
>>> that some people do run it already, so I figured I will report the issues,
>>> since other does not seems to hit it.
>>>
>>> I have amdgpu and all it's symbols built into the kernel image, and the
>>> firmware added to initrammfs. The moment modesetting is initializing I can
>>> see that native screen resolution goes, however, I can see only like 25% of
>>> the screen and this very top-left 25% of screen is duplicated to top-right.
>>> While the bottom half of screen is either black or have lines, usually gray,
>>> unless some text on screen had another color then it's green, blue, etc.
>>>
>>> Screenshots:
>>>
>>>  https://i.imgur.com/qnDOKY7.jpg
>>>  https://i.imgur.com/XH42zit.jpg
>>>
>>> The AMD symbols that I've enabled in kernel:
>>>
>>>  CONFIG_CPU_SUP_AMD=y
>>>  CONFIG_X86_MCE_AMD=y
>>>  CONFIG_AMD_NB=y
>>>  CONFIG_NET_VENDOR_AMD=y
>>>  CONFIG_DRM_AMDGPU=y
>>>  CONFIG_DRM_AMDGPU_SI=y
>>>  CONFIG_DRM_AMDGPU_CIK=y
>>>  CONFIG_DRM_AMD_ACP=y
>>>  CONFIG_DRM_AMD_DC=y
>>>  CONFIG_DRM_AMD_DC_FBC=y
>>>  CONFIG_DRM_AMD_DC_DCN1_0=y
>>>  CONFIG_HSA_AMD=y
>>>  CONFIG_AMD_IOMMU=y
>>>  CONFIG_AMD_IOMMU_V2=y
>>>
>>> The kernel log that had either drm, amd or firmware in there:
>>>
>>>  [0.00] RAMDISK: [mem 0x7f88c000-0x7fff]
>>>  [0.00] ACPI: SSDT 0x9BD94908 005367 (v02 AMD AmdTable
>>> 0002 MSFT 0202)
>>>  [0.00] ACPI: SSDT 0x9BD99C70 00119C (v01 AMDAMD
>>> CPU  0001 AMD  0001)
>>>  [0.00] ACPI: CRAT 0x9BD9AE10 000810 (v01 AMDAMD
>>> CRAT 0001 AMD  0001)
>>>  [0.00] ACPI: CDIT 0x9BD9B620 29 (v01 AMDAMD
>>> CDIT 0001 AMD  0001)
>>>  [0.00] ACPI: SSDT 0x9BD9B650 002E6E (v01 AMDAMD
>>> AOD  0001 INTL 20120913)
>>>  [0.00] ACPI: IVRS 0x9BD9E580 D0 (v02 AMDAMD
>>> IVRS 0001 AMD  )
>>>  [0.00] ACPI: SSDT 0x9BD9E650 F8 (v01 AMDAMD
>>> PT   1000 INTL 20120913)
>>>  [0.00] ACPI: SSDT 0x9BD9E748 000E96 (v01 AMD AmdTable
>>> 0001 INTL 20120913)
>>>  [0.00] ACPI: SSDT 0x9BD9F5E0 000850 (v01 AMD AmdTable
>>> 0001 INTL 20120913)
>>>  [0.00] ACPI: SSDT 0x9BD9FE30 001993 (v01 AMD AmdTable
>>> 0001 INTL 20120913)
>>>  [0.00] Kernel command line: BOOT_IMAGE=/bzImage-4.16.0-rc4
>>> rootfstype=ext4 luks enc_root=/dev/sda2 lvm root=/dev/mapper/megumin-rootfs
>>> initrd=/initramfs.cpio.gz,/firmware-initramfs.cpio.gz
>>>  [0.00] ACPI Error: AE_ALREADY_EXISTS, (SSDT:  AMD PT) while
>>> loading table (20180105/tbxfload-228)
>>>  [0.08] smpboot: CPU0: AMD Ryzen 5 2400G with Radeon Vega
>>> Graphics (family: 0x17, model: 0x11, stepping: 0x0)
>>>  [0.08] Performance Events: Fam17h core perfctr, AMD PMU
>>> driver.
>>>  [0.101786] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>>>  [0.615782] AMD-Vi: IOMMU performance counters supported
>>>  [0.623179] AMD-Vi: Found IOMMU at :00:00.2 cap 0x40
>>>  [0.623314] AMD-Vi: Extended features (0x4f77ef22294ada):
>>>  [0.623684] AMD-Vi: Lazy IO/TLB flushing enabled
>>>  [0.624533] amd_uncore: AMD NB counters detected
>>>  [0.624666] amd_uncore: AMD LLC counters detected
>>>  [0.625076] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4
>>> counters/bank).
>>>  [0.636229] AMD IOMMUv2 driver by Joerg Roedel 
>>>  [0.637179] [drm] amdgpu kernel modesetting enabled.
>>>  [0.637409] [drm] initializing kernel modesetting (RAVEN
>>> 0x1002:0x15DD 0x1458:0xD000 0xC6).
>>>  [0.637583] [drm] register mmio base: 0xFE50
>>>  [0.637709] [drm] register mmio size: 524288
>>>  [0.637852] [drm] probing gen 2 caps for device 1022:15db =
>>> 700d03/e
>>>  [0.638005] [drm] probing mlw for device 1022:15db = 700d03
>>>  [0.638213] [drm] VCN decode is enabled in VM mode
>>>  [0.638341] [drm] VCN encode is enabled in 

Re: [PATCH 1/2] drm/amdgpu: Enable scatter gather display support

[Samuel Li]

>>   domain = amdgpu_display_framebuffer_domains(adev);
>> +if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>> +DRM_INFO("Scatter gather display: enabled\n");
>> +} else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>> +DRM_INFO("Scatter gather display: auto\n");
>> +}
> 
> Dito and printing that here is not a good idea as far as I can see.
> 
> Christian.


The intention here is to print out when fb is created. You have other 
suggestions?

Sam


On 2018-03-03 08:41 AM, Christian König wrote:
> Am 03.03.2018 um 00:25 schrieb Samuel Li:
>> It's enabled by default. -1 is auto, to allow both vram and gtt
>> memory be available, for testing purpose only.
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 5 +
>>   4 files changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 292c7e7..6b0ee34 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
>>   extern int amdgpu_compute_multipipe;
>>   extern int amdgpu_gpu_recovery;
>>   extern int amdgpu_emu_mode;
>> +extern int amdgpu_sg_display;
>>     #ifdef CONFIG_DRM_AMDGPU_SI
>>   extern int amdgpu_si_support;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index 5495b29..dfa11b1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -513,8 +513,13 @@ uint32_t amdgpu_display_framebuffer_domains(struct 
>> amdgpu_device *adev)
>>   #if defined(CONFIG_DRM_AMD_DC)
>>   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
>>   adev->flags & AMD_IS_APU &&
>> -    amdgpu_device_asic_has_dc_support(adev->asic_type))
>> -    domain |= AMDGPU_GEM_DOMAIN_GTT;
>> +    amdgpu_device_asic_has_dc_support(adev->asic_type)) {
>> +    if (amdgpu_sg_display == 1) {
>> +    domain = AMDGPU_GEM_DOMAIN_GTT;
>> +    } else if (amdgpu_sg_display == -1) {
>> +    domain |= AMDGPU_GEM_DOMAIN_GTT;
>> +    }
> 
> Coding style, that if shouldn't use "{" and "}".
> 
>> +    }
>>   #endif
>>     return domain;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index e670936..f0ada24 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;
>>   int amdgpu_compute_multipipe = -1;
>>   int amdgpu_gpu_recovery = -1; /* auto */
>>   int amdgpu_emu_mode = 0;
>> +int amdgpu_sg_display = 1;
>>     MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>>   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
>> @@ -290,6 +291,9 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, 
>> int, 0444);
>>   MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
>>   module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
>>   +MODULE_PARM_DESC(sg_display, "Enable scatter gather display, (1 = enable, 
>> 0 = disable, -1 = auto");
>> +module_param_named(sg_display, amdgpu_sg_display, int, 0444);
>> +
>>   #ifdef CONFIG_DRM_AMDGPU_SI
>>     #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>> index 1206301..10f1f4f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>> @@ -138,6 +138,11 @@ static int amdgpufb_create_pinned_object(struct 
>> amdgpu_fbdev *rfbdev,
>>   mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
>>     fb_tiled);
>>   domain = amdgpu_display_framebuffer_domains(adev);
>> +    if (domain == AMDGPU_GEM_DOMAIN_GTT) {
>> +    DRM_INFO("Scatter gather display: enabled\n");
>> +    } else if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>> +    DRM_INFO("Scatter gather display: auto\n");
>> +    }
> 
> Dito and printing that here is not a good idea as far as I can see.
> 
> Christian.
> 
>>     height = ALIGN(mode_cmd->height, 8);
>>   size = mode_cmd->pitches[0] * height;
> 
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Re: [PATCH 1/4] drm/amd/pp: Replace files name rv_* with smu10_*

[Alex Deucher]

On Tue, Mar 6, 2018 at 5:10 AM, Rex Zhu  wrote:
> Powerplay is for the hw ip smu, for RV, smu10 is used,
> so use smu10 as the prefix of the files name.
>
> Change-Id: Icf9c8a9d4b5deccd4fbfb9ecfab443db79934c77
> Signed-off-by: Rex Zhu 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 1075 ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  322 --
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  | 1076 
> 
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h  |  322 ++
>  drivers/gpu/drm/amd/powerplay/smumgr/Makefile  |2 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   |  399 
>  drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h   |   61 --
>  .../gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c|  399 
>  .../gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h|   61 ++
>  10 files changed, 1860 insertions(+), 1859 deletions(-)
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
>  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
>  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
>  delete mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
>  create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
>  create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.h


I'm ok with patches 1-3, although I think we should work on renaming
the functions eventually too to match the file names.  For patch 4, I
think we should stick with the asic names.  The smu7 variants are too
confusing.  I can't remember if CI was 7.0.1 or 7.0.2, etc.  I'd
prefer to align the file names to the smu interface headers (e.g.,
smu7, smu71, smu72, smu73, smu74).  BTW, did you use git mv to
generate these patches?

Alex
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Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[Alex Deucher]

On Tue, Mar 6, 2018 at 6:18 AM, Tom St Denis  wrote:
> I believe this is the same issue I had which is a VGA handoff problem.
>
> Can you try this patch the display team sent me?
>
> Harry:  Will this patch be promoted in the next cycle?

I think it will eventually.  IIRC, there were some regressions with it
that are still being worked out.

Alex

>
> Tom
>
>
> On 03/05/2018 11:40 AM, KARBOWSKI Piotr wrote:
>>
>> Hi list,
>>
>> I'd like to report a very odd screen artifacts while running both
>> 4.16-rc3, as well as latest 4.16-rc4 with git linux-firmware.
>>
>> I am using Ryzen 2400G with the integrate Vega.
>>
>> I am aware that RAVEN support is yet to be finished, however I've read
>> that some people do run it already, so I figured I will report the issues,
>> since other does not seems to hit it.
>>
>> I have amdgpu and all it's symbols built into the kernel image, and the
>> firmware added to initrammfs. The moment modesetting is initializing I can
>> see that native screen resolution goes, however, I can see only like 25% of
>> the screen and this very top-left 25% of screen is duplicated to top-right.
>> While the bottom half of screen is either black or have lines, usually gray,
>> unless some text on screen had another color then it's green, blue, etc.
>>
>> Screenshots:
>>
>>  https://i.imgur.com/qnDOKY7.jpg
>>  https://i.imgur.com/XH42zit.jpg
>>
>> The AMD symbols that I've enabled in kernel:
>>
>>  CONFIG_CPU_SUP_AMD=y
>>  CONFIG_X86_MCE_AMD=y
>>  CONFIG_AMD_NB=y
>>  CONFIG_NET_VENDOR_AMD=y
>>  CONFIG_DRM_AMDGPU=y
>>  CONFIG_DRM_AMDGPU_SI=y
>>  CONFIG_DRM_AMDGPU_CIK=y
>>  CONFIG_DRM_AMD_ACP=y
>>  CONFIG_DRM_AMD_DC=y
>>  CONFIG_DRM_AMD_DC_FBC=y
>>  CONFIG_DRM_AMD_DC_DCN1_0=y
>>  CONFIG_HSA_AMD=y
>>  CONFIG_AMD_IOMMU=y
>>  CONFIG_AMD_IOMMU_V2=y
>>
>> The kernel log that had either drm, amd or firmware in there:
>>
>>  [0.00] RAMDISK: [mem 0x7f88c000-0x7fff]
>>  [0.00] ACPI: SSDT 0x9BD94908 005367 (v02 AMD AmdTable
>> 0002 MSFT 0202)
>>  [0.00] ACPI: SSDT 0x9BD99C70 00119C (v01 AMDAMD
>> CPU  0001 AMD  0001)
>>  [0.00] ACPI: CRAT 0x9BD9AE10 000810 (v01 AMDAMD
>> CRAT 0001 AMD  0001)
>>  [0.00] ACPI: CDIT 0x9BD9B620 29 (v01 AMDAMD
>> CDIT 0001 AMD  0001)
>>  [0.00] ACPI: SSDT 0x9BD9B650 002E6E (v01 AMDAMD
>> AOD  0001 INTL 20120913)
>>  [0.00] ACPI: IVRS 0x9BD9E580 D0 (v02 AMDAMD
>> IVRS 0001 AMD  )
>>  [0.00] ACPI: SSDT 0x9BD9E650 F8 (v01 AMDAMD
>> PT   1000 INTL 20120913)
>>  [0.00] ACPI: SSDT 0x9BD9E748 000E96 (v01 AMD AmdTable
>> 0001 INTL 20120913)
>>  [0.00] ACPI: SSDT 0x9BD9F5E0 000850 (v01 AMD AmdTable
>> 0001 INTL 20120913)
>>  [0.00] ACPI: SSDT 0x9BD9FE30 001993 (v01 AMD AmdTable
>> 0001 INTL 20120913)
>>  [0.00] Kernel command line: BOOT_IMAGE=/bzImage-4.16.0-rc4
>> rootfstype=ext4 luks enc_root=/dev/sda2 lvm root=/dev/mapper/megumin-rootfs
>> initrd=/initramfs.cpio.gz,/firmware-initramfs.cpio.gz
>>  [0.00] ACPI Error: AE_ALREADY_EXISTS, (SSDT:  AMD PT) while
>> loading table (20180105/tbxfload-228)
>>  [0.08] smpboot: CPU0: AMD Ryzen 5 2400G with Radeon Vega
>> Graphics (family: 0x17, model: 0x11, stepping: 0x0)
>>  [0.08] Performance Events: Fam17h core perfctr, AMD PMU
>> driver.
>>  [0.101786] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>>  [0.615782] AMD-Vi: IOMMU performance counters supported
>>  [0.623179] AMD-Vi: Found IOMMU at :00:00.2 cap 0x40
>>  [0.623314] AMD-Vi: Extended features (0x4f77ef22294ada):
>>  [0.623684] AMD-Vi: Lazy IO/TLB flushing enabled
>>  [0.624533] amd_uncore: AMD NB counters detected
>>  [0.624666] amd_uncore: AMD LLC counters detected
>>  [0.625076] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4
>> counters/bank).
>>  [0.636229] AMD IOMMUv2 driver by Joerg Roedel 
>>  [0.637179] [drm] amdgpu kernel modesetting enabled.
>>  [0.637409] [drm] initializing kernel modesetting (RAVEN
>> 0x1002:0x15DD 0x1458:0xD000 0xC6).
>>  [0.637583] [drm] register mmio base: 0xFE50
>>  [0.637709] [drm] register mmio size: 524288
>>  [0.637852] [drm] probing gen 2 caps for device 1022:15db =
>> 700d03/e
>>  [0.638005] [drm] probing mlw for device 1022:15db = 700d03
>>  [0.638213] [drm] VCN decode is enabled in VM mode
>>  [0.638341] [drm] VCN encode is enabled in VM mode
>>  [0.660265] [drm] BIOS signature incorrect 74 7
>>  [0.660422] [drm] vm size is 262144 GB, 4 levels, block size is
>> 9-bit, fragment size is 9-bit
>>  [0.660515] amdgpu 

Re: [PATCH] drm/amd/pp: Add #ifdef checks for CONFIG_ACPI

[Deucher, Alexander]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Tuesday, March 6, 2018 1:47:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Add #ifdef checks for CONFIG_ACPI

Fix compiling error when CONFIG_ACPI not enabled.

Change-Id: I20d3f55bbd2ad68e65363cde7452802b063643f0
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c  | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 8a37c80..aa83114 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -902,8 +902,10 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_UVDDPM);
 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_VCEDPM);

+#if defined(CONFIG_ACPI)
 if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_PCIEPerformanceRequest);
+#endif

 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 PHM_PlatformCaps_DynamicPatchPowerState);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 62ebe15..4f26014 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3596,6 +3596,7 @@ static int 
smu7_request_link_speed_change_before_state_change(

 if (target_link_speed > current_link_speed) {
 switch (target_link_speed) {
+#ifdef CONFIG_ACPI
 case PP_PCIEGen3:
 if (0 == 
amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
 break;
@@ -3605,6 +3606,7 @@ static int 
smu7_request_link_speed_change_before_state_change(
 case PP_PCIEGen2:
 if (0 == 
amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
 break;
+#endif
 default:
 data->force_pcie_gen = 
smu7_get_current_pcie_speed(hwmgr);
 break;
--
1.9.1

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RE: [PATCH] drm/atomic: Add new reverse iterator over all plane state

[Vishwakarma, Pratik]

Below mail was rejected, maybe due to attachment. Sending again without 
attachment.

Regards
Pratik

-Original Message-
From: Vishwakarma, Pratik 
Sent: Tuesday, March 6, 2018 4:22 PM
To: 'Daniel Vetter' ; Alex Deucher 
Cc: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org; Maling list - DRI developers 
; S, Shirish 
Subject: RE: [PATCH] drm/atomic: Add new reverse iterator over all plane state

Hi Daniel,

I have checked make htmldocs on v2 of this patch. I have attached output 
drm-kms.html on that thread.
No indentation issue is observed. Attached again for reference.
Can you please provide RB on that?

Regards
Pratik

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Daniel Vetter
Sent: Tuesday, March 6, 2018 3:36 PM
To: Alex Deucher 
Cc: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org; Maling list - DRI developers 
; S, Shirish 
Subject: Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state

On Wed, Feb 28, 2018 at 09:26:26AM -0500, Alex Deucher wrote:
> + dri-devel
> 
> 
> On Wed, Feb 28, 2018 at 4:33 AM, S, Shirish  wrote:
> > From: Shirish S 
> >
> > Add reverse iterator "for_each_oldnew_plane_in_state_reverse" to 
> > complement "for_each_oldnew_plane_in_state" way of reading plane 
> > states.
> >
> > The plane states are required to be read in reverse order for 
> > amdgpu, as the z order convention followed in linux is opposite to 
> > how the planes are supposed to be presented to DC engine, which is 
> > in common to both windows and linux.
> >
> > Signed-off-by: Shirish S 
> > Signed-off-by: Pratik Vishwakarma 

Makes sense.
> > ---
> >  include/drm/drm_atomic.h | 22 ++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h 
> > index cf13842..b947930 100644
> > --- a/include/drm/drm_atomic.h
> > +++ b/include/drm/drm_atomic.h
> > @@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct 
> > drm_printer *p);
> >   (new_plane_state) = 
> > (__state)->planes[__i].new_state, 1))
> >
> >  /**
> > + * for_each_oldnew_plane_in_state_reverse - iterate over all planes 
> > + in an atomic
> > + * update in reverse order

Are you sure this renders correctly in kernel-doc? Iirc you have to indent the 
continuation line.

Assuming this is fixed:

Reviewed-by: Daniel Vetter 

> > + * @__state:  drm_atomic_state pointer
> > + * @plane:  drm_plane iteration cursor
> > + * @old_plane_state:  drm_plane_state iteration cursor for 
> > +the old state
> > + * @new_plane_state:  drm_plane_state iteration cursor for 
> > +the new state
> > + * @__i: int iteration cursor, for macro-internal use
> > + *
> > + * This iterates over all planes in an atomic update in reverse 
> > +order,
> > + * tracking both old and  new state. This is useful in places where 
> > +the
> > + * state delta needs to be considered, for example in atomic check 
> > functions.
> > + */
> > +#define for_each_oldnew_plane_in_state_reverse(__state, plane, 
> > old_plane_state, new_plane_state, __i) \
> > +   (for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1);
> > \
> > +(__i) >= 0;\
> > +(__i)--)   \
> > +   for_each_if ((__state)->planes[__i].ptr &&  \
> > +((plane) = (__state)->planes[__i].ptr, \
> > + (old_plane_state) = 
> > (__state)->planes[__i].old_state,\
> > + (new_plane_state) = 
> > +(__state)->planes[__i].new_state, 1)))
> > +
> > +/**
> >   * for_each_old_plane_in_state - iterate over all planes in an atomic 
> > update
> >   * @__state:  drm_atomic_state pointer
> >   * @plane:  drm_plane iteration cursor
> > --
> > 2.7.4
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 3/6] drm/ttm: move initializing ttm->sg into ttm_tt_init_fields

[Christian König]

Better to set this with all other fields as well.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_tt.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 65976238d24b..7e672be987b5 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -77,9 +77,6 @@ int ttm_tt_create(struct ttm_buffer_object *bo, bool 
zero_alloc)
if (unlikely(bo->ttm == NULL))
return -ENOMEM;
 
-   if (bo->type == ttm_bo_type_sg)
-   bo->ttm->sg = bo->sg;
-
return 0;
 }
 
@@ -245,6 +242,7 @@ void ttm_tt_init_fields(struct ttm_tt *ttm, struct 
ttm_buffer_object *bo,
ttm->page_flags = page_flags;
ttm->state = tt_unpopulated;
ttm->swap_storage = NULL;
+   ttm->sg = bo->sg;
 }
 
 int ttm_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo,
-- 
2.14.1

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[PATCH 1/6] drm/ttm: add ttm_bo_pipeline_gutting

[Christian König]

Allows us to gut a BO of it's backing store when the driver says that it
isn't needed any more.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_bo.c  | 15 ---
 drivers/gpu/drm/ttm/ttm_bo_util.c | 24 
 include/drm/ttm/ttm_bo_driver.h   |  9 +
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index ad142a92eb80..98e06f8bf23b 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -622,14 +622,23 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
 
reservation_object_assert_held(bo->resv);
 
+   placement.num_placement = 0;
+   placement.num_busy_placement = 0;
+   bdev->driver->evict_flags(bo, );
+
+   if (!placement.num_placement && !placement.num_busy_placement) {
+   ret = ttm_bo_pipeline_gutting(bo);
+   if (ret)
+   return ret;
+
+   return ttm_tt_create(bo, false);
+   }
+
evict_mem = bo->mem;
evict_mem.mm_node = NULL;
evict_mem.bus.io_reserved_vm = false;
evict_mem.bus.io_reserved_count = 0;
 
-   placement.num_placement = 0;
-   placement.num_busy_placement = 0;
-   bdev->driver->evict_flags(bo, );
ret = ttm_bo_mem_space(bo, , _mem, ctx);
if (ret) {
if (ret != -ERESTARTSYS) {
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 6d6a3f46143b..1f730b3f18e5 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -801,3 +801,27 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
return 0;
 }
 EXPORT_SYMBOL(ttm_bo_pipeline_move);
+
+int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo)
+{
+   struct ttm_buffer_object *ghost;
+   int ret;
+
+   ret = ttm_buffer_object_transfer(bo, );
+   if (ret)
+   return ret;
+
+   ret = reservation_object_copy_fences(ghost->resv, bo->resv);
+   /* Last resort, wait for the BO to be idle when we are OOM */
+   if (ret)
+   ttm_bo_wait(bo, false, false);
+
+   memset(>mem, 0, sizeof(bo->mem));
+   bo->mem.mem_type = TTM_PL_SYSTEM;
+   bo->ttm = NULL;
+
+   ttm_bo_unreserve(ghost);
+   ttm_bo_unref();
+
+   return 0;
+}
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index f8e2515b401f..39cd6b086d3a 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -849,6 +849,15 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
 struct dma_fence *fence, bool evict,
 struct ttm_mem_reg *new_mem);
 
+/**
+ * ttm_bo_pipeline_gutting.
+ *
+ * @bo: A pointer to a struct ttm_buffer_object.
+ *
+ * Pipelined gutting a BO of it's backing store.
+ */
+int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo);
+
 /**
  * ttm_io_prot
  *
-- 
2.14.1

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[PATCH 4/6] drm/amdgpu: drop the backing store when DMA-buf imports are evicted

[Christian König]

Instead of moving this to the SYSTEM domain just drop the backing store
and let the resulting allocation be freed.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 44ae2c60c9d4..eebc9f77b611 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -203,6 +203,12 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
*bo,
.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
};
 
+   if (bo->type == ttm_bo_type_sg) {
+   placement->num_placement = 0;
+   placement->num_busy_placement = 0;
+   return;
+   }
+
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
placement->placement = 
placement->busy_placement = 
-- 
2.14.1

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[PATCH 6/6] drm/amdgpu: explicit give BO type to amdgpu_bo_create

[Christian König]

Drop the "kernel" and sg parameter and give the BO type to create
explicit to amdgpu_bo_create instead of figuring it out from the
parameters.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|  5 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c |  8 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c  |  7 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  6 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 46 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 11 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c |  7 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_test.c  | 11 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  8 ++---
 11 files changed, 58 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 292c7e72820c..b1116b773516 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -441,7 +441,7 @@ struct amdgpu_sa_bo {
 void amdgpu_gem_force_release(struct amdgpu_device *adev);
 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
 int alignment, u32 initial_domain,
-u64 flags, bool kernel,
+u64 flags, enum ttm_bo_type type,
 struct reservation_object *resv,
 struct drm_gem_object **obj);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 450426dbed92..7f096ed6e83d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -215,8 +215,9 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
if ((*mem) == NULL)
return -ENOMEM;
 
-   r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,
-AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 
&(*mem)->bo);
+   r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
+AMDGPU_GEM_CREATE_CPU_GTT_USWC, ttm_bo_type_kernel,
+NULL, &(*mem)->bo);
if (r) {
dev_err(adev->dev,
"failed to allocate BO for amdkfd (%d)\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 2fb299afc12b..02b849be083b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -80,8 +80,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, 
unsigned size,
int time;
 
n = AMDGPU_BENCHMARK_ITERATIONS;
-   r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, NULL,
-NULL, );
+   r = amdgpu_bo_create(adev, size, PAGE_SIZE,sdomain, 0,
+ttm_bo_type_kernel, NULL, );
if (r) {
goto out_cleanup;
}
@@ -93,8 +93,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, 
unsigned size,
if (r) {
goto out_cleanup;
}
-   r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, NULL,
-NULL, );
+   r = amdgpu_bo_create(adev, size, PAGE_SIZE, ddomain, 0,
+ttm_bo_type_kernel, NULL, );
if (r) {
goto out_cleanup;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index dc8d9f3216fa..cf0f186c6092 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -113,11 +113,12 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device 
*adev)
int r;
 
if (adev->gart.robj == NULL) {
-   r = amdgpu_bo_create(adev, adev->gart.table_size,
-PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
+   r = amdgpu_bo_create(adev, adev->gart.table_size, PAGE_SIZE,
+AMDGPU_GEM_DOMAIN_VRAM,
 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
-NULL, NULL, >gart.robj);
+ttm_bo_type_kernel, NULL,
+>gart.robj);
if (r) {
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 55a840ae6d68..bb9b21266b67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -45,7 +45,7 @@ void amdgpu_gem_object_free(struct drm_gem_object 

[PATCH 5/6] drm/amdgpu: initial validate the prime BOs into the CPU domain

[Christian König]

Just set the GTT domain as mandatory, so that the BO is validated into
it on first use. This allows us to setup the sg table later on.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index fb66b45548d3..44230165e181 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -106,10 +106,12 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
 
ww_mutex_lock(>lock, NULL);
ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false,
-  AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, );
+  AMDGPU_GEM_DOMAIN_CPU, 0, sg, resv, );
if (ret)
goto error;
 
+   bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
+   bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
if (attach->dmabuf->ops != _dmabuf_ops)
bo->prime_shared_count = 1;
 
-- 
2.14.1

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[PATCH 2/6] drm/ttm: add bo as parameter to the ttm_tt_create callback

[Christian König]

Instead of calculating the size in bytes just to recalculate the number
of pages from it pass the BO directly to the function.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  8 
 drivers/gpu/drm/ast/ast_ttm.c   |  6 +++---
 drivers/gpu/drm/bochs/bochs_mm.c|  5 ++---
 drivers/gpu/drm/cirrus/cirrus_ttm.c |  6 +++---
 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c |  5 ++---
 drivers/gpu/drm/mgag200/mgag200_ttm.c   |  6 +++---
 drivers/gpu/drm/nouveau/nouveau_bo.c| 10 --
 drivers/gpu/drm/nouveau/nouveau_sgdma.c |  7 +++
 drivers/gpu/drm/nouveau/nouveau_ttm.h   |  4 ++--
 drivers/gpu/drm/qxl/qxl_ttm.c   |  8 
 drivers/gpu/drm/radeon/radeon_ttm.c | 12 ++--
 drivers/gpu/drm/ttm/ttm_agp_backend.c   |  6 +++---
 drivers/gpu/drm/ttm/ttm_tt.c| 29 ++---
 drivers/gpu/drm/virtio/virtgpu_ttm.c|  7 +++
 drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c  | 10 +-
 drivers/staging/vboxvideo/vbox_ttm.c|  5 ++---
 include/drm/ttm/ttm_bo_driver.h |  6 ++
 include/drm/ttm/ttm_tt.h| 22 ++
 18 files changed, 75 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 628cbc3ab46f..44ae2c60c9d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -974,20 +974,20 @@ static struct ttm_backend_func amdgpu_backend_func = {
.destroy = _ttm_backend_destroy,
 };
 
-static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
-   unsigned long size, uint32_t page_flags)
+static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
+  uint32_t page_flags)
 {
struct amdgpu_device *adev;
struct amdgpu_ttm_tt *gtt;
 
-   adev = amdgpu_ttm_adev(bdev);
+   adev = amdgpu_ttm_adev(bo->bdev);
 
gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
if (gtt == NULL) {
return NULL;
}
gtt->ttm.ttm.func = _backend_func;
-   if (ttm_sg_tt_init(>ttm, bdev, size, page_flags)) {
+   if (ttm_sg_tt_init(>ttm, bo, page_flags)) {
kfree(gtt);
return NULL;
}
diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c
index 211224f6bdd3..fe354ebf374d 100644
--- a/drivers/gpu/drm/ast/ast_ttm.c
+++ b/drivers/gpu/drm/ast/ast_ttm.c
@@ -199,8 +199,8 @@ static struct ttm_backend_func ast_tt_backend_func = {
 };
 
 
-static struct ttm_tt *ast_ttm_tt_create(struct ttm_bo_device *bdev,
-unsigned long size, uint32_t page_flags)
+static struct ttm_tt *ast_ttm_tt_create(struct ttm_buffer_object *bo,
+   uint32_t page_flags)
 {
struct ttm_tt *tt;
 
@@ -208,7 +208,7 @@ static struct ttm_tt *ast_ttm_tt_create(struct 
ttm_bo_device *bdev,
if (tt == NULL)
return NULL;
tt->func = _tt_backend_func;
-   if (ttm_tt_init(tt, bdev, size, page_flags)) {
+   if (ttm_tt_init(tt, bo, page_flags)) {
kfree(tt);
return NULL;
}
diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c
index 73722484e12b..50c52b45448f 100644
--- a/drivers/gpu/drm/bochs/bochs_mm.c
+++ b/drivers/gpu/drm/bochs/bochs_mm.c
@@ -176,8 +176,7 @@ static struct ttm_backend_func bochs_tt_backend_func = {
.destroy = _ttm_backend_destroy,
 };
 
-static struct ttm_tt *bochs_ttm_tt_create(struct ttm_bo_device *bdev,
- unsigned long size,
+static struct ttm_tt *bochs_ttm_tt_create(struct ttm_buffer_object *bo,
  uint32_t page_flags)
 {
struct ttm_tt *tt;
@@ -186,7 +185,7 @@ static struct ttm_tt *bochs_ttm_tt_create(struct 
ttm_bo_device *bdev,
if (tt == NULL)
return NULL;
tt->func = _tt_backend_func;
-   if (ttm_tt_init(tt, bdev, size, page_flags)) {
+   if (ttm_tt_init(tt, bo, page_flags)) {
kfree(tt);
return NULL;
}
diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c 
b/drivers/gpu/drm/cirrus/cirrus_ttm.c
index 6cd0233b3bf8..f21953243790 100644
--- a/drivers/gpu/drm/cirrus/cirrus_ttm.c
+++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c
@@ -199,8 +199,8 @@ static struct ttm_backend_func cirrus_tt_backend_func = {
 };
 
 
-static struct ttm_tt *cirrus_ttm_tt_create(struct ttm_bo_device *bdev,
-unsigned long size, uint32_t page_flags)
+static struct ttm_tt *cirrus_ttm_tt_create(struct ttm_buffer_object *bo,
+  uint32_t page_flags)
 {
struct ttm_tt *tt;
 
@@ -208,7 

Re: [PATCH 2/2] drm/amdgpu: fix KV harvesting

[Zhu, Rex]

Acked-by:  Rex Zhu for the series.


Best Regards
Rex


From: amd-gfx  on behalf of Alex Deucher 

Sent: Tuesday, March 6, 2018 2:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; sta...@vger.kernel.org
Subject: [PATCH 2/2] drm/amdgpu: fix KV harvesting

Always set the graphics values to the max for the
asic type.  E.g., some 1 RB chips are actually 1 RB chips,
others are actually harvested 2 RB chips.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++
 1 file changed, 2 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 972d421caada..e13d9d83767b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4358,34 +4358,8 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device 
*adev)
 case CHIP_KAVERI:
 adev->gfx.config.max_shader_engines = 1;
 adev->gfx.config.max_tile_pipes = 4;
-   if ((adev->pdev->device == 0x1304) ||
-   (adev->pdev->device == 0x1305) ||
-   (adev->pdev->device == 0x130C) ||
-   (adev->pdev->device == 0x130F) ||
-   (adev->pdev->device == 0x1310) ||
-   (adev->pdev->device == 0x1311) ||
-   (adev->pdev->device == 0x131C)) {
-   adev->gfx.config.max_cu_per_sh = 8;
-   adev->gfx.config.max_backends_per_se = 2;
-   } else if ((adev->pdev->device == 0x1309) ||
-  (adev->pdev->device == 0x130A) ||
-  (adev->pdev->device == 0x130D) ||
-  (adev->pdev->device == 0x1313) ||
-  (adev->pdev->device == 0x131D)) {
-   adev->gfx.config.max_cu_per_sh = 6;
-   adev->gfx.config.max_backends_per_se = 2;
-   } else if ((adev->pdev->device == 0x1306) ||
-  (adev->pdev->device == 0x1307) ||
-  (adev->pdev->device == 0x130B) ||
-  (adev->pdev->device == 0x130E) ||
-  (adev->pdev->device == 0x1315) ||
-  (adev->pdev->device == 0x131B)) {
-   adev->gfx.config.max_cu_per_sh = 4;
-   adev->gfx.config.max_backends_per_se = 1;
-   } else {
-   adev->gfx.config.max_cu_per_sh = 3;
-   adev->gfx.config.max_backends_per_se = 1;
-   }
+   adev->gfx.config.max_cu_per_sh = 8;
+   adev->gfx.config.max_backends_per_se = 2;
 adev->gfx.config.max_sh_per_se = 1;
 adev->gfx.config.max_texture_channel_caches = 4;
 adev->gfx.config.max_gprs = 256;
--
2.13.6

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Re: [PATCH] drm/amd/pp: fix "Delete the wrapper layer of smu_allocate/free_memory"

[Zhu, Rex]

Reviewed-by: Rex Zhu

Best Regards
Rex



From: Christian König 
Sent: Tuesday, March 6, 2018 9:58 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amd/pp: fix "Delete the wrapper layer of 
smu_allocate/free_memory"

For amdgpu_bo_create_kernel to work the handle must be NULL initialized,
otherwise we only try to pin and map the BO.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index cf9ef7add56b..e2ee23ade5c5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -327,10 +327,10 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)

 static int rv_smu_init(struct pp_hwmgr *hwmgr)
 {
+   struct amdgpu_bo *handle = NULL;
 struct rv_smumgr *priv;
 uint64_t mc_addr;
 void *kaddr = NULL;
-   struct amdgpu_bo *handle;
 int r;

 priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index b7be91e7235b..15e1afa28018 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -377,11 +377,11 @@ static int vega10_verify_smc_interface(struct pp_hwmgr 
*hwmgr)

 static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 {
+   struct amdgpu_bo *handle = NULL;
 struct vega10_smumgr *priv;
 uint64_t mc_addr;
 void *kaddr = NULL;
 unsigned long tools_size;
-   struct amdgpu_bo *handle;
 int ret;
 struct cgs_firmware_info info = {0};

--
2.14.1

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Re: Modesetting (amdgpudrmfb) artifacts on RAVEN APU

[Tom St Denis]

I believe this is the same issue I had which is a VGA handoff problem.

Can you try this patch the display team sent me?

Harry:  Will this patch be promoted in the next cycle?

Tom

On 03/05/2018 11:40 AM, KARBOWSKI Piotr wrote:

Hi list,

I'd like to report a very odd screen artifacts while running both 
4.16-rc3, as well as latest 4.16-rc4 with git linux-firmware.


I am using Ryzen 2400G with the integrate Vega.

I am aware that RAVEN support is yet to be finished, however I've read 
that some people do run it already, so I figured I will report the 
issues, since other does not seems to hit it.


I have amdgpu and all it's symbols built into the kernel image, and the 
firmware added to initrammfs. The moment modesetting is initializing I 
can see that native screen resolution goes, however, I can see only like 
25% of the screen and this very top-left 25% of screen is duplicated to 
top-right. While the bottom half of screen is either black or have 
lines, usually gray, unless some text on screen had another color then 
it's green, blue, etc.


Screenshots:

 https://i.imgur.com/qnDOKY7.jpg
 https://i.imgur.com/XH42zit.jpg

The AMD symbols that I've enabled in kernel:

     CONFIG_CPU_SUP_AMD=y
     CONFIG_X86_MCE_AMD=y
     CONFIG_AMD_NB=y
     CONFIG_NET_VENDOR_AMD=y
     CONFIG_DRM_AMDGPU=y
     CONFIG_DRM_AMDGPU_SI=y
     CONFIG_DRM_AMDGPU_CIK=y
     CONFIG_DRM_AMD_ACP=y
     CONFIG_DRM_AMD_DC=y
     CONFIG_DRM_AMD_DC_FBC=y
     CONFIG_DRM_AMD_DC_DCN1_0=y
     CONFIG_HSA_AMD=y
     CONFIG_AMD_IOMMU=y
     CONFIG_AMD_IOMMU_V2=y

The kernel log that had either drm, amd or firmware in there:

     [    0.00] RAMDISK: [mem 0x7f88c000-0x7fff]
     [    0.00] ACPI: SSDT 0x9BD94908 005367 (v02 AMD 
AmdTable 0002 MSFT 0202)
     [    0.00] ACPI: SSDT 0x9BD99C70 00119C (v01 AMD    AMD 
CPU  0001 AMD  0001)
     [    0.00] ACPI: CRAT 0x9BD9AE10 000810 (v01 AMD    AMD 
CRAT 0001 AMD  0001)
     [    0.00] ACPI: CDIT 0x9BD9B620 29 (v01 AMD    AMD 
CDIT 0001 AMD  0001)
     [    0.00] ACPI: SSDT 0x9BD9B650 002E6E (v01 AMD    AMD 
AOD  0001 INTL 20120913)
     [    0.00] ACPI: IVRS 0x9BD9E580 D0 (v02 AMD    AMD 
IVRS 0001 AMD  )
     [    0.00] ACPI: SSDT 0x9BD9E650 F8 (v01 AMD    AMD 
PT   1000 INTL 20120913)
     [    0.00] ACPI: SSDT 0x9BD9E748 000E96 (v01 AMD 
AmdTable 0001 INTL 20120913)
     [    0.00] ACPI: SSDT 0x9BD9F5E0 000850 (v01 AMD 
AmdTable 0001 INTL 20120913)
     [    0.00] ACPI: SSDT 0x9BD9FE30 001993 (v01 AMD 
AmdTable 0001 INTL 20120913)
     [    0.00] Kernel command line: BOOT_IMAGE=/bzImage-4.16.0-rc4 
rootfstype=ext4 luks enc_root=/dev/sda2 lvm 
root=/dev/mapper/megumin-rootfs 
initrd=/initramfs.cpio.gz,/firmware-initramfs.cpio.gz
     [    0.00] ACPI Error: AE_ALREADY_EXISTS, (SSDT:  AMD PT) while 
loading table (20180105/tbxfload-228)
     [    0.08] smpboot: CPU0: AMD Ryzen 5 2400G with Radeon Vega 
Graphics (family: 0x17, model: 0x11, stepping: 0x0)
     [    0.08] Performance Events: Fam17h core perfctr, AMD PMU 
driver.

     [    0.101786] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
     [    0.615782] AMD-Vi: IOMMU performance counters supported
     [    0.623179] AMD-Vi: Found IOMMU at :00:00.2 cap 0x40
     [    0.623314] AMD-Vi: Extended features (0x4f77ef22294ada):
     [    0.623684] AMD-Vi: Lazy IO/TLB flushing enabled
     [    0.624533] amd_uncore: AMD NB counters detected
     [    0.624666] amd_uncore: AMD LLC counters detected
     [    0.625076] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4 
counters/bank).

     [    0.636229] AMD IOMMUv2 driver by Joerg Roedel 
     [    0.637179] [drm] amdgpu kernel modesetting enabled.
     [    0.637409] [drm] initializing kernel modesetting (RAVEN 
0x1002:0x15DD 0x1458:0xD000 0xC6).

     [    0.637583] [drm] register mmio base: 0xFE50
     [    0.637709] [drm] register mmio size: 524288
     [    0.637852] [drm] probing gen 2 caps for device 1022:15db = 
700d03/e

     [    0.638005] [drm] probing mlw for device 1022:15db = 700d03
     [    0.638213] [drm] VCN decode is enabled in VM mode
     [    0.638341] [drm] VCN encode is enabled in VM mode
     [    0.660265] [drm] BIOS signature incorrect 74 7
     [    0.660422] [drm] vm size is 262144 GB, 4 levels, block size is 
9-bit, fragment size is 9-bit
     [    0.660515] amdgpu :09:00.0: VRAM: 1024M 0x00F4 
- 0x00F43FFF (1024M used)
     [    0.660607] amdgpu :09:00.0: GTT: 1024M 0x00F5 - 
0x00F53FFF

     [    0.660689] [drm] Detected VRAM RAM=1024M, BAR=256M
     [    0.660756] [drm] RAM width 128bits UNKNOWN
     [    0.661653] [drm] amdgpu: 1024M of VRAM memory ready
     [    0.661720] [drm] amdgpu: 3072M of GTT memory ready.
     [    0.661793] [drm] GART: num 

[PATCH 2/2] drm/amdgpu: refactoring mailbox to fix TDR handshake bugs

[Monk Liu]

this patch actually refactor mailbox implmentations, and
all below changes are needed together to fix all those mailbox
handshake issues exposured by heavey TDR test.

1)refactor all mailbox functions based on byte accessing for mb_control
reason is to avoid touching non-related bits when writing trn/rcv part of
mailbox_control, this way some incorrect INTR sent to hypervisor
side could be avoided, and it fixes couple handshake bug.

2)trans_msg function re-impled: put a invalid
logic before transmitting message to make sure the ACK bit is in
a clear status, otherwise there is chance that ACK asserted already
before transmitting message and lead to fake ACK polling.
(hypervisor side have some tricks to workaround ACK bit being corrupted
by VF FLR which hase an side effects that may make guest side ACK bit
asserted wrongly), and clear TRANS_MSG words after message transferred.

3)for mailbox_flr_work, it is also re-worked: it takes the mutex lock
first if invoked, to block gpu recover's participate too early while
hypervisor side is doing VF FLR. (hypervisor sends FLR_NOTIFY to guest
before doing VF FLR and sentds FLR_COMPLETE after VF FLR done, and
the FLR_NOTIFY will trigger interrupt to guest which lead to
mailbox_flr_work being invoked)

This can avoid the issue that mailbox trans msg being cleared by its VF FLR.

4)for mailbox_rcv_irq IRQ routine, it should only peek msg and schedule
mailbox_flr_work, instead of ACK to hypervisor itself, because FLR_NOTIFY
msg sent from hypervisor side doesn't need VF's ACK (this is because
VF's ACK would lead to hypervisor clear its trans_valid/msg, and this
would cause handshake bug if trans_valid/msg is cleared not due to
correct VF ACK but from a wrong VF ACK like this "FLR_NOTIFY" one)

This fixed handshake bug that sometimes GUEST always couldn't receive
"READY_TO_ACCESS_GPU" msg from hypervisor.

5)seperate polling time limite accordingly:
POLL ACK cost no more than 500ms
POLL MSG cost no more than 12000ms
POLL FLR finish cost no more than 500ms

6) we still need to set adev into in_gpu_reset mode after we received
FLR_NOTIFY from host side, this can prevent innocent app wrongly succesed
to open amdgpu dri device.

FLR_NOFITY is received due to an IDLE hang detected from hypervisor side
which indicating GPU is already die in this VF.

Change-Id: I17df8b4490a5b53a1cc2bd6c8f9bc3ee14c23f1a
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 200 ++
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 +-
 2 files changed, 111 insertions(+), 93 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 271452d..8d09380 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -33,56 +33,42 @@
 
 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
 {
-   u32 reg;
-   int timeout = AI_MAILBOX_TIMEDOUT;
-   u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID);
-
-   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-mmBIF_BX_PF0_MAILBOX_CONTROL));
-   reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_ACK, 1);
-   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-  mmBIF_BX_PF0_MAILBOX_CONTROL), reg);
-
-   /*Wait for RCV_MSG_VALID to be 0*/
-   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-mmBIF_BX_PF0_MAILBOX_CONTROL));
-   while (reg & mask) {
-   if (timeout <= 0) {
-   pr_err("RCV_MSG_VALID is not cleared\n");
-   break;
-   }
-   mdelay(1);
-   timeout -=1;
-
-   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-
mmBIF_BX_PF0_MAILBOX_CONTROL));
-   }
+   const u32 offset = SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1;
+   WREG8(offset, 2);
 }
 
 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
 {
-   u32 reg;
+   const u32 offset = SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_MAILBOX_CONTROL) * 4;
+   WREG8(offset, val ? 1 : 0);
+}
 
-   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-mmBIF_BX_PF0_MAILBOX_CONTROL));
-   reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL,
-   TRN_MSG_VALID, val ? 1 : 0);
-   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL),
- reg);
+/*
+ * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
+ * RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1
+ * by host.
+ *
+ * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
+ * correct value since it doesn't return the RCV_DW0 under the case that
+ * 

[PATCH 1/2] drm/amdgpu: imlement mmio byte access helpers

[Monk Liu]

mailbox register can be accessed with a byte boundry according
to BIF team, so this patch prepares register byte access
and will be used by following patches

Change-Id: I1e84f1c6e8e75dc42eb5be09c492fa5e7eb7502a
Signed-off-by: Monk Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ++
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 292c7e7..72385bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1635,6 +1635,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, 
uint32_t reg,
uint32_t acc_flags);
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags);
+void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t 
value);
+uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
+
 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
 
@@ -1658,6 +1661,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 
AMDGPU_REGS_NO_KIQ)
 
+#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
+#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
+
 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", 
amdgpu_mm_rreg(adev, (reg), 0))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 65584f6..c8e1940 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -121,6 +121,32 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, 
uint32_t reg,
return ret;
 }
 
+/*
+ * MMIO register read with bytes helper functions
+ * @offset:bytes offset from MMIO start
+ *
+*/
+
+uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
+   if (offset < adev->rmmio_size)
+   return (readb(adev->rmmio + offset));
+   BUG();
+}
+
+/*
+ * MMIO register write with bytes helper functions
+ * @offset:bytes offset from MMIO start
+ * @value: the value want to be written to the register
+ *
+*/
+void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t 
value) {
+   if (offset < adev->rmmio_size)
+   writeb(value, adev->rmmio + offset);
+   else
+   BUG();
+}
+
+
 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
uint32_t acc_flags)
 {
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Christian König]

Am 06.03.2018 um 10:59 schrieb Emily Deng:

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

Signed-off-by: Emily Deng 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..2a27928 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
*adev)
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
   upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
sdma_offsets[i]);
-   if (ring->use_pollmem)
+   if (ring->use_pollmem) {
+   WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 1);
-   else
+   } else


According to the coding style you should use "} else {" here.

Apart from that the patch looks good to me,
Christian.


wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 0);


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Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state

[Daniel Vetter]

On Wed, Feb 28, 2018 at 09:26:26AM -0500, Alex Deucher wrote:
> + dri-devel
> 
> 
> On Wed, Feb 28, 2018 at 4:33 AM, S, Shirish  wrote:
> > From: Shirish S 
> >
> > Add reverse iterator "for_each_oldnew_plane_in_state_reverse" to
> > complement "for_each_oldnew_plane_in_state" way of reading plane
> > states.
> >
> > The plane states are required to be read in reverse order for
> > amdgpu, as the z order convention followed in linux is
> > opposite to how the planes are supposed to be presented to DC
> > engine, which is in common to both windows and linux.
> >
> > Signed-off-by: Shirish S 
> > Signed-off-by: Pratik Vishwakarma 

Makes sense.
> > ---
> >  include/drm/drm_atomic.h | 22 ++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
> > index cf13842..b947930 100644
> > --- a/include/drm/drm_atomic.h
> > +++ b/include/drm/drm_atomic.h
> > @@ -754,6 +754,28 @@ void drm_state_dump(struct drm_device *dev, struct 
> > drm_printer *p);
> >   (new_plane_state) = 
> > (__state)->planes[__i].new_state, 1))
> >
> >  /**
> > + * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an 
> > atomic
> > + * update in reverse order

Are you sure this renders correctly in kernel-doc? Iirc you have to indent
the continuation line.

Assuming this is fixed:

Reviewed-by: Daniel Vetter 

> > + * @__state:  drm_atomic_state pointer
> > + * @plane:  drm_plane iteration cursor
> > + * @old_plane_state:  drm_plane_state iteration cursor for the old 
> > state
> > + * @new_plane_state:  drm_plane_state iteration cursor for the new 
> > state
> > + * @__i: int iteration cursor, for macro-internal use
> > + *
> > + * This iterates over all planes in an atomic update in reverse order,
> > + * tracking both old and  new state. This is useful in places where the
> > + * state delta needs to be considered, for example in atomic check 
> > functions.
> > + */
> > +#define for_each_oldnew_plane_in_state_reverse(__state, plane, 
> > old_plane_state, new_plane_state, __i) \
> > +   (for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1);
> > \
> > +(__i) >= 0;\
> > +(__i)--)   \
> > +   for_each_if ((__state)->planes[__i].ptr &&  \
> > +((plane) = (__state)->planes[__i].ptr, \
> > + (old_plane_state) = 
> > (__state)->planes[__i].old_state,\
> > + (new_plane_state) = 
> > (__state)->planes[__i].new_state, 1)))
> > +
> > +/**
> >   * for_each_old_plane_in_state - iterate over all planes in an atomic 
> > update
> >   * @__state:  drm_atomic_state pointer
> >   * @plane:  drm_plane iteration cursor
> > --
> > 2.7.4
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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RE: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Deng, Emily]

The sdma v4 doesn't have the issue about the conflict between doorbell and sdma 
wptr polling.

Best Wishes,
Emily Deng



> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of zhoucm1
> Sent: Tuesday, March 06, 2018 6:03 PM
> To: Deng, Emily ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only
> enable wptr polling
> 
> How about other sdma version? like sdma v4 etc.
> 
> 
> Regards,
> 
> David Zhou
> 
> 
> On 2018年03月06日 17:59, Emily Deng wrote:
> > The sdma wptr polling memory is not fast enough, then the sdma wptr
> > register will be random, and not equal to sdma rptr, which will cause
> > sdma engine hang when load driver, so clean up the sdma wptr directly
> > to fix this issue.
> >
> > Signed-off-by: Emily Deng 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
> >   1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > index 521978c..2a27928 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > @@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
> > WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
> >upper_32_bits(wptr_gpu_addr));
> > wptr_poll_cntl =
> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> > -   if (ring->use_pollmem)
> > +   if (ring->use_pollmem) {
> > +   WREG32(mmSDMA0_GFX_RB_WPTR +
> sdma_offsets[i], 0);
> > wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> >
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
> >ENABLE, 1);
> > -   else
> > +   } else
> > wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> >
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
> >ENABLE, 0);
> 
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Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Liu, Monk]

looks we didn't hit similar issues during vega10 testing ...

From: amd-gfx  on behalf of zhoucm1 

Sent: Tuesday, March 6, 2018 6:02:35 PM
To: Deng, Emily; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr 
polling

How about other sdma version? like sdma v4 etc.


Regards,

David Zhou


On 2018年03月06日 17:59, Emily Deng wrote:
> The sdma wptr polling memory is not fast enough, then the sdma
> wptr register will be random, and not equal to sdma rptr, which
> will cause sdma engine hang when load driver, so clean up the sdma
> wptr directly to fix this issue.
>
> Signed-off-by: Emily Deng 
> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 521978c..2a27928 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
> *adev)
>WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
>   upper_32_bits(wptr_gpu_addr));
>wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
> sdma_offsets[i]);
> - if (ring->use_pollmem)
> + if (ring->use_pollmem) {
> + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
>wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
>   
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>   ENABLE, 1);
> - else
> + } else
>wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
>   
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>   ENABLE, 0);

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Re: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[zhoucm1]

How about other sdma version? like sdma v4 etc.


Regards,

David Zhou


On 2018年03月06日 17:59, Emily Deng wrote:

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

Signed-off-by: Emily Deng 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..2a27928 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
*adev)
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
   upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
sdma_offsets[i]);
-   if (ring->use_pollmem)
+   if (ring->use_pollmem) {
+   WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 1);
-   else
+   } else
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 0);


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Re: [PATCH 3/5] drm/ttm: move ttm_tt defines into ttm_tt.h

[Thomas Hellstrom]

Acked-by: Thomas Hellstrom 

On 03/06/2018 10:13 AM, Christian König wrote:

Hi Michel & Thomas,

any more comments on this? Or can I commit it?

Thanks,
Christian.

Am 27.02.2018 um 12:49 schrieb Christian König:

Let's stop mangling everything in a single header and create one header
per object instead.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/ttm/ttm_tt.c    |   6 -
  include/drm/ttm/ttm_bo_driver.h | 237 
+-
  include/drm/ttm/ttm_tt.h    | 272 


  3 files changed, 273 insertions(+), 242 deletions(-)
  create mode 100644 include/drm/ttm/ttm_tt.h

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 0ee3b8f11605..8e0b525cda00 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -31,17 +31,11 @@
  #define pr_fmt(fmt) "[TTM] " fmt
    #include 
-#include 
  #include 
  #include 
  #include 
-#include 
-#include 
-#include 
  #include 
-#include 
  #include 
-#include 
  #include 
  #ifdef CONFIG_X86
  #include 
diff --git a/include/drm/ttm/ttm_bo_driver.h 
b/include/drm/ttm/ttm_bo_driver.h

index 4312b5326f0b..f8e2515b401f 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -42,111 +42,10 @@
  #include "ttm_memory.h"
  #include "ttm_module.h"
  #include "ttm_placement.h"
+#include "ttm_tt.h"
    #define TTM_MAX_BO_PRIORITY    4U
  -struct ttm_backend_func {
-    /**
- * struct ttm_backend_func member bind
- *
- * @ttm: Pointer to a struct ttm_tt.
- * @bo_mem: Pointer to a struct ttm_mem_reg describing the
- * memory type and location for binding.
- *
- * Bind the backend pages into the aperture in the location
- * indicated by @bo_mem. This function should be able to handle
- * differences between aperture and system page sizes.
- */
-    int (*bind) (struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
-
-    /**
- * struct ttm_backend_func member unbind
- *
- * @ttm: Pointer to a struct ttm_tt.
- *
- * Unbind previously bound backend pages. This function should be
- * able to handle differences between aperture and system page 
sizes.

- */
-    int (*unbind) (struct ttm_tt *ttm);
-
-    /**
- * struct ttm_backend_func member destroy
- *
- * @ttm: Pointer to a struct ttm_tt.
- *
- * Destroy the backend. This will be call back from 
ttm_tt_destroy so

- * don't call ttm_tt_destroy from the callback or infinite loop.
- */
-    void (*destroy) (struct ttm_tt *ttm);
-};
-
-#define TTM_PAGE_FLAG_WRITE   (1 << 3)
-#define TTM_PAGE_FLAG_SWAPPED (1 << 4)
-#define TTM_PAGE_FLAG_PERSISTENT_SWAP (1 << 5)
-#define TTM_PAGE_FLAG_ZERO_ALLOC  (1 << 6)
-#define TTM_PAGE_FLAG_DMA32   (1 << 7)
-#define TTM_PAGE_FLAG_SG  (1 << 8)
-#define TTM_PAGE_FLAG_NO_RETRY  (1 << 9)
-
-enum ttm_caching_state {
-    tt_uncached,
-    tt_wc,
-    tt_cached
-};
-
-/**
- * struct ttm_tt
- *
- * @bdev: Pointer to a struct ttm_bo_device.
- * @func: Pointer to a struct ttm_backend_func that describes
- * the backend methods.
- * pointer.
- * @pages: Array of pages backing the data.
- * @num_pages: Number of pages in the page array.
- * @bdev: Pointer to the current struct ttm_bo_device.
- * @be: Pointer to the ttm backend.
- * @swap_storage: Pointer to shmem struct file for swap storage.
- * @caching_state: The current caching state of the pages.
- * @state: The current binding state of the pages.
- *
- * This is a structure holding the pages, caching- and aperture binding
- * status for a buffer object that isn't backed by fixed (VRAM / AGP)
- * memory.
- */
-
-struct ttm_tt {
-    struct ttm_bo_device *bdev;
-    struct ttm_backend_func *func;
-    struct page **pages;
-    uint32_t page_flags;
-    unsigned long num_pages;
-    struct sg_table *sg; /* for SG objects via dma-buf */
-    struct file *swap_storage;
-    enum ttm_caching_state caching_state;
-    enum {
-    tt_bound,
-    tt_unbound,
-    tt_unpopulated,
-    } state;
-};
-
-/**
- * struct ttm_dma_tt
- *
- * @ttm: Base ttm_tt struct.
- * @dma_address: The DMA (bus) addresses of the pages
- * @pages_list: used by some page allocation backend
- *
- * This is a structure holding the pages, caching- and aperture binding
- * status for a buffer object that isn't backed by fixed (VRAM / AGP)
- * memory.
- */
-struct ttm_dma_tt {
-    struct ttm_tt ttm;
-    dma_addr_t *dma_address;
-    struct list_head pages_list;
-};
-
  #define TTM_MEMTYPE_FLAG_FIXED (1 << 0)    /* Fixed 
(on-card) PCI memory */
  #define TTM_MEMTYPE_FLAG_MAPPABLE  (1 << 1)    /* Memory 
mappable */
  #define TTM_MEMTYPE_FLAG_CMA   (1 << 3)    /* Can't map 
aperture */
@@ -610,117 +509,6 @@ ttm_flag_masked(uint32_t *old, uint32_t new, 
uint32_t mask)

  return *old;
  }
  -/**
- * ttm_tt_create
- *
- * @bo: 

[PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Emily Deng]

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..2a27928 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
*adev)
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
   upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
sdma_offsets[i]);
-   if (ring->use_pollmem)
+   if (ring->use_pollmem) {
+   WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 1);
-   else
+   } else
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 0);
-- 
2.7.4

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Re: [PATCH 3/5] drm/ttm: move ttm_tt defines into ttm_tt.h

[Michel Dänzer]

On 2018-03-06 10:13 AM, Christian König wrote:
> Hi Michel & Thomas,
> 
> any more comments on this? Or can I commit it?

Acked-by: Michel Dänzer 


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RE: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Yu, Xiangliang]

Better to add comment above the code.

Reviewed-by: Xiangliang Yu 


> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Emily Deng
> Sent: Tuesday, March 06, 2018 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily 
> Subject: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable
> wptr polling
> 
> The sdma wptr polling memory is not fast enough, then the sdma wptr
> register will be random, and not equal to sdma rptr, which will cause sdma
> engine hang when load driver, so clean up the sdma wptr directly to fix this
> issue.
> 
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 521978c..2a27928 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
>   WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
>  upper_32_bits(wptr_gpu_addr));
>   wptr_poll_cntl =
> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> - if (ring->use_pollmem)
> + if (ring->use_pollmem) {
> + WREG32(mmSDMA0_GFX_RB_WPTR +
> sdma_offsets[i], 0);
>   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> 
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>  ENABLE, 1);
> - else
> + } else
>   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> 
> SDMA0_GFX_RB_WPTR_POLL_CNTL,
>  ENABLE, 0);
> --
> 2.7.4
> 
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Re: [PATCH 1/5] drm/prime: fix potential race in drm_gem_map_detach

[Daniel Vetter]

On Tue, Mar 06, 2018 at 10:30:56AM +0100, Christian König wrote:
> Am 06.03.2018 um 10:15 schrieb Daniel Vetter:
> > On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:
> > > Am 28.02.2018 um 10:48 schrieb Lucas Stach:
> > > > Hi Christian,
> > > > 
> > > > Am Dienstag, den 27.02.2018, 12:49 +0100 schrieb Christian König:
> > > > > Unpin the GEM object only after freeing the sg table.
> > > > What is the race that is being fixed here? The SG table is private to
> > > > the importer and the importer should hopefully only call map_detach if
> > > > it is done with all operations using the SG table. Thus it shouldn't
> > > > matter that the SG table might point to moved pages during execution of
> > > > this function.
> > > Exactly, it shouldn't matter. This is just a precaution.
> > > 
> > > When the device driver is buggy I want proper error messages from IOMMU 
> > > and
> > > not accessing pages which might already be reused for something else.
> > Please add this to the commit message, rather crucial to understand the
> > motivation. With that fixed you can have my
> > 
> > Reviewed-by: Daniel Vetter 
> > 
> > And pls push to drm-misc.
> 
> Can I use standard git for that now? I really don't want to mess with dim in
> my environment.

Ping Alex to run it for you please. In an ideal world we'd run all that
stuff server-side, but that's not happening anytime soon.

Also if you have any specific issues about dim stomping over your setup,
we'll be happy to fix it. If you set the (relative) paths correctly you
can hide the various additional checkouts it needs rather well.
-Daniel
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Re: [PATCH 2/5] drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays

[Daniel Vetter]

On Tue, Mar 06, 2018 at 10:25:03AM +0100, Christian König wrote:
> Am 06.03.2018 um 10:21 schrieb Daniel Vetter:
> > On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:
> > > Most of the time we only need the dma addresses.
> > > 
> > > Signed-off-by: Christian König 
> > > ---
> > >   drivers/gpu/drm/drm_prime.c | 20 ++--
> > >   1 file changed, 10 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> > > index c38dacda6119..7856a9b3f8a8 100644
> > > --- a/drivers/gpu/drm/drm_prime.c
> > > +++ b/drivers/gpu/drm/drm_prime.c
> > > @@ -922,40 +922,40 @@ EXPORT_SYMBOL(drm_prime_pages_to_sg);
> > >   /**
> > >* drm_prime_sg_to_page_addr_arrays - convert an sg table into a page 
> > > array
> > >* @sgt: scatter-gather table to convert
> > > - * @pages: array of page pointers to store the page array in
> > > + * @pages: optional array of page pointers to store the page array in
> > >* @addrs: optional array to store the dma bus address of each page
> > > - * @max_pages: size of both the passed-in arrays
> > > + * @max_entries: size of both the passed-in arrays
> > >*
> > >* Exports an sg table into an array of pages and addresses. This is 
> > > currently
> > >* required by the TTM driver in order to do correct fault handling.
> > >*/
> > Can't we just teach ttm to use sgts wherever needed, and deprecate
> > exporting dma-bufs to page arrays (which really breaks the abstraction
> > entirely and was just a quick hack to get things going that stuck around
> > for years). Last time I looked into ttm the only thing it did is convert
> > it back to sgts again (after calling dma_map once more, which the exporter
> > should have done already for you).
> 
> Thought about that as well, but the problem here isn't TTM.
> 
> We need to be able to access the SGT by an index in amdgpu to be able to
> build up the VM page tables and that is not possible because the SGT is
> potentially chained.
> 
> We could add a new sg_table access helper function to work around that
> thought.

There's some neat per-page sgt iter functions that we've build for i915.
See i915_gem_gtt.c. But yeah that's probably a pile more work, but imo
from the i915 code shuffling the end result looks fairly neat.
-Daniel
> 
> BTW: TTM isn't mapping anything in that case, we just fill in the arrays
> from the SGT.
> 
> Christian.
> 
> > -Daniel
> > 
> > >   int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page 
> > > **pages,
> > > -  dma_addr_t *addrs, int max_pages)
> > > +  dma_addr_t *addrs, int max_entries)
> > >   {
> > >   unsigned count;
> > >   struct scatterlist *sg;
> > >   struct page *page;
> > > - u32 len;
> > > - int pg_index;
> > > + u32 len, index;
> > >   dma_addr_t addr;
> > > - pg_index = 0;
> > > + index = 0;
> > >   for_each_sg(sgt->sgl, sg, sgt->nents, count) {
> > >   len = sg->length;
> > >   page = sg_page(sg);
> > >   addr = sg_dma_address(sg);
> > >   while (len > 0) {
> > > - if (WARN_ON(pg_index >= max_pages))
> > > + if (WARN_ON(index >= max_entries))
> > >   return -1;
> > > - pages[pg_index] = page;
> > > + if (pages)
> > > + pages[index] = page;
> > >   if (addrs)
> > > - addrs[pg_index] = addr;
> > > + addrs[index] = addr;
> > >   page++;
> > >   addr += PAGE_SIZE;
> > >   len -= PAGE_SIZE;
> > > - pg_index++;
> > > + index++;
> > >   }
> > >   }
> > >   return 0;
> > > -- 
> > > 2.14.1
> > > 
> > > ___
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> 

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Re: [PATCH 1/5] drm/prime: fix potential race in drm_gem_map_detach

[Christian König]

Am 06.03.2018 um 10:15 schrieb Daniel Vetter:

On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:

Am 28.02.2018 um 10:48 schrieb Lucas Stach:

Hi Christian,

Am Dienstag, den 27.02.2018, 12:49 +0100 schrieb Christian König:

Unpin the GEM object only after freeing the sg table.

What is the race that is being fixed here? The SG table is private to
the importer and the importer should hopefully only call map_detach if
it is done with all operations using the SG table. Thus it shouldn't
matter that the SG table might point to moved pages during execution of
this function.

Exactly, it shouldn't matter. This is just a precaution.

When the device driver is buggy I want proper error messages from IOMMU and
not accessing pages which might already be reused for something else.

Please add this to the commit message, rather crucial to understand the
motivation. With that fixed you can have my

Reviewed-by: Daniel Vetter 

And pls push to drm-misc.


Can I use standard git for that now? I really don't want to mess with 
dim in my environment.


Christian.
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Re: [PATCH 2/5] drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays

[Christian König]

Am 06.03.2018 um 10:21 schrieb Daniel Vetter:

On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:

Most of the time we only need the dma addresses.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/drm_prime.c | 20 ++--
  1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index c38dacda6119..7856a9b3f8a8 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -922,40 +922,40 @@ EXPORT_SYMBOL(drm_prime_pages_to_sg);
  /**
   * drm_prime_sg_to_page_addr_arrays - convert an sg table into a page array
   * @sgt: scatter-gather table to convert
- * @pages: array of page pointers to store the page array in
+ * @pages: optional array of page pointers to store the page array in
   * @addrs: optional array to store the dma bus address of each page
- * @max_pages: size of both the passed-in arrays
+ * @max_entries: size of both the passed-in arrays
   *
   * Exports an sg table into an array of pages and addresses. This is currently
   * required by the TTM driver in order to do correct fault handling.
   */

Can't we just teach ttm to use sgts wherever needed, and deprecate
exporting dma-bufs to page arrays (which really breaks the abstraction
entirely and was just a quick hack to get things going that stuck around
for years). Last time I looked into ttm the only thing it did is convert
it back to sgts again (after calling dma_map once more, which the exporter
should have done already for you).


Thought about that as well, but the problem here isn't TTM.

We need to be able to access the SGT by an index in amdgpu to be able to 
build up the VM page tables and that is not possible because the SGT is 
potentially chained.


We could add a new sg_table access helper function to work around that 
thought.


BTW: TTM isn't mapping anything in that case, we just fill in the arrays 
from the SGT.


Christian.


-Daniel


  int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page 
**pages,
-dma_addr_t *addrs, int max_pages)
+dma_addr_t *addrs, int max_entries)
  {
unsigned count;
struct scatterlist *sg;
struct page *page;
-   u32 len;
-   int pg_index;
+   u32 len, index;
dma_addr_t addr;
  
-	pg_index = 0;

+   index = 0;
for_each_sg(sgt->sgl, sg, sgt->nents, count) {
len = sg->length;
page = sg_page(sg);
addr = sg_dma_address(sg);
  
  		while (len > 0) {

-   if (WARN_ON(pg_index >= max_pages))
+   if (WARN_ON(index >= max_entries))
return -1;
-   pages[pg_index] = page;
+   if (pages)
+   pages[index] = page;
if (addrs)
-   addrs[pg_index] = addr;
+   addrs[index] = addr;
  
  			page++;

addr += PAGE_SIZE;
len -= PAGE_SIZE;
-   pg_index++;
+   index++;
}
}
return 0;
--
2.14.1

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Re: [PATCH 2/5] drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays

[Daniel Vetter]

On Tue, Feb 27, 2018 at 12:49:57PM +0100, Christian König wrote:
> Most of the time we only need the dma addresses.
> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/drm_prime.c | 20 ++--
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> index c38dacda6119..7856a9b3f8a8 100644
> --- a/drivers/gpu/drm/drm_prime.c
> +++ b/drivers/gpu/drm/drm_prime.c
> @@ -922,40 +922,40 @@ EXPORT_SYMBOL(drm_prime_pages_to_sg);
>  /**
>   * drm_prime_sg_to_page_addr_arrays - convert an sg table into a page array
>   * @sgt: scatter-gather table to convert
> - * @pages: array of page pointers to store the page array in
> + * @pages: optional array of page pointers to store the page array in
>   * @addrs: optional array to store the dma bus address of each page
> - * @max_pages: size of both the passed-in arrays
> + * @max_entries: size of both the passed-in arrays
>   *
>   * Exports an sg table into an array of pages and addresses. This is 
> currently
>   * required by the TTM driver in order to do correct fault handling.
>   */

Can't we just teach ttm to use sgts wherever needed, and deprecate
exporting dma-bufs to page arrays (which really breaks the abstraction
entirely and was just a quick hack to get things going that stuck around
for years). Last time I looked into ttm the only thing it did is convert
it back to sgts again (after calling dma_map once more, which the exporter
should have done already for you).
-Daniel

>  int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page 
> **pages,
> -  dma_addr_t *addrs, int max_pages)
> +  dma_addr_t *addrs, int max_entries)
>  {
>   unsigned count;
>   struct scatterlist *sg;
>   struct page *page;
> - u32 len;
> - int pg_index;
> + u32 len, index;
>   dma_addr_t addr;
>  
> - pg_index = 0;
> + index = 0;
>   for_each_sg(sgt->sgl, sg, sgt->nents, count) {
>   len = sg->length;
>   page = sg_page(sg);
>   addr = sg_dma_address(sg);
>  
>   while (len > 0) {
> - if (WARN_ON(pg_index >= max_pages))
> + if (WARN_ON(index >= max_entries))
>   return -1;
> - pages[pg_index] = page;
> + if (pages)
> + pages[index] = page;
>   if (addrs)
> - addrs[pg_index] = addr;
> + addrs[index] = addr;
>  
>   page++;
>   addr += PAGE_SIZE;
>   len -= PAGE_SIZE;
> - pg_index++;
> + index++;
>   }
>   }
>   return 0;
> -- 
> 2.14.1
> 
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Re: [Nouveau] [PATCH 4/5] drm/ttm: add ttm_sg_tt_init

[Daniel Vetter]

On Tue, Feb 27, 2018 at 01:07:06PM +0100, Christian König wrote:
> Hi guys,
> 
> at least on amdgpu and radeon the page array allocated by ttm_dma_tt_init is
> completely unused in the case of DMA-buf sharing. So I'm trying to get rid
> of that by only allocating the DMA address array.
> 
> Now the only other user of DMA-buf together with ttm_dma_tt_init is Nouveau.
> So my question is are you guys using the page array anywhere in your kernel
> driver in case of a DMA-buf sharing?
> 
> If no then I could just make this the default behavior for all drivers and
> save quite a bit of memory for everybody.

+1 on teaching ttm to no longer look at the struct page * in the dma-buf
sgt, but only the dma_buf address.

If there's still some need for in-kernel cpu or userspace mmap access then
imo ttm needs to be fixed to delegate all that to the right dma-buf
interfaces. The ttm abstraction is already there, it's just not passed
through.

I don't pretend to now enough of the details to review this stuff :-)
-Daniel

> 
> Thanks,
> Christian.
> 
> Am 27.02.2018 um 12:49 schrieb Christian König:
> > This allows drivers to only allocate dma addresses, but not a page
> > array.
> > 
> > Signed-off-by: Christian König 
> > ---
> >   drivers/gpu/drm/ttm/ttm_tt.c | 54 
> > 
> >   include/drm/ttm/ttm_tt.h |  2 ++
> >   2 files changed, 47 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> > index 8e0b525cda00..971133106ec2 100644
> > --- a/drivers/gpu/drm/ttm/ttm_tt.c
> > +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> > @@ -108,6 +108,16 @@ static int ttm_dma_tt_alloc_page_directory(struct 
> > ttm_dma_tt *ttm)
> > return 0;
> >   }
> > +static int ttm_sg_tt_alloc_page_directory(struct ttm_dma_tt *ttm)
> > +{
> > +   ttm->dma_address = kvmalloc_array(ttm->ttm.num_pages,
> > + sizeof(*ttm->dma_address),
> > + GFP_KERNEL | __GFP_ZERO);
> > +   if (!ttm->dma_address)
> > +   return -ENOMEM;
> > +   return 0;
> > +}
> > +
> >   #ifdef CONFIG_X86
> >   static inline int ttm_tt_set_page_caching(struct page *p,
> >   enum ttm_caching_state c_old,
> > @@ -227,8 +237,8 @@ void ttm_tt_destroy(struct ttm_tt *ttm)
> > ttm->func->destroy(ttm);
> >   }
> > -int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
> > -   unsigned long size, uint32_t page_flags)
> > +void ttm_tt_init_fields(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
> > +   unsigned long size, uint32_t page_flags)
> >   {
> > ttm->bdev = bdev;
> > ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
> > @@ -236,6 +246,12 @@ int ttm_tt_init(struct ttm_tt *ttm, struct 
> > ttm_bo_device *bdev,
> > ttm->page_flags = page_flags;
> > ttm->state = tt_unpopulated;
> > ttm->swap_storage = NULL;
> > +}
> > +
> > +int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
> > +   unsigned long size, uint32_t page_flags)
> > +{
> > +   ttm_tt_init_fields(ttm, bdev, size, page_flags);
> > if (ttm_tt_alloc_page_directory(ttm)) {
> > ttm_tt_destroy(ttm);
> > @@ -258,12 +274,7 @@ int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct 
> > ttm_bo_device *bdev,
> >   {
> > struct ttm_tt *ttm = _dma->ttm;
> > -   ttm->bdev = bdev;
> > -   ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
> > -   ttm->caching_state = tt_cached;
> > -   ttm->page_flags = page_flags;
> > -   ttm->state = tt_unpopulated;
> > -   ttm->swap_storage = NULL;
> > +   ttm_tt_init_fields(ttm, bdev, size, page_flags);
> > INIT_LIST_HEAD(_dma->pages_list);
> > if (ttm_dma_tt_alloc_page_directory(ttm_dma)) {
> > @@ -275,11 +286,36 @@ int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, 
> > struct ttm_bo_device *bdev,
> >   }
> >   EXPORT_SYMBOL(ttm_dma_tt_init);
> > +int ttm_sg_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev,
> > +  unsigned long size, uint32_t page_flags)
> > +{
> > +   struct ttm_tt *ttm = _dma->ttm;
> > +   int ret;
> > +
> > +   ttm_tt_init_fields(ttm, bdev, size, page_flags);
> > +
> > +   INIT_LIST_HEAD(_dma->pages_list);
> > +   if (page_flags & TTM_PAGE_FLAG_SG)
> > +   ret = ttm_sg_tt_alloc_page_directory(ttm_dma);
> > +   else
> > +   ret = ttm_dma_tt_alloc_page_directory(ttm_dma);
> > +   if (ret) {
> > +   ttm_tt_destroy(ttm);
> > +   pr_err("Failed allocating page table\n");
> > +   return -ENOMEM;
> > +   }
> > +   return 0;
> > +}
> > +EXPORT_SYMBOL(ttm_sg_tt_init);
> > +
> >   void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma)
> >   {
> > struct ttm_tt *ttm = _dma->ttm;
> > -   kvfree(ttm->pages);
> > +   if (ttm->pages)
> > +   kvfree(ttm->pages);
> > +   else
> > +   kvfree(ttm_dma->dma_address);
> > ttm->pages = NULL;
> > ttm_dma->dma_address = 

[PATCH] drm/amdgpu: Clean sdma wptr register when only enable wptr polling

[Emily Deng]

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

Signed-off-by: Emily Deng 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..2a27928 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device 
*adev)
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
   upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + 
sdma_offsets[i]);
-   if (ring->use_pollmem)
+   if (ring->use_pollmem) {
+   WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 1);
-   else
+   } else
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
   
SDMA0_GFX_RB_WPTR_POLL_CNTL,
   ENABLE, 0);
-- 
2.7.4

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Re: [PATCH 1/5] drm/prime: fix potential race in drm_gem_map_detach

[Daniel Vetter]

On Wed, Feb 28, 2018 at 11:25:59AM +0100, Christian König wrote:
> Am 28.02.2018 um 10:48 schrieb Lucas Stach:
> > Hi Christian,
> > 
> > Am Dienstag, den 27.02.2018, 12:49 +0100 schrieb Christian König:
> > > Unpin the GEM object only after freeing the sg table.
> > What is the race that is being fixed here? The SG table is private to
> > the importer and the importer should hopefully only call map_detach if
> > it is done with all operations using the SG table. Thus it shouldn't
> > matter that the SG table might point to moved pages during execution of
> > this function.
> 
> Exactly, it shouldn't matter. This is just a precaution.
> 
> When the device driver is buggy I want proper error messages from IOMMU and
> not accessing pages which might already be reused for something else.

Please add this to the commit message, rather crucial to understand the
motivation. With that fixed you can have my

Reviewed-by: Daniel Vetter 

And pls push to drm-misc.
-Daniel

> 
> Regards,
> Christian.
> 
> > 
> > Regards,
> > Lucas
> > 
> > > Signed-off-by: Christian König 
> > > ---
> > >   drivers/gpu/drm/drm_prime.c | 32 
> > >   1 file changed, 16 insertions(+), 16 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_prime.c
> > > b/drivers/gpu/drm/drm_prime.c
> > > index e82a976f0fba..c38dacda6119 100644
> > > --- a/drivers/gpu/drm/drm_prime.c
> > > +++ b/drivers/gpu/drm/drm_prime.c
> > > @@ -230,26 +230,26 @@ void drm_gem_map_detach(struct dma_buf
> > > *dma_buf,
> > >   struct drm_prime_attachment *prime_attach = attach->priv;
> > >   struct drm_gem_object *obj = dma_buf->priv;
> > >   struct drm_device *dev = obj->dev;
> > > - struct sg_table *sgt;
> > > - if (dev->driver->gem_prime_unpin)
> > > - dev->driver->gem_prime_unpin(obj);
> > > + if (prime_attach) {
> > > + struct sg_table *sgt = prime_attach->sgt;
> > > - if (!prime_attach)
> > > - return;
> > > -
> > > - sgt = prime_attach->sgt;
> > > - if (sgt) {
> > > - if (prime_attach->dir != DMA_NONE)
> > > - dma_unmap_sg_attrs(attach->dev, sgt->sgl,
> > > sgt->nents,
> > > -prime_attach->dir,
> > > -DMA_ATTR_SKIP_CPU_SYNC);
> > > - sg_free_table(sgt);
> > > + if (sgt) {
> > > + if (prime_attach->dir != DMA_NONE)
> > > + dma_unmap_sg_attrs(attach->dev, sgt-
> > > > sgl,
> > > +sgt->nents,
> > > +prime_attach-
> > > > dir,
> > > +DMA_ATTR_SKIP_CPU
> > > _SYNC);
> > > + sg_free_table(sgt);
> > > + }
> > > +
> > > + kfree(sgt);
> > > + kfree(prime_attach);
> > > + attach->priv = NULL;
> > >   }
> > > - kfree(sgt);
> > > - kfree(prime_attach);
> > > - attach->priv = NULL;
> > > + if (dev->driver->gem_prime_unpin)
> > > + dev->driver->gem_prime_unpin(obj);
> > >   }
> > >   EXPORT_SYMBOL(drm_gem_map_detach);
> 
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 3/5] drm/ttm: move ttm_tt defines into ttm_tt.h

[Christian König]

Hi Michel & Thomas,

any more comments on this? Or can I commit it?

Thanks,
Christian.

Am 27.02.2018 um 12:49 schrieb Christian König:

Let's stop mangling everything in a single header and create one header
per object instead.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/ttm/ttm_tt.c|   6 -
  include/drm/ttm/ttm_bo_driver.h | 237 +-
  include/drm/ttm/ttm_tt.h| 272 
  3 files changed, 273 insertions(+), 242 deletions(-)
  create mode 100644 include/drm/ttm/ttm_tt.h

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 0ee3b8f11605..8e0b525cda00 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -31,17 +31,11 @@
  #define pr_fmt(fmt) "[TTM] " fmt
  
  #include 

-#include 
  #include 
  #include 
  #include 
-#include 
-#include 
-#include 
  #include 
-#include 
  #include 
-#include 
  #include 
  #ifdef CONFIG_X86
  #include 
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 4312b5326f0b..f8e2515b401f 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -42,111 +42,10 @@
  #include "ttm_memory.h"
  #include "ttm_module.h"
  #include "ttm_placement.h"
+#include "ttm_tt.h"
  
  #define TTM_MAX_BO_PRIORITY	4U
  
-struct ttm_backend_func {

-   /**
-* struct ttm_backend_func member bind
-*
-* @ttm: Pointer to a struct ttm_tt.
-* @bo_mem: Pointer to a struct ttm_mem_reg describing the
-* memory type and location for binding.
-*
-* Bind the backend pages into the aperture in the location
-* indicated by @bo_mem. This function should be able to handle
-* differences between aperture and system page sizes.
-*/
-   int (*bind) (struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
-
-   /**
-* struct ttm_backend_func member unbind
-*
-* @ttm: Pointer to a struct ttm_tt.
-*
-* Unbind previously bound backend pages. This function should be
-* able to handle differences between aperture and system page sizes.
-*/
-   int (*unbind) (struct ttm_tt *ttm);
-
-   /**
-* struct ttm_backend_func member destroy
-*
-* @ttm: Pointer to a struct ttm_tt.
-*
-* Destroy the backend. This will be call back from ttm_tt_destroy so
-* don't call ttm_tt_destroy from the callback or infinite loop.
-*/
-   void (*destroy) (struct ttm_tt *ttm);
-};
-
-#define TTM_PAGE_FLAG_WRITE   (1 << 3)
-#define TTM_PAGE_FLAG_SWAPPED (1 << 4)
-#define TTM_PAGE_FLAG_PERSISTENT_SWAP (1 << 5)
-#define TTM_PAGE_FLAG_ZERO_ALLOC  (1 << 6)
-#define TTM_PAGE_FLAG_DMA32   (1 << 7)
-#define TTM_PAGE_FLAG_SG  (1 << 8)
-#define TTM_PAGE_FLAG_NO_RETRY   (1 << 9)
-
-enum ttm_caching_state {
-   tt_uncached,
-   tt_wc,
-   tt_cached
-};
-
-/**
- * struct ttm_tt
- *
- * @bdev: Pointer to a struct ttm_bo_device.
- * @func: Pointer to a struct ttm_backend_func that describes
- * the backend methods.
- * pointer.
- * @pages: Array of pages backing the data.
- * @num_pages: Number of pages in the page array.
- * @bdev: Pointer to the current struct ttm_bo_device.
- * @be: Pointer to the ttm backend.
- * @swap_storage: Pointer to shmem struct file for swap storage.
- * @caching_state: The current caching state of the pages.
- * @state: The current binding state of the pages.
- *
- * This is a structure holding the pages, caching- and aperture binding
- * status for a buffer object that isn't backed by fixed (VRAM / AGP)
- * memory.
- */
-
-struct ttm_tt {
-   struct ttm_bo_device *bdev;
-   struct ttm_backend_func *func;
-   struct page **pages;
-   uint32_t page_flags;
-   unsigned long num_pages;
-   struct sg_table *sg; /* for SG objects via dma-buf */
-   struct file *swap_storage;
-   enum ttm_caching_state caching_state;
-   enum {
-   tt_bound,
-   tt_unbound,
-   tt_unpopulated,
-   } state;
-};
-
-/**
- * struct ttm_dma_tt
- *
- * @ttm: Base ttm_tt struct.
- * @dma_address: The DMA (bus) addresses of the pages
- * @pages_list: used by some page allocation backend
- *
- * This is a structure holding the pages, caching- and aperture binding
- * status for a buffer object that isn't backed by fixed (VRAM / AGP)
- * memory.
- */
-struct ttm_dma_tt {
-   struct ttm_tt ttm;
-   dma_addr_t *dma_address;
-   struct list_head pages_list;
-};
-
  #define TTM_MEMTYPE_FLAG_FIXED (1 << 0) /* Fixed (on-card) PCI memory 
*/
  #define TTM_MEMTYPE_FLAG_MAPPABLE  (1 << 1) /* Memory mappable */
  #define TTM_MEMTYPE_FLAG_CMA   (1 << 3) /* Can't map aperture */
@@ -610,117 +509,6 @@ ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t 
mask)
return *old;
  }
  

RE: [PATCH] drm/amdgpu: Disable sdma wptr polling memory for sriov

[Deng, Emily]

Hi all,
 Please ignore this patch, the root cause about the sdma hang introduced by 
sdma wptr polling
has been found, will submit another patch.

Best Wishes,
Emily Deng

> -Original Message-
> From: Emily Deng [mailto:emily.d...@amd.com]
> Sent: Tuesday, March 06, 2018 10:15 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily 
> Subject: [PATCH] drm/amdgpu: Disable sdma wptr polling memory for sriov
> 
> The sdma wptr polling memory will introduce serious issue sdma hang for
> sriov environment on sdma v3.
> And the sdma wptr polling memory is only to fix the FLR cornner case, the
> issue's probabity is very low.
> 
> Change-Id: I2c447533aac6b16d541f58644d141228dd75dfb3
> Signed-off-by: Emily Deng 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index ec885ff..44d7d08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -716,10 +716,7 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
>   WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
>  upper_32_bits(wptr_gpu_addr));
>   wptr_poll_cntl =
> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> - if (amdgpu_sriov_vf(adev))
> - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
> - else
> - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
> + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> +SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
>   WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL +
> sdma_offsets[i], wptr_poll_cntl);
> 
>   /* enable DMA RB */
> --
> 2.7.4

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RE: [PATCH] Revert "drm/amdgpu: use polling mem to set SDMA3 wptr for VF"

[Deng, Emily]

Hi all,
 Please ignore this patch, the root cause about the sdma hang introduced by 
sdma wptr polling
has been found, will submit another patch.

Best Wishes,
Emily Deng

> -Original Message-
> From: Deng, Emily
> Sent: Tuesday, March 06, 2018 9:50 AM
> To: Deng, Emily ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] Revert "drm/amdgpu: use polling mem to set SDMA3
> wptr for VF"
> 
> Ping
> Hi all,
> Please help review this, the regression introduced by the commit
> 2ffe31deb27579e2f2c9444e01f4d8abf385d145 is gating the sriov sanity test.
> 
> Best Wishes,
> Emily Deng
> 
> 
> > -Original Message-
> > From: Emily Deng [mailto:emily.d...@amd.com]
> > Sent: Friday, March 02, 2018 11:32 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deng, Emily 
> > Subject: [PATCH] Revert "drm/amdgpu: use polling mem to set SDMA3 wptr
> > for VF"
> >
> > This reverts commit 2ffe31deb27579e2f2c9444e01f4d8abf385d145.
> > The sdma wptr poll memomy doesn't have the same efficiency as
> > doorbell, and it will make sdma hang when running tests.
> >
> > Change-Id: I6e334430b309b0c21aa18a08764320c7ff51e353
> > Signed-off-by: Emily Deng 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 -
> >  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 27 
> ---
> >  2 files changed, 8 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index 102dad3..5dcf98b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -186,7 +186,6 @@ struct amdgpu_ring {
> > uint64_teop_gpu_addr;
> > u32 doorbell_index;
> > booluse_doorbell;
> > -   booluse_pollmem;
> > unsignedwptr_offs;
> > unsignedfence_offs;
> > uint64_tcurrent_ctx;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > index 521978c..d3fb3ca 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> > @@ -355,7 +355,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct
> > amdgpu_ring *ring)
> > struct amdgpu_device *adev = ring->adev;
> > u32 wptr;
> >
> > -   if (ring->use_doorbell || ring->use_pollmem) {
> > +   if (ring->use_doorbell) {
> > /* XXX check if swapping is necessary on BE */
> > wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
> > } else {
> > @@ -380,13 +380,10 @@ static void sdma_v3_0_ring_set_wptr(struct
> > amdgpu_ring *ring)
> >
> > if (ring->use_doorbell) {
> > u32 *wb = (u32 *)>wb.wb[ring->wptr_offs];
> > +
> > /* XXX check if swapping is necessary on BE */
> > WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
> > WDOORBELL32(ring->doorbell_index, lower_32_bits(ring-
> > >wptr) << 2);
> > -   } else if (ring->use_pollmem) {
> > -   u32 *wb = (u32 *)>wb.wb[ring->wptr_offs];
> > -
> > -   WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
> > } else {
> > int me = (ring == >adev->sdma.instance[0].ring) ? 0 : 1;
> >
> > @@ -719,14 +716,10 @@ static int sdma_v3_0_gfx_resume(struct
> > amdgpu_device *adev)
> > WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
> >upper_32_bits(wptr_gpu_addr));
> > wptr_poll_cntl =
> > RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> > -   if (ring->use_pollmem)
> > -   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> > -
> > SDMA0_GFX_RB_WPTR_POLL_CNTL,
> > -  ENABLE, 1);
> > +   if (amdgpu_sriov_vf(adev))
> > +   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> > +SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
> > else
> > -   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> > -
> > SDMA0_GFX_RB_WPTR_POLL_CNTL,
> > -  ENABLE, 0);
> > +   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> > +SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
> > WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL +
> sdma_offsets[i],
> > wptr_poll_cntl);
> >
> > /* enable DMA RB */
> > @@ -1208,13 +1201,9 @@ static int sdma_v3_0_sw_init(void *handle)
> > for (i = 0; i < adev->sdma.num_instances; i++) {
> > ring = >sdma.instance[i].ring;
> > ring->ring_obj = NULL;
> > -   if (!amdgpu_sriov_vf(adev)) {
> > -   ring->use_doorbell = true;
> > -   ring->doorbell_index = (i == 0) ?
> > -   AMDGPU_DOORBELL_sDMA_ENGINE0 :
> > AMDGPU_DOORBELL_sDMA_ENGINE1;
> > -   } else {
> > - 

Re: [PATCH] drm/atomic: Add new reverse iterator over all plane state (V2)

[Jani Nikula]

On Mon, 05 Mar 2018, Harry Wentland  wrote:
>   make DOCBOOKS="" htmldocs

DOCBOOKS is no more. Simply 'make htmldocs' will do the same.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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