Re: [ARTIQ] FW: initial specification of the project

Hi all I like that idea - in this way we can do it really affordable with lower end FPGAs and still compatible with MTCA. If we place all RF stuff on the modules, with RF connectors mounted directly on the front panel, this could work. How we would deliver the clocks? Using external SMA

Re: [ARTIQ] FW: initial specification of the project

Such assembly technique is called: castellated PCB module https://www.google.pl/search?q=castellated+RF+modules=1920=917=lnms=isch=X=0ahUKEwjRvuqko-nLAhWnnXIKHe_IARsQ_AUIBygB

Re: [ARTIQ] FW: initial specification of the project

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration So you have 34 LVDS pairs and 8 GTP links. On 30 March 2016 at 23:00, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > > On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) > >

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and > GBE MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific

Re: [ARTIQ] FW: initial specification of the project

Maybe we should come back to the roots:) What if we use standard FMCs (LPC) with DAC/ADC channels and RF stuff _on_ them. JESD204B and some pins would go to the FPGA while DAC and RF clock would be fed externally. In this way we leave general purpose AMC board and define its functionality by FMC

Re: [ARTIQ] FW: initial specification of the project

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration So you have 34 LVDS pairs and 8 GTP links. If this works for you then I don’t have major objections. The other issue to consider is power rails, since for the analog circuitry we will probably want +/- 5V, +/- 15V

Re: [ARTIQ] FW: initial specification of the project

Well, it depends on trace width matching. We can simulate and characterize it even at much higher frequencies. If we place them really close to the DAC and match widths, remove grounds under pads, we can match it not worse than SMA connectors. We can even do even more crazy thing - try to make

Re: [ARTIQ] FW: initial specification of the project

So now we are moving towards complying with the AMC FMC physical standard. Is this something we want to do? There are pluses (able to use existing AMC FMC cards) and minuses (squeezing things in more tightly than we otherwise might have to). From: Grzegorz Kasprowicz

Re: [ARTIQ] FW: initial specification of the project

Are we talking about double width AMCs? Two DAC channels and 2 RF modules should fit. Greg -Original Message- From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] Sent: Wednesday, March 30, 2016 5:46 PM To: Leibrandt, David R. (Fed) Cc: Grzegorz Kasprowicz

Re: [ARTIQ] FW: initial specification of the project

OK, I see your point On 30 March 2016 at 23:17, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > We definitely need +/- 15V for the low frequency (e.g. trap electrode) > amplifiers. Many low noise amplifiers and RF components run off +5V or +/- > 5V and have substantial current

Re: [ARTIQ] FW: initial specification of the project

> Maybe we should come back to the roots:) What if we use standard FMCs > (LPC) with DAC/ADC channels and RF stuff _on_ them. > JESD204B and some pins would go to the FPGA while DAC and RF clock would > be fed externally. > In this way we leave general purpose AMC board and define its

Re: [ARTIQ] FW: initial specification of the project

Well, we can do another crazy thing - solder small module with RF stuff on the FMC board, under same shield. In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the functionality by soldering (automatic or manual) of just RF modules. WE can even design such modules to hold the

Re: [ARTIQ] FW: initial specification of the project

> On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) > wrote: > > Now, as you suggest we could just change the level at which we make this > break from the AMC card, shift the DACs and ADCs onto the daughter card as > well, and use FMC to communicate with the

Re: [ARTIQ] Fwd: FW: initial specification of the project

Actually, we can fit a lot to single FMC Look here: https://scontent-waw1-1.xx.fbcdn.net/hphotos-xpa1/v/t1.0-9/66620_1649317561668_2595483_n.jpg?oh=982ee50c1a1d8ecc444346c9eae1fe1c=578FA78C I managed to place there 16 AFEs, 16x130MHz ADCs, 16 buffers, FPGA, SDRAM, quad DAC with amplifier, SMPS

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) wrote: > Now, as you suggest we could just change the level at which we make this > break from the AMC card, shift the DACs and ADCs onto the daughter card as > well, and use FMC to communicate with the whole

Re: [ARTIQ] Fwd: FW: initial specification of the project

On Wed, Mar 30, 2016 at 10:22 PM, Grzegorz Kasprowicz wrote: > Actually, we can fit a lot to single FMC > Look here: > https://scontent-waw1-1.xx.fbcdn.net/hphotos-xpa1/v/t1.0-9/66620_1649317561668_2595483_n.jpg?oh=982ee50c1a1d8ecc444346c9eae1fe1c=578FA78C > I managed to place

Re: [ARTIQ] FW: initial specification of the project

We could also use a fuzz button interposer, which would do the same kind of task (low stacking height connection w/ high frequency compatibility), but I think once we start heading too far down this road the cost and complexity of making a robust solution starts to outweigh the cost of just

Re: [ARTIQ] FW: initial specification of the project

On Wed, Mar 30, 2016 at 5:57 PM, Slichter, Daniel H. (Fed) wrote: >> > What are you thinking for number of daughter cards? I suppose that >> > more would give us more flexibility, but less would be more economical >> > in terms of cost and layout area. Perhaps two

Re: [ARTIQ] Fwd: FW: initial specification of the project

> Impressive. Yep. Looks doable then. For us it would probably be either just > filtering and amplification on four channels, or upconversion (on two iq > channels then i would think). Agreed, seems doable. Filtering plus amplification should fit in a suitable footprint pretty easily. Two

Re: [ARTIQ] FW: initial specification of the project

On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > Well, you don't have to write it. > It is already available for RTOS and linux. We are not using RTOS or Linux. > But it's true - it occupies MIO bank and dedicated DDR port. But this is axi > and can be easily accessible

Re: [ARTIQ] FW: initial specification of the project

One further question: is there a plan to make a “TTL” card or a multichannel “slow” DAC card (e.g. for trap voltages), using a Centronics or d-sub type connector? These could both be more readily accomplished with their own FMC modules if we go with this architecture. From: Grzegorz

Re: [ARTIQ] FW: initial specification of the project

Looks like one could get a pretty good start on things by just copying the designs used by marki microwave: http://www.markimicrowave.com/assets/packages/CTG.pdf http://www.markimicrowave.com/assets/appnotes/an-ct-pcb.pdf On another note, I would recommend the MM1-0320HSM mixer as a good option

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and GBE > MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-specific features

Re: [ARTIQ] FW: initial specification of the project

I like this plan. I think 4 + 4 channels will also make the front panel connector density more reasonable. What are you thinking for number of daughter cards? I suppose that more would give us more flexibility, but less would be more economical in terms of cost and layout area. Perhaps two

Re: [ARTIQ] FW: initial specification of the project

> I like this plan. I think 4 + 4 channels will also make the front panel > connector > density more reasonable. What are you thinking for number of daughter > cards? I suppose that more would give us more flexibility, but less would be > more economical in terms of cost and layout area.

Re: [ARTIQ] FW: initial specification of the project

> > What are you thinking for number of daughter cards? I suppose that > > more would give us more flexibility, but less would be more economical > > in terms of cost and layout area. Perhaps two daughter cards would be > reasonable: > > one for all of the inputs and one for all of the outputs?