Re: [ARTIQ] 3.3 V I/O on kc705

[Sébastien Bourdeauducq]

Hi,

On Tuesday, September 20, 2016 09:35 AM, Jonathan Mizrahi wrote:

Thanks! I assume this is the part I need to buy?
http://www.ti.com/tool/usb-to-gpio


Yes.


The ARTIQ manual doesn't say anything about removing and replacing the
J65 jumper, which the kc705 manual talks about (p. 74). Is this unnecessary?


No. The technique described in the manual is for when the FPGA 
reprograms dynamically the power chip. Since we didn't want to bother 
with the details of programming proprietary TI power chips, we used a 
different technique that requires only existing software and hardware. 
The proposed technique will permanently program the TI chip to output 
3.3V, without FPGA intervention.



Also, are all of the I/O pins on the FMC connectors in HR banks (and
thus able to go to 3.3 V)?


IIRC yes, all HP banks go to on-board peripherals (mostly the SDRAM), 
and it would not be smart if reprogramming the FMC voltage only changed 
it for some of the pins. You can check using the schematics.


Sébastien
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Re: [ARTIQ] 3.3 V I/O on kc705

[Jonathan Mizrahi]

Thanks! I assume this is the part I need to buy?
http://www.ti.com/tool/usb-to-gpio

The ARTIQ manual doesn't say anything about removing and replacing the J65
jumper, which the kc705 manual talks about (p. 74). Is this unnecessary?

Also, are all of the I/O pins on the FMC connectors in HR banks (and thus
able to go to 3.3 V)? I could not find this clearly stated anywhere.

On Mon, Sep 19, 2016 at 7:08 PM, Slichter, Daniel H. (Fed) <
daniel.slich...@nist.gov> wrote:

> To expand, the VADJ rail supplies the output stages for the KC705 I/O
> banks connected to the FMC connectors, so if you want to drive things using
> LVCMOS or LVTTL 3.3V logic, you will have to program the VADJ rail to
> supply the necessary voltage.  It’s very straightforward; instructions are
> on the ARTIQ manual site below.
>
> > -Original Message-
> > From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Robert
> > Jördens
> > Sent: Monday, September 19, 2016 4:57 PM
> > To: Jonathan Mizrahi <jmizr...@umd.edu>
> > Cc: artiq@lists.m-labs.hk
> > Subject: Re: [ARTIQ] 3.3 V I/O on kc705
> >
> > On Mon, Sep 19, 2016 at 9:36 PM, Jonathan Mizrahi <jmizr...@umd.edu>
> > wrote:
> > > see LVTTL IOStandards, which means they're already operating at 3.3 V.
> > > This is why I'm confused about what I need to do to work at 3.3 V off
> > > the FMC connector.
> >
> > https://m-labs.hk/artiq/manual-release-2/core_device.html#vadj
> >
> > --
> > Robert Jördens.
> > ___
> > ARTIQ mailing list
> > https://ssl.serverraum.org/lists/listinfo/artiq
>
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Re: [ARTIQ] 3.3 V I/O on kc705

[Slichter, Daniel H. (Fed)]

To expand, the VADJ rail supplies the output stages for the KC705 I/O banks 
connected to the FMC connectors, so if you want to drive things using LVCMOS or 
LVTTL 3.3V logic, you will have to program the VADJ rail to supply the 
necessary voltage.  It’s very straightforward; instructions are on the ARTIQ 
manual site below.

> -Original Message-
> From: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Robert
> Jördens
> Sent: Monday, September 19, 2016 4:57 PM
> To: Jonathan Mizrahi <jmizr...@umd.edu>
> Cc: artiq@lists.m-labs.hk
> Subject: Re: [ARTIQ] 3.3 V I/O on kc705
> 
> On Mon, Sep 19, 2016 at 9:36 PM, Jonathan Mizrahi <jmizr...@umd.edu>
> wrote:
> > see LVTTL IOStandards, which means they're already operating at 3.3 V.
> > This is why I'm confused about what I need to do to work at 3.3 V off
> > the FMC connector.
> 
> https://m-labs.hk/artiq/manual-release-2/core_device.html#vadj
> 
> --
> Robert Jördens.
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> https://ssl.serverraum.org/lists/listinfo/artiq
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Re: [ARTIQ] 3.3 V I/O on kc705

[Robert Jördens]

On Mon, Sep 19, 2016 at 9:36 PM, Jonathan Mizrahi  wrote:
> see LVTTL IOStandards, which means they're already operating at 3.3 V. This
> is why I'm confused about what I need to do to work at 3.3 V off the FMC
> connector.

https://m-labs.hk/artiq/manual-release-2/core_device.html#vadj

-- 
Robert Jördens.
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